diff --git a/CMSIS/Core/Include/CMSIS_Include_core_cm_MIMX8MQ6.cmake b/CMSIS/Core/Include/CMSIS_Include_core_cm_MIMX8MQ6.cmake new file mode 100644 index 000000000..6e28ae838 --- /dev/null +++ b/CMSIS/Core/Include/CMSIS_Include_core_cm_MIMX8MQ6.cmake @@ -0,0 +1,8 @@ +include_guard(GLOBAL) +message("CMSIS_Include_core_cm component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + diff --git a/CMSIS/Core/Include/core_cm4.h b/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 000000000..12c023b80 --- /dev/null +++ b/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS/DSP/Lib/GCC/libarm_cortexM4lf_math.a b/CMSIS/DSP/Lib/GCC/libarm_cortexM4lf_math.a new file mode 100644 index 000000000..66efc87f6 Binary files /dev/null and b/CMSIS/DSP/Lib/GCC/libarm_cortexM4lf_math.a differ diff --git a/CMSIS/Driver/Include/CMSIS_Driver_Include_Common_MIMX8MQ6.cmake b/CMSIS/Driver/Include/CMSIS_Driver_Include_Common_MIMX8MQ6.cmake new file mode 100644 index 000000000..138148ead --- /dev/null +++ b/CMSIS/Driver/Include/CMSIS_Driver_Include_Common_MIMX8MQ6.cmake @@ -0,0 +1,8 @@ +include_guard(GLOBAL) +message("CMSIS_Driver_Include_Common component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + diff --git a/CMSIS/Driver/Include/CMSIS_Driver_Include_I2C_MIMX8MQ6.cmake b/CMSIS/Driver/Include/CMSIS_Driver_Include_I2C_MIMX8MQ6.cmake new file mode 100644 index 000000000..dda655cf6 --- /dev/null +++ b/CMSIS/Driver/Include/CMSIS_Driver_Include_I2C_MIMX8MQ6.cmake @@ -0,0 +1,10 @@ +include_guard(GLOBAL) +message("CMSIS_Driver_Include_I2C component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + +include(CMSIS_Driver_Include_Common_MIMX8MQ6) + diff --git a/CMSIS/Driver/Include/CMSIS_Driver_Include_SPI_MIMX8MQ6.cmake b/CMSIS/Driver/Include/CMSIS_Driver_Include_SPI_MIMX8MQ6.cmake new file mode 100644 index 000000000..e68d1534c --- /dev/null +++ b/CMSIS/Driver/Include/CMSIS_Driver_Include_SPI_MIMX8MQ6.cmake @@ -0,0 +1,10 @@ +include_guard(GLOBAL) +message("CMSIS_Driver_Include_SPI component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + +include(CMSIS_Driver_Include_Common_MIMX8MQ6) + diff --git a/CMSIS/Driver/Include/CMSIS_Driver_Include_USART_MIMX8MQ6.cmake b/CMSIS/Driver/Include/CMSIS_Driver_Include_USART_MIMX8MQ6.cmake new file mode 100644 index 000000000..68d0434b9 --- /dev/null +++ b/CMSIS/Driver/Include/CMSIS_Driver_Include_USART_MIMX8MQ6.cmake @@ -0,0 +1,10 @@ +include_guard(GLOBAL) +message("CMSIS_Driver_Include_USART component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + +include(CMSIS_Driver_Include_Common_MIMX8MQ6) + diff --git a/EVK-MIMX8MQ_manifest_v3_8.xml b/EVK-MIMX8MQ_manifest_v3_8.xml new file mode 100644 index 000000000..c1d7acf84 --- /dev/null +++ b/EVK-MIMX8MQ_manifest_v3_8.xml @@ -0,0 +1,3238 @@ + + + + + + + + + + + + + + + + + + + + + + + + Evaluation Kit for the i.MX 8M Applications Processor + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + i.MX 8M: Cortex-A53 up to 1.5GHz and Cortex-M4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SW-Content-Register.txt b/SW-Content-Register.txt index f48c720de..cb3b358b3 100644 --- a/SW-Content-Register.txt +++ b/SW-Content-Register.txt @@ -69,6 +69,17 @@ SDK_Components Name: SDK components and board peripheral drivers Location: components/ Origin: NXP (BSD-3-Clause) +usb Name: USB + Version: 2.8.0 + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code + Description: NXP USB stack. This is a version of + the USB stack that has been integrated with the + MCUXpresso SDK. + Location: middleware/usb + Origin: NXP (BSD-3-Clause) + freertos Name: FreeRTOS Version: 202012.00.0 Outgoing License: MIT diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/RTE_Device.h b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/RTE_Device.h new file mode 100644 index 000000000..9d680a304 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/RTE_Device.h @@ -0,0 +1,25 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _RTE_DEVICE_H +#define _RTE_DEVICE_H + +extern void ECSPI1_InitPins(); +extern void ECSPI1_DeinitPins(); + +/* Driver name mapping. */ +/* User needs to provide the implementation of ECSPIX_GetFreq/ECSPIX_InitPins/ECSPIX_DeinitPins for the enabled ECSPI + * instance. */ +#define RTE_SPI1 1 +#define RTE_SPI1_PIN_INIT ECSPI1_InitPins +#define RTE_SPI1_PIN_DEINIT ECSPI1_DeinitPins +#define RTE_SPI1_DMA_EN 0 + +/* ECSPI configuration. */ +#define RTE_SPI1_TRANSFER_CHANNEL kECSPI_Channel0 + +#endif /* _RTE_DEVICE_H */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/CMakeLists.txt b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..364549796 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,112 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(cmsis_ecspi_int_loopback_transfer) + +set(MCUX_SDK_PROJECT_NAME cmsis_ecspi_int_loopback_transfer.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../cmsis_ecspi_int_loopback_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../RTE_Device.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/cmsis_drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../CMSIS/Driver/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_cmsis_ecspi_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(driver_ecspi_MIMX8MQ6) + +include(CMSIS_Driver_Include_SPI_MIMX8MQ6) + +include(CMSIS_Driver_Include_Common_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/cmsis_ecspi_int_loopback_transfer.bin) + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_all.bat b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_all.sh b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_all.sh new file mode 100755 index 000000000..86624c4e1 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..373514ef3 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c16cafbd5 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_debug.bat b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_debug.sh b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_release.bat b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_release.sh b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/clean.bat b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/clean.sh b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/config.cmake b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/flags.cmake b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb 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-fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/board.c b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/board.h b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/clock_config.c b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/clock_config.h b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/cmsis_ecspi_int_loopback_transfer.c b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/cmsis_ecspi_int_loopback_transfer.c new file mode 100644 index 000000000..195411a29 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/cmsis_ecspi_int_loopback_transfer.c @@ -0,0 +1,127 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_ecspi_cmsis.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DRIVER_MASTER_SPI Driver_SPI1 +#define EXAMPLE_MASTER_SPI_BASE ECSPI1 +#define TRANSFER_SIZE 256U /*! Transfer dataSize */ +#define TRANSFER_BAUDRATE 500000U /*! Transfer baudrate - 500k */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +void ECSPI_EnableLoopBackTransfer(ECSPI_Type *base); +/* ECSPI user SignalEvent */ +void ECSPI_MasterSignalEvent_t(uint32_t event); +/******************************************************************************* + * Variables + ******************************************************************************/ +uint32_t masterRxData[TRANSFER_SIZE] = {0U}; +uint32_t masterTxData[TRANSFER_SIZE] = {0U}; + +volatile bool isTransferCompleted = false; +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t ECSPI1_GetFreq(void) +{ + return CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi1)) / + (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi1)); +} + +void ECSPI_EnableLoopBackTransfer(ECSPI_Type *base) +{ + base->TESTREG |= ECSPI_TESTREG_LBC(1); +} +void ECSPI_MasterSignalEvent_t(uint32_t event) +{ + /* user code */ + isTransferCompleted = true; + PRINTF("\r\n This is ECSPI_MasterSignalEvent_t.\r\n"); +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t errorCount; + uint32_t i; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + CLOCK_SetRootMux(kCLOCK_RootEcspi1, kCLOCK_EcspiRootmuxSysPll1); /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootEcspi1, 2U, 5U); /* Set root clock to 800MHZ / 10 = 80MHZ */ + + PRINTF("This is ECSPI CMSIS interrupt loopback transfer example.\r\n"); + PRINTF("The ECSPI will connect the transmitter and receiver sections internally.\r\n"); + + /*DSPI master init*/ + DRIVER_MASTER_SPI.Initialize(ECSPI_MasterSignalEvent_t); + DRIVER_MASTER_SPI.PowerControl(ARM_POWER_FULL); + DRIVER_MASTER_SPI.Control(ARM_SPI_MODE_MASTER, TRANSFER_BAUDRATE); + + /* Enable loopback transfer. */ + ECSPI_EnableLoopBackTransfer(EXAMPLE_MASTER_SPI_BASE); + /* Set up the transfer data */ + for (i = 0U; i < TRANSFER_SIZE; i++) + { + masterTxData[i] = i % 256U; + masterRxData[i] = 0U; + } + + isTransferCompleted = false; + PRINTF("Start transfer...\r\n"); + /* Start master transfer */ + DRIVER_MASTER_SPI.Transfer(masterTxData, masterRxData, TRANSFER_SIZE); + + /* Wait slave received all data. */ + while (!isTransferCompleted) + { + } + + PRINTF("\r\nTransfer completed!"); + errorCount = 0U; + for (i = 0U; i < TRANSFER_SIZE; i++) + { + if (masterTxData[i] != masterRxData[i]) + { + errorCount++; + } + } + if (errorCount == 0U) + { + PRINTF("\r\nECSPI transfer all data matched! \r\n"); + } + else + { + PRINTF(" \r\nError occurred in ECSPI loopback transfer ! \r\n"); + } + + DRIVER_MASTER_SPI.PowerControl(ARM_POWER_OFF); + DRIVER_MASTER_SPI.Uninitialize(); + + while (1) + { + } +} diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/cmsis_ecspi_int_loopback_transfer_v3_8.xml b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/cmsis_ecspi_int_loopback_transfer_v3_8.xml new file mode 100644 index 000000000..30c0b66bc --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/cmsis_ecspi_int_loopback_transfer_v3_8.xml @@ -0,0 +1,125 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/empty_rsc_table.c b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/fsl_iomuxc.h b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/pin_mux.c b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/pin_mux.c new file mode 100644 index 000000000..abb1aff0b --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/pin_mux.c @@ -0,0 +1,107 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +ECSPI1_InitPins: +- options: {coreID: m4} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : ECSPI1_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void ECSPI1_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +ECSPI1_DeinitPins: +- options: {coreID: m4} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : ECSPI1_DeinitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void ECSPI1_DeinitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/pin_mux.h b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/pin_mux.h new file mode 100644 index 000000000..a7ceaefca --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/pin_mux.h @@ -0,0 +1,67 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void ECSPI1_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void ECSPI1_DeinitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/readme.txt b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/readme.txt new file mode 100644 index 000000000..8f34a04c4 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/ecspi/int_loopback_transfer/readme.txt @@ -0,0 +1,66 @@ +Overview +======== +CMSIS-Driver defines generic peripheral driver interfaces for middleware making it reusable across a wide +range of supported microcontroller devices. The API connects microcontroller peripherals with middleware +that implements for example communication stacks, file systems, or graphic user interfaces. +More information and usage method please refer to http://www.keil.com/pack/doc/cmsis/Driver/html/index.html. + +The cmsis_ecspi_int_loopback_transfer example shows how to use CMSIS ECSPI driver in interrupt way: + +In this example , ECSPI will do a loopback transfer in interrupt way, so, there is no need to set up any pins. +And we should set the ECSPIx->TESTREG[LBC] bit, this bit is used in Master mode only. When this bit is set, +the ECSPI connects the transmitter and receiver sections internally, and the data shifted out from the +most-significant bit of the shift register is looped back into the least-significant bit of the Shift register. +In this way, a self-test of the complete transmit/receive path can be made. The output pins are not affected, +and the input pins are ignored. + + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo. + + +Running the demo +================ +When the demo runs successfully, the log would be seen on the debug terminal like: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +This is ECSPI CMSIS interrupt loopback transfer example. +The ECSPI will connect the transmitter and receiver sections internally. +Start transfer... + + This is ECSPI_MasterSignalEvent_t. + +Transfer completed! +ECSPI transfer all data matched! +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/RTE_Device.h b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/RTE_Device.h new file mode 100644 index 000000000..5c404111a --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/RTE_Device.h @@ -0,0 +1,22 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _RTE_DEVICE_H +#define _RTE_DEVICE_H + +extern void I2C2_InitPins(); +extern void I2C2_DeinitPins(); + +/*Driver name mapping*/ +/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. + */ +#define RTE_I2C2 1 +#define RTE_I2C2_PIN_INIT I2C2_InitPins +#define RTE_I2C2_PIN_DEINIT I2C2_DeinitPins + +/*I2C configuration*/ + +#endif /* _RTE_DEVICE_H */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/CMakeLists.txt b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/CMakeLists.txt new file mode 100644 index 000000000..803934269 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/CMakeLists.txt @@ -0,0 +1,112 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(cmsis_ii2c_int_b2b_transfer_master) + +set(MCUX_SDK_PROJECT_NAME cmsis_ii2c_int_b2b_transfer_master.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../cmsis_i2c_int_b2b_transfer_master.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../RTE_Device.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/cmsis_drivers + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../../components/uart + ${ProjDirPath}/../../../../../../../components/lists + ${ProjDirPath}/../../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../../CMSIS/Driver/Include + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_cmsis_ii2c_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(driver_ii2c_MIMX8MQ6) + +include(CMSIS_Driver_Include_I2C_MIMX8MQ6) + +include(CMSIS_Driver_Include_Common_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/cmsis_ii2c_int_b2b_transfer_master.bin) + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_all.bat b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_all.bat new file mode 100644 index 000000000..d5710260a --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_all.sh b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_all.sh new file mode 100755 index 000000000..2dd7d6219 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..8771607cb --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..1f660e5af --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..0dfc882b6 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..cbb10c43f --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_debug.bat b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_debug.bat new file mode 100644 index 000000000..0636e21b5 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_debug.sh b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_debug.sh new file mode 100755 index 000000000..30c0ab2d5 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_release.bat b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_release.bat new file mode 100644 index 000000000..a34003e0e --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_release.sh b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_release.sh new file mode 100755 index 000000000..012619cda --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/clean.bat b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/clean.sh b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/config.cmake b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/flags.cmake b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/board.c b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/board.h b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/clock_config.c b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/clock_config.h b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/cmsis_i2c_int_b2b_transfer_master.c b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/cmsis_i2c_int_b2b_transfer_master.c new file mode 100644 index 000000000..75b89b4b0 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/cmsis_i2c_int_b2b_transfer_master.c @@ -0,0 +1,147 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Standard C Included Files */ +#include +/* SDK Included Files */ +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_i2c.h" +#include "Driver_I2C.h" +#include "fsl_i2c_cmsis.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_I2C_MASTER Driver_I2C2 +#define I2C_MASTER_SLAVE_ADDR 0x7EU +#define I2C_DATA_LENGTH 32U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint8_t g_master_txBuff[I2C_DATA_LENGTH]; +uint8_t g_master_rxBuff[I2C_DATA_LENGTH]; +volatile bool g_MasterCompletionFlag = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t I2C2_GetFreq(void) +{ + return CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootI2c2)) / + (CLOCK_GetRootPostDivider(kCLOCK_RootI2c2)) / 5; /* SYSTEM PLL1 DIV5 */ +} + + +void I2C_MasterSignalEvent_t(uint32_t event) +{ + if (event == ARM_I2C_EVENT_TRANSFER_DONE) + { + g_MasterCompletionFlag = true; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + CLOCK_SetRootMux(kCLOCK_RootI2c2, kCLOCK_I2cRootmuxSysPll1Div5); /* Set I2C source to SysPLL1 Div5 160MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootI2c2, 1U, 4U); /* Set root clock to 160MHZ / 4 = 40MHZ */ + + /*Init I2C*/ + EXAMPLE_I2C_MASTER.Initialize(I2C_MasterSignalEvent_t); + + /* Enable i2c moduole and i2c clock */ + EXAMPLE_I2C_MASTER.PowerControl(ARM_POWER_FULL); + + /*config transmit speed*/ + EXAMPLE_I2C_MASTER.Control(ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_STANDARD); + + PRINTF("\r\nCMSIS I2C board2board interrupt example -- Master transfer.\r\n"); + + /*Set up i2c master to send data to master*/ + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + g_master_txBuff[i] = i; + } + PRINTF("Master will send data :"); + + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + if (i % 8 == 0) + { + PRINTF("\r\n"); + } + PRINTF("0x%2x ", g_master_txBuff[i]); + } + PRINTF("\r\n\r\n"); + + /*start transfer*/ + EXAMPLE_I2C_MASTER.MasterTransmit(I2C_MASTER_SLAVE_ADDR, g_master_txBuff, I2C_DATA_LENGTH, false); + + /*wait for master complete*/ + while (!g_MasterCompletionFlag) + { + } + + /* Reset master completion flag to false. */ + g_MasterCompletionFlag = false; + + PRINTF("Receive sent data from slave :"); + + EXAMPLE_I2C_MASTER.MasterReceive(I2C_MASTER_SLAVE_ADDR, g_master_rxBuff, I2C_DATA_LENGTH, false); + + /*wait for master complete*/ + while (!g_MasterCompletionFlag) + { + } + /* Reset master completion flag to false. */ + g_MasterCompletionFlag = false; + + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + if (i % 8 == 0) + { + PRINTF("\r\n"); + } + PRINTF("0x%2x ", g_master_rxBuff[i]); + } + PRINTF("\r\n\r\n"); + + /* Transfer completed. Check the data.*/ + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + if (g_master_rxBuff[i] != g_master_txBuff[i]) + { + PRINTF("\r\nError occurred in the transfer ! \r\n"); + break; + } + } + + PRINTF("\r\nEnd of I2C example .\r\n"); + while (1) + { + } +} diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/cmsis_ii2c_int_b2b_transfer_master_v3_8.xml b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/cmsis_ii2c_int_b2b_transfer_master_v3_8.xml new file mode 100644 index 000000000..6a653966d --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/cmsis_ii2c_int_b2b_transfer_master_v3_8.xml @@ -0,0 +1,125 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/empty_rsc_table.c b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/fsl_iomuxc.h b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/pin_mux.c b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/pin_mux.c new file mode 100644 index 000000000..190fd35ec --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/pin_mux.c @@ -0,0 +1,125 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +I2C2_InitPins: +- options: {coreID: m4} +- pin_list: + - {pin_num: G7, peripheral: I2C2, signal: i2c_scl, pin_signal: I2C2_SCL, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: F7, peripheral: I2C2, signal: i2c_sda, pin_signal: I2C2_SDA, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM, DSE: OHM_45} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : I2C2_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void I2C2_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_I2C2_SCL_I2C2_SCL, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SCL_I2C2_SCL, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_I2C2_SDA_I2C2_SDA, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SDA_I2C2_SDA, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +I2C2_DeinitPins: +- options: {coreID: m4} +- pin_list: + - {pin_num: G7, peripheral: I2C2, signal: i2c_scl, pin_signal: I2C2_SCL} + - {pin_num: F7, peripheral: I2C2, signal: i2c_sda, pin_signal: I2C2_SDA} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : I2C2_DeinitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void I2C2_DeinitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_I2C2_SCL_I2C2_SCL, 0U); + IOMUXC_SetPinMux(IOMUXC_I2C2_SDA_I2C2_SDA, 0U); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/pin_mux.h b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/pin_mux.h new file mode 100644 index 000000000..de45b6ede --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/pin_mux.h @@ -0,0 +1,67 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void I2C2_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void I2C2_DeinitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/readme.txt b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/readme.txt new file mode 100644 index 000000000..917b2df53 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/master/readme.txt @@ -0,0 +1,72 @@ +Overview +======== +CMSIS-Driver defines generic peripheral driver interfaces for middleware making it reusable across a wide +range of supported microcontroller devices. The API connects microcontroller peripherals with middleware +that implements for example communication stacks, file systems, or graphic user interfaces. +More information and usage method please refer to http://www.keil.com/pack/doc/cmsis/Driver/html/index.html. + +The i2c_interrupt_b2b_transfer_master example shows how to use CMSIS i2c driver as master to do board to board transfer +with interrupt: + +In this example, one i2c instance as master and another i2c instance on the other board as slave. Master sends a +piece of data to slave, and receive a piece of data from slave. This example checks if the data received from +slave is correct. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +I2C one board: + + Transfer data from MASTER_BOARD to SLAVE_BOARD of I2C interface, I2C2 pins of MASTER_BOARD are connected with + I2C2 pins of SLAVE_BOARD +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +SLAVE_BOARD CONNECTS TO MASTER_BOARD +Pin Name Board Location Pin Name Board Location +I2C2_SCL J801-1 I2C2_SCL J801-1 +I2C2_SDA J801-3 I2C2_SDA J801-3 +GND J801-2 GND J801-2 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +When the demo runs successfully, the following message is displayed in the terminal: + +CMSIS I2C board2board interrupt example -- Master transfer. +Master will send data : +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + +Receive sent data from slave : +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + + +End of I2C example . diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/RTE_Device.h b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/RTE_Device.h new file mode 100644 index 000000000..5c404111a --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/RTE_Device.h @@ -0,0 +1,22 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _RTE_DEVICE_H +#define _RTE_DEVICE_H + +extern void I2C2_InitPins(); +extern void I2C2_DeinitPins(); + +/*Driver name mapping*/ +/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. + */ +#define RTE_I2C2 1 +#define RTE_I2C2_PIN_INIT I2C2_InitPins +#define RTE_I2C2_PIN_DEINIT I2C2_DeinitPins + +/*I2C configuration*/ + +#endif /* _RTE_DEVICE_H */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/CMakeLists.txt b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/CMakeLists.txt new file mode 100644 index 000000000..4b2f9e7f3 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/CMakeLists.txt @@ -0,0 +1,112 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(cmsis_ii2c_int_b2b_transfer_slave) + +set(MCUX_SDK_PROJECT_NAME cmsis_ii2c_int_b2b_transfer_slave.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../cmsis_i2c_int_b2b_transfer_slave.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../RTE_Device.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/cmsis_drivers + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../../components/uart + ${ProjDirPath}/../../../../../../../components/lists + ${ProjDirPath}/../../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../../CMSIS/Driver/Include + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_cmsis_ii2c_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(driver_ii2c_MIMX8MQ6) + +include(CMSIS_Driver_Include_I2C_MIMX8MQ6) + +include(CMSIS_Driver_Include_Common_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/cmsis_ii2c_int_b2b_transfer_slave.bin) + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_all.bat b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_all.bat new file mode 100644 index 000000000..d5710260a --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_all.sh b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_all.sh new file mode 100755 index 000000000..2dd7d6219 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..8771607cb --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..1f660e5af --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..0dfc882b6 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..cbb10c43f --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_debug.bat b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_debug.bat new file mode 100644 index 000000000..0636e21b5 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_debug.sh b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_debug.sh new file mode 100755 index 000000000..30c0ab2d5 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_release.bat b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_release.bat new file mode 100644 index 000000000..a34003e0e --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_release.sh b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_release.sh new file mode 100755 index 000000000..012619cda --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/clean.bat b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/clean.sh b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/config.cmake b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/flags.cmake b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/board.c b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/board.h b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/clock_config.c b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/clock_config.h b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/cmsis_i2c_int_b2b_transfer_slave.c b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/cmsis_i2c_int_b2b_transfer_slave.c new file mode 100644 index 000000000..ef65e2532 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/cmsis_i2c_int_b2b_transfer_slave.c @@ -0,0 +1,123 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Standard C Included Files */ +#include +/* SDK Included Files */ +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_i2c.h" +#include "Driver_I2C.h" +#include "fsl_i2c_cmsis.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_I2C_SLAVE Driver_I2C2 +#define I2C_MASTER_SLAVE_ADDR 0x7EU +#define I2C_DATA_LENGTH 32U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint8_t g_slave_buff[I2C_DATA_LENGTH]; +volatile bool g_SlaveCompletionFlag = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t I2C2_GetFreq(void) +{ + return CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootI2c2)) / + (CLOCK_GetRootPostDivider(kCLOCK_RootI2c2)) / 5; /* SYSTEM PLL1 DIV5 */ +} + + +void I2C_SlaveSignalEvent_t(uint32_t event) +{ + if (event == ARM_I2C_EVENT_TRANSFER_DONE) + { + g_SlaveCompletionFlag = true; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + CLOCK_SetRootMux(kCLOCK_RootI2c2, kCLOCK_I2cRootmuxSysPll1Div5); /* Set I2C source to SysPLL1 Div5 160MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootI2c2, 1U, 4U); /* Set root clock to 160MHZ / 4 = 40MHZ */ + + PRINTF("\r\nCMSIS I2C board2board interrupt example -- Slave transfer.\r\n\r\n"); + + /*Init I2C*/ + EXAMPLE_I2C_SLAVE.Initialize(I2C_SlaveSignalEvent_t); + + /* Enable i2c moduole and i2c clock */ + EXAMPLE_I2C_SLAVE.PowerControl(ARM_POWER_FULL); + + /*config slave addr*/ + EXAMPLE_I2C_SLAVE.Control(ARM_I2C_OWN_ADDRESS, I2C_MASTER_SLAVE_ADDR); + + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + g_slave_buff[i] = 0; + } + + /*start transfer*/ + EXAMPLE_I2C_SLAVE.SlaveReceive(g_slave_buff, I2C_DATA_LENGTH); + + /* Wait for transfer completed. */ + while (!g_SlaveCompletionFlag) + { + } + + /* Reset slave completion flag to false. */ + g_SlaveCompletionFlag = false; + + EXAMPLE_I2C_SLAVE.SlaveTransmit(g_slave_buff, I2C_DATA_LENGTH); + + /* Wait for master receive completed.*/ + + PRINTF("Slave received data :"); + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + if (i % 8 == 0) + { + PRINTF("\r\n"); + } + PRINTF("0x%2x ", g_slave_buff[i]); + } + PRINTF("\r\n\r\n"); + + while (!g_SlaveCompletionFlag) + { + } + g_SlaveCompletionFlag = false; + + PRINTF("\r\nEnd of I2C example .\r\n"); + while (1) + { + } +} diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/cmsis_ii2c_int_b2b_transfer_slave_v3_8.xml b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/cmsis_ii2c_int_b2b_transfer_slave_v3_8.xml new file mode 100644 index 000000000..b6c4fac50 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/cmsis_ii2c_int_b2b_transfer_slave_v3_8.xml @@ -0,0 +1,125 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/empty_rsc_table.c b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/fsl_iomuxc.h b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/pin_mux.c b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/pin_mux.c new file mode 100644 index 000000000..190fd35ec --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/pin_mux.c @@ -0,0 +1,125 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +I2C2_InitPins: +- options: {coreID: m4} +- pin_list: + - {pin_num: G7, peripheral: I2C2, signal: i2c_scl, pin_signal: I2C2_SCL, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: F7, peripheral: I2C2, signal: i2c_sda, pin_signal: I2C2_SDA, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM, DSE: OHM_45} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : I2C2_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void I2C2_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_I2C2_SCL_I2C2_SCL, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SCL_I2C2_SCL, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_I2C2_SDA_I2C2_SDA, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SDA_I2C2_SDA, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +I2C2_DeinitPins: +- options: {coreID: m4} +- pin_list: + - {pin_num: G7, peripheral: I2C2, signal: i2c_scl, pin_signal: I2C2_SCL} + - {pin_num: F7, peripheral: I2C2, signal: i2c_sda, pin_signal: I2C2_SDA} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : I2C2_DeinitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void I2C2_DeinitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_I2C2_SCL_I2C2_SCL, 0U); + IOMUXC_SetPinMux(IOMUXC_I2C2_SDA_I2C2_SDA, 0U); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/pin_mux.h b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/pin_mux.h new file mode 100644 index 000000000..de45b6ede --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/pin_mux.h @@ -0,0 +1,67 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void I2C2_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void I2C2_DeinitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/readme.txt b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/readme.txt new file mode 100644 index 000000000..3b98b54ed --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/i2c/int_b2b_transfer/slave/readme.txt @@ -0,0 +1,69 @@ +Overview +======== +CMSIS-Driver defines generic peripheral driver interfaces for middleware making it reusable across a wide +range of supported microcontroller devices. The API connects microcontroller peripherals with middleware +that implements for example communication stacks, file systems, or graphic user interfaces. +More information and usage method please refer to http://www.keil.com/pack/doc/cmsis/Driver/html/index.html. + +The i2c_interrupt_b2b_transfer_master example shows how to use CMSIS i2c driver as master to do board to board transfer +with interrupt: + +In this example, one i2c instance as master and another i2c instance on the other board as slave. Master sends a +piece of data to slave, and receive a piece of data from slave. This example checks if the data received from +slave is correct. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +I2C one board: + + Transfer data from SLAVE_BOARD to MASTER_BOARD of I2C interface, I2C2 pins of SLAVE_BOARD are connected with + I2C2 pins of MASTER_BOARD +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +SLAVE_BOARD CONNECTS TO MASTER_BOARD +Pin Name Board Location Pin Name Board Location +I2C2_SCL J801-1 I2C2_SCL J801-1 +I2C2_SDA J801-3 I2C2_SDA J801-3 +GND J801-2 GND J801-2 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +When the demo runs successfully, the following message is displayed in the terminal: + +CMSIS I2C board2board interrupt example -- Slave transfer. + + +Slave received data : +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + + +End of I2C example . + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/RTE_Device.h b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/RTE_Device.h new file mode 100644 index 000000000..29469e688 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/RTE_Device.h @@ -0,0 +1,26 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _RTE_DEVICE_H +#define _RTE_DEVICE_H + +extern void UART2_InitPins(); +extern void UART2_DeinitPins(); + +/* Driver name mapping. */ +/* User needs to provide the implementation of UARTX_GetFreq/UARTX_InitPins/UARTX_DeinitPins for the enabled UART + * instance. */ +#define RTE_USART2 1 +#define RTE_USART2_PIN_INIT UART2_InitPins +#define RTE_USART2_PIN_DEINIT UART2_DeinitPins +#define RTE_USART2_DMA_EN 0 + +/* UART configuration. */ +#define USART_RX_BUFFER_LEN 64 +#define USART2_RX_BUFFER_ENABLE 1 + +#endif /* _RTE_DEVICE_H */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/CMakeLists.txt b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..abbdcb64f --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,110 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(cmsis_iuart_interrupt_transfer) + +set(MCUX_SDK_PROJECT_NAME cmsis_iuart_interrupt_transfer.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../cmsis_usart_interrupt_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../RTE_Device.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/cmsis_drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../CMSIS/Driver/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_cmsis_iuart_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(CMSIS_Driver_Include_USART_MIMX8MQ6) + +include(CMSIS_Driver_Include_Common_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/cmsis_iuart_interrupt_transfer.bin) + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_all.bat b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_all.sh b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_all.sh new file mode 100755 index 000000000..86624c4e1 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..373514ef3 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c16cafbd5 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_debug.bat b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_debug.sh b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_release.bat b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_release.sh b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/clean.bat b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/clean.sh b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/config.cmake b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/flags.cmake b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ 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-Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/board.c b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/board.h b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/clock_config.c b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/clock_config.h b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/cmsis_iuart_interrupt_transfer_v3_8.xml b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/cmsis_iuart_interrupt_transfer_v3_8.xml new file mode 100644 index 000000000..0edd71c3b --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/cmsis_iuart_interrupt_transfer_v3_8.xml @@ -0,0 +1,124 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/cmsis_usart_interrupt_transfer.c b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/cmsis_usart_interrupt_transfer.c new file mode 100644 index 000000000..26147b821 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/cmsis_usart_interrupt_transfer.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +#include "fsl_uart_cmsis.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_USART Driver_USART2 +#define ECHO_BUFFER_LENGTH 8 +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* USART user SignalEvent */ +void USART_SignalEvent_t(uint32_t event); +/******************************************************************************* + * Variables + ******************************************************************************/ +const uint8_t g_tipString[] = + "USART CMSIS interrupt example\r\nBoard receives 8 characters then sends them out\r\nNow please input:\r\n"; +uint8_t g_txBuffer[ECHO_BUFFER_LENGTH] = {0}; +uint8_t g_rxBuffer[ECHO_BUFFER_LENGTH] = {0}; +volatile bool rxBufferEmpty = true; +volatile bool txBufferFull = false; +volatile bool txOnGoing = false; +volatile bool rxOnGoing = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t UART2_GetFreq(void) +{ + return BOARD_DEBUG_UART_CLK_FREQ; +} +void USART_SignalEvent_t(uint32_t event) +{ + if (ARM_USART_EVENT_SEND_COMPLETE == event) + { + txBufferFull = false; + txOnGoing = false; + } + + if (ARM_USART_EVENT_RECEIVE_COMPLETE == event) + { + rxBufferEmpty = false; + rxOnGoing = false; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t i; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitMemory(); + + DEMO_USART.Initialize(USART_SignalEvent_t); + DEMO_USART.PowerControl(ARM_POWER_FULL); + + /* Set baudrate. */ + DEMO_USART.Control(ARM_USART_MODE_ASYNCHRONOUS, BOARD_DEBUG_UART_BAUDRATE); + + txOnGoing = true; + DEMO_USART.Send(g_tipString, sizeof(g_tipString) - 1); + + /* Wait send finished */ + while (txOnGoing) + { + } + + while (1) + { + /* If g_txBuffer is empty and g_rxBuffer is full, copy g_rxBuffer to g_txBuffer. */ + if ((!rxBufferEmpty) && (!txBufferFull)) + { + memcpy(g_txBuffer, g_rxBuffer, ECHO_BUFFER_LENGTH); + rxBufferEmpty = true; + txBufferFull = true; + } + + /* If RX is idle and g_rxBuffer is empty, start to read data to g_rxBuffer. */ + if ((!rxOnGoing) && rxBufferEmpty) + { + rxOnGoing = true; + DEMO_USART.Receive(g_rxBuffer, ECHO_BUFFER_LENGTH); + } + + /* If TX is idle and g_txBuffer is full, start to send data. */ + if ((!txOnGoing) && txBufferFull) + { + txOnGoing = true; + DEMO_USART.Send(g_txBuffer, ECHO_BUFFER_LENGTH); + } + + /* Delay some time, simulate the app is processing other things, input data save to ring buffer. */ + i = 0x10000U; + while (i--) + { + __NOP(); + } + } +} diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/empty_rsc_table.c b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/fsl_iomuxc.h b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/pin_mux.c b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/pin_mux.c new file mode 100644 index 000000000..228710433 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/pin_mux.c @@ -0,0 +1,111 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +UART2_InitPins: +- options: {callFromInitBoot: 'false', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : UART2_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void UART2_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +UART2_DeinitPins: +- options: {callFromInitBoot: 'false', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: GPIO5, signal: 'gpio_io, 24', pin_signal: UART2_RXD} + - {pin_num: D6, peripheral: GPIO5, signal: 'gpio_io, 25', pin_signal: UART2_TXD} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : UART2_DeinitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void UART2_DeinitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_GPIO5_IO24, 0U); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_GPIO5_IO25, 0U); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/pin_mux.h b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/pin_mux.h new file mode 100644 index 000000000..23bc67e13 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/pin_mux.h @@ -0,0 +1,67 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void UART2_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void UART2_DeinitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/readme.txt b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/readme.txt new file mode 100644 index 000000000..c238650a5 --- /dev/null +++ b/boards/evkmimx8mq/cmsis_driver_examples/uart/interrupt_transfer/readme.txt @@ -0,0 +1,56 @@ +Overview +======== +CMSIS-Driver defines generic peripheral driver interfaces for middleware making it reusable across a wide +range of supported microcontroller devices. The API connects microcontroller peripherals with middleware +that implements for example communication stacks, file systems, or graphic user interfaces. +More information and usage method please refer to http://www.keil.com/pack/doc/cmsis/Driver/html/index.html. + +The cmsis_uart_interrupt_transfer example shows how to use uart cmsis driver in interrupt way: + +In this example, one uart instance connect to PC through uart, the board will +send back all characters that PC send to the board. + +Note: The example echo every 8 characters, so input 8 characters every time. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo. + + +Running the demo +================ +When the demo runs successfully, the log would be seen on the debug terminal like: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +USART CMSIS interrupt example +Board receives 8 characters then sends them out +Now please input: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/CMakeLists.txt b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/CMakeLists.txt new file mode 100644 index 000000000..cc6019f24 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/CMakeLists.txt @@ -0,0 +1,101 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(hello_world) + +set(MCUX_SDK_PROJECT_NAME hello_world.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../hello_world.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/hello_world.bin) + diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_all.bat b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_all.bat new file mode 100644 index 000000000..0cf4090ae --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) 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-DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..c84d78542 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..5aa41a2df --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..3fd6f4a78 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c9e344144 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_debug.bat b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_debug.sh b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_debug.sh new file mode 100755 index 000000000..42803761b --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_release.bat b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_release.sh b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/clean.bat b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/clean.sh b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/config.cmake b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/demo_apps/hello_world/armgcc/flags.cmake b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/flags.cmake new file mode 100755 index 000000000..effc70e24 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/armgcc/flags.cmake @@ -0,0 +1,386 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DPRINTF_FLOAT_ENABLE=0 \ + -DSCANF_FLOAT_ENABLE=0 \ + -DPRINTF_ADVANCED_ENABLE=0 \ + -DSCANF_ADVANCED_ENABLE=0 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DPRINTF_FLOAT_ENABLE=0 \ + -DSCANF_FLOAT_ENABLE=0 \ + -DPRINTF_ADVANCED_ENABLE=0 \ + -DSCANF_ADVANCED_ENABLE=0 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DPRINTF_FLOAT_ENABLE=0 \ + -DSCANF_FLOAT_ENABLE=0 \ + -DPRINTF_ADVANCED_ENABLE=0 \ + -DSCANF_ADVANCED_ENABLE=0 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DPRINTF_FLOAT_ENABLE=0 \ + -DSCANF_FLOAT_ENABLE=0 \ + -DPRINTF_ADVANCED_ENABLE=0 \ + -DSCANF_ADVANCED_ENABLE=0 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/demo_apps/hello_world/board.c b/boards/evkmimx8mq/demo_apps/hello_world/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/demo_apps/hello_world/board.h b/boards/evkmimx8mq/demo_apps/hello_world/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/demo_apps/hello_world/clock_config.c b/boards/evkmimx8mq/demo_apps/hello_world/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/demo_apps/hello_world/clock_config.h b/boards/evkmimx8mq/demo_apps/hello_world/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/demo_apps/hello_world/empty_rsc_table.c b/boards/evkmimx8mq/demo_apps/hello_world/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/demo_apps/hello_world/fsl_iomuxc.h b/boards/evkmimx8mq/demo_apps/hello_world/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/demo_apps/hello_world/hello_world.bin b/boards/evkmimx8mq/demo_apps/hello_world/hello_world.bin new file mode 100755 index 000000000..2e524fe7f Binary files /dev/null and b/boards/evkmimx8mq/demo_apps/hello_world/hello_world.bin differ diff --git a/boards/evkmimx8mq/demo_apps/hello_world/hello_world.c b/boards/evkmimx8mq/demo_apps/hello_world/hello_world.c new file mode 100644 index 000000000..d1f35d920 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/hello_world.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + char ch; + + /* Init board hardware. */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + PRINTF("hello world.\r\n"); + + while (1) + { + ch = GETCHAR(); + PUTCHAR(ch); + } +} diff --git a/boards/evkmimx8mq/demo_apps/hello_world/hello_world_v3_8.xml b/boards/evkmimx8mq/demo_apps/hello_world/hello_world_v3_8.xml new file mode 100644 index 000000000..9a295ffdf --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/hello_world_v3_8.xml @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/demo_apps/hello_world/pin_mux.c b/boards/evkmimx8mq/demo_apps/hello_world/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/demo_apps/hello_world/pin_mux.h b/boards/evkmimx8mq/demo_apps/hello_world/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/demo_apps/hello_world/readme.txt b/boards/evkmimx8mq/demo_apps/hello_world/readme.txt new file mode 100644 index 000000000..ad9ab26bd --- /dev/null +++ b/boards/evkmimx8mq/demo_apps/hello_world/readme.txt @@ -0,0 +1,47 @@ +Overview +======== +The Hello World demo application provides a sanity check for the new SDK build environments and board bring up. The Hello +World demo prints the "Hello World" string to the terminal using the SDK UART drivers. The purpose of this demo is to +show how to use the UART, and to provide a simple project for debugging and further development. +Note: Please input one character at a time. If you input too many characters each time, the receiver may overflow +because the low level UART uses simple polling way for receiving. If you want to try inputting many characters each time, +just define DEBUG_CONSOLE_TRANSFER_NON_BLOCKING in your project to use the advanced debug console utility. + +Toolchain supported +=================== +- GCC ARM Embedded 10.2.1 +- IAR embedded Workbench 9.10.2 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +The log below shows the output of the hello world demo in the terminal window: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +hello world. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/CMakeLists.txt new file mode 100644 index 000000000..95033ca7a --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/CMakeLists.txt @@ -0,0 +1,103 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(ecspi_loopback) + +set(MCUX_SDK_PROJECT_NAME ecspi_loopback.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../ecspi_loopback.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_ecspi_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ecspi_loopback.bin) + diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 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-DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..373514ef3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q 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tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_debug.bat b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/flags.cmake new file mode 100755 index 000000000..effc70e24 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/armgcc/flags.cmake @@ -0,0 +1,386 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + 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+ -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DPRINTF_FLOAT_ENABLE=0 \ + -DSCANF_FLOAT_ENABLE=0 \ + -DPRINTF_ADVANCED_ENABLE=0 \ + -DSCANF_ADVANCED_ENABLE=0 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DPRINTF_FLOAT_ENABLE=0 \ + -DSCANF_FLOAT_ENABLE=0 \ + -DPRINTF_ADVANCED_ENABLE=0 \ + -DSCANF_ADVANCED_ENABLE=0 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/board.c b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/board.h b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/clock_config.c b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/clock_config.h b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/ecspi_loopback.c b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/ecspi_loopback.c new file mode 100644 index 000000000..063df059d --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/ecspi_loopback.c @@ -0,0 +1,114 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "fsl_ecspi.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define ECSPI_TRANSFER_SIZE 64 +#define ECSPI_TRANSFER_BAUDRATE 500000U +#define ECSPI_MASTER_BASEADDR ECSPI1 +#define ECSPI_MASTER_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi1)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi1)) +#define ECSPI_MASTER_TRANSFER_CHANNEL kECSPI_Channel0 + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Main function + */ +int main(void) +{ + uint8_t i; + ecspi_transfer_t masterXfer; + ecspi_master_config_t masterConfig; + uint32_t masterRxData[ECSPI_TRANSFER_SIZE] = {0}; + uint32_t masterTxData[ECSPI_TRANSFER_SIZE] = {0}; + + /* Init board hardware. */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + CLOCK_SetRootMux(kCLOCK_RootEcspi1, kCLOCK_EcspiRootmuxSysPll1); /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootEcspi1, 2U, 5U); /* Set root clock to 800MHZ / 10 = 80MHZ */ + + PRINTF("\r\n***ECSPI Loopback Demo***\r\n"); + PRINTF("\r\nThis demo is a loopback transfer test for ECSPI.\r\n"); + PRINTF("The ECSPI will connect the transmitter and receiver sections internally.\r\n"); + PRINTF("So, there is no need to connect the MOSI and MISO pins.\r\n"); + + /* Master config: + * masterConfig.channel = kECSPI_Channel0; + * masterConfig.burstLength = 8; + * masterConfig.samplePeriodClock = kECSPI_spiClock; + * masterConfig.baudRate_Bps = TRANSFER_BAUDRATE; + * masterConfig.chipSelectDelay = 0; + * masterConfig.samplePeriod = 0; + * masterConfig.txFifoThreshold = 1; + * masterConfig.rxFifoThreshold = 0; + * masterConfig.enableLoopback = true; + */ + ECSPI_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Bps = ECSPI_TRANSFER_BAUDRATE; + masterConfig.enableLoopback = true; + ECSPI_MasterInit(ECSPI_MASTER_BASEADDR, &masterConfig, ECSPI_MASTER_CLK_FREQ); + + for (i = 0; i < ECSPI_TRANSFER_SIZE; i++) + { + masterTxData[i] = i; + } + /*Start master transfer*/ + masterXfer.txData = masterTxData; + masterXfer.rxData = masterRxData; + masterXfer.dataSize = ECSPI_TRANSFER_SIZE; + masterXfer.channel = ECSPI_MASTER_TRANSFER_CHANNEL; + ECSPI_MasterTransferBlocking(ECSPI_MASTER_BASEADDR, &masterXfer); + + /* Compare Tx and Rx data. */ + for (i = 0; i < ECSPI_TRANSFER_SIZE; i++) + { + if (masterTxData[i] != masterRxData[i]) + { + break; + } + } + + if (ECSPI_TRANSFER_SIZE == i) + { + PRINTF("\r\nECSPI loopback test pass!"); + } + else + { + PRINTF("\r\nECSPI loopback test fail!"); + } + + /* Deinit the ECSPI. */ + ECSPI_Deinit(ECSPI_MASTER_BASEADDR); + + while (1) + { + __NOP(); + } +} diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/ecspi_loopback_v3_8.xml b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/ecspi_loopback_v3_8.xml new file mode 100644 index 000000000..f5635bb3c --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/ecspi_loopback_v3_8.xml @@ -0,0 +1,125 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/pin_mux.c b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/pin_mux.h b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/readme.txt b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/readme.txt new file mode 100644 index 000000000..d2ab968bf --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/ecspi/ecspi_loopback/readme.txt @@ -0,0 +1,52 @@ +Overview +======== +The ecspi_loopback demo shows how the ecspi do a loopback transfer internally. +The ECSPI connects the transmitter and receiver sections internally, and the data shifted out from the +most-significant bit of the shift register is looped back into the least-significant bit of the Shift register. +In this way, a self-test of the complete transmit/receive path can be made. The output pins are not affected, +and the input pins are ignored. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MCIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +If the demo run successfully, the below log will be print in the terminal window: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +***ECSPI Loopback Demo*** + +This demo is a loopback transfer test for ECSPI. +The ECSPI will connect the transmitter and receiver sections internally. +So, there is no need to connect the MOSI and MISO pins. + +ECSPI loopback test pass! +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/CMakeLists.txt new file mode 100644 index 000000000..3966e6a5f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/CMakeLists.txt @@ -0,0 +1,103 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(igpio_led_output) + +set(MCUX_SDK_PROJECT_NAME igpio_led_output.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../gpio_led_output.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_igpio_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/igpio_led_output.bin) + diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_all.sh b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_all.sh new file mode 100755 index 000000000..86624c4e1 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..373514ef3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c16cafbd5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_debug.bat b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS 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-ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/board.c b/boards/evkmimx8mq/driver_examples/gpio/led_output/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/board.h b/boards/evkmimx8mq/driver_examples/gpio/led_output/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/clock_config.c b/boards/evkmimx8mq/driver_examples/gpio/led_output/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/clock_config.h b/boards/evkmimx8mq/driver_examples/gpio/led_output/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/gpio/led_output/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/gpio/led_output/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/gpio_led_output.c b/boards/evkmimx8mq/driver_examples/gpio/led_output/gpio_led_output.c new file mode 100644 index 000000000..715e44ebd --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/gpio_led_output.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_gpio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_LED_GPIO GPIO1 +#define EXAMPLE_LED_GPIO_PIN 13U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* The PIN status */ +volatile bool g_pinSet = false; +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + /* Define the init structure for the output LED pin*/ + gpio_pin_config_t led_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; + + /* Board pin, clock, debug console init */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + /* Print a note to terminal. */ + PRINTF("\r\n GPIO Driver example\r\n"); + PRINTF("\r\n The LED is blinking.\r\n"); + + /* Init output LED GPIO. */ + GPIO_PinInit(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, &led_config); + + while (1) + { + SDK_DelayAtLeastUs(100000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1)) + GPIO_PortToggle(EXAMPLE_LED_GPIO, 1u << EXAMPLE_LED_GPIO_PIN); +#else + if (g_pinSet) + { + GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 0U); + g_pinSet = false; + } + else + { + GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 1U); + g_pinSet = true; + } +#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */ + } +} diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/igpio_led_output_v3_8.xml b/boards/evkmimx8mq/driver_examples/gpio/led_output/igpio_led_output_v3_8.xml new file mode 100644 index 000000000..67189d18d --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/igpio_led_output_v3_8.xml @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/pin_mux.c b/boards/evkmimx8mq/driver_examples/gpio/led_output/pin_mux.c new file mode 100644 index 000000000..c6836e128 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/pin_mux.c @@ -0,0 +1,73 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: K6, peripheral: GPIO1, signal: 'gpio_io, 13', pin_signal: GPIO1_IO13} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_GPIO1_IO13_GPIO1_IO13, 0U); + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/pin_mux.h b/boards/evkmimx8mq/driver_examples/gpio/led_output/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/gpio/led_output/readme.txt b/boards/evkmimx8mq/driver_examples/gpio/led_output/readme.txt new file mode 100644 index 000000000..41c97af5a --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpio/led_output/readme.txt @@ -0,0 +1,44 @@ +Overview +======== +The GPIO Example project is a demonstration program that uses the KSDK software to manipulate the general-purpose +outputs. +The example is supported by the set, clear, and toggle write-only registers for each port output data register. The +example take turns to shine the LED. + + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + +#### Please note this application can't support running with Linux BSP! #### + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +When the example runs successfully, you will find the LED RED is taking turns to shine. + diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/CMakeLists.txt new file mode 100644 index 000000000..984851c1f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/CMakeLists.txt @@ -0,0 +1,103 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(gpt_capture) + +set(MCUX_SDK_PROJECT_NAME gpt_capture.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../gpt_capture.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_gpt_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/gpt_capture.bin) + diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD 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a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..373514ef3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c16cafbd5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_debug.bat b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/board.c b/boards/evkmimx8mq/driver_examples/gpt/capture/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/board.h b/boards/evkmimx8mq/driver_examples/gpt/capture/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/clock_config.c b/boards/evkmimx8mq/driver_examples/gpt/capture/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/clock_config.h b/boards/evkmimx8mq/driver_examples/gpt/capture/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/gpt/capture/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/gpt/capture/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/gpt_capture.c b/boards/evkmimx8mq/driver_examples/gpt/capture/gpt_capture.c new file mode 100644 index 000000000..07f45764d --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/gpt_capture.c @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_gpt.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_GPT_IRQn GPT1_IRQn +#define DEMO_GPT_BASE GPT1 +/* GPT channel used for input capture */ +#define BOARD_GPT_INPUT_CAPTURE_CHANNEL kGPT_InputCapture_Channel1 +/* Interrupt to enable and flag to read; depends on the GPT channel used */ +#define EXAMPLE_GPT_CAPTURE_IRQHandler GPT1_IRQHandler +#define BOARD_GPT_CHANNEL_INTERRUPT_ENABLE kGPT_InputCapture1InterruptEnable +#define BOARD_GPT_CHANNEL_FLAG kGPT_InputCapture1Flag + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +volatile bool gptIsrFlag = false; + +/******************************************************************************* + * Code + ******************************************************************************/ +void EXAMPLE_GPT_CAPTURE_IRQHandler(void) +{ + /* Clear interrupt flag.*/ + GPT_ClearStatusFlags(DEMO_GPT_BASE, BOARD_GPT_CHANNEL_FLAG); + + gptIsrFlag = true; + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U || __CORTEX_M == 7U) + __DSB(); +#endif +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t captureVal = 0; + gpt_config_t gptConfig; + + /* Board pin, clock, debug console init */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + /* Print a note to terminal */ + PRINTF("\r\nGPT input capture example\r\n"); + PRINTF("\r\nOnce the input signal is received the input capture value is printed\r\n"); + + GPT_GetDefaultConfig(&gptConfig); + + /* Initialize GPT module */ + GPT_Init(DEMO_GPT_BASE, &gptConfig); + + /* Setup input capture on a gpt channel */ + GPT_SetInputOperationMode(DEMO_GPT_BASE, BOARD_GPT_INPUT_CAPTURE_CHANNEL, kGPT_InputOperation_RiseEdge); + + /* Enable GPT Input Capture1 interrupt */ + GPT_EnableInterrupts(DEMO_GPT_BASE, BOARD_GPT_CHANNEL_INTERRUPT_ENABLE); + + /* Enable at the Interrupt */ + EnableIRQ(DEMO_GPT_IRQn); + + /* Start Timer */ + GPT_StartTimer(DEMO_GPT_BASE); + + while (true) + { + /* Check whether occur interupt */ + if (true == gptIsrFlag) + { + captureVal = GPT_GetInputCaptureValue(DEMO_GPT_BASE, BOARD_GPT_INPUT_CAPTURE_CHANNEL); + PRINTF("\r\n Capture value =%x\r\n", captureVal); + gptIsrFlag = false; + } + else + { + __WFI(); + } + } +} diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/gpt_capture_v3_8.xml b/boards/evkmimx8mq/driver_examples/gpt/capture/gpt_capture_v3_8.xml new file mode 100644 index 000000000..a0e74d767 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/gpt_capture_v3_8.xml @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/pin_mux.c b/boards/evkmimx8mq/driver_examples/gpt/capture/pin_mux.c new file mode 100644 index 000000000..4d63ad033 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/pin_mux.c @@ -0,0 +1,73 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: G4, peripheral: GPT1, signal: 'gpt_capture, 1', pin_signal: SAI3_RXFS} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_SAI3_RXFS_GPT1_CAPTURE1, 0U); + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/pin_mux.h b/boards/evkmimx8mq/driver_examples/gpt/capture/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/gpt/capture/readme.txt b/boards/evkmimx8mq/driver_examples/gpt/capture/readme.txt new file mode 100644 index 000000000..b73fb4c4f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/capture/readme.txt @@ -0,0 +1,46 @@ +Overview +======== +The gpt_capture project is a simple demonstration program of the SDK GPT driver's input capture feature. +The example sets up a GPT channel for rise-edge capture. Once the input signal is received, +this example will print the capture value. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +Connect input signal to TP803 Test Point. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +When the example runs successfully, following information can be seen on the terminal: + +~~~~~~~~~~~~~~~~~~~~~ +GPT input capture example +Once the input signal is received the input capture value is printed +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..9c89bb80a --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/CMakeLists.txt @@ -0,0 +1,103 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(gpt_timer) + +set(MCUX_SDK_PROJECT_NAME gpt_timer.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../gpt_timer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_gpt_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/gpt_timer.bin) + diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q 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-G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_all.sh b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_all.sh new file mode 100755 index 000000000..86624c4e1 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f 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-DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c16cafbd5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_debug.bat b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- 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CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/gpt/timer/armgcc/flags.cmake new file mode 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\ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/board.c b/boards/evkmimx8mq/driver_examples/gpt/timer/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/board.h b/boards/evkmimx8mq/driver_examples/gpt/timer/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/clock_config.c b/boards/evkmimx8mq/driver_examples/gpt/timer/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/clock_config.h b/boards/evkmimx8mq/driver_examples/gpt/timer/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/gpt/timer/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/gpt/timer/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/gpt_timer.c b/boards/evkmimx8mq/driver_examples/gpt/timer/gpt_timer.c new file mode 100644 index 000000000..b26edd05d --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/gpt_timer.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_gpt.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define GPT_IRQ_ID GPT1_IRQn +#define EXAMPLE_GPT GPT1 +#define EXAMPLE_GPT_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootGpt1)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootGpt1)) / 2 /* SYSTEM PLL1 DIV2 */ +#define EXAMPLE_GPT_IRQHandler GPT1_IRQHandler + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +volatile bool gptIsrFlag = false; + +/******************************************************************************* + * Code + ******************************************************************************/ +void EXAMPLE_GPT_IRQHandler(void) +{ + /* Clear interrupt flag.*/ + GPT_ClearStatusFlags(EXAMPLE_GPT, kGPT_OutputCompare1Flag); + + gptIsrFlag = true; +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U || __CORTEX_M == 7U) + __DSB(); +#endif +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t gptFreq; + gpt_config_t gptConfig; + + /* Board pin, clock, debug console init */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + CLOCK_SetRootMux(kCLOCK_RootGpt1, kCLOCK_GptRootmuxSysPll1Div2); /* Set GPT1 source to SYSTEM PLL1 DIV2 400MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootGpt1, 1U, 4U); /* Set root clock to 400MHZ / 4 = 100MHZ */ + + GPT_GetDefaultConfig(&gptConfig); + + /* Initialize GPT module */ + GPT_Init(EXAMPLE_GPT, &gptConfig); + + /* Divide GPT clock source frequency by 3 inside GPT module */ + GPT_SetClockDivider(EXAMPLE_GPT, 3); + + /* Get GPT clock frequency */ + gptFreq = EXAMPLE_GPT_CLK_FREQ; + + /* GPT frequency is divided by 3 inside module */ + gptFreq /= 3; + + /* Set both GPT modules to 1 second duration */ + GPT_SetOutputCompareValue(EXAMPLE_GPT, kGPT_OutputCompare_Channel1, gptFreq); + + /* Enable GPT Output Compare1 interrupt */ + GPT_EnableInterrupts(EXAMPLE_GPT, kGPT_OutputCompare1InterruptEnable); + + /* Enable at the Interrupt */ + EnableIRQ(GPT_IRQ_ID); + + PRINTF("\r\nPress any key to start the example"); + GETCHAR(); + + /* Start Timer */ + PRINTF("\r\nStarting GPT timer ..."); + GPT_StartTimer(EXAMPLE_GPT); + + while (true) + { + /* Check whether occur interupt and toggle LED */ + if (true == gptIsrFlag) + { + PRINTF("\r\n GPT interrupt is occurred !"); + gptIsrFlag = false; + } + else + { + __WFI(); + } + } +} diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/gpt_timer_v3_8.xml b/boards/evkmimx8mq/driver_examples/gpt/timer/gpt_timer_v3_8.xml new file mode 100644 index 000000000..8e2341576 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/gpt_timer_v3_8.xml @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/pin_mux.c b/boards/evkmimx8mq/driver_examples/gpt/timer/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/pin_mux.h b/boards/evkmimx8mq/driver_examples/gpt/timer/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/gpt/timer/readme.txt b/boards/evkmimx8mq/driver_examples/gpt/timer/readme.txt new file mode 100644 index 000000000..e551f27ac --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/gpt/timer/readme.txt @@ -0,0 +1,59 @@ +Overview +======== +The gpt_timer project is a simple demonstration program of the SDK GPT driver. It sets up the GPT +hardware block to trigger a periodic interrupt after every 1 second. When the GPT interrupt is triggered +a message a printed on the UART terminal. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special is needed. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +When the example runs successfully, following information can be seen on the terminal: + +~~~~~~~~~~~~~~~~~~~~~ + +Press any key to start the example +s +Starting GPT timer ... + GPT interrupt is occurred ! + GPT interrupt is occurred ! + GPT interrupt is occurred ! + GPT interrupt is occurred ! + . + . + . + GPT interrupt is occurred ! + . + . + . +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/CMakeLists.txt new file mode 100644 index 000000000..f5f43a914 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/CMakeLists.txt @@ -0,0 +1,103 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(ii2c_interrupt_b2b_transfer_master) + +set(MCUX_SDK_PROJECT_NAME ii2c_interrupt_b2b_transfer_master.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../i2c_interrupt_b2b_transfer_master.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../../components/uart + ${ProjDirPath}/../../../../../../../components/lists + ${ProjDirPath}/../../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_ii2c_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ii2c_interrupt_b2b_transfer_master.bin) + diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_all.bat new file mode 100644 index 000000000..d5710260a --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_all.sh b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_all.sh new file mode 100755 index 000000000..2dd7d6219 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f 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-DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..8771607cb --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..1f660e5af --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..0dfc882b6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..cbb10c43f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_debug.bat b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_debug.bat new file mode 100644 index 000000000..0636e21b5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_debug.sh new file mode 100755 index 000000000..30c0ab2d5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_release.bat new file mode 100644 index 000000000..a34003e0e --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_release.sh new file mode 100755 index 000000000..012619cda --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/board.c b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/board.h b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/clock_config.c b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/clock_config.h b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/i2c_interrupt_b2b_transfer_master.c b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/i2c_interrupt_b2b_transfer_master.c new file mode 100644 index 000000000..1f5ad95cb --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/i2c_interrupt_b2b_transfer_master.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Standard C Included Files */ +#include +/* SDK Included Files */ +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_i2c.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_I2C_MASTER_BASEADDR I2C2 +#define I2C_MASTER_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootI2c2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootI2c2)) / 5 /* SYSTEM PLL1 DIV5 */ + +#define I2C_MASTER_SLAVE_ADDR_7BIT 0x7EU +#define I2C_BAUDRATE 100000U +#define I2C_DATA_LENGTH 32U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint8_t g_master_txBuff[I2C_DATA_LENGTH]; +uint8_t g_master_rxBuff[I2C_DATA_LENGTH]; +i2c_master_handle_t g_m_handle; +volatile bool g_MasterCompletionFlag = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void i2c_master_callback(I2C_Type *base, i2c_master_handle_t *handle, status_t status, void *userData) +{ + /* Signal transfer success when received success status. */ + if (status == kStatus_Success) + { + g_MasterCompletionFlag = true; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + i2c_master_config_t masterConfig; + uint32_t sourceClock; + i2c_master_transfer_t masterXfer; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + CLOCK_SetRootMux(kCLOCK_RootI2c2, kCLOCK_I2cRootmuxSysPll1Div5); /* Set I2C source to SysPLL1 Div5 160MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootI2c2, 1U, 4U); /* Set root clock to 160MHZ / 4 = 40MHZ */ + + PRINTF("\r\nI2C board2board interrupt example -- Master transfer.\r\n"); + + /* Set up i2c master to send data to slave*/ + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + g_master_txBuff[i] = i; + } + + PRINTF("Master will send data :"); + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + if (i % 8 == 0) + { + PRINTF("\r\n"); + } + PRINTF("0x%2x ", g_master_txBuff[i]); + } + PRINTF("\r\n\r\n"); + + /* + * masterConfig->baudRate_Bps = 100000U; + * masterConfig->enableHighDrive = false; + * masterConfig->enableStopHold = false; + * masterConfig->glitchFilterWidth = 0U; + * masterConfig->enableMaster = true; + */ + I2C_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Bps = I2C_BAUDRATE; + + sourceClock = I2C_MASTER_CLK_FREQ; + + I2C_MasterInit(EXAMPLE_I2C_MASTER_BASEADDR, &masterConfig, sourceClock); + + memset(&g_m_handle, 0, sizeof(g_m_handle)); + memset(&masterXfer, 0, sizeof(masterXfer)); + + masterXfer.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT; + masterXfer.direction = kI2C_Write; + masterXfer.subaddress = (uint32_t)NULL; + masterXfer.subaddressSize = 0; + masterXfer.data = g_master_txBuff; + masterXfer.dataSize = I2C_DATA_LENGTH; + masterXfer.flags = kI2C_TransferDefaultFlag; + + I2C_MasterTransferCreateHandle(EXAMPLE_I2C_MASTER_BASEADDR, &g_m_handle, i2c_master_callback, NULL); + I2C_MasterTransferNonBlocking(EXAMPLE_I2C_MASTER_BASEADDR, &g_m_handle, &masterXfer); + + /* Wait for transfer completed. */ + while (!g_MasterCompletionFlag) + { + } + g_MasterCompletionFlag = false; + + PRINTF("Receive sent data from slave :"); + + masterXfer.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT; + masterXfer.direction = kI2C_Read; + masterXfer.subaddress = (uint32_t)NULL; + masterXfer.subaddressSize = 0; + masterXfer.data = g_master_rxBuff; + masterXfer.dataSize = I2C_DATA_LENGTH; + + masterXfer.flags = kI2C_TransferDefaultFlag; + + I2C_MasterTransferNonBlocking(EXAMPLE_I2C_MASTER_BASEADDR, &g_m_handle, &masterXfer); + + /* Reset master completion flag to false. */ + g_MasterCompletionFlag = false; + + /* Wait for transfer completed. */ + while (!g_MasterCompletionFlag) + { + } + g_MasterCompletionFlag = false; + + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + if (i % 8 == 0) + { + PRINTF("\r\n"); + } + PRINTF("0x%2x ", g_master_rxBuff[i]); + } + PRINTF("\r\n\r\n"); + + /* Transfer completed. Check the data.*/ + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + if (g_master_rxBuff[i] != g_master_txBuff[i]) + { + PRINTF("\r\nError occurred in the transfer ! \r\n"); + break; + } + } + + PRINTF("\r\nEnd of I2C example .\r\n"); + while (1) + { + } +} diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/ii2c_interrupt_b2b_transfer_master_v3_8.xml b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/ii2c_interrupt_b2b_transfer_master_v3_8.xml new file mode 100644 index 000000000..abea18bdb --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/ii2c_interrupt_b2b_transfer_master_v3_8.xml @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/pin_mux.c b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/pin_mux.c new file mode 100644 index 000000000..39d2793ce --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/pin_mux.c @@ -0,0 +1,85 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: G7, peripheral: I2C2, signal: i2c_scl, pin_signal: I2C2_SCL, LVTTL: Disabled, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM} + - {pin_num: F7, peripheral: I2C2, signal: i2c_sda, pin_signal: I2C2_SDA, LVTTL: Disabled, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_I2C2_SCL_I2C2_SCL, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SCL_I2C2_SCL, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_I2C2_SDA_I2C2_SDA, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SDA_I2C2_SDA, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/pin_mux.h b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/readme.txt b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/readme.txt new file mode 100644 index 000000000..586255b6a --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/master/readme.txt @@ -0,0 +1,67 @@ +Overview +======== +The i2c_interrupt_b2b_transfer_master example shows how to use i2c driver as master to do board to board transfer +with interrupt: + +In this example, one i2c instance as master and another i2c instance on the other board as slave. Master sends a +piece of data to slave, and receive a piece of data from slave. This example checks if the data received from +slave is correct. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +I2C one board: + + Transfer data from MASTER_BOARD to SLAVE_BOARD of I2C interface, I2C2 pins of MASTER_BOARD are connected with + I2C2 pins of SLAVE_BOARD +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +SLAVE_BOARD CONNECTS TO MASTER_BOARD +Pin Name Board Location Pin Name Board Location +I2C2_SCL J801-1 I2C2_SCL J801-1 +I2C2_SDA J801-3 I2C2_SDA J801-3 +GND J801-2 GND J801-2 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +When the demo runs successfully, the following message is displayed in the terminal: + +I2C board2board interrupt example -- Master transfer. +Master will send data : +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + +Receive sent data from slave : +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + + +End of I2C example . diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/CMakeLists.txt new file mode 100644 index 000000000..0f535f291 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/CMakeLists.txt @@ -0,0 +1,103 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(ii2c_interrupt_b2b_transfer_slave) + +set(MCUX_SDK_PROJECT_NAME ii2c_interrupt_b2b_transfer_slave.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../i2c_interrupt_b2b_transfer_slave.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../../components/uart + ${ProjDirPath}/../../../../../../../components/lists + ${ProjDirPath}/../../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_ii2c_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ii2c_interrupt_b2b_transfer_slave.bin) + diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_all.bat new file mode 100644 index 000000000..d5710260a --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake 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"Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..8771607cb --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..1f660e5af --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..0dfc882b6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..cbb10c43f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_debug.bat b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_debug.bat new file mode 100644 index 000000000..0636e21b5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_debug.sh new file mode 100755 index 000000000..30c0ab2d5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_release.bat new file mode 100644 index 000000000..a34003e0e --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_release.sh new file mode 100755 index 000000000..012619cda --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/board.c b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/board.h b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/clock_config.c b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/clock_config.h b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/i2c_interrupt_b2b_transfer_slave.c b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/i2c_interrupt_b2b_transfer_slave.c new file mode 100644 index 000000000..0131b5c2b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/i2c_interrupt_b2b_transfer_slave.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Standard C Included Files */ +#include +/* SDK Included Files */ +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_i2c.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_I2C_SLAVE_BASEADDR I2C2 + +#define I2C_MASTER_SLAVE_ADDR_7BIT 0x7EU +#define I2C_DATA_LENGTH 32U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint8_t g_slave_buff[I2C_DATA_LENGTH]; +i2c_slave_handle_t g_s_handle; +volatile bool g_SlaveCompletionFlag = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) +{ + switch (xfer->event) + { + /* Transmit request */ + case kI2C_SlaveTransmitEvent: + /* Update information for transmit process */ + xfer->data = g_slave_buff; + xfer->dataSize = I2C_DATA_LENGTH; + break; + + /* Receive request */ + case kI2C_SlaveReceiveEvent: + /* Update information for received process */ + xfer->data = g_slave_buff; + xfer->dataSize = I2C_DATA_LENGTH; + break; + + /* Transfer done */ + case kI2C_SlaveCompletionEvent: + g_SlaveCompletionFlag = true; + break; + + default: + g_SlaveCompletionFlag = true; + break; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + i2c_slave_config_t slaveConfig; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + PRINTF("\r\nI2C board2board interrupt example -- Slave transfer.\r\n\r\n"); + + /*1.Set up i2c slave first*/ + /* + * slaveConfig->addressingMode = kI2C_Address7bit; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->enableWakeUp = false; + * slaveConfig->enableHighDrive = false; + * slaveConfig->enableBaudRateCtl = false; + * slaveConfig->enableSlave = true; + */ + I2C_SlaveGetDefaultConfig(&slaveConfig); + + slaveConfig.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT; + + I2C_SlaveInit(EXAMPLE_I2C_SLAVE_BASEADDR, &slaveConfig); + + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + g_slave_buff[i] = 0; + } + + memset(&g_s_handle, 0, sizeof(g_s_handle)); + + I2C_SlaveTransferCreateHandle(EXAMPLE_I2C_SLAVE_BASEADDR, &g_s_handle, i2c_slave_callback, NULL); + + /* Set up slave transfer. */ + I2C_SlaveTransferNonBlocking(EXAMPLE_I2C_SLAVE_BASEADDR, &g_s_handle, kI2C_SlaveCompletionEvent); + + /* Wait for transfer completed. */ + while (!g_SlaveCompletionFlag) + { + } + g_SlaveCompletionFlag = false; + + PRINTF("Slave received data :"); + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + if (i % 8 == 0) + { + PRINTF("\r\n"); + } + PRINTF("0x%2x ", g_slave_buff[i]); + } + PRINTF("\r\n\r\n"); + + /* Wait for master receive completed.*/ + while (!g_SlaveCompletionFlag) + { + } + g_SlaveCompletionFlag = false; + + PRINTF("\r\nEnd of I2C example .\r\n"); + while (1) + { + } +} diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/ii2c_interrupt_b2b_transfer_slave_v3_8.xml b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/ii2c_interrupt_b2b_transfer_slave_v3_8.xml new file mode 100644 index 000000000..0919554c6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/ii2c_interrupt_b2b_transfer_slave_v3_8.xml @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/pin_mux.c b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/pin_mux.c new file mode 100644 index 000000000..39d2793ce --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/pin_mux.c @@ -0,0 +1,85 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: G7, peripheral: I2C2, signal: i2c_scl, pin_signal: I2C2_SCL, LVTTL: Disabled, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM} + - {pin_num: F7, peripheral: I2C2, signal: i2c_sda, pin_signal: I2C2_SDA, LVTTL: Disabled, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_I2C2_SCL_I2C2_SCL, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SCL_I2C2_SCL, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_I2C2_SDA_I2C2_SDA, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SDA_I2C2_SDA, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/pin_mux.h b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/readme.txt b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/readme.txt new file mode 100644 index 000000000..7bde69a80 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/interrupt_b2b_transfer/slave/readme.txt @@ -0,0 +1,64 @@ +Overview +======== +The i2c_interrupt_b2b_transfer_slave example shows how to use i2c driver as slave to do board to board transfer +with interrupt: + +In this example, one i2c instance as slave and another i2c instance on the other board as master. Master sends a +piece of data to slave, and receive a piece of data from slave. This example checks if the data received from +slave is correct. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +I2C one board: + + Transfer data from SLAVE_BOARD to MASTER_BOARD of I2C interface, I2C2 pins of SLAVE_BOARD are connected with + I2C2 pins of MASTER_BOARD +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +SLAVE_BOARD CONNECTS TO MASTER_BOARD +Pin Name Board Location Pin Name Board Location +I2C2_SCL J801-1 I2C2_SCL J801-1 +I2C2_SDA J801-3 I2C2_SDA J801-3 +GND J801-2 GND J801-2 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +When the demo runs successfully, the following message is displayed in the terminal: + +I2C board2board interrupt example -- Slave transfer. + + +Slave received data : +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + + +End of I2C example . + diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/CMakeLists.txt new file mode 100644 index 000000000..d00918c6e --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/CMakeLists.txt @@ -0,0 +1,103 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(ii2c_polling_b2b_transfer_master) + +set(MCUX_SDK_PROJECT_NAME ii2c_polling_b2b_transfer_master.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../i2c_polling_b2b_transfer_master.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../../components/uart + ${ProjDirPath}/../../../../../../../components/lists + ${ProjDirPath}/../../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_ii2c_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ii2c_polling_b2b_transfer_master.bin) + diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_all.bat new file mode 100644 index 000000000..d5710260a --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" 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a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_release.bat new file mode 100644 index 000000000..a34003e0e --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_release.sh new file mode 100755 index 000000000..012619cda --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/board.c b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/board.h b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/clock_config.c b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/clock_config.h b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/i2c_polling_b2b_transfer_master.c b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/i2c_polling_b2b_transfer_master.c new file mode 100644 index 000000000..e13536613 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/i2c_polling_b2b_transfer_master.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Standard C Included Files */ +#include +/* SDK Included Files */ +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_i2c.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_I2C_MASTER_BASEADDR I2C2 +#define I2C_MASTER_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootI2c2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootI2c2)) / 5 /* SYSTEM PLL1 DIV5 */ + +#define I2C_MASTER_SLAVE_ADDR_7BIT 0x7EU +#define I2C_BAUDRATE 100000U +#define I2C_DATA_LENGTH 32U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint8_t g_master_txBuff[I2C_DATA_LENGTH]; +uint8_t g_master_rxBuff[I2C_DATA_LENGTH]; +volatile bool g_MasterCompletionFlag = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Main function + */ +int main(void) +{ + i2c_master_config_t masterConfig; + uint32_t sourceClock; + i2c_master_transfer_t masterXfer; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + CLOCK_SetRootMux(kCLOCK_RootI2c2, kCLOCK_I2cRootmuxSysPll1Div5); /* Set I2C source to SysPLL1 Div5 160MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootI2c2, 1U, 4U); /* Set root clock to 160MHZ / 4 = 40MHZ */ + + PRINTF("\r\nI2C board2board polling example -- Master transfer.\r\n"); + + /*2.Set up i2c master to send data to slave*/ + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + g_master_txBuff[i] = i; + } + + PRINTF("Master will send data :"); + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + if (i % 8 == 0) + { + PRINTF("\r\n"); + } + PRINTF("0x%2x ", g_master_txBuff[i]); + } + PRINTF("\r\n\r\n"); + + /* + * masterConfig->baudRate_Bps = 100000U; + * masterConfig->enableHighDrive = false; + * masterConfig->enableStopHold = false; + * masterConfig->glitchFilterWidth = 0U; + * masterConfig->enableMaster = true; + */ + I2C_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Bps = I2C_BAUDRATE; + + sourceClock = I2C_MASTER_CLK_FREQ; + + I2C_MasterInit(EXAMPLE_I2C_MASTER_BASEADDR, &masterConfig, sourceClock); + + memset(&masterXfer, 0, sizeof(masterXfer)); + + masterXfer.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT; + masterXfer.direction = kI2C_Write; + masterXfer.subaddress = (uint32_t)NULL; + masterXfer.subaddressSize = 0; + masterXfer.data = g_master_txBuff; + masterXfer.dataSize = I2C_DATA_LENGTH; + masterXfer.flags = kI2C_TransferDefaultFlag; + + I2C_MasterTransferBlocking(EXAMPLE_I2C_MASTER_BASEADDR, &masterXfer); + + PRINTF("Receive sent data from slave :"); + + masterXfer.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT; + masterXfer.direction = kI2C_Read; + masterXfer.subaddress = (uint32_t)NULL; + masterXfer.subaddressSize = 0; + masterXfer.data = g_master_rxBuff; + masterXfer.dataSize = I2C_DATA_LENGTH; + + masterXfer.flags = kI2C_TransferDefaultFlag; + + I2C_MasterTransferBlocking(EXAMPLE_I2C_MASTER_BASEADDR, &masterXfer); + + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + if (i % 8 == 0) + { + PRINTF("\r\n"); + } + PRINTF("0x%2x ", g_master_rxBuff[i]); + } + PRINTF("\r\n\r\n"); + + /* 6.Transfer completed. Check the data.*/ + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + if (g_master_rxBuff[i] != g_master_txBuff[i]) + { + PRINTF("\r\nError occurred in the transfer ! \r\n"); + break; + } + } + + PRINTF("\r\nEnd of I2C example .\r\n"); + while (1) + { + } +} diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/ii2c_polling_b2b_transfer_master_v3_8.xml b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/ii2c_polling_b2b_transfer_master_v3_8.xml new file mode 100644 index 000000000..65b7e5825 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/ii2c_polling_b2b_transfer_master_v3_8.xml @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/pin_mux.c b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/pin_mux.c new file mode 100644 index 000000000..39d2793ce --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/pin_mux.c @@ -0,0 +1,85 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: G7, peripheral: I2C2, signal: i2c_scl, pin_signal: I2C2_SCL, LVTTL: Disabled, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM} + - {pin_num: F7, peripheral: I2C2, signal: i2c_sda, pin_signal: I2C2_SDA, LVTTL: Disabled, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_I2C2_SCL_I2C2_SCL, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SCL_I2C2_SCL, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_I2C2_SDA_I2C2_SDA, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SDA_I2C2_SDA, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/pin_mux.h b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/readme.txt b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/readme.txt new file mode 100644 index 000000000..e9f745d2d --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/master/readme.txt @@ -0,0 +1,68 @@ +Overview +======== +The i2c_polling_b2b_transfer_master example shows how to use i2c driver as master to do board to board transfer +using polling method: + +In this example, one i2c instance as master and another i2c instance on the other board as slave. Master sends a +piece of data to slave, and receive a piece of data from slave. This example checks if the data received from +slave is correct. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +I2C one board: + + Transfer data from MASTER_BOARD to SLAVE_BOARD of I2C interface, I2C2 pins of MASTER_BOARD are connected with + I2C2 pins of SLAVE_BOARD +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +SLAVE_BOARD CONNECTS TO MASTER_BOARD +Pin Name Board Location Pin Name Board Location +I2C2_SCL J801-1 I2C2_SCL J801-1 +I2C2_SDA J801-3 I2C2_SDA J801-3 +GND J801-2 GND J801-2 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +When the demo runs successfully, the following message is displayed in the terminal: + + +I2C board2board polling example -- Master transfer. +Master will send data : +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + +Receive sent data from slave : +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + + +End of I2C example . diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/CMakeLists.txt new file mode 100644 index 000000000..b9f03f16d --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/CMakeLists.txt @@ -0,0 +1,103 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(ii2c_polling_b2b_transfer_slave) + +set(MCUX_SDK_PROJECT_NAME ii2c_polling_b2b_transfer_slave.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../i2c_polling_b2b_transfer_slave.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../../components/uart + ${ProjDirPath}/../../../../../../../components/lists + ${ProjDirPath}/../../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_ii2c_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ii2c_polling_b2b_transfer_slave.bin) + diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_all.bat new file mode 100644 index 000000000..d5710260a --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" 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-DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_debug.sh new file mode 100755 index 000000000..30c0ab2d5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_release.bat new file mode 100644 index 000000000..a34003e0e --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_release.sh new file mode 100755 index 000000000..012619cda --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/board.c b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/board.h b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/clock_config.c b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/clock_config.h b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/i2c_polling_b2b_transfer_slave.c b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/i2c_polling_b2b_transfer_slave.c new file mode 100644 index 000000000..78e1832d1 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/i2c_polling_b2b_transfer_slave.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Standard C Included Files */ +#include +/* SDK Included Files */ +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_i2c.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_I2C_SLAVE_BASEADDR I2C2 + +#define I2C_MASTER_SLAVE_ADDR_7BIT 0x7EU +#define I2C_DATA_LENGTH 32U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint8_t g_slave_buff[I2C_DATA_LENGTH]; +i2c_slave_handle_t g_s_handle; +volatile bool g_SlaveCompletionFlag = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) +{ + switch (xfer->event) + { + /* Transmit request */ + case kI2C_SlaveTransmitEvent: + /* Update information for transmit process */ + xfer->data = g_slave_buff; + xfer->dataSize = I2C_DATA_LENGTH; + break; + + /* Receive request */ + case kI2C_SlaveReceiveEvent: + /* Update information for received process */ + xfer->data = g_slave_buff; + xfer->dataSize = I2C_DATA_LENGTH; + break; + + /* Transfer done */ + case kI2C_SlaveCompletionEvent: + g_SlaveCompletionFlag = true; + break; + + default: + g_SlaveCompletionFlag = true; + break; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + i2c_slave_config_t slaveConfig; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + PRINTF("\r\nI2C board2board polling example -- Slave transfer.\r\n\r\n"); + + /*1.Set up i2c slave first*/ + /* + * slaveConfig->addressingMode = kI2C_Address7bit; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->enableWakeUp = false; + * slaveConfig->enableHighDrive = false; + * slaveConfig->enableBaudRateCtl = false; + * slaveConfig->enableSlave = true; + */ + I2C_SlaveGetDefaultConfig(&slaveConfig); + + slaveConfig.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT; + + I2C_SlaveInit(EXAMPLE_I2C_SLAVE_BASEADDR, &slaveConfig); + + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + g_slave_buff[i] = 0; + } + + memset(&g_s_handle, 0, sizeof(g_s_handle)); + + I2C_SlaveTransferCreateHandle(EXAMPLE_I2C_SLAVE_BASEADDR, &g_s_handle, i2c_slave_callback, NULL); + + /* Set up slave transfer. */ + I2C_SlaveTransferNonBlocking(EXAMPLE_I2C_SLAVE_BASEADDR, &g_s_handle, kI2C_SlaveCompletionEvent); + + /* Wait for transfer completed. */ + while (!g_SlaveCompletionFlag) + { + } + g_SlaveCompletionFlag = false; + + PRINTF("Slave received data :"); + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) + { + if (i % 8 == 0) + { + PRINTF("\r\n"); + } + PRINTF("0x%2x ", g_slave_buff[i]); + } + PRINTF("\r\n\r\n"); + + /* Wait for master receive completed.*/ + while (!g_SlaveCompletionFlag) + { + } + g_SlaveCompletionFlag = false; + + PRINTF("\r\nEnd of I2C example .\r\n"); + while (1) + { + } +} diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/ii2c_polling_b2b_transfer_slave_v3_8.xml b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/ii2c_polling_b2b_transfer_slave_v3_8.xml new file mode 100644 index 000000000..96a194871 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/ii2c_polling_b2b_transfer_slave_v3_8.xml @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/pin_mux.c b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/pin_mux.c new file mode 100644 index 000000000..39d2793ce --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/pin_mux.c @@ -0,0 +1,85 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: G7, peripheral: I2C2, signal: i2c_scl, pin_signal: I2C2_SCL, LVTTL: Disabled, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM} + - {pin_num: F7, peripheral: I2C2, signal: i2c_sda, pin_signal: I2C2_SDA, LVTTL: Disabled, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_I2C2_SCL_I2C2_SCL, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SCL_I2C2_SCL, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_I2C2_SDA_I2C2_SDA, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SDA_I2C2_SDA, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/pin_mux.h b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/readme.txt b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/readme.txt new file mode 100644 index 000000000..88ee6738b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/i2c/polling_b2b_transfer/slave/readme.txt @@ -0,0 +1,63 @@ +Overview +======== +The i2c_polling_b2b_transfer_slave example shows how to use i2c driver as slave to do board to board transfer +with a polling master: + +In this example, one i2c instance as slave and another i2c instance on the other board as master. Master sends a +piece of data to slave, and receive a piece of data from slave. This example checks if the data received from +slave is correct. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +I2C one board: + + Transfer data from MASTER_BOARD to SLAVE_BOARD of I2C interface, I2C2 pins of MASTER_BOARD are connected with + I2C2 pins of SLAVE_BOARD +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +SLAVE_BOARD CONNECTS TO MASTER_BOARD +Pin Name Board Location Pin Name Board Location +I2C2_SCL J801-1 I2C2_SCL J801-1 +I2C2_SDA J801-3 I2C2_SDA J801-3 +GND J801-2 GND J801-2 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +When the demo runs successfully, the following message is displayed in the terminal: + +I2C board2board polling example -- Slave transfer. + + +Slave received data : +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + + +End of I2C example . diff --git a/boards/evkmimx8mq/driver_examples/pwm/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/pwm/armgcc/CMakeLists.txt new file mode 100644 index 000000000..ff85a846e --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/armgcc/CMakeLists.txt @@ -0,0 +1,103 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(ipwm) + +set(MCUX_SDK_PROJECT_NAME ipwm.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../pwm.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(driver_ipwm_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ipwm.bin) + diff --git a/boards/evkmimx8mq/driver_examples/pwm/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/pwm/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/pwm/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/pwm/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_all.bat new file mode 100644 index 000000000..0cf4090ae --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if 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-DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_all.sh b/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_all.sh new file mode 100755 index 000000000..dbf5b91b5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..c84d78542 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..5aa41a2df --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ 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. +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/pwm/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/pwm/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/pwm/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/pwm/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/pwm/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/pwm/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/pwm/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/pwm/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/pwm/board.c b/boards/evkmimx8mq/driver_examples/pwm/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/pwm/board.h b/boards/evkmimx8mq/driver_examples/pwm/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/pwm/clock_config.c b/boards/evkmimx8mq/driver_examples/pwm/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/pwm/clock_config.h b/boards/evkmimx8mq/driver_examples/pwm/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/pwm/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/pwm/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/pwm/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/pwm/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/pwm/ipwm_v3_8.xml b/boards/evkmimx8mq/driver_examples/pwm/ipwm_v3_8.xml new file mode 100644 index 000000000..4a88b412d --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/ipwm_v3_8.xml @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/pwm/pin_mux.c b/boards/evkmimx8mq/driver_examples/pwm/pin_mux.c new file mode 100644 index 000000000..2cfd18043 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/pin_mux.c @@ -0,0 +1,76 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D3, peripheral: PWM4, signal: pwm_out, pin_signal: SAI3_MCLK, SRE: MEDIUM, DSE: OHM_45} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_SAI3_MCLK_PWM4_OUT, 0U); + IOMUXC_SetPinConfig(IOMUXC_SAI3_MCLK_PWM4_OUT, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U)); + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/pwm/pin_mux.h b/boards/evkmimx8mq/driver_examples/pwm/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/pwm/pwm.c b/boards/evkmimx8mq/driver_examples/pwm/pwm.c new file mode 100644 index 000000000..365f2ffaa --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/pwm.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_pwm.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_PWM_BASEADDR PWM4 +#define DEMO_PWM_IRQn PWM4_IRQn +#define DEMO_PWM_IRQHandler PWM4_IRQHandler +/*! @brief PWM period value. PWMO (Hz) = PCLK(Hz) / (period +2) */ +#define PWM_PERIOD_VALUE 30 + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +volatile uint32_t pwmDutycycle = 0U; +volatile bool pwmDutyUp = true; /* Indicate PWM Duty cycle is increase or decrease */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +void DEMO_PWM_IRQHandler(void) +{ + /* Gets interrupt kPWM_FIFOEmptyFlag */ + if (PWM_GetStatusFlags(DEMO_PWM_BASEADDR) & kPWM_FIFOEmptyFlag) + { + if (pwmDutyUp) + { + /* Increase duty cycle until it reach limited value. */ + if (++pwmDutycycle > PWM_PERIOD_VALUE) + { + pwmDutycycle = PWM_PERIOD_VALUE; + pwmDutyUp = false; + } + } + else + { + /* Decrease duty cycle until it reach limited value. */ + if (--pwmDutycycle == 0U) + { + pwmDutyUp = true; + } + } + /* Write duty cycle to PWM sample register. */ + PWM_SetSampleValue(DEMO_PWM_BASEADDR, pwmDutycycle); + /* Clear kPWM_FIFOEmptyFlag */ + PWM_clearStatusFlags(DEMO_PWM_BASEADDR, kPWM_FIFOEmptyFlag); + } + SDK_ISR_EXIT_BARRIER; +} + +/*! + * @brief Main function + */ +int main(void) +{ + pwm_config_t pwmConfig; + + /* Board pin, clock, debug console init */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + PRINTF("\r\nPWM driver example.\r\n"); + + /*! + * config->enableStopMode = false; + * config->enableDozeMode = false; + * config->enableWaitMode = false; + * config->enableDebugMode = false; + * config->clockSource = kPWM_LowFrequencyClock; + * config->prescale = 0U; + * config->outputConfig = kPWM_SetAtRolloverAndClearAtcomparison; + * config->fifoWater = kPWM_FIFOWaterMark_2; + * config->sampleRepeat = kPWM_EachSampleOnce; + * config->byteSwap = kPWM_ByteNoSwap; + * config->halfWordSwap = kPWM_HalfWordNoSwap; + */ + PWM_GetDefaultConfig(&pwmConfig); + + /* Initialize PWM module */ + PWM_Init(DEMO_PWM_BASEADDR, &pwmConfig); + + /* Enable FIFO empty interrupt */ + PWM_EnableInterrupts(DEMO_PWM_BASEADDR, kPWM_FIFOEmptyInterruptEnable); + + /* Three initial samples be written to the PWM Sample Register */ + for (pwmDutycycle = 0u; pwmDutycycle < 3; pwmDutycycle++) + { + PWM_SetSampleValue(DEMO_PWM_BASEADDR, pwmDutycycle); + } + + /* Check and Clear interrupt status flags */ + if (PWM_GetStatusFlags(DEMO_PWM_BASEADDR)) + { + PWM_clearStatusFlags(DEMO_PWM_BASEADDR, + kPWM_FIFOEmptyFlag | kPWM_RolloverFlag | kPWM_CompareFlag | kPWM_FIFOWriteErrorFlag); + } + + /* Write the period to the PWM Period Register */ + PWM_SetPeriodValue(DEMO_PWM_BASEADDR, PWM_PERIOD_VALUE); + + /* Enable PWM interrupt request */ + EnableIRQ(DEMO_PWM_IRQn); + + PWM_StartTimer(DEMO_PWM_BASEADDR); + + while (1) + { + } +} diff --git a/boards/evkmimx8mq/driver_examples/pwm/readme.txt b/boards/evkmimx8mq/driver_examples/pwm/readme.txt new file mode 100644 index 000000000..bad8b4e15 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/pwm/readme.txt @@ -0,0 +1,50 @@ +Overview +======== +The PWM project is a simple demonstration program of the SDK PWM driver. It sets up the PWM hardware +block to output PWM signals on one PWM channel. The example also shows PWM duty cycle is increase or decrease. +The FIFO empty interrupt is provided. A new value will be loaded into FIFO when FIFO empty status bit is set. +The PWM will run at the last set duty-cycle setting if all the values of the FIFO has been utilized, +until the FIFO is reloaded or the PWM is disabled. When a new value is written, the duty cycle changes after the current period is over. +The outputs can be observed by oscilloscope. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +Use Oscilloscope to measure and observe the Test Point TP1801 output signal. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + + +Running the demo +================ +These instructions are displayed/shown on the terminal window: +~~~~~~~~~~~~~~~~~~~~~~~ +PWM driver example. +~~~~~~~~~~~~~~~~~~~~~~~ + + diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/app.h b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/app.h new file mode 100644 index 000000000..0d8d24804 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/app.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _APP_H_ +#define _APP_H_ +/*${header:start}*/ +#include "fsl_qspi.h" +/*${header:end}*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*${macro:start}*/ +#define EXAMPLE_QSPI QuadSPI +#define QSPI_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootQspi)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootQspi)) / 8 /* SYSTEM PLL1 DIV8 */ +#define FLASH_PAGE_SIZE 256U +#define FLASH_SECTORE_SIZE 0x10000 +#define FLASH_SIZE 0x10000000U +#define QSPI_ERASE_ADDR_OFFSET 0x40000U +/*${macro:end}*/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*${prototype:start}*/ +extern uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH]; +extern qspi_flash_config_t single_config; + +void BOARD_InitHardware(void); + +/*${prototype:end}*/ + +#endif /* _APP_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..6c1c47188 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,105 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(qspi_polling_transfer) + +set(MCUX_SDK_PROJECT_NAME qspi_polling_transfer.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../qspi_polling_transfer.c" +"${ProjDirPath}/../qspi_nor_flash_ops.c" +"${ProjDirPath}/../app.h" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_qspi_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/qspi_polling_transfer.bin) + diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make 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-DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..373514ef3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c16cafbd5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_debug.bat b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/armgcc/config.cmake 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-fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/board.c b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/board.h b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/clock_config.c b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/clock_config.h b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/pin_mux.c b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/pin_mux.c new file mode 100644 index 000000000..3e8ef539b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/pin_mux.c @@ -0,0 +1,102 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: G19, peripheral: QSPI, signal: qspi_a_sclk, pin_signal: NAND_ALE, HYS: Enabled, SRE: SLOW, DSE: OHM_105} + - {pin_num: H19, peripheral: QSPI, signal: qspi_a_ss0_b, pin_signal: NAND_CE0_B, HYS: Enabled, SRE: SLOW, DSE: OHM_105} + - {pin_num: G20, peripheral: QSPI, signal: 'qspi_a_data, 0', pin_signal: NAND_DATA00, HYS: Enabled, SRE: SLOW, DSE: OHM_105} + - {pin_num: J20, peripheral: QSPI, signal: 'qspi_a_data, 1', pin_signal: NAND_DATA01, HYS: Enabled, SRE: SLOW, DSE: OHM_105} + - {pin_num: H22, peripheral: QSPI, signal: 'qspi_a_data, 2', pin_signal: NAND_DATA02, HYS: Enabled, SRE: SLOW, DSE: OHM_105} + - {pin_num: J21, peripheral: QSPI, signal: 'qspi_a_data, 3', pin_signal: NAND_DATA03, HYS: Enabled, SRE: SLOW, DSE: OHM_105} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_NAND_ALE_QSPI_A_SCLK, 0U); + IOMUXC_SetPinConfig(IOMUXC_NAND_ALE_QSPI_A_SCLK, + IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_NAND_CE0_B_QSPI_A_SS0_B, 0U); + IOMUXC_SetPinConfig(IOMUXC_NAND_CE0_B_QSPI_A_SS0_B, + IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_NAND_DATA00_QSPI_A_DATA0, 0U); + IOMUXC_SetPinConfig(IOMUXC_NAND_DATA00_QSPI_A_DATA0, + IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_NAND_DATA01_QSPI_A_DATA1, 0U); + IOMUXC_SetPinConfig(IOMUXC_NAND_DATA01_QSPI_A_DATA1, + IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_NAND_DATA02_QSPI_A_DATA2, 0U); + IOMUXC_SetPinConfig(IOMUXC_NAND_DATA02_QSPI_A_DATA2, + IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_NAND_DATA03_QSPI_A_DATA3, 0U); + IOMUXC_SetPinConfig(IOMUXC_NAND_DATA03_QSPI_A_DATA3, + IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | + IOMUXC_SW_PAD_CTL_PAD_VSEL(3U)); + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/pin_mux.h b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/qspi_nor_flash_ops.c b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/qspi_nor_flash_ops.c new file mode 100644 index 000000000..c9d96164a --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/qspi_nor_flash_ops.c @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "app.h" +#include "fsl_qspi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + *****************************************************************************/ +extern uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH]; +extern qspi_dqs_config_t dqsConfig; +extern qspi_flash_config_t single_config; +/******************************************************************************* + * Code + ******************************************************************************/ +/* Check if serial flash erase or program finished. */ +void check_if_finished(void) +{ + uint32_t val = 0; + /* Check WIP bit */ + do + { + while (QSPI_GetStatusFlags(EXAMPLE_QSPI) & kQSPI_Busy) + { + } + QSPI_ClearFifo(EXAMPLE_QSPI, kQSPI_RxFifo); + QSPI_ExecuteIPCommand(EXAMPLE_QSPI, 12U); + while (QSPI_GetStatusFlags(EXAMPLE_QSPI) & kQSPI_Busy) + { + } + val = EXAMPLE_QSPI->RBDR[0]; + /* Clear ARDB area */ + QSPI_ClearErrorFlag(EXAMPLE_QSPI, kQSPI_RxBufferDrain); + } while (val & 0x1); +} + +/* Write enable command */ +void cmd_write_enable(void) +{ + while (QSPI_GetStatusFlags(EXAMPLE_QSPI) & kQSPI_Busy) + { + } + QSPI_ExecuteIPCommand(EXAMPLE_QSPI, 4U); +} + +#if defined(FLASH_ENABLE_QUAD_CMD) +/* Enable Quad mode */ +void enable_quad_mode(void) +{ + uint32_t val[4] = {FLASH_ENABLE_QUAD_CMD, 0, 0, 0}; + + while (QSPI_GetStatusFlags(EXAMPLE_QSPI) & kQSPI_Busy) + { + } + QSPI_SetIPCommandAddress(EXAMPLE_QSPI, FSL_FEATURE_QSPI_AMBA_BASE); + + /* Clear Tx FIFO */ + QSPI_ClearFifo(EXAMPLE_QSPI, kQSPI_TxFifo); + + /* Write enable */ + cmd_write_enable(); + + /* Write data into TX FIFO, needs to write at least 16 bytes of data */ + QSPI_WriteBlocking(EXAMPLE_QSPI, val, 16U); + + /* Set seq id, write register */ + QSPI_ExecuteIPCommand(EXAMPLE_QSPI, 20); + + /* Wait until finished */ + check_if_finished(); +} +#endif + +void enable_ddr_mode(void) +{ + QSPI_EnableDDRMode(EXAMPLE_QSPI, true); +} + +#if defined(FLASH_ENABLE_OCTAL_CMD) +/* Enable Quad DDR mode */ +void enable_octal_mode(void) +{ + uint32_t val[4] = {FLASH_ENABLE_OCTAL_CMD, 0, 0, 0}; + + while (QSPI_GetStatusFlags(EXAMPLE_QSPI) & kQSPI_Busy) + { + } + QSPI_SetIPCommandAddress(EXAMPLE_QSPI, FSL_FEATURE_QSPI_AMBA_BASE); + + /* Clear Tx FIFO */ + QSPI_ClearFifo(EXAMPLE_QSPI, kQSPI_TxFifo); + + /* Write enable */ + QSPI_ExecuteIPCommand(EXAMPLE_QSPI, 32U); + + /* Write data into TX FIFO, needs to write at least 16 bytes of data */ + QSPI_WriteBlocking(EXAMPLE_QSPI, val, 16U); + + /* Set seq id, write register */ + QSPI_ExecuteIPCommand(EXAMPLE_QSPI, 20); + + /* Wait until finished */ + check_if_finished(); +} +#endif + +/*Erase sector */ +void erase_sector(uint32_t addr) +{ + while (QSPI_GetStatusFlags(EXAMPLE_QSPI) & kQSPI_Busy) + { + } + QSPI_ClearFifo(EXAMPLE_QSPI, kQSPI_TxFifo); + QSPI_SetIPCommandAddress(EXAMPLE_QSPI, addr); + cmd_write_enable(); + QSPI_ExecuteIPCommand(EXAMPLE_QSPI, 28U); + check_if_finished(); + +#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) + QSPI_ClearCache(EXAMPLE_QSPI); +#endif +} + +/* Erase all command */ +void erase_all(void) +{ + while (QSPI_GetStatusFlags(EXAMPLE_QSPI) & kQSPI_Busy) + { + } + QSPI_SetIPCommandAddress(EXAMPLE_QSPI, FSL_FEATURE_QSPI_AMBA_BASE); + /* Write enable*/ + cmd_write_enable(); + QSPI_ExecuteIPCommand(EXAMPLE_QSPI, 8U); + check_if_finished(); +#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) + QSPI_ClearCache(EXAMPLE_QSPI); +#endif +} + +/* Program page into serial flash using QSPI polling way */ +void program_page(uint32_t dest_addr, uint32_t *src_addr) +{ + uint32_t leftLongWords = 0; + + while (QSPI_GetStatusFlags(EXAMPLE_QSPI) & kQSPI_Busy) + { + } + QSPI_ClearFifo(EXAMPLE_QSPI, kQSPI_TxFifo); + + QSPI_SetIPCommandAddress(EXAMPLE_QSPI, dest_addr); + cmd_write_enable(); + while (QSPI_GetStatusFlags(EXAMPLE_QSPI) & kQSPI_Busy) + { + } + + /* First write some data into TXFIFO to prevent from underrun */ + QSPI_WriteBlocking(EXAMPLE_QSPI, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4); + src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH; + + /* Start the program */ + QSPI_SetIPCommandSize(EXAMPLE_QSPI, FLASH_PAGE_SIZE); + QSPI_ExecuteIPCommand(EXAMPLE_QSPI, 16U); + + leftLongWords = FLASH_PAGE_SIZE - 16 * sizeof(uint32_t); + QSPI_WriteBlocking(EXAMPLE_QSPI, src_addr, leftLongWords); + + /* Wait until flash finished program */ + check_if_finished(); + while (QSPI_GetStatusFlags(EXAMPLE_QSPI) & (kQSPI_Busy | kQSPI_IPAccess)) + { + } + +#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) + QSPI_ClearCache(EXAMPLE_QSPI); +#endif +} + +void qspi_nor_flash_init(QuadSPI_Type *base) +{ + uint32_t clockSourceFreq = 0; + qspi_config_t config = {0}; + + /*Get QSPI default settings and configure the qspi */ + QSPI_GetDefaultQspiConfig(&config); + + /*Set AHB buffer size for reading data through AHB bus */ + if (FLASH_PAGE_SIZE <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE) + { + config.AHBbufferSize[3] = FLASH_PAGE_SIZE; + } + else + { + config.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; + } + clockSourceFreq = QSPI_CLK_FREQ; + + QSPI_Init(base, &config, clockSourceFreq); + +#if defined(FLASH_NEED_DQS) + /* Set DQS config */ + QSPI_SetDqsConfig(base, &dqsConfig); +#endif + + /*According to serial flash feature to configure flash settings */ + QSPI_SetFlashConfig(base, &single_config); + +#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) + QSPI_ClearCache(base); +#endif +} diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/qspi_polling_transfer.c b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/qspi_polling_transfer.c new file mode 100644 index 000000000..16806337f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/qspi_polling_transfer.c @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "app.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_qspi.h" +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DUMMY_MASTER (0xE) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +extern void qspi_nor_flash_init(QuadSPI_Type *base); +#if defined(FLASH_ENABLE_QUAD_CMD) +extern void enable_quad_mode(void); +#endif +#if defined(FLASH_ENABLE_OCTAL_CMD) +extern void enable_octal_mode(void); +#endif +extern void erase_sector(uint32_t addr); +extern void erase_all(void); +extern void program_page(uint32_t dest_addr, uint32_t *src_addr); +extern void BOARD_SetQspiClock(QuadSPI_Type *qspi, uint32_t qspiClockSrc, uint32_t divider); +/******************************************************************************* + * Variables + ******************************************************************************/ +static uint32_t buff[64]; /* Test data */ +#if !defined(FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) +static bool isDivNeedRestore = false; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = + {/* Seq0 :Quad Read */ + /* CMD: 0x6B - Quad Read, Single pad */ + /* ADDR: 0x18 - 24bit address, Single pads */ + /* DUMMY: 0x06 - 8 clock cyles, Quad pads */ + /* READ: 0x80 - Read 128 bytes, Quad pads */ + /* JUMP_ON_CS: 0 */ + [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x6B, QSPI_ADDR, QSPI_PAD_1, 0x18), + [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x08, QSPI_READ, QSPI_PAD_4, 0x80), + [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0), + + /* Seq1: Write Enable */ + /* CMD: 0x06 - Write Enable, Single pad */ + [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0), + + /* Seq2: Erase All */ + /* CMD: 0x60 - Erase All chip, Single pad */ + [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0), + + /* Seq3: Read Status */ + /* CMD: 0x05 - Read Status, single pad */ + /* READ: 0x01 - Read 1 byte */ + [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1), + + /* Seq4: Page Program */ + /* CMD: 0x02 - Page Program, Single pad */ + /* ADDR: 0x18 - 24bit address, Quad pad */ + /* WRITE: 0x80 - Write 128 bytes at one pass, Quad pad */ + [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x38, QSPI_ADDR, QSPI_PAD_4, 0x18), + [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_4, 0x80, 0, 0, 0), + + /* Seq5: Write Register */ + /* CMD: 0x01 - Write Status Register, single pad */ + /* WRITE: 0x01 - Write 1 byte of data, single pad */ + [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x61, QSPI_WRITE, QSPI_PAD_1, 0x1), + + /* Seq6: Read Config Register */ + /* CMD: 0x15 - Read Config register, single pad */ + /* READ: 0x01 - Read 1 byte */ + [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1), + + /* Seq7: Erase Sector */ + /* CMD: 0x20 - Sector Erase, single pad */ + /* ADDR: 0x18 - 24 bit address, single pad */ + [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xD8, QSPI_ADDR, QSPI_PAD_1, 0x18), + + /* Match MISRA rule */ + [63] = 0}; + +qspi_flash_config_t single_config = {.flashA1Size = FLASH_SIZE, /* 4MB */ + .flashA2Size = 0, +#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) + .flashB1Size = FLASH_SIZE, + .flashB2Size = 0, +#endif +#if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH) + .dataHoldTime = 0, +#endif + .CSHoldTime = 0, + .CSSetupTime = 0, + .cloumnspace = 0, + .dataLearnValue = 0, + .endian = kQSPI_64LittleEndian, + .enableWordAddress = false}; +/* Use QSPI polling way to program serial flash */ +void qspi_polling(void) +{ + uint32_t i = 0; + uint32_t err = 0; + uint32_t addr = 0; +#if !defined(QSPI_ERASE_ADDR_OFFSET) + addr = FSL_FEATURE_QSPI_AMBA_BASE; +#else + addr = FSL_FEATURE_QSPI_AMBA_BASE + QSPI_ERASE_ADDR_OFFSET; +#endif + erase_sector(addr); + PRINTF("Erase finished!\r\n"); + +#if !defined(FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) + /* Reduce frequency while clock divder is less than 2 */ + uint8_t qspiClockDiv = ((EXAMPLE_QSPI->MCR & QuadSPI_MCR_SCLKCFG_MASK) >> QuadSPI_MCR_SCLKCFG_SHIFT) + 1U; + if (qspiClockDiv == 1U) + { + /* Reduce the frequency */ + isDivNeedRestore = true; + QSPI_Enable(EXAMPLE_QSPI, false); + EXAMPLE_QSPI->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK; + EXAMPLE_QSPI->MCR |= QuadSPI_MCR_SCLKCFG(1U); + QSPI_Enable(EXAMPLE_QSPI, true); + } +#endif + +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) + BOARD_SetQspiClock(EXAMPLE_QSPI, CLKCTL0_OSPIFCLKSEL_SEL(0), 10); +#endif + + /* Program pages in a sector */ + for (i = 0; i < FLASH_SECTORE_SIZE / FLASH_PAGE_SIZE; i++) + { + program_page(addr + i * FLASH_PAGE_SIZE, buff); + } + PRINTF("Program data finished!\r\n"); + +#if !defined(FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) + /* Restore the frequency if needed */ + if (isDivNeedRestore) + { + QSPI_Enable(EXAMPLE_QSPI, false); + EXAMPLE_QSPI->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK; + EXAMPLE_QSPI->MCR |= QuadSPI_MCR_SCLKCFG(0U); + QSPI_Enable(EXAMPLE_QSPI, true); + } +#endif + +#if defined(FLASH_NEED_DQS) +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) + BOARD_SetQspiClock(EXAMPLE_QSPI, CLKCTL0_OSPIFCLKSEL_SEL(0), 2); +#else + /* Re-configure QSPI Serial clock frequency in order to acheive high performance. */ + QSPI_ClockUpdate(EXAMPLE_QSPI); +#endif +#endif + + for (i = 0; i < FLASH_SECTORE_SIZE / 4; i++) + { + if (((uint32_t *)addr)[i] != buff[i % 64]) + { + PRINTF("The data in %d is wrong!!\r\n", i); + PRINTF("The flash value in %d is %d\r\n", i, ((uint32_t *)addr)[i]); + err++; + } + } + if (err == 0) + { + PRINTF("Program through QSPI polling succeed!\r\n"); + } +} + +int main(void) +{ + uint32_t i = 0; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + CLOCK_SetRootMux(kCLOCK_RootQspi, kCLOCK_QspiRootmuxSysPll1Div8); /* Set QSPI source to SYSTEM PLL1 DIV8 100MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootQspi, 1U, 2U); /* Set root clock to 100MHZ / 2 = 50MHZ */ + + /*Enable QSPI clock */ + PRINTF("QSPI example started!\r\n"); + + /* Copy the LUT table */ + memcpy(single_config.lookuptable, lut, sizeof(lut)); + + qspi_nor_flash_init(EXAMPLE_QSPI); + + /*Initialize data buffer */ + for (i = 0; i < 64; i++) + { + buff[i] = i; + } + +#if defined(FLASH_ENABLE_QUAD_CMD) + /* Enable Quad mode for the flash */ + enable_quad_mode(); +#endif + +#if defined(FLASH_ENABLE_OCTAL_CMD) + enable_ddr_mode(); + /* Enable Octal mode for the flash */ + enable_octal_mode(); +#endif + + /* Use polling to program flash. */ + qspi_polling(); + + while (1) + { + } +} diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/qspi_polling_transfer_v3_8.xml b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/qspi_polling_transfer_v3_8.xml new file mode 100644 index 000000000..9e79fd460 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/qspi_polling_transfer_v3_8.xml @@ -0,0 +1,125 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/readme.txt b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/readme.txt new file mode 100644 index 000000000..795c927d4 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/qspi/polling_transfer/readme.txt @@ -0,0 +1,59 @@ +Overview +======== +The qspi_polling example shows how to use qspi driver with polling: + +In this example, qspi will send data and operate the external flash connected with QSPI. Some simple flash command will +be executed, such as Write Enable, Erase sector, Program page. +Example will first erase the sector and programe a page into the flash, at last check if the data in flash is correct. + +Notice: While do program, it is not suggested to make the flash write frequency bigger than the core clock frequency. +In some tool chain's Debug version, this may cause core do not have enough speed to send data to flash. +The flash write frequency equals to QSPI working frequency plus data line number. For example, if QSPI working in 48MHz, +program command uses quad mode, the write frequency is 48MHz * 4 = 192MHz. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special is needed. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. + +~~~~~~~~~~~~~~~~~~~~~ +QSPI example started! + +Erase finished! + +Program data finished! + +Program through QSPI polling succeed! +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/rdc/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/rdc/armgcc/CMakeLists.txt new file mode 100644 index 000000000..362883dc6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/armgcc/CMakeLists.txt @@ -0,0 +1,107 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(rdc) + +set(MCUX_SDK_PROJECT_NAME rdc.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../rdc.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(driver_igpio_MIMX8MQ6) + +include(driver_cache_lmem_MIMX8MQ6) + +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(driver_rdc_sema42_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/rdc.bin) + diff --git a/boards/evkmimx8mq/driver_examples/rdc/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/rdc/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/rdc/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/rdc/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data 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. +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/rdc/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/rdc/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/rdc/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/rdc/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/rdc/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/rdc/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/rdc/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/rdc/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/rdc/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/rdc/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/rdc/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/rdc/armgcc/flags.cmake new file mode 100755 index 000000000..863000f87 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/armgcc/flags.cmake @@ -0,0 +1,374 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + 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-std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -D__SEMIHOST_HARDFAULT_DISABLE=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -D__SEMIHOST_HARDFAULT_DISABLE=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + 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-ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/rdc/board.c b/boards/evkmimx8mq/driver_examples/rdc/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/rdc/board.h b/boards/evkmimx8mq/driver_examples/rdc/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/rdc/clock_config.c b/boards/evkmimx8mq/driver_examples/rdc/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/rdc/clock_config.h b/boards/evkmimx8mq/driver_examples/rdc/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/rdc/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/rdc/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/rdc/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/rdc/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/rdc/pin_mux.c b/boards/evkmimx8mq/driver_examples/rdc/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/rdc/pin_mux.h b/boards/evkmimx8mq/driver_examples/rdc/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/rdc/rdc.c b/boards/evkmimx8mq/driver_examples/rdc/rdc.c new file mode 100644 index 000000000..85907c147 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/rdc.c @@ -0,0 +1,358 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_rdc_sema42.h" + +#include "fsl_gpio.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define APP_RDC RDC +#define APP_CUR_MASTER kRDC_Master_M4 +#define APP_CUR_MASTER_DID BOARD_DOMAIN_ID /* Current master domain ID. */ +#define APP_RDC_PERIPH kRDC_Periph_GPIO1 +#define APP_RDC_SEMA42 RDC_SEMAPHORE1 /* Current master domain ID. */ +#define APP_RDC_SEMA42_GATE (((uint8_t)APP_RDC_PERIPH) & 0x3F) + +/* OCRAM is used for demonstration here. */ +#define APP_RDC_MEM kRDC_Mem_MRC4_0 +#define APP_RDC_MEM_BASE_ADDR 0x900000 +#define APP_RDC_MEM_END_ADDR 0x920000 + +/* + * Master index: + * All masters excluding ARM core: 0 + * A53 core: 1 + * M4 core: 6 + * SDMA 3 + */ +#define APP_MASTER_INDEX 6 + +/* + * If cache is enabled, this example should maintain the cache to make sure + * CPU core accesses the memory, not cache only. + */ +#define APP_USING_CACHE 1 + +typedef enum +{ + kRDC_DEMO_None = 0, + kRDC_DEMO_Periph = 1, + kRDC_DEMO_PeriphSema42 = 2, + kRDC_DEMO_Mem = 3, +} rdc_demo_state_t; + +#define DEMO_CHECK(x) \ + if (!(x)) \ + { \ + PRINTF("Example error\r\n"); \ + for (;;) \ + ; \ + } + +/* For some platforms, the core's domain ID + * is not configured by RDC, for example, it + * is fixed value and not configurable. + * In this case, APP_ASSIGN_DOMAIN_ID_BY_RDC + * could be over-written to 0, and a function + * APP_AssignCoreDomain assigns the core's domain. + */ +#ifndef APP_ASSIGN_DOMAIN_ID_BY_RDC +#define APP_ASSIGN_DOMAIN_ID_BY_RDC 1 +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +void APP_TouchPeriph(void); +void APP_TouchMem(void); +/* + * In this function, sema42 is not required. The peripheral is set inaccessible + * by current domain. When touch the peripheral, hardfault is triggered. In + * hardfault handler, the peripheral is set accessible by current domain. + */ +static void APP_RDC_Periph(void); + +/* + * In this function, sema42 is required. The peripheral is set accessible by + * current domain, before touch the peripheral, the sema42 gate should be locked. + * So in this function, core touch the peripheral before locking the sema42 gate, + * then hardfault happens. In hardfault handler, core locks the sema42, then + * the peripheral is accessible. + */ +static void APP_RDC_PeriphWithSema42(void); + +/* + * In this function, the memory region is set inaccessible by current domain. + * When touch the memory, hardfault is triggered. In hardfault handler, the + * memory region is set accessible by current domain. + */ +static void APP_RDC_Mem(void); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Current demo state. */ +static volatile rdc_demo_state_t s_demoState = kRDC_DEMO_None; +/* HardFault happened or not. */ +static volatile bool s_faultFlag = false; +/* How many error happens during memory region demo. */ +static volatile uint32_t memDemoError = 0; + +rdc_domain_assignment_t assignment; +rdc_periph_access_config_t periphConfig; +rdc_mem_access_config_t memConfig; + +/******************************************************************************* + * Code + ******************************************************************************/ + +void APP_TouchPeriph(void) +{ + GPIO_PinRead(GPIO1, 0); +} + +void APP_TouchMem(void) +{ + /* Touch the memory. */ + (*(volatile uint32_t *)APP_RDC_MEM_BASE_ADDR)++; +} +#if APP_USING_CACHE +#include "fsl_cache.h" +#endif + +static void Fault_Handler(void) +{ + rdc_mem_status_t memStatus; + + s_faultFlag = true; + + if (kRDC_DEMO_Periph == s_demoState) + { + /* Make peripheral accessible. */ + periphConfig.policy |= RDC_ACCESS_POLICY(APP_CUR_MASTER_DID, kRDC_ReadWrite); + RDC_SetPeriphAccessConfig(APP_RDC, &periphConfig); + } + else if (kRDC_DEMO_PeriphSema42 == s_demoState) + { + /* Lock the SEMA42 gate, then the peripheral should be accessible. */ + RDC_SEMA42_Lock(APP_RDC_SEMA42, APP_RDC_SEMA42_GATE, APP_MASTER_INDEX, APP_CUR_MASTER_DID); + } + else if (kRDC_DEMO_Mem == s_demoState) + { + /* Check error status. */ + RDC_GetMemViolationStatus(APP_RDC, APP_RDC_MEM, &memStatus); + + if (false == memStatus.hasViolation) + { + memDemoError++; + } + + if (APP_CUR_MASTER_DID != memStatus.domainID) + { + memDemoError++; + } + + if (APP_RDC_MEM_BASE_ADDR != memStatus.address) + { + memDemoError++; + } + + /* Make memory region accessible. */ + memConfig.policy |= RDC_ACCESS_POLICY(APP_CUR_MASTER_DID, kRDC_ReadWrite); + RDC_SetMemAccessConfig(APP_RDC, &memConfig); + + RDC_ClearMemViolationFlag(APP_RDC, APP_RDC_MEM); + } + __DSB(); +} + +void HardFault_Handler(void) +{ + Fault_Handler(); +} + +void BusFault_Handler(void) +{ + Fault_Handler(); +} + +/*! + * @brief Main function + */ +int main(void) +{ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + /* Init GPIO used for peripheral access demonstration. */ + gpio_pin_config_t pinConfig = { + kGPIO_DigitalOutput, + 0, + kGPIO_IntRisingEdge, + }; + + GPIO_PinInit(GPIO1, 0, &pinConfig); + + /* Set the IOMUXC_GPR10[2:3], thus the memory violation triggers the hardfault. */ + *(volatile uint32_t *)0x30340028 |= (0x0C); + + PRINTF("\r\nRDC Example:\r\n"); + + RDC_Init(APP_RDC); + RDC_SEMA42_Init(APP_RDC_SEMA42); + +#if APP_ASSIGN_DOMAIN_ID_BY_RDC + /* Assign current master domain. */ + RDC_GetDefaultMasterDomainAssignment(&assignment); + assignment.domainId = APP_CUR_MASTER_DID; + RDC_SetMasterDomainAssignment(APP_RDC, APP_CUR_MASTER, &assignment); +#else + APP_AssignCoreDomain(); +#endif + + APP_RDC_Periph(); + + APP_RDC_PeriphWithSema42(); + + APP_RDC_Mem(); + + PRINTF("\r\nRDC Example Success\r\n"); + + while (1) + { + } +} + +static void APP_RDC_Periph(void) +{ + PRINTF("RDC Peripheral access control\r\n"); + + s_demoState = kRDC_DEMO_Periph; + + /* + * Item 1: Peripheral accessible. + */ + RDC_GetDefaultPeriphAccessConfig(&periphConfig); + periphConfig.periph = APP_RDC_PERIPH; + + /* Set peripheral to accessible by all domains. */ + RDC_SetPeriphAccessConfig(APP_RDC, &periphConfig); + + s_faultFlag = false; + + APP_TouchPeriph(); + + /* Peripheral is accessible, there should not be hardfault. */ + DEMO_CHECK(false == s_faultFlag); + + /* + * Item 2: Peripheral inaccessible. + */ + /* Make peripheral not accessible. */ + periphConfig.policy &= ~(RDC_ACCESS_POLICY(APP_CUR_MASTER_DID, kRDC_ReadWrite)); + RDC_SetPeriphAccessConfig(APP_RDC, &periphConfig); + + s_faultFlag = false; + APP_TouchPeriph(); + + /* Peripheral is not accessible, there should be hardfault. */ + DEMO_CHECK(true == s_faultFlag); +} + +static void APP_RDC_PeriphWithSema42(void) +{ + PRINTF("RDC Peripheral access control with SEMA42\r\n"); + + /* Demo the SEMA42 used together with RDC. */ + s_demoState = kRDC_DEMO_PeriphSema42; + + RDC_GetDefaultPeriphAccessConfig(&periphConfig); + periphConfig.periph = APP_RDC_PERIPH; + periphConfig.enableSema = true; + + RDC_SetPeriphAccessConfig(APP_RDC, &periphConfig); + + /* Make sure current core does not hold the SEMA42 gate. */ + RDC_SEMA42_Unlock(APP_RDC_SEMA42, APP_RDC_SEMA42_GATE); + DEMO_CHECK(APP_CUR_MASTER_DID != RDC_SEMA42_GetLockDomainID(APP_RDC_SEMA42, APP_RDC_SEMA42_GATE)); + + s_faultFlag = false; + + APP_TouchPeriph(); + + /* Peripheral is not accessible because SEMA42 gate not locked, there should be hardfault. */ + DEMO_CHECK(true == s_faultFlag); + + /* Demo finished, make the peripheral to default policy. */ + RDC_GetDefaultPeriphAccessConfig(&periphConfig); + + /* Set peripheral to accessible by all domains. */ + RDC_SetPeriphAccessConfig(APP_RDC, &periphConfig); + + RDC_SEMA42_Unlock(APP_RDC_SEMA42, APP_RDC_SEMA42_GATE); +} + +static void APP_RDC_Mem(void) +{ + /* + * In memory protection, please notice the cache's effect. + * For example, if a memory region has been loaded to cache + * before it is set not accessible, then CPU only access the + * cache but not the memory, application could not detect + * access violation. + */ + PRINTF("RDC memory region access control\r\n"); + + s_demoState = kRDC_DEMO_Mem; + + RDC_GetDefaultMemAccessConfig(&memConfig); + + memConfig.mem = APP_RDC_MEM; + memConfig.baseAddress = APP_RDC_MEM_BASE_ADDR; + memConfig.endAddress = APP_RDC_MEM_END_ADDR; + + /* Make memory not accessible. */ + memConfig.policy &= ~(RDC_ACCESS_POLICY(APP_CUR_MASTER_DID, kRDC_ReadWrite)); + + RDC_SetMemAccessConfig(APP_RDC, &memConfig); + +#if APP_USING_CACHE + /* + * Invalidate the cache, so new read will read from memory directly, + * to make sure trigger read error. + */ + DCACHE_InvalidateByRange(APP_RDC_MEM_BASE_ADDR, APP_RDC_MEM_END_ADDR - APP_RDC_MEM_BASE_ADDR); +#endif + + s_faultFlag = false; + + APP_TouchMem(); + +#if APP_USING_CACHE + /* + * Flush the cache, so the modified data is written to memory, + * to make sure trigger write error. + */ + DCACHE_CleanInvalidateByRange(APP_RDC_MEM_BASE_ADDR, APP_RDC_MEM_END_ADDR - APP_RDC_MEM_BASE_ADDR); + __DSB(); +#endif + + /* Memory is not accessible, there should be hardfault. */ + DEMO_CHECK(true == s_faultFlag); + DEMO_CHECK(0 == memDemoError); +} diff --git a/boards/evkmimx8mq/driver_examples/rdc/rdc_v3_8.xml b/boards/evkmimx8mq/driver_examples/rdc/rdc_v3_8.xml new file mode 100644 index 000000000..df65bcddd --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/rdc_v3_8.xml @@ -0,0 +1,124 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/rdc/readme.txt b/boards/evkmimx8mq/driver_examples/rdc/readme.txt new file mode 100644 index 000000000..451743c31 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/rdc/readme.txt @@ -0,0 +1,47 @@ +Overview +======== + +The RDC example shows how to control the peripheral and memory region +asscess policy using RDC and RDC_SEMA42 + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +The log below is shown in the terminal window: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +RDC Example: +RDC Peripheral access control +RDC Peripheral access control with SEMA42 +RDC memory region access control + +RDC Example Success +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..7f9f1ff32 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,116 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(sai_interrupt_transfer) + +set(MCUX_SDK_PROJECT_NAME sai_interrupt_transfer.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../sai_interrupt_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../music.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../components/codec/wm8524 + ${ProjDirPath}/../../../../../../components/codec + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(driver_ii2c_MIMX8MQ6) + +include(driver_wm8524_MIMX8MQ6) + +include(driver_igpio_MIMX8MQ6) + +include(driver_codec_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(component_wm8524_adapter_MIMX8MQ6) + +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_sai_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sai_interrupt_transfer.bin) + diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . 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cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/config.cmake new file mode 100755 index 000000000..ae70e6635 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_wm8524_adapter_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..ae6b871f2 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/armgcc/flags.cmake @@ -0,0 +1,382 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSDK_I2C_BASED_COMPONENT_USED=1 \ + -DBOARD_USE_CODEC=1 \ + -DCODEC_WM8524_ENABLE \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSDK_I2C_BASED_COMPONENT_USED=1 \ + -DBOARD_USE_CODEC=1 \ + -DCODEC_WM8524_ENABLE \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSDK_I2C_BASED_COMPONENT_USED=1 \ + -DBOARD_USE_CODEC=1 \ + -DCODEC_WM8524_ENABLE \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSDK_I2C_BASED_COMPONENT_USED=1 \ + -DBOARD_USE_CODEC=1 \ + -DCODEC_WM8524_ENABLE \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/board.c b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/board.h b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/clock_config.c b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/clock_config.h b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/music.h b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/music.h new file mode 100644 index 000000000..3bcf01f40 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/music.h @@ -0,0 +1,2721 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _MUSIC_H_ +#define _MUSIC_H_ + +#include "fsl_common.h" + +#if defined(__GNUC__) /* GNU Compiler */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__((aligned(4))) +#endif +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#else +#ifndef __ALIGN_END +#define __ALIGN_END +#endif +#ifndef __ALIGN_BEGIN +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) /* ARM Compiler */ +#define __ALIGN_BEGIN __attribute__((aligned(4))) +#elif defined(__ICCARM__) /* IAR Compiler */ +#define __ALIGN_BEGIN +#endif +#endif +#endif + +#if defined(__ICCARM__) +#pragma data_alignment = 4 +#endif +__ALIGN_BEGIN int a __ALIGN_END; + +#define MUSIC_LEN (48000) + +#if defined DEMO_AUDIO_DATA_PUT_INTO_SECTION +DEMO_AUDIO_DATA_PUT_INTO_SECTION(uint8_t music[], 4U) = +#else +#if defined FSL_FEATURE_SOC_MMDC_COUNT && FSL_FEATURE_SOC_MMDC_COUNT +AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint8_t music[], 4) = +#else +__ALIGN_BEGIN const uint8_t music[] __ALIGN_END = +#endif +#endif + { + 0x2F, 0x00, 0x2F, 0x00, 0x93, 0x08, 0x93, 0x08, 0x1D, 0x14, 0x1D, 0x14, 0xA3, 0x1E, 0xA3, 0x1E, 0x77, 0x29, + 0x77, 0x29, 0x96, 0x33, 0x96, 0x33, 0xA6, 0x3D, 0xA6, 0x3D, 0xF9, 0x46, 0xF9, 0x46, 0x01, 0x50, 0x01, 0x50, + 0x3D, 0x58, 0x3D, 0x58, 0xFD, 0x5F, 0xFD, 0x5F, 0xDE, 0x66, 0xDE, 0x66, 0x1E, 0x6D, 0x1E, 0x6D, 0x6E, 0x72, + 0x6E, 0x72, 0xFF, 0x76, 0xFF, 0x76, 0x96, 0x7A, 0x96, 0x7A, 0x56, 0x7D, 0x56, 0x7D, 0x16, 0x7F, 0x16, 0x7F, + 0xF2, 0x7F, 0xF2, 0x7F, 0xCD, 0x7F, 0xCD, 0x7F, 0xBE, 0x7E, 0xBE, 0x7E, 0xB6, 0x7C, 0xB6, 0x7C, 0xC4, 0x79, + 0xC4, 0x79, 0xE7, 0x75, 0xE7, 0x75, 0x2B, 0x71, 0x2B, 0x71, 0x95, 0x6B, 0x95, 0x6B, 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0xF3, 0x1D, 0xE8, 0x1D, 0xE8, 0x5A, 0xDD, 0x5A, 0xDD, 0xD8, 0xD2, 0xD8, 0xD2, 0xAE, 0xC8, 0xAE, 0xC8, + 0xED, 0xBE, 0xED, 0xBE, 0xA9, 0xB5, 0xA9, 0xB5, 0xF1, 0xAC, 0xF1, 0xAC, 0xDA, 0xA4, 0xDA, 0xA4, 0x70, 0x9D, + 0x70, 0x9D, 0xC2, 0x96, 0xC2, 0x96, 0xDD, 0x90, 0xDD, 0x90, 0xCD, 0x8B, 0xCD, 0x8B, 0x9A, 0x87, 0x9A, 0x87, + 0x4D, 0x84, 0x4D, 0x84, 0xEC, 0x81, 0xEC, 0x81, 0x7D, 0x80, 0x7D, 0x80, 0x00, 0x80, 0x00, 0x80, 0x78, 0x80, + 0x78, 0x80, 0xE4, 0x81, 0xE4, 0x81, 0x40, 0x84, 0x40, 0x84, 0x89, 0x87, 0x89, 0x87, 0xB8, 0x8B, 0xB8, 0x8B, + 0xC5, 0x90, 0xC5, 0x90, 0xA6, 0x96, 0xA6, 0x96, 0x51, 0x9D, 0x51, 0x9D, 0xB7, 0xA4, 0xB7, 0xA4, 0xCD, 0xAC, + 0xCD, 0xAC, 0x81, 0xB5, 0x81, 0xB5, 0xC3, 0xBE, 0xC3, 0xBE, 0x82, 0xC8, 0x82, 0xC8, 0xAB, 0xD2, 0xAB, 0xD2, + 0x2B, 0xDD, 0x2B, 0xDD, 0xEC, 0xE7, 0xEC, 0xE7, 0xDD, 0xF2, 0xDD, 0xF2, 0xE5, 0xFD, 0xE5, 0xFD, 0xF1, 0x08, + 0xF1, 0x08, 0xED, 0x13, 0xED, 0x13, 0xC3, 0x1E, 0xC3, 0x1E, 0x5E, 0x29, 0x5E, 0x29, 0xAB, 0x33, 0xAB, 0x33, + 0x94, 0x3D, 0x94, 0x3D, 0x08, 0x47, 0x08, 0x47, +}; + +#endif diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/pin_mux.c b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/pin_mux.c new file mode 100644 index 000000000..4571f26b1 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/pin_mux.c @@ -0,0 +1,97 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: H5, peripheral: SAI2, signal: sai_mclk, pin_signal: SAI2_MCLK, SION: DISABLED, HYS: Enabled, SRE: MEDIUM, DSE: OHM_105} + - {pin_num: J5, peripheral: SAI2, signal: sai_tx_bclk, pin_signal: SAI2_TXC, HYS: Enabled, SRE: MEDIUM, DSE: OHM_105} + - {pin_num: G5, peripheral: SAI2, signal: 'sai_tx_data, 0', pin_signal: SAI2_TXD0, HYS: Enabled, SRE: MEDIUM, DSE: OHM_105} + - {pin_num: H4, peripheral: SAI2, signal: sai_tx_sync, pin_signal: SAI2_TXFS, HYS: Enabled, SRE: MEDIUM, DSE: OHM_105, VSEL: VSEL_0} + - {pin_num: N7, peripheral: GPIO1, signal: 'gpio_io, 08', pin_signal: GPIO1_IO08, SION: ENABLED} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_GPIO1_IO08_GPIO1_IO08, 1U); + IOMUXC_SetPinMux(IOMUXC_SAI2_MCLK_SAI2_MCLK, 0U); + IOMUXC_SetPinConfig(IOMUXC_SAI2_MCLK_SAI2_MCLK, + IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_SAI2_TXC_SAI2_TX_BCLK, 0U); + IOMUXC_SetPinConfig(IOMUXC_SAI2_TXC_SAI2_TX_BCLK, + IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_SAI2_TXD0_SAI2_TX_DATA0, 0U); + IOMUXC_SetPinConfig(IOMUXC_SAI2_TXD0_SAI2_TX_DATA0, + IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_SAI2_TXFS_SAI2_TX_SYNC, 0U); + IOMUXC_SetPinConfig(IOMUXC_SAI2_TXFS_SAI2_TX_SYNC, + IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/pin_mux.h b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/readme.txt b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/readme.txt new file mode 100644 index 000000000..a72ba70c9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/readme.txt @@ -0,0 +1,46 @@ +Overview +======== +The sai_interrupt_transfer example shows how to use sai driver with interrupt: + +In this example, one sai instance playbacks the audio data stored in flash/SRAM using interrupt. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer +- Headphone + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +When the demo runs successfully, you can hear the tone and the log would be seen on the terminal like: + +~~~~~~~~~~~~~~~~~~~ +SAI example started! +SAI example finished! + ~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/sai_interrupt_transfer.c b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/sai_interrupt_transfer.c new file mode 100644 index 000000000..7b5aed97f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/sai_interrupt_transfer.c @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_sai.h" +#include "music.h" +#include "fsl_codec_common.h" + +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_wm8524.h" +#include "fsl_codec_adapter.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_SAI (I2S2) +#define DEMO_SAI_CHANNEL (0) +#define DEMO_SAI_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootSai2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootSai2)) / 6 +#define DEMO_CODEC_WM8524 (1) +#define CODEC_USEGPIO (1) +#define DEMO_CODEC_BUS_PIN (NULL) +#define DEMO_CODEC_BUS_PIN_NUM (0) +#define DEMO_CODEC_MUTE_PIN (GPIO1) +#define DEMO_CODEC_MUTE_PIN_NUM (8) + +#define DEMO_SAI_TX_SYNC_MODE kSAI_ModeAsync +#define DEMO_SAI_RX_SYNC_MODE kSAI_ModeSync +#define DEMO_SAI_MCLK_OUTPUT true +#define DEMO_SAI_MASTER_SLAVE kSAI_Master + +#define DEMO_AUDIO_DATA_CHANNEL (2U) +#define DEMO_AUDIO_BIT_WIDTH kSAI_WordWidth16bits +#define DEMO_AUDIO_SAMPLE_RATE (kSAI_SampleRate16KHz) +#define DEMO_AUDIO_MASTER_CLOCK DEMO_SAI_CLK_FREQ + +#define BOARD_MASTER_CLOCK_CONFIG() +#define BOARD_SAI_RXCONFIG(config, mode) + +#define DEMO_BOARD_CODEC_INIT BOARD_Codec_Init + +#ifndef DEMO_CODEC_INIT_DELAY_MS +#define DEMO_CODEC_INIT_DELAY_MS (1000U) +#endif +#ifndef DEMO_CODEC_VOLUME +#define DEMO_CODEC_VOLUME 100U +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +void BOARD_WM8524_Mute_GPIO(uint32_t output); +void BOARD_Codec_Init(void); +extern void BOARD_SAI_RXConfig(sai_transceiver_t *config, sai_sync_mode_t sync); +/******************************************************************************* + * Variables + ******************************************************************************/ +static wm8524_config_t wm8524Config = { + .setMute = BOARD_WM8524_Mute_GPIO, + .setProtocol = NULL, + .protocol = kWM8524_ProtocolI2S, +}; +codec_config_t boardCodecConfig = {.codecDevType = kCODEC_WM8524, .codecDevConfig = &wm8524Config}; +extern codec_handle_t codecHandle; +sai_handle_t txHandle = {0}; +static volatile bool isFinished = false; +extern codec_config_t boardCodecConfig; +codec_handle_t codecHandle; + +/******************************************************************************* + * Code + ******************************************************************************/ + +void BOARD_WM8524_Mute_GPIO(uint32_t output) +{ + GPIO_PinWrite(DEMO_CODEC_MUTE_PIN, DEMO_CODEC_MUTE_PIN_NUM, output); +} + +void BOARD_Codec_Init(void) +{ + if (CODEC_Init(&codecHandle, &boardCodecConfig) != kStatus_Success) + { + assert(false); + } +} +static void callback(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData) +{ + isFinished = true; +} + +void DelayMS(uint32_t ms) +{ + for (uint32_t i = 0; i < ms; i++) + { + SDK_DelayAtLeastUs(1000, SystemCoreClock); + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + sai_transfer_t xfer; + uint32_t temp = 0; + sai_transceiver_t saiConfig; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + CLOCK_SetRootMux(kCLOCK_RootSai2, kCLOCK_SaiRootmuxSysPll1Div6); /* Set SAI source to SYS PLL1 Div6 133MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootSai2, 1U, 3U); /* Set root clock to 133MHZ / 3 = 44MHZ */ + + /* gpio initialization */ + gpio_pin_config_t gpioConfig = {kGPIO_DigitalOutput, 1}; + GPIO_PinInit(DEMO_CODEC_MUTE_PIN, DEMO_CODEC_MUTE_PIN_NUM, &gpioConfig); + + PRINTF("SAI example started!\n\r"); + + /* SAI init */ + SAI_Init(DEMO_SAI); + SAI_TransferTxCreateHandle(DEMO_SAI, &txHandle, callback, NULL); + /* I2S mode configurations */ + SAI_GetClassicI2SConfig(&saiConfig, DEMO_AUDIO_BIT_WIDTH, kSAI_Stereo, 1U << DEMO_SAI_CHANNEL); + saiConfig.syncMode = DEMO_SAI_TX_SYNC_MODE; + saiConfig.masterSlave = DEMO_SAI_MASTER_SLAVE; + SAI_TransferTxSetConfig(DEMO_SAI, &txHandle, &saiConfig); + + /* set bit clock divider */ + SAI_TxSetBitClockRate(DEMO_SAI, DEMO_AUDIO_MASTER_CLOCK, DEMO_AUDIO_SAMPLE_RATE, DEMO_AUDIO_BIT_WIDTH, + DEMO_AUDIO_DATA_CHANNEL); + /* sai rx configurations */ + BOARD_SAI_RXCONFIG(&saiConfig, DEMO_SAI_RX_SYNC_MODE); + /* master clock configurations */ + BOARD_MASTER_CLOCK_CONFIG(); + +#if defined DEMO_BOARD_CODEC_INIT + DEMO_BOARD_CODEC_INIT(); +#else + if (CODEC_Init(&codecHandle, &boardCodecConfig) != kStatus_Success) + { + assert(false); + } + if (CODEC_SetVolume(&codecHandle, kCODEC_PlayChannelHeadphoneLeft | kCODEC_PlayChannelHeadphoneRight, + DEMO_CODEC_VOLUME) != kStatus_Success) + { + assert(false); + } +#endif + /* delay for codec output stable */ + DelayMS(DEMO_CODEC_INIT_DELAY_MS); + + /* xfer structure */ + temp = (uint32_t)music; + xfer.data = (uint8_t *)temp; + xfer.dataSize = MUSIC_LEN; + SAI_TransferSendNonBlocking(DEMO_SAI, &txHandle, &xfer); + /* Wait until finished */ + while (isFinished != true) + { + } + + PRINTF("\n\r SAI example finished!\n\r "); + while (1) + { + } +} diff --git a/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/sai_interrupt_transfer_v3_8.xml b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/sai_interrupt_transfer_v3_8.xml new file mode 100644 index 000000000..82e189c79 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sai/interrupt_transfer/sai_interrupt_transfer_v3_8.xml @@ -0,0 +1,133 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/CMakeLists.txt new file mode 100644 index 000000000..153366806 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/CMakeLists.txt @@ -0,0 +1,103 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(sema4_uboot) + +set(MCUX_SDK_PROJECT_NAME sema4_uboot.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../sema4_uboot.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_sema4_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sema4_uboot.bin) + diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD 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a/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_ddr_debug.sh @@ -0,0 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b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/board.c b/boards/evkmimx8mq/driver_examples/sema4/uboot/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/board.h b/boards/evkmimx8mq/driver_examples/sema4/uboot/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/clock_config.c b/boards/evkmimx8mq/driver_examples/sema4/uboot/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/clock_config.h b/boards/evkmimx8mq/driver_examples/sema4/uboot/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/sema4/uboot/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/sema4/uboot/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/pin_mux.c b/boards/evkmimx8mq/driver_examples/sema4/uboot/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/pin_mux.h b/boards/evkmimx8mq/driver_examples/sema4/uboot/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/readme.txt b/boards/evkmimx8mq/driver_examples/sema4/uboot/readme.txt new file mode 100644 index 000000000..3b85397c2 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/readme.txt @@ -0,0 +1,50 @@ +Overview +======== +The sema4 uboot example shows how to use SEMA4 driver to lock and unlock a sema gate, +the notification IRQ is also demonstrated in this example. +This example should work together with uboot. This example runs on Cortex-M core, +the uboot runs on the Cortex-A core. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- SD card with uboot +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + +Prepare the Demo +================ +1. Prepare an SD card with the prebuilt U-Boot image. Then, insert the SD card to the target board. +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +4. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +Follow the output log, lock and unlock the sema4 gate in uboot. The whole log: +~~~~~~~~~~~~~~~~~~~ +SEMA4 uboot example start +Lock sema4 gate in uboot using: + > mw.b 0x30ac0000 1 1 +Unlock sema4 gate in uboot using: + > mw.b 0x30ac0000 0 1 +SEMA4 uboot example success +~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/sema4_uboot.c b/boards/evkmimx8mq/driver_examples/sema4/uboot/sema4_uboot.c new file mode 100644 index 000000000..e2772ac26 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/sema4_uboot.c @@ -0,0 +1,117 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_sema4.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define APP_SEMA4 SEMA4 +#define APP_PROC_NUM 1 +#define APP_OTHER_PROC_NUM 0 +#define APP_SEMA4_GATE 0 +#define APP_SEMA4_GATE_ADDR ((uint32_t)(&(APP_SEMA4->Gate00))) +#define SEMA4_IRQHandler HS_CP1_IRQHandler +#define SOC_EnableSEMA4Intterrupt() NVIC_EnableIRQ(HS_CP1_IRQn) +#define SOC_DisableSEMA4Intterrupt() NVIC_DisableIRQ(HS_CP1_IRQn) +#define APP_ASSERT(x) \ + if (!(x)) \ + { \ + PRINTF("Example error\r\n"); \ + for (;;) \ + ; \ + } + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +void SEMA4_IRQHandler(void) +{ + /* If gate notification IRQ received, then lock the gate. */ + if (((1U << APP_SEMA4_GATE) & SEMA4_GetGateNotifyStatus(APP_SEMA4, APP_PROC_NUM))) + { + SEMA4_TryLock(APP_SEMA4, APP_SEMA4_GATE, APP_PROC_NUM); + } + __DSB(); +} + +/*! + * @brief Main function + */ +int main(void) +{ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + PRINTF("SEMA4 uboot example start\r\n"); + + SEMA4_Init(APP_SEMA4); + + SEMA4_EnableGateNotifyInterrupt(APP_SEMA4, APP_PROC_NUM, (1 << APP_SEMA4_GATE)); + + SOC_EnableSEMA4Intterrupt(); + + /* Step 1: The other core lock the sema4 gate. */ + PRINTF("Lock sema4 gate in uboot using:\r\n"); + PRINTF(" > mw.b 0x%08x %d 1 \r\n", APP_SEMA4_GATE_ADDR, APP_OTHER_PROC_NUM + 1); + + /* Wait SEMA4 gate is locked by the other core. */ + while (SEMA4_GetLockProc(APP_SEMA4, APP_SEMA4_GATE) != APP_OTHER_PROC_NUM) + { + } + + /* Step 2: Current core try to lock the sema4 gate and lock failed. */ + APP_ASSERT(kStatus_Fail == SEMA4_TryLock(APP_SEMA4, APP_SEMA4_GATE, APP_PROC_NUM)); + + /* Step 3: The other core unlock the sema4 gate. */ + PRINTF("Unlock sema4 gate in uboot using:\r\n"); + PRINTF(" > mw.b 0x%08x 0 1 \r\n", APP_SEMA4_GATE_ADDR); + + /* Wait SEMA4 gate is locked by the other core. */ + while (SEMA4_GetLockProc(APP_SEMA4, APP_SEMA4_GATE) == APP_OTHER_PROC_NUM) + { + } + + /* + * When the other core unlocked the gate, current core receives the notification + * interrupt and lock the gate in ISR. + */ + APP_ASSERT(SEMA4_GetLockProc(APP_SEMA4, APP_SEMA4_GATE) == APP_PROC_NUM); + + SEMA4_Unlock(APP_SEMA4, APP_SEMA4_GATE); + + SOC_DisableSEMA4Intterrupt(); + + SEMA4_DisableGateNotifyInterrupt(APP_SEMA4, APP_PROC_NUM, (1 << APP_SEMA4_GATE)); + + SEMA4_Deinit(APP_SEMA4); + + PRINTF("SEMA4 uboot example success\r\n"); + + while (1) + { + } +} diff --git a/boards/evkmimx8mq/driver_examples/sema4/uboot/sema4_uboot_v3_8.xml b/boards/evkmimx8mq/driver_examples/sema4/uboot/sema4_uboot_v3_8.xml new file mode 100644 index 000000000..6d6b261f4 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/sema4/uboot/sema4_uboot_v3_8.xml @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/CMakeLists.txt new file mode 100644 index 000000000..a7b7415f7 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/CMakeLists.txt @@ -0,0 +1,103 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(tmu_monitor_report) + +set(MCUX_SDK_PROJECT_NAME tmu_monitor_report.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../tmu_monitor_report.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_tmu_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/tmu_monitor_report.bin) + diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . 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-DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_all.sh b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_all.sh new file mode 100755 index 000000000..86624c4e1 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..373514ef3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c16cafbd5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_debug.bat b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + 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-DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/board.c b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/board.h b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/clock_config.c b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/clock_config.h b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/pin_mux.c b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/pin_mux.h b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/readme.txt b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/readme.txt new file mode 100644 index 000000000..e361a81b1 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/readme.txt @@ -0,0 +1,56 @@ +Overview +======== +The TMU example shows how to configure TMU register to monitor and report the temperature from one or +more remote temperature measurement sites located on the chip. + +TMU has access to multiple temperature measurement sites strategically located on the +chip. It monitors these sites and can signal an alarm if a programmed threshold is ever +exceeded. + +Note: Before monitoring the temperature, we must programming the calibration table. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +The log below shows the output of the hello world demo in the terminal window: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +TMU monitor report example. +site 1 immediate temperature is too high. 41°C +site 1 immediate temperature is too high. 41°C +site 0 immediate temperature is too high. 41°C +site 1 immediate temperature is too high. 42°C +site 0 immediate temperature is too high. 41°C +site 1 immediate temperature is too high. 42°C +... +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/tmu_monitor_report.c b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/tmu_monitor_report.c new file mode 100644 index 000000000..4e09b3bb4 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/tmu_monitor_report.c @@ -0,0 +1,106 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_tmu.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_TMU_BASE TMU +#define DEMO_TMU_IMMEDIATE_THRESOLD 0U +#define DEMO_TMU_INTERVAL_VALUE 8U +#define DEMO_TMU_IRQ TEMPMON_IRQn +#define DEMO_TMU_IRQ_HANDLER_FUNC TEMPMON_IRQHandler + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +volatile tmu_interrupt_status_t g_tmuInterruptStausStruct; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief TMU ISR. + */ +void DEMO_TMU_IRQ_HANDLER_FUNC(void) +{ + uint32_t temp; + + TMU_GetInterruptStatusFlags(DEMO_TMU_BASE, (tmu_interrupt_status_t *)&g_tmuInterruptStausStruct); + TMU_ClearInterruptStatusFlags(DEMO_TMU_BASE, g_tmuInterruptStausStruct.interruptDetectMask); + if (0U != (g_tmuInterruptStausStruct.interruptDetectMask & kTMU_ImmediateTemperatureStatusFlags)) + { + /* For site0. */ + if (0U != (g_tmuInterruptStausStruct.immediateInterruptsSiteMask & kTMU_MonitorSite0)) + { + TMU_GetImmediateTemperature(TMU, 0U, &temp); + PRINTF("site 0 immediate temperature is too high. %d celsius degree\r\n", temp); + } + /* For site1. */ + if (0U != (g_tmuInterruptStausStruct.immediateInterruptsSiteMask & kTMU_MonitorSite1)) + { + TMU_GetImmediateTemperature(TMU, 1U, &temp); + PRINTF("site 1 immediate temperature is too high. %d celsius degree\r\n", temp); + } + } + __DSB(); +} + +/*! + * @brief Main function + */ +int main(void) +{ + tmu_config_t k_tmuConfig; + tmu_thresold_config_t k_tmuThresoldConfig; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + PRINTF("TMU monitor report example.\r\n"); + + /* Initialize the TMU mode. */ + k_tmuConfig.monitorInterval = DEMO_TMU_INTERVAL_VALUE; + k_tmuConfig.monitorSiteSelection = + kTMU_MonitorSite0 | kTMU_MonitorSite1; /* Monitor temperature of site 0 and site 1. */ + k_tmuConfig.averageLPF = kTMU_AverageLowPassFilter1_0; + TMU_Init(DEMO_TMU_BASE, &k_tmuConfig); + + /* Set the temperature threshold. */ + k_tmuThresoldConfig.immediateThresoldEnable = true; + k_tmuThresoldConfig.AverageThresoldEnable = false; + k_tmuThresoldConfig.AverageCriticalThresoldEnable = false; + k_tmuThresoldConfig.immediateThresoldValue = DEMO_TMU_IMMEDIATE_THRESOLD; + k_tmuThresoldConfig.averageThresoldValue = 0U; + k_tmuThresoldConfig.averageCriticalThresoldValue = 0U; + TMU_SetHighTemperatureThresold(DEMO_TMU_BASE, &k_tmuThresoldConfig); + + /* Enable the Immediate temperature threshold exceeded interrupt. */ + TMU_EnableInterrupts(DEMO_TMU_BASE, kTMU_ImmediateTemperatureInterruptEnable); + EnableIRQ(DEMO_TMU_IRQ); + + /* Enable the monitor mode. */ + TMU_Enable(DEMO_TMU_BASE, true); + + while (true) + { + } +} diff --git a/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/tmu_monitor_report_v3_8.xml b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/tmu_monitor_report_v3_8.xml new file mode 100644 index 000000000..33c211a5e --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/tmu/tmu_monitor_report/tmu_monitor_report_v3_8.xml @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/CMakeLists.txt new file mode 100644 index 000000000..669bdf9ec --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/CMakeLists.txt @@ -0,0 +1,101 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(iuart_auto_baudrate_detect) + +set(MCUX_SDK_PROJECT_NAME iuart_auto_baudrate_detect.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../uart_auto_baudrate_detect.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/iuart_auto_baudrate_detect.bin) + diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake 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fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..373514ef3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c16cafbd5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_debug.bat b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/board.c b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/board.h b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/clock_config.c b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/clock_config.h b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/iuart_auto_baudrate_detect_v3_8.xml b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/iuart_auto_baudrate_detect_v3_8.xml new file mode 100644 index 000000000..984583a8e --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/iuart_auto_baudrate_detect_v3_8.xml @@ -0,0 +1,120 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/pin_mux.c b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/pin_mux.h b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/readme.txt b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/readme.txt new file mode 100644 index 000000000..ef816b91b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/readme.txt @@ -0,0 +1,51 @@ +Overview +======== +The uart_auto_baudrate_detect example shows how to use uart auto baud rate detect feature: + +In this example, one uart instance connect to PC through uart. First, we should send characters a or A to board. +The boars will set baud rate automatic. After baud rate has set, the board will send back all characters that PC +send to the board. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + + +Running the demo +================ +Set any baud rate in your terminal, and send character a or A to board, then +When the demo runs successfully, the log would be seen on the debug terminal like: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +UART has detect one character A +Baud rate has been set automatic! +Board will send back received characters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/uart_auto_baudrate_detect.c b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/uart_auto_baudrate_detect.c new file mode 100644 index 000000000..5067b646f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/auto_baudrate_detect/uart_auto_baudrate_detect.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_UART UART2 +#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ +#define DEMO_UART_BAUDRATE 115200U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +uint8_t infobuff[] = "UART has detected one character "; +uint8_t txbuff[] = "\r\nBaud rate has been set automatic!\r\nBoard will send back received characters\r\n"; +uint8_t rxbuff[20] = {0}; + +uint8_t fbuffer[] = ""; +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + uint8_t ch; + status_t status; + + uart_config_t config; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitMemory(); + + /* + * config.baudRate_Bps = 115200U; + * config.parityMode = kUART_ParityDisabled; + * config.stopBitCount = kUART_OneStopBit; + * config.txFifoWatermark = 2; + * config.rxFifoWatermark = 1; + * config.enableTx = false; + * config.enableRx = false; + */ + UART_GetDefaultConfig(&config); + config.baudRate_Bps = 0U; + + config.enableTx = true; + config.enableRx = true; + + status = UART_Init(DEMO_UART, &config, DEMO_UART_CLK_FREQ); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + UART_EnableAutoBaudRate(DEMO_UART, true); + + while (!UART_IsAutoBaudRateComplete(DEMO_UART)) + { + } + UART_WriteBlocking(DEMO_UART, infobuff, sizeof(infobuff) - 1); + /* Read the detect character from recevier register */ + UART_ReadBlocking(DEMO_UART, &ch, 1); + UART_WriteBlocking(DEMO_UART, &ch, 1); + + UART_WriteBlocking(DEMO_UART, txbuff, sizeof(txbuff) - 1); + + while (1) + { + UART_ReadBlocking(DEMO_UART, &ch, 1); + UART_WriteBlocking(DEMO_UART, &ch, 1); + } +} diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/CMakeLists.txt new file mode 100644 index 000000000..d435ec8f4 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/CMakeLists.txt @@ -0,0 +1,101 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(iuart_interrupt) + +set(MCUX_SDK_PROJECT_NAME iuart_interrupt.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../uart_interrupt.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/iuart_interrupt.bin) + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist 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-DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_all.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_all.sh new file mode 100755 index 000000000..86624c4e1 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..373514ef3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c16cafbd5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_debug.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + 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-Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/board.c b/boards/evkmimx8mq/driver_examples/uart/interrupt/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/board.h b/boards/evkmimx8mq/driver_examples/uart/interrupt/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/clock_config.c b/boards/evkmimx8mq/driver_examples/uart/interrupt/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/clock_config.h b/boards/evkmimx8mq/driver_examples/uart/interrupt/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/uart/interrupt/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/uart/interrupt/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/iuart_interrupt_v3_8.xml b/boards/evkmimx8mq/driver_examples/uart/interrupt/iuart_interrupt_v3_8.xml new file mode 100644 index 000000000..36f375ebd --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/iuart_interrupt_v3_8.xml @@ -0,0 +1,120 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/pin_mux.c b/boards/evkmimx8mq/driver_examples/uart/interrupt/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/pin_mux.h b/boards/evkmimx8mq/driver_examples/uart/interrupt/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/readme.txt b/boards/evkmimx8mq/driver_examples/uart/interrupt/readme.txt new file mode 100644 index 000000000..ff40bcd0c --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/readme.txt @@ -0,0 +1,50 @@ +Overview +======== +The uart_functioncal_interrupt example shows how to use uart driver functional +API to receive data with interrupt method: + +In this example, one uart instance connect to PC through uart, the board will +send back all characters that PC send to the board. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + + +Running the demo +================ +When the demo runs successfully, the log would be seen on the debug terminal like: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Uart functional interrupt example +Board receives characters then sends them out +Now please input: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt/uart_interrupt.c b/boards/evkmimx8mq/driver_examples/uart/interrupt/uart_interrupt.c new file mode 100644 index 000000000..1208e0e8a --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt/uart_interrupt.c @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_UART UART2 +#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ +#define DEMO_UART_BAUDRATE 115200U +#define DEMO_IRQn UART2_IRQn +#define DEMO_UART_IRQHandler UART2_IRQHandler + +/*! @brief Ring buffer size (Unit: Byte). */ +#define DEMO_RING_BUFFER_SIZE 16 + +/*! @brief Ring buffer to save received data. */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint8_t g_tipString[] = + "Uart functional API interrupt example\r\nBoard receives characters then sends them out\r\nNow please input:\r\n"; + +/* + Ring buffer for data input and output, in this example, input data are saved + to ring buffer in IRQ handler. The main function polls the ring buffer status, + if there are new data, then send them out. + Ring buffer full: (((rxIndex + 1) % DEMO_RING_BUFFER_SIZE) == txIndex) + Ring buffer empty: (rxIndex == txIndex) +*/ +uint8_t demoRingBuffer[DEMO_RING_BUFFER_SIZE]; +volatile uint16_t txIndex; /* Index of the data to send out. */ +volatile uint16_t rxIndex; /* Index of the memory to save new arrived data. */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +void DEMO_UART_IRQHandler(void) +{ + uint8_t data; + + /* If new data arrived. */ + if ((UART_GetStatusFlag(DEMO_UART, kUART_RxDataReadyFlag)) || (UART_GetStatusFlag(DEMO_UART, kUART_RxOverrunFlag))) + { + data = UART_ReadByte(DEMO_UART); + + /* If ring buffer is not full, add data to ring buffer. */ + if (((rxIndex + 1) % DEMO_RING_BUFFER_SIZE) != txIndex) + { + demoRingBuffer[rxIndex] = data; + rxIndex++; + rxIndex %= DEMO_RING_BUFFER_SIZE; + } + } + SDK_ISR_EXIT_BARRIER; +} + +/*! + * @brief Main function + */ +int main(void) +{ + status_t status; + uart_config_t config; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitMemory(); + + /* + * config.baudRate_Bps = 115200U; + * config.parityMode = kUART_ParityDisabled; + * config.dataBitsCount = kUART_EightDataBits; + * config.stopBitCount = kUART_OneStopBit; + * config.txFifoWatermark = 2; + * config.rxFifoWatermark = 1; + * config.enableTx = false; + * config.enableRx = false; + */ + UART_GetDefaultConfig(&config); + config.baudRate_Bps = DEMO_UART_BAUDRATE; + config.enableTx = true; + config.enableRx = true; + + status = UART_Init(DEMO_UART, &config, DEMO_UART_CLK_FREQ); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + /* Send g_tipString out. */ + UART_WriteBlocking(DEMO_UART, g_tipString, sizeof(g_tipString) / sizeof(g_tipString[0]) - 1); + + /* Enable RX interrupt. */ + UART_EnableInterrupts(DEMO_UART, kUART_RxDataReadyEnable | kUART_RxOverrunEnable); + EnableIRQ(DEMO_IRQn); + + while (1) + { + /* Send data only when UART TX register is empty and ring buffer has data to send out. */ + while ((UART_GetStatusFlag(DEMO_UART, kUART_TxReadyFlag)) && (rxIndex != txIndex)) + { + UART_WriteByte(DEMO_UART, demoRingBuffer[txIndex]); + txIndex++; + txIndex %= DEMO_RING_BUFFER_SIZE; + } + } +} diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..6c2b942bb --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,101 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(iuart_interrupt_rb_transfer) + +set(MCUX_SDK_PROJECT_NAME iuart_interrupt_rb_transfer.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../uart_interrupt_rb_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/iuart_interrupt_rb_transfer.bin) + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug 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-DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_all.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_all.sh new file mode 100755 index 000000000..86624c4e1 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..373514ef3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c16cafbd5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_debug.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + 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-ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/board.c b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/board.h b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/clock_config.c b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/clock_config.h b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/iuart_interrupt_rb_transfer_v3_8.xml b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/iuart_interrupt_rb_transfer_v3_8.xml new file mode 100644 index 000000000..9bbc90ef4 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/iuart_interrupt_rb_transfer_v3_8.xml @@ -0,0 +1,120 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/pin_mux.c b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/pin_mux.h b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/readme.txt b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/readme.txt new file mode 100644 index 000000000..a4ef43143 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/readme.txt @@ -0,0 +1,52 @@ +Overview +======== +The uart_interrupt_ring_buffer example shows how to use uart driver in interrupt way with +RX ring buffer enabled: + +In this example, one uart instance connect to PC through uart, the board will +send back all characters that PC send to the board. + +Note: The example echo every 8 characters, so input 8 characters every time. + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. +Running the demo +================ +When the demo runs successfully, the log would be seen on the debug terminal like: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +UART RX ring buffer example +Send back received data +Echo every 8 bytes +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/uart_interrupt_rb_transfer.c b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/uart_interrupt_rb_transfer.c new file mode 100644 index 000000000..67166bafa --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_rb_transfer/uart_interrupt_rb_transfer.c @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_UART UART2 +#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ +#define DEMO_UART_BAUDRATE 115200U + +#define RX_RING_BUFFER_SIZE 20U +#define ECHO_BUFFER_SIZE 8U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/* UART user callback */ +void UART_UserCallback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData); + +/******************************************************************************* + * Variables + ******************************************************************************/ +uart_handle_t g_uartHandle; +uint8_t g_tipString[] = "UART RX ring buffer example\r\nSend back received data\r\nEcho every 8 bytes\r\n"; +uint8_t g_rxRingBuffer[RX_RING_BUFFER_SIZE] = {0}; /* RX ring buffer. */ + +uint8_t g_rxBuffer[ECHO_BUFFER_SIZE] = {0}; /* Buffer for receive data to echo. */ +uint8_t g_txBuffer[ECHO_BUFFER_SIZE] = {0}; /* Buffer for send data to echo. */ +volatile bool rxBufferEmpty = true; +volatile bool txBufferFull = false; +volatile bool txOnGoing = false; +volatile bool rxOnGoing = false; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* UART user callback */ +void UART_UserCallback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData) +{ + userData = userData; + + if (kStatus_UART_TxIdle == status) + { + txBufferFull = false; + txOnGoing = false; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + uart_config_t config; + uart_transfer_t xfer; + uart_transfer_t sendXfer; + uart_transfer_t receiveXfer; + size_t receivedBytes; + uint32_t i; + status_t status; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitMemory(); + + /* + * config.baudRate_Bps = 115200U; + * config.parityMode = kUART_ParityDisabled; + * config.dataBitsCount = kUART_EightDataBits; + * config.stopBitCount = kUART_OneStopBit; + * config.txFifoWatermark = 2; + * config.rxFifoWatermark = 16; + * config.enableTx = false; + * config.enableRx = false; + */ + UART_GetDefaultConfig(&config); + config.baudRate_Bps = DEMO_UART_BAUDRATE; + config.txFifoWatermark = 2; + config.rxFifoWatermark = 16; + config.enableTx = true; + config.enableRx = true; + + status = UART_Init(DEMO_UART, &config, DEMO_UART_CLK_FREQ); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + UART_TransferCreateHandle(DEMO_UART, &g_uartHandle, UART_UserCallback, NULL); + UART_TransferStartRingBuffer(DEMO_UART, &g_uartHandle, g_rxRingBuffer, RX_RING_BUFFER_SIZE); + + /* Send g_tipString out. */ + xfer.data = g_tipString; + xfer.dataSize = sizeof(g_tipString) - 1; + txOnGoing = true; + UART_TransferSendNonBlocking(DEMO_UART, &g_uartHandle, &xfer); + + /* Wait send finished */ + while (txOnGoing) + { + } + + /* Start to echo. */ + sendXfer.data = g_txBuffer; + sendXfer.dataSize = ECHO_BUFFER_SIZE; + receiveXfer.data = g_rxBuffer; + receiveXfer.dataSize = ECHO_BUFFER_SIZE; + + while (1) + { + /* If g_txBuffer is empty and g_rxBuffer is full, copy g_rxBuffer to g_txBuffer. */ + if ((!rxBufferEmpty) && (!txBufferFull)) + { + memcpy(g_txBuffer, g_rxBuffer, ECHO_BUFFER_SIZE); + rxBufferEmpty = true; + txBufferFull = true; + } + + /* If the data in ring buffer reach ECHO_BUFFER_SIZE, then start to read data from ring buffer. */ + if (ECHO_BUFFER_SIZE <= UART_TransferGetRxRingBufferLength(&g_uartHandle)) + { + UART_TransferReceiveNonBlocking(DEMO_UART, &g_uartHandle, &receiveXfer, &receivedBytes); + rxBufferEmpty = false; + } + + /* If TX is idle and g_txBuffer is full, start to send data. */ + if ((!txOnGoing) && txBufferFull) + { + txOnGoing = true; + UART_TransferSendNonBlocking(DEMO_UART, &g_uartHandle, &sendXfer); + } + + /* Delay some time, simulate the app is processing other things, input data save to ring buffer. */ + i = 0x10U; + while (i--) + { + __NOP(); + } + } +} diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..5578f8386 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,101 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(iuart_interrupt_transfer) + +set(MCUX_SDK_PROJECT_NAME iuart_interrupt_transfer.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../uart_interrupt_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/iuart_interrupt_transfer.bin) + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_all.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_all.sh new file mode 100755 index 000000000..86624c4e1 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..373514ef3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c16cafbd5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_debug.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/board.c b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/board.h b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/clock_config.c b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/clock_config.h b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/iuart_interrupt_transfer_v3_8.xml b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/iuart_interrupt_transfer_v3_8.xml new file mode 100644 index 000000000..e4535b9dc --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/iuart_interrupt_transfer_v3_8.xml @@ -0,0 +1,120 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/pin_mux.c b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/pin_mux.h b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/readme.txt b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/readme.txt new file mode 100644 index 000000000..dba51785c --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/readme.txt @@ -0,0 +1,51 @@ +Overview +======== +The uart_interrupt example shows how to use uart driver in interrupt way: + +In this example, one uart instance connect to PC through uart, the board will +send back all characters that PC send to the board. + +Note: The example echo every 8 characters, so input 8 characters every time. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + + +Running the demo +================ +When the demo runs successfully, the log would be seen on the debug terminal like: + +Uart interrupt example +Board receives 8 characters then sends them out +Now please input: + + diff --git a/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/uart_interrupt_transfer.c b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/uart_interrupt_transfer.c new file mode 100644 index 000000000..a00664dbc --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/interrupt_transfer/uart_interrupt_transfer.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_UART UART2 +#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ + +#define ECHO_BUFFER_LENGTH 8 + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/* UART user callback */ +void UART_UserCallback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData); + +/******************************************************************************* + * Variables + ******************************************************************************/ +uart_handle_t g_uartHandle; + +uint8_t g_tipString[] = + "Uart interrupt transfer example\r\nBoard receives 8 characters then sends them out\r\nNow please input:\r\n"; + +uint8_t g_txBuffer[ECHO_BUFFER_LENGTH] = {0}; +uint8_t g_rxBuffer[ECHO_BUFFER_LENGTH] = {0}; +volatile bool rxBufferEmpty = true; +volatile bool txBufferFull = false; +volatile bool txOnGoing = false; +volatile bool rxOnGoing = false; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* UART user callback */ +void UART_UserCallback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData) +{ + userData = userData; + + if (kStatus_UART_TxIdle == status) + { + txBufferFull = false; + txOnGoing = false; + } + + if (kStatus_UART_RxIdle == status) + { + rxBufferEmpty = false; + rxOnGoing = false; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + status_t status; + uart_config_t config; + uart_transfer_t xfer; + uart_transfer_t sendXfer; + uart_transfer_t receiveXfer; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitMemory(); + /* + * config.baudRate_Bps = 115200U; + * config.parityMode = kUART_ParityDisabled; + * config.dataBitsCount = kUART_EightDataBits; + * config.stopBitCount = kUART_OneStopBit; + * config.txFifoWatermark = 2; + * config.rxFifoWatermark = 16; + * config.enableTx = false; + * config.enableRx = false; + */ + UART_GetDefaultConfig(&config); + config.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE; + config.rxFifoWatermark = 16; + config.enableTx = true; + config.enableRx = true; + + status = UART_Init(DEMO_UART, &config, DEMO_UART_CLK_FREQ); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + UART_TransferCreateHandle(DEMO_UART, &g_uartHandle, UART_UserCallback, NULL); + + /* Send g_tipString out. */ + xfer.data = g_tipString; + xfer.dataSize = sizeof(g_tipString) - 1; + txOnGoing = true; + UART_TransferSendNonBlocking(DEMO_UART, &g_uartHandle, &xfer); + + /* Wait send finished */ + while (txOnGoing) + { + } + + /* Start to echo. */ + sendXfer.data = g_txBuffer; + sendXfer.dataSize = ECHO_BUFFER_LENGTH; + receiveXfer.data = g_rxBuffer; + receiveXfer.dataSize = ECHO_BUFFER_LENGTH; + + while (1) + { + /* If RX is idle and g_rxBuffer is empty, start to read data to g_rxBuffer. */ + if ((!rxOnGoing) && rxBufferEmpty) + { + rxOnGoing = true; + UART_TransferReceiveNonBlocking(DEMO_UART, &g_uartHandle, &receiveXfer, NULL); + } + + /* If TX is idle and g_txBuffer is full, start to send data. */ + if ((!txOnGoing) && txBufferFull) + { + txOnGoing = true; + UART_TransferSendNonBlocking(DEMO_UART, &g_uartHandle, &sendXfer); + } + + /* If g_txBuffer is empty and g_rxBuffer is full, copy g_rxBuffer to g_txBuffer. */ + if ((!rxBufferEmpty) && (!txBufferFull)) + { + memcpy(g_txBuffer, g_rxBuffer, ECHO_BUFFER_LENGTH); + rxBufferEmpty = true; + txBufferFull = true; + } + } +} diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/CMakeLists.txt new file mode 100644 index 000000000..b9d120b43 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/CMakeLists.txt @@ -0,0 +1,101 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(iuart_polling) + +set(MCUX_SDK_PROJECT_NAME iuart_polling.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../uart_polling.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/iuart_polling.bin) + diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_all.sh b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_all.sh new file mode 100755 index 000000000..86624c4e1 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..373514ef3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c16cafbd5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_debug.bat b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_debug.sh b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_release.bat b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_release.sh b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + 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-fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/board.c b/boards/evkmimx8mq/driver_examples/uart/polling/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/board.h b/boards/evkmimx8mq/driver_examples/uart/polling/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/clock_config.c b/boards/evkmimx8mq/driver_examples/uart/polling/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/clock_config.h b/boards/evkmimx8mq/driver_examples/uart/polling/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/uart/polling/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/uart/polling/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/iuart_polling_v3_8.xml b/boards/evkmimx8mq/driver_examples/uart/polling/iuart_polling_v3_8.xml new file mode 100644 index 000000000..28f565063 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/iuart_polling_v3_8.xml @@ -0,0 +1,120 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/pin_mux.c b/boards/evkmimx8mq/driver_examples/uart/polling/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/pin_mux.h b/boards/evkmimx8mq/driver_examples/uart/polling/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/readme.txt b/boards/evkmimx8mq/driver_examples/uart/polling/readme.txt new file mode 100644 index 000000000..198586dab --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/readme.txt @@ -0,0 +1,48 @@ +Overview +======== +The uart_polling example shows how to use uart driver in polling way: + +In this example, one uart instance connect to PC through uart, the board will send back all characters that PC +send to the board. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + + +Running the demo +================ +When the demo runs successfully, the log would be seen on the debug terminal like: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Uart polling example +Board will send back received characters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/uart/polling/uart_polling.c b/boards/evkmimx8mq/driver_examples/uart/polling/uart_polling.c new file mode 100644 index 000000000..b88701afc --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/uart/polling/uart_polling.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_UART UART2 +#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ +#define DEMO_UART_BAUDRATE 115200U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint8_t txbuff[] = "Uart polling example\r\nBoard will send back received characters\r\n"; +uint8_t rxbuff[20] = {0}; +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + uint8_t ch; + status_t status; + uart_config_t config; + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitMemory(); + + /* + * config.baudRate_Bps = 115200U; + * config.parityMode = kUART_ParityDisabled; + * config.dataBitsCount = kUART_EightDataBits; + * config.stopBitCount = kUART_OneStopBit; + * config.txFifoWatermark = 2; + * config.rxFifoWatermark = 1; + * config.enableTx = false; + * config.enableRx = false; + */ + UART_GetDefaultConfig(&config); + config.baudRate_Bps = DEMO_UART_BAUDRATE; + config.enableTx = true; + config.enableRx = true; + + status = UART_Init(DEMO_UART, &config, DEMO_UART_CLK_FREQ); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + UART_WriteBlocking(DEMO_UART, txbuff, sizeof(txbuff) - 1); + + while (1) + { + UART_ReadBlocking(DEMO_UART, &ch, 1); + UART_WriteBlocking(DEMO_UART, &ch, 1); + } +} diff --git a/boards/evkmimx8mq/driver_examples/wdog/armgcc/CMakeLists.txt b/boards/evkmimx8mq/driver_examples/wdog/armgcc/CMakeLists.txt new file mode 100644 index 000000000..497c583f5 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/armgcc/CMakeLists.txt @@ -0,0 +1,103 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(wdog01) + +set(MCUX_SDK_PROJECT_NAME wdog01.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../wdog.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities/debug_console_lite + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities +) + +# include modules +include(utility_debug_console_lite_MIMX8MQ6) + +include(utility_assert_lite_MIMX8MQ6) + +include(driver_wdog01_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/wdog01.bin) + diff --git a/boards/evkmimx8mq/driver_examples/wdog/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/driver_examples/wdog/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/wdog/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/driver_examples/wdog/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/driver_examples/wdog/armgcc/build_all.bat b/boards/evkmimx8mq/driver_examples/wdog/armgcc/build_all.bat new file mode 100644 index 000000000..0cf4090ae --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if 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b/boards/evkmimx8mq/driver_examples/wdog/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/driver_examples/wdog/armgcc/clean.bat b/boards/evkmimx8mq/driver_examples/wdog/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/driver_examples/wdog/armgcc/clean.sh b/boards/evkmimx8mq/driver_examples/wdog/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/driver_examples/wdog/armgcc/config.cmake b/boards/evkmimx8mq/driver_examples/wdog/armgcc/config.cmake new file mode 100755 index 000000000..bc8024e2f --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/driver_examples/wdog/armgcc/flags.cmake b/boards/evkmimx8mq/driver_examples/wdog/armgcc/flags.cmake new file mode 100755 index 000000000..3491dd091 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/armgcc/flags.cmake @@ -0,0 +1,370 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + 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-fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/driver_examples/wdog/board.c b/boards/evkmimx8mq/driver_examples/wdog/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/driver_examples/wdog/board.h b/boards/evkmimx8mq/driver_examples/wdog/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/wdog/clock_config.c b/boards/evkmimx8mq/driver_examples/wdog/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/driver_examples/wdog/clock_config.h b/boards/evkmimx8mq/driver_examples/wdog/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/wdog/empty_rsc_table.c b/boards/evkmimx8mq/driver_examples/wdog/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/driver_examples/wdog/fsl_iomuxc.h b/boards/evkmimx8mq/driver_examples/wdog/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/driver_examples/wdog/pin_mux.c b/boards/evkmimx8mq/driver_examples/wdog/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/wdog/pin_mux.h b/boards/evkmimx8mq/driver_examples/wdog/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/driver_examples/wdog/readme.txt b/boards/evkmimx8mq/driver_examples/wdog/readme.txt new file mode 100644 index 000000000..9dae2de9c --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/readme.txt @@ -0,0 +1,57 @@ +Overview +======== +The WDOG Example project is to demonstrate usage of the KSDK wdog driver. +In this example,implemented to test the wdog. +Please notice that because WDOG control registers are write-once only. And +for the field WDT, once software performs a write "1" operation to this bit, +it can not be reset/cleared until the next POR, this bit does not get reset/ +cleared due to any system reset. So the WDOG_Init function can be called +only once after power reset when WDT set, and the WDOG_Disable function can +be called only once after reset. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special is needed. + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +The log below shows the output of this demo in the terminal window: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +******** System Start ******** +System reset by: Power On Reset! + +- 3.Test the WDOG refresh function by using interrupt. +--- wdog Init done--- + +WDOG has be refreshed! +WDOG has be refreshed! +WDOG has be refreshed! + +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/driver_examples/wdog/wdog.c b/boards/evkmimx8mq/driver_examples/wdog/wdog.c new file mode 100644 index 000000000..9e76302be --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/wdog.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +#include "fsl_wdog.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_WDOG_BASE WDOG3 +#define DEMO_WDOG_IRQHandler WDOG3_IRQHandler +#define EXAMPLE_DISABLE_WDOG_RESET_FUNCTION 1 + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void DEMO_WDOG_IRQHandler(void) +{ + WDOG_ClearInterruptStatus(DEMO_WDOG_BASE, kWDOG_InterruptFlag); + /* User code. User can do urgent case before timeout reset. + * IE. user can backup the ram data or ram log to flash. + * the period is set by config.interruptTimeValue, user need to + * check the period between interrupt and timeout. + */ +} + +void delay(uint32_t u32Timeout) +{ + while (u32Timeout-- > 0U) + { + __NOP(); + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint16_t resetFlag = 0U; + wdog_config_t config; + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + PRINTF("\r\n******** System Start ********\r\n"); + PRINTF("System reset by:"); + + resetFlag = WDOG_GetStatusFlags(DEMO_WDOG_BASE); + + switch (resetFlag & (kWDOG_PowerOnResetFlag | kWDOG_TimeoutResetFlag | kWDOG_SoftwareResetFlag)) + { + case kWDOG_PowerOnResetFlag: + PRINTF(" Power On Reset!\r\n"); + break; + case kWDOG_TimeoutResetFlag: + PRINTF(" Time Out Reset!\r\n"); + break; + case kWDOG_SoftwareResetFlag: + PRINTF(" Software Reset!\r\n"); + break; + default: + PRINTF(" Error status!\r\n"); + break; + } +/* Disable wdog reset function test for some devices can't using this feature. */ +#if (!(defined(EXAMPLE_DISABLE_WDOG_RESET_FUNCTION) && EXAMPLE_DISABLE_WDOG_RESET_FUNCTION)) + /* If system reset from power on, trigger a software reset. */ + if (resetFlag & kWDOG_PowerOnResetFlag) + { + PRINTF("\r\n- 1.Testing System reset by software trigger... "); + WDOG_TriggerSystemSoftwareReset(DEMO_WDOG_BASE); + } + + /* If system reset from software trigger, testing the timeout reset. */ + if (resetFlag & kWDOG_SoftwareResetFlag) + { + PRINTF("\r\n- 2.Testing system reset by WDOG timeout.\r\n"); + /* + * wdogConfig->enableWdog = true; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enablePowerdown = false; + * wdogConfig->resetExtension = flase; + * wdogConfig->timeoutValue = 0xFFU; + * wdogConfig->interruptTimeValue = 0x04u; + */ + WDOG_GetDefaultConfig(&config); + config.timeoutValue = 0xFU; /* Timeout value is (0xF + 1)/2 = 8 sec. */ + WDOG_Init(DEMO_WDOG_BASE, &config); + PRINTF("--- wdog Init done---\r\n"); + + /* without feed watch dog, wait until timeout. */ + while (1) + { + } + } + + /* If system reset from WDOG timeout, testing the refresh function using interrupt. */ + if (resetFlag & kWDOG_TimeoutResetFlag) + { +#endif + PRINTF("\r\n- 3.Test the WDOG refresh function by using interrupt.\r\n"); + /* + * wdogConfig->enableWdog = true; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enablePowerdown = false; + * wdogConfig->resetExtension = flase; + * wdogConfig->timeoutValue = 0xFFU; + * wdogConfig->interruptTimeValue = 0x04u; + */ + WDOG_GetDefaultConfig(&config); + config.timeoutValue = 0xFU; /* Timeout value is (0xF+1)/2 = 8 sec. */ + config.enableInterrupt = true; + config.interruptTimeValue = 0x4U; /* Interrupt occurred (0x4)/2 = 2 sec before WDOG timeout. */ + WDOG_Init(DEMO_WDOG_BASE, &config); + + PRINTF("--- wdog Init done---\r\n"); + +#if (!(defined(EXAMPLE_DISABLE_WDOG_RESET_FUNCTION) && EXAMPLE_DISABLE_WDOG_RESET_FUNCTION)) + } +#endif + + while (1) + { + /* User can feed WDG in their main thread. */ + WDOG_Refresh(DEMO_WDOG_BASE); + PRINTF(" \r\nWDOG has be refreshed!"); + + /* Delay. */ + delay(SystemCoreClock); + } +} diff --git a/boards/evkmimx8mq/driver_examples/wdog/wdog01_v3_8.xml b/boards/evkmimx8mq/driver_examples/wdog/wdog01_v3_8.xml new file mode 100644 index 000000000..4578df277 --- /dev/null +++ b/boards/evkmimx8mq/driver_examples/wdog/wdog01_v3_8.xml @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/evkmimx8mq.png b/boards/evkmimx8mq/evkmimx8mq.png new file mode 100644 index 000000000..26817c8e2 Binary files /dev/null and b/boards/evkmimx8mq/evkmimx8mq.png differ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/FreeRTOSConfig.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/FreeRTOSConfig.h new file mode 100644 index 000000000..7c02c13be --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/FreeRTOSConfig.h @@ -0,0 +1,161 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 10 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY 2 +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +#define configASSERT_BOOL(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} +#define configASSERT(x) configASSERT_BOOL((x)!=0) + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#endif +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/CMakeLists.txt b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/CMakeLists.txt new file mode 100644 index 000000000..c9655dd78 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/CMakeLists.txt @@ -0,0 +1,123 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(rpmsg_lite_pingpong_rtos_linux_remote) + +set(MCUX_SDK_PROJECT_NAME rpmsg_lite_pingpong_rtos_linux_remote.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../main_remote.c" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../rpmsg_config.h" +"${ProjDirPath}/../rsc_table.c" +"${ProjDirPath}/../rsc_table.h" +"${ProjDirPath}/../remoteproc.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../middleware/multicore + ${ProjDirPath}/../../../../../../rtos/freertos + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/serial_manager + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include +) + +# include modules +include(middleware_multicore_rpmsg_lite_imx8mq_m4_freertos_MIMX8MQ6) + +include(middleware_freertos-kernel_heap_4_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_mu_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(utility_debug_console_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_serial_manager_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(component_serial_manager_uart_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(utility_assert_MIMX8MQ6) + +include(middleware_multicore_rpmsg_lite_MIMX8MQ6) + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/rpmsg_lite_pingpong_rtos_linux_remote.bin) + diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..7cd2c1827 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..f59eebb35 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.bat b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G 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/F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.sh b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.bat b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.sh b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.bat b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.sh b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/config.cmake b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/config.cmake new file mode 100755 index 000000000..6a7f992aa --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/config.cmake @@ -0,0 +1,4 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) +set(CONFIG_USE_middleware_freertos-kernel_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/flags.cmake b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/flags.cmake new file mode 100755 index 000000000..3a0932ebf --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/flags.cmake @@ -0,0 +1,398 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSDK_OS_FREE_RTOS \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSDK_OS_FREE_RTOS \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSDK_OS_FREE_RTOS \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSDK_OS_FREE_RTOS \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Xlinker \ + --defsym=__stack_size__=0x400 \ + -Xlinker \ + --defsym=__heap_size__=0x400 \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Xlinker \ + --defsym=__stack_size__=0x400 \ + -Xlinker \ + --defsym=__heap_size__=0x400 \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Xlinker \ + --defsym=__stack_size__=0x400 \ + -Xlinker \ + --defsym=__heap_size__=0x400 \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Xlinker \ + --defsym=__stack_size__=0x400 \ + -Xlinker \ + --defsym=__heap_size__=0x400 \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.c b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.c b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/fsl_iomuxc.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/main_remote.c b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/main_remote.c new file mode 100644 index 000000000..56e15f9d3 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/main_remote.c @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include "rpmsg_lite.h" +#include "rpmsg_queue.h" +#include "rpmsg_ns.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "FreeRTOS.h" +#include "task.h" + +#include "fsl_uart.h" +#include "rsc_table.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define RPMSG_LITE_LINK_ID (RL_PLATFORM_IMX8MQ_M4_USER_LINK_ID) +#define RPMSG_LITE_SHMEM_BASE (VDEV0_VRING_BASE) +#define RPMSG_LITE_NS_ANNOUNCE_STRING "rpmsg-openamp-demo-channel" +#define RPMSG_LITE_MASTER_IS_LINUX + +#define APP_DEBUG_UART_BAUDRATE (115200U) /* Debug console baud rate. */ +#define APP_TASK_STACK_SIZE (256U) +#ifndef LOCAL_EPT_ADDR +#define LOCAL_EPT_ADDR (30U) +#endif +#define APP_RPMSG_READY_EVENT_DATA (1U) + +typedef struct the_message +{ + uint32_t DATA; +} THE_MESSAGE, *THE_MESSAGE_PTR; + +static volatile THE_MESSAGE msg = {0}; +#ifdef RPMSG_LITE_MASTER_IS_LINUX +static char helloMsg[13]; +#endif /* RPMSG_LITE_MASTER_IS_LINUX */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +static TaskHandle_t app_task_handle = NULL; + +static void app_nameservice_isr_cb(uint32_t new_ept, const char *new_ept_name, uint32_t flags, void *user_data) +{ +} + +#ifdef MCMGR_USED +/*! + * @brief Application-specific implementation of the SystemInitHook() weak function. + */ +void SystemInitHook(void) +{ + /* Initialize MCMGR - low level multicore management library. Call this + function as close to the reset entry as possible to allow CoreUp event + triggering. The SystemInitHook() weak function overloading is used in this + application. */ + (void)MCMGR_EarlyInit(); +} +#endif /* MCMGR_USED */ + +static void app_task(void *param) +{ + volatile uint32_t remote_addr; + struct rpmsg_lite_endpoint *volatile my_ept; + volatile rpmsg_queue_handle my_queue; + struct rpmsg_lite_instance *volatile my_rpmsg; + volatile rpmsg_ns_handle ns_handle; + + /* Print the initial banner */ + (void)PRINTF("\r\nRPMSG Ping-Pong FreeRTOS RTOS API Demo...\r\n"); + +#ifdef MCMGR_USED + uint32_t startupData; + mcmgr_status_t status; + + /* Get the startup data */ + do + { + status = MCMGR_GetStartupData(&startupData); + } while (status != kStatus_MCMGR_Success); + + my_rpmsg = rpmsg_lite_remote_init((void *)(char *)startupData, RPMSG_LITE_LINK_ID, RL_NO_FLAGS); + + /* Signal the other core we are ready by triggering the event and passing the APP_RPMSG_READY_EVENT_DATA */ + (void)MCMGR_TriggerEvent(kMCMGR_RemoteApplicationEvent, APP_RPMSG_READY_EVENT_DATA); +#else + (void)PRINTF("RPMSG Share Base Addr is 0x%x\r\n", RPMSG_LITE_SHMEM_BASE); + my_rpmsg = rpmsg_lite_remote_init((void *)RPMSG_LITE_SHMEM_BASE, RPMSG_LITE_LINK_ID, RL_NO_FLAGS); +#endif /* MCMGR_USED */ + while (0 == rpmsg_lite_is_link_up(my_rpmsg)) + { + } + (void)PRINTF("Link is up!\r\n"); + + my_queue = rpmsg_queue_create(my_rpmsg); + my_ept = rpmsg_lite_create_ept(my_rpmsg, LOCAL_EPT_ADDR, rpmsg_queue_rx_cb, my_queue); + ns_handle = rpmsg_ns_bind(my_rpmsg, app_nameservice_isr_cb, ((void *)0)); + /* Introduce some delay to avoid NS announce message not being captured by the master side. + This could happen when the remote side execution is too fast and the NS announce message is triggered + before the nameservice_isr_cb is registered on the master side. */ + SDK_DelayAtLeastUs(1000000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + (void)rpmsg_ns_announce(my_rpmsg, my_ept, RPMSG_LITE_NS_ANNOUNCE_STRING, (uint32_t)RL_NS_CREATE); + (void)PRINTF("Nameservice announce sent.\r\n"); + +#ifdef RPMSG_LITE_MASTER_IS_LINUX + /* Wait Hello handshake message from Remote Core. */ + (void)rpmsg_queue_recv(my_rpmsg, my_queue, (uint32_t *)&remote_addr, helloMsg, sizeof(helloMsg), ((void *)0), + RL_BLOCK); +#endif /* RPMSG_LITE_MASTER_IS_LINUX */ + + while (msg.DATA <= 100U) + { + (void)PRINTF("Waiting for ping...\r\n"); + (void)rpmsg_queue_recv(my_rpmsg, my_queue, (uint32_t *)&remote_addr, (char *)&msg, sizeof(THE_MESSAGE), + ((void *)0), RL_BLOCK); + msg.DATA++; + (void)PRINTF("Sending pong...\r\n"); + (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, sizeof(THE_MESSAGE), RL_BLOCK); + } + + (void)PRINTF("Ping pong done, deinitializing...\r\n"); + + (void)rpmsg_lite_destroy_ept(my_rpmsg, my_ept); + my_ept = ((void *)0); + (void)rpmsg_queue_destroy(my_rpmsg, my_queue); + my_queue = ((void *)0); + (void)rpmsg_ns_unbind(my_rpmsg, ns_handle); + (void)rpmsg_lite_deinit(my_rpmsg); + msg.DATA = 0U; + + (void)PRINTF("Looping forever...\r\n"); + + /* End of the example */ + for (;;) + { + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + /* Initialize standard SDK demo application pins */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + copyResourceTable(); + +#ifdef MCMGR_USED + /* Initialize MCMGR before calling its API */ + (void)MCMGR_Init(); +#endif /* MCMGR_USED */ + + if (xTaskCreate(app_task, "APP_TASK", APP_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY + 1U, &app_task_handle) != pdPASS) + { + (void)PRINTF("\r\nFailed to create application task\r\n"); + for (;;) + { + } + } + + vTaskStartScheduler(); + + (void)PRINTF("Failed to start FreeRTOS on core0.\r\n"); + for (;;) + { + } +} diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.c b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/readme.txt b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/readme.txt new file mode 100644 index 000000000..0f0a14fc1 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/readme.txt @@ -0,0 +1,85 @@ +Overview +======== +The Multicore RPMsg-Lite pingpong RTOS project is a simple demonstration program that uses the +MCUXpresso SDK software and the RPMsg-Lite library and shows how to implement the inter-core +communicaton between cores of the multicore system. The primary core releases the secondary core +from the reset and then the inter-core communication is established. Once the RPMsg is initialized +and endpoints are created the message exchange starts, incrementing a virtual counter that is part +of the message payload. The message pingpong finishes when the counter reaches the value of 100. +Then the RPMsg-Lite is deinitialized and the procedure of the data exchange is repeated again. + +Shared memory usage +This multicore example uses the shared memory for data exchange. The shared memory region is +defined and the size can be adjustable in the linker file. The shared memory region start address +and the size have to be defined in linker file for each core equally. The shared memory start +address is then exported from the linker to the application. + +Toolchain supported +=================== +- GCC ARM Embedded 10.2.1 +- IAR embedded Workbench 9.10.2 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special is needed. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open two serial terminals for A53 core and M4 core with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Using U-Boot command to run the demo.bin file. For details, please refer to Getting Started with MCUXpresso SDK i.MX 8M Quad.pdf +5. After running the demo.bin, using the "boot" command to boot the kernel on the A core terminal; +6. After the kernel is boot, using "root" to login. +7. After login, make sure imx_rpmsg_pingpong kernel module is inserted (lsmod) or insert it (modprobe imx_rpmsg_pingpong). + +Running the demo +================ + +After the boot process succeeds, the ARM Cortex-M4 terminal displays the following information: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +RPMSG Ping-Pong FreeRTOS RTOS API Demo... +RPMSG Share Base Addr is 0xb8000000 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +During boot the Kernel,the ARM Cortex-M4 terminal displays the following information: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Link is up! +Nameservice announce sent. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +After the Linux RPMsg pingpong module was installed, the ARM Cortex-M4 terminal displays the following information: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Waiting for ping... +Sending pong... +Waiting for ping... +Sending pong... +Waiting for ping... +Sending pong... +...... +Waiting for ping... +Sending pong... +Ping pong done, deinitializing... +Looping forever... +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The Cortex-A terminal displays the following information: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +get 1 (src: 0x1e) +get 3 (src: 0x1e) +...... +get 99 (src: 0x1e) +get 101 (src: 0x1e) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/remoteproc.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/remoteproc.h new file mode 100644 index 000000000..7dad9c9eb --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/remoteproc.h @@ -0,0 +1,372 @@ +/* + * Remoteproc Framework + * + * Copyright 2020 NXP. + * Copyright(c) 2018 Xilinx Ltd. + * Copyright(c) 2011 Texas Instruments, Inc. + * Copyright(c) 2011 Google, Inc. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef REMOTEPROC_H +#define REMOTEPROC_H + +#include + +#if defined __cplusplus +extern "C" { +#endif + +#define RSC_NOTIFY_ID_ANY 0xFFFFFFFFUL + +#define RPROC_MAX_NAME_LEN 32 + +/* IAR ARM build tools */ +#if defined(__ICCARM__) + +#ifndef METAL_PACKED_BEGIN +#define METAL_PACKED_BEGIN __packed +#endif + +#ifndef METAL_PACKED_END +#define METAL_PACKED_END +#endif + +/* GNUC */ +#elif defined(__GNUC__) + +#ifndef METAL_PACKED_BEGIN +#define METAL_PACKED_BEGIN +#endif + +#ifndef METAL_PACKED_END +#define METAL_PACKED_END __attribute__((__packed__)) +#endif + +/* ARMCC */ +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) + +#ifndef METAL_PACKED_BEGIN +#define METAL_PACKED_BEGIN _Pragma("pack(1U)") +#endif + +#ifndef METAL_PACKED_END +#define METAL_PACKED_END _Pragma("pack()") +#endif + +#else +/* There is no default definition here to avoid wrong structures packing in case of not supported compiler */ +#error Please implement the structure packing macros for your compiler here! +#endif + +/** + * struct resource_table - firmware resource table header + * @ver: version number + * @num: number of resource entries + * @reserved: reserved (must be zero) + * @offset: array of offsets pointing at the various resource entries + * + * A resource table is essentially a list of system resources required + * by the remote remoteproc. It may also include configuration entries. + * If needed, the remote remoteproc firmware should contain this table + * as a dedicated ".resource_table" ELF section. + * + * Some resources entries are mere announcements, where the host is informed + * of specific remoteproc configuration. Other entries require the host to + * do something (e.g. allocate a system resource). Sometimes a negotiation + * is expected, where the firmware requests a resource, and once allocated, + * the host should provide back its details (e.g. address of an allocated + * memory region). + * + * The header of the resource table, as expressed by this structure, + * contains a version number (should we need to change this format in the + * future), the number of available resource entries, and their offsets + * in the table. + * + * Immediately following this header are the resource entries themselves, + * each of which begins with a resource entry header (as described below). + */ +METAL_PACKED_BEGIN +struct resource_table +{ + uint32_t ver; + uint32_t num; + uint32_t reserved[2]; + uint32_t offset[0]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_hdr - firmware resource entry header + * @type: resource type + * @data: resource data + * + * Every resource entry begins with a 'struct fw_rsc_hdr' header providing + * its @type. The content of the entry itself will immediately follow + * this header, and it should be parsed according to the resource type. + */ +METAL_PACKED_BEGIN +struct fw_rsc_hdr +{ + uint32_t type; + uint8_t data[0]; +} METAL_PACKED_END; + +/** + * enum fw_resource_type - types of resource entries + * + * @RSC_CARVEOUT: request for allocation of a physically contiguous + * memory region. + * @RSC_DEVMEM: request to iommu_map a memory-based peripheral. + * @RSC_TRACE: announces the availability of a trace buffer into which + * the remote remoteproc will be writing logs. + * @RSC_VDEV: declare support for a virtio device, and serve as its + * virtio header. + * @RSC_VENDOR_START: start of the vendor specific resource types range + * @RSC_VENDOR_END : end of the vendor specific resource types range + * @RSC_LAST: just keep this one at the end + * + * For more details regarding a specific resource type, please see its + * dedicated structure below. + * + * Please note that these values are used as indices to the rproc_handle_rsc + * lookup table, so please keep them sane. Moreover, @RSC_LAST is used to + * check the validity of an index before the lookup table is accessed, so + * please update it as needed. + */ +enum fw_resource_type +{ + RSC_CARVEOUT = 0, + RSC_DEVMEM = 1, + RSC_TRACE = 2, + RSC_VDEV = 3, + RSC_LAST = 4, + RSC_VENDOR_START = 128, + RSC_VENDOR_END = 512, +}; + +#define FW_RSC_U64_ADDR_ANY 0xFFFFFFFFFFFFFFFFUL +#define FW_RSC_U32_ADDR_ANY 0xFFFFFFFFUL + +/** + * struct fw_rsc_carveout - physically contiguous memory request + * @da: device address + * @pa: physical address + * @len: length (in bytes) + * @flags: iommu protection flags + * @reserved: reserved (must be zero) + * @name: human-readable name of the requested memory region + * + * This resource entry requests the host to allocate a physically contiguous + * memory region. + * + * These request entries should precede other firmware resource entries, + * as other entries might request placing other data objects inside + * these memory regions (e.g. data/code segments, trace resource entries, ...). + * + * Allocating memory this way helps utilizing the reserved physical memory + * (e.g. CMA) more efficiently, and also minimizes the number of TLB entries + * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB + * pressure is important; it may have a substantial impact on performance. + * + * If the firmware is compiled with static addresses, then @da should specify + * the expected device address of this memory region. If @da is set to + * FW_RSC_ADDR_ANY, then the host will dynamically allocate it, and then + * overwrite @da with the dynamically allocated address. + * + * We will always use @da to negotiate the device addresses, even if it + * isn't using an iommu. In that case, though, it will obviously contain + * physical addresses. + * + * Some remote remoteprocs needs to know the allocated physical address + * even if they do use an iommu. This is needed, e.g., if they control + * hardware accelerators which access the physical memory directly (this + * is the case with OMAP4 for instance). In that case, the host will + * overwrite @pa with the dynamically allocated physical address. + * Generally we don't want to expose physical addresses if we don't have to + * (remote remoteprocs are generally _not_ trusted), so we might want to + * change this to happen _only_ when explicitly required by the hardware. + * + * @flags is used to provide IOMMU protection flags, and @name should + * (optionally) contain a human readable name of this carveout region + * (mainly for debugging purposes). + */ +METAL_PACKED_BEGIN +struct fw_rsc_carveout +{ + uint32_t type; + uint32_t da; + uint32_t pa; + uint32_t len; + uint32_t flags; + uint32_t reserved; + uint8_t name[RPROC_MAX_NAME_LEN]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_devmem - iommu mapping request + * @da: device address + * @pa: physical address + * @len: length (in bytes) + * @flags: iommu protection flags + * @reserved: reserved (must be zero) + * @name: human-readable name of the requested region to be mapped + * + * This resource entry requests the host to iommu map a physically contiguous + * memory region. This is needed in case the remote remoteproc requires + * access to certain memory-based peripherals; _never_ use it to access + * regular memory. + * + * This is obviously only needed if the remote remoteproc is accessing memory + * via an iommu. + * + * @da should specify the required device address, @pa should specify + * the physical address we want to map, @len should specify the size of + * the mapping and @flags is the IOMMU protection flags. As always, @name may + * (optionally) contain a human readable name of this mapping (mainly for + * debugging purposes). + * + * Note: at this point we just "trust" those devmem entries to contain valid + * physical addresses, but this isn't safe and will be changed: eventually we + * want remoteproc implementations to provide us ranges of physical addresses + * the firmware is allowed to request, and not allow firmwares to request + * access to physical addresses that are outside those ranges. + */ +METAL_PACKED_BEGIN +struct fw_rsc_devmem +{ + uint32_t type; + uint32_t da; + uint32_t pa; + uint32_t len; + uint32_t flags; + uint32_t reserved; + uint8_t name[RPROC_MAX_NAME_LEN]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_trace - trace buffer declaration + * @da: device address + * @len: length (in bytes) + * @reserved: reserved (must be zero) + * @name: human-readable name of the trace buffer + * + * This resource entry provides the host information about a trace buffer + * into which the remote remoteproc will write log messages. + * + * @da specifies the device address of the buffer, @len specifies + * its size, and @name may contain a human readable name of the trace buffer. + * + * After booting the remote remoteproc, the trace buffers are exposed to the + * user via debugfs entries (called trace0, trace1, etc..). + */ +METAL_PACKED_BEGIN +struct fw_rsc_trace +{ + uint32_t type; + uint32_t da; + uint32_t len; + uint32_t reserved; + uint8_t name[RPROC_MAX_NAME_LEN]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_vdev_vring - vring descriptor entry + * @da: device address + * @align: the alignment between the consumer and producer parts of the vring + * @num: num of buffers supported by this vring (must be power of two) + * @notifyid is a unique rproc-wide notify index for this vring. This notify + * index is used when kicking a remote remoteproc, to let it know that this + * vring is triggered. + * @reserved: reserved (must be zero) + * + * This descriptor is not a resource entry by itself; it is part of the + * vdev resource type (see below). + * + * Note that @da should either contain the device address where + * the remote remoteproc is expecting the vring, or indicate that + * dynamically allocation of the vring's device address is supported. + */ +METAL_PACKED_BEGIN +struct fw_rsc_vdev_vring +{ + uint32_t da; + uint32_t align; + uint32_t num; + uint32_t notifyid; + uint32_t reserved; +} METAL_PACKED_END; + +/** + * struct fw_rsc_vdev - virtio device header + * @id: virtio device id (as in virtio_ids.h) + * @notifyid is a unique rproc-wide notify index for this vdev. This notify + * index is used when kicking a remote remoteproc, to let it know that the + * status/features of this vdev have changes. + * @dfeatures specifies the virtio device features supported by the firmware + * @gfeatures is a place holder used by the host to write back the + * negotiated features that are supported by both sides. + * @config_len is the size of the virtio config space of this vdev. The config + * space lies in the resource table immediate after this vdev header. + * @status is a place holder where the host will indicate its virtio progress. + * @num_of_vrings indicates how many vrings are described in this vdev header + * @reserved: reserved (must be zero) + * @vring is an array of @num_of_vrings entries of 'struct fw_rsc_vdev_vring'. + * + * This resource is a virtio device header: it provides information about + * the vdev, and is then used by the host and its peer remote remoteprocs + * to negotiate and share certain virtio properties. + * + * By providing this resource entry, the firmware essentially asks remoteproc + * to statically allocate a vdev upon registration of the rproc (dynamic vdev + * allocation is not yet supported). + * + * Note: unlike virtualization systems, the term 'host' here means + * the Linux side which is running remoteproc to control the remote + * remoteprocs. We use the name 'gfeatures' to comply with virtio's terms, + * though there isn't really any virtualized guest OS here: it's the host + * which is responsible for negotiating the final features. + * Yeah, it's a bit confusing. + * + * Note: immediately following this structure is the virtio config space for + * this vdev (which is specific to the vdev; for more info, read the virtio + * spec). the size of the config space is specified by @config_len. + */ +METAL_PACKED_BEGIN +struct fw_rsc_vdev +{ + uint32_t type; + uint32_t id; + uint32_t notifyid; + uint32_t dfeatures; + uint32_t gfeatures; + uint32_t config_len; + uint8_t status; + uint8_t num_of_vrings; + uint8_t reserved[2]; + struct fw_rsc_vdev_vring vring[0]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_vendor - remote processor vendor specific resource + * @len: length of the resource + * + * This resource entry tells the host the vendor specific resource + * required by the remote. + * + * These request entries should precede other shared resource entries + * such as vdevs, vrings. + */ +METAL_PACKED_BEGIN +struct fw_rsc_vendor +{ + uint32_t type; + uint32_t len; +} METAL_PACKED_END; + +#if defined __cplusplus +} +#endif + +#endif /* REMOTEPROC_H_ */ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_config.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_config.h new file mode 100644 index 000000000..ff0f400a8 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_config.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * Copyright (c) 2015 Xilinx, Inc. + * Copyright (c) 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPMSG_CONFIG_H_ +#define RPMSG_CONFIG_H_ + +/*! + * @addtogroup config + * @{ + * @file + */ + +//! @name Configuration options +//@{ + +//! @def RL_MS_PER_INTERVAL +//! +//! Delay in milliseconds used in non-blocking API functions for polling. +//! The default value is 1. +#define RL_MS_PER_INTERVAL (1) + +//! @def RL_BUFFER_PAYLOAD_SIZE +//! +//! Size of the buffer payload, it must be equal to (240, 496, 1008, ...) +//! [2^n - 16]. Ensure the same value is defined on both sides of rpmsg +//! communication. The default value is 496U. +#define RL_BUFFER_PAYLOAD_SIZE (496U) + +//! @def RL_BUFFER_COUNT +//! +//! Number of the buffers, it must be power of two (2, 4, ...). +//! The default value is 2U. +//! Note this value defines the buffer count for one direction of the rpmsg +//! communication only, i.e. if the default value of 2 is used +//! in rpmsg_config.h files for the master and the remote side, 4 buffers +//! in total are created in the shared memory. +#define RL_BUFFER_COUNT (256U) + +//! @def RL_API_HAS_ZEROCOPY +//! +//! Zero-copy API functions enabled/disabled. +//! The default value is 1 (enabled). +#define RL_API_HAS_ZEROCOPY (1) + +//! @def RL_USE_STATIC_API +//! +//! Static API functions (no dynamic allocation) enabled/disabled. +//! The default value is 0 (static API disabled). +#define RL_USE_STATIC_API (0) + +//! @def RL_CLEAR_USED_BUFFERS +//! +//! Clearing used buffers before returning back to the pool of free buffers +//! enabled/disabled. +//! The default value is 0 (disabled). +#define RL_CLEAR_USED_BUFFERS (0) + +//! @def RL_USE_MCMGR_IPC_ISR_HANDLER +//! +//! When enabled IPC interrupts are managed by the Multicore Manager (IPC +//! interrupts router), when disabled RPMsg-Lite manages IPC interrupts +//! by itself. +//! The default value is 0 (no MCMGR IPC ISR handler used). +#define RL_USE_MCMGR_IPC_ISR_HANDLER (0) + +//! @def RL_USE_ENVIRONMENT_CONTEXT +//! +//! When enabled the environment layer uses its own context. +//! Added for QNX port mainly, but can be used if required. +//! The default value is 0 (no context, saves some RAM). +#define RL_USE_ENVIRONMENT_CONTEXT (0) + +//! @def RL_DEBUG_CHECK_BUFFERS +//! +//! Do not use in RPMsg-Lite to Linux configuration +#define RL_DEBUG_CHECK_BUFFERS (0) +//@} + +#endif /* RPMSG_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_lite_pingpong_rtos_linux_remote_v3_8.xml b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_lite_pingpong_rtos_linux_remote_v3_8.xml new file mode 100644 index 000000000..eadcd3ffa --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_lite_pingpong_rtos_linux_remote_v3_8.xml @@ -0,0 +1,146 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.c b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.c new file mode 100644 index 000000000..5346e3dca --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file populates resource table for BM remote + * for use by the Linux Master */ + +#include "board.h" +#include "rsc_table.h" +#include "rpmsg_lite.h" +#include + +#define NUM_VRINGS 0x02 + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const struct remote_resource_table resources = { + /* Version */ + 1, + + /* NUmber of table entries */ + NO_RESOURCE_ENTRIES, + /* reserved fields */ + { + 0, + 0, + }, + + /* Offsets of rsc entries */ + { + offsetof(struct remote_resource_table, user_vdev), + }, + + /* SRTM virtio device entry */ + { + RSC_VDEV, + 7, + 0, + RSC_VDEV_FEATURE_NS, + 0, + 0, + 0, + NUM_VRINGS, + {0, 0}, + }, + + /* Vring rsc entry - part of vdev rsc entry */ + {VDEV0_VRING_BASE, VRING_ALIGN, RL_BUFFER_COUNT, 0, 0}, + {VDEV0_VRING_BASE + VRING_SIZE, VRING_ALIGN, RL_BUFFER_COUNT, 1, 0}, +}; + +void copyResourceTable(void) +{ + /* + * Resource table should be copied to VDEV0_VRING_BASE + RESOURCE_TABLE_OFFSET. + * VDEV0_VRING_BASE is temperorily kept for backward compatibility, will be + * removed in future release + */ + memcpy((void *)VDEV0_VRING_BASE, &resources, sizeof(resources)); + memcpy((void *)(VDEV0_VRING_BASE + RESOURCE_TABLE_OFFSET), &resources, sizeof(resources)); +} diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.h new file mode 100644 index 000000000..9562f6911 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file populates resource table for BM remote + * for use by the Linux Master */ + +#ifndef RSC_TABLE_H_ +#define RSC_TABLE_H_ + +#include +#include + +#if defined __cplusplus +extern "C" { +#endif + +#define NO_RESOURCE_ENTRIES (1) +#define RSC_VDEV_FEATURE_NS (1) /* Support name service announcement */ + +/* Resource table for the given remote */ +METAL_PACKED_BEGIN +struct remote_resource_table +{ + uint32_t version; + uint32_t num; + uint32_t reserved[2]; + uint32_t offset[NO_RESOURCE_ENTRIES]; + + /* rpmsg vdev entry for user app communication */ + struct fw_rsc_vdev user_vdev; + struct fw_rsc_vdev_vring user_vring0; + struct fw_rsc_vdev_vring user_vring1; +} METAL_PACKED_END; + +/* + * Copy resource table to shared memory base for early M4 boot case. + * In M4 early boot case, Linux kernel need to get resource table before file system gets loaded. + */ +void copyResourceTable(void); + +#if defined __cplusplus +} +#endif + +#endif /* RSC_TABLE_H_ */ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/FreeRTOSConfig.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/FreeRTOSConfig.h new file mode 100644 index 000000000..88eaaeb2d --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/FreeRTOSConfig.h @@ -0,0 +1,160 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 10 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY 2 +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +#define configASSERT_BOOL(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} +#define configASSERT(x) configASSERT_BOOL((x)!=0) + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#endif +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/CMakeLists.txt b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/CMakeLists.txt new file mode 100644 index 000000000..cf30cea04 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/CMakeLists.txt @@ -0,0 +1,123 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(rpmsg_lite_str_echo_rtos_imxcm4) + +set(MCUX_SDK_PROJECT_NAME rpmsg_lite_str_echo_rtos_imxcm4.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../main_remote.c" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../rpmsg_config.h" +"${ProjDirPath}/../rsc_table.c" +"${ProjDirPath}/../rsc_table.h" +"${ProjDirPath}/../remoteproc.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../middleware/multicore + ${ProjDirPath}/../../../../../rtos/freertos + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/serial_manager + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include +) + +# include modules +include(middleware_multicore_rpmsg_lite_imx8mq_m4_freertos_MIMX8MQ6) + +include(middleware_freertos-kernel_heap_4_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(driver_mu_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(utility_debug_console_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_serial_manager_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(component_serial_manager_uart_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(utility_assert_MIMX8MQ6) + +include(middleware_multicore_rpmsg_lite_MIMX8MQ6) + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/rpmsg_lite_str_echo_rtos.bin) + diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..7cd2c1827 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..f59eebb35 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.bat b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.bat new file mode 100644 index 000000000..0cf4090ae --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug 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-DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.sh b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.sh new file mode 100755 index 000000000..dbf5b91b5 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..c84d78542 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..5aa41a2df --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..3fd6f4a78 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c9e344144 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.bat b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.sh b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.sh new file mode 100755 index 000000000..42803761b --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.bat b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.bat 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-DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.bat b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.sh b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/config.cmake b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/config.cmake new file mode 100755 index 000000000..6a7f992aa --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/config.cmake @@ -0,0 +1,4 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) +set(CONFIG_USE_middleware_freertos-kernel_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/flags.cmake b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/flags.cmake new file mode 100755 index 000000000..3a0932ebf --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/flags.cmake @@ -0,0 +1,398 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSDK_OS_FREE_RTOS \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSDK_OS_FREE_RTOS \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSDK_OS_FREE_RTOS \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSDK_OS_FREE_RTOS \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Xlinker \ + --defsym=__stack_size__=0x400 \ + -Xlinker \ + --defsym=__heap_size__=0x400 \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Xlinker \ + --defsym=__stack_size__=0x400 \ + -Xlinker \ + --defsym=__heap_size__=0x400 \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Xlinker \ + --defsym=__stack_size__=0x400 \ + -Xlinker \ + --defsym=__heap_size__=0x400 \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Xlinker \ + --defsym=__stack_size__=0x400 \ + -Xlinker \ + --defsym=__heap_size__=0x400 \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/board.c b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/board.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.c b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/fsl_iomuxc.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/main_remote.c b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/main_remote.c new file mode 100644 index 000000000..1d15a3b0c --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/main_remote.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include "rpmsg_lite.h" +#include "rpmsg_queue.h" +#include "rpmsg_ns.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "FreeRTOS.h" +#include "task.h" + +#include "fsl_uart.h" +#include "rsc_table.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define RPMSG_LITE_SHMEM_BASE (VDEV0_VRING_BASE) +#define RPMSG_LITE_LINK_ID (RL_PLATFORM_IMX8MQ_M4_USER_LINK_ID) +#define RPMSG_LITE_NS_ANNOUNCE_STRING "rpmsg-virtual-tty-channel-1" +#define APP_TASK_STACK_SIZE (256) +#ifndef LOCAL_EPT_ADDR +#define LOCAL_EPT_ADDR (30) +#endif + +/* Globals */ +static char app_buf[512]; /* Each RPMSG buffer can carry less than 512 payload */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +static TaskHandle_t app_task_handle = NULL; + +static void app_task(void *param) +{ + volatile uint32_t remote_addr; + struct rpmsg_lite_endpoint *volatile my_ept; + volatile rpmsg_queue_handle my_queue; + struct rpmsg_lite_instance *volatile my_rpmsg; + void *rx_buf; + uint32_t len; + int32_t result; + void *tx_buf; + uint32_t size; + + /* Print the initial banner */ + PRINTF("\r\nRPMSG String Echo FreeRTOS RTOS API Demo...\r\n"); + +#ifdef MCMGR_USED + uint32_t startupData; + + /* Get the startup data */ + (void)MCMGR_GetStartupData(kMCMGR_Core1, &startupData); + + my_rpmsg = rpmsg_lite_remote_init((void *)startupData, RPMSG_LITE_LINK_ID, RL_NO_FLAGS); + + /* Signal the other core we are ready */ + (void)MCMGR_SignalReady(kMCMGR_Core1); +#else + my_rpmsg = rpmsg_lite_remote_init((void *)RPMSG_LITE_SHMEM_BASE, RPMSG_LITE_LINK_ID, RL_NO_FLAGS); +#endif /* MCMGR_USED */ + + while (0 == rpmsg_lite_is_link_up(my_rpmsg)) + ; + + my_queue = rpmsg_queue_create(my_rpmsg); + my_ept = rpmsg_lite_create_ept(my_rpmsg, LOCAL_EPT_ADDR, rpmsg_queue_rx_cb, my_queue); + (void)rpmsg_ns_announce(my_rpmsg, my_ept, RPMSG_LITE_NS_ANNOUNCE_STRING, RL_NS_CREATE); + + PRINTF("\r\nNameservice sent, ready for incoming messages...\r\n"); + + for (;;) + { + /* Get RPMsg rx buffer with message */ + result = + rpmsg_queue_recv_nocopy(my_rpmsg, my_queue, (uint32_t *)&remote_addr, (char **)&rx_buf, &len, RL_BLOCK); + if (result != 0) + { + assert(false); + } + + /* Copy string from RPMsg rx buffer */ + assert(len < sizeof(app_buf)); + memcpy(app_buf, rx_buf, len); + app_buf[len] = 0; /* End string by '\0' */ + + if ((len == 2) && (app_buf[0] == 0xd) && (app_buf[1] == 0xa)) + PRINTF("Get New Line From Master Side\r\n"); + else + PRINTF("Get Message From Master Side : \"%s\" [len : %d]\r\n", app_buf, len); + + /* Get tx buffer from RPMsg */ + tx_buf = rpmsg_lite_alloc_tx_buffer(my_rpmsg, &size, RL_BLOCK); + assert(tx_buf); + /* Copy string to RPMsg tx buffer */ + memcpy(tx_buf, app_buf, len); + /* Echo back received message with nocopy send */ + result = rpmsg_lite_send_nocopy(my_rpmsg, my_ept, remote_addr, tx_buf, len); + if (result != 0) + { + assert(false); + } + /* Release held RPMsg rx buffer */ + result = rpmsg_queue_nocopy_free(my_rpmsg, rx_buf); + if (result != 0) + { + assert(false); + } + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + /* Initialize standard SDK demo application pins */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + copyResourceTable(); + +#ifdef MCMGR_USED + /* Initialize MCMGR before calling its API */ + (void)MCMGR_Init(); +#endif /* MCMGR_USED */ + + if (xTaskCreate(app_task, "APP_TASK", APP_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY + 1, &app_task_handle) != pdPASS) + { + PRINTF("\r\nFailed to create application task\r\n"); + for (;;) + ; + } + + vTaskStartScheduler(); + + PRINTF("Failed to start FreeRTOS on core0.\n"); + for (;;) + ; +} diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.c b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/readme.txt b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/readme.txt new file mode 100644 index 000000000..bd5751d45 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/readme.txt @@ -0,0 +1,77 @@ +Overview +======== +The Multicore RPMsg-Lite string echo project is a simple demonstration program that uses the +MCUXpresso SDK software and the RPMsg-Lite library and shows how to implement the inter-core +communicaton between cores of the multicore system. + +It works with Linux RPMsg master peer to transfer string content back and forth. The name service +handshake is performed first to create the communication channels. Next, Linux OS waits for user +input to the RPMsg virtual tty. Anything which is received is sent to M4. M4 displays what is +received, and echoes back the same message as an acknowledgement. The tty reader on the Linux side +can get the message, and start another transaction. The demo demonstrates RPMsg’s ability to send +arbitrary content back and forth. Note: The maximum message length supported by RPMsg is now 496 +bytes. String longer than 496 will be divided by virtual tty into several messages. + +Shared memory usage +This multicore example uses the shared memory for data exchange. The shared memory region is +defined and the size can be adjustable in the linker file. The shared memory region start address +and the size have to be defined in linker file for each core equally. The shared memory start +address is then exported from the linker to the application. + +Toolchain supported +=================== +- GCC ARM Embedded 10.2.1 +- IAR embedded Workbench 9.10.2 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special is needed. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open two serial terminals for A53 core and M4 core with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Using U-Boot command to run the demo.bin file. For details, please refer to Getting Started with MCUXpresso SDK i.MX 8M Quad.pdf +5. After running the demo.bin, using the "boot" command to boot the kernel on the A core terminal; +6. After the kernel is boot, using "root" to login. +7. After login, make sure imx_rpmsg_tty kernel module is inserted (lsmod) or insert it (modprobe imx_rpmsg_tty). + +Running the demo +================ +After the boot process succeeds, the ARM Cortex-M4 terminal displays the following information: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +RPMSG String Echo FreeRTOS RTOS API Demo... + +Nameservice sent, ready for incoming messages... +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +After the Linux RPMsg tty module was installed, the ARM Cortex-M4 terminal displays the following +information: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Get Messgae From Master Side : "hello world!" [len : 12] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The user can then input an arbitrary string to the virtual RPMsg tty using the following echo command on +Cortex-A terminal: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +echo test > /dev/ttyRPMSG30 log below shows the output of the RPMsg-Lite str echo demo in the terminal window: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +On the M4 terminal, the received string content and its length is output, as shown in the log. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Get Message From Master Side : "test" [len : 4] +Get New Line From Master Side +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/remoteproc.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/remoteproc.h new file mode 100644 index 000000000..7dad9c9eb --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/remoteproc.h @@ -0,0 +1,372 @@ +/* + * Remoteproc Framework + * + * Copyright 2020 NXP. + * Copyright(c) 2018 Xilinx Ltd. + * Copyright(c) 2011 Texas Instruments, Inc. + * Copyright(c) 2011 Google, Inc. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef REMOTEPROC_H +#define REMOTEPROC_H + +#include + +#if defined __cplusplus +extern "C" { +#endif + +#define RSC_NOTIFY_ID_ANY 0xFFFFFFFFUL + +#define RPROC_MAX_NAME_LEN 32 + +/* IAR ARM build tools */ +#if defined(__ICCARM__) + +#ifndef METAL_PACKED_BEGIN +#define METAL_PACKED_BEGIN __packed +#endif + +#ifndef METAL_PACKED_END +#define METAL_PACKED_END +#endif + +/* GNUC */ +#elif defined(__GNUC__) + +#ifndef METAL_PACKED_BEGIN +#define METAL_PACKED_BEGIN +#endif + +#ifndef METAL_PACKED_END +#define METAL_PACKED_END __attribute__((__packed__)) +#endif + +/* ARMCC */ +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) + +#ifndef METAL_PACKED_BEGIN +#define METAL_PACKED_BEGIN _Pragma("pack(1U)") +#endif + +#ifndef METAL_PACKED_END +#define METAL_PACKED_END _Pragma("pack()") +#endif + +#else +/* There is no default definition here to avoid wrong structures packing in case of not supported compiler */ +#error Please implement the structure packing macros for your compiler here! +#endif + +/** + * struct resource_table - firmware resource table header + * @ver: version number + * @num: number of resource entries + * @reserved: reserved (must be zero) + * @offset: array of offsets pointing at the various resource entries + * + * A resource table is essentially a list of system resources required + * by the remote remoteproc. It may also include configuration entries. + * If needed, the remote remoteproc firmware should contain this table + * as a dedicated ".resource_table" ELF section. + * + * Some resources entries are mere announcements, where the host is informed + * of specific remoteproc configuration. Other entries require the host to + * do something (e.g. allocate a system resource). Sometimes a negotiation + * is expected, where the firmware requests a resource, and once allocated, + * the host should provide back its details (e.g. address of an allocated + * memory region). + * + * The header of the resource table, as expressed by this structure, + * contains a version number (should we need to change this format in the + * future), the number of available resource entries, and their offsets + * in the table. + * + * Immediately following this header are the resource entries themselves, + * each of which begins with a resource entry header (as described below). + */ +METAL_PACKED_BEGIN +struct resource_table +{ + uint32_t ver; + uint32_t num; + uint32_t reserved[2]; + uint32_t offset[0]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_hdr - firmware resource entry header + * @type: resource type + * @data: resource data + * + * Every resource entry begins with a 'struct fw_rsc_hdr' header providing + * its @type. The content of the entry itself will immediately follow + * this header, and it should be parsed according to the resource type. + */ +METAL_PACKED_BEGIN +struct fw_rsc_hdr +{ + uint32_t type; + uint8_t data[0]; +} METAL_PACKED_END; + +/** + * enum fw_resource_type - types of resource entries + * + * @RSC_CARVEOUT: request for allocation of a physically contiguous + * memory region. + * @RSC_DEVMEM: request to iommu_map a memory-based peripheral. + * @RSC_TRACE: announces the availability of a trace buffer into which + * the remote remoteproc will be writing logs. + * @RSC_VDEV: declare support for a virtio device, and serve as its + * virtio header. + * @RSC_VENDOR_START: start of the vendor specific resource types range + * @RSC_VENDOR_END : end of the vendor specific resource types range + * @RSC_LAST: just keep this one at the end + * + * For more details regarding a specific resource type, please see its + * dedicated structure below. + * + * Please note that these values are used as indices to the rproc_handle_rsc + * lookup table, so please keep them sane. Moreover, @RSC_LAST is used to + * check the validity of an index before the lookup table is accessed, so + * please update it as needed. + */ +enum fw_resource_type +{ + RSC_CARVEOUT = 0, + RSC_DEVMEM = 1, + RSC_TRACE = 2, + RSC_VDEV = 3, + RSC_LAST = 4, + RSC_VENDOR_START = 128, + RSC_VENDOR_END = 512, +}; + +#define FW_RSC_U64_ADDR_ANY 0xFFFFFFFFFFFFFFFFUL +#define FW_RSC_U32_ADDR_ANY 0xFFFFFFFFUL + +/** + * struct fw_rsc_carveout - physically contiguous memory request + * @da: device address + * @pa: physical address + * @len: length (in bytes) + * @flags: iommu protection flags + * @reserved: reserved (must be zero) + * @name: human-readable name of the requested memory region + * + * This resource entry requests the host to allocate a physically contiguous + * memory region. + * + * These request entries should precede other firmware resource entries, + * as other entries might request placing other data objects inside + * these memory regions (e.g. data/code segments, trace resource entries, ...). + * + * Allocating memory this way helps utilizing the reserved physical memory + * (e.g. CMA) more efficiently, and also minimizes the number of TLB entries + * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB + * pressure is important; it may have a substantial impact on performance. + * + * If the firmware is compiled with static addresses, then @da should specify + * the expected device address of this memory region. If @da is set to + * FW_RSC_ADDR_ANY, then the host will dynamically allocate it, and then + * overwrite @da with the dynamically allocated address. + * + * We will always use @da to negotiate the device addresses, even if it + * isn't using an iommu. In that case, though, it will obviously contain + * physical addresses. + * + * Some remote remoteprocs needs to know the allocated physical address + * even if they do use an iommu. This is needed, e.g., if they control + * hardware accelerators which access the physical memory directly (this + * is the case with OMAP4 for instance). In that case, the host will + * overwrite @pa with the dynamically allocated physical address. + * Generally we don't want to expose physical addresses if we don't have to + * (remote remoteprocs are generally _not_ trusted), so we might want to + * change this to happen _only_ when explicitly required by the hardware. + * + * @flags is used to provide IOMMU protection flags, and @name should + * (optionally) contain a human readable name of this carveout region + * (mainly for debugging purposes). + */ +METAL_PACKED_BEGIN +struct fw_rsc_carveout +{ + uint32_t type; + uint32_t da; + uint32_t pa; + uint32_t len; + uint32_t flags; + uint32_t reserved; + uint8_t name[RPROC_MAX_NAME_LEN]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_devmem - iommu mapping request + * @da: device address + * @pa: physical address + * @len: length (in bytes) + * @flags: iommu protection flags + * @reserved: reserved (must be zero) + * @name: human-readable name of the requested region to be mapped + * + * This resource entry requests the host to iommu map a physically contiguous + * memory region. This is needed in case the remote remoteproc requires + * access to certain memory-based peripherals; _never_ use it to access + * regular memory. + * + * This is obviously only needed if the remote remoteproc is accessing memory + * via an iommu. + * + * @da should specify the required device address, @pa should specify + * the physical address we want to map, @len should specify the size of + * the mapping and @flags is the IOMMU protection flags. As always, @name may + * (optionally) contain a human readable name of this mapping (mainly for + * debugging purposes). + * + * Note: at this point we just "trust" those devmem entries to contain valid + * physical addresses, but this isn't safe and will be changed: eventually we + * want remoteproc implementations to provide us ranges of physical addresses + * the firmware is allowed to request, and not allow firmwares to request + * access to physical addresses that are outside those ranges. + */ +METAL_PACKED_BEGIN +struct fw_rsc_devmem +{ + uint32_t type; + uint32_t da; + uint32_t pa; + uint32_t len; + uint32_t flags; + uint32_t reserved; + uint8_t name[RPROC_MAX_NAME_LEN]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_trace - trace buffer declaration + * @da: device address + * @len: length (in bytes) + * @reserved: reserved (must be zero) + * @name: human-readable name of the trace buffer + * + * This resource entry provides the host information about a trace buffer + * into which the remote remoteproc will write log messages. + * + * @da specifies the device address of the buffer, @len specifies + * its size, and @name may contain a human readable name of the trace buffer. + * + * After booting the remote remoteproc, the trace buffers are exposed to the + * user via debugfs entries (called trace0, trace1, etc..). + */ +METAL_PACKED_BEGIN +struct fw_rsc_trace +{ + uint32_t type; + uint32_t da; + uint32_t len; + uint32_t reserved; + uint8_t name[RPROC_MAX_NAME_LEN]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_vdev_vring - vring descriptor entry + * @da: device address + * @align: the alignment between the consumer and producer parts of the vring + * @num: num of buffers supported by this vring (must be power of two) + * @notifyid is a unique rproc-wide notify index for this vring. This notify + * index is used when kicking a remote remoteproc, to let it know that this + * vring is triggered. + * @reserved: reserved (must be zero) + * + * This descriptor is not a resource entry by itself; it is part of the + * vdev resource type (see below). + * + * Note that @da should either contain the device address where + * the remote remoteproc is expecting the vring, or indicate that + * dynamically allocation of the vring's device address is supported. + */ +METAL_PACKED_BEGIN +struct fw_rsc_vdev_vring +{ + uint32_t da; + uint32_t align; + uint32_t num; + uint32_t notifyid; + uint32_t reserved; +} METAL_PACKED_END; + +/** + * struct fw_rsc_vdev - virtio device header + * @id: virtio device id (as in virtio_ids.h) + * @notifyid is a unique rproc-wide notify index for this vdev. This notify + * index is used when kicking a remote remoteproc, to let it know that the + * status/features of this vdev have changes. + * @dfeatures specifies the virtio device features supported by the firmware + * @gfeatures is a place holder used by the host to write back the + * negotiated features that are supported by both sides. + * @config_len is the size of the virtio config space of this vdev. The config + * space lies in the resource table immediate after this vdev header. + * @status is a place holder where the host will indicate its virtio progress. + * @num_of_vrings indicates how many vrings are described in this vdev header + * @reserved: reserved (must be zero) + * @vring is an array of @num_of_vrings entries of 'struct fw_rsc_vdev_vring'. + * + * This resource is a virtio device header: it provides information about + * the vdev, and is then used by the host and its peer remote remoteprocs + * to negotiate and share certain virtio properties. + * + * By providing this resource entry, the firmware essentially asks remoteproc + * to statically allocate a vdev upon registration of the rproc (dynamic vdev + * allocation is not yet supported). + * + * Note: unlike virtualization systems, the term 'host' here means + * the Linux side which is running remoteproc to control the remote + * remoteprocs. We use the name 'gfeatures' to comply with virtio's terms, + * though there isn't really any virtualized guest OS here: it's the host + * which is responsible for negotiating the final features. + * Yeah, it's a bit confusing. + * + * Note: immediately following this structure is the virtio config space for + * this vdev (which is specific to the vdev; for more info, read the virtio + * spec). the size of the config space is specified by @config_len. + */ +METAL_PACKED_BEGIN +struct fw_rsc_vdev +{ + uint32_t type; + uint32_t id; + uint32_t notifyid; + uint32_t dfeatures; + uint32_t gfeatures; + uint32_t config_len; + uint8_t status; + uint8_t num_of_vrings; + uint8_t reserved[2]; + struct fw_rsc_vdev_vring vring[0]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_vendor - remote processor vendor specific resource + * @len: length of the resource + * + * This resource entry tells the host the vendor specific resource + * required by the remote. + * + * These request entries should precede other shared resource entries + * such as vdevs, vrings. + */ +METAL_PACKED_BEGIN +struct fw_rsc_vendor +{ + uint32_t type; + uint32_t len; +} METAL_PACKED_END; + +#if defined __cplusplus +} +#endif + +#endif /* REMOTEPROC_H_ */ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_config.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_config.h new file mode 100644 index 000000000..ff0f400a8 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_config.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * Copyright (c) 2015 Xilinx, Inc. + * Copyright (c) 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPMSG_CONFIG_H_ +#define RPMSG_CONFIG_H_ + +/*! + * @addtogroup config + * @{ + * @file + */ + +//! @name Configuration options +//@{ + +//! @def RL_MS_PER_INTERVAL +//! +//! Delay in milliseconds used in non-blocking API functions for polling. +//! The default value is 1. +#define RL_MS_PER_INTERVAL (1) + +//! @def RL_BUFFER_PAYLOAD_SIZE +//! +//! Size of the buffer payload, it must be equal to (240, 496, 1008, ...) +//! [2^n - 16]. Ensure the same value is defined on both sides of rpmsg +//! communication. The default value is 496U. +#define RL_BUFFER_PAYLOAD_SIZE (496U) + +//! @def RL_BUFFER_COUNT +//! +//! Number of the buffers, it must be power of two (2, 4, ...). +//! The default value is 2U. +//! Note this value defines the buffer count for one direction of the rpmsg +//! communication only, i.e. if the default value of 2 is used +//! in rpmsg_config.h files for the master and the remote side, 4 buffers +//! in total are created in the shared memory. +#define RL_BUFFER_COUNT (256U) + +//! @def RL_API_HAS_ZEROCOPY +//! +//! Zero-copy API functions enabled/disabled. +//! The default value is 1 (enabled). +#define RL_API_HAS_ZEROCOPY (1) + +//! @def RL_USE_STATIC_API +//! +//! Static API functions (no dynamic allocation) enabled/disabled. +//! The default value is 0 (static API disabled). +#define RL_USE_STATIC_API (0) + +//! @def RL_CLEAR_USED_BUFFERS +//! +//! Clearing used buffers before returning back to the pool of free buffers +//! enabled/disabled. +//! The default value is 0 (disabled). +#define RL_CLEAR_USED_BUFFERS (0) + +//! @def RL_USE_MCMGR_IPC_ISR_HANDLER +//! +//! When enabled IPC interrupts are managed by the Multicore Manager (IPC +//! interrupts router), when disabled RPMsg-Lite manages IPC interrupts +//! by itself. +//! The default value is 0 (no MCMGR IPC ISR handler used). +#define RL_USE_MCMGR_IPC_ISR_HANDLER (0) + +//! @def RL_USE_ENVIRONMENT_CONTEXT +//! +//! When enabled the environment layer uses its own context. +//! Added for QNX port mainly, but can be used if required. +//! The default value is 0 (no context, saves some RAM). +#define RL_USE_ENVIRONMENT_CONTEXT (0) + +//! @def RL_DEBUG_CHECK_BUFFERS +//! +//! Do not use in RPMsg-Lite to Linux configuration +#define RL_DEBUG_CHECK_BUFFERS (0) +//@} + +#endif /* RPMSG_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_lite_str_echo_rtos_imxcm4_v3_8.xml b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_lite_str_echo_rtos_imxcm4_v3_8.xml new file mode 100644 index 000000000..b1c5c85fb --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_lite_str_echo_rtos_imxcm4_v3_8.xml @@ -0,0 +1,147 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.c b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.c new file mode 100644 index 000000000..5346e3dca --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file populates resource table for BM remote + * for use by the Linux Master */ + +#include "board.h" +#include "rsc_table.h" +#include "rpmsg_lite.h" +#include + +#define NUM_VRINGS 0x02 + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const struct remote_resource_table resources = { + /* Version */ + 1, + + /* NUmber of table entries */ + NO_RESOURCE_ENTRIES, + /* reserved fields */ + { + 0, + 0, + }, + + /* Offsets of rsc entries */ + { + offsetof(struct remote_resource_table, user_vdev), + }, + + /* SRTM virtio device entry */ + { + RSC_VDEV, + 7, + 0, + RSC_VDEV_FEATURE_NS, + 0, + 0, + 0, + NUM_VRINGS, + {0, 0}, + }, + + /* Vring rsc entry - part of vdev rsc entry */ + {VDEV0_VRING_BASE, VRING_ALIGN, RL_BUFFER_COUNT, 0, 0}, + {VDEV0_VRING_BASE + VRING_SIZE, VRING_ALIGN, RL_BUFFER_COUNT, 1, 0}, +}; + +void copyResourceTable(void) +{ + /* + * Resource table should be copied to VDEV0_VRING_BASE + RESOURCE_TABLE_OFFSET. + * VDEV0_VRING_BASE is temperorily kept for backward compatibility, will be + * removed in future release + */ + memcpy((void *)VDEV0_VRING_BASE, &resources, sizeof(resources)); + memcpy((void *)(VDEV0_VRING_BASE + RESOURCE_TABLE_OFFSET), &resources, sizeof(resources)); +} diff --git a/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.h b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.h new file mode 100644 index 000000000..9562f6911 --- /dev/null +++ b/boards/evkmimx8mq/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file populates resource table for BM remote + * for use by the Linux Master */ + +#ifndef RSC_TABLE_H_ +#define RSC_TABLE_H_ + +#include +#include + +#if defined __cplusplus +extern "C" { +#endif + +#define NO_RESOURCE_ENTRIES (1) +#define RSC_VDEV_FEATURE_NS (1) /* Support name service announcement */ + +/* Resource table for the given remote */ +METAL_PACKED_BEGIN +struct remote_resource_table +{ + uint32_t version; + uint32_t num; + uint32_t reserved[2]; + uint32_t offset[NO_RESOURCE_ENTRIES]; + + /* rpmsg vdev entry for user app communication */ + struct fw_rsc_vdev user_vdev; + struct fw_rsc_vdev_vring user_vring0; + struct fw_rsc_vdev_vring user_vring1; +} METAL_PACKED_END; + +/* + * Copy resource table to shared memory base for early M4 boot case. + * In M4 early boot case, Linux kernel need to get resource table before file system gets loaded. + */ +void copyResourceTable(void); + +#if defined __cplusplus +} +#endif + +#endif /* RSC_TABLE_H_ */ diff --git a/boards/evkmimx8mq/project_template/board.c b/boards/evkmimx8mq/project_template/board.c new file mode 100644 index 000000000..eb7f36fc8 --- /dev/null +++ b/boards/evkmimx8mq/project_template/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/project_template/board.h b/boards/evkmimx8mq/project_template/board.h new file mode 100644 index 000000000..c38b6cbdb --- /dev/null +++ b/boards/evkmimx8mq/project_template/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/project_template/clock_config.c b/boards/evkmimx8mq/project_template/clock_config.c new file mode 100644 index 000000000..8f13460ee --- /dev/null +++ b/boards/evkmimx8mq/project_template/clock_config.c @@ -0,0 +1,147 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would also do configuration on the SYSTEM PLL1 to 800Mhz and SYSTEM PLL2 to 1000Mhz by U-Boot.*/ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI M4 root to 25M first in order to configure the SYSTEM PLL2. */ + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc25m); + + CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + + CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + CLOCK_EnableClock(kCLOCK_Sim_m); + CLOCK_EnableClock(kCLOCK_Sim_main); + CLOCK_EnableClock(kCLOCK_Sim_s); + CLOCK_EnableClock(kCLOCK_Sim_wakeup); + CLOCK_EnableClock(kCLOCK_Debug); + CLOCK_EnableClock(kCLOCK_Dram); + CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/project_template/clock_config.h b/boards/evkmimx8mq/project_template/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/project_template/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/project_template/peripherals.c b/boards/evkmimx8mq/project_template/peripherals.c new file mode 100644 index 000000000..69af4a74c --- /dev/null +++ b/boards/evkmimx8mq/project_template/peripherals.c @@ -0,0 +1,23 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v1.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Included files + ******************************************************************************/ +#include "peripherals.h" + +/******************************************************************************* + * BOARD_InitBootPeripherals function + ******************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ +} diff --git a/boards/evkmimx8mq/project_template/peripherals.h b/boards/evkmimx8mq/project_template/peripherals.h new file mode 100644 index 000000000..36b2e05a7 --- /dev/null +++ b/boards/evkmimx8mq/project_template/peripherals.h @@ -0,0 +1,23 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ +/******************************************************************************* + * BOARD_InitBootPeripherals function + ******************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ + +#endif /* _PERIPHERALS_H_ */ diff --git a/boards/evkmimx8mq/project_template/pin_mux.c b/boards/evkmimx8mq/project_template/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/project_template/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/project_template/pin_mux.h b/boards/evkmimx8mq/project_template/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/project_template/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/FreeRTOSConfig.h b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/FreeRTOSConfig.h new file mode 100644 index 000000000..15534d8db --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/FreeRTOSConfig.h @@ -0,0 +1,158 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#endif +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/CMakeLists.txt b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/CMakeLists.txt new file mode 100644 index 000000000..85dca1e4e --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/CMakeLists.txt @@ -0,0 +1,117 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_ecspi_loopback) + +set(MCUX_SDK_PROJECT_NAME freertos_ecspi_loopback.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_ecspi_loopback.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../../rtos/freertos + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../../devices/MIMX8MQ6/utilities + ${ProjDirPath}/../../../../../../components/uart + ${ProjDirPath}/../../../../../../components/serial_manager + ${ProjDirPath}/../../../../../../components/lists + ${ProjDirPath}/../../../../../../CMSIS/Core/Include +) + +# include modules +include(driver_clock_MIMX8MQ6) + +include(driver_ecspi_MIMX8MQ6) + +include(driver_ecspi_freertos_MIMX8MQ6) + +include(middleware_freertos-kernel_heap_4_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(utility_debug_console_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_serial_manager_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(component_serial_manager_uart_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(utility_assert_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_ecspi_loopback.bin) + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_all.bat b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_all.bat new file mode 100644 index 000000000..a6ec19ae5 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_all.sh b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_all.sh new file mode 100755 index 000000000..86624c4e1 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_all.sh @@ -0,0 +1,29 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..dcefedafe --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..3446fb757 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_release.bat b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_release.bat new file mode 100644 index 000000000..373514ef3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c16cafbd5 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_debug.bat b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_debug.sh b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_release.bat b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_release.sh b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/clean.bat b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/clean.sh b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/config.cmake b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/config.cmake new file mode 100755 index 000000000..92f07e0ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/flags.cmake b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/flags.cmake new file mode 100755 index 000000000..75eb75e9a --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/flags.cmake @@ -0,0 +1,382 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/board.c b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/board.h b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/clock_config.c b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/clock_config.h b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/empty_rsc_table.c b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/freertos_ecspi_loopback.c b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/freertos_ecspi_loopback.c new file mode 100644 index 000000000..7137da847 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/freertos_ecspi_loopback.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* FreeRTOS kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "fsl_ecspi.h" +#include "fsl_ecspi_freertos.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define ECSPI_TRANSFER_SIZE 64 +#define ECSPI_TRANSFER_BAUDRATE 500000U +#define ECSPI_MASTER_BASEADDR ECSPI1 +#define ECSPI_MASTER_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi1)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi1)) +#define ECSPI_MASTER_TRANSFER_CHANNEL kECSPI_Channel0 +#define EXAMPLE_ECSPI_MASTER_IRQN ECSPI1_IRQn + +/* Task priorities. */ +#define ecspi_task_PRIORITY (configMAX_PRIORITIES - 2) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void ecspi_task(void *pvParameters); +uint32_t masterRxData[ECSPI_TRANSFER_SIZE] = {0}; +uint32_t masterTxData[ECSPI_TRANSFER_SIZE] = {0}; +static ecspi_master_config_t masterConfig; +static ecspi_transfer_t masterXfer; +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Application entry point. + */ +int main(void) +{ + /* Init board hardware. */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + CLOCK_SetRootMux(kCLOCK_RootEcspi1, kCLOCK_EcspiRootmuxSysPll1); /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootEcspi1, 2U, 5U); /* Set root clock to 800MHZ / 10 = 80MHZ */ + /* Set IRQ priority for freertos_ecspi */ + NVIC_SetPriority(EXAMPLE_ECSPI_MASTER_IRQN, 2); + + PRINTF("\r\n***FreeRTOS ECSPI Loopback Demo***\r\n"); + PRINTF("\r\nThis demo is a loopback transfer test for ECSPI.\r\n"); + PRINTF("The ECSPI will connect the transmitter and receiver sections internally.\r\n"); + PRINTF("So, there is no need to connect the MOSI and MISO pins.\r\n"); + + if (xTaskCreate(ecspi_task, "Ecspi_task", configMINIMAL_STACK_SIZE + 100, NULL, ecspi_task_PRIORITY, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + vTaskStartScheduler(); + for (;;) + ; +} + +/*! + * @brief Task responsible for ecspi. + */ +static void ecspi_task(void *pvParameters) +{ + uint8_t i; + status_t status; + ecspi_rtos_handle_t master_rtos_handle; + + ECSPI_MasterGetDefaultConfig(&masterConfig); + + masterConfig.baudRate_Bps = ECSPI_TRANSFER_BAUDRATE; + masterConfig.enableLoopback = true; + + status = ECSPI_RTOS_Init(&master_rtos_handle, ECSPI_MASTER_BASEADDR, &masterConfig, ECSPI_MASTER_CLK_FREQ); + + if (status != kStatus_Success) + { + PRINTF("ECSPI meets error during initialization. \r\n"); + vTaskSuspend(NULL); + } + + for (i = 0; i < ECSPI_TRANSFER_SIZE; i++) + { + masterTxData[i] = i; + } + masterXfer.txData = masterTxData; + masterXfer.rxData = masterRxData; + masterXfer.dataSize = ECSPI_TRANSFER_SIZE; + masterXfer.channel = ECSPI_MASTER_TRANSFER_CHANNEL; + /*Start master transfer*/ + + status = ECSPI_RTOS_Transfer(&master_rtos_handle, &masterXfer); + if (status != kStatus_Success) + { + PRINTF("ECSPI transfer completed with error. \r\n\r\n"); + vTaskSuspend(NULL); + } + + /* Compare Tx and Rx data. */ + for (i = 0; i < ECSPI_TRANSFER_SIZE; i++) + { + if (masterTxData[i] != masterRxData[i]) + { + break; + } + } + + if (ECSPI_TRANSFER_SIZE == i) + { + PRINTF("\r\nFreeRTOS ECSPI loopback test pass!"); + } + else + { + PRINTF("\r\nFreeRTOS ECSPI loopback test fail!"); + } + + /* Deinit the ECSPI. */ + ECSPI_RTOS_Deinit(&master_rtos_handle); + vTaskSuspend(NULL); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/freertos_ecspi_loopback_v3_8.xml b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/freertos_ecspi_loopback_v3_8.xml new file mode 100644 index 000000000..a9a613110 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/freertos_ecspi_loopback_v3_8.xml @@ -0,0 +1,133 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/fsl_iomuxc.h b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/pin_mux.c b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/pin_mux.h b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/readme.txt b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/readme.txt new file mode 100644 index 000000000..b3e5398ac --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_ecspi/ecspi_loopback/readme.txt @@ -0,0 +1,51 @@ +Overview +======== +The freertos_ecspi_loopback demo shows how the ecspi do a loopback transfer internally in FreeRTOS. +The ECSPI connects the transmitter and receiver sections internally, and the data shifted out from the +most-significant bit of the shift register is looped back into the least-significant bit of the Shift register. +In this way, a self-test of the complete transmit/receive path can be made. The output pins are not affected, +and the input pins are ignored. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MCIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +If the demo run successfully, the below log will be print in the terminal window: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +***FreeRTOS ECSPI Loopback Demo*** + +This demo is a loopback transfer test for ECSPI. +The ECSPI will connect the transmitter and receiver sections internally. +So, there is no need to connect the MOSI and MISO pins. + +FreeRTOS ECSPI loopback test pass! +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/FreeRTOSConfig.h b/boards/evkmimx8mq/rtos_examples/freertos_event/FreeRTOSConfig.h new file mode 100644 index 000000000..f127dc22c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/FreeRTOSConfig.h @@ -0,0 +1,161 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#endif +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/CMakeLists.txt b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/CMakeLists.txt new file mode 100644 index 000000000..7ff0aa2b2 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/CMakeLists.txt @@ -0,0 +1,113 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_event) + +set(MCUX_SDK_PROJECT_NAME freertos_event.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_event.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../rtos/freertos + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/serial_manager + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include +) + +# include modules +include(driver_clock_MIMX8MQ6) + +include(middleware_freertos-kernel_heap_4_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(utility_debug_console_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_serial_manager_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(component_serial_manager_uart_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(utility_assert_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_event.bin) + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/build_all.bat b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/build_all.bat new file mode 100644 index 000000000..0cf4090ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD 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b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..c84d78542 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..5aa41a2df --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ 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b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/clean.bat b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/clean.sh b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/config.cmake b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/config.cmake new file mode 100755 index 000000000..92f07e0ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/flags.cmake b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/flags.cmake new file mode 100755 index 000000000..75eb75e9a --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/armgcc/flags.cmake @@ -0,0 +1,382 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/board.c b/boards/evkmimx8mq/rtos_examples/freertos_event/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/board.h b/boards/evkmimx8mq/rtos_examples/freertos_event/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/clock_config.c b/boards/evkmimx8mq/rtos_examples/freertos_event/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/clock_config.h b/boards/evkmimx8mq/rtos_examples/freertos_event/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/empty_rsc_table.c b/boards/evkmimx8mq/rtos_examples/freertos_event/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/freertos_event.c b/boards/evkmimx8mq/rtos_examples/freertos_event/freertos_event.c new file mode 100644 index 000000000..ccc63eb05 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/freertos_event.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* FreeRTOS kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define B0 (1 << 0) +#define B1 (1 << 1) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void write_task_1(void *pvParameters); +static void write_task_2(void *pvParameters); +static void read_task(void *pvParameters); +/******************************************************************************* + * Globals + ******************************************************************************/ +static EventGroupHandle_t event_group = NULL; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + event_group = xEventGroupCreate(); + if (xTaskCreate(write_task_1, "WRITE_TASK_1", configMINIMAL_STACK_SIZE + 100, NULL, tskIDLE_PRIORITY + 1, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + if (xTaskCreate(write_task_2, "WRITE_TASK_2", configMINIMAL_STACK_SIZE + 100, NULL, tskIDLE_PRIORITY + 1, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + if (xTaskCreate(read_task, "READ_TASK", configMINIMAL_STACK_SIZE + 100, NULL, tskIDLE_PRIORITY + 2, NULL) != pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + /* Start scheduling. */ + vTaskStartScheduler(); + for (;;) + ; +} + +/*! + * @brief write_task_1 function + */ +static void write_task_1(void *pvParameters) +{ + while (1) + { + xEventGroupSetBits(event_group, B0); + } +} + +/*! + * @brief write_task_2 function + */ +static void write_task_2(void *pvParameters) +{ + while (1) + { + xEventGroupSetBits(event_group, B1); + } +} + +/*! + * @brief read_task function + */ +static void read_task(void *pvParameters) +{ + EventBits_t event_bits; + while (1) + { + event_bits = xEventGroupWaitBits(event_group, /* The event group handle. */ + B0 | B1, /* The bit pattern the event group is waiting for. */ + pdTRUE, /* B0 and B1 will be cleared automatically. */ + pdFALSE, /* Don't wait for both bits, either bit unblock task. */ + portMAX_DELAY); /* Block indefinitely to wait for the condition to be met. */ + + if ((event_bits & (B0 | B1)) == (B0 | B1)) + { + PRINTF("Both bits are set."); + } + else if ((event_bits & B0) == B0) + { + PRINTF("Bit B0 is set.\r\n"); + } + else if ((event_bits & B1) == B1) + { + PRINTF("Bit B1 is set.\r\n"); + } + } +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/freertos_event_v3_8.xml b/boards/evkmimx8mq/rtos_examples/freertos_event/freertos_event_v3_8.xml new file mode 100644 index 000000000..fa0241bed --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/freertos_event_v3_8.xml @@ -0,0 +1,131 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/fsl_iomuxc.h b/boards/evkmimx8mq/rtos_examples/freertos_event/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/pin_mux.c b/boards/evkmimx8mq/rtos_examples/freertos_event/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/pin_mux.h b/boards/evkmimx8mq/rtos_examples/freertos_event/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_event/readme.txt b/boards/evkmimx8mq/rtos_examples/freertos_event/readme.txt new file mode 100644 index 000000000..3036068c9 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_event/readme.txt @@ -0,0 +1,59 @@ +Overview +======== +This document explains the freertos_event example. It shows how task waits for an event (defined set +of bits in event group). This event can be set by any other process or interrupt in the system. + +The example application creates three tasks. Two write tasks write_task_1 and write_task_2 +continuously setting event bit 0 and bit 1. + +Read_task is waiting for any event bit and printing actual state on console. Event bits are +automatically cleared after read task is entered. + +Three possible states can occurre: +Both bits are set.z +Bit B0 is set. +Bit B1 is set. + + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +After the board is flashed the Tera Term will start printing the state of event bits. + +Example output: +Bit B1 is set. +Bit B0 is set. +Bit B1 is set. +Bit B0 is set. +Bit B1 is set diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/FreeRTOSConfig.h b/boards/evkmimx8mq/rtos_examples/freertos_generic/FreeRTOSConfig.h new file mode 100644 index 000000000..400017271 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/FreeRTOSConfig.h @@ -0,0 +1,161 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#endif +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/CMakeLists.txt b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/CMakeLists.txt new file mode 100644 index 000000000..f1cd915e5 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/CMakeLists.txt @@ -0,0 +1,113 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_generic) + +set(MCUX_SDK_PROJECT_NAME freertos_generic.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_generic.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../rtos/freertos + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/serial_manager + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include +) + +# include modules +include(driver_clock_MIMX8MQ6) + +include(middleware_freertos-kernel_heap_4_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(utility_debug_console_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_serial_manager_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(component_serial_manager_uart_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(utility_assert_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_generic.bin) + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data 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b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/clean.sh b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/config.cmake b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/config.cmake new file mode 100755 index 000000000..92f07e0ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/flags.cmake b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/flags.cmake new file mode 100755 index 000000000..75eb75e9a --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/armgcc/flags.cmake @@ -0,0 +1,382 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/board.c b/boards/evkmimx8mq/rtos_examples/freertos_generic/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/board.h b/boards/evkmimx8mq/rtos_examples/freertos_generic/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/clock_config.c b/boards/evkmimx8mq/rtos_examples/freertos_generic/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/clock_config.h b/boards/evkmimx8mq/rtos_examples/freertos_generic/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/empty_rsc_table.c b/boards/evkmimx8mq/rtos_examples/freertos_generic/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/freertos_generic.c b/boards/evkmimx8mq/rtos_examples/freertos_generic/freertos_generic.c new file mode 100644 index 000000000..f96458c28 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/freertos_generic.c @@ -0,0 +1,398 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "semphr.h" + +/* TODO Add any manufacture supplied header files necessary for CMSIS functions +to be available here. */ +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Priorities at which the tasks are created. The event semaphore task is +given the maximum priority of ( configMAX_PRIORITIES - 1 ) to ensure it runs as +soon as the semaphore is given. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define mainQUEUE_SEND_TASK_PRIORITY (tskIDLE_PRIORITY + 1) +#define mainEVENT_SEMAPHORE_TASK_PRIORITY (configMAX_PRIORITIES - 1) + +/* The rate at which data is sent to the queue, specified in milliseconds, and +converted to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_PERIOD_MS (200 / portTICK_PERIOD_MS) + +/* The period of the example software timer, specified in milliseconds, and +converted to ticks using the portTICK_PERIOD_MS constant. */ +#define mainSOFTWARE_TIMER_PERIOD_MS (1000 / portTICK_PERIOD_MS) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH (1) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* + * The queue send and receive tasks as described in the comments at the top of + * this file. + */ +static void prvQueueReceiveTask(void *pvParameters); +static void prvQueueSendTask(void *pvParameters); + +/* + * The callback function assigned to the example software timer as described at + * the top of this file. + */ +static void vExampleTimerCallback(TimerHandle_t xTimer); + +/* + * The event semaphore task as described at the top of this file. + */ +static void prvEventSemaphoreTask(void *pvParameters); + +/******************************************************************************* + * Globals + ******************************************************************************/ +/* The queue used by the queue send and queue receive tasks. */ +static QueueHandle_t xQueue = NULL; + +/* The semaphore (in this case binary) that is used by the FreeRTOS tick hook + * function and the event semaphore task. + */ +static SemaphoreHandle_t xEventSemaphore = NULL; + +/* The counters used by the various examples. The usage is described in the + * comments at the top of this file. + */ +static volatile uint32_t ulCountOfTimerCallbackExecutions = 0; +static volatile uint32_t ulCountOfItemsReceivedOnQueue = 0; +static volatile uint32_t ulCountOfReceivedSemaphores = 0; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + TimerHandle_t xExampleSoftwareTimer = NULL; + + /* Init board hardware. */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + /* Create the queue used by the queue send and queue receive tasks. */ + xQueue = xQueueCreate(/* The number of items the queue can hold. */ + mainQUEUE_LENGTH, + /* The size of each item the queue holds. */ + sizeof(uint32_t)); + + /* Enable queue view in MCUX IDE FreeRTOS TAD plugin. */ + if (xQueue != NULL) + { + vQueueAddToRegistry(xQueue, "xQueue"); + } + + /* Create the semaphore used by the FreeRTOS tick hook function and the + event semaphore task. */ + vSemaphoreCreateBinary(xEventSemaphore); + + /* Create the queue receive task as described in the comments at the top + of this file. */ + if (xTaskCreate(/* The function that implements the task. */ + prvQueueReceiveTask, + /* Text name for the task, just to help debugging. */ + "Rx", + /* The size (in words) of the stack that should be created + for the task. */ + configMINIMAL_STACK_SIZE + 166, + /* A parameter that can be passed into the task. Not used + in this simple demo. */ + NULL, + /* The priority to assign to the task. tskIDLE_PRIORITY + (which is 0) is the lowest priority. configMAX_PRIORITIES - 1 + is the highest priority. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, + /* Used to obtain a handle to the created task. Not used in + this simple demo, so set to NULL. */ + NULL) != pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + + /* Create the queue send task in exactly the same way. Again, this is + described in the comments at the top of the file. */ + if (xTaskCreate(prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE + 166, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + + /* Create the task that is synchronised with an interrupt using the + xEventSemaphore semaphore. */ + if (xTaskCreate(prvEventSemaphoreTask, "Sem", configMINIMAL_STACK_SIZE + 166, NULL, + mainEVENT_SEMAPHORE_TASK_PRIORITY, NULL) != pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + + /* Create the software timer as described in the comments at the top of + this file. */ + xExampleSoftwareTimer = xTimerCreate(/* A text name, purely to help + debugging. */ + "LEDTimer", + /* The timer period, in this case + 1000ms (1s). */ + mainSOFTWARE_TIMER_PERIOD_MS, + /* This is a periodic timer, so + xAutoReload is set to pdTRUE. */ + pdTRUE, + /* The ID is not used, so can be set + to anything. */ + (void *)0, + /* The callback function that switches + the LED off. */ + vExampleTimerCallback); + + /* Start the created timer. A block time of zero is used as the timer + command queue cannot possibly be full here (this is the first timer to + be created, and it is not yet running). */ + xTimerStart(xExampleSoftwareTimer, 0); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following line + will never be reached. If the following line does execute, then there was + insufficient FreeRTOS heap memory available for the idle and/or timer tasks + to be created. See the memory management section on the FreeRTOS web site + for more details. */ + for (;;) + ; +} + +/*! + * @brief Timer callback. + */ +static void vExampleTimerCallback(TimerHandle_t xTimer) +{ + /* The timer has expired. Count the number of times this happens. The + timer that calls this function is an auto re-load timer, so it will + execute periodically. */ + ulCountOfTimerCallbackExecutions++; +} + +/*! + * @brief Task prvQueueSendTask periodically sending message. + */ +static void prvQueueSendTask(void *pvParameters) +{ + TickType_t xNextWakeTime; + const uint32_t ulValueToSend = 100UL; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for (;;) + { + /* Place this task in the blocked state until it is time to run again. + The block time is specified in ticks, the constant used converts ticks + to ms. While in the Blocked state this task will not consume any CPU + time. */ + vTaskDelayUntil(&xNextWakeTime, mainQUEUE_SEND_PERIOD_MS); + + /* Send to the queue - causing the queue receive task to unblock and + increment its counter. 0 is used as the block time so the sending + operation will not block - it shouldn't need to block as the queue + should always be empty at this point in the code. */ + xQueueSend(xQueue, &ulValueToSend, 0); + } +} + +/*! + * @brief Task prvQueueReceiveTask waiting for message. + */ +static void prvQueueReceiveTask(void *pvParameters) +{ + uint32_t ulReceivedValue; + + for (;;) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive(xQueue, &ulReceivedValue, portMAX_DELAY); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, increment the counter. */ + if (ulReceivedValue == 100UL) + { + /* Count the number of items that have been received correctly. */ + ulCountOfItemsReceivedOnQueue++; + PRINTF("Receive message counter: %d.\r\n", ulCountOfItemsReceivedOnQueue); + } + } +} + +/*! + * @brief task prvEventSemaphoreTask is waiting for semaphore. + */ +static void prvEventSemaphoreTask(void *pvParameters) +{ + for (;;) + { + /* Block until the semaphore is 'given'. */ + if (xSemaphoreTake(xEventSemaphore, portMAX_DELAY) != pdTRUE) + { + PRINTF("Failed to take semaphore.\r\n"); + } + + /* Count the number of times the semaphore is received. */ + ulCountOfReceivedSemaphores++; + + PRINTF("Event task is running.\r\n"); + } +} + +/*! + * @brief tick hook is executed every tick. + */ +void vApplicationTickHook(void) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + static uint32_t ulCount = 0; + + /* The RTOS tick hook function is enabled by setting configUSE_TICK_HOOK to + 1 in FreeRTOSConfig.h. + + "Give" the semaphore on every 500th tick interrupt. */ + ulCount++; + if (ulCount >= 500UL) + { + /* This function is called from an interrupt context (the RTOS tick + interrupt), so only ISR safe API functions can be used (those that end + in "FromISR()". + + xHigherPriorityTaskWoken was initialised to pdFALSE, and will be set to + pdTRUE by xSemaphoreGiveFromISR() if giving the semaphore unblocked a + task that has equal or higher priority than the interrupted task. */ + xSemaphoreGiveFromISR(xEventSemaphore, &xHigherPriorityTaskWoken); + ulCount = 0UL; + } + + /* If xHigherPriorityTaskWoken is pdTRUE then a context switch should + normally be performed before leaving the interrupt (because during the + execution of the interrupt a task of equal or higher priority than the + running task was unblocked). The syntax required to context switch from + an interrupt is port dependent, so check the documentation of the port you + are using. + + In this case, the function is running in the context of the tick interrupt, + which will automatically check for the higher priority task to run anyway, + so no further action is required. */ +} + +/*! + * @brief Malloc failed hook. + */ +void vApplicationMallocFailedHook(void) +{ + /* The malloc failed hook is enabled by setting + configUSE_MALLOC_FAILED_HOOK to 1 in FreeRTOSConfig.h. + + Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + for (;;) + ; +} + +/*! + * @brief Stack overflow hook. + */ +void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName) +{ + (void)pcTaskName; + (void)xTask; + + /* Run time stack overflow checking is performed if + configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. pxCurrentTCB can be + inspected in the debugger if the task name passed into this function is + corrupt. */ + for (;;) + ; +} + +/*! + * @brief Idle hook. + */ +void vApplicationIdleHook(void) +{ + volatile size_t xFreeStackSpace; + + /* The idle task hook is enabled by setting configUSE_IDLE_HOOK to 1 in + FreeRTOSConfig.h. + + This function is called on each cycle of the idle task. In this case it + does nothing useful, other than report the amount of FreeRTOS heap that + remains unallocated. */ + xFreeStackSpace = xPortGetFreeHeapSize(); + + if (xFreeStackSpace > 100) + { + /* By now, the kernel has allocated everything it is going to, so + if there is a lot of heap remaining unallocated then + the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be + reduced accordingly. */ + } +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/freertos_generic_v3_8.xml b/boards/evkmimx8mq/rtos_examples/freertos_generic/freertos_generic_v3_8.xml new file mode 100644 index 000000000..dc65190aa --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/freertos_generic_v3_8.xml @@ -0,0 +1,131 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/fsl_iomuxc.h b/boards/evkmimx8mq/rtos_examples/freertos_generic/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/pin_mux.c b/boards/evkmimx8mq/rtos_examples/freertos_generic/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/pin_mux.h b/boards/evkmimx8mq/rtos_examples/freertos_generic/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_generic/readme.txt b/boards/evkmimx8mq/rtos_examples/freertos_generic/readme.txt new file mode 100644 index 000000000..b75498356 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_generic/readme.txt @@ -0,0 +1,73 @@ +Overview +======== + +This document explains the freertos_generic example. It is based on code FreeRTOS documentation from +http://www.freertos.org/Hardware-independent-RTOS-example.html. It shows combination of several +tasks with queue, software timer, tick hook and semaphore. + +The example application creates three tasks. The prvQueueSendTask periodically sending data to +xQueue queue. The prvQueueReceiveTask is waiting for incoming message and counting number of +received messages. Task prvEventSemaphoreTask is waiting for xEventSemaphore semaphore given from +vApplicationTickHook. Tick hook give semaphore every 500 ms. + +Other hook types used for RTOS and resource statistics are also demonstrated in example: +* vApplicationIdleHook +* vApplicationStackOverflowHook +* vApplicationMallocFailedHook + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +After the board is flashed the Tera Term will start periodically printing the state of generic example. + +Example output: +Event task is running. +Receive message counter: 1. +Receive message counter: 2. +Receive message counter: 3. +Receive message counter: 4. +Receive message counter: 5. +Receive message counter: 6. +Receive message counter: 7. +Receive message counter: 8. +Receive message counter: 9. +Receive message counter: 10. +Receive message counter: 11. +Receive message counter: 12. +Event task is running. +Receive message counter: 13. +Receive message counter: 14. +... diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/FreeRTOSConfig.h b/boards/evkmimx8mq/rtos_examples/freertos_hello/FreeRTOSConfig.h new file mode 100644 index 000000000..f127dc22c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/FreeRTOSConfig.h @@ -0,0 +1,161 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#endif +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/CMakeLists.txt b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/CMakeLists.txt new file mode 100644 index 000000000..2ca15b918 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/CMakeLists.txt @@ -0,0 +1,113 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_hello) + +set(MCUX_SDK_PROJECT_NAME freertos_hello.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_hello.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../rtos/freertos + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/serial_manager + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include +) + +# include modules +include(driver_clock_MIMX8MQ6) + +include(middleware_freertos-kernel_heap_4_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(utility_debug_console_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_serial_manager_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(component_serial_manager_uart_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(utility_assert_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_hello.bin) + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_all.bat b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_all.bat new file mode 100644 index 000000000..0cf4090ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD 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b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..c84d78542 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..5aa41a2df --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ 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-DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c9e344144 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_debug.bat b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_debug.sh b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_debug.sh new file mode 100755 index 000000000..42803761b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_release.bat b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_release.sh b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/clean.bat b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/clean.sh b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/config.cmake b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/config.cmake new file mode 100755 index 000000000..92f07e0ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/flags.cmake b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/flags.cmake new file mode 100755 index 000000000..75eb75e9a --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/armgcc/flags.cmake @@ -0,0 +1,382 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/board.c b/boards/evkmimx8mq/rtos_examples/freertos_hello/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/board.h b/boards/evkmimx8mq/rtos_examples/freertos_hello/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/clock_config.c b/boards/evkmimx8mq/rtos_examples/freertos_hello/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/clock_config.h b/boards/evkmimx8mq/rtos_examples/freertos_hello/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/empty_rsc_table.c b/boards/evkmimx8mq/rtos_examples/freertos_hello/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/freertos_hello.c b/boards/evkmimx8mq/rtos_examples/freertos_hello/freertos_hello.c new file mode 100644 index 000000000..7646f317c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/freertos_hello.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* FreeRTOS kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Task priorities. */ +#define hello_task_PRIORITY (configMAX_PRIORITIES - 1) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void hello_task(void *pvParameters); + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Application entry point. + */ +int main(void) +{ + /* Init board hardware. */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + if (xTaskCreate(hello_task, "Hello_task", configMINIMAL_STACK_SIZE + 100, NULL, hello_task_PRIORITY, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + vTaskStartScheduler(); + for (;;) + ; +} + +/*! + * @brief Task responsible for printing of "Hello world." message. + */ +static void hello_task(void *pvParameters) +{ + for (;;) + { + PRINTF("Hello world.\r\n"); + vTaskSuspend(NULL); + } +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/freertos_hello_v3_8.xml b/boards/evkmimx8mq/rtos_examples/freertos_hello/freertos_hello_v3_8.xml new file mode 100644 index 000000000..f895288a8 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/freertos_hello_v3_8.xml @@ -0,0 +1,131 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/fsl_iomuxc.h b/boards/evkmimx8mq/rtos_examples/freertos_hello/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/pin_mux.c b/boards/evkmimx8mq/rtos_examples/freertos_hello/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/pin_mux.h b/boards/evkmimx8mq/rtos_examples/freertos_hello/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_hello/readme.txt b/boards/evkmimx8mq/rtos_examples/freertos_hello/readme.txt new file mode 100644 index 000000000..dfab31a7a --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_hello/readme.txt @@ -0,0 +1,50 @@ +Overview +======== +The Hello World project is a simple demonstration program that uses the SDK UART drivere in +combination with FreeRTOS. The purpose of this demo is to show how to use the debug console and to +provide a simple project for debugging and further development. + +The example application creates one task called hello_task. This task print "Hello world." message +via debug console utility and suspend itself. + + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +After the board is flashed the Tera Term will print "Hello world" message on terminal. + +Example output: +Hello world. diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/FreeRTOSConfig.h b/boards/evkmimx8mq/rtos_examples/freertos_i2c/FreeRTOSConfig.h new file mode 100644 index 000000000..f127dc22c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/FreeRTOSConfig.h @@ -0,0 +1,161 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#endif +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/CMakeLists.txt b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/CMakeLists.txt new file mode 100644 index 000000000..a4d6f8983 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/CMakeLists.txt @@ -0,0 +1,117 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_i2c) + +set(MCUX_SDK_PROJECT_NAME freertos_i2c.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_i2c.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../rtos/freertos + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/serial_manager + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include +) + +# include modules +include(driver_ii2c_MIMX8MQ6) + +include(driver_ii2c_freertos_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(middleware_freertos-kernel_heap_4_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(utility_debug_console_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_serial_manager_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(component_serial_manager_uart_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(utility_assert_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_i2c.bin) + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data 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CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/build_release.bat b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/build_release.sh b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/clean.bat b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/clean.sh b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/config.cmake b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/config.cmake new file mode 100755 index 000000000..92f07e0ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/flags.cmake b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/flags.cmake new file mode 100755 index 000000000..75eb75e9a --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/armgcc/flags.cmake @@ -0,0 +1,382 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/board.c b/boards/evkmimx8mq/rtos_examples/freertos_i2c/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/board.h b/boards/evkmimx8mq/rtos_examples/freertos_i2c/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/clock_config.c b/boards/evkmimx8mq/rtos_examples/freertos_i2c/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/clock_config.h b/boards/evkmimx8mq/rtos_examples/freertos_i2c/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/empty_rsc_table.c b/boards/evkmimx8mq/rtos_examples/freertos_i2c/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/freertos_i2c.c b/boards/evkmimx8mq/rtos_examples/freertos_i2c/freertos_i2c.c new file mode 100644 index 000000000..44125f792 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/freertos_i2c.c @@ -0,0 +1,422 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Standard C Included Files */ +#include + +/* FreeRTOS kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "semphr.h" + +/* SDK Included Files */ +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_i2c.h" +#include "fsl_i2c_freertos.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_I2C_MASTER_BASE I2C2 +#define EXAMPLE_I2C_MASTER_IRQN I2C2_IRQn +#define EXAMPLE_I2C_MASTER_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootI2c2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootI2c2)) / 5 /* SYSTEM PLL1 DIV5 */ +#define EXAMPLE_I2C_SLAVE_BASE I2C2 +#define EXAMPLE_I2C_SLAVE_IRQN I2C2_IRQn +#define EXAMPLE_I2C_SLAVE_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootI2c2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootI2c2)) / 5 /* SYSTEM PLL1 DIV5 */ +#define SINGLE_BOARD 0 +#define BOARD_TO_BOARD 1 + +#define EXAMPLE_CONNECT_I2C BOARD_TO_BOARD +#if (EXAMPLE_CONNECT_I2C == BOARD_TO_BOARD) +#define isMASTER 0 +#define isSLAVE 1 +#define I2C_MASTER_SLAVE isMASTER +#endif + +#if (EXAMPLE_CONNECT_I2C == BOARD_TO_BOARD) +#define EXAMPLE_I2C_DEALY_COUNT 1000u +#endif + +#define EXAMPLE_I2C_MASTER ((I2C_Type *)EXAMPLE_I2C_MASTER_BASE) +#define EXAMPLE_I2C_SLAVE ((I2C_Type *)EXAMPLE_I2C_SLAVE_BASE) + +#define I2C_MASTER_SLAVE_ADDR_7BIT (0x7EU) +#define I2C_BAUDRATE (100000) /* 100K */ +#define I2C_DATA_LENGTH (32) /* MAX is 256 */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint8_t g_slave_buff[I2C_DATA_LENGTH]; +uint8_t g_master_buff[I2C_DATA_LENGTH]; + +i2c_master_handle_t *g_m_handle; +i2c_slave_handle_t g_s_handle; +SemaphoreHandle_t i2c_sem; + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Task priorities. */ +#define slave_task_PRIORITY (configMAX_PRIORITIES - 1) +#define master_task_PRIORITY (configMAX_PRIORITIES - 2) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void slave_task(void *pvParameters); +#if ((I2C_MASTER_SLAVE == isMaster) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)) +static void master_task(void *pvParameters); +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +int main(void) +{ + /* Init board hardware. */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + + CLOCK_SetRootMux(kCLOCK_RootI2c2, kCLOCK_I2cRootmuxSysPll1Div5); /* Set I2C source to SysPLL1 Div5 160MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootI2c2, 1U, 4U); /* Set root clock to 160MHZ / 4 = 40MHZ */ + + NVIC_SetPriority(EXAMPLE_I2C_SLAVE_IRQN, 2); + NVIC_SetPriority(EXAMPLE_I2C_MASTER_IRQN, 3); + + PRINTF("\r\n==FreeRTOS I2C example start.==\r\n"); +#if (EXAMPLE_CONNECT_I2C == SINGLE_BOARD) + PRINTF("This example use one i2c instance as master and another as slave on one board.\r\n"); +#elif (EXAMPLE_CONNECT_I2C == BOARD_TO_BOARD) + PRINTF("This example use two boards to connect with one as master and another as slave.\r\n"); +#endif + + if (xTaskCreate(slave_task, "Slave_task", configMINIMAL_STACK_SIZE + 100, NULL, slave_task_PRIORITY, NULL) != + pdPASS) + { + PRINTF("Failed to create slave task"); + while (1) + ; + } + + vTaskStartScheduler(); + for (;;) + ; +} + +/*! + * @brief Data structure and callback function for slave I2C communication. + */ + +typedef struct _callback_message_t +{ + status_t async_status; + SemaphoreHandle_t sem; +} callback_message_t; + +#if (I2C_MASTER_SLAVE == isSLAVE) +static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) +{ + callback_message_t *cb_msg = (callback_message_t *)userData; + BaseType_t reschedule = 0; + + switch (xfer->event) + { + /* Transmit request */ + case kI2C_SlaveTransmitEvent: + /* Update information for transmit process */ + xfer->data = g_slave_buff; + xfer->dataSize = I2C_DATA_LENGTH; + break; + + /* Receive request */ + case kI2C_SlaveReceiveEvent: + /* Update information for received process */ + xfer->data = g_slave_buff; + xfer->dataSize = I2C_DATA_LENGTH; + break; + + /* Transfer done */ + case kI2C_SlaveCompletionEvent: + cb_msg->async_status = xfer->completionStatus; + xSemaphoreGiveFromISR(cb_msg->sem, &reschedule); + portYIELD_FROM_ISR(reschedule); + break; + + default: + break; + } +} +#endif + +/*! + * @brief Task responsible for slave I2C communication. + */ + +static void slave_task(void *pvParameters) +{ +#if ((I2C_MASTER_SLAVE == isSLAVE) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)) + i2c_slave_config_t slaveConfig; +#endif + + callback_message_t cb_msg = {0}; + + cb_msg.sem = xSemaphoreCreateBinary(); + if (cb_msg.sem == NULL) + { + PRINTF("I2C slave: Error creating semaphore\r\n"); + vTaskSuspend(NULL); + } + i2c_sem = cb_msg.sem; + +#if ((I2C_MASTER_SLAVE == isSLAVE) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)) + /* Set up I2C slave */ + /* + * slaveConfig.addressingMode = kI2C_Address7bit; + * slaveConfig.enableGeneralCall = false; + * slaveConfig.enableWakeUp = false; + * slaveConfig.enableBaudRateCtl = false; + * slaveConfig.enableSlave = true; + */ + I2C_SlaveGetDefaultConfig(&slaveConfig); + slaveConfig.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT; +#if defined(FSL_FEATURE_SOC_I2C_COUNT) && FSL_FEATURE_SOC_I2C_COUNT + slaveConfig.addressingMode = kI2C_Address7bit; + slaveConfig.upperAddress = 0; /* not used for this example */ + I2C_SlaveInit(EXAMPLE_I2C_SLAVE, &slaveConfig, EXAMPLE_I2C_SLAVE_CLK_FREQ); +#endif +#if defined(FSL_FEATURE_SOC_II2C_COUNT) && FSL_FEATURE_SOC_II2C_COUNT + I2C_SlaveInit(EXAMPLE_I2C_SLAVE, &slaveConfig); +#endif + for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++) + { + g_slave_buff[i] = 0; + } + + memset(&g_s_handle, 0, sizeof(g_s_handle)); + + I2C_SlaveTransferCreateHandle(EXAMPLE_I2C_SLAVE, &g_s_handle, i2c_slave_callback, &cb_msg); + I2C_SlaveTransferNonBlocking(EXAMPLE_I2C_SLAVE, &g_s_handle, kI2C_SlaveCompletionEvent); +#endif /* ((I2C_MASTER_SLAVE == isSLAVE) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)) */ + +#if ((I2C_MASTER_SLAVE == isMASTER) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)) + if (xTaskCreate(master_task, "Master_task", configMINIMAL_STACK_SIZE + 124, NULL, master_task_PRIORITY, NULL) != + pdPASS) + { + PRINTF("Failed to create master task"); + vTaskSuspend(NULL); + } +#endif /* ((I2C_MASTER_SLAVE == isMASTER) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)) */ + + /* Wait for transfer to finish */ + if (xSemaphoreTake(cb_msg.sem, portMAX_DELAY) != pdTRUE) + { + PRINTF("Failed to take semaphore.\r\n"); + } + +#if ((I2C_MASTER_SLAVE == isSLAVE) || (EXAMPLE_CONNECT_DSPI == SINGLE_BOARD)) + if (cb_msg.async_status == kStatus_Success) + { + PRINTF("I2C slave transfer completed successfully. \r\n\r\n"); + } + else + { + PRINTF("I2C slave transfer completed with error. \r\n\r\n"); + } + +#if (EXAMPLE_CONNECT_I2C == SINGLE_BOARD) + for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++) + { + if (g_slave_buff[i] != g_master_buff[i]) + { + PRINTF("\r\nError occurred in this transfer ! \r\n"); + break; + } + } +#endif + + PRINTF("Slave received data :"); + for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++) + { + if (i % 8 == 0) + { + PRINTF("\r\n"); + } + PRINTF("0x%2x ", g_slave_buff[i]); + } + PRINTF("\r\n\r\n"); + +#if (EXAMPLE_CONNECT_I2C == SINGLE_BOARD) + /* Set up slave ready to send data to master. */ + for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++) + { + g_slave_buff[i] = ~g_slave_buff[i]; + } + + PRINTF("This time , slave will send data: :"); + for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++) + { + if (i % 8 == 0) + { + PRINTF("\r\n"); + } + PRINTF("0x%2x ", g_slave_buff[i]); + } + PRINTF("\r\n\r\n"); +#endif +#endif + + /* Wait for transfer to finish */ + if (xSemaphoreTake(cb_msg.sem, portMAX_DELAY) != pdTRUE) + { + PRINTF("Failed to take semaphore.\r\n"); + } +#if (EXAMPLE_CONNECT_I2C == BOARD_TO_BOARD) + PRINTF("\r\nEnd of FreeRTOS I2C example.\r\n"); +#endif + + vTaskSuspend(NULL); +} + +#if ((I2C_MASTER_SLAVE == isMaster) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)) +static void master_task(void *pvParameters) +{ + i2c_rtos_handle_t master_rtos_handle; + i2c_master_config_t masterConfig; + i2c_master_transfer_t masterXfer; + uint32_t sourceClock; + status_t status; + + /* Set up i2c master to send data to slave */ + for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++) + { + g_master_buff[i] = i; + } + + PRINTF("Master will send data :"); + for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++) + { + if (i % 8 == 0) + { + PRINTF("\r\n"); + } + PRINTF("0x%2x ", g_master_buff[i]); + } + PRINTF("\r\n\r\n"); + + /* + * masterConfig.baudRate_Bps = 100000U; + * masterConfig.enableStopHold = false; + * masterConfig.glitchFilterWidth = 0U; + * masterConfig.enableMaster = true; + */ + I2C_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Bps = I2C_BAUDRATE; + sourceClock = EXAMPLE_I2C_MASTER_CLK_FREQ; + + status = I2C_RTOS_Init(&master_rtos_handle, EXAMPLE_I2C_MASTER, &masterConfig, sourceClock); + if (status != kStatus_Success) + { + PRINTF("I2C master: error during init, %d", status); + } + + g_m_handle = &master_rtos_handle.drv_handle; + + memset(&masterXfer, 0, sizeof(masterXfer)); + masterXfer.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT; + masterXfer.direction = kI2C_Write; + masterXfer.subaddress = 0; + masterXfer.subaddressSize = 0; + masterXfer.data = g_master_buff; + masterXfer.dataSize = I2C_DATA_LENGTH; + masterXfer.flags = kI2C_TransferDefaultFlag; + + status = I2C_RTOS_Transfer(&master_rtos_handle, &masterXfer); + if (status != kStatus_Success) + { + PRINTF("I2C master: error during write transaction, %d", status); + } +#if (EXAMPLE_CONNECT_I2C == BOARD_TO_BOARD) + /* Delay to wait slave is ready */ + SDK_DelayAtLeastUs(5000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); +#endif + /* Set up master to receive data from slave. */ + + for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++) + { + g_master_buff[i] = 0; + } + + masterXfer.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT; + masterXfer.direction = kI2C_Read; + masterXfer.subaddress = 0; + masterXfer.subaddressSize = 0; + masterXfer.data = g_master_buff; + masterXfer.dataSize = I2C_DATA_LENGTH; + masterXfer.flags = kI2C_TransferDefaultFlag; + + status = I2C_RTOS_Transfer(&master_rtos_handle, &masterXfer); + if (status != kStatus_Success) + { + PRINTF("I2C master: error during read transaction, %d", status); + } +#if (EXAMPLE_CONNECT_DSPI == BOARD_TO_BOARD) + else + { + xSemaphoreGive(i2c_sem); + } +#endif + +#if (EXAMPLE_CONNECT_I2C == SINGLE_BOARD) + /* Transfer completed. Check the data. */ + for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++) + { + if (g_slave_buff[i] != g_master_buff[i]) + { + PRINTF("\r\nError occurred in the transfer ! \r\n"); + break; + } + } +#endif + + PRINTF("Master received data :"); + for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++) + { + if (i % 8 == 0) + { + PRINTF("\r\n"); + } + PRINTF("0x%2x ", g_master_buff[i]); + } + PRINTF("\r\n\r\n"); + + PRINTF("\r\nEnd of FreeRTOS I2C example.\r\n"); + + vTaskSuspend(NULL); +} +#endif //((I2C_MASTER_SLAVE == isMaster) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)) diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/freertos_i2c_v3_8.xml b/boards/evkmimx8mq/rtos_examples/freertos_i2c/freertos_i2c_v3_8.xml new file mode 100644 index 000000000..2ec08711c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/freertos_i2c_v3_8.xml @@ -0,0 +1,133 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/fsl_iomuxc.h b/boards/evkmimx8mq/rtos_examples/freertos_i2c/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/pin_mux.c b/boards/evkmimx8mq/rtos_examples/freertos_i2c/pin_mux.c new file mode 100644 index 000000000..16c2772c3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/pin_mux.c @@ -0,0 +1,85 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v7.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.7.8 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM, DSE: OHM_45} + - {pin_num: G7, peripheral: I2C2, signal: i2c_scl, pin_signal: I2C2_SCL, LVTTL: Disabled, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM} + - {pin_num: F7, peripheral: I2C2, signal: i2c_sda, pin_signal: I2C2_SDA, LVTTL: Disabled, ODE: Enabled, SION: ENABLED, HYS: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_I2C2_SCL_I2C2_SCL, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SCL_I2C2_SCL, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_I2C2_SDA_I2C2_SDA, 1U); + IOMUXC_SetPinConfig(IOMUXC_I2C2_SDA_I2C2_SDA, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/pin_mux.h b/boards/evkmimx8mq/rtos_examples/freertos_i2c/pin_mux.h new file mode 100644 index 000000000..acba6d31c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_i2c/readme.txt b/boards/evkmimx8mq/rtos_examples/freertos_i2c/readme.txt new file mode 100644 index 000000000..b125e4256 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_i2c/readme.txt @@ -0,0 +1,194 @@ +Overview +======== +The freertos_i2c example shows an application using RTOS tasks with I2C driver: + +The example may support 2 different connections (it depends on the specific board): +On board connection and board to board connection. + +With one board connection, 2 I2C instances of the same board are used. One i2c instance used as I2C master and another I2C instance used as I2C slave . + Default settings in freertos_i2c.c (in folder boards\\rtos_examples\freertos_i2c) is applied. + Two tasks are created. One task is associated with an I2C master operation and another task deals with I2C slave operation. + 1. I2C master task sends data to I2C slave task. + 2. I2C master task reads data sent back from I2C slave task. + + The transmit data and the receive data of both I2C master task and I2C slave task are printed out on terminal. + +With board to board connection, one I2C instance on one board is used as I2C master and the I2C instance on other board is used as I2C slave. Tasks are created to run on each board to handle I2C communication. + File freertos_i2c.c should have following definitions: + #define EXAMPLE_CONNECT_I2C BOARD_TO_BOARD + For board used as I2C master: + #define I2C_MASTER_SLAVE isMASTER + For board used as I2C slave: + #define I2C_MASTER_SLAVE isSLAVE + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +Please note only board to board connection is supported, on board connection is not supported. +Transfer data from MASTER_BOARD to SLAVE_BOARD of I2C interface, I2C2 pins of MASTER_BOARD are connected with I2C2 pins of SLAVE_BOARD. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +SLAVE_BOARD CONNECTS TO MASTER_BOARD +Pin Name Board Location Pin Name Board Location +I2C2_SCL J801-1 I2C2_SCL J801-1 +I2C2_SDA J801-3 I2C2_SDA J801-3 +GND J801-2 GND J801-2 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +When the example runs successfully: +If using 1 board, you can see the similar information from the terminal as below. (Applicable to all boards except TWR-KM34Z75M) + + + +==FreeRTOS I2C example start.== + +This example use one i2c instance as master and another as slave on one board. + +Master will send data : + +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 + +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f + +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 + +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + + + +I2C slave transfer completed successfully. + + + +Slave received data : + +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 + +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f + +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 + +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + + + +This time , slave will send data: : + +0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 + +0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 + +0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 0xe8 + +0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0 + + + +Master received data : + +0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 + +0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 + +0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 0xe8 + +0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0 + + + + + +End of FreeRTOS I2C example. + + +If using 2 boards, you can see the similar information from the terminal associated with master board and slave board as below. (Applicable to all boards) + +For master: + +==FreeRTOS I2C example start.== + +This example use two boards to connect with one as master and another as slave. + +Master will send data : + +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 + +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f + +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 + +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + + + +Master received data : + +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 + +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f + +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 + +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + + + + + +End of FreeRTOS I2C example. + + +For slave: + + +==FreeRTOS I2C example start.== + +This example use two boards to connect with one as master and another as slave. + +I2C slave transfer completed successfully. + + + +Slave received data : + +0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7 + +0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f + +0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 + +0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f + + + + + +End of FreeRTOS I2C example. diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/FreeRTOSConfig.h b/boards/evkmimx8mq/rtos_examples/freertos_mutex/FreeRTOSConfig.h new file mode 100644 index 000000000..f127dc22c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/FreeRTOSConfig.h @@ -0,0 +1,161 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#endif +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/CMakeLists.txt b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/CMakeLists.txt new file mode 100644 index 000000000..31831d517 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/CMakeLists.txt @@ -0,0 +1,113 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_mutex) + +set(MCUX_SDK_PROJECT_NAME freertos_mutex.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_mutex.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../rtos/freertos + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/serial_manager + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include +) + +# include modules +include(driver_clock_MIMX8MQ6) + +include(middleware_freertos-kernel_heap_4_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(utility_debug_console_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_serial_manager_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(component_serial_manager_uart_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(utility_assert_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_mutex.bin) + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/build_all.bat b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/build_all.bat new file mode 100644 index 000000000..0cf4090ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD 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b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..c84d78542 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..5aa41a2df --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ 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b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/clean.bat b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/clean.sh b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/config.cmake b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/config.cmake new file mode 100755 index 000000000..92f07e0ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/flags.cmake b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/flags.cmake new file mode 100755 index 000000000..75eb75e9a --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/armgcc/flags.cmake @@ -0,0 +1,382 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/board.c b/boards/evkmimx8mq/rtos_examples/freertos_mutex/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/board.h b/boards/evkmimx8mq/rtos_examples/freertos_mutex/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/clock_config.c b/boards/evkmimx8mq/rtos_examples/freertos_mutex/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/clock_config.h b/boards/evkmimx8mq/rtos_examples/freertos_mutex/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/empty_rsc_table.c b/boards/evkmimx8mq/rtos_examples/freertos_mutex/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/freertos_mutex.c b/boards/evkmimx8mq/rtos_examples/freertos_mutex/freertos_mutex.c new file mode 100644 index 000000000..1aa612c9b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/freertos_mutex.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "semphr.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +SemaphoreHandle_t xMutex; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void write_task_1(void *pvParameters); +static void write_task_2(void *pvParameters); + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + xMutex = xSemaphoreCreateMutex(); + + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + if (xTaskCreate(write_task_1, "WRITE_TASK_1", configMINIMAL_STACK_SIZE + 128, NULL, tskIDLE_PRIORITY + 1, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + if (xTaskCreate(write_task_2, "WRITE_TASK_2", configMINIMAL_STACK_SIZE + 128, NULL, tskIDLE_PRIORITY + 1, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + /* Start scheduling. */ + vTaskStartScheduler(); + for (;;) + ; +} + +/*! + * @brief Write Task 1 function + */ +static void write_task_1(void *pvParameters) +{ + while (1) + { + if (xSemaphoreTake(xMutex, portMAX_DELAY) != pdTRUE) + { + PRINTF("Failed to take semaphore.\r\n"); + } + PRINTF("ABCD |"); + taskYIELD(); + PRINTF(" EFGH\r\n"); + xSemaphoreGive(xMutex); + taskYIELD(); + } +} + +/*! + * @brief Write Task 2 function + */ +static void write_task_2(void *pvParameters) +{ + while (1) + { + if (xSemaphoreTake(xMutex, portMAX_DELAY) != pdTRUE) + { + PRINTF("Failed to take semaphore.\r\n"); + } + PRINTF("1234 |"); + taskYIELD(); + PRINTF(" 5678\r\n"); + xSemaphoreGive(xMutex); + taskYIELD(); + } +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/freertos_mutex_v3_8.xml b/boards/evkmimx8mq/rtos_examples/freertos_mutex/freertos_mutex_v3_8.xml new file mode 100644 index 000000000..07129a346 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/freertos_mutex_v3_8.xml @@ -0,0 +1,131 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/fsl_iomuxc.h b/boards/evkmimx8mq/rtos_examples/freertos_mutex/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/pin_mux.c b/boards/evkmimx8mq/rtos_examples/freertos_mutex/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/pin_mux.h b/boards/evkmimx8mq/rtos_examples/freertos_mutex/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_mutex/readme.txt b/boards/evkmimx8mq/rtos_examples/freertos_mutex/readme.txt new file mode 100644 index 000000000..a003c4af6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_mutex/readme.txt @@ -0,0 +1,61 @@ +Overview +======== +This document explains the freertos_mutex example. It shows how mutex manage access to common +resource (terminal output). + +The example application creates two identical instances of write_task. Each task will lock the mutex +before printing and unlock it after printing to ensure that the outputs from tasks are not mixed +together. + +The test_task accept output message during creation as function parameter. Output message have two +parts. If xMutex is unlocked, the write_task_1 acquire xMutex and print first part of message. Then +rescheduling is performed. In this moment scheduler check if some other task could run, but second +task write_task+_2 is blocked because xMutex is already locked by first write task. The first +write_task_1 continue from last point by printing of second message part. Finaly the xMutex is +unlocked and second instance of write_task_2 is executed. + + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +After the board is flashed the Tera Term will start periodically printing strings synchronized by +mutex. + +Example output: +"ABCD | EFGH" +"1234 | 5678" +"ABCD | EFGH" +"1234 | 5678" diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/FreeRTOSConfig.h b/boards/evkmimx8mq/rtos_examples/freertos_queue/FreeRTOSConfig.h new file mode 100644 index 000000000..9c1603926 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/FreeRTOSConfig.h @@ -0,0 +1,160 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#endif +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/CMakeLists.txt b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/CMakeLists.txt new file mode 100644 index 000000000..ddba9bbe3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/CMakeLists.txt @@ -0,0 +1,113 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_queue) + +set(MCUX_SDK_PROJECT_NAME freertos_queue.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_queue.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../rtos/freertos + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/serial_manager + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include +) + +# include modules +include(driver_clock_MIMX8MQ6) + +include(middleware_freertos-kernel_heap_4_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(utility_debug_console_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_serial_manager_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(component_serial_manager_uart_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(utility_assert_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_queue.bin) + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/build_all.bat b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/build_all.bat new file mode 100644 index 000000000..0cf4090ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD 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b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..c84d78542 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..5aa41a2df --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ 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b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/clean.bat b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/clean.sh b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/config.cmake b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/config.cmake new file mode 100755 index 000000000..92f07e0ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/flags.cmake b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/flags.cmake new file mode 100755 index 000000000..75eb75e9a --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/armgcc/flags.cmake @@ -0,0 +1,382 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/board.c b/boards/evkmimx8mq/rtos_examples/freertos_queue/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/board.h b/boards/evkmimx8mq/rtos_examples/freertos_queue/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/clock_config.c b/boards/evkmimx8mq/rtos_examples/freertos_queue/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/clock_config.h b/boards/evkmimx8mq/rtos_examples/freertos_queue/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/empty_rsc_table.c b/boards/evkmimx8mq/rtos_examples/freertos_queue/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/freertos_queue.c b/boards/evkmimx8mq/rtos_examples/freertos_queue/freertos_queue.c new file mode 100644 index 000000000..ccc4db5cd --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/freertos_queue.c @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*System includes.*/ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define MAX_LOG_LENGTH 20 +/******************************************************************************* + * Globals + ******************************************************************************/ +/* Logger queue handle */ +static QueueHandle_t log_queue = NULL; +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Application API */ +static void write_task_1(void *pvParameters); +static void write_task_2(void *pvParameters); + +/* Logger API */ +void log_add(char *log); +void log_init(uint32_t queue_length, uint32_t max_log_lenght); +static void log_task(void *pvParameters); +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Main function + */ +int main(void) +{ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + /* Initialize logger for 10 logs with maximum lenght of one log 20 B */ + log_init(10, MAX_LOG_LENGTH); + if (xTaskCreate(write_task_1, "WRITE_TASK_1", configMINIMAL_STACK_SIZE + 166, NULL, tskIDLE_PRIORITY + 2, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + if (xTaskCreate(write_task_2, "WRITE_TASK_2", configMINIMAL_STACK_SIZE + 166, NULL, tskIDLE_PRIORITY + 2, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + vTaskStartScheduler(); + for (;;) + ; +} + +/******************************************************************************* + * Application functions + ******************************************************************************/ +/*! + * @brief write_task_1 function + */ +static void write_task_1(void *pvParameters) +{ + char log[MAX_LOG_LENGTH + 1]; + uint32_t i = 0; + for (i = 0; i < 5; i++) + { + sprintf(log, "Task1 Message %d", (int)i); + log_add(log); + taskYIELD(); + } + vTaskSuspend(NULL); +} + +/*! + * @brief write_task_2 function + */ +static void write_task_2(void *pvParameters) +{ + char log[MAX_LOG_LENGTH + 1]; + uint32_t i = 0; + for (i = 0; i < 5; i++) + { + sprintf(log, "Task2 Message %d", (int)i); + log_add(log); + taskYIELD(); + } + vTaskSuspend(NULL); +} + +/******************************************************************************* + * Logger functions + ******************************************************************************/ +/*! + * @brief log_add function + */ +void log_add(char *log) +{ + xQueueSend(log_queue, log, 0); +} + +/*! + * @brief log_init function + */ +void log_init(uint32_t queue_length, uint32_t max_log_lenght) +{ + log_queue = xQueueCreate(queue_length, max_log_lenght); + /* Enable queue view in MCUX IDE FreeRTOS TAD plugin. */ + if (log_queue != NULL) + { + vQueueAddToRegistry(log_queue, "LogQ"); + } + if (xTaskCreate(log_task, "log_task", configMINIMAL_STACK_SIZE + 166, NULL, tskIDLE_PRIORITY + 1, NULL) != pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } +} + +/*! + * @brief log_print_task function + */ +static void log_task(void *pvParameters) +{ + uint32_t counter = 0; + char log[MAX_LOG_LENGTH + 1]; + while (1) + { + if (xQueueReceive(log_queue, log, portMAX_DELAY) != pdTRUE) + { + PRINTF("Failed to receive queue.\r\n"); + } + PRINTF("Log %d: %s\r\n", counter, log); + counter++; + } +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/freertos_queue_v3_8.xml b/boards/evkmimx8mq/rtos_examples/freertos_queue/freertos_queue_v3_8.xml new file mode 100644 index 000000000..ac2b26b8b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/freertos_queue_v3_8.xml @@ -0,0 +1,131 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/fsl_iomuxc.h b/boards/evkmimx8mq/rtos_examples/freertos_queue/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/pin_mux.c b/boards/evkmimx8mq/rtos_examples/freertos_queue/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/pin_mux.h b/boards/evkmimx8mq/rtos_examples/freertos_queue/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_queue/readme.txt b/boards/evkmimx8mq/rtos_examples/freertos_queue/readme.txt new file mode 100644 index 000000000..8e705e752 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_queue/readme.txt @@ -0,0 +1,64 @@ +Overview +======== + +This document explains the freertos_queue example. This example introduce simple logging mechanism +based on message passing. + +Example could be devided in two parts. First part is logger. It contain three tasks: +log_add().....Add new message into the log. Call xQueueSend function to pass new message into + message queue. +log_init()....Initialize logger (create logging task and message queue log_queue). +log_task()....Task responsible for printing of log output. + +Second part is application of this simple logging mechanism. Each of two tasks write_task_1 and +write_task_2 print 5 messages into log. + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +After the board is flashed the Tera Term will show debug console output. + +Example output: +Log 0: Task1 Message 0 +Log 1: Task2 Message 0 +Log 2: Task1 Message 1 +Log 3: Task2 Message 1 +Log 4: Task1 Message 2 +Log 5: Task2 Message 2 +Log 6: Task1 Message 3 +Log 7: Task2 Message 3 +Log 8: Task1 Message 4 +Log 9: Task2 Message 4 diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/FreeRTOSConfig.h b/boards/evkmimx8mq/rtos_examples/freertos_sem/FreeRTOSConfig.h new file mode 100644 index 000000000..a83e36ec4 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/FreeRTOSConfig.h @@ -0,0 +1,161 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#endif +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/CMakeLists.txt b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/CMakeLists.txt new file mode 100644 index 000000000..f341288da --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/CMakeLists.txt @@ -0,0 +1,113 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_sem) + +set(MCUX_SDK_PROJECT_NAME freertos_sem.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_sem.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../rtos/freertos + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/serial_manager + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include +) + +# include modules +include(driver_clock_MIMX8MQ6) + +include(middleware_freertos-kernel_heap_4_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(utility_debug_console_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_serial_manager_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(component_serial_manager_uart_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(utility_assert_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_sem.bin) + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_all.bat b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_all.bat new file mode 100644 index 000000000..0cf4090ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q 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-DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_ddr_debug.bat b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..c84d78542 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..5aa41a2df --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f 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CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_release.bat b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_release.sh b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/clean.bat b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/clean.sh b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/config.cmake b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/config.cmake new file mode 100755 index 000000000..92f07e0ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/flags.cmake b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/flags.cmake new file mode 100755 index 000000000..75eb75e9a --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/armgcc/flags.cmake @@ -0,0 +1,382 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/board.c b/boards/evkmimx8mq/rtos_examples/freertos_sem/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/board.h b/boards/evkmimx8mq/rtos_examples/freertos_sem/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/clock_config.c b/boards/evkmimx8mq/rtos_examples/freertos_sem/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/clock_config.h b/boards/evkmimx8mq/rtos_examples/freertos_sem/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/empty_rsc_table.c b/boards/evkmimx8mq/rtos_examples/freertos_sem/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/freertos_sem.c b/boards/evkmimx8mq/rtos_examples/freertos_sem/freertos_sem.c new file mode 100644 index 000000000..c687f776d --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/freertos_sem.c @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "semphr.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define TASK_PRIO (configMAX_PRIORITIES - 1) +#define CONSUMER_LINE_SIZE 3 +SemaphoreHandle_t xSemaphore_producer; +SemaphoreHandle_t xSemaphore_consumer; +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void producer_task(void *pvParameters); +static void consumer_task(void *pvParameters); + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + /* Init board hardware. */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + if (xTaskCreate(producer_task, "PRODUCER_TASK", configMINIMAL_STACK_SIZE + 128, NULL, TASK_PRIO, NULL) != pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + /* Start scheduling. */ + vTaskStartScheduler(); + for (;;) + ; +} + +/*! + * @brief Task producer_task. + */ +static void producer_task(void *pvParameters) +{ + uint32_t i; + + PRINTF("Producer_task created.\r\n"); + xSemaphore_producer = xSemaphoreCreateBinary(); + if (xSemaphore_producer == NULL) + { + PRINTF("xSemaphore_producer creation failed.\r\n"); + vTaskSuspend(NULL); + } + + xSemaphore_consumer = xSemaphoreCreateBinary(); + if (xSemaphore_consumer == NULL) + { + PRINTF("xSemaphore_consumer creation failed.\r\n"); + vTaskSuspend(NULL); + } + + for (i = 0; i < CONSUMER_LINE_SIZE; i++) + { + if (xTaskCreate(consumer_task, "CONSUMER_TASK", configMINIMAL_STACK_SIZE + 128, (void *)i, TASK_PRIO, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + vTaskSuspend(NULL); + } + else + { + PRINTF("Consumer_task %d created.\r\n", i); + } + } + + while (1) + { + /* Producer is ready to provide item. */ + xSemaphoreGive(xSemaphore_consumer); + /* Producer is waiting when consumer will be ready to accept item. */ + if (xSemaphoreTake(xSemaphore_producer, portMAX_DELAY) == pdTRUE) + { + PRINTF("Producer released item.\r\n"); + } + else + { + PRINTF("Producer is waiting for customer.\r\n"); + } + } +} + +/*! + * @brief Task consumer_task. + */ +static void consumer_task(void *pvParameters) +{ + PRINTF("Consumer number: %d\r\n", pvParameters); + while (1) + { + /* Consumer is ready to accept. */ + xSemaphoreGive(xSemaphore_producer); + /* Consumer is waiting when producer will be ready to produce item. */ + if (xSemaphoreTake(xSemaphore_consumer, portMAX_DELAY) == pdTRUE) + { + PRINTF("Consumer %d accepted item.\r\n", pvParameters); + } + else + { + PRINTF("Consumer %d is waiting for producer.\r\n", pvParameters); + } + } +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/freertos_sem_v3_8.xml b/boards/evkmimx8mq/rtos_examples/freertos_sem/freertos_sem_v3_8.xml new file mode 100644 index 000000000..1284613ec --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/freertos_sem_v3_8.xml @@ -0,0 +1,131 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/fsl_iomuxc.h b/boards/evkmimx8mq/rtos_examples/freertos_sem/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/pin_mux.c b/boards/evkmimx8mq/rtos_examples/freertos_sem/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/pin_mux.h b/boards/evkmimx8mq/rtos_examples/freertos_sem/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_sem/readme.txt b/boards/evkmimx8mq/rtos_examples/freertos_sem/readme.txt new file mode 100644 index 000000000..875f82a9b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_sem/readme.txt @@ -0,0 +1,65 @@ +Overview +======== +This document explains the freertos_sem example, what to expect when running it and a brief +introduction to the API. The freertos_sem example code shows how semaphores works. Two different +tasks are synchronized in bilateral rendezvous model. + +The example uses four tasks. One producer_task and three consumer_tasks. The producer_task starts by +creating of two semaphores (xSemaphore_producer and xSemaphore_consumer). These semaphores control +access to virtual item. The synchronization is based on bilateral rendezvous pattern. Both of +consumer and producer must be prepared to enable transaction. + + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +After the board is flashed the Tera Term will show debug console output. + +Example output: +Producer_task created. +Consumer_task 0 created. +Consumer_task 1 created. +Consumer_task 2 created. +Consumer number: 0 +Consumer 0 accepted item. +Consumer number: 1 +Consumer number: 2 +Producer released item. +Consumer 0 accepted item. +Producer released item. +Consumer 1 accepted item. +Producer released item. +Consumer 2 accepted item. diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/FreeRTOSConfig.h b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/FreeRTOSConfig.h new file mode 100644 index 000000000..f127dc22c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/FreeRTOSConfig.h @@ -0,0 +1,161 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#endif +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/CMakeLists.txt b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..7ddf04297 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/CMakeLists.txt @@ -0,0 +1,113 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_swtimer) + +set(MCUX_SDK_PROJECT_NAME freertos_swtimer.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_swtimer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../rtos/freertos + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/serial_manager + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include +) + +# include modules +include(driver_clock_MIMX8MQ6) + +include(middleware_freertos-kernel_heap_4_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(utility_debug_console_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_serial_manager_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(component_serial_manager_uart_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(utility_assert_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_swtimer.bin) + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/build_all.bat b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/build_all.bat new file mode 100644 index 000000000..0cf4090ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist 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-DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/build_release.sh b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/clean.bat b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/clean.sh b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/config.cmake b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/config.cmake new file mode 100755 index 000000000..92f07e0ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/flags.cmake b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/flags.cmake new file mode 100755 index 000000000..75eb75e9a --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/armgcc/flags.cmake @@ -0,0 +1,382 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/board.c b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/board.h b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/clock_config.c b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/clock_config.h b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/empty_rsc_table.c b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/freertos_swtimer.c b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/freertos_swtimer.c new file mode 100644 index 000000000..82f3785ff --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/freertos_swtimer.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Standard includes. */ +#include +#include +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The software timer period. */ +#define SW_TIMER_PERIOD_MS (1000 / portTICK_PERIOD_MS) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* The callback function. */ +static void SwTimerCallback(TimerHandle_t xTimer); + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + TimerHandle_t SwTimerHandle = NULL; + + /* Init board hardware. */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + SystemCoreClockUpdate(); + /* Create the software timer. */ + SwTimerHandle = xTimerCreate("SwTimer", /* Text name. */ + SW_TIMER_PERIOD_MS, /* Timer period. */ + pdTRUE, /* Enable auto reload. */ + 0, /* ID is not used. */ + SwTimerCallback); /* The callback function. */ + /* Start timer. */ + xTimerStart(SwTimerHandle, 0); + /* Start scheduling. */ + vTaskStartScheduler(); + for (;;) + ; +} + +/*! + * @brief Software timer callback. + */ +static void SwTimerCallback(TimerHandle_t xTimer) +{ + PRINTF("Tick.\r\n"); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/freertos_swtimer_v3_8.xml b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/freertos_swtimer_v3_8.xml new file mode 100644 index 000000000..33e5e86f4 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/freertos_swtimer_v3_8.xml @@ -0,0 +1,131 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/fsl_iomuxc.h b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/pin_mux.c b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/pin_mux.h b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_swtimer/readme.txt b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/readme.txt new file mode 100644 index 000000000..81f9f623c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_swtimer/readme.txt @@ -0,0 +1,51 @@ +Overview +======== +This document explains the freertos_swtimer example. It shows usage of software timer and its +callback. + +The example application creates one software timer SwTimer. The timer’s callback SwTimerCallback is +periodically executed and text “Tick.†is printed to terminal. + + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +After the board is flashed the Tera Term will show output message. + +Example output: +Tick. +Tick. +Tick. diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/FreeRTOSConfig.h b/boards/evkmimx8mq/rtos_examples/freertos_tickless/FreeRTOSConfig.h new file mode 100644 index 000000000..54abef255 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/FreeRTOSConfig.h @@ -0,0 +1,162 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 2 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 +#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 1 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#endif +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/CMakeLists.txt b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/CMakeLists.txt new file mode 100644 index 000000000..076cd43d5 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/CMakeLists.txt @@ -0,0 +1,120 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_tickless) + +set(MCUX_SDK_PROJECT_NAME freertos_tickless.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../low_power_tickless/fsl_tickless_gpt.c" +"${ProjDirPath}/../low_power_tickless/fsl_tickless_gpt.h" +"${ProjDirPath}/../freertos_tickless.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. + ${ProjDirPath}/../low_power_tickless +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../rtos/freertos + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/serial_manager + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include +) + +# include modules +include(driver_gpt_MIMX8MQ6) + +include(driver_igpio_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(middleware_freertos-kernel_heap_4_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(utility_debug_console_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_serial_manager_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(component_serial_manager_uart_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(utility_assert_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_tickless.bin) + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/build_all.bat b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/build_all.bat new file mode 100644 index 000000000..0cf4090ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist 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-DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/build_release.sh b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/clean.bat b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/clean.sh b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/config.cmake b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/config.cmake new file mode 100755 index 000000000..92f07e0ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/flags.cmake b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/flags.cmake new file mode 100755 index 000000000..a1d3e4dcb --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/armgcc/flags.cmake @@ -0,0 +1,394 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -DIMX8MSCALE_SERIES \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -DIMX8MSCALE_SERIES \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \ + ${CMAKE_ASM_FLAGS_DDR_DEBUG} \ + -D__STARTUP_CLEAR_BSS \ + -DIMX8MSCALE_SERIES \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \ + ${CMAKE_ASM_FLAGS_DDR_RELEASE} \ + -D__STARTUP_CLEAR_BSS \ + -DIMX8MSCALE_SERIES \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DIMX8MSCALE_SERIES \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DIMX8MSCALE_SERIES \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_DEBUG " \ + ${CMAKE_C_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DIMX8MSCALE_SERIES \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_DDR_RELEASE " \ + ${CMAKE_C_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DIMX8MSCALE_SERIES \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DIMX8MSCALE_SERIES \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX8MQ6DVAJZ \ + -DIMX8MSCALE_SERIES \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \ + ${CMAKE_CXX_FLAGS_DDR_DEBUG} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DIMX8MSCALE_SERIES \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \ + ${CMAKE_CXX_FLAGS_DDR_RELEASE} \ + -DCPU_MIMX8MQ6DVAJZ \ + -DIMX8MSCALE_SERIES \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/board.c b/boards/evkmimx8mq/rtos_examples/freertos_tickless/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/board.h b/boards/evkmimx8mq/rtos_examples/freertos_tickless/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/clock_config.c b/boards/evkmimx8mq/rtos_examples/freertos_tickless/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/clock_config.h b/boards/evkmimx8mq/rtos_examples/freertos_tickless/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/empty_rsc_table.c b/boards/evkmimx8mq/rtos_examples/freertos_tickless/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/freertos_tickless.c b/boards/evkmimx8mq/rtos_examples/freertos_tickless/freertos_tickless.c new file mode 100644 index 000000000..922109843 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/freertos_tickless.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "semphr.h" + +#include "fsl_debug_console.h" +#include "fsl_gpio.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && (FSL_FEATURE_SOC_PORT_COUNT > 0) +#include "fsl_port.h" +#endif +#include "fsl_uart.h" +#if configUSE_TICKLESS_IDLE == 2 +#include "fsl_gpt.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Task priorities. */ +/* clang-format off */ +#define tickless_task_PRIORITY ( configMAX_PRIORITIES - 2 ) +#define SW_task_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define TIME_DELAY_SLEEP 5000 + +/* Interrupt priorities. */ +#define SW_NVIC_PRIO 2 + +/* clang-format on */ +/******************************************************************************* + * Prototypes + ******************************************************************************/ +extern void vPortGptIsr(void); +IRQn_Type vPortGetGptIrqn(void); +GPT_Type *vPortGetGptBase(void); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static void Tickless_task(void *pvParameters); +static void SW_task(void *pvParameters); + +SemaphoreHandle_t xSWSemaphore = NULL; +/******************************************************************************* + * Code + ******************************************************************************/ + +#if configUSE_TICKLESS_IDLE == 2 +/*! + * @brief Interrupt service fuction of GPT timer. + * + * This function to call low power timer ISR + */ +void GPT1_IRQHandler(void) +{ + vPortGptIsr(); +} + +/*! + * @brief Fuction of GPT timer. + * + * This function to return GPT timer base address + */ + +GPT_Type *vPortGetGptBase(void) +{ + return GPT1; +} + +/*! + * @brief Fuction of GPT timer. + * + * This function to return GPT timer interrupt number + */ + +IRQn_Type vPortGetGptIrqn(void) +{ + return GPT1_IRQn; +} +#endif +/*! + * @brief Main function + */ +int main(void) +{ +/* Define the init structure for the input switch pin */ +#ifdef BOARD_SW_NAME + gpio_pin_config_t sw_config = { + kGPIO_DigitalInput, + 0, +#if defined(FSL_FEATURE_SOC_IGPIO_COUNT) && (FSL_FEATURE_SOC_IGPIO_COUNT > 0) + kGPIO_IntRisingEdge, +#endif + }; +#endif +#if configUSE_TICKLESS_IDLE == 2 + gpt_config_t gptConfig; +#endif + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); +#if configUSE_TICKLESS_IDLE == 2 + CLOCK_SetRootMux(kCLOCK_RootGpt1, kCLOCK_GptRootmuxSysPll1Div20); /* Set GPT1 source to SysPLL1 Div20 40MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootGpt1, 1U, 5U); /* Set root clock to 40MHZ / 5 = 8MHZ */ + GPT_GetDefaultConfig(&gptConfig); + + /* Initialize GPT module */ + GPT_Init(GPT1, &gptConfig); + + /* Divide GPT clock source frequency by 1 inside GPT module */ + GPT_SetClockDivider(GPT1, 1); + + /* Enable GPT Output Compare1 interrupt */ + GPT_EnableInterrupts(GPT1, kGPT_OutputCompare1InterruptEnable); + + /* Enable at the Interrupt */ + EnableIRQ(GPT1_IRQn); +#endif + + PRINTF("Press any key to start the example\r\n"); + GETCHAR(); + + /* Print a note to terminal. */ + PRINTF("Tickless Demo example\r\n"); +#ifdef BOARD_SW_NAME + PRINTF("Press or turn on %s to wake up the CPU\r\n", BOARD_SW_NAME); + +/* Init input switch GPIO. */ +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && (FSL_FEATURE_SOC_PORT_COUNT > 0) + PORT_SetPinInterruptConfig(BOARD_SW_PORT, BOARD_SW_GPIO_PIN, kPORT_InterruptFallingEdge); +#endif + +#if defined(__CORTEX_M) + NVIC_SetPriority(BOARD_SW_IRQ, SW_NVIC_PRIO); +#else + GIC_SetPriority(BOARD_SW_IRQ, BOARD_SW_GIC_PRIO); +#endif + + EnableIRQ(BOARD_SW_IRQ); + GPIO_PinInit(BOARD_SW_GPIO, BOARD_SW_GPIO_PIN, &sw_config); +#if defined(FSL_FEATURE_SOC_IGPIO_COUNT) && (FSL_FEATURE_SOC_IGPIO_COUNT > 0) + GPIO_PortClearInterruptFlags(BOARD_SW_GPIO, 1U << BOARD_SW_GPIO_PIN); + GPIO_PortEnableInterrupts(BOARD_SW_GPIO, 1U << BOARD_SW_GPIO_PIN); +#endif +#endif + + /*Create tickless task*/ + if (xTaskCreate(Tickless_task, "Tickless_task", configMINIMAL_STACK_SIZE + 100, NULL, tickless_task_PRIORITY, + NULL) != pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + if (xTaskCreate(SW_task, "Switch_task", configMINIMAL_STACK_SIZE + 100, NULL, SW_task_PRIORITY, NULL) != pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + PRINTF("\r\nTick count :\r\n"); + /*Task Scheduler*/ + vTaskStartScheduler(); + for (;;) + ; +} + +/* Tickless Task */ +static void Tickless_task(void *pvParameters) +{ + for (;;) + { + PRINTF("%d\r\n", xTaskGetTickCount()); + vTaskDelay(TIME_DELAY_SLEEP); + } +} + +/* Switch Task */ +static void SW_task(void *pvParameters) +{ + xSWSemaphore = xSemaphoreCreateBinary(); + for (;;) + { + if (xSemaphoreTake(xSWSemaphore, portMAX_DELAY) == pdTRUE) + { + PRINTF("CPU woken up by external interrupt\r\n"); + } + } +} +/*! + * @brief Interrupt service fuction of switch. + * + * This function to wake up CPU + */ +#ifdef BOARD_SW_NAME +void BOARD_SW_IRQ_HANDLER(void) +{ + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + +/* Clear external interrupt flag. */ +#ifdef BOARD_SW_DELAY + volatile uint32_t i = 0; + for (i = 0; i < 10000000; ++i) + { + __NOP(); /* delay */ + } + GPIO_PortClearInterruptFlags(BOARD_SW_GPIO, 1U << BOARD_SW_GPIO_PIN); + if (1 == GPIO_PinRead(BOARD_SW_GPIO, BOARD_SW_GPIO_PIN)) + { + xSemaphoreGiveFromISR(xSWSemaphore, &xHigherPriorityTaskWoken); + } +#else + GPIO_PortClearInterruptFlags(BOARD_SW_GPIO, 1U << BOARD_SW_GPIO_PIN); + xSemaphoreGiveFromISR(xSWSemaphore, &xHigherPriorityTaskWoken); +#endif +} +#endif diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/freertos_tickless_v3_8.xml b/boards/evkmimx8mq/rtos_examples/freertos_tickless/freertos_tickless_v3_8.xml new file mode 100644 index 000000000..4fab60c05 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/freertos_tickless_v3_8.xml @@ -0,0 +1,141 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/fsl_iomuxc.h b/boards/evkmimx8mq/rtos_examples/freertos_tickless/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/low_power_tickless/fsl_tickless_gpt.c b/boards/evkmimx8mq/rtos_examples/freertos_tickless/low_power_tickless/fsl_tickless_gpt.c new file mode 100644 index 000000000..2b779d5bc --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/low_power_tickless/fsl_tickless_gpt.c @@ -0,0 +1,219 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* Compiler includes. */ +#if defined(__ICCARM__) +#include +#endif + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if configUSE_TICKLESS_IDLE == 2 +#include "fsl_gpt.h" +#else +#include "fsl_device_registers.h" +#endif + +#include "fsl_tickless_gpt.h" + +extern uint32_t SystemCoreClock; /* in Kinetis SDK, this contains the system core clock speed */ + +/* + * GPT timer base address and interrupt number + */ + +#if configUSE_TICKLESS_IDLE == 2 +extern GPT_Type *vPortGetGptBase(void); +extern IRQn_Type vPortGetGptIrqn(void); +#endif /* configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +/* + * The number of SysTick increments that make up one tick period. + */ +#if configUSE_TICKLESS_IDLE == 2 +static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if configUSE_TICKLESS_IDLE == 2 +static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The number of GPT increments that make up one tick period. + */ +#if configUSE_TICKLESS_IDLE == 2 +static uint32_t ulLPTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The flag of GPT is occurs or not. + */ +#if configUSE_TICKLESS_IDLE == 2 +static volatile bool ulLPTimerInterruptFired = false; +#endif /* configUSE_TICKLESS_IDLE */ + +#if configUSE_TICKLESS_IDLE == 2 +void vPortGptIsr(void) +{ + ulLPTimerInterruptFired = true; + /* Clear interrupt flag.*/ + GPT_ClearStatusFlags(GPT1, kGPT_OutputCompare1Flag); +} + +void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) +{ + uint32_t ulReloadValue, ulCompleteTickPeriods; + TickType_t xModifiableIdleTime; + GPT_Type *pxGptBase; + + pxGptBase = vPortGetGptBase(); + if (pxGptBase == 0) + return; + /* Make sure the SysTick reload value does not overflow the counter. */ + if (xExpectedIdleTime > xMaximumPossibleSuppressedTicks) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + if (xExpectedIdleTime == 0) + return; + + /* Calculate the reload value required to wait xExpectedIdleTime + tick periods. -1 is used because this code will execute part way + through one of the tick periods. */ + ulReloadValue = (ulLPTimerCountsForOneTick * (xExpectedIdleTime - 1UL)); + + /* Stop the GPT and systick momentarily. The time the GPT and systick is stopped for + is accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + GPT_StopTimer(pxGptBase); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + method as that will mask interrupts that should exit sleep mode. */ + __disable_irq(); + __DSB(); + __ISB(); + + /* If a context switch is pending or a task is waiting for the scheduler + to be unsuspended then abandon the low power entry. */ + if (eTaskConfirmSleepModeStatus() == eAbortSleep) + { + /* Restart from whatever is left in the count register to complete + this tick period. */ + SysTick->LOAD = SysTick->VAL; + + /* Restart SysTick. */ + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + + /* Reset the reload register to the value required for normal tick + periods. */ + SysTick->LOAD = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_irq() + call above. */ + __enable_irq(); + } + else + { + /* Set the new reload value. */ + GPT_SetOutputCompareValue(pxGptBase, kGPT_OutputCompare_Channel1, ulReloadValue); + + /* Enable GPT. */ + GPT_StartTimer(pxGptBase); + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + set its parameter to 0 to indicate that its implementation contains + its own wait for interrupt or wait for event instruction, and so wfi + should not be executed again. However, the original expected idle + time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING(xModifiableIdleTime); + if (xModifiableIdleTime > 0) + { + __DSB(); + __WFI(); + __ISB(); + } + configPOST_SLEEP_PROCESSING(xExpectedIdleTime); + + ulLPTimerInterruptFired = false; + + /* Re-enable interrupts - see comments above __disable_irq() + call above. */ + __enable_irq(); + __NOP(); + if (ulLPTimerInterruptFired) + { + /* The tick interrupt handler will already have pended the tick + processing in the kernel. As the pending tick will be + processed as soon as this function exits, the tick value + maintained by the tick is stepped forward by one less than the + time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + ulLPTimerInterruptFired = false; + } + else + { + /* Something other than the tick interrupt ended the sleep. + Work out how long the sleep lasted rounded to complete tick + periods (not the ulReload value which accounted for part + ticks). */ + ulCompleteTickPeriods = (GPT_GetCurrentTimerCount(pxGptBase)) / ulLPTimerCountsForOneTick; + } + + /* Stop GPT when CPU waked up then set SysTick->LOAD back to its standard + value. The critical section is used to ensure the tick interrupt + can only execute once in the case that the reload register is near + zero. */ + GPT_StopTimer(pxGptBase); + portENTER_CRITICAL(); + { + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + vTaskStepTick(ulCompleteTickPeriods); + SysTick->LOAD = ulTimerCountsForOneTick - 1UL; + } + portEXIT_CRITICAL(); + } +} + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void vPortSetupTimerInterrupt(void) +{ + /* Calculate the constants required to configure the tick interrupt. */ + ulTimerCountsForOneTick = (configCPU_CLOCK_HZ / configTICK_RATE_HZ); + ulLPTimerCountsForOneTick = (configGPT_CLOCK_HZ / configTICK_RATE_HZ); + if (ulLPTimerCountsForOneTick != 0) + { + xMaximumPossibleSuppressedTicks = portMAX_32_BIT_NUMBER / ulLPTimerCountsForOneTick; + } + else + { + /* ulLPTimerCountsForOneTick is zero, not allowed state */ + while (1) + ; + } + NVIC_EnableIRQ(vPortGetGptIrqn()); + + /* Configure SysTick to interrupt at the requested rate. */ + SysTick->LOAD = (configCPU_CLOCK_HZ / configTICK_RATE_HZ) - 1UL; + SysTick->VAL = 0UL; + SysTick->CTRL = (SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk); +} +#endif /* #if configUSE_TICKLESS_IDLE */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/low_power_tickless/fsl_tickless_gpt.h b/boards/evkmimx8mq/rtos_examples/freertos_tickless/low_power_tickless/fsl_tickless_gpt.h new file mode 100644 index 000000000..25ddc7e83 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/low_power_tickless/fsl_tickless_gpt.h @@ -0,0 +1,27 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_TICKLESS_GPT_H +#define FSL_TICKLESS_GPT_H + +#include "fsl_clock.h" + +#if defined(MIMXRT1176_cm7_SERIES) || defined(MIMXRT1176_cm4_SERIES) || defined(MIMXRT1166_cm7_SERIES) || \ + defined(MIMXRT1166_cm4_SERIES) +#define configGPT_CLOCK_HZ (CLOCK_GetFreq(kCLOCK_OscRc48MDiv2)) +#elif defined(IMX8MSCALE_SERIES) +#define configGPT_CLOCK_HZ \ + (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootGpt1)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootGpt1)) / 20) +#else +#define configGPT_CLOCK_HZ (CLOCK_GetFreq(kCLOCK_IpgClk) / 2) +#endif +/* The GPT is a 32-bit counter. */ +#define portMAX_32_BIT_NUMBER (0xffffffffUL) + +#endif /* FSL_TICKLESS_GPT_H */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/pin_mux.c b/boards/evkmimx8mq/rtos_examples/freertos_tickless/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/pin_mux.h b/boards/evkmimx8mq/rtos_examples/freertos_tickless/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_tickless/readme.txt b/boards/evkmimx8mq/rtos_examples/freertos_tickless/readme.txt new file mode 100644 index 000000000..8b0511b98 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_tickless/readme.txt @@ -0,0 +1,70 @@ +Overview +======== +This document explains the freertos_tickless example. It shows how the CPU enters the sleep mode and then +it is woken up either by expired time delay using low power timer module or by external interrupt caused by a +user defined button. + + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +After flashing the example to the board the console will start printing the number of tick count periodically +when the CPU is running. +To wake up the CPU by external interrupt, press the button, that is specified at the beginning of the +example (SWx where x is the number of the user defined button). When the button is pressed, the console prints +out the "CPU woken up by external interrupt" message. + +Example output: + +Press any key to start the example +Tickless Demo example +Press or turn on SWx to wake up the CPU + +Tick count : +0 +5000 +10000 +CPU woken up by external interrupt +15000 +20000 +25000 + +Explanation of the example +The example application prints the actual tick count number every time after the specified +delay. When the vTaskDelay() is called, the CPU enters the sleep mode for that defined period +of time. + +While the CPU is in sleep mode and the user defined button is pressed, the CPU is woken up +by the external interrupt and continues to sleep after the interrupt is handled. +The period of time delay is not changed after the external interrupt occurs. diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/FreeRTOSConfig.h b/boards/evkmimx8mq/rtos_examples/freertos_uart/FreeRTOSConfig.h new file mode 100644 index 000000000..f127dc22c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/FreeRTOSConfig.h @@ -0,0 +1,161 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(20 * 1024)) +#endif +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/CMakeLists.txt b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/CMakeLists.txt new file mode 100644 index 000000000..8670728e1 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/CMakeLists.txt @@ -0,0 +1,115 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_uart) + +set(MCUX_SDK_PROJECT_NAME freertos_uart.elf) + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_uart.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +"${ProjDirPath}/../fsl_iomuxc.h" +"${ProjDirPath}/../empty_rsc_table.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/drivers + ${ProjDirPath}/../../../../../rtos/freertos + ${ProjDirPath}/../../../../../devices/MIMX8MQ6 + ${ProjDirPath}/../../../../../devices/MIMX8MQ6/utilities + ${ProjDirPath}/../../../../../components/uart + ${ProjDirPath}/../../../../../components/serial_manager + ${ProjDirPath}/../../../../../components/lists + ${ProjDirPath}/../../../../../CMSIS/Core/Include +) + +# include modules +include(driver_iuart_MIMX8MQ6) + +include(driver_iuart_freertos_MIMX8MQ6) + +include(driver_clock_MIMX8MQ6) + +include(middleware_freertos-kernel_heap_4_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + +include(driver_rdc_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + +include(utility_debug_console_MIMX8MQ6) + +include(component_iuart_adapter_MIMX8MQ6) + +include(component_serial_manager_MIMX8MQ6) + +include(component_lists_MIMX8MQ6) + +include(component_serial_manager_uart_MIMX8MQ6) + +include(device_MIMX8MQ6_startup_MIMX8MQ6) + +include(utility_assert_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + +include(utilities_misc_utilities_MIMX8MQ6) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + +include(device_MIMX8MQ6_system_MIMX8MQ6) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_uart.bin) + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_all.bat b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_all.bat new file mode 100644 index 000000000..0cf4090ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_all.bat @@ -0,0 +1,29 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s 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b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_ddr_debug.bat new file mode 100644 index 000000000..c84d78542 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_ddr_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_ddr_debug.sh b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_ddr_debug.sh new file mode 100755 index 000000000..5aa41a2df --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_ddr_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f 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-DCMAKE_BUILD_TYPE=ddr_release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_ddr_release.sh b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_ddr_release.sh new file mode 100755 index 000000000..c9e344144 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_ddr_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_debug.bat b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e 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CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_release.bat b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_release.sh b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/clean.bat b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/clean.bat new file mode 100644 index 000000000..bb038c720 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release ddr_debug ddr_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/clean.sh b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/clean.sh new file mode 100755 index 000000000..8ae553026 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release ddr_debug ddr_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/config.cmake b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/config.cmake new file mode 100755 index 000000000..92f07e0ae --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX8MQ6 true) +set(CONFIG_USE_driver_iuart_MIMX8MQ6 true) diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/armgcc/flags.cmake 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-DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m4 \ + -Wall \ + -Wno-address-of-packed-member \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \ + -g \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \ + -mcpu=cortex-m4 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wl,--print-memory-usage \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld -static \ +") diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/board.c b/boards/evkmimx8mq/rtos_examples/freertos_uart/board.c new file mode 100644 index 000000000..85b8f9a92 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + uint8_t domainId = 0U; + + domainId = RDC_GetCurrentMasterDomainId(RDC); + /* Only configure the RDC if RDC peripheral write access allowed. */ + if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) + { + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + } + + /* + * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM. + * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at + * domain 0. + */ + CLOCK_EnableClock(kCLOCK_Iomux); + + CLOCK_EnableClock(kCLOCK_Ipmux1); + CLOCK_EnableClock(kCLOCK_Ipmux2); + CLOCK_EnableClock(kCLOCK_Ipmux3); + CLOCK_EnableClock(kCLOCK_Ipmux4); + + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/board.h b/boards/evkmimx8mq/rtos_examples/freertos_uart/board.h new file mode 100644 index 000000000..f28f8a8d6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/board.h @@ -0,0 +1,50 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +/* Shared memory base for RPMsg communication. */ +#define VDEV0_VRING_BASE (0xB8000000U) +#define RESOURCE_TABLE_OFFSET (0xFF000) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/clock_config.c b/boards/evkmimx8mq/rtos_examples/freertos_uart/clock_config.c new file mode 100644 index 000000000..2cce38da9 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/clock_config.c @@ -0,0 +1,161 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, + .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot. + * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make + * the SOC hang. + */ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + // CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI root to 25M first in order to configure the SYSTEM PLL2. */ + // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + + // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + // + // CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + // CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + // CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/clock_config.h b/boards/evkmimx8mq/rtos_examples/freertos_uart/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/empty_rsc_table.c b/boards/evkmimx8mq/rtos_examples/freertos_uart/empty_rsc_table.c new file mode 100644 index 000000000..37bb8dc0b --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/empty_rsc_table.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, Mentor Graphics Corporation + * All rights reserved. + * Copyright (c) 2015 Xilinx, Inc. All rights reserved. + * Copyright 2020 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * This file provides the default empty resource table data structure + * placed in the .resource_table section of the ELF file. This facilitates + * basic support of remoteproc firmware loading from the Linux kernel. + * + * The .resource_table section has to be present in the ELF file in order + * for the remoteproc ELF parser to accept the binary. + * + * See other multicore examples such as those utilizing rpmsg for a examples + * of non-empty resource table. + * + */ + +#include + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif + +const uint32_t resource_table[] = { + /* Version */ + 1, + + /* Number of table entries - resource table empty */ + 0, + + /* reserved fields */ + 0, 0}; diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/freertos_uart.c b/boards/evkmimx8mq/rtos_examples/freertos_uart/freertos_uart.c new file mode 100644 index 000000000..09f5ed9e2 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/freertos_uart.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* FreeRTOS kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +#include "fsl_uart_freertos.h" +#include "fsl_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_UART UART2 +#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ +#define DEMO_IRQn UART2_IRQn +/* Task priorities. */ +#define uart_task_PRIORITY (configMAX_PRIORITIES - 1) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void uart_task(void *pvParameters); + +/******************************************************************************* + * Variables + ******************************************************************************/ +char *to_send = "FreeRTOS UART driver example!\r\n"; +char *send_ring_overrun = "\r\nRing buffer overrun!\r\n"; +char *send_hardware_overrun = "\r\nHardware buffer overrun!\r\n"; +uint8_t background_buffer[32]; +uint8_t recv_buffer[4]; + +uart_rtos_handle_t handle; +struct _uart_handle t_handle; + +uart_rtos_config_t uart_config = { + .baudrate = 115200, + .parity = kUART_ParityDisabled, + .stopbits = kUART_OneStopBit, + .buffer = background_buffer, + .buffer_size = sizeof(background_buffer), +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Application entry point. + */ +int main(void) +{ + /* Init board hardware. */ + /* Board specific RDC settings */ + BOARD_RdcInit(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + BOARD_InitMemory(); + NVIC_SetPriority(DEMO_IRQn, 3); + if (xTaskCreate(uart_task, "Uart_task", configMINIMAL_STACK_SIZE + 100, NULL, uart_task_PRIORITY, NULL) != pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + vTaskStartScheduler(); + for (;;) + ; +} + +/*! + * @brief Task responsible for loopback. + */ +static void uart_task(void *pvParameters) +{ + int error; + size_t n = 0; + + uart_config.srcclk = DEMO_UART_CLK_FREQ; + uart_config.base = DEMO_UART; + + if (kStatus_Success != UART_RTOS_Init(&handle, &t_handle, &uart_config)) + { + vTaskSuspend(NULL); + } + + /* Send introduction message. */ + if (kStatus_Success != UART_RTOS_Send(&handle, (uint8_t *)to_send, strlen(to_send))) + { + vTaskSuspend(NULL); + } + + /* Receive user input and send it back to terminal. */ + do + { + error = UART_RTOS_Receive(&handle, recv_buffer, sizeof(recv_buffer), &n); + if (error == kStatus_UART_RxHardwareOverrun) + { + /* Notify about hardware buffer overrun */ + if (kStatus_Success != + UART_RTOS_Send(&handle, (uint8_t *)send_hardware_overrun, strlen(send_hardware_overrun))) + { + vTaskSuspend(NULL); + } + } + if (error == kStatus_UART_RxRingBufferOverrun) + { + /* Notify about ring buffer overrun */ + if (kStatus_Success != UART_RTOS_Send(&handle, (uint8_t *)send_ring_overrun, strlen(send_ring_overrun))) + { + vTaskSuspend(NULL); + } + } + if (n > 0) + { + /* send back the received data */ + UART_RTOS_Send(&handle, recv_buffer, n); + } + } while (kStatus_Success == error); + + UART_RTOS_Deinit(&handle); + vTaskSuspend(NULL); +} diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/freertos_uart_v3_8.xml b/boards/evkmimx8mq/rtos_examples/freertos_uart/freertos_uart_v3_8.xml new file mode 100644 index 000000000..f81866fac --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/freertos_uart_v3_8.xml @@ -0,0 +1,132 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/fsl_iomuxc.h b/boards/evkmimx8mq/rtos_examples/freertos_uart/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/pin_mux.c b/boards/evkmimx8mq/rtos_examples/freertos_uart/pin_mux.c new file mode 100644 index 000000000..b9d9d6184 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/pin_mux.c @@ -0,0 +1,71 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMX8MQ6xxxJZ +package_id: MIMX8MQ6DVAJZ +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: m4} +- pin_list: + - {pin_num: B6, peripheral: UART2, signal: uart_rx, pin_signal: UART2_RXD, PUE: Enabled, SRE: MEDIUM} + - {pin_num: D6, peripheral: UART2, signal: uart_tx, pin_signal: UART2_TXD, PUE: Enabled, SRE: MEDIUM} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */ + IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U); + IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SRE(1U) | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/pin_mux.h b/boards/evkmimx8mq/rtos_examples/freertos_uart/pin_mux.h new file mode 100644 index 000000000..148f03bf6 --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/pin_mux.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/evkmimx8mq/rtos_examples/freertos_uart/readme.txt b/boards/evkmimx8mq/rtos_examples/freertos_uart/readme.txt new file mode 100644 index 000000000..8803a9a1d --- /dev/null +++ b/boards/evkmimx8mq/rtos_examples/freertos_uart/readme.txt @@ -0,0 +1,43 @@ +Overview +======== +The UART example for FreeRTOS demonstrates the possibility to use the UART driver in the RTOS. +The example uses single instance of UART IP and writes string into, then reads back chars. +After every 4B received, these are sent back on UART. + +Toolchain supported +=================== +- IAR embedded Workbench 9.10.2 +- GCC ARM Embedded 10.2.1 + +Hardware requirements +===================== +- Micro USB cable +- MIMX8MQ6-EVK board +- J-Link Debug Probe +- 12V power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect 12V power supply and J-Link Debug Probe to the board, switch SW701 to power on the board +2. Connect a USB cable between the host PC and the J1701 USB port on the target board. +3. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Download the program to the target board. +5. Launch the debugger in your IDE to begin running the demo. + +Running the demo +================ +You will see the welcome string printed out on the console. +You can send characters to the console back and they will be printed out onto console in a group of 4 characters. + diff --git a/components/button/fsl_component_button.c b/components/button/fsl_component_button.c new file mode 100644 index 000000000..77c35ac37 --- /dev/null +++ b/components/button/fsl_component_button.c @@ -0,0 +1,569 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_adapter_gpio.h" +#include "fsl_component_timer_manager.h" + +#include "fsl_component_button.h" +/* + * The OSA_USED macro can only be defined when the OSA component is used. + * If the source code of the OSA component does not exist, the OSA_USED cannot be defined. + * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED + * also cannot be defined. + * The source code path of the OSA component is /components/osa. + * + */ +#if defined(OSA_USED) +#include "fsl_os_abstraction.h" +#if (defined(BUTTON_USE_COMMON_TASK) && (BUTTON_USE_COMMON_TASK > 0U)) +#include "fsl_component_common_task.h" +#endif +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#if defined(OSA_USED) +#include "fsl_os_abstraction.h" +#if (defined(USE_RTOS) && (USE_RTOS > 0U)) +#define BUTTON_SR_ALLOC() OSA_SR_ALLOC() +#define BUTTON_ENTER_CRITICAL() OSA_ENTER_CRITICAL(); +#define BUTTON_EXIT_CRITICAL() OSA_EXIT_CRITICAL() +#else +#define BUTTON_SR_ALLOC() +#define BUTTON_ENTER_CRITICAL() +#define BUTTON_EXIT_CRITICAL() +#endif +#else +#define BUTTON_SR_ALLOC() uint32_t buttonPrimask; +#define BUTTON_ENTER_CRITICAL() buttonPrimask = DisableGlobalIRQ(); +#define BUTTON_EXIT_CRITICAL() EnableGlobalIRQ(buttonPrimask); +#endif + +typedef enum _button_press_status +{ + kStatus_BUTTON_PressIdle = 0U, /*!< Idle */ + kStatus_BUTTON_Pressed = 1U, /*!< Pressed */ + kStatus_BUTTON_PressDoubleStart = 2U, /*!< Start double click */ + kStatus_BUTTON_PressDoublePressed = 3U, /*!< Second press for double click */ +} button_press_status_t; + +typedef struct _button_state +{ + struct _button_state *next; + button_callback_t callback; + void *callbackParam; + GPIO_HANDLE_DEFINE(gpioHandle); + volatile uint32_t pushPeriodCount; + volatile uint32_t pushPeriodCountLast; + uint8_t pinStateDefault; + uint8_t port; + uint8_t pin; + struct + { + volatile uint8_t pressed : 3U; + volatile uint8_t msg : 5U; + } state; +} button_state_t; + +typedef struct _button_list +{ + volatile uint32_t periodCount; + TIMER_MANAGER_HANDLE_DEFINE(timerHandle); +#if defined(OSA_USED) + +#if (defined(BUTTON_USE_COMMON_TASK) && (BUTTON_USE_COMMON_TASK > 0U)) + common_task_message_t commonTaskMsg; +#else + OSA_EVENT_HANDLE_DEFINE(eventHandle); + OSA_TASK_HANDLE_DEFINE(taskHandle); +#endif + +#endif + button_state_t *button; + volatile uint8_t timerOpenedNesting; + volatile uint8_t activeButtonCount; +} button_list_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void BUTTON_Task(void *param); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +static button_list_t s_buttonList; + +#if defined(OSA_USED) +#if (defined(BUTTON_USE_COMMON_TASK) && (BUTTON_USE_COMMON_TASK > 0U)) +#else +/* + * \brief Defines the button task's stack + */ +static OSA_TASK_DEFINE(BUTTON_Task, BUTTON_TASK_PRIORITY, 1, BUTTON_TASK_STACK_SIZE, false); +#endif +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BUTTON_NotificationUpdate(button_state_t *buttonState, button_event_t event) +{ + buttonState->state.pressed = (uint8_t)kStatus_BUTTON_PressIdle; + buttonState->state.msg = (uint8_t)event; +#if defined(OSA_USED) + +#if (defined(BUTTON_USE_COMMON_TASK) && (BUTTON_USE_COMMON_TASK > 0U)) + s_buttonList.commonTaskMsg.callback = BUTTON_Task; + s_buttonList.commonTaskMsg.callbackParam = buttonState; + (void)COMMON_TASK_post_message(&s_buttonList.commonTaskMsg); +#else + (void)OSA_EventSet((osa_event_handle_t)s_buttonList.eventHandle, BUTTON_EVENT_BUTTON); +#endif + +#else + BUTTON_Task(&s_buttonList); +#endif +} + +static void BUTTON_Event(void *param) +{ + button_state_t *buttonState = (button_state_t *)param; + uint8_t pinState = 0U; + + assert(param); + + (void)HAL_GpioGetInput(buttonState->gpioHandle, &pinState); + pinState = (0U != pinState) ? 1U : 0U; + if (((uint8_t)kStatus_BUTTON_PressIdle == buttonState->state.pressed) || + ((uint8_t)kStatus_BUTTON_PressDoubleStart == buttonState->state.pressed)) + { + if (buttonState->pinStateDefault != pinState) + { + buttonState->state.pressed++; + buttonState->pushPeriodCount = s_buttonList.periodCount; + + /* Start timer for interval scan button state. */ + if (0U == s_buttonList.activeButtonCount) + { + (void)TM_Start(s_buttonList.timerHandle, (uint8_t)kTimerModeIntervalTimer, BUTTON_TIMER_INTERVAL); + } + s_buttonList.activeButtonCount++; + } + } + else + { + if (buttonState->pinStateDefault == pinState) + { + if ((BUTTON_DOUBLE_CLICK_THRESHOLD + buttonState->pushPeriodCountLast) >= buttonState->pushPeriodCount) + { + if ((s_buttonList.periodCount - buttonState->pushPeriodCount) < BUTTON_SHORT_PRESS_THRESHOLD) + { +#if (defined(BUTTON_EVENT_DOUBLECLICK_ENABLE) && BUTTON_EVENT_DOUBLECLICK_ENABLE > 0U) + BUTTON_NotificationUpdate(buttonState, kBUTTON_EventDoubleClick); +#endif /* BUTTON_EVENT_DOUBLECLICK_ENABLE */ + } + else + { + BUTTON_NotificationUpdate(buttonState, kBUTTON_EventError); + } + } + else + { + if ((s_buttonList.periodCount - buttonState->pushPeriodCount) < BUTTON_SHORT_PRESS_THRESHOLD) + { + buttonState->pushPeriodCountLast = s_buttonList.periodCount; + buttonState->state.pressed = (uint8_t)kStatus_BUTTON_PressDoubleStart; + } +#if (defined(BUTTON_EVENT_SHORTPRESS_ENABLE) && BUTTON_EVENT_SHORTPRESS_ENABLE > 0U) + else if ((s_buttonList.periodCount - buttonState->pushPeriodCount) < BUTTON_LONG_PRESS_THRESHOLD) + { + BUTTON_NotificationUpdate(buttonState, kBUTTON_EventShortPress); + } +#endif /* BUTTON_EVENT_SHORTPRESS_ENABLE */ +#if (defined(BUTTON_EVENT_LONGPRESS_ENABLE) && BUTTON_EVENT_LONGPRESS_ENABLE > 0U) + else + { + BUTTON_NotificationUpdate(buttonState, kBUTTON_EventLongPress); + } +#else + else + { + BUTTON_NotificationUpdate(buttonState, kBUTTON_EventError); + } +#endif /* BUTTON_EVENT_LONGPRESS_ENABLE */ + } + } + } +} + +static void BUTTON_Task(void *param) +{ +#if defined(OSA_USED) + +#if (defined(BUTTON_USE_COMMON_TASK) && (BUTTON_USE_COMMON_TASK > 0U)) +#else + osa_event_flags_t ev = 0; + + do + { + if (KOSA_StatusSuccess == + OSA_EventWait((osa_event_handle_t)s_buttonList.eventHandle, osaEventFlagsAll_c, 0U, osaWaitForever_c, &ev)) + { +#endif + +#endif + button_state_t *buttonState = s_buttonList.button; + BUTTON_SR_ALLOC(); + + BUTTON_ENTER_CRITICAL(); + while (NULL != buttonState) + { + if (0U != buttonState->state.msg) + { + button_callback_message_t msg; + BUTTON_EXIT_CRITICAL(); + msg.event = (button_event_t)buttonState->state.msg; + (void)buttonState->callback(buttonState, &msg, buttonState->callbackParam); + buttonState->state.msg = 0U; + BUTTON_ENTER_CRITICAL(); + + /* Stop timer for efficiency */ + s_buttonList.activeButtonCount--; + if (0U == s_buttonList.activeButtonCount) + { + (void)TM_Stop(s_buttonList.timerHandle); + } + } + buttonState = buttonState->next; + } + BUTTON_EXIT_CRITICAL(); +#if defined(OSA_USED) + +#if (defined(BUTTON_USE_COMMON_TASK) && (BUTTON_USE_COMMON_TASK > 0U)) +#else + } + } while (0U != gUseRtos_c); +#endif + +#endif +} + +static void BUTTON_TimerEvent(void *param) +{ +#if (defined(BUTTON_EVENT_ONECLICK_ENABLE) && BUTTON_EVENT_ONECLICK_ENABLE > 0U) + button_state_t *buttonState; + BUTTON_SR_ALLOC(); +#endif /* BUTTON_EVENT_ONECLICK_ENABLE */ + + s_buttonList.periodCount += BUTTON_TIMER_INTERVAL; + +#if (defined(BUTTON_EVENT_ONECLICK_ENABLE) && BUTTON_EVENT_ONECLICK_ENABLE > 0U) + BUTTON_ENTER_CRITICAL(); + buttonState = s_buttonList.button; + while (NULL != buttonState) + { + /* + * The code block is used to indentify the button event is one click or double click. + * If the flag pending is set and the button is not pressed, check the user activity is timeout or not. + * If is times out, notify the upper layer it is kBUTTON_EventOneClick. + * Otherwise, check the status next time. + */ + if ((uint8_t)kStatus_BUTTON_PressDoubleStart == buttonState->state.pressed) + { + if ((BUTTON_DOUBLE_CLICK_THRESHOLD + buttonState->pushPeriodCountLast) < s_buttonList.periodCount) + { + BUTTON_NotificationUpdate(buttonState, kBUTTON_EventOneClick); + buttonState->pushPeriodCountLast = 0U; + } + } + buttonState = buttonState->next; + } + BUTTON_EXIT_CRITICAL(); +#endif /* BUTTON_EVENT_ONECLICK_ENABLE */ +} + +static void BUTTON_OpenTimer(void) +{ + BUTTON_SR_ALLOC(); + uint8_t initTimer = 0U; + + BUTTON_ENTER_CRITICAL(); + initTimer = (uint8_t)(!(bool)s_buttonList.timerOpenedNesting); + s_buttonList.timerOpenedNesting++; + BUTTON_EXIT_CRITICAL(); + + if (0U != initTimer) + { + timer_status_t timerStatus; + timerStatus = TM_Open((timer_handle_t)s_buttonList.timerHandle); + assert(kStatus_TimerSuccess == timerStatus); + + timerStatus = TM_InstallCallback(s_buttonList.timerHandle, BUTTON_TimerEvent, &s_buttonList); + assert(kStatus_TimerSuccess == timerStatus); + + (void)timerStatus; + } +} + +static void BUTTON_CloseTimer(void) +{ + BUTTON_SR_ALLOC(); + uint8_t deinitTimer = 0U; + + BUTTON_ENTER_CRITICAL(); + if (s_buttonList.timerOpenedNesting > 0U) + { + s_buttonList.timerOpenedNesting--; + deinitTimer = (uint8_t)(!(bool)s_buttonList.timerOpenedNesting); + } + BUTTON_EXIT_CRITICAL(); + + if (0U != deinitTimer) + { + timer_status_t timerStatus; + timerStatus = TM_Close((timer_handle_t)s_buttonList.timerHandle); + assert(kStatus_TimerSuccess == timerStatus); + (void)timerStatus; + } +} + +button_status_t BUTTON_Init(button_handle_t buttonHandle, button_config_t *buttonConfig) +{ + button_state_t *buttonState; + hal_gpio_status_t gpioStatus; + BUTTON_SR_ALLOC(); + + assert((NULL != buttonHandle) && (NULL != buttonConfig)); + assert(BUTTON_HANDLE_SIZE >= sizeof(button_state_t)); + + buttonState = (button_state_t *)buttonHandle; + + (void)memset(buttonHandle, 0, sizeof(button_state_t)); + + BUTTON_ENTER_CRITICAL(); + BUTTON_OpenTimer(); + if (NULL == s_buttonList.button) + { +#if defined(OSA_USED) + +#if (defined(BUTTON_USE_COMMON_TASK) && (BUTTON_USE_COMMON_TASK > 0U)) + (void)COMMON_TASK_init(); +#else + osa_status_t osaStatus; + + osaStatus = OSA_EventCreate((osa_event_handle_t)s_buttonList.eventHandle, 1U); + assert(KOSA_StatusSuccess == osaStatus); + + osaStatus = OSA_TaskCreate((osa_task_handle_t)s_buttonList.taskHandle, OSA_TASK(BUTTON_Task), &s_buttonList); + assert(KOSA_StatusSuccess == osaStatus); + (void)osaStatus; +#endif + +#endif + } + else + { + buttonState->next = s_buttonList.button; + } + s_buttonList.button = buttonState; + /* Timer only works when button have activities, so s_buttonList.periodCount would be 0 for the first press and + double click check case will be triggered. So we need set a start time for prevent this situation, a start time + bigger than BUTTON_DOUBLE_CLICK_THRESHOLD is works. */ + s_buttonList.periodCount = BUTTON_DOUBLE_CLICK_THRESHOLD + BUTTON_TIMER_INTERVAL; + BUTTON_EXIT_CRITICAL(); + + (void)memcpy(&buttonState->pinStateDefault, &buttonConfig->gpio.pinStateDefault, 3U); + gpioStatus = HAL_GpioInit(buttonState->gpioHandle, (hal_gpio_pin_config_t *)((void *)buttonConfig)); + + assert(kStatus_HAL_GpioSuccess == gpioStatus); + + gpioStatus = HAL_GpioSetTriggerMode(buttonState->gpioHandle, kHAL_GpioInterruptEitherEdge); + assert(kStatus_HAL_GpioSuccess == gpioStatus); + (void)gpioStatus; + + return kStatus_BUTTON_Success; +} + +button_status_t BUTTON_InstallCallback(button_handle_t buttonHandle, button_callback_t callback, void *callbackParam) +{ + button_state_t *buttonState; + assert(buttonHandle); + + buttonState = (button_state_t *)buttonHandle; + + buttonState->callback = callback; + buttonState->callbackParam = callbackParam; + + (void)HAL_GpioInstallCallback(buttonState->gpioHandle, BUTTON_Event, buttonState); + + return kStatus_BUTTON_Success; +} + +button_status_t BUTTON_Deinit(button_handle_t buttonHandle) +{ + button_state_t *buttonState; + button_state_t *buttonStatePre; + BUTTON_SR_ALLOC(); + + assert(buttonHandle); + + buttonState = (button_state_t *)buttonHandle; + + BUTTON_ENTER_CRITICAL(); + buttonStatePre = s_buttonList.button; + if (buttonStatePre != buttonState) + { + while ((NULL != buttonStatePre) && (buttonStatePre->next != buttonState)) + { + buttonStatePre = buttonStatePre->next; + } + if (NULL != buttonStatePre) + { + buttonStatePre->next = buttonState->next; + } + } + else + { + s_buttonList.button = buttonState->next; + } + + if (NULL == s_buttonList.button) + { +#if defined(OSA_USED) + +#if (defined(BUTTON_USE_COMMON_TASK) && (BUTTON_USE_COMMON_TASK > 0U)) + +#else + (void)OSA_TaskDestroy((osa_task_handle_t)s_buttonList.taskHandle); + (void)OSA_EventDestroy((osa_event_handle_t)s_buttonList.eventHandle); +#endif + +#endif + } + BUTTON_CloseTimer(); + BUTTON_EXIT_CRITICAL(); + + (void)HAL_GpioDeinit(buttonState->gpioHandle); + + return kStatus_BUTTON_Success; +} + +button_status_t BUTTON_GetInput(button_handle_t buttonHandle, uint8_t *pinState) +{ + button_state_t *buttonState; + + assert(buttonHandle); + + buttonState = (button_state_t *)buttonHandle; + + (void)HAL_GpioGetInput(buttonState->gpioHandle, pinState); + + return kStatus_BUTTON_Success; +} + +button_status_t BUTTON_WakeUpSetting(button_handle_t buttonHandle, uint8_t enable) +{ + button_state_t *buttonState; + hal_gpio_status_t status; + + assert(buttonHandle); + + buttonState = (button_state_t *)buttonHandle; + + status = HAL_GpioWakeUpSetting(buttonState->gpioHandle, enable); + + if (kStatus_HAL_GpioSuccess == status) + { + return kStatus_BUTTON_Success; + } + return kStatus_BUTTON_Error; +} + +button_status_t BUTTON_EnterLowpower(button_handle_t buttonHandle) +{ + button_state_t *buttonState; + hal_gpio_status_t status; + /* MISRA C-2012 Rule 11.6 */ + uint32_t *pLowpowerHandle = BUTTON_ALL_ENTER_EXIT_LOWPOWER_HANDLE; + + assert(buttonHandle); + + if ((button_handle_t)pLowpowerHandle != buttonHandle) + { + buttonState = (button_state_t *)buttonHandle; + } + else + { + buttonState = s_buttonList.button; + } + + while (NULL != buttonState) + { + status = HAL_GpioEnterLowpower(buttonState->gpioHandle); + + assert(kStatus_HAL_GpioSuccess == status); + (void)status; + + BUTTON_CloseTimer(); + + if ((button_handle_t)pLowpowerHandle != buttonHandle) + { + break; + } + + buttonState = buttonState->next; + } + + return kStatus_BUTTON_Success; +} + +button_status_t BUTTON_ExitLowpower(button_handle_t buttonHandle) +{ + button_state_t *buttonState; + hal_gpio_status_t status; + /* MISRA C-2012 Rule 11.6 */ + uint32_t *pLowpowerHandle = BUTTON_ALL_ENTER_EXIT_LOWPOWER_HANDLE; + + assert(buttonHandle); + + if ((button_handle_t)pLowpowerHandle != buttonHandle) + { + buttonState = (button_state_t *)buttonHandle; + } + else + { + buttonState = s_buttonList.button; + } + + while (NULL != buttonState) + { + status = HAL_GpioExitLowpower(buttonState->gpioHandle); + + assert(kStatus_HAL_GpioSuccess == status); + (void)status; + + BUTTON_OpenTimer(); + + BUTTON_Event(buttonState); + + if ((button_handle_t)pLowpowerHandle != buttonHandle) + { + break; + } + + buttonState = buttonState->next; + } + + return kStatus_BUTTON_Success; +} diff --git a/components/button/fsl_component_button.h b/components/button/fsl_component_button.h new file mode 100644 index 000000000..b63b47567 --- /dev/null +++ b/components/button/fsl_component_button.h @@ -0,0 +1,314 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __BUTTON_H__ +#define __BUTTON_H__ + +#include "fsl_common.h" +#if (defined(COMMON_TASK_ENABLE) && (COMMON_TASK_ENABLE == 0U)) +#include "fsl_component_common_task.h" +#endif /* COMMON_TASK_ENABLE */ +#include "fsl_adapter_gpio.h" +/*! + * @addtogroup Button + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Definition of feature 'one click' enable macro. */ +#ifndef BUTTON_EVENT_ONECLICK_ENABLE +#define BUTTON_EVENT_ONECLICK_ENABLE (1) +#endif +/*! @brief Definition of feature 'double click' enable macro. */ +#ifndef BUTTON_EVENT_DOUBLECLICK_ENABLE +#define BUTTON_EVENT_DOUBLECLICK_ENABLE (1) +#endif +/*! @brief Definition of feature 'short press' enable macro. */ +#ifndef BUTTON_EVENT_SHORTPRESS_ENABLE +#define BUTTON_EVENT_SHORTPRESS_ENABLE (1) +#endif +/*! @brief Definition of feature 'long press' enable macro. */ +#ifndef BUTTON_EVENT_LONGPRESS_ENABLE +#define BUTTON_EVENT_LONGPRESS_ENABLE (1) +#endif + +/*! @brief Definition of all buttons enter/exit lowpower handle macro. */ +#define BUTTON_ALL_ENTER_EXIT_LOWPOWER_HANDLE ((uint32_t *)0xffffffffU) /* MISRA C-2012 Rule 11.6 */ + +/*! @brief Definition of button handle size as HAL_GPIO_HANDLE_SIZE + button dedicated size. */ +#define BUTTON_HANDLE_SIZE (16U + 24U) + +/*! @brief The handle of button */ +typedef void *button_handle_t; + +/*! + * @brief Defines the button handle + * + * This macro is used to define a 4 byte aligned button handle. + * Then use "(button_handle_t)name" to get the button handle. + * + * The macro should be global and could be optional. You could also define button handle by yourself. + * + * This is an example, + * @code + * BUTTON_HANDLE_DEFINE(buttonHandle); + * @endcode + * + * @param name The name string of the button handle. + */ +#define BUTTON_HANDLE_DEFINE(name) uint32_t name[((BUTTON_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] + +/*! + * @brief Defines the button handle array + * + * This macro is used to define a 4 byte aligned button handle array. + * Then use "(button_handle_t)name[0]" to get the first button handle. + * + * The macro should be global and could be optional. You could also define these button handle by yourself. + * + * This is an example, + * @code + * BUTTON_HANDLE_DEFINE(buttonHandleArray, 1); + * @endcode + * + * @param name The name string of the button handle array. + * @param count The amount of button handle. + */ +#define BUTTON_HANDLE_ARRAY_DEFINE(name, count) \ + uint32_t name[count][((BUTTON_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] + +/*! @brief Definition of button timer interval,unit is ms. */ +#define BUTTON_TIMER_INTERVAL (25U) + +/*! @brief Definition of button short press threshold,unit is ms. */ +#define BUTTON_SHORT_PRESS_THRESHOLD (200U) + +/*! @brief Definition of button long press threshold,unit is ms. */ +#define BUTTON_LONG_PRESS_THRESHOLD (500U) + +/*! @brief Definition of button double click threshold,unit is ms. */ +#define BUTTON_DOUBLE_CLICK_THRESHOLD (200U) + +/*! @brief Definition to determine whether use common task. */ +#ifndef BUTTON_USE_COMMON_TASK +#define BUTTON_USE_COMMON_TASK (0U) +#if (defined(COMMON_TASK_ENABLE) && (COMMON_TASK_ENABLE == 0U)) +#undef BUTTON_USE_COMMON_TASK +#define BUTTON_USE_COMMON_TASK (0U) +#endif +#endif + +/*! @brief Definition of button task priority. */ +#ifndef BUTTON_TASK_PRIORITY +#define BUTTON_TASK_PRIORITY (2U) +#endif + +/*! @brief Definition of button task stack size. */ +#ifndef BUTTON_TASK_STACK_SIZE +#define BUTTON_TASK_STACK_SIZE (1000U) +#endif + +/*! @brief Definition of button event. */ +#define BUTTON_EVENT_BUTTON (1U) + +/*! @brief The status type of button */ +typedef enum _button_status +{ + kStatus_BUTTON_Success = kStatus_Success, /*!< Success */ + kStatus_BUTTON_Error = MAKE_STATUS(kStatusGroup_BUTTON, 1), /*!< Failed */ + kStatus_BUTTON_LackSource = MAKE_STATUS(kStatusGroup_BUTTON, 2), /*!< Lack of sources */ +} button_status_t; + +/*! @brief The event type of button */ +typedef enum _button_event +{ + kBUTTON_EventOneClick = 0x01U, /*!< One click with short time, the duration of key down and key up is less than + #BUTTON_SHORT_PRESS_THRESHOLD. */ + kBUTTON_EventDoubleClick, /*!< Double click with short time, the duration of key down and key up is less than + #BUTTON_SHORT_PRESS_THRESHOLD. And the duration of the two button actions does not + exceed #BUTTON_DOUBLE_CLICK_THRESHOLD. */ + kBUTTON_EventShortPress, /*!< Press with short time, the duration of key down and key up is no less than + #BUTTON_SHORT_PRESS_THRESHOLD and less than #BUTTON_LONG_PRESS_THRESHOLD. */ + kBUTTON_EventLongPress, /*!< Press with long time, the duration of key down and key up is no less than + #BUTTON_LONG_PRESS_THRESHOLD. */ + kBUTTON_EventError, /*!< Error event if the button actions cannot be identified. */ +} button_event_t; + +/*! @brief The callback message struct of button */ +typedef struct _button_callback_message_struct +{ + button_event_t event; +} button_callback_message_t; + +/*! @brief The callback function of button */ +typedef button_status_t (*button_callback_t)(void *buttonHandle, + button_callback_message_t *message, + void *callbackParam); + +/*! @brief The button gpio config structure */ +typedef struct _button_gpio_config +{ + hal_gpio_direction_t direction; /*!< GPIO Pin direction (0 - In, 1 - Out)*/ + uint8_t pinStateDefault; /*!< GPIO Pin voltage when button is not pressed (0 - low level, 1 - high level)*/ + uint8_t port; /*!< GPIO Port */ + uint8_t pin; /*!< GPIO Pin */ +} button_gpio_config_t; + +/*! @brief The button config structure */ +typedef struct _button_config +{ + button_gpio_config_t gpio; +} button_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes a button with the button handle and the user configuration structure. + * + * This function configures the button with user-defined settings. The user can configure the configuration + * structure. The parameter buttonHandle is a pointer to point to a memory space of size #BUTTON_HANDLE_SIZE allocated + * by the caller. + * + * Example below shows how to use this API to configure the button. + * For one button, + * @code + * static BUTTON_HANDLE_DEFINE(s_buttonHandle); + * button_config_t buttonConfig; + * buttonConfig.gpio.port = 0; + * buttonConfig.gpio.pin = 1; + * buttonConfig.gpio.pinStateDefault = 0; + * BUTTON_Init((button_handle_t)s_buttonHandle, &buttonConfig); + * @endcode + * For multiple buttons, + * @code + * static BUTTON_HANDLE_ARRAY_DEFINE(s_buttonArrayHandle, count); + * button_config_t buttonArrayConfig[count]; + * for(uint8_t i = 0U; i < count; i++) + * { + * buttonArrayConfig[i].gpio.port = 0; + * buttonArrayConfig[i].gpio.pin = 1; + * buttonArrayConfig[i].gpio.pinStateDefault = 0; + * BUTTON_Init((button_handle_t)s_buttonArrayHandle[i], &buttonArrayConfig[i]); + * } + * @endcode + * + * @param buttonHandle Pointer to point to a memory space of size #BUTTON_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define one handle in the following two ways: + * #BUTTON_HANDLE_DEFINE(buttonHandle); + * or + * uint32_t buttonHandle[((BUTTON_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * You can define multiple handles in the following way: + * #BUTTON_HANDLE_ARRAY_DEFINE(buttonHandleArray, count); + * @param buttonConfig Pointer to user-defined configuration structure. + * @return Indicates whether initialization was successful or not. + * @retval kStatus_BUTTON_Error An error occurred. + * @retval kStatus_BUTTON_Success Button initialization succeed. + */ +button_status_t BUTTON_Init(button_handle_t buttonHandle, button_config_t *buttonConfig); + +/*! @}*/ + +/*! + * @name Install callback + * @{ + */ + +/*! + * @brief Installs a callback and callback parameter. + * + * This function is used to install the callback and callback parameter for button module. + * Once the button is pressed, the button driver will identify the behavior and notify the + * upper layer with the button event by the installed callback function. Currently, the Button + * supports the three types of event, click, double click and long press. Detail information refer + * to #button_event_t. + * + * @param buttonHandle Button handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @return Indicates whether callback install was successful or not. + * @retval kStatus_BUTTON_Success Successfully install the callback. + */ +button_status_t BUTTON_InstallCallback(button_handle_t buttonHandle, button_callback_t callback, void *callbackParam); + +/*! @}*/ + +/*! + * @brief Deinitializes a button instance. + * + * This function deinitializes the button instance. + * + * @param buttonHandle button handle pointer. + * @retval kStatus_BUTTON_Success button de-initialization succeed. + */ +button_status_t BUTTON_Deinit(button_handle_t buttonHandle); + +/*! + * @brief Get button pin input. + * + * This function is used for get the button pin input. + * + * @param buttonHandle button handle pointer. + * @param pinState a pointer to save the pin state. + * @retval kStatus_BUTTON_Error An error occurred. + * @retval kStatus_BUTTON_Success Set successfully. + */ +button_status_t BUTTON_GetInput(button_handle_t buttonHandle, uint8_t *pinState); + +/*! + * @brief Enables or disables the button wake-up feature. + * + * This function enables or disables the button wake-up feature. + * + * @param buttonHandle button handle pointer. + * @param enable enable or disable (0 - disable, 1 - enable). + * @retval kStatus_BUTTON_Error An error occurred. + * @retval kStatus_BUTTON_Success Set successfully. + */ +button_status_t BUTTON_WakeUpSetting(button_handle_t buttonHandle, uint8_t enable); + +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @param buttonHandle button handle pointer. + * @retval kStatus_BUTTON_Success Successful operation. + */ +button_status_t BUTTON_EnterLowpower(button_handle_t buttonHandle); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @param buttonHandle button handle pointer. + * @retval kStatus_BUTTON_Success Successful operation. + */ +button_status_t BUTTON_ExitLowpower(button_handle_t buttonHandle); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* __BUTTON_H__ */ diff --git a/components/codec/component_wm8524_adapter_MIMX8MQ6.cmake b/components/codec/component_wm8524_adapter_MIMX8MQ6.cmake new file mode 100644 index 000000000..b67311f2d --- /dev/null +++ b/components/codec/component_wm8524_adapter_MIMX8MQ6.cmake @@ -0,0 +1,18 @@ +include_guard(GLOBAL) +message("component_wm8524_adapter component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/port/wm8524/fsl_codec_wm8524_adapter.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/port/wm8524 + ${CMAKE_CURRENT_LIST_DIR}/port +) + + +include(driver_wm8524_MIMX8MQ6) + +include(driver_codec_MIMX8MQ6) + diff --git a/components/codec/driver_codec_MIMX8MQ6.cmake b/components/codec/driver_codec_MIMX8MQ6.cmake new file mode 100644 index 000000000..d397c2994 --- /dev/null +++ b/components/codec/driver_codec_MIMX8MQ6.cmake @@ -0,0 +1,54 @@ +include_guard(GLOBAL) +message("driver_codec component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_codec_common.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +#OR Logic component +if(CONFIG_USE_component_wm8904_adapter_MIMX8MQ6) + include(component_wm8904_adapter_MIMX8MQ6) +endif() +if(CONFIG_USE_component_wm8960_adapter_MIMX8MQ6) + include(component_wm8960_adapter_MIMX8MQ6) +endif() +if(CONFIG_USE_component_wm8524_adapter_MIMX8MQ6) + include(component_wm8524_adapter_MIMX8MQ6) +endif() +if(CONFIG_USE_component_sgtl_adapter_MIMX8MQ6) + include(component_sgtl_adapter_MIMX8MQ6) +endif() +if(CONFIG_USE_component_da7212_adapter_MIMX8MQ6) + include(component_da7212_adapter_MIMX8MQ6) +endif() +if(CONFIG_USE_component_ak4497_adapter_MIMX8MQ6) + include(component_ak4497_adapter_MIMX8MQ6) +endif() +if(CONFIG_USE_component_tfa9xxx_adapter_MIMX8MQ6) + include(component_tfa9xxx_adapter_MIMX8MQ6) +endif() +if(CONFIG_USE_component_tfa9896_adapter_MIMX8MQ6) + include(component_tfa9896_adapter_MIMX8MQ6) +endif() +if(CONFIG_USE_component_cs42888_adapter_MIMX8MQ6) + include(component_cs42888_adapter_MIMX8MQ6) +endif() +if(CONFIG_USE_component_cs42448_adapter_MIMX8MQ6) + include(component_cs42448_adapter_MIMX8MQ6) +endif() +if(CONFIG_USE_component_codec_adapters_MIMX8MQ6) + include(component_codec_adapters_MIMX8MQ6) +endif() +if(NOT (CONFIG_USE_component_wm8904_adapter_MIMX8MQ6 OR CONFIG_USE_component_wm8960_adapter_MIMX8MQ6 OR CONFIG_USE_component_wm8524_adapter_MIMX8MQ6 OR CONFIG_USE_component_sgtl_adapter_MIMX8MQ6 OR CONFIG_USE_component_da7212_adapter_MIMX8MQ6 OR CONFIG_USE_component_ak4497_adapter_MIMX8MQ6 OR CONFIG_USE_component_tfa9xxx_adapter_MIMX8MQ6 OR CONFIG_USE_component_tfa9896_adapter_MIMX8MQ6 OR CONFIG_USE_component_cs42888_adapter_MIMX8MQ6 OR CONFIG_USE_component_cs42448_adapter_MIMX8MQ6 OR CONFIG_USE_component_codec_adapters_MIMX8MQ6)) + message(WARNING "Since component_wm8904_adapter_MIMX8MQ6/component_wm8960_adapter_MIMX8MQ6/component_wm8524_adapter_MIMX8MQ6/component_sgtl_adapter_MIMX8MQ6/component_da7212_adapter_MIMX8MQ6/component_ak4497_adapter_MIMX8MQ6/component_tfa9xxx_adapter_MIMX8MQ6/component_tfa9896_adapter_MIMX8MQ6/component_cs42888_adapter_MIMX8MQ6/component_cs42448_adapter_MIMX8MQ6/component_codec_adapters_MIMX8MQ6 is not included at first or config in config.cmake file, use component_wm8904_adapter_MIMX8MQ6 by default.") + include(component_wm8904_adapter_MIMX8MQ6) +endif() + +include(driver_common_MIMX8MQ6) + diff --git a/components/codec/port/wm8524/fsl_codec_wm8524_adapter.c b/components/codec/port/wm8524/fsl_codec_wm8524_adapter.c new file mode 100644 index 000000000..33503a9ff --- /dev/null +++ b/components/codec/port/wm8524/fsl_codec_wm8524_adapter.c @@ -0,0 +1,178 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_codec_wm8524_adapter.h" +#include "fsl_codec_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +static const codec_capability_t s_wm8524_capability; +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Codec initilization. + * + * param handle codec handle. + * param config codec configuration. + * return kStatus_Success is success, else initial failed. + */ +status_t HAL_CODEC_WM8524_Init(void *handle, void *config) +{ + assert((config != NULL) && (handle != NULL)); + + codec_config_t *codecConfig = (codec_config_t *)config; + + wm8524_config_t *devConfig = (wm8524_config_t *)(codecConfig->codecDevConfig); + wm8524_handle_t *devHandle = (wm8524_handle_t *)((uint32_t)(((codec_handle_t *)handle)->codecDevHandle)); + + ((codec_handle_t *)handle)->codecCapability = &s_wm8524_capability; + + /* codec device initialization */ + return WM8524_Init(devHandle, devConfig); +} + +/*! + * brief Codec de-initilization. + * + * param handle codec handle. + * return kStatus_Success is success, else de-initial failed. + */ +status_t HAL_CODEC_WM8524_Deinit(void *handle) +{ + return kStatus_CODEC_NotSupport; +} + +/*! + * brief set audio data format. + * + * param handle codec handle. + * param mclk master clock frequency in HZ. + * param sampleRate sample rate in HZ. + * param bitWidth bit width. + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetFormat(void *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth) +{ + /* wm8524 support sample rate range:8K~192k */ + if ((sampleRate < 8000U) || ((sampleRate > 192000U))) + { + return kStatus_CODEC_NotSupport; + } + + return kStatus_Success; +} + +/*! + * brief set audio codec module volume. + * + * param handle codec handle. + * param channel audio codec play channel, can be a value or combine value of _codec_play_channel. + * param volume volume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value. + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetVolume(void *handle, uint32_t playChannel, uint32_t volume) +{ + return kStatus_CODEC_NotSupport; +} + +/*! + * brief set audio codec module mute. + * + * param handle codec handle. + * param channel audio codec play channel, can be a value or combine value of _codec_play_channel. + * param isMute true is mute, false is unmute. + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetMute(void *handle, uint32_t playChannel, bool isMute) +{ + assert(handle != NULL); + + WM8524_SetMute((wm8524_handle_t *)((uint32_t)(((codec_handle_t *)handle)->codecDevHandle)), isMute); + + return kStatus_Success; +} + +/*! + * brief set audio codec module power. + * + * param handle codec handle. + * param module audio codec module. + * param powerOn true is power on, false is power down. + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetPower(void *handle, uint32_t module, bool powerOn) +{ + return kStatus_CODEC_NotSupport; +} + +/*! + * brief codec set record channel. + * + * param handle codec handle. + * param leftRecordChannel audio codec record channel, reference _codec_record_channel, can be a value or combine value + of member in _codec_record_channel. + * param rightRecordChannel audio codec record channel, reference _codec_record_channel, can be a value combine of + member in _codec_record_channel. + + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetRecordChannel(void *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel) +{ + return kStatus_CODEC_NotSupport; +} + +/*! + * brief codec set record source. + * + * param handle codec handle. + * param source audio codec record source, can be a value or combine value of _codec_record_source. + * + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetRecord(void *handle, uint32_t recordSource) +{ + return kStatus_CODEC_NotSupport; +} + +/*! + * brief codec set play source. + * + * param handle codec handle. + * param playSource audio codec play source, can be a value or combine value of _codec_play_source. + * + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetPlay(void *handle, uint32_t playSource) +{ + return kStatus_CODEC_NotSupport; +} + +/*! + * brief codec module control. + * + * param handle codec handle. + * param cmd module control cmd, reference _codec_module_ctrl_cmd. + * param data value to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine + * of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference + * codec specific driver for detail configurations. + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_ModuleControl(void *handle, uint32_t cmd, uint32_t data) +{ + return kStatus_CODEC_NotSupport; +} diff --git a/components/codec/port/wm8524/fsl_codec_wm8524_adapter.h b/components/codec/port/wm8524/fsl_codec_wm8524_adapter.h new file mode 100644 index 000000000..8d7095695 --- /dev/null +++ b/components/codec/port/wm8524/fsl_codec_wm8524_adapter.h @@ -0,0 +1,282 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CODEC_WM8524_ADAPTER_H_ +#define _FSL_CODEC_WM8524_ADAPTER_H_ + +#include "fsl_wm8524.h" + +/*! + * @addtogroup wm8524_adapter + * @ingroup codec_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*!@brief codec handler size */ +#define HAL_CODEC_WM8524_HANDLER_SIZE (4) +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif +/*! + * @brief Codec initilization. + * + * @param handle codec handle. + * @param config codec configuration. + * @return kStatus_Success is success, else initial failed. + */ +status_t HAL_CODEC_WM8524_Init(void *handle, void *config); + +/*! + * @brief Codec de-initilization. + * + * @param handle codec handle. + * @return kStatus_Success is success, else de-initial failed. + */ +status_t HAL_CODEC_WM8524_Deinit(void *handle); + +/*! + * @brief set audio data format. + * + * @param handle codec handle. + * @param mclk master clock frequency in HZ. + * @param sampleRate sample rate in HZ. + * @param bitWidth bit width. + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetFormat(void *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth); + +/*! + * @brief set audio codec module volume. + * + * @param handle codec handle. + * @param playChannel audio codec play channel, can be a value or combine value of _codec_play_channel. + * @param volume volume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value. + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetVolume(void *handle, uint32_t playChannel, uint32_t volume); + +/*! + * @brief set audio codec module mute. + * + * @param handle codec handle. + * @param playChannel audio codec play channel, can be a value or combine value of _codec_play_channel. + * @param isMute true is mute, false is unmute. + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetMute(void *handle, uint32_t playChannel, bool isMute); + +/*! + * @brief set audio codec module power. + * + * @param handle codec handle. + * @param module audio codec module. + * @param powerOn true is power on, false is power down. + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetPower(void *handle, uint32_t module, bool powerOn); + +/*! + * @brief codec set record source. + * + * @param handle codec handle. + * @param recordSource audio codec record source, can be a value or combine value of _codec_record_source. + * + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetRecord(void *handle, uint32_t recordSource); + +/*! + * @brief codec set record channel. + * + * @param handle codec handle. + * @param leftRecordChannel audio codec record channel, reference _codec_record_channel, can be a value or combine value + of member in _codec_record_channel. + * @param rightRecordChannel audio codec record channel, reference _codec_record_channel, can be a value combine of + member in _codec_record_channel. + + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetRecordChannel(void *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel); + +/*! + * @brief codec set play source. + * + * @param handle codec handle. + * @param playSource audio codec play source, can be a value or combine value of _codec_play_source. + * + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_SetPlay(void *handle, uint32_t playSource); + +/*! + * @brief codec module control. + * + * This function is used for codec module control, support switch digital interface cmd, can be expand to support codec + * module specific feature + * + * @param handle codec handle. + * @param cmd module control cmd, reference _codec_module_ctrl_cmd. + * @param data value to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine + * of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference + * codec specific driver for detail configurations. + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_WM8524_ModuleControl(void *handle, uint32_t cmd, uint32_t data); + +#if !(defined CODEC_MULTI_ADAPTERS && CODEC_MULTI_ADAPTERS) +/*! + * @brief Codec initilization. + * + * @param handle codec handle. + * @param config codec configuration. + * @return kStatus_Success is success, else initial failed. + */ +static inline status_t HAL_CODEC_Init(void *handle, void *config) +{ + return HAL_CODEC_WM8524_Init(handle, config); +} + +/*! + * @brief Codec de-initilization. + * + * @param handle codec handle. + * @return kStatus_Success is success, else de-initial failed. + */ +static inline status_t HAL_CODEC_Deinit(void *handle) +{ + return HAL_CODEC_WM8524_Deinit(handle); +} + +/*! + * @brief set audio data format. + * + * @param handle codec handle. + * @param mclk master clock frequency in HZ. + * @param sampleRate sample rate in HZ. + * @param bitWidth bit width. + * @return kStatus_Success is success, else configure failed. + */ +static inline status_t HAL_CODEC_SetFormat(void *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth) +{ + return HAL_CODEC_WM8524_SetFormat(handle, mclk, sampleRate, bitWidth); +} + +/*! + * @brief set audio codec module volume. + * + * @param handle codec handle. + * @param playChannel audio codec play channel, can be a value or combine value of _codec_play_channel. + * @param volume volume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value. + * @return kStatus_Success is success, else configure failed. + */ +static inline status_t HAL_CODEC_SetVolume(void *handle, uint32_t playChannel, uint32_t volume) +{ + return HAL_CODEC_WM8524_SetVolume(handle, playChannel, volume); +} + +/*! + * @brief set audio codec module mute. + * + * @param handle codec handle. + * @param playChannel audio codec play channel, can be a value or combine value of _codec_play_channel. + * @param isMute true is mute, false is unmute. + * @return kStatus_Success is success, else configure failed. + */ +static inline status_t HAL_CODEC_SetMute(void *handle, uint32_t playChannel, bool isMute) +{ + return HAL_CODEC_WM8524_SetMute(handle, playChannel, isMute); +} + +/*! + * @brief set audio codec module power. + * + * @param handle codec handle. + * @param module audio codec module. + * @param powerOn true is power on, false is power down. + * @return kStatus_Success is success, else configure failed. + */ +static inline status_t HAL_CODEC_SetPower(void *handle, uint32_t module, bool powerOn) +{ + return HAL_CODEC_WM8524_SetPower(handle, module, powerOn); +} + +/*! + * @brief codec set record source. + * + * @param handle codec handle. + * @param recordSource audio codec record source, can be a value or combine value of _codec_record_source. + * + * @return kStatus_Success is success, else configure failed. + */ +static inline status_t HAL_CODEC_SetRecord(void *handle, uint32_t recordSource) +{ + return HAL_CODEC_WM8524_SetRecord(handle, recordSource); +} + +/*! + * @brief codec set record channel. + * + * @param handle codec handle. + * @param leftRecordChannel audio codec record channel, reference _codec_record_channel, can be a value or combine value + of member in _codec_record_channel. + * @param rightRecordChannel audio codec record channel, reference _codec_record_channel, can be a value combine of + member in _codec_record_channel. + + * @return kStatus_Success is success, else configure failed. + */ +static inline status_t HAL_CODEC_SetRecordChannel(void *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel) +{ + return HAL_CODEC_WM8524_SetRecordChannel(handle, leftRecordChannel, rightRecordChannel); +} + +/*! + * @brief codec set play source. + * + * @param handle codec handle. + * @param playSource audio codec play source, can be a value or combine value of _codec_play_source. + * + * @return kStatus_Success is success, else configure failed. + */ +static inline status_t HAL_CODEC_SetPlay(void *handle, uint32_t playSource) +{ + return HAL_CODEC_WM8524_SetPlay(handle, playSource); +} + +/*! + * @brief codec module control. + * + * This function is used for codec module control, support switch digital interface cmd, can be expand to support codec + * module specific feature + * + * @param handle codec handle. + * @param cmd module control cmd, reference _codec_module_ctrl_cmd. + * @param data value to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine + * of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference + * codec specific driver for detail configurations. + * @return kStatus_Success is success, else configure failed. + */ +static inline status_t HAL_CODEC_ModuleControl(void *handle, uint32_t cmd, uint32_t data) +{ + return HAL_CODEC_WM8524_ModuleControl(handle, cmd, data); +} +#endif + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_CODEC_WM8524_ADAPTER_H_ */ diff --git a/components/codec/wm8524/driver_wm8524_MIMX8MQ6.cmake b/components/codec/wm8524/driver_wm8524_MIMX8MQ6.cmake new file mode 100644 index 000000000..b968c10ea --- /dev/null +++ b/components/codec/wm8524/driver_wm8524_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_wm8524 component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_wm8524.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/components/codec/wm8524/fsl_wm8524.c b/components/codec/wm8524/fsl_wm8524.c new file mode 100644 index 000000000..240280b84 --- /dev/null +++ b/components/codec/wm8524/fsl_wm8524.c @@ -0,0 +1,85 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_wm8524.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initializes WM8524. + * + * param handle WM8524 handle structure. + * param config WM8524 configure structure. + * return kStatus_Success. + */ +status_t WM8524_Init(wm8524_handle_t *handle, wm8524_config_t *config) +{ + assert(config != NULL); + wm8524_config_t *wm8524Config = (wm8524_config_t *)config; + + handle->config = config; + + if ((wm8524Config->setProtocol) != NULL) + { + /* set format */ + WM8524_ConfigFormat(handle, wm8524Config->protocol); + } + + /* Unmute codec */ + wm8524Config->setMute(kWM8524_Unmute); + + return kStatus_Success; +} + +/*! + * brief Configure WM8524 audio protocol. + * + * param handle WM8524 handle structure. + * param protocol WM8524 configuration structure. + */ +void WM8524_ConfigFormat(wm8524_handle_t *handle, wm8524_protocol_t protocol) +{ + assert(handle->config != NULL); + assert(handle->config->setProtocol != NULL); + + wm8524_config_t *wm8524Config = (wm8524_config_t *)handle->config; + + if (protocol != kWM8524_ProtocolRightJustified) + { + wm8524Config->setProtocol((uint32_t)protocol); + } +} + +/*! + * brief Sets the codec mute state. + * + * param handle WM8524 handle structure. + * param isMute true means mute, false means normal. + */ +void WM8524_SetMute(wm8524_handle_t *handle, bool isMute) +{ + assert(handle->config != NULL); + assert(handle->config->setMute != NULL); + + wm8524_config_t *wm8524Config = (wm8524_config_t *)handle->config; + + wm8524Config->setMute(!isMute); +} diff --git a/components/codec/wm8524/fsl_wm8524.h b/components/codec/wm8524/fsl_wm8524.h new file mode 100644 index 000000000..9e2078dd9 --- /dev/null +++ b/components/codec/wm8524/fsl_wm8524.h @@ -0,0 +1,98 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_WM8524_H_ +#define _FSL_WM8524_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wm8524 + * @ingroup codec + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief WM8524 driver version 2.1.1. */ +#define FSL_WM8524_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +/*!< mute control io function pointer */ +typedef void (*wm8524_setMuteIO)(uint32_t output); +/*!< format control io function pointer */ +typedef void (*wm8524_setProtocolIO)(uint32_t output); + +/*! @brief The audio data transfer protocol. */ +typedef enum _wm8524_protocol +{ + kWM8524_ProtocolLeftJustified = 0x0, /*!< Left justified mode */ + kWM8524_ProtocolI2S = 0x1, /*!< I2S mode */ + kWM8524_ProtocolRightJustified = 0x2, /*!< Right justified mode */ +} wm8524_protocol_t; + +/*! @brief wm8524 mute operation */ +enum _wm8524_mute_control +{ + kWM8524_Mute = 0U, /*!< mute left and right channel DAC */ + kWM8524_Unmute = 1U, /*!< unmute left and right channel DAC */ +}; + +/*!< @brief WM8524 configurations */ +typedef struct _wm8524_config +{ + wm8524_setMuteIO setMute; /*!< mute io control function pointer */ + wm8524_setProtocolIO setProtocol; /*!< format io control function pointer */ + wm8524_protocol_t protocol; /*!< Protocol of the codec */ +} wm8524_config_t; + +/*!@brief WM8524 handler */ +typedef struct _wm8524_handle_t +{ + wm8524_config_t *config; /*!< wm8524 config pointer */ +} wm8524_handle_t; +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes WM8524. + * + * @param handle WM8524 handle structure. + * @param config WM8524 configure structure. + * @return kStatus_Success. + */ +status_t WM8524_Init(wm8524_handle_t *handle, wm8524_config_t *config); + +/*! + * @brief Configure WM8524 audio protocol. + * + * @param handle WM8524 handle structure. + * @param protocol WM8524 configuration structure. + */ +void WM8524_ConfigFormat(wm8524_handle_t *handle, wm8524_protocol_t protocol); + +/*! + * @brief Sets the codec mute state. + * + * @param handle WM8524 handle structure. + * @param isMute true means mute, false means normal. + */ +void WM8524_SetMute(wm8524_handle_t *handle, bool isMute); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ +#endif /* _FSL_WM8524_H_ */ diff --git a/components/common_task/fsl_component_common_task.c b/components/common_task/fsl_component_common_task.c new file mode 100644 index 000000000..a4650da7a --- /dev/null +++ b/components/common_task/fsl_component_common_task.c @@ -0,0 +1,117 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * The OSA_USED macro can only be defined when the OSA component is used. + * If the source code of the OSA component does not exist, the OSA_USED cannot be defined. + * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED + * also cannot be defined. + * The source code path of the OSA component is /components/osa. + * + */ +#if defined(OSA_USED) +#if (defined(COMMON_TASK_ENABLE) && (COMMON_TASK_ENABLE > 0U)) + +#include "fsl_os_abstraction.h" + +#include "fsl_component_common_task.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +typedef struct _common_task_state +{ + OSA_TASK_HANDLE_DEFINE(commonTaskHandle); + OSA_MSGQ_HANDLE_DEFINE(msgqhandle, COMMON_TASK_MAX_MSGQ_COUNT, sizeof(void *)); + uint8_t isInitialized; +} common_task_state_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +void COMMON_TASK_task(osa_task_param_t param); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +extern const uint8_t gUseRtos_c; +static common_task_state_t s_commonTaskState[1]; +OSA_TASK_DEFINE(COMMON_TASK_task, COMMON_TASK_PRIORITY, 1, COMMON_TASK_STACK_SIZE, false); + +/******************************************************************************* + * Code + ******************************************************************************/ + +void COMMON_TASK_task(osa_task_param_t param) +{ + common_task_state_t *commonTaskStateHandle = (common_task_state_t *)param; + common_task_message_t *msg; + do + { + if (KOSA_StatusSuccess == + OSA_MsgQGet((osa_msgq_handle_t)commonTaskStateHandle->msgqhandle, &msg, osaWaitForever_c)) + { + if (msg->callback) + { + msg->callback(msg->callbackParam); + } + } + } while (gUseRtos_c); +} + +common_task_status_t COMMON_TASK_init(void) +{ + osa_status_t status; + + if (s_commonTaskState->isInitialized) + { + return kStatus_COMMON_TASK_Error; + } + s_commonTaskState->isInitialized = 1U; + + status = + OSA_MsgQCreate((osa_msgq_handle_t)s_commonTaskState->msgqhandle, COMMON_TASK_MAX_MSGQ_COUNT, sizeof(void *)); + assert(KOSA_StatusSuccess == status); + + status = OSA_TaskCreate((osa_task_handle_t)s_commonTaskState->commonTaskHandle, OSA_TASK(COMMON_TASK_task), + s_commonTaskState); + assert(KOSA_StatusSuccess == status); + (void)status; + + return kStatus_COMMON_TASK_Success; +} + +common_task_status_t COMMON_TASK_deinit(void) +{ + if (!s_commonTaskState->isInitialized) + { + return kStatus_COMMON_TASK_Error; + } + + OSA_MsgQDestroy((osa_msgq_handle_t)s_commonTaskState->msgqhandle); + OSA_TaskDestroy((osa_task_handle_t)s_commonTaskState->commonTaskHandle); + s_commonTaskState->isInitialized = 0U; + + return kStatus_COMMON_TASK_Success; +} + +common_task_status_t COMMON_TASK_post_message(common_task_message_t *msg) +{ + assert(msg); + assert(msg->callback); + assert(s_commonTaskState->isInitialized); + + if (KOSA_StatusSuccess != OSA_MsgQPut((osa_msgq_handle_t)s_commonTaskState->msgqhandle, &msg)) + { + return kStatus_COMMON_TASK_Error; + } + return kStatus_COMMON_TASK_Success; +} +#endif +#endif diff --git a/components/common_task/fsl_component_common_task.h b/components/common_task/fsl_component_common_task.h new file mode 100644 index 000000000..9cdc6764e --- /dev/null +++ b/components/common_task/fsl_component_common_task.h @@ -0,0 +1,126 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __COMMON_TASK_H__ +#define __COMMON_TASK_H__ + +#include "fsl_common.h" +/*! + * @addtogroup CommonTask + * @{ + */ + +#ifndef COMMON_TASK_ENABLE +#define COMMON_TASK_ENABLE (0) +#endif +#if !defined(OSA_USED) +#undef COMMON_TASK_ENABLE +#define COMMON_TASK_ENABLE (0) +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#if defined(OSA_USED) + +/*! @brief Definition of common task max msg queue count. */ +#ifndef COMMON_TASK_MAX_MSGQ_COUNT +#define COMMON_TASK_MAX_MSGQ_COUNT (8U) +#endif + +/*! @brief Definition of common task priority. */ +#ifndef COMMON_TASK_PRIORITY +#define COMMON_TASK_PRIORITY (9U) +#endif + +/*! @brief Definition of common task stack size. */ +#ifndef COMMON_TASK_STACK_SIZE +#define COMMON_TASK_STACK_SIZE (2000U) +#endif + +/*! @brief The status type of common task */ +typedef enum _common_task_status +{ + kStatus_COMMON_TASK_Success = kStatus_Success, /*!< Success */ + kStatus_COMMON_TASK_Error = MAKE_STATUS(kStatusGroup_COMMON_TASK, 1), /*!< Failed */ + kStatus_COMMON_TASK_Busy = MAKE_STATUS(kStatusGroup_COMMON_TASK, 2), /*!< Busy */ +} common_task_status_t; + +/*! @brief The callback function of common task */ +typedef void (*common_task_message_callback_t)(void *callbackParam); + +/*! @brief The callback message struct of common task */ +typedef struct _common_task_message +{ + common_task_message_callback_t callback; + void *callbackParam; +} common_task_message_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Common task functional operation + * @{ + */ + +/*! + * @brief Initializes the common task module + * + * This function is used to initialize the common task module. The module is a delegation for other modules + * without the self task. The common task will be created when the function is calling. + * The task stack size is set by #COMMON_TASK_STACK_SIZE. And the task priority is defined by #COMMON_TASK_PRIORITY. + * And a message queue is created with the length #COMMON_TASK_MAX_MSGQ_COUN by the function. + * + * This is an example. + * @code + * COMMON_TASK_init(); + * @endcode + * @retval kStatus_COMMON_TASK_Success The common task initialization succeed. + * @retval kStatus_COMMON_TASK_Error An error occurred when the common task is initialized. + */ +common_task_status_t COMMON_TASK_init(void); + +/*! + * @brief De-initializes the common task module + * + * This function is used to de-initialize the common task module. + * + * @retval kStatus_COMMON_TASK_Success The common task de-initialization succeed. + * @retval kStatus_COMMON_TASK_Error An error occurred when the common task is de-initialized. + */ +common_task_status_t COMMON_TASK_deinit(void); + +/*! + * @brief Posts a new message to common task + * + * This function is used to post a new message to common task. The message space cannot be released until + * the message is executed. + * + * @param msg Pointer to point to a memory space of #common_task_message_t allocated by the caller. + * @retval kStatus_COMMON_TASK_Success The common task de-initialization succeed. + * @retval kStatus_COMMON_TASK_Error An error occurred when post a message to the common task. + */ +common_task_status_t COMMON_TASK_post_message(common_task_message_t *msg); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif + +/*! @}*/ + +#endif diff --git a/components/crc/fsl_adapter_crc.h b/components/crc/fsl_adapter_crc.h new file mode 100644 index 000000000..a4a483598 --- /dev/null +++ b/components/crc/fsl_adapter_crc.h @@ -0,0 +1,127 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CRC_H_ +#define _CRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup CRC_Adapter + * @{ + */ + +/************************************************************************************ +************************************************************************************* +* Include +************************************************************************************* +***********************************************************************************/ + +/************************************************************************************ +************************************************************************************* +* Public types +************************************************************************************* +************************************************************************************/ +/*! @brief crcRefIn definitions. */ +typedef enum _hal_crc_cfg_refin +{ + KHAL_CrcInputNoRef = 0U, /*!< Do not manipulate input data stream. */ + KHAL_CrcRefInput = 1U /*!< Reflect each byte in the input stream bitwise. */ +} hal_crc_cfg_refin_t; + +/*! @brief crcRefOut definitions. */ +typedef enum _hal_crc_cfg_refout +{ + KHAL_CrcOutputNoRef = 0U, /*!< Do not manipulate CRC result. */ + KHAL_CrcRefOutput = 1U /*!< CRC result is to be reflected bitwise (operated on entire word). */ +} hal_crc_cfg_refout_t; + +/*! @brief crcByteOrder definitions. */ +typedef enum _hal_crc_cfg_byteord +{ + KHAL_CrcLSByteFirst = 0U, /*!< Byte order of the CRC LS Byte first. */ + KHAL_CrcMSByteFirst = 1U /*!< Bit order of the CRC MS Byte first. */ +} hal_crc_cfg_byteord_t; + +/*! @brief CRC polynomials to use. */ +typedef enum _hal_crc_polynomial +{ + KHAL_CrcPolynomial_CRC_8_CCITT = 0x103, /*!< x^8+x^2+x^1+1 */ + KHAL_CrcPolynomial_CRC_16 = 0x1021, /*!< x^16+x^12+x^5+1 */ + KHAL_CrcPolynomial_CRC_32 = 0x4C11DB7U, /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ +} hal_crc_polynomial_t; + +/*! @brief CRC configuration structure. */ +typedef struct _hal_crc_config +{ + hal_crc_cfg_refin_t crcRefIn; /*!< CRC reflect input. See "hal_crc_cfg_refin_t". */ + hal_crc_cfg_refout_t crcRefOut; /*!< CRC reflect output. See "hal_crc_cfg_refout_t". */ + hal_crc_cfg_byteord_t crcByteOrder; /*!< CRC byte order. See "hal_crc_cfg_byteord_t". */ + uint32_t crcSeed; /*!< CRC Seed value. Initial value for CRC LFSR. */ + uint32_t crcPoly; /*!< CRC Polynomial value. */ + uint32_t crcXorOut; /*!< XOR mask for CRC result (for no mask, should be 0). */ + uint8_t complementChecksum; /*!< wether output the complement checksum. */ + uint8_t crcSize; /*!< Number of CRC octets, 2 mean use CRC16, 4 mean use CRC32. */ + uint8_t crcStartByte; /*!< Start CRC with this byte position. Byte #0 is the first byte of Sync Address. */ +} hal_crc_config_t; + +/************************************************************************************ +************************************************************************************* +* Public prototypes +************************************************************************************* +************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name CRC + * @{ + */ + +/*! + * @brief Compute CRC function. + * + * The function computes the CRC. + * + * @code + * config = (hal_crc_config_t) { + * .crcSize = 4, + * .crcStartByte = 0, + * .crcRefIn = KHAL_CrcInputNoRef, + * .crcRefOut = KHAL_CrcOutputNoRef, + * .crcByteOrder = KHAL_CrcMSByteFirst, + * .complementChecksum = true, + * .crcSeed = 0xFFFFFFFF, + * .crcPoly = KHAL_CrcPolynomial_CRC_32, + * .crcXorOut = 0xFFFFFFFF, + * }; + * + * res = HAL_CrcCompute(&config, (uint8_t *) pattern, strlen(pattern)); + * @endcode + * + * @note The settings for compute CRC are taken from the passed CRC_config_t structure. + * + * @param crcConfig configuration structure. + * @param dataIn input data buffer. + * @param length input data buffer size. + * + * @retval Computed CRC value. + */ +uint32_t HAL_CrcCompute(hal_crc_config_t *crcConfig, uint8_t *dataIn, uint32_t length); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _CRC_H_ */ diff --git a/components/crc/fsl_adapter_software_crc.c b/components/crc/fsl_adapter_software_crc.c new file mode 100644 index 000000000..4e7815ca7 --- /dev/null +++ b/components/crc/fsl_adapter_software_crc.c @@ -0,0 +1,94 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_adapter_crc.h" + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t HAL_CrcCompute(hal_crc_config_t *crcConfig, uint8_t *dataIn, uint32_t length) +{ + uint32_t shiftReg = crcConfig->crcSeed << ((4U - crcConfig->crcSize) << 3U); + uint32_t crcPoly = crcConfig->crcPoly << ((4U - crcConfig->crcSize) << 3U); + uint32_t crcXorOut = crcConfig->crcXorOut << ((4U - crcConfig->crcSize) << 3U); + uint16_t startOffset = crcConfig->crcStartByte; + uint8_t crcBits = 8U * crcConfig->crcSize; + uint32_t computedCRC = 0; + uint32_t i, j; + uint8_t data = 0; + uint8_t bit; + + /* Size 0 will bypass CRC calculation. */ + if (crcConfig->crcSize != 0U) + { + for (i = 0UL + startOffset; i < length; i++) + { + data = dataIn[i]; + + if (crcConfig->crcRefIn == KHAL_CrcRefInput) + { + bit = 0U; + for (j = 0U; j < 8U; j++) + { + bit = (bit << 1); + bit |= ((data & 1U) != 0U) ? 1U : 0U; + data = (data >> 1); + } + data = bit; + } + + for (j = 0; j < 8U; j++) + { + bit = ((data & 0x80U) != 0U) ? 1U : 0U; + data = (data << 1); + + if ((shiftReg & 1UL << 31) != 0U) + { + bit = (bit != 0U) ? 0U : 1U; + } + + shiftReg = (shiftReg << 1); + + if (bit != 0U) + { + shiftReg ^= crcPoly; + } + + if ((bool)bit && ((crcPoly & (1UL << (32U - crcBits))) != 0U)) + { + shiftReg |= (1UL << (32U - crcBits)); + } + else + { + shiftReg &= ~(1UL << (32U - crcBits)); + } + } + } + + shiftReg ^= crcXorOut; + + if (crcConfig->crcByteOrder == KHAL_CrcMSByteFirst) + { + computedCRC = (shiftReg >> (32U - crcBits)); + } + else + { + computedCRC = 0; + j = 1U; + for (i = 0; i < 32U; i++) + { + computedCRC = (computedCRC << 1); + computedCRC |= ((shiftReg & j) != 0U) ? 1U : 0U; + j = (j << 1); + } + } + } + + return computedCRC; +} diff --git a/components/gpio/fsl_adapter_gpio.h b/components/gpio/fsl_adapter_gpio.h new file mode 100644 index 000000000..1d86da927 --- /dev/null +++ b/components/gpio/fsl_adapter_gpio.h @@ -0,0 +1,293 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_GPIO_H__ +#define __HAL_GPIO_H__ + +#include "fsl_common.h" +#if defined(SDK_OS_FREE_RTOS) +#include "FreeRTOS.h" +#endif + +/*! + * @addtogroup GPIO_Adapter + * @{ + */ + +/******************************************************************************* + * Public macro + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +#define FSL_GPIO_ADAPTER_VERSION (MAKE_VERSION(1, 0, 1)) /*!< Version 1.0.1. */ + /*@}*/ + +/*! @brief Definition of GPIO conflict check Enable. */ +#ifndef HAL_GPIO_CONFLICT_CHECK_ENABLE +#define HAL_GPIO_CONFLICT_CHECK_ENABLE (1) +#endif + +/*! @brief Definition of GPIO adapter handle size. */ +#define HAL_GPIO_HANDLE_SIZE (16U) + +/*! + * @brief Defines the gpio handle + * + * This macro is used to define a 4 byte aligned gpio handle. + * Then use "(hal_gpio_handle_t)name" to get the gpio handle. + * + * The macro should be global and could be optional. You could also define gpio handle by yourself. + * + * This is an example, + * @code + * GPIO_HANDLE_DEFINE(gpioHandle); + * @endcode + * + * @param name The name string of the gpio handle. + */ +#define GPIO_HANDLE_DEFINE(name) uint32_t name[((HAL_GPIO_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] + +/*! @brief Definition of GPIO adapter isr priority. */ +#ifndef HAL_GPIO_ISR_PRIORITY +#if defined(__GIC_PRIO_BITS) +#define HAL_GPIO_ISR_PRIORITY (25U) +#else +#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) +#define HAL_GPIO_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) +#else +/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc. + * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum + * priority is 3 (2^2 - 1). So, the default value is 3. + */ +#define HAL_GPIO_ISR_PRIORITY (3U) +#endif /* defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) */ +#endif /* defined(__GIC_PRIO_BITS) */ +#endif /* HAL_GPIO_ISR_PRIORITY */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The handle of GPIO adapter. */ +typedef void *hal_gpio_handle_t; + +/*! @brief The callback function of GPIO adapter. */ +typedef void (*hal_gpio_callback_t)(void *param); + +/*! @brief The interrupt trigger of GPIO adapter. */ +typedef enum _hal_gpio_interrupt_trigger +{ + kHAL_GpioInterruptDisable = 0x0U, /*!< Interrupt disable. */ + kHAL_GpioInterruptLogicZero = 0x1U, /*!< Interrupt when logic zero. */ + kHAL_GpioInterruptRisingEdge = 0x2U, /*!< Interrupt on rising edge. */ + kHAL_GpioInterruptFallingEdge = 0x3U, /*!< Interrupt on falling edge. */ + kHAL_GpioInterruptEitherEdge = 0x4U, /*!< Interrupt on either edge. */ + kHAL_GpioInterruptLogicOne = 0x5U, /*!< Interrupt when logic one. */ +} hal_gpio_interrupt_trigger_t; + +/*! @brief The status of GPIO adapter. */ +typedef enum _hal_gpio_status +{ + kStatus_HAL_GpioSuccess = kStatus_Success, /*!< Success */ + kStatus_HAL_GpioError = MAKE_STATUS(kStatusGroup_HAL_GPIO, 1), /*!< Failed */ + kStatus_HAL_GpioLackSource = MAKE_STATUS(kStatusGroup_HAL_GPIO, 2), /*!< Lack of sources */ + kStatus_HAL_GpioPinConflict = MAKE_STATUS(kStatusGroup_HAL_GPIO, 3), /*!< PIN conflict */ +} hal_gpio_status_t; + +/*! @brief The direction of GPIO adapter. */ +typedef enum _hal_gpio_direction +{ + kHAL_GpioDirectionIn = 0x00U, /*!< Out */ + kHAL_GpioDirectionOut, /*!< In */ +} hal_gpio_direction_t; + +/*! @brief The pin config struct of GPIO adapter. */ +typedef struct _hal_gpio_pin_config +{ + hal_gpio_direction_t direction; + uint8_t level; + uint8_t port; + uint8_t pin; +} hal_gpio_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Initializes static variable located in .bss section. + * + * This function is used to initialize variable located in .bss section. + * Usually users don't need to call this API. + * It's just used in the case GPIO adapter is used before .bss section is automatically cleaned up by IDE. + * Example below shows how to use this API. + * @code + * HAL_GpioPreInit(); + * GPIO_HANDLE_DEFINE(g_GpioHandle); + * hal_gpio_pin_config_t config; + * config.direction = kHAL_GpioDirectionOut; + * config.port = 0; + * config.pin = 0; + * config.level = 0; + * HAL_GpioInit((hal_gpio_handle_t)g_GpioHandle, &config); + * @endcode + */ +void HAL_GpioPreInit(void); + +/*! + * @brief Initializes an GPIO instance with the GPIO handle and the user configuration structure. + * + * This function configures the GPIO module with user-defined settings. The user can configure the configuration + * structure. The parameter gpioHandle is a pointer to point to a memory space of size #HAL_GPIO_HANDLE_SIZE allocated + * by the caller. Example below shows how to use this API to configure the GPIO. + * @code + * GPIO_HANDLE_DEFINE(g_GpioHandle); + * hal_gpio_pin_config_t config; + * config.direction = kHAL_GpioDirectionOut; + * config.port = 0; + * config.pin = 0; + * config.level = 0; + * HAL_GpioInit((hal_gpio_handle_t)g_GpioHandle, &config); + * @endcode + * + * @param gpioHandle GPIO handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #GPIO_HANDLE_DEFINE(gpioHandle); + * or + * uint32_t gpioHandle[((HAL_GPIO_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param pinConfig Pointer to user-defined configuration structure. + * @retval kStatus_HAL_GpioError An error occurred while initializing the GPIO. + * @retval kStatus_HAL_GpioPinConflict The pair of the pin and port passed by pinConfig is initialized. + * @retval kStatus_HAL_GpioSuccess GPIO initialization succeed + */ +hal_gpio_status_t HAL_GpioInit(hal_gpio_handle_t gpioHandle, hal_gpio_pin_config_t *pinConfig); + +/*! + * @brief Deinitializes a GPIO instance. + * + * This function disables the trigger mode. + * + * @param gpioHandle GPIO handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @retval kStatus_HAL_GpioSuccess GPIO de-initialization succeed + */ +hal_gpio_status_t HAL_GpioDeinit(hal_gpio_handle_t gpioHandle); + +/*! + * @brief Gets the pin voltage. + * + * This function gets the pin voltage. 0 - low level voltage, 1 - high level voltage. + * + * @param gpioHandle GPIO handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @param pinState A pointer to save the pin state. + * @retval kStatus_HAL_GpioSuccess Get successfully. + */ +hal_gpio_status_t HAL_GpioGetInput(hal_gpio_handle_t gpioHandle, uint8_t *pinState); + +/*! + * @brief Sets the pin voltage. + * + * This function sets the pin voltage. 0 - low level voltage, 1 - high level voltage. + * + * @param gpioHandle GPIO handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @param pinState Pin state. + * @retval kStatus_HAL_GpioSuccess Set successfully. + */ +hal_gpio_status_t HAL_GpioSetOutput(hal_gpio_handle_t gpioHandle, uint8_t pinState); + +/*! + * @brief Gets the pin interrupt trigger mode. + * + * This function gets the pin interrupt trigger mode. The trigger mode please refer to + * #hal_gpio_interrupt_trigger_t. + * + * @param gpioHandle GPIO handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @param gpioTrigger A pointer to save the pin trigger mode value. + * @retval kStatus_HAL_GpioSuccess Get successfully. + * @retval kStatus_HAL_GpioError The pin is the ouput setting. + */ +hal_gpio_status_t HAL_GpioGetTriggerMode(hal_gpio_handle_t gpioHandle, hal_gpio_interrupt_trigger_t *gpioTrigger); + +/*! + * @brief Sets the pin interrupt trigger mode. + * + * This function sets the pin interrupt trigger mode. The trigger mode please refer to + * #hal_gpio_interrupt_trigger_t. + * + * @param gpioHandle GPIO handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @param gpioTrigger The pin trigger mode value. + * @retval kStatus_HAL_GpioSuccess Set successfully. + * @retval kStatus_HAL_GpioError The pin is the ouput setting. + */ +hal_gpio_status_t HAL_GpioSetTriggerMode(hal_gpio_handle_t gpioHandle, hal_gpio_interrupt_trigger_t gpioTrigger); + +/*! + * @brief Installs a callback and callback parameter. + * + * This function is used to install the callback and callback parameter for GPIO module. + * When the pin state interrupt happened, the driver will notify the upper layer by the installed callback + * function. After the callback called, the GPIO pin state can be got by calling function #HAL_GpioGetInput. + * + * @param gpioHandle GPIO handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_HAL_GpioSuccess Successfully install the callback. + */ +hal_gpio_status_t HAL_GpioInstallCallback(hal_gpio_handle_t gpioHandle, + hal_gpio_callback_t callback, + void *callbackParam); + +/*! + * @brief Enables or disables the GPIO wake-up feature. + * + * This function enables or disables the GPIO wake-up feature. + * + * @param gpioHandle GPIO handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @param enable enable or disable (0 - disable, 1 - enable). + * @retval kStatus_HAL_GpioError An error occurred. + * @retval kStatus_HAL_GpioSuccess Set successfully. + */ +hal_gpio_status_t HAL_GpioWakeUpSetting(hal_gpio_handle_t gpioHandle, uint8_t enable); + +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @param gpioHandle GPIO handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @retval kStatus_HAL_GpioSuccess Successful operation. + */ +hal_gpio_status_t HAL_GpioEnterLowpower(hal_gpio_handle_t gpioHandle); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @param gpioHandle GPIO handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @retval kStatus_HAL_GpioSuccess Successful operation. + */ +hal_gpio_status_t HAL_GpioExitLowpower(hal_gpio_handle_t gpioHandle); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +/*! @}*/ +#endif /* __HAL_GPIO_H__ */ diff --git a/components/gpio/fsl_adapter_igpio.c b/components/gpio/fsl_adapter_igpio.c new file mode 100644 index 000000000..b642df4f6 --- /dev/null +++ b/components/gpio/fsl_adapter_igpio.c @@ -0,0 +1,492 @@ +/* + * Copyright 2018 - 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_device_registers.h" +#include "fsl_gpio.h" +#include "fsl_adapter_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "component.igpio_adapter" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The pin config struct of gpio adapter. */ +typedef struct _hal_gpio_pin +{ + uint16_t port : 4U; + uint16_t pin : 5U; + uint16_t direction : 1U; + uint16_t trigger : 3U; + uint16_t reserved : 3U; +} hal_gpio_pin_t; + +typedef struct _hal_gpio_state +{ + struct _hal_gpio_state *next; + hal_gpio_callback_t callback; + void *callbackParam; + hal_gpio_pin_t pin; +} hal_gpio_state_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void HAL_GpioInterruptHandle(uint8_t port); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +static hal_gpio_state_t *s_GpioHead; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void HAL_GpioInterruptHandle(uint8_t port) +{ + hal_gpio_state_t *head = s_GpioHead; + GPIO_Type *gpioList[] = GPIO_BASE_PTRS; + uint32_t intFlag; + + /* Get and clear gpio pin interrupt Flag */ + intFlag = GPIO_PortGetInterruptFlags(gpioList[port]); + GPIO_PortClearInterruptFlags(gpioList[port], intFlag); + + while (NULL != head) + { + /* Check which triger is ON! */ + if (kHAL_GpioInterruptDisable != (hal_gpio_interrupt_trigger_t)head->pin.trigger) + { + if ((port == head->pin.port) && (0U != (intFlag & ((uint32_t)1 << head->pin.pin)))) + { + if ((NULL != head->callback)) + { + head->callback(head->callbackParam); + } + } + } + + head = head->next; + } +} +/* IRQHandler for GPIO1 */ +#if defined(GPIO1) && (FSL_FEATURE_SOC_IGPIO_COUNT > 0U) +void GPIO1_Combined_0_15_IRQHandler(void); +void GPIO1_Combined_0_15_IRQHandler(void) +{ + HAL_GpioInterruptHandle(1); + + SDK_ISR_EXIT_BARRIER; +} +void GPIO1_Combined_16_31_IRQHandler(void); +void GPIO1_Combined_16_31_IRQHandler(void) +{ + HAL_GpioInterruptHandle(1); + + SDK_ISR_EXIT_BARRIER; +} +#endif +/* IRQHandler for GPIO2 */ +#if defined(GPIO2) && (FSL_FEATURE_SOC_IGPIO_COUNT > 0U) +void GPIO2_Combined_0_15_IRQHandler(void); +void GPIO2_Combined_0_15_IRQHandler(void) +{ + HAL_GpioInterruptHandle(2); + + SDK_ISR_EXIT_BARRIER; +} +void GPIO2_Combined_16_31_IRQHandler(void); +void GPIO2_Combined_16_31_IRQHandler(void) +{ + HAL_GpioInterruptHandle(2); + + SDK_ISR_EXIT_BARRIER; +} +#endif +/* IRQHandler for GPIO3 */ +#if defined(GPIO3) && (FSL_FEATURE_SOC_IGPIO_COUNT > 0U) +void GPIO3_Combined_0_15_IRQHandler(void); +void GPIO3_Combined_0_15_IRQHandler(void) +{ + HAL_GpioInterruptHandle(3); + + SDK_ISR_EXIT_BARRIER; +} +void GPIO3_Combined_16_31_IRQHandler(void); +void GPIO3_Combined_16_31_IRQHandler(void) +{ + HAL_GpioInterruptHandle(3); + + SDK_ISR_EXIT_BARRIER; +} +#endif +/* IRQHandler for GPIO4 */ +#if defined(GPIO4) && (FSL_FEATURE_SOC_IGPIO_COUNT > 0U) +void GPIO4_Combined_0_15_IRQHandler(void); +void GPIO4_Combined_0_15_IRQHandler(void) +{ + HAL_GpioInterruptHandle(4); + + SDK_ISR_EXIT_BARRIER; +} +void GPIO4_Combined_16_31_IRQHandler(void); +void GPIO4_Combined_16_31_IRQHandler(void) +{ + HAL_GpioInterruptHandle(4); + + SDK_ISR_EXIT_BARRIER; +} +#endif +/* IRQHandler for GPIO5 */ +#if defined(GPIO5) && (FSL_FEATURE_SOC_IGPIO_COUNT > 0U) +void GPIO5_Combined_0_15_IRQHandler(void); +void GPIO5_Combined_0_15_IRQHandler(void) +{ + HAL_GpioInterruptHandle(5); + + SDK_ISR_EXIT_BARRIER; +} +void GPIO5_Combined_16_31_IRQHandler(void); +void GPIO5_Combined_16_31_IRQHandler(void) +{ + HAL_GpioInterruptHandle(5); + + SDK_ISR_EXIT_BARRIER; +} +#endif +/* IRQHandler for GPIO6 GPIO7 GPIO8 GPIO9 */ +#if defined(GPIO6) && defined(GPIO7) && defined(GPIO8) && defined(GPIO9) && (FSL_FEATURE_SOC_IGPIO_COUNT > 8U) +void GPIO6_7_8_9_IRQHandler(void); +void GPIO6_7_8_9_IRQHandler(void) +{ + HAL_GpioInterruptHandle(6); + HAL_GpioInterruptHandle(7); + HAL_GpioInterruptHandle(8); + HAL_GpioInterruptHandle(9); + + SDK_ISR_EXIT_BARRIER; +} +#endif + +static hal_gpio_status_t HAL_GpioConflictSearch(hal_gpio_state_t *head, uint8_t port, uint8_t pin) +{ + while (NULL != head) + { + if ((head->pin.port == port) && (head->pin.pin == pin)) + { + return kStatus_HAL_GpioPinConflict; + } + head = head->next; + } + return kStatus_HAL_GpioSuccess; +} + +static hal_gpio_status_t HAL_GpioAddItem(hal_gpio_state_t **head, hal_gpio_state_t *node) +{ + hal_gpio_state_t *p = *head; + uint32_t regPrimask; + + regPrimask = DisableGlobalIRQ(); + + if (NULL == p) + { + *head = node; + } + else + { + while (NULL != p->next) + { + if (p == node) + { + EnableGlobalIRQ(regPrimask); + return kStatus_HAL_GpioPinConflict; + } + p = p->next; + } + + p->next = node; + } + node->next = NULL; + EnableGlobalIRQ(regPrimask); + return kStatus_HAL_GpioSuccess; +} + +static hal_gpio_status_t HAL_GpioRemoveItem(hal_gpio_state_t **head, hal_gpio_state_t *node) +{ + hal_gpio_state_t *p = *head; + hal_gpio_state_t *q = NULL; + uint32_t regPrimask; + + regPrimask = DisableGlobalIRQ(); + while (NULL != p) + { + if (p == node) + { + if (NULL == q) + { + *head = p->next; + } + else + { + q->next = p->next; + } + break; + } + else + { + q = p; + p = p->next; + } + } + EnableGlobalIRQ(regPrimask); + return kStatus_HAL_GpioSuccess; +} + +void HAL_GpioPreInit(void) +{ + s_GpioHead = NULL; +} + +hal_gpio_status_t HAL_GpioInit(hal_gpio_handle_t gpioHandle, hal_gpio_pin_config_t *pinConfig) +{ + hal_gpio_state_t *gpioState; + GPIO_Type *gpioList[] = GPIO_BASE_PTRS; + hal_gpio_status_t status = kStatus_HAL_GpioSuccess; + gpio_pin_config_t gpioPinconfig = { + kGPIO_DigitalInput, + 0, + kGPIO_NoIntmode, + }; + + assert(gpioHandle); + assert(pinConfig); + assert(HAL_GPIO_HANDLE_SIZE >= sizeof(hal_gpio_state_t)); + + gpioState = (hal_gpio_state_t *)gpioHandle; + + /* Check if the port is vaild */ + if (NULL == gpioList[pinConfig->port]) + { + return kStatus_HAL_GpioError; + } + + if ((NULL != s_GpioHead) && + (kStatus_HAL_GpioSuccess != HAL_GpioConflictSearch(s_GpioHead, pinConfig->port, pinConfig->pin))) + { + return kStatus_HAL_GpioPinConflict; + } + + status = HAL_GpioAddItem(&s_GpioHead, gpioState); + if (kStatus_HAL_GpioSuccess != status) + { + return status; + } + + gpioState->pin.pin = pinConfig->pin; + gpioState->pin.port = pinConfig->port; + gpioState->pin.direction = (uint16_t)pinConfig->direction; + gpioState->pin.trigger = (uint16_t)kHAL_GpioInterruptDisable; + + if (kHAL_GpioDirectionOut == (hal_gpio_direction_t)pinConfig->direction) + { + gpioPinconfig.direction = kGPIO_DigitalOutput; + } + else + { + gpioPinconfig.direction = kGPIO_DigitalInput; + } + gpioPinconfig.outputLogic = pinConfig->level; + GPIO_PinInit(gpioList[gpioState->pin.port], gpioState->pin.pin, &gpioPinconfig); + return kStatus_HAL_GpioSuccess; +} + +hal_gpio_status_t HAL_GpioDeinit(hal_gpio_handle_t gpioHandle) +{ + hal_gpio_state_t *gpioState; + GPIO_Type *gpioList[] = GPIO_BASE_PTRS; + + assert(gpioHandle); + + gpioState = (hal_gpio_state_t *)gpioHandle; + + if ((uint16_t)kHAL_GpioDirectionIn == gpioState->pin.direction) + { + GPIO_PortDisableInterrupts(gpioList[gpioState->pin.port], ((uint32_t)1U << gpioState->pin.pin)); + } + + (void)HAL_GpioRemoveItem(&s_GpioHead, gpioState); + return kStatus_HAL_GpioSuccess; +} + +hal_gpio_status_t HAL_GpioGetInput(hal_gpio_handle_t gpioHandle, uint8_t *pinState) +{ + hal_gpio_state_t *gpioStateHandle; + GPIO_Type *gpioList[] = GPIO_BASE_PTRS; + + assert(gpioHandle); + + gpioStateHandle = (hal_gpio_state_t *)gpioHandle; + + *pinState = ((0U != GPIO_PinRead(gpioList[gpioStateHandle->pin.port], gpioStateHandle->pin.pin)) ? 1U : 0U); + return kStatus_HAL_GpioSuccess; +} + +hal_gpio_status_t HAL_GpioSetOutput(hal_gpio_handle_t gpioHandle, uint8_t pinState) +{ + hal_gpio_state_t *gpioStateHandle; + GPIO_Type *gpioList[] = GPIO_BASE_PTRS; + + assert(gpioHandle); + + gpioStateHandle = (hal_gpio_state_t *)gpioHandle; + + GPIO_PinWrite(gpioList[gpioStateHandle->pin.port], gpioStateHandle->pin.pin, (0U != pinState) ? 1U : 0U); + return kStatus_HAL_GpioSuccess; +} + +hal_gpio_status_t HAL_GpioInstallCallback(hal_gpio_handle_t gpioHandle, + hal_gpio_callback_t callback, + void *callbackParam) +{ + hal_gpio_state_t *gpioStateHandle; + + assert(gpioHandle); + + gpioStateHandle = (hal_gpio_state_t *)gpioHandle; + + gpioStateHandle->callbackParam = callbackParam; + gpioStateHandle->callback = callback; + + return kStatus_HAL_GpioSuccess; +} + +hal_gpio_status_t HAL_GpioGetTriggerMode(hal_gpio_handle_t gpioHandle, hal_gpio_interrupt_trigger_t *gpioTrigger) +{ + hal_gpio_state_t *gpioStateHandle; + + assert(gpioHandle); + + gpioStateHandle = (hal_gpio_state_t *)gpioHandle; + + if (kHAL_GpioDirectionOut == (hal_gpio_direction_t)gpioStateHandle->pin.direction) + { + return kStatus_HAL_GpioError; + } + + *gpioTrigger = (hal_gpio_interrupt_trigger_t)gpioStateHandle->pin.trigger; + return kStatus_HAL_GpioSuccess; +} + +hal_gpio_status_t HAL_GpioSetTriggerMode(hal_gpio_handle_t gpioHandle, hal_gpio_interrupt_trigger_t gpioTrigger) +{ + hal_gpio_state_t *gpioStateHandle; + GPIO_Type *gpioList[] = GPIO_BASE_PTRS; + uint32_t regPrimask; + IRQn_Type gpioLowIRQsList[] = GPIO_COMBINED_LOW_IRQS; + IRQn_Type gpioHighIRQsList[] = GPIO_COMBINED_HIGH_IRQS; + gpio_interrupt_mode_t triggerType; + + assert(gpioHandle); + + gpioStateHandle = (hal_gpio_state_t *)gpioHandle; + + if (kHAL_GpioDirectionOut == (hal_gpio_direction_t)gpioStateHandle->pin.direction) + { + return kStatus_HAL_GpioError; + } + + switch (gpioTrigger) + { + case kHAL_GpioInterruptLogicZero: + triggerType = kGPIO_IntLowLevel; + break; + case kHAL_GpioInterruptLogicOne: + triggerType = kGPIO_IntHighLevel; + break; + case kHAL_GpioInterruptRisingEdge: + triggerType = kGPIO_IntRisingEdge; + break; + case kHAL_GpioInterruptFallingEdge: + triggerType = kGPIO_IntFallingEdge; + break; + case kHAL_GpioInterruptEitherEdge: + triggerType = kGPIO_IntRisingOrFallingEdge; + break; + default: + triggerType = kGPIO_NoIntmode; + break; + } + + gpioStateHandle->pin.trigger = (uint16_t)gpioTrigger; + + /* Disbale Global Interrupt */ + regPrimask = DisableGlobalIRQ(); + + /* initialize gpio interrupt */ + GPIO_PinSetInterruptConfig(gpioList[gpioStateHandle->pin.port], gpioStateHandle->pin.pin, triggerType); + + /* Enable IRQ */ + if (triggerType != kGPIO_NoIntmode) + { + GPIO_PortEnableInterrupts(gpioList[gpioStateHandle->pin.port], ((uint32_t)1 << gpioStateHandle->pin.pin)); + if (gpioStateHandle->pin.pin <= 15U) + { + NVIC_SetPriority(gpioLowIRQsList[gpioStateHandle->pin.port], HAL_GPIO_ISR_PRIORITY); + (void)EnableIRQ(gpioLowIRQsList[gpioStateHandle->pin.port]); + } + else + { + NVIC_SetPriority(gpioHighIRQsList[gpioStateHandle->pin.port], HAL_GPIO_ISR_PRIORITY); + (void)EnableIRQ(gpioHighIRQsList[gpioStateHandle->pin.port]); + } + } + else + { + GPIO_PortDisableInterrupts(gpioList[gpioStateHandle->pin.port], ((uint32_t)1 << gpioStateHandle->pin.pin)); + } + + /* Enable Global Interrupt */ + EnableGlobalIRQ(regPrimask); + + return kStatus_HAL_GpioSuccess; +} + +hal_gpio_status_t HAL_GpioWakeUpSetting(hal_gpio_handle_t gpioHandle, uint8_t enable) +{ + hal_gpio_state_t *gpioStateHandle; + assert(gpioHandle); + + gpioStateHandle = (hal_gpio_state_t *)gpioHandle; + + if (kHAL_GpioDirectionOut == (hal_gpio_direction_t)gpioStateHandle->pin.direction) + { + return kStatus_HAL_GpioError; + } + + return kStatus_HAL_GpioSuccess; +} + +hal_gpio_status_t HAL_GpioEnterLowpower(hal_gpio_handle_t gpioHandle) +{ + assert(gpioHandle); + + return kStatus_HAL_GpioSuccess; +} + +hal_gpio_status_t HAL_GpioExitLowpower(hal_gpio_handle_t gpioHandle) +{ + assert(gpioHandle); + + return kStatus_HAL_GpioSuccess; +} diff --git a/components/led/fsl_component_led.c b/components/led/fsl_component_led.c new file mode 100644 index 000000000..ffe23c3b4 --- /dev/null +++ b/components/led/fsl_component_led.c @@ -0,0 +1,806 @@ +/* + * Copyright 2018 - 2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_adapter_gpio.h" +#include "fsl_component_timer_manager.h" + +#include "fsl_component_led.h" +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) +#include "fsl_adapter_pwm.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(OSA_USED) +#include "fsl_os_abstraction.h" +#if (defined(USE_RTOS) && (USE_RTOS > 0U)) +#define LED_ENTER_CRITICAL() \ + OSA_SR_ALLOC(); \ + OSA_ENTER_CRITICAL() +#define LED_EXIT_CRITICAL() OSA_EXIT_CRITICAL() +#else +#define LED_ENTER_CRITICAL() +#define LED_EXIT_CRITICAL() +#endif +#else +#define LED_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ(); +#define LED_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask); +#endif + +/* LED control type enumeration */ +typedef enum _led_control_type +{ + kLED_TurnOffOn = 0x01U, /*!< Turn Off or on*/ + kLED_Flash, /*!< Flash */ +#if (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) + kLED_TricolorCycleFlash, /*!< Tricolor Cycle Flash */ + kLED_CycleFlash, /*!< Cycle Flash */ +#endif /* (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) */ + kLED_Dimming, /*!< Dimming */ +} led_control_type_t; + +/* LED Dimming state structure when dimming is enabled */ +typedef struct _led_dimming +{ + uint8_t increasement; + uint8_t powerDelta[sizeof(led_config_t) / sizeof(led_pin_config_t)]; +} led_dimming_t; + +/*! @brief The pin config struct of LED */ +typedef struct _led_pin +{ + union + { + struct + { + uint16_t type : 2U; /*!< LED type, 1 - RGB, 2 - Monochrome */ + uint16_t dimmingEnable : 1U; /*!< dimming enable, 0 - disable, 1 - enable */ + uint16_t : 13U; + } config; + struct + { + uint16_t : 3U; + uint16_t port : 4U; /*!< GPIO Port */ + uint16_t pin : 5U; /*!< GPIO Pin */ + uint16_t pinStateDefault : 1U; /*!< GPIO Pin voltage when LED is off (0 - low level, 1 - high level)*/ + uint16_t : 3U; + } gpio; + struct + { + uint16_t : 3U; + uint16_t instance : 4U; /*!< PWM instance of the pin */ + uint16_t channel : 5U; /*!< PWM channel of the pin */ + uint16_t pinStateDefault : 1U; /*!< The Pin voltage when LED is off (0 - low level, 1 - high level)*/ + uint16_t : 3U; + } dimming; + }; +} led_pin_t; + +/* LED state structure */ +typedef struct _led_state +{ + struct _led_state *next; + uint32_t gpioHandle[sizeof(led_config_t) / sizeof(led_pin_config_t)] + [((HAL_GPIO_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + volatile uint32_t expiryPeriodCount; +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) + uint32_t pwmHandle[sizeof(led_config_t) / sizeof(led_pin_config_t)] + [((HAL_PWM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; +#endif + uint32_t flashCycle; + led_color_t settingColor; + led_color_t currentColor; + led_color_t nextColor; +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + led_config_t *pinsConfig; +#else + led_pin_t pins[sizeof(led_config_t) / sizeof(led_pin_config_t)]; +#endif + uint16_t flashPeriod; +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) + led_dimming_t dimming; +#endif + struct + { + uint16_t controlType : 4U; +#if (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) + uint16_t flashCount : 3U; +#endif + uint16_t : 1U; + uint16_t flashDuty : 7U; + uint16_t : 1U; + }; +} led_state_t; + +typedef struct _led_list +{ + led_state_t *ledState; + volatile uint32_t periodCount; + TIMER_MANAGER_HANDLE_DEFINE(timerHandle); +} led_list_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +static led_list_t s_ledList; + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) +#pragma inline = never +#pragma optimize = no_inline +#elif defined(__GNUC__) +#endif + +static led_status_t LED_SetStatus(led_state_t *ledState, led_color_t color, uint32_t threshold) +{ +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + led_pin_config_t *ledRgbPin; +#else + led_pin_t *ledRgbPin; +#endif + led_status_t status = kStatus_LED_Success; + led_color_t colorSet; + uint8_t count = 1; + + ledState->expiryPeriodCount = s_ledList.periodCount + threshold; + +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + ledRgbPin = (led_pin_config_t *)(void *)&ledState->pinsConfig->ledRgb; +#else + ledRgbPin = (led_pin_t *)ledState->pins; +#endif + +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + if (kLED_TypeRgb == ledState->pinsConfig->type) +#else + if ((uint16_t)kLED_TypeRgb == ledRgbPin->config.type) +#endif + { + count = sizeof(led_config_t) / sizeof(led_pin_config_t); + } + + for (uint8_t i = 0; i < count; i++) + { + colorSet = ((color >> (i * 8U)) & (0xFFU)); +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + if (0U != ledRgbPin[i].dimmingEnable) +#else + if (0U != ledRgbPin[i].config.dimmingEnable) +#endif + { + (void)HAL_PwmUpdateDutycycle(ledState->pwmHandle[i], (uint8_t)ledRgbPin[i].dimming.channel, + kHAL_EdgeAlignedPwm, (uint8_t)(colorSet * 100U / 255U)); + } + else +#endif + { +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + (void)HAL_GpioSetOutput(ledState->gpioHandle[i], (colorSet != 0U) ? + (1U - (uint8_t)ledRgbPin[i].gpio.level) : + (uint8_t)ledRgbPin[i].gpio.level); +#else + (void)HAL_GpioSetOutput(ledState->gpioHandle[i], (colorSet != 0U) ? + (1U - (uint8_t)ledRgbPin[i].gpio.pinStateDefault) : + (uint8_t)ledRgbPin[i].gpio.pinStateDefault); +#endif + } + } + + return status; +} + +static void LED_TimerEvent(void *param) +{ + led_state_t *ledState = (led_state_t *)s_ledList.ledState; + uint32_t threshold = 0; + led_color_t color; +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) + uint16_t power[sizeof(led_config_t) / sizeof(led_pin_config_t)]; + uint8_t count = sizeof(led_config_t) / sizeof(led_pin_config_t); +#endif + + s_ledList.periodCount += LED_TIMER_INTERVAL; + + while (NULL != ledState) + { + if (s_ledList.periodCount >= ledState->expiryPeriodCount) + { + switch (ledState->controlType) + { + case (uint16_t)kLED_Flash: /*!< Flash */ +#if (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) + case (uint16_t)kLED_TricolorCycleFlash: /*!< Tricolor Cycle Flash */ + case (uint16_t)kLED_CycleFlash: /*!< Cycle Flash */ +#endif /* (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) */ + if (LED_FLASH_CYCLE_FOREVER != ledState->flashCycle) + { + if ((0U != ledState->flashCycle)) + { + if (((led_color_t)kLED_Black == ledState->currentColor) || (100U == ledState->flashDuty)) + { + ledState->flashCycle--; + } + } + } + if (0U != ledState->flashCycle) + { + if ((100U > ledState->flashDuty)) + { + color = ledState->nextColor; + ledState->nextColor = ledState->currentColor; + ledState->currentColor = color; + } + + if (((led_color_t)kLED_Black == ledState->currentColor)) + { + threshold = (uint32_t)ledState->flashPeriod * (100U - (uint32_t)ledState->flashDuty) / 100U; + } + else + { +#if (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) + ledState->flashCount++; + if ((uint16_t)kLED_TricolorCycleFlash == ledState->controlType) + { + ledState->currentColor = (led_color_t)(0xFFUL << ((ledState->flashCount % 3U) * 8U)); + } + else if ((uint16_t)kLED_CycleFlash == ledState->controlType) + { + color = 0; + if (0U == ((ledState->flashCount) & 0x07U)) + { + (ledState->flashCount)++; + } + if (0U != ((ledState->flashCount) & 0x04U)) + { + color = (led_color_t)0xFF0000; + } + if (0U != ((ledState->flashCount) & 0x02U)) + { + color |= (led_color_t)0xFF00; + } + if (0U != ((ledState->flashCount) & 0x01U)) + { + color |= (led_color_t)0xFF; + } + ledState->currentColor = color; + } + else + { + /*Misra Rule 15.7*/ + } +#endif /* (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) */ + threshold = (uint32_t)ledState->flashPeriod * (uint32_t)(ledState->flashDuty) / 100U; + } + + (void)LED_SetStatus(ledState, ledState->currentColor, threshold); + } + break; +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) + case (uint16_t)kLED_Dimming: /*!< Dimming */ + for (uint8_t i = 0; i < count; i++) + { + uint8_t value = (uint8_t)((ledState->currentColor >> (8U * i)) & 0xFFU); + if (0U != ledState->dimming.increasement) + { + if ((value + ledState->dimming.powerDelta[i]) < 0xFFU) + { + power[i] = (uint16_t)value + (uint16_t)ledState->dimming.powerDelta[i]; + } + else + { + power[i] = 0xFFU; + } + } + else + { + if (value > ledState->dimming.powerDelta[i]) + { + power[i] = (uint16_t)value - (uint16_t)ledState->dimming.powerDelta[i]; + } + else + { + power[i] = 0; + } + } + +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + if (kLED_TypeMonochrome == ledState->pinsConfig->type) +#else + if ((uint16_t)kLED_TypeMonochrome == ledState->pins[0].config.type) +#endif + { + break; + } + } + ledState->currentColor = LED_MAKE_COLOR(power[0], power[1], power[2]); + (void)LED_SetStatus(ledState, ledState->currentColor, ledState->flashPeriod); + break; +#endif + default: + /* MISRA Rule 16.4*/ + break; + } + } + ledState = ledState->next; + } +} + +led_status_t LED_Init(led_handle_t ledHandle, led_config_t *ledConfig) +{ + led_state_t *ledState; + led_pin_config_t *ledRgbConfigPin; +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) +#else + hal_gpio_pin_config_t controlPin; +#endif + uint32_t count = 1; + uint32_t regPrimask; + int i; +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) + /* The configure parameters check only work on debug mode in order to reduce code size. */ +#ifdef NDEBUG +#else /* NDEBUG */ + uint8_t rgbFlag = 0; + uint8_t rgbDimmingFlag = 0; +#endif /* NDEBUG */ +#endif + + assert((NULL != ledHandle) && (NULL != ledConfig)); + assert(LED_HANDLE_SIZE >= sizeof(led_state_t)); + + if (kLED_TypeRgb == ledConfig->type) + { + count = sizeof(led_config_t) / sizeof(led_pin_config_t); + } + + ledState = (led_state_t *)ledHandle; + + (void)memset(ledHandle, 0, sizeof(led_state_t)); + + regPrimask = DisableGlobalIRQ(); + if (NULL == s_ledList.ledState) + { + do + { + timer_status_t tmState; + tmState = TM_Open((timer_handle_t)s_ledList.timerHandle); + assert(kStatus_TimerSuccess == tmState); + + tmState = TM_InstallCallback(s_ledList.timerHandle, LED_TimerEvent, &s_ledList); + assert(kStatus_TimerSuccess == tmState); + + tmState = TM_Start(s_ledList.timerHandle, (uint8_t)kTimerModeIntervalTimer, LED_TIMER_INTERVAL); + assert(kStatus_TimerSuccess == tmState); + (void)tmState; + + s_ledList.ledState = ledState; + } while (false); + } + else + { + ledState->next = s_ledList.ledState; + s_ledList.ledState = ledState; + } + EnableGlobalIRQ(regPrimask); + + assert(s_ledList.ledState); + ledState->settingColor = (led_color_t)kLED_White; + ledRgbConfigPin = (led_pin_config_t *)(void *)&ledConfig->ledRgb; + +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + ledState->pinsConfig = ledConfig; +#else + controlPin.direction = kHAL_GpioDirectionOut; +#endif +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) + /* The configure parameters check only work on debug mode in order to reduce code size. */ +#ifdef NDEBUG +#else /* NDEBUG */ + for (i = 0; i < (int)count; i++) + { + if (0U != ledRgbConfigPin[i].dimmingEnable) + { + rgbDimmingFlag = 1; + } + else + { + rgbFlag = 1; + } + } + assert(!((0U != rgbDimmingFlag) && (0U != rgbFlag))); +#endif /* NDEBUG */ +#endif + for (i = 0; i < (int)count; i++) + { +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) +#else + ledState->pins[i].config.type = (uint16_t)ledConfig->type; +#endif +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) + if (0U != ledRgbConfigPin[i].dimmingEnable) + { + hal_pwm_setup_config_t setupConfig; +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) +#else + ledState->pins[i].config.dimmingEnable = ledRgbConfigPin[i].dimmingEnable; + ledState->pins[i].dimming.instance = ledRgbConfigPin[i].dimming.instance; + ledState->pins[i].dimming.channel = ledRgbConfigPin[i].dimming.channel; + ledState->pins[i].dimming.pinStateDefault = ledRgbConfigPin[i].dimming.pinStateDefault; +#endif + (void)HAL_PwmInit((hal_pwm_handle_t)ledState->pwmHandle[i], ledRgbConfigPin[i].dimming.instance, + ledRgbConfigPin[i].dimming.sourceClock); + setupConfig.dutyCyclePercent = 0; + setupConfig.level = (0U != ledRgbConfigPin[i].dimming.pinStateDefault) ? + (hal_pwm_level_select_t)kHAL_PwmLowTrue : + (hal_pwm_level_select_t)kHAL_PwmHighTrue; + setupConfig.mode = kHAL_EdgeAlignedPwm; + setupConfig.pwmFreq_Hz = 1000U; + (void)HAL_PwmSetupPwm(ledState->pwmHandle[i], ledRgbConfigPin[i].dimming.channel, &setupConfig); + } + else +#endif + { +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) +#else + ledState->pins[i].gpio.port = ledRgbConfigPin[i].gpio.port; + ledState->pins[i].gpio.pin = ledRgbConfigPin[i].gpio.pin; + ledState->pins[i].gpio.pinStateDefault = ledRgbConfigPin[i].gpio.pinStateDefault; + controlPin.port = ledRgbConfigPin[i].gpio.port; + controlPin.pin = ledRgbConfigPin[i].gpio.pin; + controlPin.level = ledRgbConfigPin[i].gpio.pinStateDefault; +#endif + +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + if (kStatus_HAL_GpioSuccess != HAL_GpioInit((hal_gpio_handle_t)ledState->gpioHandle[i], + (hal_gpio_pin_config_t *)&ledRgbConfigPin[i].gpio)) +#else + if (kStatus_HAL_GpioSuccess != HAL_GpioInit((hal_gpio_handle_t)ledState->gpioHandle[i], &controlPin)) +#endif + { + return kStatus_LED_Error; + } + } + } + + return LED_TurnOnOff(ledState, 0); +} + +led_status_t LED_Deinit(led_handle_t ledHandle) +{ + led_state_t *ledState; + led_state_t *ledStatePre; + uint32_t regPrimask; +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + led_pin_config_t *ledRgbPin; +#else + led_pin_t *ledRgbPin; +#endif +#endif + + assert(ledHandle); + + ledState = (led_state_t *)ledHandle; + + regPrimask = DisableGlobalIRQ(); + ledStatePre = s_ledList.ledState; + if (ledStatePre != ledState) + { + while ((NULL != ledStatePre) && (ledStatePre->next != ledState)) + { + ledStatePre = ledStatePre->next; + } + if (NULL != ledStatePre) + { + ledStatePre->next = ledState->next; + } + } + else + { + s_ledList.ledState = ledState->next; + } + + if (NULL == s_ledList.ledState) + { + (void)TM_Close(s_ledList.timerHandle); + } + EnableGlobalIRQ(regPrimask); + +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + ledRgbPin = (led_pin_config_t *)(void *)&ledState->pinsConfig->ledRgb; +#else + ledRgbPin = (led_pin_t *)(ledState->pins); +#endif +#endif + for (uint32_t i = 0; i < (sizeof(led_config_t) / sizeof(led_pin_config_t)); i++) + { +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + if (0U != ledRgbPin[i].dimmingEnable) +#else + if (0u != ledRgbPin[i].config.dimmingEnable) +#endif + { + HAL_PwmDeinit(ledState->pwmHandle[i]); + } + else +#endif + { + (void)HAL_GpioDeinit(ledState->gpioHandle[i]); + } +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + if (kLED_TypeRgb != ledState->pinsConfig->type) +#else + if (((uint16_t)kLED_TypeRgb != ledState->pins[i].config.type)) +#endif + { + break; + } + } + + return kStatus_LED_Success; +} + +led_status_t LED_TurnOnOff(led_handle_t ledHandle, uint8_t turnOnOff) +{ + led_state_t *ledState; + + assert(ledHandle); + + ledState = (led_state_t *)ledHandle; + ledState->controlType = (uint16_t)kLED_TurnOffOn; + ledState->currentColor = (1U == turnOnOff) ? ledState->settingColor : (led_color_t)kLED_Black; + (void)LED_SetStatus(ledState, ledState->currentColor, 0); + return kStatus_LED_Success; +} + +led_status_t LED_SetColor(led_handle_t ledHandle, led_color_t ledRgbColor) +{ + led_state_t *ledState; + + assert(ledHandle); + + ledState = (led_state_t *)ledHandle; +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + assert(kLED_TypeRgb == ledState->pinsConfig->type); +#else + assert((uint16_t)kLED_TypeRgb == ledState->pins[0].config.type); +#endif + + ledState->settingColor = ledRgbColor; + + return kStatus_LED_Success; +} + +led_status_t LED_Flash(led_handle_t ledHandle, led_flash_config_t *ledFlash) +{ + led_state_t *ledState; + + assert(ledHandle); + assert(ledFlash); + assert(ledFlash->times); + assert(ledFlash->duty <= 100U); + + ledState = (led_state_t *)ledHandle; + + ledState->flashPeriod = ledFlash->period; + ledState->flashDuty = ledFlash->duty; + + ledState->currentColor = ledState->settingColor; + ledState->flashCycle = ledFlash->times; + ledState->nextColor = (led_color_t)kLED_Black; + +#if (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) + if (kLED_FlashOneColor == ledFlash->flashType) + { + ledState->controlType = (uint16_t)kLED_Flash; + } + else + { +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + assert(kLED_TypeRgb == ledState->pinsConfig->type); +#else + assert((uint16_t)kLED_TypeRgb == ledState->pins[0].config.type); +#endif + ledState->controlType = (uint16_t)kLED_CycleFlash; + } +#else + ledState->controlType = (uint16_t)kLED_Flash; +#endif /* (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) */ + (void)LED_SetStatus(ledState, ledState->currentColor, + ((uint32_t)ledState->flashPeriod * (uint32_t)ledState->flashDuty) / 100U); + return kStatus_LED_Success; +} + +led_status_t LED_Blip(led_handle_t ledHandle) +{ + led_flash_config_t ledFlash; + + ledFlash.duty = 50; + ledFlash.flashType = kLED_FlashOneColor; + ledFlash.period = LED_BLIP_INTERVAL; + ledFlash.times = 1; + return LED_Flash(ledHandle, &ledFlash); +} + +led_status_t LED_Dimming(led_handle_t ledHandle, uint16_t dimmingPeriod, uint8_t increasement) +{ +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) + led_state_t *ledState; + uint16_t power[sizeof(led_config_t) / sizeof(led_pin_config_t)]; + uint8_t value; + uint8_t count = sizeof(led_config_t) / sizeof(led_pin_config_t); + + assert(ledHandle); + assert(dimmingPeriod); + + ledState = (led_state_t *)ledHandle; + +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + assert(ledState->pinsConfig->ledRgb.redPin.dimmingEnable); +#else + assert(ledState->pins[0].config.dimmingEnable); +#endif + + LED_ENTER_CRITICAL(); + + ledState->controlType = (uint16_t)kLED_Dimming; + ledState->flashPeriod = LED_DIMMING_UPDATE_INTERVAL; + ledState->flashDuty = 100U; + ledState->dimming.increasement = increasement; + +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + if (kLED_TypeRgb == ledState->pinsConfig->type) +#else + if ((uint16_t)kLED_TypeRgb == ledState->pins[0].config.type) +#endif + { + ledState->currentColor = ledState->settingColor; + } + + for (uint8_t i = 0U; i < count; i++) + { + ledState->dimming.powerDelta[i] = 0U; + } + + for (uint8_t i = 0U; i < count; i++) + { + value = (uint8_t)((ledState->currentColor >> (8U * (i))) & 0xFFU); + if (0U != ledState->dimming.increasement) + { + ledState->dimming.powerDelta[i] = + (uint8_t)(((uint16_t)0xFF - value) * LED_DIMMING_UPDATE_INTERVAL / (dimmingPeriod)); + if ((value + ledState->dimming.powerDelta[i]) < 0xFFU) + { + power[i] = (uint16_t)value + ledState->dimming.powerDelta[i]; + } + else + { + power[i] = 0xFFU; + } + } + else + { + ledState->dimming.powerDelta[i] = + (uint8_t)((uint16_t)(value)*LED_DIMMING_UPDATE_INTERVAL / (dimmingPeriod)); + if (value > ledState->dimming.powerDelta[i]) + { + power[i] = (uint16_t)value - (uint16_t)ledState->dimming.powerDelta[i]; + } + else + { + power[i] = 0U; + } + } +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + if (kLED_TypeMonochrome == ledState->pinsConfig->type) +#else + if ((uint16_t)kLED_TypeMonochrome == ledState->pins[0].config.type) +#endif + { + break; + } + } + + ledState->currentColor = LED_MAKE_COLOR(power[0], power[1], power[2]); + ledState->flashCycle = LED_FLASH_CYCLE_FOREVER; + LED_EXIT_CRITICAL(); + (void)LED_SetStatus(ledState, ledState->currentColor, ledState->flashPeriod); + + return kStatus_LED_Success; +#else + return kStatus_LED_Error; +#endif +} + +led_status_t LED_EnterLowpower(led_handle_t ledHandle) +{ +#if 0 + led_state_t* ledState; + led_pin_config_t* ledRgbPin; + led_status_t status; + int count; + + assert(ledHandle); + + ledState = (led_state_t*)ledHandle; + + ledRgbPin = (led_pin_config_t*)&ledState->config.ledRgb; + if (kLED_TypeRgb == ledState->config.type) + { + count = sizeof(led_config_t) / sizeof(led_pin_config_t); + } + else + { + count = 1; + } + + for (int i = 0;i < count; i++) + { +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) + if (ledRgbPin[i].dimmingEnable) + { + HAL_PwmEnterLowpower(ledRgbPin[i].dimming.instance, ledRgbPin[i].dimming.channel); + } + else +#endif + { + HAL_GpioEnterLowpower(ledState->gpioHandle[i]); + } + } +#endif + return kStatus_LED_Success; +} + +led_status_t LED_ExitLowpower(led_handle_t ledHandle) +{ +#if 0 + led_state_t* ledState; + led_pin_config_t* ledRgbPin; + led_status_t status; + int count; + + assert(ledHandle); + + ledState = (led_state_t*)ledHandle; + + ledRgbPin = (led_pin_config_t*)&ledState->config.ledRgb; + if (kLED_TypeRgb == ledState->config.type) + { + count = sizeof(led_config_t) / sizeof(led_pin_config_t); + } + else + { + count = 1; + } + + for (int i = 0;i < count; i++) + { +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) + if (ledRgbPin[i].dimmingEnable) + { + HAL_PwmExitLowpower(ledRgbPin[i].dimming.instance, ledRgbPin[i].dimming.channel); + } + else +#endif + { + HAL_GpioExitLowpower(ledState->gpioHandle[i]); + } + } +#endif + return kStatus_LED_Success; +} diff --git a/components/led/fsl_component_led.h b/components/led/fsl_component_led.h new file mode 100644 index 000000000..034eedb1c --- /dev/null +++ b/components/led/fsl_component_led.h @@ -0,0 +1,393 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __LED_H__ +#define __LED_H__ + +#include "fsl_common.h" +#include "fsl_adapter_gpio.h" +/*! + * @addtogroup LED + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Definition to determine whether enable dimming. */ +#ifndef LED_DIMMING_ENABLEMENT +#define LED_DIMMING_ENABLEMENT (0U) /*!< Enable or disable the dimming feature */ +#endif + +/*! @brief Definition to determine whether enable color wheel. */ +#ifndef LED_COLOR_WHEEL_ENABLEMENT +#define LED_COLOR_WHEEL_ENABLEMENT (0U) /*!< Enable or disable the color wheel feature */ +#endif + +/*! @brief Definition to determine whether use confgure structure. */ +#ifndef LED_USE_CONFIGURE_STRUCTURE +#define LED_USE_CONFIGURE_STRUCTURE (1U) /*!< Enable or disable the confgure structure pointer */ +#endif +/*! @brief The handle of LED */ +typedef void *led_handle_t; + +/*! @brief Definition of LED handle size. */ +#if (defined(LED_DIMMING_ENABLEMENT) && (LED_DIMMING_ENABLEMENT > 0U)) +/* HAL_GPIO_HANDLE_SIZE * 3 + HAL_PWM_HANDLE_SIZE *3 + LED dedicated size */ +#define LED_HANDLE_SIZE ((16U * 3U) + (8U * 3U) + 40U) +#else +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) +/* HAL_GPIO_HANDLE_SIZE * 3 + LED dedicated size */ +#define LED_HANDLE_SIZE ((16U * 3U) + 32U) +#else +/* HAL_GPIO_HANDLE_SIZE * 3 + LED dedicated size */ +#define LED_HANDLE_SIZE ((16U * 3U) + 36U) +#endif +#endif + +/*! + * @brief Defines the led handle + * + * This macro is used to define a 4 byte aligned led handle. + * Then use "(led_handle_t)name" to get the led handle. + * + * The macro should be global and could be optional. You could also define led handle by yourself. + * + * This is an example, + * @code + * LED_HANDLE_DEFINE(ledHandle); + * @endcode + * + * @param name The name string of the led handle. + */ +#define LED_HANDLE_DEFINE(name) uint32_t name[((LED_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] + +/*! + * @brief Defines the led handle array + * + * This macro is used to define a 4 byte aligned led handle array. + * Then use "(led_handle_t)name[0]" to get the first led handle. + * + * The macro should be global and could be optional. You could also define these led handle by yourself. + * + * This is an example, + * @code + * LED_HANDLE_ARRAY_DEFINE(ledHandleArray,1); + * @endcode + * + * @param name The name string of the led handle array. + * @param count The amount of led handle. + */ +#define LED_HANDLE_ARRAY_DEFINE(name, count) \ + uint32_t name[count][((LED_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] + +/*! @brief Definition of LED timer interval,unit is ms. */ +#define LED_TIMER_INTERVAL (100U) + +/*! @brief Definition of LED dimming update interval,unit is ms. */ +#define LED_DIMMING_UPDATE_INTERVAL (100U) + +/*! @brief Definition of LED flash cycle forever. */ +#define LED_FLASH_CYCLE_FOREVER (0xFFFFFFFFU) + +/*! @brief Definition of LED blip interval,unit is ms. */ +#define LED_BLIP_INTERVAL (250U) + +/*! @brief The status type of LED */ +typedef enum _led_status +{ + kStatus_LED_Success = kStatus_Success, /*!< Success */ + kStatus_LED_Error = MAKE_STATUS(kStatusGroup_LED, 1), /*!< Failed */ + kStatus_LED_InvalidParameter = MAKE_STATUS(kStatusGroup_LED, 2), /*!< Invalid parameter*/ +} led_status_t; + +/*! @brief The flash type of LED */ +typedef enum _led_flash_type +{ + kLED_FlashOneColor = 0x00U, /*!< Fast with one color */ +#if (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) + kLED_FlashColorWheel, /*!< Fast with color wheel */ +#endif /* (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) */ +} led_flash_type_t; + +/*! @brief The color struct of LED */ +typedef uint32_t led_color_t; + +/*! @brief Definition to set LED color. */ +#define LED_MAKE_COLOR(r, g, b) ((led_color_t)((((led_color_t)b) << 16) | (((led_color_t)g) << 8) | ((led_color_t)r))) + +/*! @brief The color type of LED */ +enum _led_color +{ + kLED_Black = LED_MAKE_COLOR(0, 0, 0), /*!< Black */ + kLED_Red = LED_MAKE_COLOR(255, 0, 0), /*!< Red */ + kLED_Green = LED_MAKE_COLOR(0, 255, 0), /*!< Green */ + kLED_Yellow = LED_MAKE_COLOR(255, 255, 0), /*!< Yellow */ + kLED_Blue = LED_MAKE_COLOR(0, 0, 255), /*!< Blue */ + kLED_Pink = LED_MAKE_COLOR(255, 0, 255), /*!< Pink */ + kLED_Aquamarine = LED_MAKE_COLOR(0, 255, 255), /*!< Aquamarine */ + kLED_White = LED_MAKE_COLOR(255, 255, 255), /*!< White */ +}; + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +/*! @brief The pin config struct of LED */ +typedef struct _led_pin_config +{ + uint8_t dimmingEnable; /*!< dimming enable, 0 - disable, 1 - enable */ + union + { +#if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) + hal_gpio_pin_config_t gpio; +#else + struct + { + uint8_t port; /*!< GPIO Port */ + uint8_t pin; /*!< GPIO Pin */ + uint8_t pinStateDefault; /*!< GPIO Pin voltage when LED is off (0 - low level, 1 - high level)*/ + } gpio; +#endif + struct + { + uint32_t sourceClock; /*!< The clock source of the PWM module */ + uint8_t instance; /*!< PWM instance of the pin */ + uint8_t channel; /*!< PWM channel of the pin */ + uint8_t pinStateDefault; /*!< The Pin voltage when LED is off (0 - low level, 1 - high level)*/ + } dimming; + }; +} led_pin_config_t; + +/*! @brief The pin config struct of rgb LED */ +typedef struct _led_rgb_config +{ + led_pin_config_t redPin; /*!< Red pin setting */ + led_pin_config_t greenPin; /*!< Green pin setting */ + led_pin_config_t bluePin; /*!< Blue pin setting */ +} led_rgb_config_t; + +/*! @brief The pin config struct of monochrome LED */ +typedef struct _led_monochrome_config +{ + led_pin_config_t monochromePin; /*!< Monochrome pin setting */ +} led_monochrome_config_t; + +/*! @brief The type of LED */ +typedef enum _led_type +{ + kLED_TypeRgb = 0x01U, /*!< RGB LED */ + kLED_TypeMonochrome = 0x02U, /*!< Monochrome LED */ +} led_type_t; + +/*! @brief The config struct of LED */ +typedef struct _led_config +{ + led_type_t type; + union + { + led_rgb_config_t ledRgb; /*!< RGB setting */ + led_monochrome_config_t ledMonochrome; /*!< Monochrome setting */ + }; +} led_config_t; + +/*! @brief The flash config struct of LED */ +typedef struct _led_flash_config +{ + uint32_t times; /*!< Flash times, LED_FLASH_CYCLE_FOREVER for forever */ + uint16_t period; /*!< Flash period, unit is ms */ + led_flash_type_t flashType; /*!< Flash type, one color or color wheel. Refer to #led_flash_type_t */ + uint8_t duty; /*!< Duty of the LED on for one period (duration = duty * period / 100). */ +} led_flash_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @brief Initializes a LED with the LED handle and the user configuration structure. + * + * This function configures the LED with user-defined settings. The user can configure the configuration + * structure. The parameter ledHandle is a pointer to point to a memory space of size #LED_HANDLE_SIZE allocated by the + * caller. The LED supports two types LED, RGB and monochrome. Please refer to #led_type_t. These two types can be set + * by using #led_config_t. The LED also supports LED dimming mode. + * + * Example below shows how to use this API to configure the LED. + * For monochrome LED, + * @code + * static LED_HANDLE_DEFINE(s_ledMonochromeHandle); + * led_config_t ledMonochromeConfig; + * ledMonochromeConfig.type = kLED_TypeMonochrome; + * ledMonochromeConfig.ledMonochrome.monochromePin.dimmingEnable = 0; + * ledMonochromeConfig.ledMonochrome.monochromePin.gpio.port = 0; + * ledMonochromeConfig.ledMonochrome.monochromePin.gpio.pin = 1; + * ledMonochromeConfig.ledMonochrome.monochromePin.gpio.pinStateDefault = 0; + * LED_Init((led_handle_t)s_ledMonochromeHandle, &ledMonochromeConfig); + * @endcode + * For rgb LED, + * @code + * static LED_HANDLE_DEFINE(s_ledRgbHandle); + * led_config_t ledRgbConfig; + * ledRgbConfig.type = kLED_TypeRgb; + * ledRgbConfig.ledRgb.redPin.dimmingEnable = 0; + * ledRgbConfig.ledRgb.redPin.gpio.port = 0; + * ledRgbConfig.ledRgb.redPin.gpio.pin = 1; + * ledRgbConfig.ledRgb.redPin.gpio.pinStateDefault = 0; + * ledRgbConfig.ledRgb.greenPin.dimmingEnable = 0; + * ledRgbConfig.ledRgb.greenPin.gpio.port = 0; + * ledRgbConfig.ledRgb.greenPin.gpio.pin = 2; + * ledRgbConfig.ledRgb.greenPin.gpio.pinStateDefault = 0; + * ledRgbConfig.ledRgb.bluePin.dimmingEnable = 0; + * ledRgbConfig.ledRgb.bluePin.gpio.port = 0; + * ledRgbConfig.ledRgb.bluePin.gpio.pin = 3; + * ledRgbConfig.ledRgb.bluePin.gpio.pinStateDefault = 0; + * LED_Init((led_handle_t)s_ledRgbHandle, &ledRgbConfig); + * @endcode + * For dimming monochrome LED, + * @code + * static LED_HANDLE_DEFINE(s_ledMonochromeHandle); + * led_config_t ledMonochromeConfig; + * ledMonochromeConfig.type = kLED_TypeMonochrome; + * ledMonochromeConfig.ledMonochrome.monochromePin.dimmingEnable = 1; + * ledMonochromeConfig.ledMonochrome.monochromePin.dimming.sourceClock = 48000000; + * ledMonochromeConfig.ledMonochrome.monochromePin.dimming.instance = 0; + * ledMonochromeConfig.ledMonochrome.monochromePin.dimming.channel = 1; + * ledMonochromeConfig.ledMonochrome.monochromePin.dimming.pinStateDefault = 0; + * LED_Init((led_handle_t)s_ledMonochromeHandle, &ledMonochromeConfig); + * @endcode + * For multiple LEDs, + * @code + * static LED_HANDLE_ARRAY_DEFINE(s_ledArrayHandle, count); + * led_config_t ledArrayConfig[count]; + * for(uint8_t i = 0; i < count; i++ ) + * { + * ledArrayConfig[i].type = kLED_TypeMonochrome; + * ledArrayConfig[i].ledMonochrome.monochromePin.dimmingEnable = 1; + * ledArrayConfig[i].ledMonochrome.monochromePin.dimming.sourceClock = 48000000; + * ledArrayConfig[i].ledMonochrome.monochromePin.dimming.instance = 0; + * ledArrayConfig[i].ledMonochrome.monochromePin.dimming.channel = 1; + * ledArrayConfig[i].ledMonochrome.monochromePin.dimming.pinStateDefault = 0; + * LED_Init((led_handle_t)s_ledArrayHandle[i], &ledArrayConfig[i]); + * } + * @endcode + * + * @param ledHandle Pointer to point to a memory space of size #LED_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define one handle in the following two ways: + * #LED_HANDLE_DEFINE(ledHandle); + * or + * uint32_t ledHandle[((LED_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * You can define multiple handles in the following way: + * #LED_HANDLE_ARRAY_DEFINE(ledHandleArray, count); + * @param ledConfig Pointer to user-defined configuration structure. + * please note, if the LED_USE_CONFIGURE_STRUCTURE is set to 1, then user must use const buffer + * forledConfig, LED module will directly use the const buffer. + * @retval kStatus_LED_Error An error occurred. + * @retval kStatus_LED_Success LED initialization succeed. + */ +led_status_t LED_Init(led_handle_t ledHandle, led_config_t *ledConfig); + +/*! + * @brief Deinitializes a LED instance. + * + * This function deinitializes the LED instance. + * + * @param ledHandle LED handle pointer. + * @retval kStatus_LED_Success LED de-initialization succeed. + */ +led_status_t LED_Deinit(led_handle_t ledHandle); + +/*! + * @brief Sets the LED color. + * + * This function sets the LED color. The function only supports the RGB LED. + * The default color is #kLED_White. Please refer to #LED_MAKE_COLOR(r,g,b). + * + * @param ledHandle LED handle pointer. + * @param ledRgbColor LED color. + * @retval kStatus_LED_Error An error occurred. + * @retval kStatus_LED_Success Color setting succeed. + */ +led_status_t LED_SetColor(led_handle_t ledHandle, led_color_t ledRgbColor); + +/*! + * @brief Turns on or off the LED. + * + * This function turns on or off the led. + * + * @param ledHandle LED handle pointer. + * @param turnOnOff Setting value, 1 - turns on, 0 - turns off. + * @retval kStatus_LED_Error An error occurred. + * @retval kStatus_LED_Success Successfully turn on or off the LED. + */ +led_status_t LED_TurnOnOff(led_handle_t ledHandle, uint8_t turnOnOff); + +/*! + * @brief Blips the LED. + * + * This function blips the led. + * + * @param ledHandle LED handle pointer. + * @retval kStatus_LED_Error An error occurred. + * @retval kStatus_LED_Success Successfully blip the LED. + */ +led_status_t LED_Blip(led_handle_t ledHandle); + +/*! + * @brief Flashes the LED. + * + * This function flashes the led. The flash configuration is passed by using #led_flash_config_t. + * + * @param ledHandle LED handle pointer. + * @param ledFlash LED flash configuration. + * @retval kStatus_LED_Error An error occurred. + * @retval kStatus_LED_Success Successfully flash the LED. + */ +led_status_t LED_Flash(led_handle_t ledHandle, led_flash_config_t *ledFlash); + +/*! + * @brief Adjusts the brightness of the LED. + * + * This function adjust the brightness of the LED. + * + * @param ledHandle LED handle pointer. + * @param dimmingPeriod The duration of the dimming (unit is ms). + * @param increasement Brighten or dim (1 - brighten, 0 - dim). + * @retval kStatus_LED_Error An error occurred. + * @retval kStatus_LED_Success Successfully adjust the brightness of the LED. + */ +led_status_t LED_Dimming(led_handle_t ledHandle, uint16_t dimmingPeriod, uint8_t increasement); + +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @param ledHandle LED handle pointer. + * @retval kStatus_LED_Success Successful operation. + */ +led_status_t LED_EnterLowpower(led_handle_t ledHandle); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @param ledHandle LED handle pointer. + * @retval kStatus_LED_Success Successful operation. + */ +led_status_t LED_ExitLowpower(led_handle_t ledHandle); + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /* __LED_H__ */ diff --git a/components/lists/component_lists_MIMX8MQ6.cmake b/components/lists/component_lists_MIMX8MQ6.cmake new file mode 100644 index 000000000..2aae8b7c7 --- /dev/null +++ b/components/lists/component_lists_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("component_lists component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_component_generic_list.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/components/mem_manager/fsl_component_mem_manager.c b/components/mem_manager/fsl_component_mem_manager.c new file mode 100644 index 000000000..43a5941b9 --- /dev/null +++ b/components/mem_manager/fsl_component_mem_manager.c @@ -0,0 +1,747 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#if defined(MEM_STATISTICS_INTERNAL) || defined(MEM_MANAGER_BENCH) +#include "fsl_component_timer_manager.h" +#include "fsl_component_mem_manager_internal.h" +#endif /* MEM_STATISTICS_INTERNAL MEM_MANAGER_BENCH*/ +#include "fsl_component_mem_manager.h" +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) +#include "fsl_debug_console.h" +#endif + +#if defined(OSA_USED) +#include "fsl_os_abstraction.h" +#if (defined(USE_RTOS) && (USE_RTOS > 0U)) +#define MEM_ENTER_CRITICAL() \ + OSA_SR_ALLOC(); \ + OSA_ENTER_CRITICAL() +#define MEM_EXIT_CRITICAL() OSA_EXIT_CRITICAL() +#else +#define MEM_ENTER_CRITICAL() +#define MEM_EXIT_CRITICAL() +#endif +#else +#define MEM_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ(); +#define MEM_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask); +#endif +#if !defined(gMemManagerLight) || (gMemManagerLight == 0) +/***************************************************************************** +****************************************************************************** +* Private macros +****************************************************************************** +*****************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) +#define __mem_get_LR() __get_LR() +#elif defined(__GNUC__) +#define __mem_get_LR() __builtin_return_address(0) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define __mem_get_LR() __return_address() +#endif + +#if (defined(MEM_MANAGER_PRE_CONFIGURE) && (MEM_MANAGER_PRE_CONFIGURE > 0U)) +#undef _block_set_ +#undef _eol_ + +#define _eol_ ; +#define _block_set_ MEM_BLOCK_BUFFER_NONAME_DEFINE + +PoolsDetails_c + +#undef _block_set_ +#undef _number_of_blocks_ +#undef _eol_ +#undef _pool_id_ + +#define _eol_ , +#define _block_set_ MEM_BLOCK_NONAME_BUFFER + + static uint8_t const *s_PoolList[] = {PoolsDetails_c}; +#endif /*MEM_MANAGER_PRE_CONFIGURE*/ + +/***************************************************************************** +****************************************************************************** +* Private type definitions +****************************************************************************** +*****************************************************************************/ +/*! @brief Buffer pools structure*/ +typedef struct _mem_pool_structure +{ + struct _mem_pool_structure *nextPool; + uint8_t *pHeap; + uint32_t heapSize; +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) + uint16_t allocatedBlocksPeak; + uint16_t poolFragmentWaste; + uint16_t poolTotalFragmentWaste; + uint16_t poolFragmentWastePeak; + uint16_t poolFragmentMinWaste; +#endif /*MEM_MANAGER_ENABLE_TRACE*/ + uint16_t poolId; + uint16_t blockSize; + uint16_t numBlocks; + uint16_t allocatedBlocks; +} mem_pool_structure_t; + +/*! @brief Header description for buffers.*/ +typedef struct _block_list_header +{ + uint16_t allocated; + uint16_t blockSize; +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) + uint32_t caller; + uint16_t allocatedBytes; +#endif /*MEM_MANAGER_ENABLE_TRACE*/ +} block_list_header_t; + +/*! @brief State structure for memory manager. */ +typedef struct _mem_manager_info +{ + mem_pool_structure_t *pHeadPool; + uint16_t poolNum; +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) + uint16_t allocationFailures; + uint16_t freeFailures; +#endif /*MEM_MANAGER_ENABLE_TRACE*/ +} mem_manager_info_t; + +/***************************************************************************** +****************************************************************************** +* Public memory declarations +****************************************************************************** +*****************************************************************************/ +/***************************************************************************** + ***************************************************************************** + * Private prototypes + ***************************************************************************** + *****************************************************************************/ +/***************************************************************************** + ***************************************************************************** + * Private memory definitions + ***************************************************************************** + *****************************************************************************/ +static mem_manager_info_t s_memmanager = {0}; +#ifdef MEM_STATISTICS_INTERNAL +static mem_statis_t s_memStatis; +#endif /* MEM_STATISTICS_INTERNAL */ + +/***************************************************************************** +****************************************************************************** +* Private API macro define +****************************************************************************** +*****************************************************************************/ +#define BLOCK_HDR_SIZE sizeof(block_list_header_t) +/***************************************************************************** +****************************************************************************** +* Private functions +****************************************************************************** +*****************************************************************************/ +#ifdef MEM_STATISTICS_INTERNAL +static void MEM_BufferAllocates_memStatis(void *buffer, uint32_t time, uint32_t requestedSize) +{ + block_list_header_t *pBlock = (block_list_header_t *)buffer - 1; + /* existing block must have a BlockHdr and a next BlockHdr */ + assert((pBlock != NULL)); + + s_memStatis.nb_alloc++; + /* Sort the buffers by size, based on defined thresholds */ + if (requestedSize <= SMALL_BUFFER_SIZE) + { + s_memStatis.nb_small_buffer++; + UPDATE_PEAK(s_memStatis.nb_small_buffer, s_memStatis.peak_small_buffer); + } + else if (requestedSize <= LARGE_BUFFER_SIZE) + { + s_memStatis.nb_medium_buffer++; + UPDATE_PEAK(s_memStatis.nb_medium_buffer, s_memStatis.peak_medium_buffer); + } + else + { + s_memStatis.nb_large_buffer++; + UPDATE_PEAK(s_memStatis.nb_large_buffer, s_memStatis.peak_large_buffer); + } + /* the RAM allocated is the buffer size and the block header size*/ + s_memStatis.ram_allocated += (uint16_t)(requestedSize + BLOCK_HDR_SIZE); + UPDATE_PEAK(s_memStatis.ram_allocated, s_memStatis.peak_ram_allocated); + + uint32_t block_size = 0U; + + block_size = pBlock->blockSize; + + assert(block_size >= requestedSize); + /* ram lost is the difference between block size and buffer size */ + s_memStatis.ram_lost += (uint16_t)(block_size - requestedSize); + UPDATE_PEAK(s_memStatis.ram_lost, s_memStatis.peak_ram_lost); + + /* UPDATE_PEAK(((uint32_t)FreeBlockHdrList.tail + BLOCK_HDR_SIZE), s_memStatis.peak_upper_addr); */ + +#ifdef MEM_MANAGER_BENCH + if (time != 0U) + { + /* update mem stats used for benchmarking */ + s_memStatis.last_alloc_block_size = (uint16_t)block_size; + s_memStatis.last_alloc_buff_size = (uint16_t)requestedSize; + s_memStatis.last_alloc_time = (uint16_t)time; + s_memStatis.total_alloc_time += time; + s_memStatis.average_alloc_time = (uint16_t)(s_memStatis.total_alloc_time / s_memStatis.nb_alloc); + UPDATE_PEAK((uint16_t)time, s_memStatis.peak_alloc_time); + } + else /* alloc time is not correct, we bypass this allocation's data */ + { + s_memStatis.nb_alloc--; + } +#else + NOT_USED(time); +#endif /* MEM_MANAGER_BENCH */ +} + +static void MEM_BufferFrees_memStatis(void *buffer) +{ + block_list_header_t *pBlock = (block_list_header_t *)buffer - 1; + s_memStatis.ram_allocated -= (uint16_t)(pBlock->allocatedBytes + BLOCK_HDR_SIZE); + /* Sort the buffers by size, based on defined thresholds */ + if (pBlock->allocatedBytes <= SMALL_BUFFER_SIZE) + { + s_memStatis.nb_small_buffer--; + } + else if (pBlock->allocatedBytes <= LARGE_BUFFER_SIZE) + { + s_memStatis.nb_medium_buffer--; + } + else + { + s_memStatis.nb_large_buffer--; + } + + uint16_t block_size = 0U; + block_size = pBlock->blockSize; + + assert(block_size >= pBlock->allocatedBytes); + assert(s_memStatis.ram_lost >= (block_size - pBlock->allocatedBytes)); + + /* as the buffer is free, the ram is not "lost" anymore */ + s_memStatis.ram_lost -= (block_size - pBlock->allocatedBytes); +} +#endif +#if defined(MEM_STATISTICS_INTERNAL) +static void MEM_Reports_memStatis(void) +{ + MEM_DBG_LOG("**************** MEM STATS REPORT **************"); + MEM_DBG_LOG("Nb Alloc: %d\r\n", s_memStatis.nb_alloc); + MEM_DBG_LOG("Small buffers: %d\r\n", s_memStatis.nb_small_buffer); + MEM_DBG_LOG("Medium buffers: %d\r\n", s_memStatis.nb_medium_buffer); + MEM_DBG_LOG("Large buffers: %d\r\n", s_memStatis.nb_large_buffer); + MEM_DBG_LOG("Peak small: %d\r\n ", s_memStatis.peak_small_buffer); + MEM_DBG_LOG("Peak medium: %d\r\n ", s_memStatis.peak_medium_buffer); + MEM_DBG_LOG("Peak large: %d\r\n ", s_memStatis.peak_large_buffer); + MEM_DBG_LOG("Current RAM allocated: %d bytes\r\n", s_memStatis.ram_allocated); + MEM_DBG_LOG("Peak RAM allocated: %d bytes\r\n", s_memStatis.peak_ram_allocated); + MEM_DBG_LOG("Current RAM lost: %d bytes\r\n", s_memStatis.ram_lost); + MEM_DBG_LOG("Peak RAM lost: %d bytes\r\n", s_memStatis.peak_ram_lost); + MEM_DBG_LOG("Peak Upper Address: %x\r\n", s_memStatis.peak_upper_addr); +#ifdef MEM_MANAGER_BENCH + MEM_DBG_LOG("************************************************\r\n"); + MEM_DBG_LOG("********* MEM MANAGER BENCHMARK REPORT *********\r\n"); + MEM_DBG_LOG("Last Alloc Time: %d us\r\n", s_memStatis.last_alloc_time); + MEM_DBG_LOG("Last Alloc Block Size: %d bytes\r\n", s_memStatis.last_alloc_block_size); + MEM_DBG_LOG("Last Alloc Buffer Size: %d bytes\r\n", s_memStatis.last_alloc_buff_size); + MEM_DBG_LOG("Average Alloc Time: %d us\r\n", s_memStatis.average_alloc_time); + MEM_DBG_LOG("Peak Alloc Time: %d us\r\n", s_memStatis.peak_alloc_time); +#endif /* MEM_MANAGER_BENCH */ + MEM_DBG_LOG("************************************************"); +} +#endif /* MEM_STATISTICS_INTERNAL */ + +/***************************************************************************** +****************************************************************************** +* Public functions +****************************************************************************** +*****************************************************************************/ +/*! + * @brief Initialises the Memory Manager. + * + */ +mem_status_t MEM_Init(void) +{ + static bool initialized = false; + assert(sizeof(mem_pool_structure_t) == MEM_POOL_SIZE); + assert(sizeof(block_list_header_t) == MEM_BLOCK_SIZE); + if (!initialized) + { + s_memmanager.pHeadPool = NULL; + s_memmanager.poolNum = 0; +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) + s_memmanager.allocationFailures = 0; + s_memmanager.freeFailures = 0; +#endif /*MEM_MANAGER_ENABLE_TRACE*/ +#if (defined(MEM_MANAGER_PRE_CONFIGURE) && (MEM_MANAGER_PRE_CONFIGURE > 0U)) + for (uint8_t i = 0; i < (sizeof(s_PoolList) / sizeof(s_PoolList[0])); i++) + { + (void)MEM_AddBuffer(s_PoolList[i]); + } +#endif /*MEM_MANAGER_PRE_CONFIGURE*/ + initialized = true; + } + return kStatus_MemSuccess; +} + +/*! + * @brief Add memory buffer to memory manager buffer list. + * + * @note This API should be called when need add memory buffer to memory manager buffer list. First use + * MEM_BLOCK_BUFFER_DEFINE to + * define memory buffer, then call MEM_AddBuffer function with MEM_BLOCK_BUFFER Macro. + * @code + * MEM_BLOCK_BUFFER_DEFINE(app64, 5, 64,0); + * MEM_BLOCK_BUFFER_DEFINE(app128, 6, 128,0); + * MEM_BLOCK_BUFFER_DEFINE(app256, 7, 256,0); + * + * MEM_AddBuffer(MEM_BLOCK_BUFFER(app64)); + * MEM_AddBuffer(MEM_BLOCK_BUFFER(app128)); + * MEM_AddBuffer(MEM_BLOCK_BUFFER(app256)); + * @endcode + * + * @param buffer Pointer the memory pool buffer, use MEM_BLOCK_BUFFER Macro as the input parameter. + * + * @retval kStatus_MemSuccess Memory manager add Buffer succeed. + * @retval kStatus_MemInitError Memory manager add Buffer error occurred. + */ +mem_status_t MEM_AddBuffer(const uint8_t *buffer) +{ + mem_config_t *memConfig = (mem_config_t *)(void *)buffer; + mem_pool_structure_t *pPool = (mem_pool_structure_t *)(void *)memConfig->pbuffer; + uint8_t *pHeap = &memConfig->pbuffer[sizeof(mem_pool_structure_t)]; + mem_pool_structure_t *pPrevPool, *pTempPool; + + assert(buffer); + assert(memConfig->numberOfBlocks); + assert(memConfig->blockSize); + + MEM_ENTER_CRITICAL(); +#if (defined(MEM_MANAGER_PRE_CONFIGURE) && (MEM_MANAGER_PRE_CONFIGURE == 0U)) + (void)MEM_Init(); +#endif + pPool->pHeap = pHeap; + pPool->numBlocks = memConfig->numberOfBlocks; + pPool->blockSize = memConfig->blockSize; + pPool->poolId = *(uint16_t *)(void *)(&buffer[4]); + pPool->heapSize = + (MEM_POOL_SIZE + (uint32_t)memConfig->numberOfBlocks * (MEM_BLOCK_SIZE + (uint32_t)memConfig->blockSize)); +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) + pPool->allocatedBlocksPeak = 0; + pPool->poolTotalFragmentWaste = 0; + pPool->poolFragmentWaste = 0; + pPool->poolFragmentWastePeak = 0; + pPool->poolFragmentMinWaste = 0xffff; +#endif /*MEM_MANAGER_ENABLE_TRACE*/ + if (s_memmanager.pHeadPool == NULL) + { + s_memmanager.pHeadPool = pPool; + } + else + { + pTempPool = s_memmanager.pHeadPool; + pPrevPool = pTempPool; + while (NULL != pTempPool) + { + if (((pPool->blockSize >= pPrevPool->blockSize) && (pPool->blockSize <= pTempPool->blockSize)) || + (pPool->blockSize <= pPrevPool->blockSize)) + { + if (pTempPool == s_memmanager.pHeadPool) + { + s_memmanager.pHeadPool = pPool; + } + else + { + pPrevPool->nextPool = pPool; + } + pPool->nextPool = pTempPool; + break; + } + pPrevPool = pTempPool; + pTempPool = pTempPool->nextPool; + } + if (pPool->blockSize > pPrevPool->blockSize) + { + pPrevPool->nextPool = pPool; + } + } + + s_memmanager.poolNum++; + MEM_EXIT_CRITICAL(); + return kStatus_MemSuccess; +} + +/*! + * @brief Remove memory buffer from memory manager buffer list. + * + * @note This API should be called when need remove memory buffer to memory manager buffer list. Use with + * MEM_BLOCK_BUFFER Macro as input parameter. + * + * @param buffer Pointer the memory pool buffer, use MEM_BLOCK_BUFFER Macro as the input parameter. + * + * @retval kStatus_MemSuccess Memory manager remove buffer succeed. + * @retval kStatus_MemUnknownError Memory manager remove buffer error occurred. + */ +#if (defined(MEM_MANAGER_BUFFER_REMOVE) && (MEM_MANAGER_BUFFER_REMOVE > 0U)) +mem_status_t MEM_RemoveBuffer(uint8_t *buffer) +{ + mem_config_t *memConfig = (mem_config_t *)(void *)buffer; + mem_pool_structure_t *pPool = (mem_pool_structure_t *)(void *)memConfig->pbuffer; + uint8_t *pHeap = &memConfig->pbuffer[sizeof(mem_pool_structure_t)]; + mem_pool_structure_t *pPrevPool, *pTempPool; + + assert(buffer); + assert(memConfig->numberOfBlocks > 0U); + assert(memConfig->blockSize > 0U); + + MEM_ENTER_CRITICAL(); + pTempPool = s_memmanager.pHeadPool; + pPrevPool = pTempPool; + while (NULL != pTempPool) + { + if (0U != pPool->allocatedBlocks) + { + break; + } + if (pTempPool->pHeap == pHeap) + { + if (pPool == s_memmanager.pHeadPool) + { + s_memmanager.pHeadPool = pPool->nextPool; + } + else + { + pPrevPool->nextPool = pPool->nextPool; + } + s_memmanager.poolNum--; + MEM_EXIT_CRITICAL(); + return kStatus_MemSuccess; + } + pPrevPool = pTempPool; + pTempPool = pTempPool->nextPool; + } + MEM_EXIT_CRITICAL(); + return kStatus_MemUnknownError; +} +#endif /* MEM_MANAGER_BUFFER_REMOVE */ + +/*! + * @brief Allocate a block from the memory pools. The function uses the + * numBytes argument to look up a pool with adequate block sizes. + * + * @param numBytes The number of bytes will be allocated. + * @param poolId The ID of the pool where to search for a free buffer. + * @retval Memory buffer address when allocate success, NULL when allocate fail. + */ +void *MEM_BufferAllocWithId(uint32_t numBytes, uint8_t poolId) +{ +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) + uint32_t fragmentWaste = 0; +#endif /*MEM_MANAGER_ENABLE_TRACE*/ + mem_pool_structure_t *pPool = s_memmanager.pHeadPool; + block_list_header_t *pBlock; + void *buffer = NULL; + + MEM_ENTER_CRITICAL(); +#ifdef MEM_MANAGER_BENCH + uint32_t START_TIME = 0U, STOP_TIME = 0U, ALLOC_TIME = 0U; + START_TIME = TM_GetTimestamp(); +#endif /* MEM_MANAGER_BENCH */ + + while (0U != numBytes) + { + if ((numBytes <= pPool->blockSize) && (pPool->poolId == poolId)) + { + for (uint32_t i = 0; i < pPool->numBlocks; i++) + { + pBlock = (block_list_header_t *)(void *)(pPool->pHeap + i * ((uint32_t)pPool->blockSize + + (uint32_t)sizeof(block_list_header_t))); + if (0U == pBlock->allocated) + { + pBlock->allocated = 1; + pBlock->blockSize = pPool->blockSize; +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) + pBlock->allocatedBytes = (uint16_t)numBytes; + pBlock->caller = (uint32_t)((uint32_t *)__mem_get_LR()); +#endif /*MEM_MANAGER_ENABLE_TRACE*/ + pBlock++; + pPool->allocatedBlocks++; + buffer = pBlock; + (void)memset(buffer, 0x0, pBlock->blockSize); + break; + } + } + } + if (NULL != buffer) + { + break; + } + /* Try next pool*/ + pPool = pPool->nextPool; + if (NULL == pPool) + { + break; + } + } +#ifdef MEM_MANAGER_BENCH + STOP_TIME = TM_GetTimestamp(); + ALLOC_TIME = STOP_TIME - START_TIME; +#endif /* MEM_MANAGER_BENCH */ +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) + if (NULL == buffer) + { + s_memmanager.allocationFailures++; + } +#endif /*MEM_MANAGER_ENABLE_TRACE*/ + +#ifdef MEM_STATISTICS_INTERNAL +#ifdef MEM_MANAGER_BENCH + MEM_BufferAllocates_memStatis(buffer, ALLOC_TIME, numBytes); +#else + MEM_BufferAllocates_memStatis(buffer, 0, numBytes); +#endif + + if ((s_memStatis.nb_alloc % NB_ALLOC_REPORT_THRESHOLD) == 0U) + { + MEM_Reports_memStatis(); + } +#endif /* MEM_STATISTICS_INTERNAL */ +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) + if (pPool->allocatedBlocks > pPool->allocatedBlocksPeak) + { + pPool->allocatedBlocksPeak = pPool->allocatedBlocks; + } + fragmentWaste = pPool->blockSize - numBytes; + if (fragmentWaste > pPool->poolFragmentWastePeak) + { + pPool->poolFragmentWastePeak = (uint16_t)fragmentWaste; + } + pPool->poolFragmentWaste = (uint16_t)fragmentWaste; + pPool->poolTotalFragmentWaste += (uint16_t)fragmentWaste; + if (fragmentWaste < pPool->poolFragmentMinWaste) + { + pPool->poolFragmentMinWaste = (uint16_t)fragmentWaste; + } +#endif /*MEM_MANAGER_ENABLE_TRACE*/ + MEM_EXIT_CRITICAL(); + return buffer; +} + +/*! + * @brief Memory buffer free. + * + * @param buffer The memory buffer address will be free. + * @retval kStatus_MemSuccess Memory free succeed. + * @retval kStatus_MemFreeError Memory free error occurred. + */ +mem_status_t MEM_BufferFree(void *buffer /* IN: Block of memory to free*/ +) +{ + block_list_header_t *pBlock; + mem_pool_structure_t *pPool = s_memmanager.pHeadPool; + MEM_ENTER_CRITICAL(); + + do + { + if (NULL == buffer) + { + break; + } +#if defined(MEM_STATISTICS_INTERNAL) + MEM_BufferFrees_memStatis(buffer); +#endif /* MEM_STATISTICS_INTERNAL */ + pBlock = (block_list_header_t *)buffer - 1; + assert(pBlock); + if (1U == pBlock->allocated) + { + (void)memset(pBlock, 0x0, (sizeof(block_list_header_t) + (uint32_t)pBlock->blockSize)); + MEM_EXIT_CRITICAL(); + while (true) + { + if (((uint32_t)pPool->pHeap <= (uint32_t)pBlock) && + ((uint32_t)pBlock < + (uint32_t)pPool->pHeap + + pPool->numBlocks * ((uint32_t)pPool->blockSize + (uint32_t)sizeof(block_list_header_t)))) + { + pPool->allocatedBlocks--; + return kStatus_MemSuccess; + } + pPool = pPool->nextPool; + if (NULL == pPool) + { + return kStatus_MemFreeError; + } + } + } + +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) + s_memmanager.freeFailures++; +#endif /*MEM_MANAGER_ENABLE_TRACE*/ + + } while (false); + + MEM_EXIT_CRITICAL(); + return kStatus_MemFreeError; +} + +/*! + * @brief Returns the size of a given buffer. + * + * @param buffer The memory buffer address will be free. + * @retval The size of a given buffer. + */ +uint16_t MEM_BufferGetSize(void *buffer) /* IN: Block of memory to get size*/ +{ + block_list_header_t *pBlock; + assert(buffer); + + pBlock = (block_list_header_t *)buffer - 1; + assert(pBlock); + + return pBlock->blockSize; +} + +/*! + * @brief Frees all allocated blocks by selected source and in selected pool. + * + * @param poolId Selected pool Id (4 LSBs of poolId parameter) and selected + * source Id (4 MSBs of poolId parameter). + * @retval kStatus_MemSuccess Memory free succeed. + * @retval kStatus_MemFreeError Memory free error occurred. + */ +mem_status_t MEM_BufferFreeAllWithId(uint8_t poolId) +{ + mem_pool_structure_t *pPool = s_memmanager.pHeadPool; + + MEM_ENTER_CRITICAL(); + + while (pPool != NULL) + { + if (pPool->poolId == poolId) + { + (void)memset(pPool->pHeap, 0x0, + ((sizeof(block_list_header_t) + (uint32_t)pPool->blockSize) * pPool->numBlocks)); +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) + pPool->allocatedBlocksPeak = 0; + pPool->poolTotalFragmentWaste = 0; + pPool->poolFragmentWaste = 0; + pPool->poolFragmentWastePeak = 0; + pPool->poolFragmentMinWaste = 0xffff; +#endif /*MEM_MANAGER_ENABLE_TRACE*/ + pPool->allocatedBlocks = 0; + } + pPool = pPool->nextPool; + } + + MEM_EXIT_CRITICAL(); + return kStatus_MemSuccess; +} + +/*! + * @brief Memory buffer realloc. + * + * @param buffer The memory buffer address will be reallocated. + * @param new_size The number of bytes will be reallocated + * @retval kStatus_MemSuccess Memory free succeed. + * @retval kStatus_MemFreeError Memory free error occurred. + */ +void *MEM_BufferRealloc(void *buffer, uint32_t new_size) +{ + void *realloc_buffer = NULL; + uint16_t block_size = 0U; + + if (new_size == 0U) + { + /* new requested size is 0, free old buffer */ + (void)MEM_BufferFree(buffer); + realloc_buffer = NULL; + } + else if (buffer == NULL) + { + /* input buffer is NULL simply allocate a new buffer and return it */ + realloc_buffer = MEM_BufferAllocWithId(new_size, 0U); + } + else + { + block_size = MEM_BufferGetSize(buffer); + + if ((uint16_t)new_size <= block_size) + { + /* current buffer is large enough for the new requested size + we can still use it */ + realloc_buffer = buffer; + } + else + { + /* not enough space in the current block, creating a new one */ + realloc_buffer = MEM_BufferAllocWithId(new_size, 0U); + + if (realloc_buffer != NULL) + { + /* copy input buffer data to new buffer */ + (void)memcpy(realloc_buffer, buffer, (uint32_t)block_size); + + /* free old buffer */ + (void)MEM_BufferFree(buffer); + } + } + } + + return realloc_buffer; +} + +/*! + * @brief Get the address after the last allocated block if MemManagerLight is used. + * + * @retval 0 Return 0 in case of the legacy MemManager. + */ +uint32_t MEM_GetHeapUpperLimit(void) +{ + return 0; +} + +/*! + * @brief Trace memory manager all information to use debug. + * + */ +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) +void MEM_Trace(void) +{ + mem_pool_structure_t *pPool = s_memmanager.pHeadPool; + block_list_header_t *pBlock; + (void)PRINTF("MEM_Trace debug information, Pools Number:%d allocationFailures: %d freeFailures:%d \r\n", + s_memmanager.poolNum, s_memmanager.allocationFailures, s_memmanager.allocationFailures, + s_memmanager.freeFailures); + while (NULL != pPool) + { + (void)PRINTF("POOL: ID %d blockSize:%d status:\r\n", pPool->poolId, pPool->blockSize); + (void)PRINTF( + "numBlocks allocatedBlocks allocatedBlocksPeak poolFragmentWaste poolFragmentWastePeak " + "poolFragmentMinWaste poolTotalFragmentWaste\r\n"); + (void)PRINTF( + " %d %d %d %d %d %d " + " %d \r\n", + pPool->numBlocks, pPool->allocatedBlocks, pPool->allocatedBlocksPeak, pPool->poolFragmentWaste, + pPool->poolFragmentWastePeak, pPool->poolFragmentMinWaste, pPool->poolTotalFragmentWaste); + (void)PRINTF("Currently pool meory block allocate status: \r\n"); + for (uint32_t i = 0; i < pPool->numBlocks; i++) + { + pBlock = (block_list_header_t *)(void *)(pPool->pHeap + + i * ((uint32_t)pPool->blockSize + sizeof(block_list_header_t))); + + (void)PRINTF("Block %d caller : 0x%x Allocated %d bytes: %d \r\n", i, pBlock->caller, pBlock->allocated, + pBlock->allocatedBytes); + } + /* Try next pool*/ + pPool = pPool->nextPool; + } +} +#endif /*MEM_MANAGER_ENABLE_TRACE*/ +#endif /*gMemManagerLight*/ diff --git a/components/mem_manager/fsl_component_mem_manager.h b/components/mem_manager/fsl_component_mem_manager.h new file mode 100644 index 000000000..e106ff7c1 --- /dev/null +++ b/components/mem_manager/fsl_component_mem_manager.h @@ -0,0 +1,321 @@ +/* + * Copyright 2018, 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MEM_MANAGER_H__ +#define __MEM_MANAGER_H__ + +#include "fsl_common.h" +/*! + * @addtogroup MemManager + * @{ + */ + +/***************************************************************************** +****************************************************************************** +* Public macros +****************************************************************************** +*****************************************************************************/ +/* + * @brief Configures the memory manager light enable. + */ +#ifndef gMemManagerLight +#define gMemManagerLight (1) +#endif + +/* + * @brief Configures the memory manager trace debug enable. + */ +#ifndef MEM_MANAGER_ENABLE_TRACE +#define MEM_MANAGER_ENABLE_TRACE (0) +#endif + +/* + * @brief Configures the memory manager remove memory buffer. + */ +#ifndef MEM_MANAGER_BUFFER_REMOVE +#define MEM_MANAGER_BUFFER_REMOVE (0) +#endif + +/* + * @brief Configures the memory manager pre configure. + */ +#ifndef MEM_MANAGER_PRE_CONFIGURE +#define MEM_MANAGER_PRE_CONFIGURE (1) +#endif + +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) +#ifndef MEM_POOL_SIZE +#define MEM_POOL_SIZE (32U) +#endif +#ifndef MEM_BLOCK_SIZE +#define MEM_BLOCK_SIZE (12U) +#endif +#else +#ifndef MEM_POOL_SIZE +#define MEM_POOL_SIZE (20U) +#endif +#ifndef MEM_BLOCK_SIZE +#define MEM_BLOCK_SIZE (4U) +#endif +#endif + +#define MAX_POOL_ID 3U + +/* Debug Macros - stub if not defined */ +#ifndef MEM_DBG_LOG +#define MEM_DBG_LOG(...) +#endif + +/* Default memory allocator */ +#ifndef MEM_BufferAlloc +#define MEM_BufferAlloc(numBytes) MEM_BufferAllocWithId(numBytes, 0) +#endif + +#if (defined(MEM_MANAGER_PRE_CONFIGURE) && (MEM_MANAGER_PRE_CONFIGURE > 0U)) +/* + * Defines pools by block size and number of blocks. Must be aligned to 4 bytes. + * Defines block as (blockSize ,numberOfBlocks, id), id must be keep here, + * even id is 0, will be _block_set_(64, 8, 0) _eol_ + * and _block_set_(64, 8) _eol_\ could not supported + */ +#ifndef PoolsDetails_c +#define PoolsDetails_c _block_set_(64, 8, 0) _eol_ _block_set_(128, 2, 1) _eol_ _block_set_(256, 6, 1) _eol_ +#endif /* PoolsDetails_c */ + +#define MEM_BLOCK_DATA_BUFFER_NONAME_DEFINE(blockSize, numberOfBlocks, id) \ + uint32_t g_poolBuffer##blockSize##_##numberOfBlocks##_##id[(MEM_POOL_SIZE + (numberOfBlocks)*MEM_BLOCK_SIZE + \ + ((numberOfBlocks) * (blockSize)) + 3U) >> \ + 2U]; + +#define MEM_BLOCK_BUFFER_NONAME_DEFINE(blockSize, numberOfBlocks, id) \ + MEM_BLOCK_DATA_BUFFER_NONAME_DEFINE(blockSize, numberOfBlocks, id) \ + const static mem_config_t g_poolHeadBuffer##blockSize##_##numberOfBlocks##_##id = { \ + (blockSize), (numberOfBlocks), (id), (0), (uint8_t *)&g_poolBuffer####blockSize##_##numberOfBlocks##_##id[0]} +#define MEM_BLOCK_NONAME_BUFFER(blockSize, numberOfBlocks, id) \ + (uint8_t *)&g_poolHeadBuffer##blockSize##_##numberOfBlocks##_##id +#endif /* MEM_MANAGER_PRE_CONFIGURE */ + +/*! + * @brief Defines the memory buffer + * + * This macro is used to define the shell memory buffer for memory manager. + * And then uses the macro MEM_BLOCK_BUFFER to get the memory buffer pointer. + * The macro should not be used in any function. + * + * This is a example, + * @code + * MEM_BLOCK_BUFFER_DEFINE(app64, 5, 64,0); + * MEM_BLOCK_BUFFER_DEFINE(app128, 6, 128,0); + * MEM_BLOCK_BUFFER_DEFINE(app256, 7, 256,0); + * @endcode + * + * @param name The name string of the memory buffer. + * @param numberOfBlocks The number Of Blocks. + * @param blockSize The memory block size. + * @param id The id Of memory buffer. + */ +#define MEM_BLOCK_DATA_BUFFER_DEFINE(name, numberOfBlocks, blockSize, id) \ + uint32_t \ + g_poolBuffer##name[(MEM_POOL_SIZE + numberOfBlocks * MEM_BLOCK_SIZE + numberOfBlocks * blockSize + 3U) >> 2U]; + +#define MEM_BLOCK_BUFFER_DEFINE(name, numberOfBlocks, blockSize, id) \ + MEM_BLOCK_DATA_BUFFER_DEFINE(name, numberOfBlocks, blockSize, id) \ + mem_config_t g_poolHeadBuffer##name = {(blockSize), (numberOfBlocks), (id), (0), (uint8_t *)&g_poolBuffer##name[0]} + +/*! \ + * @brief Gets the memory buffer pointer \ + * \ + * This macro is used to get the memory buffer pointer. The macro should \ + * not be used before the macro MEM_BLOCK_BUFFER_DEFINE is used. \ + * \ + * @param name The memory name string of the buffer. \ + */ +#define MEM_BLOCK_BUFFER(name) (uint8_t *)&g_poolHeadBuffer##name + +/***************************************************************************** +****************************************************************************** +* Public type definitions +****************************************************************************** +*****************************************************************************/ + +/**@brief Memory status. */ +typedef enum _mem_status +{ + kStatus_MemSuccess = kStatus_Success, /* No error occurred */ + kStatus_MemInitError = MAKE_STATUS(kStatusGroup_MEM_MANAGER, 1), /* Memory initialization error */ + kStatus_MemAllocError = MAKE_STATUS(kStatusGroup_MEM_MANAGER, 2), /* Memory allocation error */ + kStatus_MemFreeError = MAKE_STATUS(kStatusGroup_MEM_MANAGER, 3), /* Memory free error */ + kStatus_MemUnknownError = MAKE_STATUS(kStatusGroup_MEM_MANAGER, 4), /* something bad has happened... */ +} mem_status_t; + +/**@brief Memory user config. */ +typedef struct _mem_config +{ + uint16_t blockSize; /*< The memory block size. */ + uint16_t numberOfBlocks; /*< The number Of Blocks. */ + uint16_t poolId; /*< The pool id Of Blocks. */ + uint16_t reserved; /*< reserved. */ + uint8_t *pbuffer; /*< buffer. */ +} mem_config_t; + +/***************************************************************************** +****************************************************************************** +* Public memory declarations +****************************************************************************** +*****************************************************************************/ +/***************************************************************************** +****************************************************************************** +* Public prototypes +****************************************************************************** +*****************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ +#if (defined(MEM_MANAGER_PRE_CONFIGURE) && (MEM_MANAGER_PRE_CONFIGURE > 0U)) +/*! + * @brief Initialises the Memory Manager. + * + */ +mem_status_t MEM_Init(void); + +#endif + +#if !defined(gMemManagerLight) || (gMemManagerLight == 0) +/*! + * @brief Add memory buffer to memory manager buffer list. + * + * @note This API should be called when need add memory buffer to memory manager buffer list. First use + * MEM_BLOCK_BUFFER_DEFINE to + * define memory buffer, then call MEM_AddBuffer function with MEM_BLOCK_BUFFER Macro as the input parameter. + * @code + * MEM_BLOCK_BUFFER_DEFINE(app64, 5, 64,0); + * MEM_BLOCK_BUFFER_DEFINE(app128, 6, 128,0); + * MEM_BLOCK_BUFFER_DEFINE(app256, 7, 256,0); + * + * MEM_AddBuffer(MEM_BLOCK_BUFFER(app64)); + * MEM_AddBuffer(MEM_BLOCK_BUFFER(app128)); + * MEM_AddBuffer(MEM_BLOCK_BUFFER(app256)); + * @endcode + * + * @param buffer Pointer the memory pool buffer, use MEM_BLOCK_BUFFER Macro as the input parameter. + * + * @retval kStatus_MemSuccess Memory manager add buffer succeed. + * @retval kStatus_MemUnknownError Memory manager add buffer error occurred. + */ +mem_status_t MEM_AddBuffer(const uint8_t *buffer); +#endif /* gMemManagerLight */ + +#if !defined(gMemManagerLight) || (gMemManagerLight == 0) +#if (defined(MEM_MANAGER_BUFFER_REMOVE) && (MEM_MANAGER_BUFFER_REMOVE > 0U)) +/*! + * @brief Remove memory buffer from memory manager buffer list. + * + * @note This API should be called when need remove memory buffer from memory manager buffer list. Use MEM_BLOCK_BUFFER + * Macro as the input parameter. + * + * @param buffer Pointer the memory pool buffer, use MEM_BLOCK_BUFFER Macro as the input parameter. + * + * @retval kStatus_MemSuccess Memory manager remove buffer succeed. + * @retval kStatus_MemUnknownError Memory manager remove buffer error occurred. + */ +mem_status_t MEM_RemoveBuffer(uint8_t *buffer); +#endif /* MEM_MANAGER_BUFFER_REMOVE */ +#endif /* gMemManagerLight */ +/*! + * @brief Allocate a block from the memory pools. The function uses the + * numBytes argument to look up a pool with adequate block sizes. + * + * @param numBytes The number of bytes will be allocated. + * @param poolId The ID of the pool where to search for a free buffer. + * @retval Memory buffer address when allocate success, NULL when allocate fail. + */ +void *MEM_BufferAllocWithId(uint32_t numBytes, uint8_t poolId); + +/*! + * @brief Memory buffer free . + * + * @param buffer The memory buffer address will be free. + * @retval kStatus_MemSuccess Memory free succeed. + * @retval kStatus_MemFreeError Memory free error occurred. + */ +mem_status_t MEM_BufferFree(void *buffer); + +/*! + * @brief Returns the size of a given buffer. + * + * @param buffer The memory buffer address will be get size. + * @retval The size of a given buffer. + */ +uint16_t MEM_BufferGetSize(void *buffer); + +/*! + * @brief Frees all allocated blocks by selected source and in selected pool. + * + * @param poolId Selected pool Id (4 LSBs of poolId parameter) and selected + * source Id (4 MSBs of poolId parameter). + * @retval kStatus_MemSuccess Memory free succeed. + * @retval kStatus_MemFreeError Memory free error occurred. + */ +mem_status_t MEM_BufferFreeAllWithId(uint8_t poolId); + +/*! + * @brief Memory buffer realloc. + * + * @param buffer The memory buffer address will be reallocated. + * @param new_size The number of bytes will be reallocated + * @retval kStatus_MemSuccess Memory free succeed. + * @retval kStatus_MemFreeError Memory free error occurred. + */ +void *MEM_BufferRealloc(void *buffer, uint32_t new_size); + +/*! + * @brief Get the address after the last allocated block if MemManagerLight is used. + * + * @retval UpperLimit Return the address after the last allocated block if MemManagerLight is used. + * @retval 0 Return 0 in case of the legacy MemManager. + */ +uint32_t MEM_GetHeapUpperLimit(void); + +#if !defined(gMemManagerLight) || (gMemManagerLight == 0) +#if (defined(MEM_MANAGER_ENABLE_TRACE) && (MEM_MANAGER_ENABLE_TRACE > 0U)) +/*! + * @brief Function to print statistics related to memory blocks managed by memory manager. Like bellow: + * allocationFailures: 241 freeFailures:0 + * POOL: ID 0 status: + * numBlocks allocatedBlocks allocatedBlocksPeak poolFragmentWaste poolFragmentWastePeak poolFragmentMinWaste + * poolTotalFragmentWaste + * 5 5 5 59 63 59 305 + * Currently pool meory block allocate status: + * Block 0 Allocated bytes: 1 + * Block 1 Allocated bytes: 2 + * Block 2 Allocated bytes: 3 + * Block 3 Allocated bytes: 4 + * Block 4 Allocated bytes: 5 + * + * @details This API prints information with respects to each pool and block, including Allocated size, + * total block count, number of blocks in use at the time of printing, The API is intended to + * help developers tune the block sizes to make optimal use of memory for the application. + * + * @note This API should be disable by configure MEM_MANAGER_ENABLE_TRACE to 0 + * + */ +void MEM_Trace(void); + +#endif /* MEM_MANAGER_ENABLE_TRACE */ +#endif /* gMemManagerLight */ + +#if defined(gMemManagerLight) && (gMemManagerLight == 1) +void *MEM_CallocAlt(size_t len, size_t val); +#endif /*gMemManagerLight == 1*/ + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /* #ifndef __MEM_MANAGER_H__ */ diff --git a/components/mem_manager/fsl_component_mem_manager_light.c b/components/mem_manager/fsl_component_mem_manager_light.c new file mode 100644 index 000000000..959d31d9d --- /dev/null +++ b/components/mem_manager/fsl_component_mem_manager_light.c @@ -0,0 +1,849 @@ +/*! ********************************************************************************* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * \file + * + * This is the source file for the Memory Manager. + * + * SPDX-License-Identifier: BSD-3-Clause + ********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ + +#include "fsl_common.h" +#if defined(MEM_STATISTICS_INTERNAL) || defined(MEM_MANAGER_BENCH) +#include "fsl_component_timer_manager.h" +#include "fsl_component_mem_manager_internal.h" +#endif /* MEM_STATISTICS_INTERNAL MEM_MANAGER_BENCH*/ +#include "fsl_component_mem_manager.h" +#if defined(gDebugConsoleEnable_d) && (gDebugConsoleEnable_d == 1) +#include "fsl_debug_console.h" +#endif + +#if defined(gMemManagerLight) && (gMemManagerLight == 1) + +#ifndef cMemManagerLightReuseFreeBlocks +#define cMemManagerLightReuseFreeBlocks 1 +#endif + +#if defined(cMemManagerLightReuseFreeBlocks) && (cMemManagerLightReuseFreeBlocks > 0) +/* because a more restrictive on the size of the free blocks when cMemManagerLightReuseFreeBlocks + is set, we need to enable a garbage collector to clean up the free block when possible */ +#ifndef gMemManagerLightFreeBlocksCleanUp +#define gMemManagerLightFreeBlocksCleanUp 1 +#endif +#endif + +#ifndef gMemManagerLightGuardsCheckEnable +#define gMemManagerLightGuardsCheckEnable 0 +#endif + +/*! ********************************************************************************* +************************************************************************************* +* Private macros +************************************************************************************* +********************************************************************************** */ + +#define MEM_BLOCK_HEAP_SIZE(blockSize, numberOfBlocks, id) ((numberOfBlocks) * ((blockSize) + 16)) + +#undef _block_set_ +#undef _eol_ + +#define _eol_ + +#define _block_set_ MEM_BLOCK_HEAP_SIZE + +#define heapSize_c (PoolsDetails_c 0) + +#define MEMMANAGER_BLOCK_INVALID (uint16_t)0x0 /* Used to remove a block in the heap - debug only */ +#define MEMMANAGER_BLOCK_FREE (uint16_t)0xBA00 /* Mark a previous allocated block as free */ +#define MEMMANAGER_BLOCK_USED (uint16_t)0xBABE /* Mark the block as allocated */ + +#define BLOCK_HDR_SIZE (ROUNDUP_WORD(sizeof(blockHeader_t))) + +#define ROUNDUP_WORD(__x) (((((__x)-1U) & ~0x3U) + 4U) & 0XFFFFFFFFU) + +#define BLOCK_HDR_PREGUARD_SIZE 28U +#define BLOCK_HDR_PREGUARD_PATTERN 0x28U +#define BLOCK_HDR_POSTGUARD_SIZE 28U +#define BLOCK_HDR_POSTGUARD_PATTERN 0x39U + +#if defined(__IAR_SYSTEMS_ICC__) +#define __mem_get_LR() __get_LR() +#elif defined(__GNUC__) +#define __mem_get_LR() __builtin_return_address(0) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define __mem_get_LR() __return_address() +#endif + +#if defined(gMemManagerLightGuardsCheckEnable) && (gMemManagerLightGuardsCheckEnable == 1) +#define gMemManagerLightAddPreGuard 1 +#define gMemManagerLightAddPostGuard 1 +#endif + +#ifndef gMemManagerLightAddPreGuard +#define gMemManagerLightAddPreGuard 0 +#endif + +#ifndef gMemManagerLightAddPostGuard +#define gMemManagerLightAddPostGuard 0 +#endif + +/************************************************************************************ +************************************************************************************* +* Private type definitions +************************************************************************************* +************************************************************************************/ + +typedef struct blockHeader_s +{ +#if defined(gMemManagerLightAddPreGuard) && (gMemManagerLightAddPreGuard == 1) + uint8_t preguard[BLOCK_HDR_PREGUARD_SIZE]; +#endif + uint16_t used; +#if defined(MEM_STATISTICS) + uint16_t buff_size; +#endif + struct blockHeader_s *next; + struct blockHeader_s *next_free; + struct blockHeader_s *prev_free; +#ifdef MEM_TRACKING + void *first_alloc_caller; + void *second_alloc_caller; +#endif +#if defined(gMemManagerLightAddPostGuard) && (gMemManagerLightAddPostGuard == 1) + uint8_t postguard[BLOCK_HDR_POSTGUARD_SIZE]; +#endif +} blockHeader_t; + +typedef struct freeBlockHeaderList_s +{ + struct blockHeader_s *head; + struct blockHeader_s *tail; +} freeBlockHeaderList_t; + +typedef union void_ptr_tag +{ + uint32_t raw_address; + uint32_t *address_ptr; + void *void_ptr; + blockHeader_t *block_hdr_ptr; +} void_ptr_t; + +/*! ********************************************************************************* +************************************************************************************* +* Private memory declarations +************************************************************************************* +********************************************************************************** */ + +/* Allocate memHeap array in the .heap section to ensure the size of the .heap section is large enough + for the application (from app_preinclude.h) + However, the real heap used at run time will cover all the .heap section so this area can be bigger + than the requested heapSize_c - see memHeapEnd */ +#if defined(__IAR_SYSTEMS_ICC__) +#pragma location = ".heap" +static uint32_t memHeap[heapSize_c / sizeof(uint32_t)]; +#elif defined(__GNUC__) +static uint32_t memHeap[heapSize_c / sizeof(uint32_t)] __attribute__((section(".heap"))); +#elif defined(__CC_ARM) +static uint32_t memHeap[heapSize_c / sizeof(uint32_t)] __attribute__((section(".heap"))); +#else +#error "Compiler unknown!" +#endif + +extern uint32_t __HEAP_end__[]; +static const uint32_t memHeapEnd = (uint32_t)&__HEAP_end__; + +static freeBlockHeaderList_t FreeBlockHdrList; + +#ifdef MEM_STATISTICS_INTERNAL +static mem_statis_t s_memStatis; +#endif /* MEM_STATISTICS_INTERNAL */ + +/*! ********************************************************************************* +************************************************************************************* +* Private functions +************************************************************************************* +********************************************************************************** */ + +#ifdef MEM_STATISTICS_INTERNAL +static void MEM_Inits_memStatis(mem_statis_t *s_memStatis_) +{ + (void)memset(s_memStatis_, 0, sizeof(mem_statis_t)); + SystemCoreClockUpdate(); +} + +static void MEM_BufferAllocates_memStatis(void *buffer, uint32_t time, uint32_t requestedSize) +{ + void_ptr_t buffer_ptr; + void_ptr_t blockHdr_ptr; + blockHeader_t *BlockHdr; + + /* Using union to fix Misra */ + buffer_ptr.void_ptr = buffer; + blockHdr_ptr.raw_address = buffer_ptr.raw_address - BLOCK_HDR_SIZE; + BlockHdr = blockHdr_ptr.block_hdr_ptr; + + /* existing block must have a BlockHdr and a next BlockHdr */ + assert((BlockHdr != NULL) && (BlockHdr->next != NULL)); + + s_memStatis.nb_alloc++; + /* Sort the buffers by size, based on defined thresholds */ + if (requestedSize <= SMALL_BUFFER_SIZE) + { + s_memStatis.nb_small_buffer++; + UPDATE_PEAK(s_memStatis.nb_small_buffer, s_memStatis.peak_small_buffer); + } + else if (requestedSize <= LARGE_BUFFER_SIZE) + { + s_memStatis.nb_medium_buffer++; + UPDATE_PEAK(s_memStatis.nb_medium_buffer, s_memStatis.peak_medium_buffer); + } + else + { + s_memStatis.nb_large_buffer++; + UPDATE_PEAK(s_memStatis.nb_large_buffer, s_memStatis.peak_large_buffer); + } + /* the RAM allocated is the buffer size and the block header size*/ + s_memStatis.ram_allocated += (uint16_t)(requestedSize + BLOCK_HDR_SIZE); + UPDATE_PEAK(s_memStatis.ram_allocated, s_memStatis.peak_ram_allocated); + + uint32_t block_size = 0U; + block_size = (uint32_t)BlockHdr->next - (uint32_t)BlockHdr - BLOCK_HDR_SIZE; + + assert(block_size >= requestedSize); + /* ram lost is the difference between block size and buffer size */ + s_memStatis.ram_lost += (uint16_t)(block_size - requestedSize); + UPDATE_PEAK(s_memStatis.ram_lost, s_memStatis.peak_ram_lost); + + UPDATE_PEAK(((uint32_t)FreeBlockHdrList.tail + BLOCK_HDR_SIZE), s_memStatis.peak_upper_addr); + +#ifdef MEM_MANAGER_BENCH + if (time != 0U) + { + /* update mem stats used for benchmarking */ + s_memStatis.last_alloc_block_size = (uint16_t)block_size; + s_memStatis.last_alloc_buff_size = (uint16_t)requestedSize; + s_memStatis.last_alloc_time = (uint16_t)time; + s_memStatis.total_alloc_time += time; + s_memStatis.average_alloc_time = (uint16_t)(s_memStatis.total_alloc_time / s_memStatis.nb_alloc); + UPDATE_PEAK((uint16_t)time, s_memStatis.peak_alloc_time); + } + else /* alloc time is not correct, we bypass this allocation's data */ + { + s_memStatis.nb_alloc--; + } +#else + NOT_USED(time); +#endif /* MEM_MANAGER_BENCH */ +} + +static void MEM_BufferFrees_memStatis(void *buffer) +{ + void_ptr_t buffer_ptr; + void_ptr_t blockHdr_ptr; + blockHeader_t *BlockHdr; + + /* Use union to fix Misra */ + buffer_ptr.void_ptr = buffer; + blockHdr_ptr.raw_address = buffer_ptr.raw_address - BLOCK_HDR_SIZE; + BlockHdr = blockHdr_ptr.block_hdr_ptr; + + /* Existing block must have a next block hdr */ + assert((BlockHdr != NULL) && (BlockHdr->next != NULL)); + + s_memStatis.ram_allocated -= (uint16_t)(BlockHdr->buff_size + BLOCK_HDR_SIZE); + /* Sort the buffers by size, based on defined thresholds */ + if (BlockHdr->buff_size <= SMALL_BUFFER_SIZE) + { + s_memStatis.nb_small_buffer--; + } + else if (BlockHdr->buff_size <= LARGE_BUFFER_SIZE) + { + s_memStatis.nb_medium_buffer--; + } + else + { + s_memStatis.nb_large_buffer--; + } + + uint16_t block_size = 0U; + block_size = (uint16_t)((uint32_t)BlockHdr->next - (uint32_t)BlockHdr - BLOCK_HDR_SIZE); + + assert(block_size >= BlockHdr->buff_size); + assert(s_memStatis.ram_lost >= (block_size - BlockHdr->buff_size)); + + /* as the buffer is free, the ram is not "lost" anymore */ + s_memStatis.ram_lost -= (block_size - BlockHdr->buff_size); +} + +#endif /* MEM_STATISTICS_INTERNAL */ + +#if defined(gMemManagerLightFreeBlocksCleanUp) && (gMemManagerLightFreeBlocksCleanUp == 1) +static void MEM_BufferFreeBlocksCleanUp(blockHeader_t *BlockHdr) +{ + blockHeader_t *NextBlockHdr = BlockHdr->next; + blockHeader_t *NextFreeBlockHdr = BlockHdr->next_free; + + /* This function shouldn't be called on the last free block */ + assert(BlockHdr < FreeBlockHdrList.tail); + + while (NextBlockHdr == NextFreeBlockHdr) + { + if (NextBlockHdr == NULL) + { + assert(BlockHdr->next == BlockHdr->next_free); + assert(BlockHdr->used == MEMMANAGER_BLOCK_FREE); + /* pool is reached. All buffers from BlockHdr to the pool are free + remove all next buffers */ + BlockHdr->next = NULL; + BlockHdr->next_free = NULL; + FreeBlockHdrList.tail = BlockHdr; + break; + } + NextBlockHdr = NextBlockHdr->next; + NextFreeBlockHdr = NextFreeBlockHdr->next_free; + } +} +#endif /* gMemManagerLightFreeBlocksCleanUp */ + +#if defined(gMemManagerLightGuardsCheckEnable) && (gMemManagerLightGuardsCheckEnable == 1) +static void MEM_BlockHeaderCheck(blockHeader_t *BlockHdr) +{ + bool_t ret; + + ret = FLib_MemCmpToVal((const void *)&BlockHdr->preguard, BLOCK_HDR_PREGUARD_PATTERN, BLOCK_HDR_PREGUARD_SIZE); + if (ret == 0) + { + MEM_DBG_LOG("Preguard Block Header Corrupted %x", BlockHdr); + } + assert(ret); + + ret = FLib_MemCmpToVal((const void *)&BlockHdr->postguard, BLOCK_HDR_POSTGUARD_PATTERN, BLOCK_HDR_POSTGUARD_SIZE); + if (ret == 0) + { + MEM_DBG_LOG("Postguard Block Header Corrupted %x", BlockHdr); + } + assert(ret); +} + +static void MEM_BlockHeaderSetGuards(blockHeader_t *BlockHdr) +{ + FLib_MemSet((void *)&BlockHdr->preguard, BLOCK_HDR_PREGUARD_PATTERN, BLOCK_HDR_PREGUARD_SIZE); + FLib_MemSet((void *)&BlockHdr->postguard, BLOCK_HDR_POSTGUARD_PATTERN, BLOCK_HDR_POSTGUARD_SIZE); +} + +#endif + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ + +#if defined(MEM_STATISTICS_INTERNAL) +static void MEM_Reports_memStatis(void) +{ + MEM_DBG_LOG("**************** MEM STATS REPORT **************"); + MEM_DBG_LOG("Nb Alloc: %d\r\n", s_memStatis.nb_alloc); + MEM_DBG_LOG("Small buffers: %d\r\n", s_memStatis.nb_small_buffer); + MEM_DBG_LOG("Medium buffers: %d\r\n", s_memStatis.nb_medium_buffer); + MEM_DBG_LOG("Large buffers: %d\r\n", s_memStatis.nb_large_buffer); + MEM_DBG_LOG("Peak small: %d\r\n ", s_memStatis.peak_small_buffer); + MEM_DBG_LOG("Peak medium: %d\r\n ", s_memStatis.peak_medium_buffer); + MEM_DBG_LOG("Peak large: %d\r\n ", s_memStatis.peak_large_buffer); + MEM_DBG_LOG("Current RAM allocated: %d bytes\r\n", s_memStatis.ram_allocated); + MEM_DBG_LOG("Peak RAM allocated: %d bytes\r\n", s_memStatis.peak_ram_allocated); + MEM_DBG_LOG("Current RAM lost: %d bytes\r\n", s_memStatis.ram_lost); + MEM_DBG_LOG("Peak RAM lost: %d bytes\r\n", s_memStatis.peak_ram_lost); + MEM_DBG_LOG("Peak Upper Address: %x\r\n", s_memStatis.peak_upper_addr); +#ifdef MEM_MANAGER_BENCH + MEM_DBG_LOG("************************************************\r\n"); + MEM_DBG_LOG("********* MEM MANAGER BENCHMARK REPORT *********\r\n"); + MEM_DBG_LOG("Last Alloc Time: %d us\r\n", s_memStatis.last_alloc_time); + MEM_DBG_LOG("Last Alloc Block Size: %d bytes\r\n", s_memStatis.last_alloc_block_size); + MEM_DBG_LOG("Last Alloc Buffer Size: %d bytes\r\n", s_memStatis.last_alloc_buff_size); + MEM_DBG_LOG("Average Alloc Time: %d us\r\n", s_memStatis.average_alloc_time); + MEM_DBG_LOG("Peak Alloc Time: %d us\r\n", s_memStatis.peak_alloc_time); +#endif /* MEM_MANAGER_BENCH */ + MEM_DBG_LOG("************************************************"); +} +#endif /* MEM_STATISTICS_INTERNAL */ + +mem_status_t MEM_Init(void) +{ + static bool initialized = false; + if (initialized == false) + { + initialized = true; + /* union to solve Misra 11.3 */ + void_ptr_t ptr; + ptr.address_ptr = memHeap; + blockHeader_t *firstBlockHdr; + firstBlockHdr = ptr.block_hdr_ptr; + + /* MEM_DBG_LOG("%x %d\r\n", memHeap, heapSize_c/sizeof(uint32_t)); */ + + /* Init firstBlockHdr as a free block */ + firstBlockHdr->next = NULL; + firstBlockHdr->used = MEMMANAGER_BLOCK_FREE; + firstBlockHdr->next_free = NULL; + firstBlockHdr->prev_free = NULL; + +#if defined(MEM_STATISTICS) + firstBlockHdr->buff_size = 0U; +#endif + + /* Init FreeBlockHdrList with firstBlockHdr */ + FreeBlockHdrList.head = firstBlockHdr; + FreeBlockHdrList.tail = firstBlockHdr; + +#if defined(gMemManagerLightGuardsCheckEnable) && (gMemManagerLightGuardsCheckEnable == 1) + MEM_BlockHeaderSetGuards(firstBlockHdr); +#endif + +#if defined(MEM_STATISTICS_INTERNAL) + /* Init memory statistics */ + MEM_Inits_memStatis(&s_memStatis); +#endif + } + + return kStatus_MemSuccess; +} +static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) +{ + blockHeader_t *FreeBlockHdr = FreeBlockHdrList.head; + blockHeader_t *NextFreeBlockHdr = FreeBlockHdr->next_free; + blockHeader_t *PrevFreeBlockHdr = FreeBlockHdr->prev_free; + blockHeader_t *BlockHdrFound = NULL; + +#if defined(cMemManagerLightReuseFreeBlocks) && (cMemManagerLightReuseFreeBlocks > 0) + blockHeader_t *UsableBlockHdr = NULL; +#endif + void *buffer = NULL; + + uint32_t regPrimask = DisableGlobalIRQ(); + +#ifdef MEM_MANAGER_BENCH + uint32_t START_TIME = 0U, STOP_TIME = 0U, ALLOC_TIME = 0U; + START_TIME = TM_GetTimestamp(); +#endif /* MEM_MANAGER_BENCH */ + + do + { + assert(FreeBlockHdr->used == MEMMANAGER_BLOCK_FREE); + if (FreeBlockHdr->next != NULL) + { + uint32_t available_size; + available_size = (uint32_t)FreeBlockHdr->next - (uint32_t)FreeBlockHdr - BLOCK_HDR_SIZE; + /* if a next block hdr exists, it means (by design) that a next free block exists too + Because the last block header at the end of the heap will always be free + So, the current block header cant be the tail, and the next free cant be NULL */ + assert(FreeBlockHdr < FreeBlockHdrList.tail); + assert(FreeBlockHdr->next_free != NULL); + + if (available_size >= numBytes) /* enough space in this free buffer */ + { +#if defined(cMemManagerLightReuseFreeBlocks) && (cMemManagerLightReuseFreeBlocks > 0) + /* this block could be used if the memory pool if full, so we memorize it */ + if (UsableBlockHdr == NULL) + { + UsableBlockHdr = FreeBlockHdr; + } + /* to avoid waste of large blocks with small blocks, make sure the required size is big enough for the + available block otherwise, try an other block ! */ + if ((available_size - numBytes) < (available_size >> cMemManagerLightReuseFreeBlocks)) +#endif + { + /* Found a matching free block */ + FreeBlockHdr->used = MEMMANAGER_BLOCK_USED; +#if defined(MEM_STATISTICS_INTERNAL) + FreeBlockHdr->buff_size = (uint16_t)numBytes; +#endif + NextFreeBlockHdr = FreeBlockHdr->next_free; + PrevFreeBlockHdr = FreeBlockHdr->prev_free; + + /* In the current state, the current block header can be anywhere + from list head to previous block of list tail */ + if (FreeBlockHdrList.head == FreeBlockHdr) + { + FreeBlockHdrList.head = NextFreeBlockHdr; + NextFreeBlockHdr->prev_free = NULL; + } + else + { + assert(FreeBlockHdrList.head->next_free <= FreeBlockHdr); + + NextFreeBlockHdr->prev_free = PrevFreeBlockHdr; + PrevFreeBlockHdr->next_free = NextFreeBlockHdr; + } + + BlockHdrFound = FreeBlockHdr; + break; + } + } + } + else + { + /* last block in the heap, check if available space to allocate the block */ + uint32_t available_size; + available_size = memHeapEnd - (uint32_t)FreeBlockHdr - BLOCK_HDR_SIZE; + assert(FreeBlockHdr == FreeBlockHdrList.tail); + + if (available_size >= (numBytes + BLOCK_HDR_SIZE)) /* need to keep the room for the next BlockHeader */ + { + FreeBlockHdr->used = MEMMANAGER_BLOCK_USED; +#if defined(MEM_STATISTICS_INTERNAL) + FreeBlockHdr->buff_size = (uint16_t)numBytes; +#endif + FreeBlockHdr->next = + (blockHeader_t *)ROUNDUP_WORD(((uint32_t)FreeBlockHdr + BLOCK_HDR_SIZE + numBytes)); + FreeBlockHdr->next_free = FreeBlockHdr->next; + + PrevFreeBlockHdr = FreeBlockHdr->prev_free; + + NextFreeBlockHdr = FreeBlockHdr->next_free; + NextFreeBlockHdr->used = MEMMANAGER_BLOCK_FREE; +#if defined(MEM_STATISTICS_INTERNAL) + NextFreeBlockHdr->buff_size = 0U; +#endif + NextFreeBlockHdr->next = NULL; + NextFreeBlockHdr->next_free = NULL; + NextFreeBlockHdr->prev_free = PrevFreeBlockHdr; + + if (FreeBlockHdrList.head == FreeBlockHdr) + { + assert(FreeBlockHdrList.head == FreeBlockHdrList.tail); + assert(PrevFreeBlockHdr == NULL); + /* last free block in heap was the only free block available + so now the first free block in the heap is the next one */ + FreeBlockHdrList.head = FreeBlockHdr->next_free; + } + else + { + /* update previous free block header to point its next + to the new free block */ + PrevFreeBlockHdr->next_free = NextFreeBlockHdr; + } + + /* new free block is now the tail of the free block list */ + FreeBlockHdrList.tail = NextFreeBlockHdr; + +#if defined(gMemManagerLightGuardsCheckEnable) && (gMemManagerLightGuardsCheckEnable == 1) + MEM_BlockHeaderSetGuards(NextFreeBlockHdr); +#endif + + BlockHdrFound = FreeBlockHdr; + } +#if defined(cMemManagerLightReuseFreeBlocks) && (cMemManagerLightReuseFreeBlocks > 0) + else if (UsableBlockHdr != NULL) + { + /* we found a free block that can be used */ + UsableBlockHdr->used = MEMMANAGER_BLOCK_USED; +#if defined(MEM_STATISTICS_INTERNAL) + UsableBlockHdr->buff_size = (uint16_t)numBytes; +#endif + NextFreeBlockHdr = UsableBlockHdr->next_free; + PrevFreeBlockHdr = UsableBlockHdr->prev_free; + + /* In the current state, the current block header can be anywhere + from list head to previous block of list tail */ + if (FreeBlockHdrList.head == UsableBlockHdr) + { + FreeBlockHdrList.head = NextFreeBlockHdr; + NextFreeBlockHdr->prev_free = NULL; + } + else + { + assert(FreeBlockHdrList.head->next_free <= UsableBlockHdr); + + NextFreeBlockHdr->prev_free = PrevFreeBlockHdr; + PrevFreeBlockHdr->next_free = NextFreeBlockHdr; + } + BlockHdrFound = UsableBlockHdr; + } +#endif + else + { + BlockHdrFound = NULL; + } + break; + } +#if defined(gMemManagerLightGuardsCheckEnable) && (gMemManagerLightGuardsCheckEnable == 1) + MEM_BlockHeaderCheck(FreeBlockHdr->next_free); +#endif + FreeBlockHdr = FreeBlockHdr->next_free; + /* avoid looping */ + assert(FreeBlockHdr != FreeBlockHdr->next_free); + } while (true); + /* MEM_DBG_LOG("BlockHdrFound: %x", BlockHdrFound); */ + +#ifdef MEM_DEBUG_OUT_OF_MEMORY + assert(BlockHdrFound); +#endif + +#ifdef MEM_MANAGER_BENCH + STOP_TIME = TM_GetTimestamp(); + ALLOC_TIME = STOP_TIME - START_TIME; +#endif /* MEM_MANAGER_BENCH */ + + if (BlockHdrFound != NULL) + { + void_ptr_t buffer_ptr; +#ifdef MEM_TRACKING + void_ptr_t lr; + lr.raw_address = __get_LR(); + BlockHdrFound->first_alloc_caller = lr.void_ptr; +#endif + buffer_ptr.raw_address = (uint32_t)BlockHdrFound + BLOCK_HDR_SIZE; + buffer = buffer_ptr.void_ptr; + (void)memset(buffer, 0x0, numBytes); + } + +#ifdef MEM_STATISTICS_INTERNAL +#ifdef MEM_MANAGER_BENCH + MEM_BufferAllocates_memStatis(buffer, ALLOC_TIME, numBytes); +#else + MEM_BufferAllocates_memStatis(buffer, 0, numBytes); +#endif + + if ((s_memStatis.nb_alloc % NB_ALLOC_REPORT_THRESHOLD) == 0U) + { + MEM_Reports_memStatis(); + } +#endif /* MEM_STATISTICS_INTERNAL */ + + EnableGlobalIRQ(regPrimask); + + return buffer; +} + +void *MEM_BufferAllocWithId(uint32_t numBytes, uint8_t poolId) +{ +#ifdef MEM_TRACKING + void_ptr_t BlockHdr_ptr; +#endif + void_ptr_t buffer_ptr; + + /* Alloc a buffer */ + buffer_ptr.void_ptr = MEM_BufferAllocate(numBytes, poolId); + +#ifdef MEM_TRACKING + if (buffer_ptr.void_ptr != NULL) + { + BlockHdr_ptr.raw_address = buffer_ptr.raw_address - BLOCK_HDR_SIZE; + /* store caller */ + BlockHdr_ptr.block_hdr_ptr->second_alloc_caller = (void *)((uint32_t *)__mem_get_LR()); + ; + } +#endif + + return buffer_ptr.void_ptr; +} + +mem_status_t MEM_BufferFree(void *buffer /* IN: Block of memory to free*/) +{ + mem_status_t ret = kStatus_MemSuccess; + void_ptr_t buffer_ptr; + buffer_ptr.void_ptr = buffer; + + if (buffer == NULL) + { + ret = kStatus_MemFreeError; + } + else + { + uint32_t regPrimask = DisableGlobalIRQ(); + + blockHeader_t *BlockHdr; + BlockHdr = (blockHeader_t *)(buffer_ptr.raw_address - BLOCK_HDR_SIZE); + + /* assert checks */ + assert(BlockHdr->used == MEMMANAGER_BLOCK_USED); + assert(BlockHdr->next != NULL); + /* when allocating a buffer, we always create a FreeBlockHdr at + the end of the buffer, so the FreeBlockHdrList.tail should always + be at a higher address than current BlockHdr */ + assert(BlockHdr < FreeBlockHdrList.tail); + +#if defined(gMemManagerLightGuardsCheckEnable) && (gMemManagerLightGuardsCheckEnable == 1) + MEM_BlockHeaderCheck(BlockHdr->next); +#endif + + /* MEM_DBG_LOG("%x %d", BlockHdr, BlockHdr->buff_size); */ + +#if defined(MEM_STATISTICS_INTERNAL) + MEM_BufferFrees_memStatis(buffer); +#endif /* MEM_STATISTICS_INTERNAL */ + + if (BlockHdr < FreeBlockHdrList.head) + { + /* BlockHdr is placed before FreeBlockHdrList.head so we can set it as + the new head of the list */ + BlockHdr->next_free = FreeBlockHdrList.head; + BlockHdr->prev_free = NULL; + FreeBlockHdrList.head->prev_free = BlockHdr; + FreeBlockHdrList.head = BlockHdr; + } + else + { + /* we want to find the previous free block header + here, we cannot use prev_free as this information could be outdated + so we need to run through the whole list to be sure to catch the + correct previous free block header */ + blockHeader_t *PrevFreeBlockHdr = FreeBlockHdrList.head; + while ((uint32_t)PrevFreeBlockHdr->next_free < (uint32_t)BlockHdr) + { + PrevFreeBlockHdr = PrevFreeBlockHdr->next_free; + } + /* insert the new free block in the list */ + BlockHdr->next_free = PrevFreeBlockHdr->next_free; + BlockHdr->prev_free = PrevFreeBlockHdr; + BlockHdr->next_free->prev_free = BlockHdr; + PrevFreeBlockHdr->next_free = BlockHdr; + } + + BlockHdr->used = MEMMANAGER_BLOCK_FREE; +#if defined(MEM_STATISTICS_INTERNAL) + BlockHdr->buff_size = 0U; +#endif + +#if defined(gMemManagerLightFreeBlocksCleanUp) && (gMemManagerLightFreeBlocksCleanUp == 1) + MEM_BufferFreeBlocksCleanUp(BlockHdr); +#endif + + EnableGlobalIRQ(regPrimask); + } + + return ret; +} + +mem_status_t MEM_BufferFreeAllWithId(uint8_t poolId) +{ + mem_status_t status = kStatus_MemSuccess; +#if (defined(MEM_TRACK_ALLOC_SOURCE) && (MEM_TRACK_ALLOC_SOURCE == 1)) +#ifdef MEMMANAGER_NOT_IMPLEMENTED_YET + +#endif /* MEMMANAGER_NOT_IMPLEMENTED_YET */ +#else /* (defined(MEM_TRACK_ALLOC_SOURCE) && (MEM_TRACK_ALLOC_SOURCE == 1)) */ + status = kStatus_MemFreeError; +#endif /* (defined(MEM_TRACK_ALLOC_SOURCE) && (MEM_TRACK_ALLOC_SOURCE == 1)) */ + return status; +} + +uint32_t MEM_GetHeapUpperLimit(void) +{ + /* There is always a free block at the end of the heap + and this free block is the tail of the list */ + return ((uint32_t)FreeBlockHdrList.tail + BLOCK_HDR_SIZE); +} + +uint16_t MEM_BufferGetSize(void *buffer) +{ + blockHeader_t *BlockHdr = NULL; + uint16_t size; + /* union used to fix Misra */ + void_ptr_t buffer_ptr; + buffer_ptr.void_ptr = buffer; + + if (buffer != NULL) + { + BlockHdr = (blockHeader_t *)(buffer_ptr.raw_address - BLOCK_HDR_SIZE); + /* block size is the space between current BlockHdr and next BlockHdr */ + size = (uint16_t)((uint32_t)BlockHdr->next - (uint32_t)BlockHdr - BLOCK_HDR_SIZE); + } + else + { + /* is case of a NULL buffer, we return 0U */ + size = 0U; + } + + return size; +} + +void *MEM_BufferRealloc(void *buffer, uint32_t new_size) +{ + void *realloc_buffer = NULL; + uint16_t block_size = 0U; + + assert(new_size <= 0x0000FFFFU); /* size will be casted to 16 bits */ + + if (new_size == 0U) + { + /* new requested size is 0, free old buffer */ + (void)MEM_BufferFree(buffer); + realloc_buffer = NULL; + } + else if (buffer == NULL) + { + /* input buffer is NULL simply allocate a new buffer and return it */ + realloc_buffer = MEM_BufferAllocate(new_size, 0U); + } + else + { + block_size = MEM_BufferGetSize(buffer); + + if ((uint16_t)new_size <= block_size) + { + /* current buffer is large enough for the new requested size + we can still use it */ + realloc_buffer = buffer; + } + else + { + /* not enough space in the current block, creating a new one */ + realloc_buffer = MEM_BufferAllocate(new_size, 0); + + if (realloc_buffer != NULL) + { + /* copy input buffer data to new buffer */ + (void)memcpy(realloc_buffer, buffer, (uint32_t)block_size); + + /* free old buffer */ + (void)MEM_BufferFree(buffer); + } + } + } + + return realloc_buffer; +} + +#if 0 /* MISRA C-2012 Rule 8.4 */ +uint32_t MEM_GetAvailableBlocks(uint32_t size) +{ + /* Function not implemented yet */ + assert(0); + + return 0U; +} +#endif + +void *MEM_CallocAlt(size_t len, size_t val) +{ + size_t blk_size; + + blk_size = len * val; + + void *pData = MEM_BufferAllocate(blk_size, 0); + if (NULL != pData) + { + (void)memset(pData, 0, blk_size); + } + + return pData; +} + +#if 0 /* MISRA C-2012 Rule 8.4 */ +void MEM_FreeAlt(void *pData) +{ + /* Function not implemented yet */ + assert(0); +} +#endif + +#endif diff --git a/components/osa/fsl_os_abstraction.h b/components/osa/fsl_os_abstraction.h new file mode 100644 index 000000000..9f4fe4d8e --- /dev/null +++ b/components/osa/fsl_os_abstraction.h @@ -0,0 +1,906 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_OS_ABSTRACTION_H_ +#define _FSL_OS_ABSTRACTION_H_ + +#include "fsl_common.h" +#include "fsl_os_abstraction_config.h" +#include "fsl_component_generic_list.h" + +/*! + * @addtogroup osa_adapter + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Type for the Task Priority*/ +typedef uint16_t osa_task_priority_t; +/*! @brief Type for a task handler */ +typedef void *osa_task_handle_t; +/*! @brief Type for the parameter to be passed to the task at its creation */ +typedef void *osa_task_param_t; +/*! @brief Type for task pointer. Task prototype declaration */ +typedef void (*osa_task_ptr_t)(osa_task_param_t task_param); +/*! @brief Type for the semaphore handler */ +typedef void *osa_semaphore_handle_t; +/*! @brief Type for the mutex handler */ +typedef void *osa_mutex_handle_t; +/*! @brief Type for the event handler */ +typedef void *osa_event_handle_t; +/*! @brief Type for an event flags group, bit 32 is reserved. */ +typedef uint32_t osa_event_flags_t; +/*! @brief Message definition. */ +typedef void *osa_msg_handle_t; +/*! @brief Type for the message queue handler */ +typedef void *osa_msgq_handle_t; +/*! @brief Type for the Timer handler */ +typedef void *osa_timer_handle_t; +/*! @brief Type for the Timer callback function pointer. */ +typedef void (*osa_timer_fct_ptr_t)(void const *argument); +/*! @brief Thread Definition structure contains startup information of a thread.*/ +typedef struct osa_task_def_tag +{ + osa_task_ptr_t pthread; /*!< start address of thread function*/ + uint32_t tpriority; /*!< initial thread priority*/ + uint32_t instances; /*!< maximum number of instances of that thread function*/ + uint32_t stacksize; /*!< stack size requirements in bytes; 0 is default stack size*/ + uint32_t *tstack; /*!< stack pointer*/ + void *tlink; /*!< link pointer*/ + uint8_t *tname; /*!< name pointer*/ + uint8_t useFloat; /*!< is use float*/ +} osa_task_def_t; +/*! @brief Thread Link Definition structure .*/ +typedef struct osa_thread_link_tag +{ + uint8_t link[12]; /*!< link*/ + osa_task_handle_t osThreadId; /*!< thread id*/ + osa_task_def_t *osThreadDefHandle; /*!< pointer of thread define handle*/ + uint32_t *osThreadStackHandle; /*!< pointer of thread stack handle*/ +} osa_thread_link_t, *osa_thread_link_handle_t; + +/*! @brief Definition structure contains timer parameters.*/ +typedef struct osa_time_def_tag +{ + osa_timer_fct_ptr_t pfCallback; /* < start address of a timer function */ + void *argument; /* < argument of a timer function */ +} osa_time_def_t; + +/*! @brief Type for the timer definition*/ +typedef enum _osa_timer +{ + KOSA_TimerOnce = 0, /*!< one-shot timer*/ + KOSA_TimerPeriodic = 1 /*!< repeating timer*/ +} osa_timer_t; + +/*! @brief Defines the return status of OSA's functions */ +typedef enum _osa_status +{ + KOSA_StatusSuccess = kStatus_Success, /*!< Success */ + KOSA_StatusError = MAKE_STATUS(kStatusGroup_OSA, 1), /*!< Failed */ + KOSA_StatusTimeout = MAKE_STATUS(kStatusGroup_OSA, 2), /*!< Timeout occurs while waiting */ + KOSA_StatusIdle = MAKE_STATUS(kStatusGroup_OSA, 3), /*!< Used for bare metal only, the wait object is not ready + and timeout still not occur */ +} osa_status_t; + +#ifdef USE_RTOS +#undef USE_RTOS +#endif + +#if defined(SDK_OS_MQX) +#define USE_RTOS (1) +#elif defined(SDK_OS_FREE_RTOS) +#define USE_RTOS (1) +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#define OSA_TASK_HANDLE_SIZE (12U) +#else +#define OSA_TASK_HANDLE_SIZE (16U) +#endif +#define OSA_EVENT_HANDLE_SIZE (8U) +#define OSA_SEM_HANDLE_SIZE (4U) +#define OSA_MUTEX_HANDLE_SIZE (4U) +#define OSA_MSGQ_HANDLE_SIZE (4U) +#define OSA_MSG_HANDLE_SIZE (0U) +#elif defined(SDK_OS_UCOSII) +#define USE_RTOS (1) +#elif defined(SDK_OS_UCOSIII) +#define USE_RTOS (1) +#elif defined(FSL_RTOS_THREADX) +#define USE_RTOS (1) +#else +#define USE_RTOS (0) +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#define OSA_TASK_HANDLE_SIZE (24U) +#else +#define OSA_TASK_HANDLE_SIZE (28U) +#endif +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +#define OSA_EVENT_HANDLE_SIZE (20U) +#else +#define OSA_EVENT_HANDLE_SIZE (16U) +#endif /* FSL_OSA_TASK_ENABLE */ +#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U)) +#define OSA_SEM_HANDLE_SIZE (12U) +#define OSA_MUTEX_HANDLE_SIZE (12U) +#else +#define OSA_SEM_HANDLE_SIZE (4U) +#define OSA_MUTEX_HANDLE_SIZE (4U) +#endif +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +#define OSA_MSGQ_HANDLE_SIZE (32U) +#else +#define OSA_MSGQ_HANDLE_SIZE (28U) +#endif /* FSL_OSA_TASK_ENABLE */ +#define OSA_MSG_HANDLE_SIZE (4U) +#endif + +/*! @brief Priority setting for OSA. */ +#ifndef OSA_PRIORITY_IDLE +#define OSA_PRIORITY_IDLE (6) +#endif + +#ifndef OSA_PRIORITY_LOW +#define OSA_PRIORITY_LOW (5) +#endif + +#ifndef OSA_PRIORITY_BELOW_NORMAL +#define OSA_PRIORITY_BELOW_NORMAL (4) +#endif + +#ifndef OSA_PRIORITY_NORMAL +#define OSA_PRIORITY_NORMAL (3) +#endif + +#ifndef OSA_PRIORITY_ABOVE_NORMAL +#define OSA_PRIORITY_ABOVE_NORMAL (2) +#endif + +#ifndef OSA_PRIORITY_HIGH +#define OSA_PRIORITY_HIGH (1) +#endif + +#ifndef OSA_PRIORITY_REAL_TIME +#define OSA_PRIORITY_REAL_TIME (0) +#endif + +#ifndef OSA_TASK_PRIORITY_MAX +#define OSA_TASK_PRIORITY_MAX (0) +#endif + +#ifndef OSA_TASK_PRIORITY_MIN +#define OSA_TASK_PRIORITY_MIN (15) +#endif + +#define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t)) + +/*! @brief Constant to pass as timeout value in order to wait indefinitely. */ +#define osaWaitNone_c ((uint32_t)(0)) +#define osaWaitForever_c ((uint32_t)(-1)) +#define osaEventFlagsAll_c ((osa_event_flags_t)(0x00FFFFFF)) +#define osThreadStackArray(name) osThread_##name##_stack +#define osThreadStackDef(name, stacksize, instances) \ + const uint32_t osThreadStackArray(name)[SIZE_IN_UINT32_UNITS(stacksize) * (instances)]; + +/* ==== Thread Management ==== */ + +/* Create a Thread Definition with function, priority, and stack requirements. + * \param name name of the thread function. + * \param priority initial priority of the thread function. + * \param instances number of possible thread instances. + * \param stackSz stack size (in bytes) requirements for the thread function. + * \param useFloat + */ +#if defined(SDK_OS_MQX) +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + osa_thread_link_t osThreadLink_##name[instances] = {0}; \ + osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \ + (name), (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \ + (uint8_t *)#name, (useFloat)} +#elif defined(SDK_OS_UCOSII) +#if gTaskMultipleInstancesManagement_c +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + osa_thread_link_t osThreadLink_##name[instances] = {0}; \ + osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \ + (name), (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \ + (uint8_t *)#name, (useFloat)} +#else +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \ + (name), (priority), (instances), (stackSz), osThreadStackArray(name), NULL, (uint8_t *)#name, (useFloat)} +#endif +#elif defined(FSL_RTOS_THREADX) +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + uint32_t s_stackBuffer##name[(stackSz + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]; \ + static const osa_task_def_t os_thread_def_##name = { \ + (name), (priority), (instances), (stackSz), s_stackBuffer##name, NULL, (uint8_t *)#name, (useFloat)} +#else +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + const osa_task_def_t os_thread_def_##name = {(name), (priority), (instances), (stackSz), \ + NULL, NULL, (uint8_t *)#name, (useFloat)} +#endif +/* Access a Thread defintion. + * \param name name of the thread definition object. + */ +#define OSA_TASK(name) (const osa_task_def_t *)&os_thread_def_##name + +#define OSA_TASK_PROTO(name) extern osa_task_def_t os_thread_def_##name +/* ==== Timer Management ==== + * Define a Timer object. + * \param name name of the timer object. + * \param function name of the timer call back function. + */ + +#define OSA_TIMER_DEF(name, function) osa_time_def_t os_timer_def_##name = {(function), NULL} + +/* Access a Timer definition. + * \param name name of the timer object. + */ +#define OSA_TIMER(name) &os_timer_def_##name + +/* ==== Buffer Definition ==== */ + +/*! + * @brief Defines the semaphore handle + * + * This macro is used to define a 4 byte aligned semaphore handle. + * Then use "(osa_semaphore_handle_t)name" to get the semaphore handle. + * + * The macro should be global and could be optional. You could also define semaphore handle by yourself. + * + * This is an example, + * @code + * OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle); + * @endcode + * + * @param name The name string of the semaphore handle. + */ +#define OSA_SEMAPHORE_HANDLE_DEFINE(name) \ + uint32_t name[(OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +/*! + * @brief Defines the mutex handle + * + * This macro is used to define a 4 byte aligned mutex handle. + * Then use "(osa_mutex_handle_t)name" to get the mutex handle. + * + * The macro should be global and could be optional. You could also define mutex handle by yourself. + * + * This is an example, + * @code + * OSA_MUTEX_HANDLE_DEFINE(mutexHandle); + * @endcode + * + * @param name The name string of the mutex handle. + */ +#define OSA_MUTEX_HANDLE_DEFINE(name) uint32_t name[(OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +/*! + * @brief Defines the event handle + * + * This macro is used to define a 4 byte aligned event handle. + * Then use "(osa_event_handle_t)name" to get the event handle. + * + * The macro should be global and could be optional. You could also define event handle by yourself. + * + * This is an example, + * @code + * OSA_EVENT_HANDLE_DEFINE(eventHandle); + * @endcode + * + * @param name The name string of the event handle. + */ +#define OSA_EVENT_HANDLE_DEFINE(name) uint32_t name[(OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +/*! + * @brief Defines the message queue handle + * + * This macro is used to define a 4 byte aligned message queue handle. + * Then use "(osa_msgq_handle_t)name" to get the message queue handle. + * + * The macro should be global and could be optional. You could also define message queue handle by yourself. + * + * This is an example, + * @code + * OSA_MSGQ_HANDLE_DEFINE(msgqHandle, 3, sizeof(msgStruct)); + * @endcode + * + * @param name The name string of the message queue handle. + * @param numberOfMsgs Number of messages. + * @param msgSize Message size. + * + */ +#if defined(SDK_OS_FREE_RTOS) +/*< Macro For FREE_RTOS*/ +#define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \ + uint32_t name[(OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] +#else +/*< Macro For BARE_MATEL*/ +#define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \ + uint32_t name[((OSA_MSGQ_HANDLE_SIZE + numberOfMsgs * msgSize) + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] +#endif + +/*! + * @brief Defines the TASK handle + * + * This macro is used to define a 4 byte aligned TASK handle. + * Then use "(osa_task_handle_t)name" to get the TASK handle. + * + * The macro should be global and could be optional. You could also define TASK handle by yourself. + * + * This is an example, + * @code + * OSA_TASK_HANDLE_DEFINE(taskHandle); + * @endcode + * + * @param name The name string of the TASK handle. + */ +#define OSA_TASK_HANDLE_DEFINE(name) uint32_t name[(OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +#if defined(SDK_OS_FREE_RTOS) +#include "fsl_os_abstraction_free_rtos.h" +#elif defined(FSL_RTOS_THREADX) +#include "fsl_os_abstraction_threadx.h" +#else +#include "fsl_os_abstraction_bm.h" +#endif + +extern const uint8_t gUseRtos_c; + +/* + * alloc the temporary memory to store the status + */ +#define OSA_SR_ALLOC() uint32_t osaCurrentSr; +/* + * Enter critical mode + */ +#define OSA_ENTER_CRITICAL() OSA_EnterCritical(&osaCurrentSr) +/* + * Exit critical mode and retore the previous mode + */ +#define OSA_EXIT_CRITICAL() OSA_ExitCritical(osaCurrentSr) + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Reserves the requested amount of memory in bytes. + * + * The function is used to reserve the requested amount of memory in bytes and initializes it to 0. + * + * @param length Amount of bytes to reserve. + * + * @return Pointer to the reserved memory. NULL if memory can't be allocated. + */ +void *OSA_MemoryAllocate(uint32_t length); + +/*! + * @brief Frees the memory previously reserved. + * + * The function is used to free the memory block previously reserved. + * + * @param p Pointer to the start of the memory block previously reserved. + * + */ +void OSA_MemoryFree(void *p); + +/*! + * @brief Enter critical with nesting mode. + * + * @param sr Store current status and return to caller. + */ +void OSA_EnterCritical(uint32_t *sr); + +/*! + * @brief Exit critical with nesting mode. + * + * @param sr Previous status to restore. + */ +void OSA_ExitCritical(uint32_t sr); + +/*! + * @name Task management + * @{ + */ + +/*! + * @brief Initialize OSA. + * + * This function is used to setup the basic services. + * + * Example below shows how to use this API to create the task handle. + * @code + * OSA_Init(); + * @endcode + */ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +void OSA_Init(void); +#endif + +/*! + * @brief Start OSA schedule. + * + * This function is used to start OSA scheduler. + * + * Example below shows how to use this API to start osa schedule. + * @code + * OSA_Start(); + * @endcode + */ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +void OSA_Start(void); +#endif + +/*! + * @brief Creates a task. + * + * This function is used to create task based on the resources defined + * by the macro OSA_TASK_DEFINE. + * + * Example below shows how to use this API to create the task handle. + * @code + * OSA_TASK_HANDLE_DEFINE(taskHandle); + * OSA_TASK_DEFINE( Job1, OSA_PRIORITY_HIGH, 1, 800, 0); + * OSA_TaskCreate((osa_task_handle_t)taskHandle, OSA_TASK(Job1), (osa_task_param_t)NULL); + * @endcode + * + * @param taskHandle Pointer to a memory space of size OSA_TASK_HANDLE_SIZE allocated by the caller, task handle. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_TASK_HANDLE_DEFINE(taskHandle); + * or + * uint32_t taskHandle[((OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param thread_def pointer to theosa_task_def_t structure which defines the task. + * @param task_param Pointer to be passed to the task when it is created. + * @retval KOSA_StatusSuccess The task is successfully created. + * @retval KOSA_StatusError The task can not be created. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, + const osa_task_def_t *thread_def, + osa_task_param_t task_param); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Gets the handler of active task. + * + * @return Handler to current active task. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_handle_t OSA_TaskGetCurrentHandle(void); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Puts the active task to the end of scheduler's queue. + * + * When a task calls this function, it gives up the CPU and puts itself to the + * end of a task ready list. + * + * @retval KOSA_StatusSuccess The function is called successfully. + * @retval KOSA_StatusError Error occurs with this function. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskYield(void); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Gets the priority of a task. + * + * @param taskHandle The handler of the task whose priority is received. + * + * @return Task's priority. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Sets the priority of a task. + * + * @param taskHandle The handler of the task whose priority is set. + * @param taskPriority The priority to set. + * + * @retval KOSA_StatusSuccess Task's priority is set successfully. + * @retval KOSA_StatusError Task's priority can not be set. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Destroys a previously created task. + * + * @param taskHandle The handler of the task to destroy. + * + * @retval KOSA_StatusSuccess The task was successfully destroyed. + * @retval KOSA_StatusError Task destruction failed or invalid parameter. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Creates a semaphore with a given value. + * + * This function creates a semaphore and sets the value to the parameter + * initValue. + * + * Example below shows how to use this API to create the semaphore handle. + * @code + * OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle); + * OSA_SemaphoreCreate((osa_semaphore_handle_t)semaphoreHandle, 0xff); + * @endcode + * + * @param semaphoreHandle Pointer to a memory space of size OSA_SEM_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle); + * or + * uint32_t semaphoreHandle[((OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param initValue Initial value the semaphore will be set to. + * + * @retval KOSA_StatusSuccess the new semaphore if the semaphore is created successfully. + * @retval KOSA_StatusError if the semaphore can not be created. + */ +osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue); + +/*! + * @brief Destroys a previously created semaphore. + * + * @param semaphoreHandle The semaphore handle. + * The macro SEMAPHORE_HANDLE_BUFFER_GET is used to get the semaphore buffer pointer, + * and should not be used before the macro SEMAPHORE_HANDLE_BUFFER_DEFINE is used. + * + * @retval KOSA_StatusSuccess The semaphore is successfully destroyed. + * @retval KOSA_StatusError The semaphore can not be destroyed. + */ +osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle); + +/*! + * @brief Pending a semaphore with timeout. + * + * This function checks the semaphore's counting value. If it is positive, + * decreases it and returns KOSA_StatusSuccess. Otherwise, a timeout is used + * to wait. + * + * @param semaphoreHandle The semaphore handle. + * @param millisec The maximum number of milliseconds to wait if semaphore is not + * positive. Pass osaWaitForever_c to wait indefinitely, pass 0 + * will return KOSA_StatusTimeout immediately. + * + * @retval KOSA_StatusSuccess The semaphore is received. + * @retval KOSA_StatusTimeout The semaphore is not received within the specified 'timeout'. + * @retval KOSA_StatusError An incorrect parameter was passed. + */ +osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec); + +/*! + * @brief Signals for someone waiting on the semaphore to wake up. + * + * Wakes up one task that is waiting on the semaphore. If no task is waiting, increases + * the semaphore's counting value. + * + * @param semaphoreHandle The semaphore handle to signal. + * + * @retval KOSA_StatusSuccess The semaphore is successfully signaled. + * @retval KOSA_StatusError The object can not be signaled or invalid parameter. + * + */ +osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle); + +/*! + * @brief Create an unlocked mutex. + * + * This function creates a non-recursive mutex and sets it to unlocked status. + * + * Example below shows how to use this API to create the mutex handle. + * @code + * OSA_MUTEX_HANDLE_DEFINE(mutexHandle); + * OSA_MutexCreate((osa_mutex_handle_t)mutexHandle); + * @endcode + * + * @param mutexHandle Pointer to a memory space of size OSA_MUTEX_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_MUTEX_HANDLE_DEFINE(mutexHandle); + * or + * uint32_t mutexHandle[((OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @retval KOSA_StatusSuccess the new mutex if the mutex is created successfully. + * @retval KOSA_StatusError if the mutex can not be created. + */ +osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle); + +/*! + * @brief Waits for a mutex and locks it. + * + * This function checks the mutex's status. If it is unlocked, locks it and returns the + * KOSA_StatusSuccess. Otherwise, waits for a timeout in milliseconds to lock. + * + * @param mutexHandle The mutex handle. + * @param millisec The maximum number of milliseconds to wait for the mutex. + * If the mutex is locked, Pass the value osaWaitForever_c will + * wait indefinitely, pass 0 will return KOSA_StatusTimeout + * immediately. + * + * @retval KOSA_StatusSuccess The mutex is locked successfully. + * @retval KOSA_StatusTimeout Timeout occurred. + * @retval KOSA_StatusError Incorrect parameter was passed. + * + * @note This is non-recursive mutex, a task can not try to lock the mutex it has locked. + */ +osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec); + +/*! + * @brief Unlocks a previously locked mutex. + * + * @param mutexHandle The mutex handle. + * + * @retval KOSA_StatusSuccess The mutex is successfully unlocked. + * @retval KOSA_StatusError The mutex can not be unlocked or invalid parameter. + */ +osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle); + +/*! + * @brief Destroys a previously created mutex. + * + * @param mutexHandle The mutex handle. + * + * @retval KOSA_StatusSuccess The mutex is successfully destroyed. + * @retval KOSA_StatusError The mutex can not be destroyed. + * + */ +osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle); + +/*! + * @brief Initializes an event object with all flags cleared. + * + * This function creates an event object and set its clear mode. If autoClear + * is 1, when a task gets the event flags, these flags will be + * cleared automatically. Otherwise these flags must + * be cleared manually. + * + * Example below shows how to use this API to create the event handle. + * @code + * OSA_EVENT_HANDLE_DEFINE(eventHandle); + * OSA_EventCreate((osa_event_handle_t)eventHandle, 0); + * @endcode + * + * @param eventHandle Pointer to a memory space of size OSA_EVENT_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_EVENT_HANDLE_DEFINE(eventHandle); + * or + * uint32_t eventHandle[((OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param autoClear 1 The event is auto-clear. + * 0 The event manual-clear + * @retval KOSA_StatusSuccess the new event if the event is created successfully. + * @retval KOSA_StatusError if the event can not be created. + */ +osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear); + +/*! + * @brief Sets one or more event flags. + * + * Sets specified flags of an event object. + * + * @param eventHandle The event handle. + * @param flagsToSet Flags to be set. + * + * @retval KOSA_StatusSuccess The flags were successfully set. + * @retval KOSA_StatusError An incorrect parameter was passed. + */ +osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet); + +/*! + * @brief Clears one or more flags. + * + * Clears specified flags of an event object. + * + * @param eventHandle The event handle. + * @param flagsToClear Flags to be clear. + * + * @retval KOSA_StatusSuccess The flags were successfully cleared. + * @retval KOSA_StatusError An incorrect parameter was passed. + */ +osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear); + +/*! + * @brief Get event's flags. + * + * Get specified flags of an event object. + * + * @param eventHandle The event handle. + * The macro EVENT_HANDLE_BUFFER_GET is used to get the event buffer pointer, + * and should not be used before the macro EVENT_HANDLE_BUFFER_DEFINE is used. + * @param flagsMask The flags user want to get are specified by this parameter. + * @param pFlagsOfEvent The event flags are obtained by this parameter. + * + * @retval KOSA_StatusSuccess The event flags were successfully got. + * @retval KOSA_StatusError An incorrect parameter was passed. + */ +osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, + osa_event_flags_t flagsMask, + osa_event_flags_t *pFlagsOfEvent); + +/*! + * @brief Waits for specified event flags to be set. + * + * This function waits for a combination of flags to be set in an event object. + * Applications can wait for any/all bits to be set. Also this function could + * obtain the flags who wakeup the waiting task. + * + * @param eventHandle The event handle. + * @param flagsToWait Flags that to wait. + * @param waitAll Wait all flags or any flag to be set. + * @param millisec The maximum number of milliseconds to wait for the event. + * If the wait condition is not met, pass osaWaitForever_c will + * wait indefinitely, pass 0 will return KOSA_StatusTimeout + * immediately. + * @param pSetFlags Flags that wakeup the waiting task are obtained by this parameter. + * + * @retval KOSA_StatusSuccess The wait condition met and function returns successfully. + * @retval KOSA_StatusTimeout Has not met wait condition within timeout. + * @retval KOSA_StatusError An incorrect parameter was passed. + + * + * @note Please pay attention to the flags bit width, FreeRTOS uses the most + * significant 8 bis as control bits, so do not wait these bits while using + * FreeRTOS. + * + */ +osa_status_t OSA_EventWait(osa_event_handle_t eventHandle, + osa_event_flags_t flagsToWait, + uint8_t waitAll, + uint32_t millisec, + osa_event_flags_t *pSetFlags); + +/*! + * @brief Destroys a previously created event object. + * + * @param eventHandle The event handle. + * + * @retval KOSA_StatusSuccess The event is successfully destroyed. + * @retval KOSA_StatusError Event destruction failed. + */ +osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle); + +/*! + * @brief Initializes a message queue. + * + * This function allocates memory for and initializes a message queue. Message queue elements are hardcoded as void*. + * + * Example below shows how to use this API to create the massage queue handle. + * @code + * OSA_MSGQ_HANDLE_DEFINE(msgqHandle); + * OSA_MsgQCreate((osa_msgq_handle_t)msgqHandle, 5U, sizeof(msg)); + * @endcode + * + * @param msgqHandle Pointer to a memory space of size #(OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize) on bare-matel + * and #(OSA_MSGQ_HANDLE_SIZE) on FreeRTOS allocated by the caller, message queue handle. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_MSGQ_HANDLE_DEFINE(msgqHandle); + * or + * For bm: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * For freertos: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param msgNo :number of messages the message queue should accommodate. + * @param msgSize :size of a single message structure. + * + * @retval KOSA_StatusSuccess Message queue successfully Create. + * @retval KOSA_StatusError Message queue create failure. + */ +osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize); + +/*! + * @brief Puts a message at the end of the queue. + * + * This function puts a message to the end of the message queue. If the queue + * is full, this function returns the KOSA_StatusError; + * + * @param msgqHandle Message Queue handler. + * @param pMessage Pointer to the message to be put into the queue. + * + * @retval KOSA_StatusSuccess Message successfully put into the queue. + * @retval KOSA_StatusError The queue was full or an invalid parameter was passed. + */ +osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage); + +/*! + * @brief Reads and remove a message at the head of the queue. + * + * This function gets a message from the head of the message queue. If the + * queue is empty, timeout is used to wait. + * + * @param msgqHandle Message Queue handler. + * @param pMessage Pointer to a memory to save the message. + * @param millisec The number of milliseconds to wait for a message. If the + * queue is empty, pass osaWaitForever_c will wait indefinitely, + * pass 0 will return KOSA_StatusTimeout immediately. + * + * @retval KOSA_StatusSuccess Message successfully obtained from the queue. + * @retval KOSA_StatusTimeout The queue remains empty after timeout. + * @retval KOSA_StatusError Invalid parameter. + */ +osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec); + +/*! + * @brief Get the available message + * + * This function is used to get the available message. + * + * @param msgqHandle Message Queue handler. + * + * @return Available message count + */ +int OSA_MsgQAvailableMsgs(osa_msgq_handle_t msgqHandle); + +/*! + * @brief Destroys a previously created queue. + * + * @param msgqHandle Message Queue handler. + * + * @retval KOSA_StatusSuccess The queue was successfully destroyed. + * @retval KOSA_StatusError Message queue destruction failed. + */ +osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle); + +/*! + * @brief Enable all interrupts. + */ +void OSA_InterruptEnable(void); + +/*! + * @brief Disable all interrupts. + */ +void OSA_InterruptDisable(void); + +/*! + * @brief Enable all interrupts using PRIMASK. + */ +void OSA_EnableIRQGlobal(void); + +/*! + * @brief Disable all interrupts using PRIMASK. + */ +void OSA_DisableIRQGlobal(void); + +/*! + * @brief Delays execution for a number of milliseconds. + * + * @param millisec The time in milliseconds to wait. + */ +void OSA_TimeDelay(uint32_t millisec); + +/*! + * @brief This function gets current time in milliseconds. + * + * @retval current time in milliseconds + */ +uint32_t OSA_TimeGetMsec(void); + +/*! + * @brief Installs the interrupt handler. + * + * @param IRQNumber IRQ number of the interrupt. + * @param handler The interrupt handler to install. + */ +void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void)); + +/*! @}*/ +#ifdef __cplusplus +} +#endif +/*! @}*/ +#endif diff --git a/components/osa/fsl_os_abstraction_bm.c b/components/osa/fsl_os_abstraction_bm.c new file mode 100644 index 000000000..007cb55a0 --- /dev/null +++ b/components/osa/fsl_os_abstraction_bm.c @@ -0,0 +1,1346 @@ +/*! + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * + * + * This is the source file for the OS Abstraction layer for MQXLite. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "fsl_component_generic_list.h" +#include "fsl_os_abstraction.h" +#include "fsl_os_abstraction_bm.h" +#include + +/*! ********************************************************************************* +************************************************************************************* +* Private macros +************************************************************************************* +********************************************************************************** */ + +/* Weak function. */ +#if defined(__GNUC__) +#define __WEAK_FUNC __attribute__((weak)) +#elif defined(__ICCARM__) +#define __WEAK_FUNC __weak +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define __WEAK_FUNC __attribute__((weak)) +#endif + +#ifdef DEBUG_ASSERT +#define OS_ASSERT(condition) \ + if (!(condition)) \ + while (1) \ + ; +#else +#define OS_ASSERT(condition) (void)(condition); +#endif + +/************************************************************************************ +************************************************************************************* +* Private type definitions +************************************************************************************* +************************************************************************************/ + +/*! @brief Type for an semaphore */ +typedef struct Semaphore +{ +#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U)) + uint32_t time_start; /*!< The time to start timeout */ + uint32_t timeout; /*!< Timeout to wait in milliseconds */ +#endif + volatile uint8_t isWaiting; /*!< Is any task waiting for a timeout on this object */ + volatile uint8_t semCount; /*!< The count value of the object */ + +} semaphore_t; + +/*! @brief Type for a mutex */ +typedef struct Mutex +{ +#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U)) + uint32_t time_start; /*!< The time to start timeout */ + uint32_t timeout; /*!< Timeout to wait in milliseconds */ +#endif + volatile uint8_t isWaiting; /*!< Is any task waiting for a timeout on this mutex */ + volatile uint8_t isLocked; /*!< Is the object locked or not */ +} mutex_t; + +#define gIdleTaskPriority_c ((task_priority_t)0) +#define gInvalidTaskPriority_c ((task_priority_t)-1) + +/*! @brief Type for a task handler, returned by the OSA_TaskCreate function */ +typedef void (*task_t)(task_param_t param); +/*! @brief Task control block for bare metal. */ +typedef struct TaskControlBlock +{ + list_element_t link; + osa_task_ptr_t p_func; /*!< Task's entry */ + osa_task_priority_t priority; /*!< Task's priority */ + osa_task_param_t param; /*!< Task's parameter */ + uint8_t haveToRun; /*!< Task was signaled */ +} task_control_block_t; + +/*! @brief Type for a task pointer */ +typedef task_control_block_t *task_handler_t; + +/*! @brief Type for a task stack */ +typedef uint32_t task_stack_t; + +/*! @brief Type for an event object */ +typedef struct Event +{ + uint32_t time_start; /*!< The time to start timeout */ + uint32_t timeout; /*!< Timeout to wait in milliseconds */ + volatile event_flags_t flags; /*!< The flags status */ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + task_handler_t waitingTask; /*!< Handler to the waiting task */ +#endif + uint8_t autoClear; /*!< Auto clear or manual clear */ + volatile uint8_t isWaiting; /*!< Is any task waiting for a timeout on this event */ +} event_t; + +/*! @brief Type for a message queue */ +typedef struct MsgQueue +{ + volatile uint8_t isWaiting; /*!< Is any task waiting for a timeout */ + uint32_t time_start; /*!< The time to start timeout */ + uint32_t timeout; /*!< Timeout to wait in milliseconds */ + uint32_t size; /*!< The size(byte) of a single message */ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + task_handler_t waitingTask; /*!< Handler to the waiting task */ +#endif + uint8_t *queueMem; /*!< Points to the queue memory */ + uint16_t number; /*!< The number of messages in the queue */ + uint16_t max; /*!< The max number of queue messages */ + uint16_t head; /*!< Index of the next message to be read */ + uint16_t tail; /*!< Index of the next place to write to */ +} msg_queue_t; + +/*! @brief Type for a message queue handler */ +typedef msg_queue_t *msg_queue_handler_t; + +/*! @brief State structure for bm osa manager. */ +typedef struct _osa_state +{ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + list_label_t taskList; + task_handler_t curTaskHandler; +#endif + volatile uint32_t interruptDisableCount; + volatile uint32_t tickCounter; +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +#if (defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U)) + OSA_TASK_HANDLE_DEFINE(mainTaskHandle); +#endif +#endif +} osa_state_t; + +/*! ********************************************************************************* +************************************************************************************* +* Private prototypes +************************************************************************************* +********************************************************************************** */ +__WEAK_FUNC void main_task(osa_task_param_t arg); +__WEAK_FUNC void main_task(osa_task_param_t arg) +{ +} +__WEAK_FUNC void OSA_TimeInit(void); +__WEAK_FUNC uint32_t OSA_TimeDiff(uint32_t time_start, uint32_t time_end); + +/*! ********************************************************************************* +************************************************************************************* +* Public memory declarations +************************************************************************************* +********************************************************************************** */ +const uint8_t gUseRtos_c = USE_RTOS; /* USE_RTOS = 0 for BareMetal and 1 for OS */ + +/*! ********************************************************************************* +************************************************************************************* +* Private memory declarations +************************************************************************************* +********************************************************************************** */ +static osa_state_t s_osaState; + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MemoryAllocate + * Description : Reserves the requested amount of memory in bytes. + * + *END**************************************************************************/ +void *OSA_MemoryAllocate(uint32_t length) +{ + void *p = (void *)malloc(length); + + if (NULL != p) + { + (void)memset(p, 0, length); + } + + return p; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MemoryFree + * Description : Frees the memory previously reserved. + * + *END**************************************************************************/ +void OSA_MemoryFree(void *p) +{ + free(p); +} + +void OSA_EnterCritical(uint32_t *sr) +{ + *sr = DisableGlobalIRQ(); +} + +void OSA_ExitCritical(uint32_t sr) +{ + EnableGlobalIRQ(sr); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EnableIRQGlobal + * Description : Disable system interrupt. + * + *END**************************************************************************/ +void OSA_EnableIRQGlobal(void) +{ + if (s_osaState.interruptDisableCount > 0U) + { + s_osaState.interruptDisableCount--; + + if (0U == s_osaState.interruptDisableCount) + { + __enable_irq(); + } + /* call core API to enable the global interrupt*/ + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_DisableIRQGlobal + * Description : Disable system interrupt + * This function will disable the global interrupt by calling the core API + * + *END**************************************************************************/ +void OSA_DisableIRQGlobal(void) +{ + /* call core API to disable the global interrupt*/ + __disable_irq(); + + /* update counter*/ + s_osaState.interruptDisableCount++; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskGetCurrentHandle + * Description : This function is used to get current active task's handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_handle_t OSA_TaskGetCurrentHandle(void) +{ + return (osa_task_handle_t)s_osaState.curTaskHandler; +} +#endif +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EXT_TaskYield + * Description : When a task calls this function, it will give up CPU and put + * itself to the tail of ready list. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskYield(void) +{ + return KOSA_StatusSuccess; +} +#endif +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskGetPriority + * Description : This function returns task's priority by task handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle) +{ + assert(taskHandle); + task_handler_t handler = (task_handler_t)taskHandle; + return handler->priority; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskSetPriority + * Description : This function sets task's priority by task handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority) +{ + assert(taskHandle); + list_element_handle_t list_element; + task_control_block_t *tcb = NULL; +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + task_control_block_t *preTcb = NULL; +#endif + task_control_block_t *ptaskStruct = (task_control_block_t *)taskHandle; + uint32_t regPrimask; + + ptaskStruct->priority = taskPriority; + (void)LIST_RemoveElement(&ptaskStruct->link); + /* Insert task control block into the task list. */ + list_element = LIST_GetHead(&s_osaState.taskList); + while (NULL != list_element) + { + tcb = (task_control_block_t *)(void *)list_element; + if (ptaskStruct->priority <= tcb->priority) + { +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + if (preTcb == NULL) + { + (&tcb->link)->list->head = (struct list_element_tag *)(void *)ptaskStruct; + } + else + { + (&preTcb->link)->next = (struct list_element_tag *)(void *)ptaskStruct; + } + (&ptaskStruct->link)->list = (&tcb->link)->list; + (&ptaskStruct->link)->next = (struct list_element_tag *)(void *)tcb; + (&ptaskStruct->link)->list->size++; +#else + (void)LIST_AddPrevElement(&tcb->link, &ptaskStruct->link); +#endif + break; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + preTcb = tcb; +#endif + list_element = LIST_GetNext(list_element); + } + if (ptaskStruct->priority > tcb->priority) + { + OSA_EnterCritical(®Primask); + (void)LIST_AddTail(&s_osaState.taskList, (list_element_handle_t)(void *)&(ptaskStruct->link)); + OSA_ExitCritical(regPrimask); + } + + return KOSA_StatusSuccess; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskCreate + * Description : This function is used to create a task and make it ready. + * Param[in] : threadDef - Definition of the thread. + * task_param - Parameter to pass to the new thread. + * Return Thread handle of the new thread, or NULL if failed. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, const osa_task_def_t *thread_def, osa_task_param_t task_param) +{ + list_element_handle_t list_element; + + task_control_block_t *tcb = NULL; +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + task_control_block_t *preTcb = NULL; +#endif + list_status_t listStatus; + + task_control_block_t *ptaskStruct = (task_control_block_t *)taskHandle; + uint32_t regPrimask; + assert(sizeof(task_control_block_t) == OSA_TASK_HANDLE_SIZE); + assert(taskHandle); + + ptaskStruct->p_func = thread_def->pthread; + ptaskStruct->haveToRun = 1U; + ptaskStruct->priority = (uint16_t)PRIORITY_OSA_TO_RTOS(thread_def->tpriority); + ptaskStruct->param = task_param; + + list_element = LIST_GetHead(&s_osaState.taskList); + while (NULL != list_element) + { + tcb = (task_control_block_t *)(void *)list_element; + if (ptaskStruct->priority <= tcb->priority) + { + OSA_EnterCritical(®Primask); +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + if (preTcb == NULL) + { + (&tcb->link)->list->head = (struct list_element_tag *)(void *)ptaskStruct; + } + else + { + (&preTcb->link)->next = (struct list_element_tag *)(void *)ptaskStruct; + } + (&ptaskStruct->link)->list = (&tcb->link)->list; + (&ptaskStruct->link)->next = (struct list_element_tag *)(void *)tcb; + (&ptaskStruct->link)->list->size++; + OSA_ExitCritical(regPrimask); + return KOSA_StatusSuccess; +#else + listStatus = LIST_AddPrevElement(&tcb->link, &ptaskStruct->link); + OSA_ExitCritical(regPrimask); + if (listStatus == (list_status_t)kLIST_DuplicateError) + { + return KOSA_StatusError; + } + break; +#endif + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + preTcb = tcb; +#endif + list_element = LIST_GetNext(list_element); + } + + if ((NULL == tcb) || (ptaskStruct->priority > tcb->priority)) + { + OSA_EnterCritical(®Primask); + listStatus = LIST_AddTail(&s_osaState.taskList, (list_element_handle_t)(void *)&(ptaskStruct->link)); + (void)listStatus; + assert(listStatus == kLIST_Ok); + OSA_ExitCritical(regPrimask); + } + + return KOSA_StatusSuccess; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskDestroy + * Description : This function destroy a task. + * Param[in] :taskHandle - Thread handle. + * Return KOSA_StatusSuccess if the task is destroied, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle) +{ + uint32_t regPrimask; + assert(taskHandle); + + OSA_EnterCritical(®Primask); + (void)LIST_RemoveElement(taskHandle); + OSA_ExitCritical(regPrimask); + return KOSA_StatusSuccess; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TimeInit + * Description : This function initializes the timer used in BM OSA, the + * functions such as OSA_TimeDelay, OSA_TimeGetMsec, and the timeout are all + * based on this timer. + * + *END**************************************************************************/ +__WEAK_FUNC void OSA_TimeInit(void) +{ +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk); + SysTick->LOAD = (uint32_t)(SystemCoreClock / 1000U - 1U); + SysTick->VAL = 0; + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_CLKSOURCE_Msk; +#endif +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TimeDiff + * Description : This function gets the difference between two time stamp, + * time overflow is considered. + * + *END**************************************************************************/ +__WEAK_FUNC uint32_t OSA_TimeDiff(uint32_t time_start, uint32_t time_end) +{ + if (time_end >= time_start) + { + return time_end - time_start; + } + else + { + return FSL_OSA_TIME_RANGE - time_start + time_end + 1UL; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA__TimeDelay + * Description : This function is used to suspend the active thread for the given number of milliseconds. + * + *END**************************************************************************/ +void OSA_TimeDelay(uint32_t millisec) +{ +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + uint32_t currTime, timeStart; + + timeStart = OSA_TimeGetMsec(); + + do + { + currTime = OSA_TimeGetMsec(); /* Get current time stamp */ + } while (millisec >= OSA_TimeDiff(timeStart, currTime)); +#endif +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TimeGetMsec + * Description : This function gets current time in milliseconds. + * + *END**************************************************************************/ +__WEAK_FUNC uint32_t OSA_TimeGetMsec(void) +{ +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + return s_osaState.tickCounter; +#else + return 0; +#endif +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreCreate + * Description : This function is used to create a semaphore. + * Return : Semaphore handle of the new semaphore, or NULL if failed. + * + *END**************************************************************************/ + +osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue) +{ + semaphore_t *pSemStruct = (semaphore_t *)semaphoreHandle; + assert(sizeof(semaphore_t) <= OSA_SEM_HANDLE_SIZE); + assert(semaphoreHandle); + + pSemStruct->semCount = (uint8_t)initValue; + pSemStruct->isWaiting = 0U; +#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U)) +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + + pSemStruct->time_start = 0U; + pSemStruct->timeout = 0U; +#endif +#endif + return KOSA_StatusSuccess; +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreDestroy + * Description : This function is used to destroy a semaphore. + * Return : KOSA_StatusSuccess if the semaphore is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle) +{ + assert(semaphoreHandle); + semaphore_t *pSemStruct = (semaphore_t *)semaphoreHandle; + + /* Destroy semaphoreHandle's data */ + (void)memset(pSemStruct, 0, sizeof(semaphore_t)); + + return KOSA_StatusSuccess; +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreWait + * Description : This function checks the semaphore's counting value, if it is + * positive, decreases it and returns KOSA_StatusSuccess, otherwise, timeout + * will be used for wait. The parameter timeout indicates how long should wait + * in milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will + * return KOSA_StatusTimeout immediately if semaphore is not positive. + * This function returns KOSA_StatusSuccess if the semaphore is received, returns + * KOSA_StatusTimeout if the semaphore is not received within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec) +{ + semaphore_t *pSemStruct = (semaphore_t *)semaphoreHandle; + uint32_t regPrimask; + assert(semaphoreHandle); +#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U)) +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + uint32_t currentTime; +#endif +#endif + /* Check the sem count first. Deal with timeout only if not already set */ + + if (0U != pSemStruct->semCount) + { + OSA_EnterCritical(®Primask); + pSemStruct->semCount--; + pSemStruct->isWaiting = 0U; + OSA_ExitCritical(regPrimask); + return KOSA_StatusSuccess; + } + else + { + if (0U == millisec) + { + /* If timeout is 0 and semaphore is not available, return kStatus_OSA_Timeout. */ + return KOSA_StatusTimeout; + } +#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U)) +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + else if (0U != pSemStruct->isWaiting) + { + /* Check for timeout */ + currentTime = OSA_TimeGetMsec(); + if (pSemStruct->timeout < OSA_TimeDiff(pSemStruct->time_start, currentTime)) + { + OSA_EnterCritical(®Primask); + pSemStruct->isWaiting = 0U; + OSA_ExitCritical(regPrimask); + return KOSA_StatusTimeout; + } + } + else if (millisec != osaWaitForever_c) /* If don't wait forever, start the timer */ + { + /* Start the timeout counter */ + OSA_EnterCritical(®Primask); + pSemStruct->isWaiting = 1U; + OSA_ExitCritical(regPrimask); + pSemStruct->time_start = OSA_TimeGetMsec(); + pSemStruct->timeout = millisec; + } +#endif +#endif + else + { + ; + } + } + + return KOSA_StatusIdle; +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphorePost + * Description : This function is used to wake up one task that wating on the + * semaphore. If no task is waiting, increase the semaphore. The function returns + * KOSA_StatusSuccess if the semaphre is post successfully, otherwise returns + * KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle) +{ + semaphore_t *pSemStruct = (semaphore_t *)semaphoreHandle; + uint32_t regPrimask; + assert(semaphoreHandle); + + /* The max value is 0xFF */ + if (0xFFU == pSemStruct->semCount) + { + return KOSA_StatusError; + } + OSA_EnterCritical(®Primask); + ++pSemStruct->semCount; + OSA_ExitCritical(regPrimask); + + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexCreate + * Description : This function is used to create a mutex. + * Return : Mutex handle of the new mutex, or NULL if failed. + * + *END**************************************************************************/ +osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle) +{ + mutex_t *pMutexStruct = (mutex_t *)mutexHandle; + assert(sizeof(mutex_t) <= OSA_MUTEX_HANDLE_SIZE); + assert(mutexHandle); + + pMutexStruct->isLocked = 0U; + pMutexStruct->isWaiting = 0U; +#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U)) +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + + pMutexStruct->time_start = 0u; + pMutexStruct->timeout = 0u; +#endif +#endif + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexLock + * Description : This function checks the mutex's status, if it is unlocked, + * lock it and returns KOSA_StatusSuccess, otherwise, wait for the mutex. + * MQX does not support timeout to wait for a mutex. + * This function returns KOSA_StatusSuccess if the mutex is obtained, returns + * KOSA_StatusError if any errors occur during waiting. If the mutex has been + * locked, pass 0 as timeout will return KOSA_StatusTimeout immediately. + * + *END**************************************************************************/ +osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec) +{ +#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U)) +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + uint32_t currentTime; +#endif +#endif + mutex_t *pMutexStruct = (mutex_t *)mutexHandle; + uint32_t regPrimask; + + /* Always check first. Deal with timeout only if not available. */ + if (0U == pMutexStruct->isLocked) + { + /* Get the lock and return success */ + OSA_EnterCritical(®Primask); + pMutexStruct->isLocked = 1U; + pMutexStruct->isWaiting = 0U; + OSA_ExitCritical(regPrimask); + return KOSA_StatusSuccess; + } + else + { + if (0U == millisec) + { + /* If timeout is 0 and mutex is not available, return kStatus_OSA_Timeout. */ + return KOSA_StatusTimeout; + } +#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U)) +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + else if (pMutexStruct->isWaiting != 0U) + { + /* Check for timeout */ + currentTime = OSA_TimeGetMsec(); + if (pMutexStruct->timeout < OSA_TimeDiff(pMutexStruct->time_start, currentTime)) + { + OSA_EnterCritical(®Primask); + pMutexStruct->isWaiting = 0U; + OSA_ExitCritical(regPrimask); + return KOSA_StatusTimeout; + } + } + else if (millisec != osaWaitForever_c) /* If dont't wait forever, start timer. */ + { + /* Start the timeout counter */ + OSA_EnterCritical(®Primask); + pMutexStruct->isWaiting = 1U; + OSA_ExitCritical(regPrimask); + pMutexStruct->time_start = OSA_TimeGetMsec(); + pMutexStruct->timeout = millisec; + } +#endif +#endif + else + { + ; + } + } + + return KOSA_StatusIdle; +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexUnlock + * Description : This function is used to unlock a mutex. + * + *END**************************************************************************/ +osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle) +{ + mutex_t *pMutexStruct = (mutex_t *)mutexHandle; + uint32_t regPrimask; + assert(mutexHandle); + + OSA_EnterCritical(®Primask); + pMutexStruct->isLocked = 0U; + OSA_ExitCritical(regPrimask); + return KOSA_StatusSuccess; +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexDestroy + * Description : This function is used to destroy a mutex. + * Return : KOSA_StatusSuccess if the lock object is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle) +{ + assert(mutexHandle); + mutex_t *pMutexStruct = (mutex_t *)mutexHandle; + + /* Destory mutexHandle's data */ + (void)memset(pMutexStruct, 0, sizeof(mutex_t)); + + return KOSA_StatusSuccess; +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventCreate + * Description : This function is used to create a event object. + * Return : Event handle of the new event, or NULL if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear) +{ + event_t *pEventStruct = eventHandle; + assert(sizeof(event_t) == OSA_EVENT_HANDLE_SIZE); + assert(eventHandle); + + pEventStruct->isWaiting = 0U; + pEventStruct->flags = 0; + pEventStruct->autoClear = autoClear; + pEventStruct->time_start = 0u; + pEventStruct->timeout = 0u; +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + pEventStruct->waitingTask = NULL; +#endif + return KOSA_StatusSuccess; +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventSet + * Description : Set one or more event flags of an event object. + * Return : KOSA_StatusSuccess if set successfully, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet) +{ + event_t *pEventStruct; + uint32_t regPrimask; + pEventStruct = (event_t *)eventHandle; + /* Set flags ensuring atomic operation */ + OSA_EnterCritical(®Primask); + pEventStruct->flags |= flagsToSet; +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + if (pEventStruct->waitingTask != NULL) + { + pEventStruct->waitingTask->haveToRun = 1U; + } +#endif + OSA_ExitCritical(regPrimask); + + return KOSA_StatusSuccess; +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventClear + * Description : Clear one or more event flags of an event object. + * Return :KOSA_StatusSuccess if clear successfully, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear) +{ + event_t *pEventStruct; + uint32_t regPrimask; + pEventStruct = (event_t *)eventHandle; + /* Clear flags ensuring atomic operation */ + OSA_EnterCritical(®Primask); + pEventStruct->flags &= ~flagsToClear; + if (0U != pEventStruct->flags) + { +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + if (NULL != pEventStruct->waitingTask) + { + pEventStruct->waitingTask->haveToRun = 1U; + } +#endif + } + OSA_ExitCritical(regPrimask); + + return KOSA_StatusSuccess; +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventGet + * Description : This function is used to get event's flags that specified by prameter + * flagsMask, and the flags (user specified) are obatianed by parameter pFlagsOfEvent. So + * you should pass the parameter 0xffffffff to specify you want to get all. + * Return :KOSA_StatusSuccess if event flags were successfully got, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, osa_event_flags_t flagsMask, osa_event_flags_t *pFlagsOfEvent) +{ + event_t *pEventStruct; + pEventStruct = (event_t *)eventHandle; + OSA_SR_ALLOC(); + + if (NULL == pFlagsOfEvent) + { + return KOSA_StatusError; + } + + OSA_ENTER_CRITICAL(); + *pFlagsOfEvent = pEventStruct->flags & flagsMask; + OSA_EXIT_CRITICAL(); + + return KOSA_StatusSuccess; +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventWait + * Description : This function checks the event's status, if it meets the wait + * condition, return KOSA_StatusSuccess, otherwise, timeout will be used for + * wait. The parameter timeout indicates how long should wait in milliseconds. + * Pass osaWaitForever_c to wait indefinitely, pass 0 will return the value + * KOSA_StatusTimeout immediately if wait condition is not met. The event flags + * will be cleared if the event is auto clear mode. Flags that wakeup waiting + * task could be obtained from the parameter setFlags. + * This function returns KOSA_StatusSuccess if wait condition is met, returns + * KOSA_StatusTimeout if wait condition is not met within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_EventWait(osa_event_handle_t eventHandle, + osa_event_flags_t flagsToWait, + uint8_t waitAll, + uint32_t millisec, + osa_event_flags_t *pSetFlags) +{ + event_t *pEventStruct; + uint32_t regPrimask; +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + uint32_t currentTime; +#endif + osa_status_t retVal = KOSA_StatusIdle; + if (NULL == pSetFlags) + { + return KOSA_StatusError; + } + + pEventStruct = (event_t *)eventHandle; + + OSA_EnterCritical(®Primask); +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +#if (TASK_MAX_NUM > 0) + pEventStruct->waitingTask = OSA_TaskGetCurrentHandle(); +#endif +#endif + + *pSetFlags = pEventStruct->flags & flagsToWait; + + /* Check the event flag first, if does not meet wait condition, deal with timeout. */ + if (((0U == waitAll) && (0U != *pSetFlags)) || (*pSetFlags == flagsToWait)) + { + pEventStruct->isWaiting = 0U; + if (1U == pEventStruct->autoClear) + { + pEventStruct->flags &= ~flagsToWait; + } + retVal = KOSA_StatusSuccess; + } + else + { + if (0U == millisec) + { + /* If timeout is 0 and wait condition is not met, return kStatus_OSA_Timeout. */ + retVal = KOSA_StatusTimeout; + } +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + else if (0U != pEventStruct->isWaiting) + { + /* Check for timeout */ + currentTime = OSA_TimeGetMsec(); + if (pEventStruct->timeout < OSA_TimeDiff(pEventStruct->time_start, currentTime)) + { + pEventStruct->isWaiting = 0U; + retVal = KOSA_StatusTimeout; + } + } + else if (millisec != osaWaitForever_c) /* If no timeout, don't start the timer */ + { + /* Start the timeout counter */ + pEventStruct->isWaiting = 1U; + pEventStruct->time_start = OSA_TimeGetMsec(); + pEventStruct->timeout = millisec; + } +#endif + else + { +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + pEventStruct->waitingTask->haveToRun = 0U; +#endif + } + } + + OSA_ExitCritical(regPrimask); + + return retVal; +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventDestroy + * Description : This function is used to destroy a event object. Return + * KOSA_StatusSuccess if the event object is destroyed successfully, otherwise + * return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle) +{ + assert(eventHandle); + event_t *pEventStruct = (event_t *)eventHandle; + + /* Destroy eventHandle's data */ + (void)memset(pEventStruct, 0, sizeof(event_t)); + + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQCreate + * Description : This function is used to create a message queue. + * Return : the handle to the message queue if create successfully, otherwise + * return NULL. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize) +{ + msg_queue_t *pMsgQStruct = msgqHandle; + assert(sizeof(msg_queue_t) == OSA_MSGQ_HANDLE_SIZE); + assert(msgqHandle); + + pMsgQStruct->max = (uint16_t)msgNo; + pMsgQStruct->number = 0; + pMsgQStruct->head = 0; + pMsgQStruct->tail = 0; + pMsgQStruct->size = msgSize; + pMsgQStruct->queueMem = (uint8_t *)((uint8_t *)msgqHandle + sizeof(msg_queue_t)); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQPut + * Description : This function is used to put a message to a message queue. + * Return : KOSA_StatusSuccess if the message is put successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage) +{ + assert(msgqHandle); + msg_queue_t *pQueue; + osa_status_t status = KOSA_StatusSuccess; + uint32_t regPrimask; + + uint8_t *pMsgArray; + + pQueue = (msg_queue_t *)msgqHandle; + + if (NULL == pQueue->queueMem) + { + return KOSA_StatusError; + } + + OSA_EnterCritical(®Primask); + if (pQueue->number >= pQueue->max) + { + status = KOSA_StatusError; + } + else + { + pMsgArray = &pQueue->queueMem[pQueue->tail]; + for (uint32_t i = 0; i < pQueue->size; i++) + { + pMsgArray[i] = *((uint8_t *)pMessage + i); + } + + pQueue->number++; + pQueue->tail += (uint16_t)pQueue->size; + + if (pQueue->tail >= (pQueue->max * pQueue->size)) + { + pQueue->tail = 0; + } +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + if (NULL != pQueue->waitingTask) + { + pQueue->waitingTask->haveToRun = 1U; + } +#endif + } + OSA_ExitCritical(regPrimask); + return status; +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQGet + * Description : This function checks the queue's status, if it is not empty, + * get message from it and return KOSA_StatusSuccess, otherwise, timeout will + * be used for wait. The parameter timeout indicates how long should wait in + * milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will return + * KOSA_StatusTimeout immediately if queue is empty. + * This function returns KOSA_StatusSuccess if message is got successfully, + * returns KOSA_StatusTimeout if message queue is empty within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec) +{ + assert(msgqHandle); + msg_queue_t *pQueue; + osa_status_t status = KOSA_StatusSuccess; + uint32_t regPrimask; + + uint8_t *pMsgArray; + +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + uint32_t currentTime; +#endif + + pQueue = (msg_queue_t *)msgqHandle; + + if (NULL == pQueue->queueMem) + { + return KOSA_StatusError; + } + +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + pQueue->waitingTask = OSA_TaskGetCurrentHandle(); +#endif + + OSA_EnterCritical(®Primask); + if (0U != pQueue->number) + { + pMsgArray = (uint8_t *)pMessage; + for (uint32_t i = 0; i < pQueue->size; i++) + { + pMsgArray[i] = pQueue->queueMem[pQueue->head + i]; + } + + pQueue->number--; + pQueue->head += (uint16_t)pQueue->size; + pQueue->isWaiting = 0U; + + if (pQueue->head >= (pQueue->max * pQueue->size)) + { + pQueue->head = 0; + } + status = KOSA_StatusSuccess; + } + else + { + if (0U == millisec) + { + /* If timeout is 0 and wait condition is not met, return kStatus_OSA_Timeout. */ + status = KOSA_StatusTimeout; + } +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + else if (0U != pQueue->isWaiting) + { + /* Check for timeout */ + status = KOSA_StatusIdle; /* Before a timeout, the status should be idle. */ + currentTime = OSA_TimeGetMsec(); + if (pQueue->timeout < OSA_TimeDiff(pQueue->time_start, currentTime)) + { + pQueue->isWaiting = 0U; + status = KOSA_StatusTimeout; + } + } + else if (millisec != osaWaitForever_c) /* If no timeout, don't start the timer */ + { + /* Start the timeout counter */ + pQueue->isWaiting = 1U; + pQueue->time_start = OSA_TimeGetMsec(); + pQueue->timeout = millisec; + status = KOSA_StatusIdle; + } +#endif + else + { +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + pQueue->waitingTask->haveToRun = 0U; +#endif + status = KOSA_StatusIdle; + } + } + OSA_ExitCritical(regPrimask); + + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQAvailableMsgs + * Description : This function is used to get the available message. + * Return : Available message count + * + *END**************************************************************************/ +int OSA_MsgQAvailableMsgs(osa_msgq_handle_t msgqHandle) +{ + assert(msgqHandle); + msg_queue_t *pQueue = (msg_queue_t *)msgqHandle; + + return (int)pQueue->number; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EXT_MsgQDestroy + * Description : This function is used to destroy the message queue. + * Return : KOSA_StatusSuccess if the message queue is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle) +{ + assert(msgqHandle); + msg_queue_t *pQueue = (msg_queue_t *)msgqHandle; + + /* Destory msgqHandle's data */ + /* OSA_MsgQGet() & OSA_MsgQPut() will check queueMem, if NULL will return an error. */ + (void)memset(pQueue, 0, sizeof(msg_queue_t)); + + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptEnable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptEnable(void) +{ + OSA_EnableIRQGlobal(); +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptDisable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptDisable(void) +{ + OSA_DisableIRQGlobal(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InstallIntHandler + * Description : This function is used to install interrupt handler. + * + *END**************************************************************************/ +void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void)) +{ +#if defined(__IAR_SYSTEMS_ICC__) + _Pragma("diag_suppress = Pm138") +#endif +#if defined(ENABLE_RAM_VECTOR_TABLE) + (void) InstallIRQHandler((IRQn_Type)IRQNumber, (uint32_t) * (uint32_t *)&handler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#if defined(__IAR_SYSTEMS_ICC__) + _Pragma("diag_remark = PM138") +#endif +} + +/*! ********************************************************************************* +************************************************************************************* +* Private functions +************************************************************************************* +********************************************************************************** */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +#if (defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U)) +static OSA_TASK_DEFINE(main_task, gMainThreadPriority_c, 1, gMainThreadStackSize_c, 0); + +void main(void) +{ + OSA_Init(); + + /* Initialize MCU clock */ + extern void BOARD_InitHardware(void); + BOARD_InitHardware(); + + (void)OSA_TaskCreate((osa_task_handle_t)s_osaState.mainTaskHandle, OSA_TASK(main_task), NULL); + + OSA_Start(); +} +#endif /*(defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U))*/ +#endif /* FSL_OSA_TASK_ENABLE */ + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_Init + * Description : This function is used to setup the basic services, it should + * be called first in function main. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +void OSA_Init(void) +{ + LIST_Init((&s_osaState.taskList), 0); + s_osaState.curTaskHandler = NULL; + s_osaState.interruptDisableCount = 0U; + s_osaState.tickCounter = 0U; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_Start + * Description : This function is used to start RTOS scheduler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +void OSA_Start(void) +{ + list_element_handle_t list_element; + task_control_block_t *tcb; + +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + OSA_TimeInit(); +#endif + + while (true) + { + list_element = LIST_GetHead(&s_osaState.taskList); + while (NULL != list_element) + { + tcb = (task_control_block_t *)(void *)list_element; + s_osaState.curTaskHandler = (osa_task_handle_t)tcb; + if (0U != tcb->haveToRun) + { + if (NULL != tcb->p_func) + { + tcb->p_func(tcb->param); + } + list_element = LIST_GetHead(&s_osaState.taskList); + } + else + { + list_element = LIST_GetNext(list_element); + } + } + } +} + +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : SysTick_Handler + * Description : This ISR of the SYSTICK timer. + * + *END**************************************************************************/ +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) +void SysTick_Handler(void); +void SysTick_Handler(void) +{ + s_osaState.tickCounter++; +} +#endif diff --git a/components/osa/fsl_os_abstraction_bm.h b/components/osa/fsl_os_abstraction_bm.h new file mode 100644 index 000000000..84a5bd17a --- /dev/null +++ b/components/osa/fsl_os_abstraction_bm.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#if !defined(__FSL_OS_ABSTRACTION_BM_H__) +#define __FSL_OS_ABSTRACTION_BM_H__ + +/*! + * @addtogroup os_abstraction_bm + * @{ + */ + +/******************************************************************************* + * Declarations + ******************************************************************************/ +/*! @brief Bare Metal does not use timer. */ +#ifndef FSL_OSA_BM_TIMER_NONE +#define FSL_OSA_BM_TIMER_NONE 0U +#endif + +/*! @brief Bare Metal uses SYSTICK as timer. */ +#ifndef FSL_OSA_BM_TIMER_SYSTICK +#define FSL_OSA_BM_TIMER_SYSTICK 1U +#endif + +/*! @brief Configure what timer is used in Bare Metal. */ +#ifndef FSL_OSA_BM_TIMER_CONFIG +#define FSL_OSA_BM_TIMER_CONFIG FSL_OSA_BM_TIMER_NONE +#endif + +/*! @brief Type for task parameter */ +typedef void *task_param_t; + +/*! @brief Type for an event flags group, bit 32 is reserved */ +typedef uint32_t event_flags_t; + +/*! @brief Constant to pass as timeout value in order to wait indefinitely. */ +#define OSA_WAIT_FOREVER 0xFFFFFFFFU + +/*! @brief How many tasks can the bare metal support. */ +#ifndef TASK_MAX_NUM +#define TASK_MAX_NUM 7 +#endif + +/*! @brief OSA's time range in millisecond, OSA time wraps if exceeds this value. */ +#define FSL_OSA_TIME_RANGE 0xFFFFFFFFU + +/*! @brief The default interrupt handler installed in vector table. */ +#define OSA_DEFAULT_INT_HANDLER ((osa_int_handler_t)(&DefaultISR)) + +/*! @brief The default interrupt handler installed in vector table. */ +extern void DefaultISR(void); + +/*! + * @name Thread management + * @{ + */ + +/*! + * @brief To provide unified priority for upper layer, OSA layer makes conversation. + */ +#define PRIORITY_OSA_TO_RTOS(osa_prio) (osa_prio) +#define PRIORITY_RTOS_TO_OSA(rtos_prio) (rtos_prio) + +/*! @}*/ +/*! @}*/ +#endif /* __FSL_OS_ABSTRACTION_BM_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/components/osa/fsl_os_abstraction_config.h b/components/osa/fsl_os_abstraction_config.h new file mode 100644 index 000000000..7996d93dd --- /dev/null +++ b/components/osa/fsl_os_abstraction_config.h @@ -0,0 +1,44 @@ +/*! + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_ +#define _FSL_OS_ABSTRACTION_CONFIG_H_ + +#ifndef gMainThreadStackSize_c +#define gMainThreadStackSize_c 1024 +#endif + +#ifndef gMainThreadPriority_c +#define gMainThreadPriority_c 7 +#endif + +#ifndef gTaskMultipleInstancesManagement_c +#define gTaskMultipleInstancesManagement_c 0 +#endif + +/*! @brief Definition to determine whether enable OSA's TASK module. */ +#ifndef OSA_USED +#ifndef FSL_OSA_TASK_ENABLE +#define FSL_OSA_TASK_ENABLE 0U +#endif +#else +#if defined(FSL_OSA_TASK_ENABLE) +#undef FSL_OSA_TASK_ENABLE +#endif +#define FSL_OSA_TASK_ENABLE 1U +#endif /* OSA_USED */ + +#ifndef FSL_OSA_MAIN_FUNC_ENABLE +#define FSL_OSA_MAIN_FUNC_ENABLE 1U +#endif + +#ifndef FSL_OSA_BM_TIMEOUT_ENABLE +#define FSL_OSA_BM_TIMEOUT_ENABLE 0U +#endif + +#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */ diff --git a/components/osa/fsl_os_abstraction_free_rtos.c b/components/osa/fsl_os_abstraction_free_rtos.c new file mode 100644 index 000000000..24cf2317b --- /dev/null +++ b/components/osa/fsl_os_abstraction_free_rtos.c @@ -0,0 +1,1088 @@ +/*! ********************************************************************************* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2019 NXP + * All rights reserved. + * + * + * This is the source file for the OS Abstraction layer for freertos. + * + * SPDX-License-Identifier: BSD-3-Clause + ********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "fsl_common.h" +#include "fsl_os_abstraction.h" +#include "fsl_os_abstraction_free_rtos.h" +#include +#include "fsl_component_generic_list.h" + +/*! ********************************************************************************* +************************************************************************************* +* Private macros +************************************************************************************* +********************************************************************************** */ + +/* Weak function. */ +#if defined(__GNUC__) +#define __WEAK_FUNC __attribute__((weak)) +#elif defined(__ICCARM__) +#define __WEAK_FUNC __weak +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define __WEAK_FUNC __attribute__((weak)) +#endif + +#define millisecToTicks(millisec) (((millisec)*configTICK_RATE_HZ + 999U) / 1000U) + +#ifdef DEBUG_ASSERT +#define OS_ASSERT(condition) \ + if (!(condition)) \ + while (1) \ + ; +#else +#define OS_ASSERT(condition) (void)(condition); +#endif + +/*! @brief Converts milliseconds to ticks*/ +#define MSEC_TO_TICK(msec) \ + (((uint32_t)(msec) + 500uL / (uint32_t)configTICK_RATE_HZ) * (uint32_t)configTICK_RATE_HZ / 1000uL) +#define TICKS_TO_MSEC(tick) ((uint32_t)((uint64_t)(tick)*1000uL / (uint64_t)configTICK_RATE_HZ)) +/************************************************************************************ +************************************************************************************* +* Private type definitions +************************************************************************************* +************************************************************************************/ +typedef struct osa_freertos_task +{ + list_element_t link; + TaskHandle_t taskHandle; +} osa_freertos_task_t; + +typedef struct _osa_event_struct +{ + EventGroupHandle_t handle; /* The event handle */ + uint8_t autoClear; /*!< Auto clear or manual clear */ +} osa_event_struct_t; + +/*! @brief State structure for bm osa manager. */ +typedef struct _osa_state +{ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + list_label_t taskList; +#if (defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U)) + OSA_TASK_HANDLE_DEFINE(mainTaskHandle); +#endif +#endif + uint32_t basePriority; + int32_t basePriorityNesting; + uint32_t interruptDisableCount; +} osa_state_t; + +/*! ********************************************************************************* +************************************************************************************* +* Private prototypes +************************************************************************************* +********************************************************************************** */ +__WEAK_FUNC void main_task(void const *argument); +__WEAK_FUNC void main_task(void const *argument) +{ +} + +void startup_task(void *argument); + +/*! ********************************************************************************* +************************************************************************************* +* Public memory declarations +************************************************************************************* +********************************************************************************** */ +const uint8_t gUseRtos_c = USE_RTOS; /* USE_RTOS = 0 for BareMetal and 1 for OS */ + +static osa_state_t s_osaState = {0}; +/*! ********************************************************************************* +************************************************************************************* +* Private memory declarations +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MemoryAllocate + * Description : Reserves the requested amount of memory in bytes. + * + *END**************************************************************************/ +void *OSA_MemoryAllocate(uint32_t length) +{ + void *p = (void *)pvPortMalloc(length); + + if (NULL != p) + { + (void)memset(p, 0, length); + } + + return p; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MemoryFree + * Description : Frees the memory previously reserved. + * + *END**************************************************************************/ +void OSA_MemoryFree(void *p) +{ + vPortFree(p); +} + +void OSA_EnterCritical(uint32_t *sr) +{ +#if defined(__GIC_PRIO_BITS) + if ((__get_CPSR() & CPSR_M_Msk) == 0x13) +#else + if (0U != __get_IPSR()) +#endif + { + *sr = portSET_INTERRUPT_MASK_FROM_ISR(); + } + else + { + portENTER_CRITICAL(); + } +} + +void OSA_ExitCritical(uint32_t sr) +{ +#if defined(__GIC_PRIO_BITS) + if ((__get_CPSR() & CPSR_M_Msk) == 0x13) +#else + if (0U != __get_IPSR()) +#endif + { + portCLEAR_INTERRUPT_MASK_FROM_ISR(sr); + } + else + { + portEXIT_CRITICAL(); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : startup_task + * Description : Wrapper over main_task.. + * + *END**************************************************************************/ +void startup_task(void *argument) +{ + main_task(argument); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskGetCurrentHandle + * Description : This function is used to get current active task's handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_handle_t OSA_TaskGetCurrentHandle(void) +{ + list_element_handle_t list_element; + osa_freertos_task_t *ptask; + + list_element = LIST_GetHead(&s_osaState.taskList); + while (NULL != list_element) + { + ptask = (osa_freertos_task_t *)(void *)list_element; + if (ptask->taskHandle == xTaskGetCurrentTaskHandle()) + { + return (osa_task_handle_t)ptask; + } + list_element = LIST_GetNext(list_element); + } + return NULL; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskYield + * Description : When a task calls this function, it will give up CPU and put + * itself to the tail of ready list. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskYield(void) +{ + taskYIELD(); + return KOSA_StatusSuccess; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskGetPriority + * Description : This function returns task's priority by task handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle) +{ + assert(NULL != taskHandle); + osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; + return (osa_task_priority_t)(PRIORITY_RTOS_TO_OSA(uxTaskPriorityGet(ptask->taskHandle))); +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskSetPriority + * Description : This function sets task's priority by task handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority) +{ + assert(NULL != taskHandle); + osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; + vTaskPrioritySet((task_handler_t)ptask->taskHandle, PRIORITY_OSA_TO_RTOS(taskPriority)); + return KOSA_StatusSuccess; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskCreate + * Description : This function is used to create a task and make it ready. + * Param[in] : threadDef - Definition of the thread. + * task_param - Parameter to pass to the new thread. + * Return Thread handle of the new thread, or NULL if failed. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, const osa_task_def_t *thread_def, osa_task_param_t task_param) +{ + assert(sizeof(osa_freertos_task_t) == OSA_TASK_HANDLE_SIZE); + assert(NULL != taskHandle); + TaskHandle_t pxCreatedTask; + osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; + + if (xTaskCreate((TaskFunction_t)thread_def->pthread, /* pointer to the task */ + (char const *)thread_def->tname, /* task name for kernel awareness debugging */ + (configSTACK_DEPTH_TYPE)thread_def->stacksize / sizeof(portSTACK_TYPE), /* task stack size */ + (task_param_t)task_param, /* optional task startup argument */ + PRIORITY_OSA_TO_RTOS(thread_def->tpriority), /* initial priority */ + &pxCreatedTask /* optional task handle to create */ + ) == pdPASS) + { + ptask->taskHandle = pxCreatedTask; + OSA_InterruptDisable(); + (void)LIST_AddTail(&s_osaState.taskList, (list_element_handle_t) & (ptask->link)); + OSA_InterruptEnable(); + return KOSA_StatusSuccess; + } + return KOSA_StatusError; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskDestroy + * Description : This function destroy a task. + * Param[in] :taskHandle - Thread handle. + * Return KOSA_StatusSuccess if the task is destroied, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle) +{ + assert(NULL != taskHandle); + osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; + osa_status_t status; + uint16_t oldPriority; + /*Change priority to avoid context switches*/ + oldPriority = OSA_TaskGetPriority(OSA_TaskGetCurrentHandle()); + (void)OSA_TaskSetPriority(OSA_TaskGetCurrentHandle(), OSA_PRIORITY_REAL_TIME); +#if INCLUDE_vTaskDelete /* vTaskDelete() enabled */ + vTaskDelete((task_handler_t)ptask->taskHandle); + status = KOSA_StatusSuccess; +#else + status = KOSA_StatusError; /* vTaskDelete() not available */ +#endif + (void)OSA_TaskSetPriority(OSA_TaskGetCurrentHandle(), oldPriority); + OSA_InterruptDisable(); + (void)LIST_RemoveElement(taskHandle); + OSA_InterruptEnable(); + return status; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TimeDelay + * Description : This function is used to suspend the active thread for the given number of milliseconds. + * + *END**************************************************************************/ +void OSA_TimeDelay(uint32_t millisec) +{ + vTaskDelay(millisecToTicks(millisec)); +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TimeGetMsec + * Description : This function gets current time in milliseconds. + * + *END**************************************************************************/ +uint32_t OSA_TimeGetMsec(void) +{ + TickType_t ticks; + + if (0U != __get_IPSR()) + { + ticks = xTaskGetTickCountFromISR(); + } + else + { + ticks = xTaskGetTickCount(); + } + + return TICKS_TO_MSEC(ticks); +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreCreate + * Description : This function is used to create a semaphore. + * Return : Semaphore handle of the new semaphore, or NULL if failed. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue) +{ + assert(sizeof(osa_semaphore_handle_t) == OSA_SEM_HANDLE_SIZE); + assert(NULL != semaphoreHandle); + + union + { + QueueHandle_t sem; + uint32_t semhandle; + } xSemaHandle; + + xSemaHandle.sem = xSemaphoreCreateCounting(0xFF, initValue); + if (NULL != xSemaHandle.sem) + { + *(uint32_t *)semaphoreHandle = xSemaHandle.semhandle; + return KOSA_StatusSuccess; + } + return KOSA_StatusError; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreDestroy + * Description : This function is used to destroy a semaphore. + * Return : KOSA_StatusSuccess if the semaphore is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle) +{ + assert(NULL != semaphoreHandle); + QueueHandle_t sem = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle); + + vSemaphoreDelete(sem); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreWait + * Description : This function checks the semaphore's counting value, if it is + * positive, decreases it and returns KOSA_StatusSuccess, otherwise, timeout + * will be used for wait. The parameter timeout indicates how long should wait + * in milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will + * return KOSA_StatusTimeout immediately if semaphore is not positive. + * This function returns KOSA_StatusSuccess if the semaphore is received, returns + * KOSA_StatusTimeout if the semaphore is not received within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec) +{ + uint32_t timeoutTicks; + assert(NULL != semaphoreHandle); + QueueHandle_t sem = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle); + + /* Convert timeout from millisecond to tick. */ + if (millisec == osaWaitForever_c) + { + timeoutTicks = portMAX_DELAY; + } + else + { + timeoutTicks = MSEC_TO_TICK(millisec); + } + + if (pdFALSE == xSemaphoreTake(sem, timeoutTicks)) + { + return KOSA_StatusTimeout; /* timeout */ + } + else + { + return KOSA_StatusSuccess; /* semaphore taken */ + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphorePost + * Description : This function is used to wake up one task that wating on the + * semaphore. If no task is waiting, increase the semaphore. The function returns + * KOSA_StatusSuccess if the semaphre is post successfully, otherwise returns + * KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle) +{ + assert(NULL != semaphoreHandle); + osa_status_t status = KOSA_StatusError; + QueueHandle_t sem = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle); + + if (0U != __get_IPSR()) + { + portBASE_TYPE taskToWake = pdFALSE; + + if (pdTRUE == xSemaphoreGiveFromISR(sem, &taskToWake)) + { + portYIELD_FROM_ISR((taskToWake)); + status = KOSA_StatusSuccess; + } + else + { + status = KOSA_StatusError; + } + } + else + { + if (pdTRUE == xSemaphoreGive(sem)) + { + status = KOSA_StatusSuccess; /* sync object given */ + } + else + { + status = KOSA_StatusError; + } + } + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexCreate + * Description : This function is used to create a mutex. + * Return : Mutex handle of the new mutex, or NULL if failed. + * + *END**************************************************************************/ +osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle) +{ + assert(sizeof(osa_mutex_handle_t) == OSA_MUTEX_HANDLE_SIZE); + assert(NULL != mutexHandle); + + union + { + QueueHandle_t mutex; + uint32_t pmutexHandle; + } xMutexHandle; + + xMutexHandle.mutex = xSemaphoreCreateRecursiveMutex(); + if (NULL != xMutexHandle.mutex) + { + *(uint32_t *)mutexHandle = xMutexHandle.pmutexHandle; + return KOSA_StatusSuccess; + } + return KOSA_StatusError; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexLock + * Description : This function checks the mutex's status, if it is unlocked, + * lock it and returns KOSA_StatusSuccess, otherwise, wait for the mutex. + * This function returns KOSA_StatusSuccess if the mutex is obtained, returns + * KOSA_StatusError if any errors occur during waiting. If the mutex has been + * locked, pass 0 as timeout will return KOSA_StatusTimeout immediately. + * + *END**************************************************************************/ +osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec) +{ + assert(NULL != mutexHandle); + uint32_t timeoutTicks; + QueueHandle_t mutex = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle); + + /* Convert timeout from millisecond to tick. */ + if (millisec == osaWaitForever_c) + { + timeoutTicks = portMAX_DELAY; + } + else + { + timeoutTicks = MSEC_TO_TICK(millisec); + } + + if (pdFALSE == xSemaphoreTakeRecursive(mutex, timeoutTicks)) + { + return KOSA_StatusTimeout; /* timeout */ + } + else + { + return KOSA_StatusSuccess; /* semaphore taken */ + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexUnlock + * Description : This function is used to unlock a mutex. + * + *END**************************************************************************/ +osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle) +{ + assert(NULL != mutexHandle); + QueueHandle_t mutex = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle); + + if (pdFALSE == xSemaphoreGiveRecursive(mutex)) + { + return KOSA_StatusError; + } + else + { + return KOSA_StatusSuccess; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexDestroy + * Description : This function is used to destroy a mutex. + * Return : KOSA_StatusSuccess if the lock object is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle) +{ + assert(NULL != mutexHandle); + QueueHandle_t mutex = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle); + + vSemaphoreDelete(mutex); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventCreate + * Description : This function is used to create a event object. + * Return : Event handle of the new event, or NULL if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear) +{ + assert(NULL != eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + pEventStruct->handle = xEventGroupCreate(); + if (NULL != pEventStruct->handle) + { + pEventStruct->autoClear = autoClear; + } + else + { + return KOSA_StatusError; + } + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventSet + * Description : Set one or more event flags of an event object. + * Return : KOSA_StatusSuccess if set successfully, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet) +{ + portBASE_TYPE taskToWake = pdFALSE; + BaseType_t result; + assert(NULL != eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + if (NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + if (0U != __get_IPSR()) + { +#if (configUSE_TRACE_FACILITY == 1) + result = xEventGroupSetBitsFromISR(pEventStruct->handle, (event_flags_t)flagsToSet, &taskToWake); +#else + result = xEventGroupSetBitsFromISR((void *)pEventStruct->handle, (event_flags_t)flagsToSet, &taskToWake); +#endif + assert(pdPASS == result); + (void)result; + portYIELD_FROM_ISR((taskToWake)); + } + else + { + (void)xEventGroupSetBits(pEventStruct->handle, (event_flags_t)flagsToSet); + } + + (void)result; + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventClear + * Description : Clear one or more event flags of an event object. + * Return :KOSA_StatusSuccess if clear successfully, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear) +{ + assert(NULL != eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + if (NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + + if (0U != __get_IPSR()) + { +#if (configUSE_TRACE_FACILITY == 1) + (void)xEventGroupClearBitsFromISR(pEventStruct->handle, (event_flags_t)flagsToClear); +#else + (void)xEventGroupClearBitsFromISR((void *)pEventStruct->handle, (event_flags_t)flagsToClear); +#endif + } + else + { + (void)xEventGroupClearBits(pEventStruct->handle, (event_flags_t)flagsToClear); + } + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventGet + * Description : This function is used to get event's flags that specified by prameter + * flagsMask, and the flags (user specified) are obatianed by parameter pFlagsOfEvent. So + * you should pass the parameter 0xffffffff to specify you want to check all. + * Return :KOSA_StatusSuccess if event flags were successfully got, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, osa_event_flags_t flagsMask, osa_event_flags_t *pFlagsOfEvent) +{ + assert(NULL != eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + EventBits_t eventFlags; + + if (NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + + if (NULL == pFlagsOfEvent) + { + return KOSA_StatusError; + } + + if (0U != __get_IPSR()) + { + eventFlags = xEventGroupGetBitsFromISR(pEventStruct->handle); + } + else + { + eventFlags = xEventGroupGetBits(pEventStruct->handle); + } + + *pFlagsOfEvent = (osa_event_flags_t)eventFlags & flagsMask; + + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventWait + * Description : This function checks the event's status, if it meets the wait + * condition, return KOSA_StatusSuccess, otherwise, timeout will be used for + * wait. The parameter timeout indicates how long should wait in milliseconds. + * Pass osaWaitForever_c to wait indefinitely, pass 0 will return the value + * KOSA_StatusTimeout immediately if wait condition is not met. The event flags + * will be cleared if the event is auto clear mode. Flags that wakeup waiting + * task could be obtained from the parameter setFlags. + * This function returns KOSA_StatusSuccess if wait condition is met, returns + * KOSA_StatusTimeout if wait condition is not met within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_EventWait(osa_event_handle_t eventHandle, + osa_event_flags_t flagsToWait, + uint8_t waitAll, + uint32_t millisec, + osa_event_flags_t *pSetFlags) +{ + assert(NULL != eventHandle); + BaseType_t clearMode; + uint32_t timeoutTicks; + event_flags_t flagsSave; + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + /* Clean FreeRTOS cotrol flags */ + flagsToWait = flagsToWait & 0x00FFFFFFU; + if (NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + + /* Convert timeout from millisecond to tick. */ + if (millisec == osaWaitForever_c) + { + timeoutTicks = portMAX_DELAY; + } + else + { + timeoutTicks = millisec / portTICK_PERIOD_MS; + } + + clearMode = (pEventStruct->autoClear != 0U) ? pdTRUE : pdFALSE; + + flagsSave = xEventGroupWaitBits(pEventStruct->handle, (event_flags_t)flagsToWait, clearMode, (BaseType_t)waitAll, + timeoutTicks); + + flagsSave &= (event_flags_t)flagsToWait; + if (NULL != pSetFlags) + { + *pSetFlags = (osa_event_flags_t)flagsSave; + } + + if (0U != flagsSave) + { + return KOSA_StatusSuccess; + } + else + { + return KOSA_StatusTimeout; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventDestroy + * Description : This function is used to destroy a event object. Return + * KOSA_StatusSuccess if the event object is destroyed successfully, otherwise + * return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle) +{ + assert(NULL != eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + if (NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + vEventGroupDelete(pEventStruct->handle); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQCreate + * Description : This function is used to create a message queue. + * Return : the handle to the message queue if create successfully, otherwise + * return NULL. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize) +{ + assert(sizeof(osa_msgq_handle_t) == OSA_MSGQ_HANDLE_SIZE); + assert(NULL != msgqHandle); + + union + { + QueueHandle_t msgq; + uint32_t pmsgqHandle; + } xMsgqHandle; + + /* Create the message queue where the number and size is specified by msgNo and msgSize */ + xMsgqHandle.msgq = xQueueCreate(msgNo, msgSize); + if (NULL != xMsgqHandle.msgq) + { + *(uint32_t *)msgqHandle = xMsgqHandle.pmsgqHandle; + return KOSA_StatusSuccess; + } + return KOSA_StatusError; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQPut + * Description : This function is used to put a message to a message queue. + * Return : KOSA_StatusSuccess if the message is put successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage) +{ + osa_status_t osaStatus; + assert(NULL != msgqHandle); + portBASE_TYPE taskToWake = pdFALSE; + QueueHandle_t handler = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle); + + if (0U != __get_IPSR()) + { + if (pdTRUE == xQueueSendToBackFromISR(handler, pMessage, &taskToWake)) + { + portYIELD_FROM_ISR((taskToWake)); + osaStatus = KOSA_StatusSuccess; + } + else + { + osaStatus = KOSA_StatusError; + } + } + else + { + osaStatus = (xQueueSendToBack(handler, pMessage, 0) == pdPASS) ? (KOSA_StatusSuccess) : (KOSA_StatusError); + } + + return osaStatus; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQGet + * Description : This function checks the queue's status, if it is not empty, + * get message from it and return KOSA_StatusSuccess, otherwise, timeout will + * be used for wait. The parameter timeout indicates how long should wait in + * milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will return + * KOSA_StatusTimeout immediately if queue is empty. + * This function returns KOSA_StatusSuccess if message is got successfully, + * returns KOSA_StatusTimeout if message queue is empty within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec) +{ + osa_status_t osaStatus; + assert(NULL != msgqHandle); + QueueHandle_t handler = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle); + + uint32_t timeoutTicks; + + if (millisec == osaWaitForever_c) + { + timeoutTicks = portMAX_DELAY; + } + else + { + timeoutTicks = MSEC_TO_TICK(millisec); + } + if (pdPASS != xQueueReceive(handler, pMessage, timeoutTicks)) + { + osaStatus = KOSA_StatusTimeout; /* not able to send it to the queue? */ + } + else + { + osaStatus = KOSA_StatusSuccess; + } + return osaStatus; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQAvailableMsgs + * Description : This function is used to get the available message. + * Return : Available message count + * + *END**************************************************************************/ +int OSA_MsgQAvailableMsgs(osa_msgq_handle_t msgqHandle) +{ + QueueHandle_t handler; + assert(NULL != msgqHandle); + handler = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle); + return (int)uxQueueMessagesWaiting((QueueHandle_t)handler); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQDestroy + * Description : This function is used to destroy the message queue. + * Return : KOSA_StatusSuccess if the message queue is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle) +{ + assert(NULL != msgqHandle); + QueueHandle_t handler = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle); + + vQueueDelete(handler); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptEnable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptEnable(void) +{ + if (0U != __get_IPSR()) + { + if (1 == s_osaState.basePriorityNesting) + { + portCLEAR_INTERRUPT_MASK_FROM_ISR(s_osaState.basePriority); + } + + if (s_osaState.basePriorityNesting > 0) + { + s_osaState.basePriorityNesting--; + } + } + else + { + portEXIT_CRITICAL(); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptDisable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptDisable(void) +{ + if (0U != __get_IPSR()) + { + if (0 == s_osaState.basePriorityNesting) + { + s_osaState.basePriority = portSET_INTERRUPT_MASK_FROM_ISR(); + } + s_osaState.basePriorityNesting++; + } + else + { + portENTER_CRITICAL(); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EnableIRQGlobal + * Description : enable interrupts using PRIMASK register. + * + *END**************************************************************************/ +void OSA_EnableIRQGlobal(void) +{ + if (s_osaState.interruptDisableCount > 0U) + { + s_osaState.interruptDisableCount--; + + if (0U == s_osaState.interruptDisableCount) + { + __enable_irq(); + } + /* call core API to enable the global interrupt*/ + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_DisableIRQGlobal + * Description : disable interrupts using PRIMASK register. + * + *END**************************************************************************/ +void OSA_DisableIRQGlobal(void) +{ + /* call core API to disable the global interrupt*/ + __disable_irq(); + + /* update counter*/ + s_osaState.interruptDisableCount++; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InstallIntHandler + * Description : This function is used to install interrupt handler. + * + *END**************************************************************************/ +void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void)) +{ +#if defined(__IAR_SYSTEMS_ICC__) + _Pragma("diag_suppress = Pm138") +#endif +#if defined(ENABLE_RAM_VECTOR_TABLE) + (void) InstallIRQHandler((IRQn_Type)IRQNumber, (uint32_t) * (uint32_t *)&handler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#if defined(__IAR_SYSTEMS_ICC__) + _Pragma("diag_remark = PM138") +#endif +} + +/*!********************************************************************************* +************************************************************************************* +* Private functions +************************************************************************************* +********************************************************************************** */ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +#if (defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U)) +static OSA_TASK_DEFINE(startup_task, gMainThreadPriority_c, 1, gMainThreadStackSize_c, 0); + +int main(void) +{ + extern void BOARD_InitHardware(void); + OSA_Init(); + /* Initialize MCU clock */ + BOARD_InitHardware(); + + (void)OSA_TaskCreate((osa_task_handle_t)s_osaState.mainTaskHandle, OSA_TASK(startup_task), NULL); + + OSA_Start(); + return 0; +} +#endif /*(defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U))*/ +#endif /* FSL_OSA_TASK_ENABLE */ + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_Init + * Description : This function is used to setup the basic services, it should + * be called first in function main. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +void OSA_Init(void) +{ + LIST_Init((&s_osaState.taskList), 0); + s_osaState.basePriorityNesting = 0; + s_osaState.interruptDisableCount = 0; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_Start + * Description : This function is used to start RTOS scheduler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +void OSA_Start(void) +{ + vTaskStartScheduler(); +} +#endif diff --git a/components/osa/fsl_os_abstraction_free_rtos.h b/components/osa/fsl_os_abstraction_free_rtos.h new file mode 100644 index 000000000..00b4b6011 --- /dev/null +++ b/components/osa/fsl_os_abstraction_free_rtos.h @@ -0,0 +1,132 @@ +/*! ********************************************************************************* + * Copyright (c) 2013-2014, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * ile + * + * SPDX-License-Identifier: BSD-3-Clause + ********************************************************************************** */ +#if !defined(__FSL_OS_ABSTRACTION_FREERTOS_H__) +#define __FSL_OS_ABSTRACTION_FREERTOS_H__ + +#if defined(__IAR_SYSTEMS_ICC__) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + */ +/* http://supp.iar.com/Support/?note=24725 */ + +#define MISRAC_DISABLE \ + _Pragma( \ + "diag_suppress= \ + Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\ + Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\ + Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\ + Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\ + Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\ + Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\ + Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\ + Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\ + Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\ + Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\ + Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\ + Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\ + Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\ + Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\ + Pm155") + +#define MISRAC_ENABLE \ + _Pragma( \ + "diag_default= \ + Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\ + Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\ + Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\ + Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\ + Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\ + Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\ + Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\ + Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\ + Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\ + Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\ + Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\ + Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\ + Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\ + Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\ + Pm155") +#else +/* Empty MISRA C macros for other toolchains. */ +#define MISRAC_DISABLE +#define MISRAC_ENABLE +#endif + +MISRAC_DISABLE +#include "FreeRTOS.h" +#include "semphr.h" +#include "event_groups.h" +MISRAC_ENABLE + +/*! + * @addtogroup os_abstraction_free_rtos + * @{ + */ + +/******************************************************************************* + * Declarations + ******************************************************************************/ +/*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */ +typedef TaskHandle_t task_handler_t; + +/*! @brief Type for a task stack.*/ +typedef portSTACK_TYPE task_stack_t; + +/*! @brief Type for task parameter */ +typedef void *task_param_t; + +/*! @brief Type for an event flags object.*/ +typedef EventBits_t event_flags_t; + +/*! @brief Constant to pass as timeout value in order to wait indefinitely. */ +#define OSA_WAIT_FOREVER 0xFFFFFFFFU + +/*! @brief OSA's time range in millisecond, OSA time wraps if exceeds this value. */ +#define FSL_OSA_TIME_RANGE 0xFFFFFFFFU + +/*! @brief The default interrupt handler installed in vector table. */ +#define OSA_DEFAULT_INT_HANDLER ((osa_int_handler_t)(&DefaultISR)) + +extern void DefaultISR(void); + +/*! + * @name Thread management + * @{ + */ + +/*! + * @brief To provide unified task piority for upper layer, OSA layer makes conversion. + */ +#define PRIORITY_OSA_TO_RTOS(osa_prio) ((UBaseType_t)configMAX_PRIORITIES - (osa_prio)-2U) +#define PRIORITY_RTOS_TO_OSA(rtos_prio) ((UBaseType_t)configMAX_PRIORITIES - (rtos_prio)-2U) + +/* @}*/ + +/*! + * @name Message queues + * @{ + */ + +/*! + * @brief This macro statically reserves the memory required for the queue. + * + * @param name Identifier for the memory region. + * @param number Number of elements in the queue. + * @param size Size of every elements in words. + */ +#define MSG_QUEUE_DECLARE(name, number, size) msg_queue_t *name = NULL + +/* @}*/ + +/*! @}*/ +/*! @}*/ +/*! @}*/ + +#endif /* __FSL_OS_ABSTRACTION_FREERTOS_H__ */ diff --git a/components/osa/fsl_os_abstraction_threadx.c b/components/osa/fsl_os_abstraction_threadx.c new file mode 100644 index 000000000..ff5e36ffc --- /dev/null +++ b/components/osa/fsl_os_abstraction_threadx.c @@ -0,0 +1,973 @@ +/*! ********************************************************************************* + * Copyright 2020 NXP + * All rights reserved. + * + * + * This is the source file for the OS Abstraction layer for thread. + * + * SPDX-License-Identifier: BSD-3-Clause + ********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "fsl_common.h" +#include "fsl_os_abstraction.h" +#include "tx_api.h" +#include "tx_event_flags.h" +#include +#include "fsl_component_generic_list.h" +#include "fsl_os_abstraction_threadx.h" + +/*! ********************************************************************************* +************************************************************************************* +* Private macros +************************************************************************************* +********************************************************************************** */ + +/* Weak function. */ +#if defined(__GNUC__) +#define __WEAK_FUNC __attribute__((weak)) +#elif defined(__ICCARM__) +#define __WEAK_FUNC __weak +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define __WEAK_FUNC __attribute__((weak)) +#endif + +#define millisecToTicks(millisec) (((millisec)*configTICK_RATE_HZ + 999U) / 1000U) + +#ifdef DEBUG_ASSERT +#define OS_ASSERT(condition) \ + if (!(condition)) \ + while (1) \ + ; +#else +#define OS_ASSERT(condition) (void)(condition); +#endif + +#define configTICK_RATE_HZ ((uint32_t)1000U) + +/*! @brief Converts milliseconds to ticks*/ +#define MSEC_TO_TICK(msec) \ + (((uint32_t)(msec) + 500uL / (uint32_t)configTICK_RATE_HZ) * (uint32_t)configTICK_RATE_HZ / 1000uL) +#define TICKS_TO_MSEC(tick) ((uint32_t)((uint64_t)(tick)*1000uL / (uint64_t)configTICK_RATE_HZ)) +/************************************************************************************ +************************************************************************************* +* Private type definitions +************************************************************************************* +************************************************************************************/ +typedef struct osa_thread_task +{ + list_element_t link; + TX_THREAD taskHandle; +} osa_thread_task_t; + +typedef struct _osa_event_struct +{ + TX_EVENT_FLAGS_GROUP handle; /* The event handle */ + uint8_t autoClear; /*!< Auto clear or manual clear */ +} osa_event_struct_t; + +/*! @brief State structure for thread osa manager. */ +typedef struct _osa_state +{ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + list_label_t taskList; +#endif + uint32_t basePriority; + int32_t basePriorityNesting; + uint32_t interruptDisableCount; +} osa_state_t; + +/*! ********************************************************************************* +************************************************************************************* +* Private prototypes +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public memory declarations +************************************************************************************* +********************************************************************************** */ +const uint8_t gUseRtos_c = USE_RTOS; // USE_RTOS = 0 for BareMetal and 1 for OS + +static uint32_t s_primask; + +static osa_state_t s_osaState = {0}; +/*! ********************************************************************************* +************************************************************************************* +* Private memory declarations +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MemoryAllocate + * Description : Reserves the requested amount of memory in bytes. + * + *END**************************************************************************/ +void *OSA_MemoryAllocate(uint32_t length) +{ + return NULL; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MemoryFree + * Description : Frees the memory previously reserved. + * + *END**************************************************************************/ +void OSA_MemoryFree(void *p) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EnterCritical + * Description : Enter critical. + * + *END**************************************************************************/ +void OSA_EnterCritical(uint32_t *sr) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_ExitCritical + * Description : Exit critical. + * + *END**************************************************************************/ +void OSA_ExitCritical(uint32_t sr) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_Init + * Description : This function is used to setup the basic services, it should + * be called first in function main. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +void OSA_Init(void) +{ + LIST_Init((&s_osaState.taskList), 0); + s_osaState.basePriorityNesting = 0; + s_osaState.interruptDisableCount = 0; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_Start + * Description : This function is used to start RTOS scheduler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +void OSA_Start(void) +{ + tx_kernel_enter(); +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskGetCurrentHandle + * Description : This function is used to get current active task's handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_handle_t OSA_TaskGetCurrentHandle(void) +{ + return NULL; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskYield + * Description : When a task calls this function, it will give up CPU and put + * itself to the tail of ready list. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskYield(void) +{ + return KOSA_StatusSuccess; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskGetPriority + * Description : This function returns task's priority by task handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle) +{ + return 0U; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskSetPriority + * Description : This function sets task's priority by task handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority) +{ + return KOSA_StatusSuccess; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskCreate + * Description : This function is used to create a task and make it ready. + * Param[in] : threadDef - Definition of the thread. + * task_param - Parameter to pass to the new thread. + * Return Thread handle of the new thread, or NULL if failed. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, const osa_task_def_t *thread_def, osa_task_param_t task_param) +{ + assert(taskHandle); + osa_status_t status = KOSA_StatusError; + osa_thread_task_t *ptask = (osa_thread_task_t *)taskHandle; + + if (tx_thread_create(&ptask->taskHandle, /* task handle, allocated by application */ + (char *)thread_def->tname, /* thread name */ + (void (*)(ULONG))thread_def->pthread, /* entry function */ + (ULONG)(*(ULONG *)task_param), /* entry input */ + (void *)thread_def->tstack, /* stack start */ + (ULONG)thread_def->stacksize, /* stack size */ + PRIORITY_OSA_TO_THREAD(thread_def->tpriority), /* initial priority */ + 0U, /* preempt threshold */ + 0U, /* time slice */ + true /* auto start */ + ) == TX_SUCCESS) + { + OSA_InterruptDisable(); + (void)LIST_AddTail(&s_osaState.taskList, (list_element_handle_t) & (ptask->link)); + OSA_InterruptEnable(); + status = KOSA_StatusSuccess; + } + return status; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskDestroy + * Description : This function destroy a task. + * Param[in] :taskHandle - Thread handle. + * Return KOSA_StatusSuccess if the task is destroied, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle) +{ + assert(taskHandle); + osa_thread_task_t *ptask = (osa_thread_task_t *)taskHandle; + osa_status_t status = KOSA_StatusSuccess; + uint16_t oldPriority; + +#if 0 + /*Change priority to avoid context switches*/ + oldPriority = OSA_TaskGetPriority(OSA_TaskGetCurrentHandle()); + (void)OSA_TaskSetPriority(OSA_TaskGetCurrentHandle(), OSA_PRIORITY_REAL_TIME); + if (TX_SUCCESS != tx_thread_delete(&ptask->taskHandle)) + { + status = KOSA_StatusError; + } + (void)OSA_TaskSetPriority(OSA_TaskGetCurrentHandle(), oldPriority); + OSA_InterruptDisable(); + (void)LIST_RemoveElement(taskHandle); + OSA_InterruptEnable(); +#else + if (TX_SUCCESS != tx_thread_delete(&ptask->taskHandle)) + { + status = KOSA_StatusError; + } + (void)LIST_RemoveElement(taskHandle); +#endif + return status; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TimeDelay + * Description : This function is used to suspend the active thread for the given number of milliseconds. + * + *END**************************************************************************/ +void OSA_TimeDelay(uint32_t millisec) +{ +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TimeGetMsec + * Description : This function gets current time in milliseconds. + * + *END**************************************************************************/ +uint32_t OSA_TimeGetMsec(void) +{ + return 0U; +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreCreate + * Description : This function is used to create a semaphore. + * Return : Semaphore handle of the new semaphore, or NULL if failed. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue) +{ + assert(semaphoreHandle); + osa_status_t status = KOSA_StatusSuccess; + + if (TX_SUCCESS != tx_semaphore_create((TX_SEMAPHORE *)semaphoreHandle, NULL, initValue)) + { + status = KOSA_StatusError; + } + + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreDestroy + * Description : This function is used to destroy a semaphore. + * Return : KOSA_StatusSuccess if the semaphore is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle) +{ + assert(semaphoreHandle); + osa_status_t status = KOSA_StatusSuccess; + + if (TX_SUCCESS != tx_semaphore_delete((TX_SEMAPHORE *)semaphoreHandle)) + { + status = KOSA_StatusError; + } + + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreWait + * Description : This function checks the semaphore's counting value, if it is + * positive, decreases it and returns KOSA_StatusSuccess, otherwise, timeout + * will be used for wait. The parameter timeout indicates how long should wait + * in milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will + * return KOSA_StatusTimeout immediately if semaphore is not positive. + * This function returns KOSA_StatusSuccess if the semaphore is received, returns + * KOSA_StatusTimeout if the semaphore is not received within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec) +{ + assert(semaphoreHandle); + osa_status_t status = KOSA_StatusSuccess; + uint32_t timeoutTicks; + + /* Convert timeout from millisecond to tick. */ + if (millisec == osaWaitForever_c) + { + timeoutTicks = TX_WAIT_FOREVER; + } + else + { + timeoutTicks = MSEC_TO_TICK(millisec); + } + + if (TX_SUCCESS != tx_semaphore_get((TX_SEMAPHORE *)semaphoreHandle, timeoutTicks)) + { + status = KOSA_StatusError; + } + + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphorePost + * Description : This function is used to wake up one task that wating on the + * semaphore. If no task is waiting, increase the semaphore. The function returns + * KOSA_StatusSuccess if the semaphre is post successfully, otherwise returns + * KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle) +{ + assert(semaphoreHandle); + osa_status_t status = KOSA_StatusSuccess; + + if (TX_SUCCESS != tx_semaphore_put((TX_SEMAPHORE *)semaphoreHandle)) + { + status = KOSA_StatusError; + } + + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexCreate + * Description : This function is used to create a mutex. + * Return : KOSA_StatusSuccess if mutex is created successfully, otherwise returns + * KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle) +{ + assert(mutexHandle); + osa_status_t status = KOSA_StatusSuccess; + + if (TX_SUCCESS != tx_mutex_create((TX_MUTEX *)mutexHandle, NULL, 0U)) + { + status = KOSA_StatusError; + } + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexLock + * Description : This function checks the mutex's status, if it is unlocked, + * lock it and returns KOSA_StatusSuccess, otherwise, wait for the mutex. + * This function returns KOSA_StatusSuccess if the mutex is obtained, returns + * KOSA_StatusError if any errors occur during waiting. If the mutex has been + * locked, pass 0 as timeout will return KOSA_StatusTimeout immediately. + * + *END**************************************************************************/ +osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec) +{ + assert(mutexHandle); + uint32_t timeoutTicks; + osa_status_t status = KOSA_StatusSuccess; + + /* Convert timeout from millisecond to tick. */ + if (millisec == osaWaitForever_c) + { + timeoutTicks = TX_WAIT_FOREVER; + } + else + { + timeoutTicks = MSEC_TO_TICK(millisec); + } + + if (TX_SUCCESS != tx_mutex_get((TX_MUTEX *)mutexHandle, timeoutTicks)) + { + status = KOSA_StatusError; + } + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexUnlock + * Description : This function is used to unlock a mutex. + * + *END**************************************************************************/ +osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle) +{ + assert(mutexHandle); + osa_status_t status = KOSA_StatusSuccess; + + if (TX_SUCCESS != tx_mutex_put((TX_MUTEX *)mutexHandle)) + { + status = KOSA_StatusError; + } + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexDestroy + * Description : This function is used to destroy a mutex. + * Return : KOSA_StatusSuccess if the lock object is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle) +{ + assert(mutexHandle); + osa_status_t status = KOSA_StatusSuccess; + + if (TX_SUCCESS != tx_mutex_delete((TX_MUTEX *)mutexHandle)) + { + status = KOSA_StatusError; + } + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventCreate + * Description : This function is used to create a event object. + * Return : Event handle of the new event, or NULL if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear) +{ + assert(eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + osa_status_t status = KOSA_StatusSuccess; + + if (TX_SUCCESS == tx_event_flags_create(&pEventStruct->handle, NULL)) + { + pEventStruct->autoClear = autoClear; + } + else + { + status = KOSA_StatusError; + } + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventSet + * Description : Set one or more event flags of an event object. + * Return : KOSA_StatusSuccess if set successfully, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet) +{ + assert(eventHandle); + osa_status_t status = KOSA_StatusSuccess; + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + /*the 3rd parameter is set_option + if it's 0x2, will clear the specified flags by "ANDing" the flags into the current events of the group. + if it's other value, will set the flags by "or" logic*/ + if (TX_SUCCESS != tx_event_flags_set(&pEventStruct->handle, flagsToSet, 0U)) + { + status = KOSA_StatusError; + } + + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventClear + * Description : Clear one or more event flags of an event object. + * Return :KOSA_StatusSuccess if clear successfully, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear) +{ + assert(eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + pEventStruct->handle.tx_event_flags_group_current &= ~flagsToClear; + + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventGet + * Description : This function is used to get event's flags that specified by prameter + * flagsMask, and the flags (user specified) are obatianed by parameter pFlagsOfEvent. So + * you should pass the parameter 0xffffffff to specify you want to check all. + * Return :KOSA_StatusSuccess if event flags were successfully got, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, osa_event_flags_t flagsMask, osa_event_flags_t *pFlagsOfEvent) +{ + assert(eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + osa_status_t status = KOSA_StatusSuccess; + + if (NULL == pFlagsOfEvent) + { + status = KOSA_StatusError; + } + else + { + *pFlagsOfEvent = pEventStruct->handle.tx_event_flags_group_current & flagsMask; + } + + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventWait + * Description : This function checks the event's status, if it meets the wait + * condition, return KOSA_StatusSuccess, otherwise, timeout will be used for + * wait. The parameter timeout indicates how long should wait in milliseconds. + * Pass osaWaitForever_c to wait indefinitely, pass 0 will return the value + * KOSA_StatusTimeout immediately if wait condition is not met. The event flags + * will be cleared if the event is auto clear mode. Flags that wakeup waiting + * task could be obtained from the parameter setFlags. + * This function returns KOSA_StatusSuccess if wait condition is met, returns + * KOSA_StatusTimeout if wait condition is not met within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_EventWait(osa_event_handle_t eventHandle, + osa_event_flags_t flagsToWait, + uint8_t waitAll, + uint32_t millisec, + osa_event_flags_t *pSetFlags) +{ + assert(eventHandle); + uint32_t timeoutTicks; + osa_event_flags_t flagsSave; + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + /* Clean FreeRTOS cotrol flags */ + flagsToWait = flagsToWait & 0x00FFFFFFU; + + /* Convert timeout from millisecond to tick. */ + if (millisec == osaWaitForever_c) + { + timeoutTicks = TX_WAIT_FOREVER; + } + else + { + timeoutTicks = MSEC_TO_TICK(millisec); + } + + if (pEventStruct->autoClear != 0U) + { + if (TX_SUCCESS != tx_event_flags_get(&pEventStruct->handle, flagsToWait, TX_EVENT_FLAGS_CLEAR_MASK, + (ULONG *)&flagsSave, timeoutTicks)) + { + return KOSA_StatusError; + } + } + else + { + if (TX_SUCCESS != tx_event_flags_get(&pEventStruct->handle, flagsToWait, 0U, (ULONG *)&flagsSave, timeoutTicks)) + { + return KOSA_StatusError; + } + } + + flagsSave &= (osa_event_flags_t)flagsToWait; + if (NULL != pSetFlags) + { + *pSetFlags = (osa_event_flags_t)flagsSave; + } + + if (0U != flagsSave) + { + return KOSA_StatusSuccess; + } + else + { + return KOSA_StatusTimeout; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventDestroy + * Description : This function is used to destroy a event object. Return + * KOSA_StatusSuccess if the event object is destroyed successfully, otherwise + * return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle) +{ + assert(eventHandle); + osa_status_t status = KOSA_StatusSuccess; + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + if (TX_SUCCESS != tx_event_flags_delete(&pEventStruct->handle)) + { + status = KOSA_StatusError; + } + + return status; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQCreate + * Description : This function is used to create a message queue. + * Return : the handle to the message queue if create successfully, otherwise + * return NULL. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize) +{ +#if 0 + assert(sizeof(osa_msgq_handle_t) == OSA_MSGQ_HANDLE_SIZE); + assert(msgqHandle); + + union + { + QueueHandle_t msgq; + uint32_t pmsgqHandle; + } xMsgqHandle; + + /* Create the message queue where the number and size is specified by msgNo and msgSize */ + xMsgqHandle.msgq = xQueueCreate(msgNo, msgSize); + if (NULL != xMsgqHandle.msgq) + { + *(uint32_t *)msgqHandle = xMsgqHandle.pmsgqHandle; + return KOSA_StatusSuccess; + } +#endif + return KOSA_StatusError; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQPut + * Description : This function is used to put a message to a message queue. + * Return : KOSA_StatusSuccess if the message is put successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage) +{ +#if 0 + osa_status_t osaStatus; + assert(msgqHandle); + portBASE_TYPE taskToWake = pdFALSE; + QueueHandle_t handler = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle); + + if (0U != __get_IPSR()) + { + if (pdTRUE == xQueueSendToBackFromISR(handler, pMessage, &taskToWake)) + { + portYIELD_FROM_ISR((taskToWake)); + osaStatus = KOSA_StatusSuccess; + } + else + { + osaStatus = KOSA_StatusError; + } + } + else + { + osaStatus = (xQueueSendToBack(handler, pMessage, 0) == pdPASS) ? (KOSA_StatusSuccess) : (KOSA_StatusError); + } + return osaStatus; +#endif + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQGet + * Description : This function checks the queue's status, if it is not empty, + * get message from it and return KOSA_StatusSuccess, otherwise, timeout will + * be used for wait. The parameter timeout indicates how long should wait in + * milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will return + * KOSA_StatusTimeout immediately if queue is empty. + * This function returns KOSA_StatusSuccess if message is got successfully, + * returns KOSA_StatusTimeout if message queue is empty within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec) +{ +#if 0 + osa_status_t osaStatus; + assert(msgqHandle); + QueueHandle_t handler = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle); + + uint32_t timeoutTicks; + + if (millisec == osaWaitForever_c) + { + timeoutTicks = TX_WAIT_FOREVER; + } + else + { + timeoutTicks = MSEC_TO_TICK(millisec); + } + if (pdPASS != xQueueReceive(handler, pMessage, timeoutTicks)) + { + osaStatus = KOSA_StatusTimeout; /* not able to send it to the queue? */ + } + else + { + osaStatus = KOSA_StatusSuccess; + } + return osaStatus; +#endif + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQDestroy + * Description : This function is used to destroy the message queue. + * Return : KOSA_StatusSuccess if the message queue is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle) +{ +#if 0 + assert(msgqHandle); + QueueHandle_t handler = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle); + + vQueueDelete(handler); +#endif + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptEnable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptEnable(void) +{ +#if 0 + if (0U != __get_IPSR()) + { + if (1 == s_osaState.basePriorityNesting) + { + portCLEAR_INTERRUPT_MASK_FROM_ISR(s_osaState.basePriority); + } + + if (s_osaState.basePriorityNesting > 0) + { + s_osaState.basePriorityNesting--; + } + } + else + { + portEXIT_CRITICAL(); + } +#endif +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptDisable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptDisable(void) +{ +#if 0 + if (0U != __get_IPSR()) + { + if (0 == s_osaState.basePriorityNesting) + { + s_osaState.basePriority = portSET_INTERRUPT_MASK_FROM_ISR(); + } + s_osaState.basePriorityNesting++; + } + else + { + portENTER_CRITICAL(); + } +#endif +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EnableIRQGlobal + * Description : enable interrupts using PRIMASK register. + * + *END**************************************************************************/ +void OSA_EnableIRQGlobal(void) +{ + EnableGlobalIRQ(s_primask); +#if 0 + if (s_osaState.interruptDisableCount > 0U) + { + s_osaState.interruptDisableCount--; + + if (0U == s_osaState.interruptDisableCount) + { + __enable_irq(); + } + /* call core API to enable the global interrupt*/ + } +#endif +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_DisableIRQGlobal + * Description : disable interrupts using PRIMASK register. + * + *END**************************************************************************/ +void OSA_DisableIRQGlobal(void) +{ +#if 0 + /* call core API to disable the global interrupt*/ + __disable_irq(); + + /* update counter*/ + s_osaState.interruptDisableCount++; +#endif + s_primask = DisableGlobalIRQ(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InstallIntHandler + * Description : This function is used to install interrupt handler. + * + *END**************************************************************************/ +void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void)) +{ +#if defined(__IAR_SYSTEMS_ICC__) + _Pragma("diag_suppress = Pm138") +#endif +#if defined(ENABLE_RAM_VECTOR_TABLE) + (void) InstallIRQHandler((IRQn_Type)IRQNumber, (uint32_t) * (uint32_t *)&handler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#if defined(__IAR_SYSTEMS_ICC__) + _Pragma("diag_remark = PM138") +#endif +} + +/*!********************************************************************************* +************************************************************************************* +* Private functions +************************************************************************************* +********************************************************************************** */ +#if 0 +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +#if (defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U)) +/*task buffer: list_element_t + TCB*/ +static uint32_t + s_startupTaskHandle[(sizeof(TX_THREAD) + sizeof(list_element_t) + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]; + +OSA_TASK_DEFINE(startup_task, gMainThreadPriority_c, 1, gMainThreadStackSize_c, 0); + +int main(void) +{ + extern void BOARD_InitHardware(void); + + OSA_Init(); + /* Initialize MCU clock */ + BOARD_InitHardware(); + + (void)OSA_TaskCreate((osa_task_handle_t)s_startupTaskHandle, OSA_TASK(startup_task), NULL); + + OSA_Start(); + + return 0; +} +#endif /*(defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U))*/ +#endif /* FSL_OSA_TASK_ENABLE */ +#endif diff --git a/components/osa/fsl_os_abstraction_threadx.h b/components/osa/fsl_os_abstraction_threadx.h new file mode 100644 index 000000000..3876f751c --- /dev/null +++ b/components/osa/fsl_os_abstraction_threadx.h @@ -0,0 +1,41 @@ +/*! ********************************************************************************* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + ********************************************************************************** */ +#if !defined(__FSL_OS_ABSTRACTION_THREADX_H__) +#define __FSL_OS_ABSTRACTION_THREADX_H__ + +#include "tx_api.h" +#include "fsl_component_generic_list.h" + +/*! + * @addtogroup os_abstraction_thread + * @{ + */ + +/******************************************************************************* + * Declarations + ******************************************************************************/ +/*! @brief OSA task handle size. */ +#define OSA_TASK_HANDLE_SIZE (sizeof(TX_THREAD) + sizeof(list_element_t)) + +/*! @brief OSA event handle size. */ +#define OSA_EVENT_HANDLE_SIZE (sizeof(TX_EVENT_FLAGS_GROUP) + sizeof(uint8_t)) + +/*! @brief OSA semaphore handle size. */ +#define OSA_SEM_HANDLE_SIZE sizeof(TX_SEMAPHORE) + +/*! @brief OSA mutex handle size. */ +#define OSA_MUTEX_HANDLE_SIZE sizeof(TX_MUTEX) + +#define configMAX_PRIORITIES 32U + +/*! + * @brief To provide unified task priority for upper layer, OSA layer makes conversion. + */ +#define PRIORITY_OSA_TO_THREAD(osa_prio) ((UINT)configMAX_PRIORITIES - (osa_prio)-2U) +#define PRIORITY_THREAD_TO_OSA(thread_prio) ((UINT)configMAX_PRIORITIES - (thread_prio)-2U) + +#endif /* __FSL_OS_ABSTRACTION_THREADX_H__ */ diff --git a/components/panic/fsl_component_panic.c b/components/panic/fsl_component_panic.c new file mode 100644 index 000000000..a8fe45586 --- /dev/null +++ b/components/panic/fsl_component_panic.c @@ -0,0 +1,87 @@ +/*! + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * + * ile + * + * This is the source file for the Panic module. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "fsl_common.h" +#include "fsl_component_panic.h" +#if (defined(PANIC_ENABLE_LOG) && (PANIC_ENABLE_LOG > 0U)) +#include "fsl_debug_console.h" +#endif + +/*! ********************************************************************************* +************************************************************************************* +* Private memory declarations +************************************************************************************* +********************************************************************************** */ +#if (defined(PANIC_ENABLE_LOG) && (PANIC_ENABLE_LOG > 0U)) +static panic_data_t panic_data; +#endif +/*! ********************************************************************************* +************************************************************************************* +* Private macros +************************************************************************************* +********************************************************************************** */ +#if defined(__IAR_SYSTEMS_ICC__) +/* __get_LR() declaration not included to avoid issues with different versions of IAR compiler */ +#elif defined(__GNUC__) +#define __get_LR() __builtin_return_address(0) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#if (__ARMCC_VERSION >= 6010050) +#define __get_LR() __builtin_return_address(0) +#else +#define __get_LR() __return_address() +#endif +#endif +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* + * \brief This function will halt the system + * + * \param[in] id Description of the param2 in parameter + * \param[in] location address where the Panic occurred + * \param[in] extra1 parameter to be stored in Panic structure + * \param[in] extra2 parameter to be stored in Panic structure + * + ********************************************************************************** */ + +void panic(panic_id_t id, uint32_t location, uint32_t extra1, uint32_t extra2) +{ +#if (defined(PANIC_ENABLE_LOG) && (PANIC_ENABLE_LOG > 0U)) + panic_data.id = id; + panic_data.location = location; + panic_data.extra1 = extra1; + panic_data.extra2 = extra2; + panic_data.linkRegister = (uint32_t)((uint32_t *)__get_LR()); + panic_data.cpsr_contents = 0; + + (void)PRINTF("System Panic happen: \r\n"); + (void)PRINTF("Panic id: 0x%x \r\n", id); + (void)PRINTF("Panic location: 0x%x \r\n", location); + (void)PRINTF("Panic extra1: 0x%x \r\n", extra1); + (void)PRINTF("Panic extra2: 0x%x \r\n", extra2); + (void)PRINTF("Panic linkRegister: 0x%x \r\n", panic_data.linkRegister); +#endif + + (void)DisableGlobalIRQ(); /* disable interrupts */ + + /* infinite loop just to ensure this routine never returns */ + for (;;) + { + } +} diff --git a/components/panic/fsl_component_panic.h b/components/panic/fsl_component_panic.h new file mode 100644 index 000000000..4979122a5 --- /dev/null +++ b/components/panic/fsl_component_panic.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * + * + * This is the header file for the Panic module. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PANIC_H__ +#define __PANIC_H__ + +#include "fsl_common.h" +/*! + * @addtogroup Panic + * @{ + */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public type definitions +************************************************************************************* +********************************************************************************** */ + +/**@brief panic id. */ +typedef uint32_t panic_id_t; + +/**@brief panic data structure. */ +typedef struct _panic_data +{ + panic_id_t id; /* Panic ID */ + uint32_t location; /* location address where the Panic occurred */ + uint32_t extra1; /* extra1 */ + uint32_t extra2; /* extra2 */ + uint32_t linkRegister; /* Link register */ + uint32_t cpsr_contents; /* cpsr_contents*/ + uint8_t stack_dump[4]; /* initially just contain the contents of the LR */ +} panic_data_t; + +/*! ********************************************************************************* +************************************************************************************* +* Public macros +************************************************************************************* +********************************************************************************** */ +#ifndef PANIC_ENABLE_LOG +#define PANIC_ENABLE_LOG (0) +#endif + +#define ID_PANIC(grp, value) ((panic_id_t)(((panic_id_t)(grp) << 16) + ((panic_id_t)(value)))) + +/*! ********************************************************************************* +************************************************************************************* +* Public prototypes +************************************************************************************* +********************************************************************************** */ + +/*! + * @brief Panic function. + * + * + * @param id Panic ID + * @param location location address where the Panic occurred + * @param extra1 extra1 parameter to be stored in Panic structure. + * @param extra2 extra2 parameter to be stored in Panic structure + * @retval No return vaule. + */ +void panic(panic_id_t id, uint32_t location, uint32_t extra1, uint32_t extra2); +/*! @}*/ +#endif /* __PANIC_H__ */ diff --git a/components/rng/fsl_adapter_rng.h b/components/rng/fsl_adapter_rng.h new file mode 100644 index 000000000..667007f81 --- /dev/null +++ b/components/rng/fsl_adapter_rng.h @@ -0,0 +1,102 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HAL_RNG_H_ +#define _HAL_RNG_H_ + +#include "fsl_common.h" +/*! + * @addtogroup RNG_Adapter + * @{ + */ + +/************************************************************************************ +************************************************************************************* +* Include +************************************************************************************* +***********************************************************************************/ + +/************************************************************************************ +************************************************************************************* +* Public types +************************************************************************************* +************************************************************************************/ + +/*! @brief Hal rand status. */ +typedef enum _hal_rng_status +{ + kStatus_HAL_RngSuccess = kStatus_Success, /*!< Success */ + KStatus_HAL_RngNotSupport = MAKE_STATUS(kStatusGroup_HAL_RNG, 1), /*!instance], kGPT_OutputCompare1Flag); + if (halTimerState->callback != NULL) + { + halTimerState->callback(halTimerState->callbackParam); + } +} + +void GPT0_IRQHandler(void); +void GPT0_IRQHandler(void) +{ + HAL_TimerInterruptHandle(0); + SDK_ISR_EXIT_BARRIER; +} + +void GPT1_IRQHandler(void); +void GPT1_IRQHandler(void) +{ + HAL_TimerInterruptHandle(1); + SDK_ISR_EXIT_BARRIER; +} +void GPT2_IRQHandler(void); +void GPT2_IRQHandler(void) +{ + HAL_TimerInterruptHandle(2); + SDK_ISR_EXIT_BARRIER; +} +/************************************************************************************ +************************************************************************************* +* Public functions +************************************************************************************* +************************************************************************************/ +hal_timer_status_t HAL_TimerInit(hal_timer_handle_t halTimerHandle, hal_timer_config_t *halTimerConfig) +{ + IRQn_Type instanceIrq[] = GPT_IRQS; + IRQn_Type irqId; + hal_timer_handle_struct_t *halTimerState = halTimerHandle; + /* Structure of initialize GPT */ + gpt_config_t gptConfig; + + assert(sizeof(hal_timer_handle_struct_t) == HAL_TIMER_HANDLE_SIZE); + assert(halTimerConfig); + assert(halTimerHandle); + assert(halTimerConfig->instance < (sizeof(s_GptBase) / sizeof(GPT_Type *))); + + halTimerState->timeout = halTimerConfig->timeout; + halTimerState->instance = halTimerConfig->instance; + halTimerState->timerClock_Hz = halTimerConfig->srcClock_Hz; + irqId = instanceIrq[halTimerState->instance]; + GPT_GetDefaultConfig(&gptConfig); + + /* Initialize GPT module */ + GPT_Init(s_GptBase[halTimerState->instance], &gptConfig); + /* Set both GPT modules to 1 second duration */ + GPT_SetOutputCompareValue(s_GptBase[halTimerState->instance], kGPT_OutputCompare_Channel1, + (uint32_t)USEC_TO_COUNT(halTimerState->timeout, halTimerState->timerClock_Hz)); + /* Enable GPT Output Compare1 interrupt */ + GPT_EnableInterrupts(s_GptBase[halTimerState->instance], (uint32_t)kGPT_OutputCompare1InterruptEnable); + + s_timerHandle[halTimerState->instance] = halTimerHandle; + NVIC_SetPriority((IRQn_Type)irqId, HAL_TIMER_ISR_PRIORITY); + (void)EnableIRQ(irqId); + return kStatus_HAL_TimerSuccess; +} + +/*************************************************************************************/ +void HAL_TimerDeinit(hal_timer_handle_t halTimerHandle) +{ + assert(halTimerHandle); + hal_timer_handle_struct_t *halTimerState = halTimerHandle; + s_timerHandle[halTimerState->instance] = NULL; + GPT_Deinit(s_GptBase[halTimerState->instance]); +} + +/*************************************************************************************/ +void HAL_TimerEnable(hal_timer_handle_t halTimerHandle) +{ + assert(halTimerHandle); + hal_timer_handle_struct_t *halTimerState = halTimerHandle; + GPT_StartTimer(s_GptBase[halTimerState->instance]); +} + +/*************************************************************************************/ +void HAL_TimerDisable(hal_timer_handle_t halTimerHandle) +{ + assert(halTimerHandle); + hal_timer_handle_struct_t *halTimerState = halTimerHandle; + GPT_StopTimer(s_GptBase[halTimerState->instance]); +} + +/*************************************************************************************/ +void HAL_TimerInstallCallback(hal_timer_handle_t halTimerHandle, hal_timer_callback_t callback, void *callbackParam) +{ + assert(halTimerHandle); + hal_timer_handle_struct_t *halTimerState = halTimerHandle; + halTimerState->callback = callback; + halTimerState->callbackParam = callbackParam; +} + +uint32_t HAL_TimerGetMaxTimeout(hal_timer_handle_t halTimerHandle) +{ + uint32_t reserveCount; + assert(halTimerHandle); + hal_timer_handle_struct_t *halTimerState = halTimerHandle; + reserveCount = (uint32_t)MSEC_TO_COUNT((4), (halTimerState->timerClock_Hz)); + if (reserveCount < MSEC_TO_COUNT((1), (halTimerState->timerClock_Hz))) + { + return 1000; + } + return (uint32_t)COUNT_TO_USEC(((uint64_t)0xFFFFUL - (uint64_t)reserveCount), halTimerState->timerClock_Hz); +} +/* return micro us */ +uint32_t HAL_TimerGetCurrentTimerCount(hal_timer_handle_t halTimerHandle) +{ + assert(halTimerHandle); + hal_timer_handle_struct_t *halTimerState = halTimerHandle; + return (uint32_t)COUNT_TO_USEC((uint64_t)GPT_GetCurrentTimerCount(s_GptBase[halTimerState->instance]), + halTimerState->timerClock_Hz); +} + +hal_timer_status_t HAL_TimerUpdateTimeout(hal_timer_handle_t halTimerHandle, uint32_t timeout) +{ + uint32_t tickCount; + assert(halTimerHandle); + hal_timer_handle_struct_t *halTimerState = halTimerHandle; + halTimerState->timeout = timeout; + tickCount = (uint32_t)USEC_TO_COUNT(halTimerState->timeout, halTimerState->timerClock_Hz); + if ((tickCount < 1U) || (tickCount > 0xfff0U)) + { + return kStatus_HAL_TimerOutOfRanger; + } + GPT_SetOutputCompareValue(s_GptBase[halTimerState->instance], kGPT_OutputCompare_Channel1, tickCount); + return kStatus_HAL_TimerSuccess; +} + +void HAL_TimerExitLowpower(hal_timer_handle_t halTimerHandle) +{ + assert(halTimerHandle); +} + +void HAL_TimerEnterLowpower(hal_timer_handle_t halTimerHandle) +{ + assert(halTimerHandle); +} diff --git a/components/timer/fsl_adapter_timer.h b/components/timer/fsl_adapter_timer.h new file mode 100644 index 000000000..c904e69e1 --- /dev/null +++ b/components/timer/fsl_adapter_timer.h @@ -0,0 +1,255 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _TIMER_H_ +#define _TIMER_H_ + +#include "fsl_common.h" +/*! + * @addtogroup Timer_Adapter + * @{ + */ + +/*! + * @brief The timer adapter component + * + * The timer adapter is built based on the timer SDK driver provided by the NXP + * MCUXpresso SDK. The timer adapter could provide high accuracy timer for user. + * Since callback function would be handled in ISR, and timer clock use high + * accuracy clock, user can get accuracy millisecond timer. + * + * The timer adapter would be used with different HW timer modules like FTM, PIT, LPTMR. + * But at the same time, only one HW timer module could be used. On different platforms, different + * HW timer module would be used. For the platforms which have multiple HW timer modules, + * one HW timer module would be selected as the default, but it is easy to change the default + * HW timer module to another. Just two steps to switch the HW timer module: + * 1.Remove the default HW timer module source file from the project + * 2.Add the expected HW timer module source file to the project. + * For example, in platform FRDM-K64F, there are two HW timer modules available, FTM and PIT. + * FTM is used as the default HW timer, so ftm_adapter.c and timer.h is included in the project by + * default. If PIT is expected to be used as the HW timer, ftm_adapter.c need to be removed from the + * project and pit_adapter.c should be included in the project + */ + +/************************************************************************************ +************************************************************************************* +* Include +************************************************************************************* +***********************************************************************************/ + +#if defined(SDK_OS_FREE_RTOS) +#include "FreeRTOS.h" +#endif + +/************************************************************************************ +************************************************************************************* +* Public types +************************************************************************************* +************************************************************************************/ +/*! @brief HAL timer callback function. */ +typedef void (*hal_timer_callback_t)(void* param); + +/*! @brief HAL timer status. */ +typedef enum _hal_timer_status +{ + kStatus_HAL_TimerSuccess = kStatus_Success, /*!< Success */ + kStatus_HAL_TimerNotSupport = MAKE_STATUS(kStatusGroup_HAL_TIMER, 1), /*!< Not Support */ + kStatus_HAL_TimerIsUsed = MAKE_STATUS(kStatusGroup_HAL_TIMER, 2), /*!< timer is used */ + kStatus_HAL_TimerInvalid = MAKE_STATUS(kStatusGroup_HAL_TIMER, 3), /*!< timer is invalid */ + kStatus_HAL_TimerOutOfRanger = MAKE_STATUS(kStatusGroup_HAL_TIMER, 4), /*!< timer is Out Of Ranger */ +} hal_timer_status_t; + +/*! @brief HAL timer configuration structure for HAL timer setting. */ +typedef struct _hal_timer_config +{ + uint32_t timeout; /*!< Timeout of the timer, should use microseconds, for example: if set timeout to 1000, mean 1000 microseconds + interval would generate timer timeout interrupt*/ + uint32_t srcClock_Hz; /*!< Source clock of the timer */ + uint8_t instance; /*!< Hardware timer module instance, for example: if you want use FTM0,then the instance is configured to 0, if + you want use FTM2 hardware timer, then configure the instance to 2, detail information please refer to the + SOC corresponding RM.Invalid instance value will cause initialization failure. */ +#if (defined(TM_ENABLE_TIMER_CLOCK_SELECT) && (TM_ENABLE_TIMER_CLOCK_SELECT > 0U)) + uint8_t clockSrcSelect; /*!< Select clock source. It is just for lptmr timer clock select, if the lptmr does not + want to use the default clock source*/ +#endif +} hal_timer_config_t; + +/*! @brief Definition of timer adapter handle size. */ +#define HAL_TIMER_HANDLE_SIZE (20U) + +/*! + * @brief Defines the timer handle + * + * This macro is used to define a 4 byte aligned timer handle. + * Then use "(hal_timer_handle_t)name" to get the timer handle. + * + * The macro should be global and could be optional. You could also define timer handle by yourself. + * + * This is an example, + * @code + * TIMER_HANDLE_DEFINE(timerHandle); + * @endcode + * + * @param name The name string of the timer handle. + */ +#define TIMER_HANDLE_DEFINE(name) uint32_t name[((HAL_TIMER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] + +/*! @brief HAL timer handle. */ +typedef void* hal_timer_handle_t; + +#if defined(__GIC_PRIO_BITS) +#ifndef HAL_TIMER_ISR_PRIORITY +#define HAL_TIMER_ISR_PRIORITY (25U) +#endif +#else +#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) +#ifndef HAL_TIMER_ISR_PRIORITY +#define HAL_TIMER_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) +#endif +#else +/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc. + * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum + * priority is 3 (2^2 - 1). So, the default value is 3. + */ +#ifndef HAL_TIMER_ISR_PRIORITY +#define HAL_TIMER_ISR_PRIORITY (3U) +#endif +#endif +#endif + +/************************************************************************************ +************************************************************************************* +* Public prototypes +************************************************************************************* +************************************************************************************/ +#if defined(__cplusplus) + extern "C" { +#endif /* _cplusplus */ + +/*! + * @brief Initializes the timer adapter module for a timer basic operation. + * + * @note This API should be called at the beginning of the application using the timer adapter. + * For Initializes timer adapter, + * @code + * TIMER_HANDLE_DEFINE(halTimerHandle); + * hal_timer_config_t halTimerConfig; + * halTimerConfig.timeout = 1000; + * halTimerConfig.srcClock_Hz = BOARD_GetTimeSrcClock(); + * halTimerConfig.instance = 0; + * HAL_TimerInit((hal_timer_handle_t)halTimerHandle, &halTimerConfig); + * @endcode + * + * @param halTimerHandle HAL timer adapter handle, the handle buffer with size #HAL_TIMER_HANDLE_SIZE + * should be allocated at upper level. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #TIMER_HANDLE_DEFINE(halTimerHandle); + * or + * uint32_t halTimerHandle[((HAL_TIMER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param halTimerConfig A pointer to the HAL timer configuration structure + * @retval kStatus_HAL_TimerSuccess The timer adapter module initialization succeed. + * @retval kStatus_HAL_TimerOutOfRanger The timer adapter instance out of ranger. + */ +hal_timer_status_t HAL_TimerInit(hal_timer_handle_t halTimerHandle, hal_timer_config_t* halTimerConfig); + +/*! + * @brief DeInitilizate the timer adapter module. + * + * @note This API should be called when not using the timer adapter anymore. + * + * @param halTimerHandle HAL timer adapter handle + */ +void HAL_TimerDeinit(hal_timer_handle_t halTimerHandle); + +/*! + * @brief Enable the timer adapter module. + * + * @note This API should be called when enable the timer adapter. + * + * @param halTimerHandle HAL timer adapter handle + */ +void HAL_TimerEnable(hal_timer_handle_t halTimerHandle); + +/*! + * @brief Disable the timer adapter module. + * + * @note This API should be called when disable the timer adapter. + * + * @param halTimerHandle HAL timer adapter handle + */ +void HAL_TimerDisable(hal_timer_handle_t halTimerHandle); + +/*! + * @brief Install the timer adapter module callback function. + * + * @note This API should be called to when to install callback function for the timer.Since callback function + * would be handled in ISR, and timer clock use high accuracy clock, user can get accuracy millisecond timer. + * + * @param halTimerHandle HAL timer adapter handle + * @param callback The installed callback function by upper layer + * @param callbackParam The callback function parameter + */ +void HAL_TimerInstallCallback(hal_timer_handle_t halTimerHandle, hal_timer_callback_t callback, void* callbackParam); + +/*! + * @brief Get the timer count of the timer adapter. + * + * @note This API should be return the real-time timer counting value in a range from 0 to a + * timer period, and return microseconds. + * + * @param halTimerHandle HAL timer adapter handle + * @retval the real-time timer counting value and return microseconds. + */ +uint32_t HAL_TimerGetCurrentTimerCount(hal_timer_handle_t halTimerHandle); + +/*! + * @brief Update the timeout of the timer adapter to generate timeout interrupt. + * + * @note This API should be called when need set the timeout of the timer interrupt.. + * + * @param halTimerHandle HAL timer adapter handle + * @param timeout Timeout time, should be used microseconds. + * @retval kStatus_HAL_TimerSuccess The timer adapter module update timeout succeed. + * @retval kStatus_HAL_TimerOutOfRanger The timer adapter set the timeout out of ranger. + */ +hal_timer_status_t HAL_TimerUpdateTimeout(hal_timer_handle_t halTimerHandle, uint32_t timeout); + +/*! + * @brief Get maximum Timer timeout + * + * @note This API should to get maximum Timer timeout value to avoid overflow + * + * @param halTimerHandle HAL timer adapter handle + * @retval get the real-time timer maximum timeout value and return microseconds. + */ +uint32_t HAL_TimerGetMaxTimeout(hal_timer_handle_t halTimerHandle); + +/*! + * @brief Timer adapter power up function. + * + * @note This API should be called by low power module when system exit from sleep mode. + * + * @param halTimerHandle HAL timer adapter handle + */ +void HAL_TimerExitLowpower(hal_timer_handle_t halTimerHandle); + +/*! + * @brief Timer adapter power down function. + * + * @note This API should be called by low power module before system enter into sleep mode. + * + * @param halTimerHandle HAL timer adapter handle + */ +void HAL_TimerEnterLowpower(hal_timer_handle_t halTimerHandle); + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /* _TIMER_H_ */ diff --git a/components/timer_manager/fsl_component_timer_manager.c b/components/timer_manager/fsl_component_timer_manager.c new file mode 100644 index 000000000..939c3f7a9 --- /dev/null +++ b/components/timer_manager/fsl_component_timer_manager.c @@ -0,0 +1,894 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_component_timer_manager.h" +#include "fsl_adapter_timer.h" +#if (defined(TM_ENABLE_TIME_STAMP) && (TM_ENABLE_TIME_STAMP > 0U)) +#include "fsl_adapter_time_stamp.h" +#endif +/* + * The OSA_USED macro can only be defined when the OSA component is used. + * If the source code of the OSA component does not exist, the OSA_USED cannot be defined. + * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED + * also cannot be defined. + * The source code path of the OSA component is /components/osa. + * + */ +#if defined(OSA_USED) +#include "fsl_os_abstraction.h" +#if (defined(TM_COMMON_TASK_ENABLE) && (TM_COMMON_TASK_ENABLE > 0U)) +#include "fsl_component_common_task.h" +#endif +#endif + +#if defined(OSA_USED) +#if (defined(USE_RTOS) && (USE_RTOS > 0U)) +#define TIMER_ENTER_CRITICAL() \ + OSA_SR_ALLOC(); \ + OSA_ENTER_CRITICAL() +#define TIMER_EXIT_CRITICAL() OSA_EXIT_CRITICAL() +#else +#define TIMER_ENTER_CRITICAL() +#define TIMER_EXIT_CRITICAL() +#endif +#else +#define TIMER_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ(); +#define TIMER_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask); +#endif + +/***************************************************************************** +****************************************************************************** +* Private macros +****************************************************************************** +*****************************************************************************/ +#define mTmrDummyEvent_c (1UL << 16U) + +/**@brief Timer status. */ +typedef enum _timer_state +{ + kTimerStateFree_c = 0x00, /**< The timer free status. */ + kTimerStateActive_c = 0x20, /**< The timer active status. */ + kTimerStateReady_c = 0x40, /**< The timer ready status. */ + kTimerStateInactive_c = 0x80, /**< The timer inactive status. */ + kTimerStateMask_c = 0xE0, /**< The timer status mask all. */ + kTimerModeMask_c = 0x1F, /**< The timer mode mask all. */ +} timer_state_t; + +/***************************************************************************** +****************************************************************************** +* Private type definitions +****************************************************************************** +*****************************************************************************/ +/*! @brief Timer handle structure for timer manager. */ +typedef struct _timer_handle_struct_t +{ + struct _timer_handle_struct_t *next; /*!< LIST_ element of the link */ + volatile uint8_t tmrStatus; /*!< Timer status and mode*/ + uint64_t timeoutInUs; /*!< Time out of the timer, should be microseconds */ + uint64_t remainingUs; /*!< Remaining of the timer, should be microseconds */ + timer_callback_t pfCallBack; /*!< Callback function of the timer */ + void *param; /*!< Parameter of callback function of the timer */ +} timer_handle_struct_t; +/*! @brief State structure for timer manager. */ +typedef struct _timermanager_state +{ + uint32_t mUsInTimerInterval; /*!< Timer intervl in microseconds */ + uint32_t previousTimeInUs; /*!< Previous timer count in microseconds */ + timer_handle_struct_t *timerHead; /*!< Timer list head */ + TIMER_HANDLE_DEFINE(halTimerHandle); /*!< Timer handle buffer */ +#if (defined(TM_ENABLE_TIME_STAMP) && (TM_ENABLE_TIME_STAMP > 0U)) + TIME_STAMP_HANDLE_DEFINE(halTimeStampHandle); /*!< Time stamp handle buffer */ +#endif +#if defined(OSA_USED) +#if (defined(TM_COMMON_TASK_ENABLE) && (TM_COMMON_TASK_ENABLE > 0U)) + common_task_message_t mTimerCommontaskMsg; /*!< Timer common_task message */ +#else + OSA_EVENT_HANDLE_DEFINE(halTimerTaskEventHandle); /*!< Timer task event handle buffer */ + OSA_TASK_HANDLE_DEFINE(timerTaskHandle); /*!< Timer task id */ +#endif +#endif + volatile uint8_t numberOfActiveTimers; /*!< Number of active Timers*/ + volatile uint8_t numberOfLowPowerActiveTimers; /*!< Number of low power active Timers */ + volatile uint8_t timerHardwareIsRunning; /*!< Hardware timer is runnig */ + uint8_t initialized; /*!< Timer is initialized */ +} timermanager_state_t; + +/***************************************************************************** +****************************************************************************** +* Public memory declarations +****************************************************************************** +*****************************************************************************/ + +/***************************************************************************** + ***************************************************************************** + * Private prototypes + ***************************************************************************** + *****************************************************************************/ + +/*! ------------------------------------------------------------------------- + * \brief Function called by driver ISR on channel match in interrupt context. + *---------------------------------------------------------------------------*/ +static void HAL_TIMER_Callback(void *param); + +/*! ------------------------------------------------------------------------- + * \brief Timer thread. + * Called by the kernel when the timer ISR posts a timer event. + * \param[in] param - User parameter to timer thread; not used. + *---------------------------------------------------------------------------*/ +static void TimerManagerTask(void *param); + +static void TimerEnable(timer_handle_t timerHandle); + +static timer_status_t TimerStop(timer_handle_t timerHandle); + +/***************************************************************************** + ***************************************************************************** + * Private memory definitions + ***************************************************************************** + *****************************************************************************/ +static timermanager_state_t s_timermanager = {0}; +/***************************************************************************** +****************************************************************************** +* Private API macro define +****************************************************************************** +*****************************************************************************/ + +#define IncrementActiveTimerNumber(type) \ + ((((type) & (uint8_t)kTimerModeLowPowerTimer) != 0U) ? (++s_timermanager.numberOfLowPowerActiveTimers) : \ + (++s_timermanager.numberOfActiveTimers)) +#define DecrementActiveTimerNumber(type) \ + ((((type) & (uint8_t)kTimerModeLowPowerTimer) != 0U) ? (--s_timermanager.numberOfLowPowerActiveTimers) : \ + (--s_timermanager.numberOfActiveTimers)) + +/* + * \brief Detect if the timer is a low-power timer + */ +#define IsLowPowerTimer(type) ((type) & (uint8_t)kTimerModeLowPowerTimer) + +#if defined(OSA_USED) +#if (defined(TM_COMMON_TASK_ENABLE) && (TM_COMMON_TASK_ENABLE > 0U)) + +#else +/* + * \brief Defines the timer thread's stack + */ +static OSA_TASK_DEFINE(TimerManagerTask, TM_TASK_PRIORITY, 1, TM_TASK_STACK_SIZE, false); +#endif +#endif + +/***************************************************************************** +****************************************************************************** +* Private functions +****************************************************************************** +*****************************************************************************/ +/*!------------------------------------------------------------------------- + * \brief Returns the timer status + * \param[in] timerHandle - the handle of timer + * \return see definition of uint8_t + *---------------------------------------------------------------------------*/ +static uint8_t TimerGetTimerStatus(timer_handle_t timerHandle) +{ + timer_handle_struct_t *timer = (timer_handle_struct_t *)timerHandle; + return timer->tmrStatus & (uint8_t)kTimerStateMask_c; +} + +/*! ------------------------------------------------------------------------- + * \brief Set the timer status + * \param[in] timerHandle - the handle of timer + * \param[in] status - the status of the timer + *---------------------------------------------------------------------------*/ +static void TimerSetTimerStatus(timer_handle_t timerHandle, uint8_t status) +{ + timer_handle_struct_t *timer = (timer_handle_struct_t *)timerHandle; + timer->tmrStatus &= (~(uint8_t)kTimerStateMask_c); + timer->tmrStatus |= status; +} + +/*! ------------------------------------------------------------------------- + * \brief Returns the timer type + * \param[in] timerHandle - the handle of timer + * \return see definition of uint8_t + *---------------------------------------------------------------------------*/ +static uint8_t TimerGetTimerType(timer_handle_t timerHandle) +{ + timer_handle_struct_t *timer = (timer_handle_struct_t *)timerHandle; + return timer->tmrStatus & (uint8_t)kTimerModeMask_c; +} + +/*! ------------------------------------------------------------------------- + * \brief Set the timer type + * \param[in] timerHandle - the handle of timer + * \param[in] timerType - timer type + *---------------------------------------------------------------------------*/ +static void TimerSetTimerType(timer_handle_t timerHandle, uint8_t timerType) +{ + timer_handle_struct_t *timer = (timer_handle_struct_t *)timerHandle; + timer->tmrStatus &= (~(uint8_t)kTimerModeMask_c); + timer->tmrStatus |= timerType; +} + +/*! ------------------------------------------------------------------------- + * \brief Set the timer free + * \param[in] timerHandle - the handle of timer + * \param[in] type - timer type + *---------------------------------------------------------------------------*/ +static void TimerMarkTimerFree(timer_handle_t timerHandle) +{ + timer_handle_struct_t *timer = (timer_handle_struct_t *)timerHandle; + timer->tmrStatus = 0; +} + +/*! ------------------------------------------------------------------------- + * \brief Notify Timer task to run. + * \return + *---------------------------------------------------------------------------*/ +static void NotifyTimersTask(void) +{ +#if defined(OSA_USED) +#if (defined(TM_COMMON_TASK_ENABLE) && (TM_COMMON_TASK_ENABLE > 0U)) + s_timermanager.mTimerCommontaskMsg.callback = TimerManagerTask; + (void)COMMON_TASK_post_message(&s_timermanager.mTimerCommontaskMsg); +#else + (void)OSA_EventSet((osa_event_handle_t)s_timermanager.halTimerTaskEventHandle, mTmrDummyEvent_c); +#endif +#else + TimerManagerTask(NULL); +#endif +} + +/*! ------------------------------------------------------------------------- + * \brief Update Remaining Us for all Active timers + * \return + *---------------------------------------------------------------------------*/ +static void TimersUpdate(bool updateRemainingUs, bool updateOnlyPowerTimer, uint32_t remainingUs) +{ + timer_handle_struct_t *th = s_timermanager.timerHead; + + if ((s_timermanager.numberOfLowPowerActiveTimers != 0U) || (s_timermanager.numberOfActiveTimers != 0U)) + { + while (th != NULL) + { + if (updateRemainingUs) + { + if ((timer_state_t)TimerGetTimerStatus(th) == kTimerStateActive_c) + { + if ((updateOnlyPowerTimer && (0U != IsLowPowerTimer(TimerGetTimerType(th)))) || + (!updateOnlyPowerTimer)) + + { + if (th->remainingUs > remainingUs) + { + th->remainingUs = th->remainingUs - remainingUs; + } + else + { + th->remainingUs = 0; + } + } + } + } + th = th->next; + } + } +} + +/*! ------------------------------------------------------------------------- + * \brief Update Remaining Us for all Active timers and sync timer task + * \return + *---------------------------------------------------------------------------*/ +static void TimersUpdateSyncTask(uint32_t remainingUs) +{ + TimersUpdate(true, false, remainingUs); + s_timermanager.previousTimeInUs = HAL_TimerGetCurrentTimerCount((hal_timer_handle_t)s_timermanager.halTimerHandle); + NotifyTimersTask(); +} + +/*! ------------------------------------------------------------------------- + * \brief Function called by driver ISR on channel match in interrupt context. + *---------------------------------------------------------------------------*/ +static void HAL_TIMER_Callback(void *param) +{ + TimersUpdateSyncTask(s_timermanager.mUsInTimerInterval); +} +/*! ------------------------------------------------------------------------- + * \brief TimerManager task. + * Called by the kernel when the timer ISR posts a timer event. + * \param[in] param + *---------------------------------------------------------------------------*/ +static void TimerManagerTask(void *param) +{ + uint8_t timerType; + timer_state_t state; + static uint32_t mpevUsInTimerInterval = 0; + uint8_t activeLPTimerNum, activeTimerNum; + +#if defined(OSA_USED) +#if (defined(TM_COMMON_TASK_ENABLE) && (TM_COMMON_TASK_ENABLE > 0U)) + { +#else + osa_event_flags_t ev = 0; + do + { + if (KOSA_StatusSuccess == OSA_EventWait((osa_event_handle_t)s_timermanager.halTimerTaskEventHandle, + osaEventFlagsAll_c, 0U, osaWaitForever_c, &ev)) + { +#endif +#endif + + uint32_t regPrimask = DisableGlobalIRQ(); + s_timermanager.mUsInTimerInterval = HAL_TimerGetMaxTimeout((hal_timer_handle_t)s_timermanager.halTimerHandle); + timer_handle_struct_t *th = s_timermanager.timerHead; + while (NULL != th) + { + timerType = TimerGetTimerType(th); + state = (timer_state_t)TimerGetTimerStatus(th); + if (kTimerStateReady_c == state) + { + TimerSetTimerStatus(th, (uint8_t)kTimerStateActive_c); + if (s_timermanager.mUsInTimerInterval > th->timeoutInUs) + { + s_timermanager.mUsInTimerInterval = (uint32_t)th->timeoutInUs; + } + } + if (kTimerStateActive_c == state) + { + /* This timer is active. Decrement it's countdown.. */ + if (0U >= th->remainingUs) + { + /* If this is an interval timer, restart it. Otherwise, mark it as inactive. */ + if (0U != (timerType & (uint32_t)(kTimerModeSingleShot))) + { + th->remainingUs = 0; + (void)TimerStop(th); + state = (timer_state_t)TimerGetTimerStatus(th); + } + else + { + th->remainingUs = th->timeoutInUs; + } + /* This timer has expired. */ + /*Call callback if it is not NULL*/ + EnableGlobalIRQ(regPrimask); + if (NULL != th->pfCallBack) + { + th->pfCallBack(th->param); + } + regPrimask = DisableGlobalIRQ(); + } + if ((kTimerStateActive_c == state) && (s_timermanager.mUsInTimerInterval > th->remainingUs)) + { + s_timermanager.mUsInTimerInterval = (uint32_t)th->remainingUs; + } + } + else + { + /* Ignore any timer that is not active. */ + } + th = th->next; + } + + activeLPTimerNum = s_timermanager.numberOfLowPowerActiveTimers; + activeTimerNum = s_timermanager.numberOfActiveTimers; + + if ((0U != activeLPTimerNum) || (0U != activeTimerNum)) + { + if ((s_timermanager.mUsInTimerInterval != mpevUsInTimerInterval) || + (0U == s_timermanager.timerHardwareIsRunning)) + { + HAL_TimerDisable((hal_timer_handle_t)s_timermanager.halTimerHandle); + (void)HAL_TimerUpdateTimeout((hal_timer_handle_t)s_timermanager.halTimerHandle, + s_timermanager.mUsInTimerInterval); + HAL_TimerEnable((hal_timer_handle_t)s_timermanager.halTimerHandle); + mpevUsInTimerInterval = s_timermanager.mUsInTimerInterval; + } + s_timermanager.timerHardwareIsRunning = (uint8_t) true; + } + EnableGlobalIRQ(regPrimask); +#if defined(OSA_USED) +#if (defined(TM_COMMON_TASK_ENABLE) && (TM_COMMON_TASK_ENABLE > 0U)) + } +#else + } + } while (0U != gUseRtos_c); +#endif +#endif +} + +/*! ------------------------------------------------------------------------- + * \brief stop a specified timer. + * \param[in] timerHandle - the handle of the timer + * \return see definition of timer_status_t + *---------------------------------------------------------------------------*/ +static timer_status_t TimerStop(timer_handle_t timerHandle) +{ + timer_status_t status = kStatus_TimerInvalidId; + timer_state_t state; + uint8_t activeLPTimerNum, activeTimerNum; + uint32_t regPrimask = DisableGlobalIRQ(); + if (NULL != timerHandle) + { + state = (timer_state_t)TimerGetTimerStatus(timerHandle); + status = kStatus_TimerSuccess; + if ((state == kTimerStateActive_c) || (state == kTimerStateReady_c)) + { + TimerSetTimerStatus(timerHandle, (uint8_t)kTimerStateInactive_c); + DecrementActiveTimerNumber(TimerGetTimerType(timerHandle)); + /* if no sw active timers are enabled, */ + /* call the TimerManagerTask() to countdown the ticks and stop the hw timer*/ + activeLPTimerNum = s_timermanager.numberOfLowPowerActiveTimers; + activeTimerNum = s_timermanager.numberOfActiveTimers; + if ((0U == activeTimerNum) && (0U == activeLPTimerNum)) + { + if (0U != s_timermanager.timerHardwareIsRunning) + { + HAL_TimerDisable((hal_timer_handle_t)s_timermanager.halTimerHandle); + s_timermanager.timerHardwareIsRunning = 0U; + } + } + } + } + EnableGlobalIRQ(regPrimask); + return status; +} + +/*! ------------------------------------------------------------------------- + * \brief Enable the specified timer + * \param[in] timerHandle - the handle of the timer + *---------------------------------------------------------------------------*/ +static void TimerEnable(timer_handle_t timerHandle) +{ + assert(timerHandle); + uint32_t regPrimask = DisableGlobalIRQ(); + + if ((uint8_t)kTimerStateInactive_c == TimerGetTimerStatus(timerHandle)) + { + IncrementActiveTimerNumber(TimerGetTimerType(timerHandle)); + TimerSetTimerStatus(timerHandle, (uint8_t)kTimerStateReady_c); + TimersUpdateSyncTask(HAL_TimerGetCurrentTimerCount((hal_timer_handle_t)s_timermanager.halTimerHandle)); + } + EnableGlobalIRQ(regPrimask); +} + +/***************************************************************************** +****************************************************************************** +* Public functions +****************************************************************************** +*****************************************************************************/ +/*! + * @brief Initializes timer manager module with the user configuration structure. + * + * + * @param timerConfig Pointer to user-defined timer configuration structure. + * @retval kStatus_TimerSuccess Timer manager initialization succeed. + * @retval kStatus_TimerError An error occurred. + */ +timer_status_t TM_Init(timer_config_t *timerConfig) +{ + hal_timer_config_t halTimerConfig; + hal_timer_handle_t halTimerHandle = &s_timermanager.halTimerHandle[0]; + hal_timer_status_t status; +#if (defined(TM_ENABLE_TIME_STAMP) && (TM_ENABLE_TIME_STAMP > 0U)) + hal_time_stamp_config_t halTimeStampConfig; + hal_time_stamp_handle_t halTimeStampHandle = &s_timermanager.halTimeStampHandle[0]; +#endif + assert(timerConfig); + /* Check if TMR is already initialized */ + if (0U == s_timermanager.initialized) + { + halTimerConfig.timeout = 1000; + halTimerConfig.srcClock_Hz = timerConfig->srcClock_Hz; + halTimerConfig.instance = timerConfig->instance; +#if (defined(TM_ENABLE_TIMER_CLOCK_SELECT) && (TM_ENABLE_TIMER_CLOCK_SELECT > 0U)) + halTimerConfig.clockSrcSelect = timerConfig->clockSrcSelect; +#endif + status = HAL_TimerInit(halTimerHandle, &halTimerConfig); + assert(kStatus_HAL_TimerSuccess == status); + (void)status; + + HAL_TimerInstallCallback(halTimerHandle, HAL_TIMER_Callback, NULL); + s_timermanager.mUsInTimerInterval = halTimerConfig.timeout; +#if defined(OSA_USED) +#if (defined(TM_COMMON_TASK_ENABLE) && (TM_COMMON_TASK_ENABLE > 0U)) + (void)COMMON_TASK_init(); +#else + osa_status_t osaStatus; + osaStatus = OSA_EventCreate((osa_event_handle_t)s_timermanager.halTimerTaskEventHandle, 1U); + assert(KOSA_StatusSuccess == (osa_status_t)osaStatus); + (void)osaStatus; + + osaStatus = OSA_TaskCreate((osa_task_handle_t)s_timermanager.timerTaskHandle, OSA_TASK(TimerManagerTask), NULL); + assert(KOSA_StatusSuccess == (osa_status_t)osaStatus); + (void)osaStatus; +#endif +#endif +#if (defined(TM_ENABLE_TIME_STAMP) && (TM_ENABLE_TIME_STAMP > 0U)) + halTimeStampConfig.srcClock_Hz = timerConfig->timeStampSrcClock_Hz; + halTimeStampConfig.instance = timerConfig->timeStampInstance; +#if (defined(TM_ENABLE_TIME_STAMP_CLOCK_SELECT) && (TM_ENABLE_TIME_STAMP_CLOCK_SELECT > 0U)) + halTimeStampConfig.clockSrcSelect = timerConfig->clockSrcSelect; +#endif + HAL_TimeStampInit(halTimeStampHandle, &halTimeStampConfig); +#endif + s_timermanager.initialized = 1U; + } + return kStatus_TimerSuccess; +} + +/*! + * @brief Deinitialize timer manager module. + * + */ +void TM_Deinit(void) +{ +#if defined(OSA_USED) +#if (defined(TM_COMMON_TASK_ENABLE) && (TM_COMMON_TASK_ENABLE > 0U)) +#else + (void)OSA_EventDestroy((osa_event_handle_t)s_timermanager.halTimerTaskEventHandle); + (void)OSA_TaskDestroy((osa_task_handle_t)s_timermanager.timerTaskHandle); +#endif +#endif + HAL_TimerDeinit((hal_timer_handle_t)s_timermanager.halTimerHandle); + (void)memset(&s_timermanager, 0x0, sizeof(s_timermanager)); +} + +/*! + * @brief Power up timer manager module. + * + */ +void TM_ExitLowpower(void) +{ +#if (defined(TM_ENABLE_LOW_POWER_TIMER) && (TM_ENABLE_LOW_POWER_TIMER > 0U)) + HAL_TimerExitLowpower((hal_timer_handle_t)s_timermanager.halTimerHandle); +#endif +#if (defined(TM_ENABLE_TIME_STAMP) && (TM_ENABLE_TIME_STAMP > 0U)) + HAL_TimeStampExitLowpower(s_timermanager.halTimerHandle); +#endif +} + +/*! + * @brief Power down timer manager module. + * + */ +void TM_EnterLowpower(void) +{ +#if (defined(TM_ENABLE_LOW_POWER_TIMER) && (TM_ENABLE_LOW_POWER_TIMER > 0U)) + HAL_TimerEnterLowpower((hal_timer_handle_t)s_timermanager.halTimerHandle); +#endif +} + +/*! + * @brief Get a time-stamp value + * + */ +uint64_t TM_GetTimestamp(void) +{ +#if (defined(TM_ENABLE_TIME_STAMP) && (TM_ENABLE_TIME_STAMP > 0U)) + return HAL_GetTimeStamp((hal_time_stamp_handle_t)s_timermanager.halTimeStampHandle); +#else + return 0U; +#endif /* TM_ENABLE_TIME_STAMP */ +} + +/*! + * @brief Open a timer with user handle. + * + * @param timerHandle Pointer to point to a memory space of size #TIMER_HANDLE_SIZE allocated by the + * caller. + * @retval kStatus_TimerSuccess Timer open succeed. + * @retval kStatus_TimerError An error occurred. + */ +timer_status_t TM_Open(timer_handle_t timerHandle) +{ + timer_handle_struct_t *timerState = timerHandle; + assert(sizeof(timer_handle_struct_t) == TIMER_HANDLE_SIZE); + assert(timerHandle); + TIMER_ENTER_CRITICAL(); + TimerSetTimerStatus(timerState, (uint8_t)kTimerStateInactive_c); + if (NULL == s_timermanager.timerHead) + { + s_timermanager.timerHead = timerHandle; + } + else + { + timerState->next = s_timermanager.timerHead; + s_timermanager.timerHead = timerHandle; + } + TIMER_EXIT_CRITICAL(); + return kStatus_TimerSuccess; +} + +/*! + * @brief Close a timer with user handle. + * + * @param timerHandle - the handle of the timer + * + * @retval kStatus_TimerSuccess Timer close succeed. + * @retval kStatus_TimerError An error occurred. + */ +timer_status_t TM_Close(timer_handle_t timerHandle) +{ + timer_status_t status; + timer_handle_struct_t *timerState = timerHandle; + timer_handle_struct_t *timerStatePre; + assert(timerHandle); + TIMER_ENTER_CRITICAL(); + status = TM_Stop(timerHandle); + + assert(kStatus_TimerSuccess == status); + (void)status; + + TimerMarkTimerFree(timerHandle); + + timerStatePre = s_timermanager.timerHead; + + if (timerStatePre != timerState) + { + while ((NULL != timerStatePre) && (timerStatePre->next != timerState)) + { + timerStatePre = timerStatePre->next; + } + if (NULL != timerStatePre) + { + timerStatePre->next = timerState->next; + } + } + else + { + s_timermanager.timerHead = timerState->next; + } + TIMER_EXIT_CRITICAL(); + return kStatus_TimerSuccess; +} + +/*! + * @brief Check if all timers except the LP timers are OFF + * + * + * @retval return 1 there are no active non-low power timers, 0 otherwise. + */ + +uint8_t TM_AreAllTimersOff(void) +{ + return s_timermanager.numberOfActiveTimers == 0U ? 1U : 0U; +} + +/*! + * @brief Check if a specified timer is active + * + * @param timerHandle - the handle of the timer + * + * @retval return 1 if timer is active, return 0 if timer is not active. + */ +uint8_t TM_IsTimerActive(timer_handle_t timerHandle) +{ + assert(timerHandle); + return (uint8_t)(TimerGetTimerStatus(timerHandle) == (uint8_t)kTimerStateActive_c); +} + +/*! + * @brief Check if a specified timer is ready + * + * @param timerHandle - the handle of the timer + * + * @retval return 1 if timer is ready, return 0 if timer is not ready. + */ +uint8_t TM_IsTimerReady(timer_handle_t timerHandle) +{ + assert(timerHandle); + return (uint8_t)(TimerGetTimerStatus(timerHandle) == (uint8_t)kTimerStateReady_c); +} + +/*! + * @brief Install a specified timer callback + * + * @param timerHandle - the handle of the timer + * @param callback - callback function + * @param callbackParam - parameter to callback function + * + * @retval kStatus_TimerSuccess Timer install callback succeed. + * + */ +timer_status_t TM_InstallCallback(timer_handle_t timerHandle, timer_callback_t callback, void *callbackParam) +{ + timer_handle_struct_t *th = timerHandle; + + assert(timerHandle); + th->pfCallBack = callback; + th->param = callbackParam; + + return kStatus_TimerSuccess; +} + +/*! + * @brief Start a specified timer + * + * @param timerHandle - the handle of the timer + * @param timerType - the type of the timer + * @param timerTimout - time expressed in millisecond units + * + * @retval kStatus_TimerSuccess Timer start succeed. + * @retval kStatus_TimerError An error occurred. + */ +timer_status_t TM_Start(timer_handle_t timerHandle, uint8_t timerType, uint32_t timerTimeout) +{ + timer_status_t status; + timer_handle_struct_t *th = timerHandle; + assert(timerHandle); + /* Stopping an already stopped timer is harmless. */ + status = TM_Stop(timerHandle); + assert(status == kStatus_TimerSuccess); + + TimerSetTimerType(timerHandle, timerType); + + if (0U != ((uint8_t)timerType & (uint8_t)kTimerModeSetMinuteTimer)) + { + th->timeoutInUs = (uint64_t)1000U * 1000U * 60U * timerTimeout; + th->remainingUs = (uint64_t)1000U * 1000U * 60U * timerTimeout; + } + else if (0U != ((uint8_t)timerType & (uint8_t)kTimerModeSetSecondTimer)) + { + th->timeoutInUs = (uint64_t)1000U * 1000U * timerTimeout; + th->remainingUs = (uint64_t)1000U * 1000U * timerTimeout; + } + else + { + th->timeoutInUs = (uint64_t)1000U * timerTimeout; + th->remainingUs = (uint64_t)1000U * timerTimeout; + } + + /* Enable timer, the timer task will do the rest of the work. */ + TimerEnable(timerHandle); + + return status; +} + +/*! + * @brief Stop a specified timer + * + * @param timerHandle - the handle of the timer + * + * @retval kStatus_TimerSuccess Timer stop succeed. + * @retval kStatus_TimerError An error occurred. + */ +timer_status_t TM_Stop(timer_handle_t timerHandle) +{ + timer_status_t status; + uint32_t regPrimask = DisableGlobalIRQ(); + + status = TimerStop(timerHandle); + TimersUpdateSyncTask(HAL_TimerGetCurrentTimerCount((hal_timer_handle_t)s_timermanager.halTimerHandle)); + EnableGlobalIRQ(regPrimask); + return status; +} + +/*! + * @brief Returns the remaining time until timeout + * + * @param timerHandle - the handle of the timer + * + * @retval remaining time in microseconds until first timer timeouts. + */ +uint32_t TM_GetRemainingTime(timer_handle_t timerHandle) +{ + timer_handle_struct_t *timerState = timerHandle; + assert(timerHandle); + return ((uint32_t)(timerState->remainingUs) - + (uint32_t)(HAL_TimerGetCurrentTimerCount((hal_timer_handle_t)s_timermanager.halTimerHandle) - + s_timermanager.previousTimeInUs)); +} + +/*! + * @brief Get the first expire time of timer + * + * @param timerHandle - the handle of the timer + * + * @retval return the first expire time us of all timer. + */ +uint32_t TM_GetFirstExpireTime(uint8_t timerType) +{ + uint32_t min = 0xFFFFFFFFU; + uint32_t remainingTime; + + timer_handle_struct_t *th = s_timermanager.timerHead; + while (NULL != th) + { + if ((bool)TM_IsTimerActive(th) && ((timerType & TimerGetTimerType(th)) > 0U)) + { + remainingTime = TM_GetRemainingTime(th); + if (remainingTime < min) + { + min = remainingTime; + } + } + th = th->next; + } + return min; +} + +/*! + * @brief Returns the handle of the timer of the first allocated timer that has the + * specified parameter. + * + * @param param - specified parameter of timer + * + * @retval return the handle of the timer if success. + */ +timer_handle_t TM_GetFirstTimerWithParam(void *param) +{ + timer_handle_struct_t *th = s_timermanager.timerHead; + + while (NULL != th) + { + if (th->param == param) + { + return th; + } + th = th->next; + } + return NULL; +} + +/*! + * @brief Returns not counted time before entering in sleep,This function is called + * by Low Power module; + * + * @retval return microseconds that wasn't counted before entering in sleep. + */ +uint32_t TM_NotCountedTimeBeforeSleep(void) +{ + uint32_t timeUs = 0; +#if (defined(TM_ENABLE_LOW_POWER_TIMER) && (TM_ENABLE_LOW_POWER_TIMER > 0U)) + uint32_t currentTimeInUs; + + if (0U != s_timermanager.numberOfLowPowerActiveTimers) + { + currentTimeInUs = HAL_TimerGetCurrentTimerCount((hal_timer_handle_t)s_timermanager.halTimerHandle); + HAL_TimerDisable((hal_timer_handle_t)s_timermanager.halTimerHandle); + s_timermanager.timerHardwareIsRunning = 0U; + + /* The hw timer is stopped but keep s_timermanager.timerHardwareIsRunning = TRUE...*/ + /* The Lpm timers are considered as being in running mode, so that */ + /* not to start the hw timer if a TMR event occurs (this shouldn't happen) */ + + timeUs = (uint32_t)(currentTimeInUs - s_timermanager.previousTimeInUs); + return timeUs; + } + return 0; +#endif +} + +/*! + * @brief Sync low power timer in sleep mode,This function is called by Low Power module; + * + * @param sleepDurationTmrUs - sleep duration in TMR microseconds + * + */ +void TM_SyncLpmTimers(uint32_t sleepDurationTmrUs) +{ +#if (defined(TM_ENABLE_LOW_POWER_TIMER) && (TM_ENABLE_LOW_POWER_TIMER > 0U)) + + TimersUpdateSyncTask(sleepDurationTmrUs); + HAL_TimerEnable((hal_timer_handle_t)s_timermanager.halTimerHandle); + s_timermanager.previousTimeInUs = HAL_TimerGetCurrentTimerCount((hal_timer_handle_t)s_timermanager.halTimerHandle); + +#else + sleepDurationTmrUs = sleepDurationTmrUs; +#endif /* #if (TM_ENABLE_LOW_POWER_TIMER) */ +} + +/*! + * @brief Make timer task ready after wakeup from lowpower mode,This function is called + * by Low Power module; + * + */ +void TM_MakeTimerTaskReady(void) +{ +#if (defined(TM_ENABLE_LOW_POWER_TIMER) && (TM_ENABLE_LOW_POWER_TIMER > 0U)) + NotifyTimersTask(); +#endif +} diff --git a/components/timer_manager/fsl_component_timer_manager.h b/components/timer_manager/fsl_component_timer_manager.h new file mode 100644 index 000000000..4473284b6 --- /dev/null +++ b/components/timer_manager/fsl_component_timer_manager.h @@ -0,0 +1,394 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __TIMERS_MANAGER_H__ +#define __TIMERS_MANAGER_H__ + +#include "fsl_common.h" +#if (defined(COMMON_TASK_ENABLE) && (COMMON_TASK_ENABLE == 0U)) +#include "fsl_component_common_task.h" +#endif /* COMMON_TASK_ENABLE */ +/*! + * @addtogroup Timer_Manager + * @{ + */ + +/*! + * @brief The timer manager component + * + * The timer manager is built based on the timer adapter component provided by the NXP + * MCUXpresso SDK. It could provide bellow features: + * shall support SingleShot,repeater,one minute timer,one second timer and low power mode + * shall support timer open ,close, start and stop operation, and support callback function install + * And provide 1ms accuracy timers + * + * The timer manager would be used with different HW timer modules like FTM, PIT, LPTMR. + * But at the same time, only one HW timer module could be used. On different platforms,different + * HW timer module would be used. For the platforms which have multiple HW timer modules, + * one HW timer module would be selected as the default, but it is easy to change the default + * HW timer module to another. Just two steps to switch the HW timer module: + * 1.Remove the default HW timer module source file from the project + * 2.Add the expected HW timer module source file to the project. + * For example, in platform FRDM-K64F, there are two HW timer modules available, FTM and PIT. + * FTM is used as the default HW timer, so ftm_adapter.c and timer.h is included in the project by + * default.If PIT is expected to be used as the HW timer, ftm_adapter.c need to be removed from the + * project and pit_adapter.c should be included in the project + */ +/***************************************************************************** +****************************************************************************** +* Public macros +****************************************************************************** +*****************************************************************************/ +/* + * @brief Configures the common task enable.If set to 1, then timer will use common task and consume less ram/flash + * size. + */ +#ifndef TM_COMMON_TASK_ENABLE +#define TM_COMMON_TASK_ENABLE (0) +#if (defined(COMMON_TASK_ENABLE) && (COMMON_TASK_ENABLE == 0U)) +#undef TM_COMMON_TASK_ENABLE +#define TM_COMMON_TASK_ENABLE (0U) +#endif +#endif +/* + * @brief Configures the timer task stack size. + */ +#ifndef TM_TASK_STACK_SIZE +#define TM_TASK_STACK_SIZE (600U) +#endif + +/* + * @brief Configures the timer task priority. + */ +#ifndef TM_TASK_PRIORITY +#define TM_TASK_PRIORITY (4U) +#endif + +/* + * @brief Enable/Disable Low Power Timer + * VALID RANGE: TRUE/FALSE + */ +#ifndef TM_ENABLE_LOW_POWER_TIMER +#define TM_ENABLE_LOW_POWER_TIMER (1) +#endif +/* + * @brief Enable/Disable TimeStamp + * VALID RANGE: TRUE/FALSE + */ +#ifndef TM_ENABLE_TIME_STAMP +#define TM_ENABLE_TIME_STAMP (0) +#endif + +/* + * @brief Enable/Disable clock select + * This macro just for lptmr timer clock select, if the lptmr does not to use the default clock source. + */ +#ifndef TM_ENABLE_TIMER_CLOCK_SELECT +#define TM_ENABLE_TIMER_CLOCK_SELECT (0) +#endif +/* + * @brief Enable/Disable clock select + * This macro just for lptmr time stamp clock select, if the lptmr does not to use the default clock source. + */ +#ifndef TM_ENABLE_TIME_STAMP_CLOCK_SELECT +#define TM_ENABLE_TIME_STAMP_CLOCK_SELECT (0) +#endif +/*! @brief Definition of timer manager handle size. */ +#define TIMER_HANDLE_SIZE (32U) + +/*! + * @brief Defines the timer manager handle + * + * This macro is used to define a 4 byte aligned timer manager handle. + * Then use "(eeprom_handle_t)name" to get the timer manager handle. + * + * The macro should be global and could be optional. You could also define timer manager handle by yourself. + * + * This is an example, + * @code + * TIMER_MANAGER_HANDLE_DEFINE(timerManagerHandle); + * @endcode + * + * @param name The name string of the timer manager handle. + */ +#define TIMER_MANAGER_HANDLE_DEFINE(name) uint32_t name[(TIMER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +/***************************************************************************** +****************************************************************************** +* Public type definitions +****************************************************************************** +*****************************************************************************/ +/**@brief Timer status. */ +typedef enum _timer_status +{ + kStatus_TimerSuccess = kStatus_Success, /*!< Success */ + kStatus_TimerInvalidId = MAKE_STATUS(kStatusGroup_TIMERMANAGER, 1), /*!< Invalid Id */ + kStatus_TimerNotSupport = MAKE_STATUS(kStatusGroup_TIMERMANAGER, 2), /*!< Not Support */ + kStatus_TimerOutOfRange = MAKE_STATUS(kStatusGroup_TIMERMANAGER, 3), /*!< Out Of Range */ + kStatus_TimerError = MAKE_STATUS(kStatusGroup_TIMERMANAGER, 4), /*!< Fail */ +} timer_status_t; + +/**@brief Timer modes. */ +typedef enum _timer_mode +{ + kTimerModeSingleShot = 0x01U, /**< The timer will expire only once. */ + kTimerModeIntervalTimer = 0x02U, /**< The timer will restart each time it expires. */ + kTimerModeSetMinuteTimer = 0x04U, /**< The timer will one minute timer. */ + kTimerModeSetSecondTimer = 0x08U, /**< The timer will one second timer. */ + kTimerModeLowPowerTimer = 0x10U, /**< The timer will low power mode timer. */ +} timer_mode_t; + +/**@brief Timer config. */ +typedef struct _timer_config +{ + uint32_t srcClock_Hz; /**< The timer source clock frequency. */ + uint8_t instance; /*!< Hardware timer module instance, for example: if you want use FTM0,then the instance + is configured to 0, if you want use FTM2 hardware timer, then configure the instance + to 2, detail information please refer to the SOC corresponding RM. Invalid instance + value will cause initialization failure. */ +#if (defined(TM_ENABLE_TIMER_CLOCK_SELECT) && (TM_ENABLE_TIMER_CLOCK_SELECT > 0U)) + uint8_t clockSrcSelect; /*!< Select clock source. It is just for lptmr timer clock select, if the lptmr does not + to use the default clock source*/ +#endif +#if (defined(TM_ENABLE_TIME_STAMP) && (TM_ENABLE_TIME_STAMP > 0U)) + uint32_t timeStampSrcClock_Hz; /**< The timer stamp source clock frequency. */ + uint8_t timeStampInstance; /**< Hardware timer module instance. This instance for time stamp */ +#if (defined(TM_ENABLE_TIME_STAMP_CLOCK_SELECT) && (TM_ENABLE_TIME_STAMP_CLOCK_SELECT > 0U)) + uint8_t timeStampClockSrcSelect; /*!< Select clock source. It is just for lptmr timer clock select, if the lptmr + does not to use the default clock source*/ +#endif +#endif +} timer_config_t; + +/* + * @brief Timer handle + */ +typedef void *timer_handle_t; + +/* + * @brief Timer callback fiction + */ +typedef void (*timer_callback_t)(void *param); + +/* + * \brief Converts the macro argument from seconds to microseconds + */ +#define TmSecondsToMicroseconds(n) ((uint64_t)((n)*1000000UL)) + +/* + * \brief Converts the macro argument from seconds to milliseconds + */ +#define TmSecondsToMilliseconds(n) ((uint32_t)((n)*1000UL)) + +/* + * \brief Converts the macro argument from microseconds to seconds + */ +#define TmMicrosecondsToSeconds(n) (((n) + 500000U) / 1000000U) +/***************************************************************************** +****************************************************************************** +* Public memory declarations +****************************************************************************** +*****************************************************************************/ + +/***************************************************************************** +****************************************************************************** +* Public prototypes +****************************************************************************** +*****************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @brief Initializes timer manager module with the user configuration structure. + * + * For Initializes timer manager, + * @code + * timer_config_t timerConfig; + * timerConfig.instance = 0; + * timerConfig.srcClock_Hz = BOARD_GetTimerSrcClock(); + * TM_Init(&timerConfig); + * @endcode + * + * @param timerConfig Pointer to user-defined timer configuration structure. + * @retval kStatus_TimerSuccess Timer manager initialization succeed. + * @retval kStatus_TimerError An error occurred. + */ +timer_status_t TM_Init(timer_config_t *timerConfig); + +/*! + * @brief Deinitialize timer manager module. + * + */ +void TM_Deinit(void); + +/*! + * @brief Power up timer manager module. + * + */ +void TM_ExitLowpower(void); + +/*! + * @brief Power down timer manager module. + * + */ +void TM_EnterLowpower(void); + +/*! + * @brief Open a timer with user handle. + * + * @param timerHandle Pointer to a memory space of size #TIMER_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #TIMER_MANAGER_HANDLE_DEFINE(timerHandle); + * or + * uint32_t timerHandle[((TIMER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @retval kStatus_TimerSuccess Timer open succeed. + * @retval kStatus_TimerError An error occurred. + */ +timer_status_t TM_Open(timer_handle_t timerHandle); + +/*! + * @brief Close a timer with user handle. + * + * @param timerHandle the handle of the timer + * + * @retval kStatus_TimerSuccess Timer close succeed. + * @retval kStatus_TimerError An error occurred. + */ +timer_status_t TM_Close(timer_handle_t timerHandle); + +/*! + * @brief Install a specified timer callback + * + * @param timerHandle the handle of the timer + * @param callback callback function + * @param callbackParam parameter to callback function + * + * @retval kStatus_TimerSuccess Timer install callback succeed. + * + */ +timer_status_t TM_InstallCallback(timer_handle_t timerHandle, timer_callback_t callback, void *callbackParam); + +/*! + * @brief Start a specified timer + * + * @param timerHandle the handle of the timer + * @param timerType The mode of the timer, for example: kTimerModeSingleShot for the timer will expire + * only once, kTimerModeIntervalTimer, the timer will restart each time it expires. + * If low power mode is used at the same time. It should be set like this: kTimerModeSingleShot | + * kTimerModeLowPowerTimer + * @param timerTimeout The timer timeout in milliseconds unit for kTimerModeSingleShot, kTimerModeIntervalTimer + * and kTimerModeLowPowerTimer,if kTimerModeSetMinuteTimer timeout for minutes unit, if + * kTimerModeSetSecondTimer the timeout for seconds unit. + * + * @retval kStatus_TimerSuccess Timer start succeed. + * @retval kStatus_TimerError An error occurred. + */ +timer_status_t TM_Start(timer_handle_t timerHandle, uint8_t timerType, uint32_t timerTimeout); + +/*! + * @brief Stop a specified timer + * + * @param timerHandle the handle of the timer + * + * @retval kStatus_TimerSuccess Timer stop succeed. + * @retval kStatus_TimerError An error occurred. + */ +timer_status_t TM_Stop(timer_handle_t timerHandle); + +/*! + * @brief Check if a specified timer is active + * + * @param timerHandle the handle of the timer + * + * @retval return 1 if timer is active, return 0 if timer is not active. + */ +uint8_t TM_IsTimerActive(timer_handle_t timerHandle); + +/*! + * @brief Check if a specified timer is ready + * + * @param timerHandle the handle of the timer + * + * @retval return 1 if timer is ready, return 0 if timer is not ready. + */ +uint8_t TM_IsTimerReady(timer_handle_t timerHandle); + +/*! + * @brief Returns the remaining time until timeout + * + * @param timerHandle the handle of the timer + * + * @retval remaining time in microseconds until first timer timeouts. + */ +uint32_t TM_GetRemainingTime(timer_handle_t timerHandle); + +/*! + * @brief Get the first expire time of timer + * + * @param timerType The mode of the timer, for example: kTimerModeSingleShot for the timer will expire + * only once, kTimerModeIntervalTimer, the timer will restart each time it expires. + * + * @retval return the first expire time of all timer. + */ +uint32_t TM_GetFirstExpireTime(uint8_t timerType); + +/*! + * @brief Returns the handle of the timer of the first allocated timer that has the + * specified parameter. + * + * @param param specified parameter of timer + * + * @retval return the handle of the timer if success. + */ +timer_handle_t TM_GetFirstTimerWithParam(void *param); + +/*! + * @brief Check if all timers except the LP timers are OFF + * + * + * @retval return 1 there are no active non-low power timers, 0 otherwise. + */ +uint8_t TM_AreAllTimersOff(void); + +/*! + * @brief Returns not counted time before system entering in sleep, This function is called + * by Low Power module. + * + * @retval return microseconds that wasn't counted before entering in sleep. + */ +uint32_t TM_NotCountedTimeBeforeSleep(void); + +/*! + * @brief Sync low power timer in sleep mode, This function is called by Low Power module; + * + * @param sleepDurationTmrUs sleep duration in microseconds unit + * + */ +void TM_SyncLpmTimers(uint32_t sleepDurationTmrUs); + +/*! + * @brief Make timer task ready after wakeup from lowpower mode, This function is called + * by Low Power module; + * + */ +void TM_MakeTimerTaskReady(void); + +/*! + * @brief Get a time-stamp value + * + */ +uint64_t TM_GetTimestamp(void); + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /* #ifndef __TIMERS_MANAGER_H__ */ diff --git a/components/uart/component_iuart_adapter_MIMX8MQ6.cmake b/components/uart/component_iuart_adapter_MIMX8MQ6.cmake new file mode 100644 index 000000000..5815d585b --- /dev/null +++ b/components/uart/component_iuart_adapter_MIMX8MQ6.cmake @@ -0,0 +1,17 @@ +include_guard(GLOBAL) +message("component_iuart_adapter component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_adapter_iuart.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + +include(driver_iuart_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/MIMX8MQ6_cm4.h b/devices/MIMX8MQ6/MIMX8MQ6_cm4.h new file mode 100644 index 000000000..bda710b4e --- /dev/null +++ b/devices/MIMX8MQ6/MIMX8MQ6_cm4.h @@ -0,0 +1,59343 @@ +/* +** ################################################################### +** Processors: MIMX8MQ6CVAHZ +** MIMX8MQ6DVAJZ +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b210305 +** +** Abstract: +** CMSIS Peripheral Access Layer for MIMX8MQ6_cm4 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2017-01-10) +** Initial version. +** - rev. 2.0 (2017-04-27) +** Rev.B Header EAR1 +** - rev. 3.0 (2017-07-19) +** Rev.C Header EAR2 +** - rev. 4.0 (2018-01-26) +** Rev.D Header RFP +** +** ################################################################### +*/ + +/*! + * @file MIMX8MQ6_cm4.h + * @version 4.0 + * @date 2018-01-26 + * @brief CMSIS Peripheral Access Layer for MIMX8MQ6_cm4 + * + * CMSIS Peripheral Access Layer for MIMX8MQ6_cm4 + */ + +#ifndef _MIMX8MQ6_CM4_H_ +#define _MIMX8MQ6_CM4_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0400U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + GPR_IRQ_IRQn = 0, /**< GPR Interrupt. Used to notify cores on exception condition while boot. */ + DAP_IRQn = 1, /**< DAP Interrupt */ + SDMA1_IRQn = 2, /**< AND of all 48 SDMA interrupts (events) from all the channels */ + GPU_IRQn = 3, /**< GPU Interrupt */ + SNVS_IRQn = 4, /**< ON-OFF button press shorter than 5 seconds (pulse event) */ + LCDIF_IRQn = 5, /**< LCDIF Sync Interrupt */ + SPDIF1_IRQn = 6, /**< SPDIF1 Interrupt */ + H264_IRQn = 7, /**< h264 Decoder Interrupt */ + VPUDMA_IRQn = 8, /**< VPU DMA Interrupt */ + QOS_IRQn = 9, /**< QOS interrupt */ + WDOG3_IRQn = 10, /**< Watchdog Timer reset */ + HS_CP1_IRQn = 11, /**< HS Interrupt Request */ + APBHDMA_IRQn = 12, /**< GPMI operation channel 0-3 description complete interrupt */ + SPDIF2_IRQn = 13, /**< SPDIF2 Interrupt */ + BCH_IRQn = 14, /**< BCH operation complete interrupt */ + GPMI_IRQn = 15, /**< GPMI operation TIMEOUT ERROR interrupt */ + HDMI_IRQ0_IRQn = 16, /**< HDMI Interrupt 0 */ + HDMI_IRQ1_IRQn = 17, /**< HDMI Interrupt 1 */ + HDMI_IRQ2_IRQn = 18, /**< HDMI Interrupt 2 */ + SNVS_Consolidated_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */ + SNVS_Security_IRQn = 20, /**< SRTC Security Interrupt. TZ. */ + CSU_IRQn = 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted. */ + USDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */ + USDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */ + DDC_IRQn = 24, /**< DC8000 Display Controller IRQ */ + DTRC_IRQn = 25, /**< DTRC interrupt */ + UART1_IRQn = 26, /**< UART-1 ORed interrupt */ + UART2_IRQn = 27, /**< UART-2 ORed interrupt */ + UART3_IRQn = 28, /**< UART-3 ORed interrupt */ + UART4_IRQn = 29, /**< UART-4 ORed interrupt */ + VP9_IRQn = 30, /**< VP9 Decoder interrupt */ + ECSPI1_IRQn = 31, /**< ECSPI1 interrupt request line to the core. */ + ECSPI2_IRQn = 32, /**< ECSPI2 interrupt request line to the core. */ + ECSPI3_IRQn = 33, /**< ECSPI3 interrupt request line to the core. */ + MIPI_DSI_IRQn = 34, /**< DSI Interrupt */ + I2C1_IRQn = 35, /**< I2C-1 Interrupt */ + I2C2_IRQn = 36, /**< I2C-2 Interrupt */ + I2C3_IRQn = 37, /**< I2C-3 Interrupt */ + I2C4_IRQn = 38, /**< I2C-4 Interrupt */ + RDC_IRQn = 39, /**< RDC interrupt */ + USB1_IRQn = 40, /**< USB1 Interrupt */ + USB2_IRQn = 41, /**< USB1 Interrupt */ + CSI1_IRQn = 42, /**< CSI1 interrupt */ + CSI2_IRQn = 43, /**< CSI2 interrupt */ + MIPI_CSI1_IRQn = 44, /**< MIPI-CSI-1 Interrupt */ + MIPI_CSI2_IRQn = 45, /**< MIPI-CSI-2 Interrupt */ + GPT6_IRQn = 46, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ + SCTR_IRQ0_IRQn = 47, /**< ISO7816IP Interrupt 0 */ + SCTR_IRQ1_IRQn = 48, /**< ISO7816IP Interrupt 1 */ + TEMPMON_IRQn = 49, /**< TempSensor (Temperature alarm). */ + I2S3_IRQn = 50, /**< SAI3 Receive / Transmit Interrupt */ + GPT5_IRQn = 51, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ + GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ + GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ + GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ + GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ + GPIO1_INT7_IRQn = 56, /**< Active HIGH Interrupt from INT7 from GPIO */ + GPIO1_INT6_IRQn = 57, /**< Active HIGH Interrupt from INT6 from GPIO */ + GPIO1_INT5_IRQn = 58, /**< Active HIGH Interrupt from INT5 from GPIO */ + GPIO1_INT4_IRQn = 59, /**< Active HIGH Interrupt from INT4 from GPIO */ + GPIO1_INT3_IRQn = 60, /**< Active HIGH Interrupt from INT3 from GPIO */ + GPIO1_INT2_IRQn = 61, /**< Active HIGH Interrupt from INT2 from GPIO */ + GPIO1_INT1_IRQn = 62, /**< Active HIGH Interrupt from INT1 from GPIO */ + GPIO1_INT0_IRQn = 63, /**< Active HIGH Interrupt from INT0 from GPIO */ + GPIO1_Combined_0_15_IRQn = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ + GPIO1_Combined_16_31_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ + GPIO2_Combined_0_15_IRQn = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ + GPIO2_Combined_16_31_IRQn = 67, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */ + GPIO3_Combined_0_15_IRQn = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ + GPIO3_Combined_16_31_IRQn = 69, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */ + GPIO4_Combined_0_15_IRQn = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */ + GPIO4_Combined_16_31_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */ + GPIO5_Combined_0_15_IRQn = 72, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */ + GPIO5_Combined_16_31_IRQn = 73, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */ + PCIE_CTRL2_IRQ0_IRQn = 74, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL2_IRQ1_IRQn = 75, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL2_IRQ2_IRQn = 76, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL2_IRQ3_IRQn = 77, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + WDOG1_IRQn = 78, /**< Watchdog Timer reset */ + WDOG2_IRQn = 79, /**< Watchdog Timer reset */ + PCIE_CTRL2_IRQn = 80, /**< Channels [63:32] interrupts requests */ + PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */ + PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */ + PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */ + PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */ + CCM_IRQ1_IRQn = 85, /**< CCM, Interrupt Request 1 */ + CCM_IRQ2_IRQn = 86, /**< CCM, Interrupt Request 2 */ + GPC_IRQn = 87, /**< GPC Interrupt Request 1 */ + MU_A53_IRQn = 88, /**< Interrupt to A53 */ + SRC_IRQn = 89, /**< SRC interrupt request */ + I2S56_IRQn = 90, /**< SAI5/6 Receive / Transmit Interrupt */ + RTIC_IRQn = 91, /**< RTIC Interrupt */ + CPU_PerformanceUnit_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n] */ + CPU_CTI_Trigger_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[n] */ + SRC_Combined_IRQn = 94, /**< Combined CPU wdog interrupts (4x) out of SRC. */ + I2S1_IRQn = 95, /**< SAI1 Receive / Transmit Interrupt */ + I2S2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */ + MU_M4_IRQn = 97, /**< Interrupt to M4 */ + DDR_PerformanceMonitor_IRQn = 98, /**< ddr Interrupt for performance monitor */ + DDR_IRQn = 99, /**< ddr Interrupt */ + I2S4_IRQn = 100, /**< SAI4 Receive / Transmit Interrupt */ + CPU_Error_AXI_IRQn = 101, /**< CPU Error indicator for AXI transaction with a write response error condition */ + CPU_Error_L2RAM_IRQn = 102, /**< CPU Error indicator for L2 RAM double-bit ECC error */ + SDMA2_IRQn = 103, /**< AND of all 48 SDMA interrupts (events) from all the channels */ + Reserved120_IRQn = 104, /**< Reserved */ + CAAM_IRQ0_IRQn = 105, /**< CAAM interrupt queue for JQ */ + CAAM_IRQ1_IRQn = 106, /**< CAAM interrupt queue for JQ */ + QSPI_IRQn = 107, /**< QSPI Interrupt */ + TZASC_IRQn = 108, /**< TZASC (PL380) interrupt */ + Reserved125_IRQn = 109, /**< Reserved */ + Reserved126_IRQn = 110, /**< Reserved */ + Reserved127_IRQn = 111, /**< Reserved */ + PERFMON1_IRQn = 112, /**< General Interrupt */ + PERFMON2_IRQn = 113, /**< General Interrupt */ + CAAM_IRQ2_IRQn = 114, /**< CAAM interrupt queue for JQ */ + CAAM_ERROR_IRQn = 115, /**< Recoverable error interrupt */ + HS_CP0_IRQn = 116, /**< HS Interrupt Request */ + HEVC_IRQn = 117, /**< HEVC interrupt */ + ENET_MAC0_Rx_Tx_Done1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ + ENET_MAC0_Rx_Tx_Done2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ + ENET_IRQn = 120, /**< MAC 0 IRQ */ + ENET_1588_IRQn = 121, /**< MAC 0 1588 Timer Interrupt - synchronous */ + PCIE_CTRL1_IRQ0_IRQn = 122, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL1_IRQ1_IRQn = 123, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL1_IRQ2_IRQn = 124, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL1_IRQ3_IRQn = 125, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + Reserved142_IRQn = 126, /**< Reserved */ + PCIE_CTRL1_IRQn = 127 /**< Channels [63:32] interrupts requests */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_MIMX8MQ6_cm4.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_mux_ctl_pad +{ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_MDC = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_MDIO = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_TD3 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_TD2 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_TD1 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_TD0 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_TXC = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_RXC = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_RD0 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_RD1 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_RD2 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET_RD3 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_STROBE = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD2_CD_B = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD2_CLK = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD2_CMD = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD2_WP = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXC = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXC = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXC = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXC = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXC = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXD = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXC = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXD = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SPDIF_TX = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SPDIF_RX = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_I2C1_SCL = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_I2C1_SDA = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_I2C2_SCL = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_I2C2_SDA = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_I2C3_SCL = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_I2C3_SDA = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_I2C4_SCL = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_I2C4_SDA = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_RXD = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_TXD = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_RXD = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_TXD = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_RXD = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_TXD = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART4_RXD = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART4_TXD = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_sw_mux_ctl_pad_t; + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad +{ + kIOMUXC_SW_PAD_CTL_PAD_TEST_MODE = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_RTC = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ONOFF = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_POR_B = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_RTC_RESET_B = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_MDC = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_MDIO = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_TD3 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_TD2 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_TD1 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_TD0 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_TXC = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_RXC = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_RD0 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_RD1 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_RD2 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET_RD3 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA4 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA5 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA6 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA7 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_STROBE = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD2_CD_B = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD2_CLK = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD2_CMD = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD2_WP = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXFS = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXC = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD0 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD1 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD2 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD3 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD4 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD5 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD6 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD7 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXFS = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXC = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD0 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD1 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD2 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD3 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD4 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD5 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD6 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD7 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXC = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXC = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXC = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXD = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXC = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXD = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SPDIF_TX = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SPDIF_RX = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_I2C1_SCL = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_I2C1_SDA = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_I2C2_SCL = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_I2C2_SDA = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_I2C3_SDA = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_I2C4_SCL = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_I2C4_SDA = 145U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_RXD = 146U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_TXD = 147U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_RXD = 148U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_TXD = 149U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_RXD = 150U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_TXD = 151U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART4_RXD = 152U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART4_TXD = 153U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_sw_pad_ctl_pad_t; + +/* @} */ + +/*! + * @brief Enumeration for the IOMUXC select input + * + * Defines the enumeration for the IOMUXC select input collections. + */ +typedef enum _iomuxc_select_input +{ + kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 0U, /**< IOMUXC select input index */ + kIOMUXC_ENET1_MDIO_SELECT_INPUT = 1U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 2U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 3U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 4U, /**< IOMUXC select input index */ + kIOMUXC_SAI5_RX_BCLK_SELECT_INPUT = 5U, /**< IOMUXC select input index */ + kIOMUXC_SAI5_RXD0_SELECT_INPUT = 6U, /**< IOMUXC select input index */ + kIOMUXC_SAI5_RXD1_SELECT_INPUT = 7U, /**< IOMUXC select input index */ + kIOMUXC_SAI5_RXD2_SELECT_INPUT = 8U, /**< IOMUXC select input index */ + kIOMUXC_SAI5_RXD3_SELECT_INPUT = 9U, /**< IOMUXC select input index */ + kIOMUXC_SAI5_RX_SYNC_SELECT_INPUT = 10U, /**< IOMUXC select input index */ + kIOMUXC_SAI5_TX_BCLK_SELECT_INPUT = 11U, /**< IOMUXC select input index */ + kIOMUXC_SAI5_TX_SYNC_SELECT_INPUT = 12U, /**< IOMUXC select input index */ + kIOMUXC_UART1_RTS_B_SELECT_INPUT = 13U, /**< IOMUXC select input index */ + kIOMUXC_UART1_RXD_SELECT_INPUT = 14U, /**< IOMUXC select input index */ + kIOMUXC_UART2_RTS_B_SELECT_INPUT = 15U, /**< IOMUXC select input index */ + kIOMUXC_UART2_RXD_SELECT_INPUT = 16U, /**< IOMUXC select input index */ + kIOMUXC_UART3_RTS_B_SELECT_INPUT = 17U, /**< IOMUXC select input index */ + kIOMUXC_UART3_RXD_SELECT_INPUT = 18U, /**< IOMUXC select input index */ + kIOMUXC_UART4_RTS_B_SELECT_INPUT = 19U, /**< IOMUXC select input index */ + kIOMUXC_UART4_RXD_SELECT_INPUT = 20U, /**< IOMUXC select input index */ + kIOMUXC_SAI6_RX_BCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */ + kIOMUXC_SAI6_RXD0_SELECT_INPUT = 22U, /**< IOMUXC select input index */ + kIOMUXC_SAI6_RX_SYNC_SELECT_INPUT = 23U, /**< IOMUXC select input index */ + kIOMUXC_SAI6_TX_BCLK_SELECT_INPUT = 24U, /**< IOMUXC select input index */ + kIOMUXC_SAI6_TX_SYNC_SELECT_INPUT = 25U, /**< IOMUXC select input index */ + kIOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT = 26U, /**< IOMUXC select input index */ + kIOMUXC_PCIE2_CLKREQ_B_SELECT_INPUT = 27U, /**< IOMUXC select input index */ + kIOMUXC_SAI5_MCLK_SELECT_INPUT = 28U, /**< IOMUXC select input index */ + kIOMUXC_SAI6_MCLK_SELECT_INPUT = 29U, /**< IOMUXC select input index */ +} iomuxc_select_input_t; + +/*! + * @addtogroup rdc_mapping + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the RDC mapping + * + * Defines the structure for the RDC resource collections. + */ + +typedef enum _rdc_master +{ + kRDC_Master_A53 = 0U, /**< ARM Cortex-A53 RDC Master */ + kRDC_Master_M4 = 1U, /**< ARM Cortex-M4 RDC Master */ + kRDC_Master_PCIE1 = 2U, /**< PCIE1 RDC Master */ + kRDC_Master_PCIE2 = 3U, /**< PCIE2 RDC Master */ + kRDC_Master_VPU = 4U, /**< VPU RDC Master */ + kRDC_Master_LCDIF = 5U, /**< LCDIF RDC Master */ + kRDC_Master_CSI1 = 6U, /**< CSI1 PORT RDC Master */ + kRDC_Master_CSI2 = 7U, /**< CSI2 RDC Master */ + kRDC_Master_Coresight = 8U, /**< CORESIGHT RDC Master */ + kRDC_Master_DAP = 9U, /**< DAP RDC Master */ + kRDC_Master_CAAM = 10U, /**< CAAM RDC Master */ + kRDC_Master_SDMA1_PERIPH = 11U, /**< SDMA1 PERIPHERAL RDC Master */ + kRDC_Master_SDMA1_BURST = 12U, /**< SDMA1 BURST RDC Master */ + kRDC_Master_APBHDMA = 13U, /**< APBH DMA RDC Master */ + kRDC_Master_RAWNAND = 14U, /**< RAW NAND RDC Master */ + kRDC_Master_USDHC1 = 15U, /**< USDHC1 RDC Master */ + kRDC_Master_USDHC2 = 16U, /**< USDHC2 RDC Master */ + kRDC_Master_DP = 17U, /**< DP RDC Master */ + kRDC_Master_GPU = 18U, /**< GPU RDC Master */ + kRDC_Master_USB1 = 19U, /**< USB1 RDC Master */ + kRDC_Master_USB2 = 20U, /**< USB2 RDC Master */ + kRDC_Master_TESTPORT = 21U, /**< TESTPORT RDC Master */ + kRDC_Master_ENET1TX = 22U, /**< ENET1 TX RDC Master */ + kRDC_Master_ENET1RX = 23U, /**< ENET1 RX RDC Master */ + kRDC_Master_SDMA2_PERIPH = 24U, /**< SDMA2 PERIPH RDC Master */ + kRDC_Master_SDMA2_BURST = 24U, /**< SDMA2 BURST RDC Master */ + kRDC_Master_SDMA2_SPDA2 = 24U, /**< SDMA2 to SPDA2 RDC Master */ + kRDC_Master_SDMA1_SPBA1 = 26U, /**< SDMA1 to SPBA1 RDC Master */ +} rdc_master_t; + +typedef enum _rdc_mem +{ + kRDC_Mem_MRC0_0 = 0U, /**< MMDC/DRAM. Region resolution 4KB. */ + kRDC_Mem_MRC0_1 = 1U, + kRDC_Mem_MRC0_2 = 2U, + kRDC_Mem_MRC0_3 = 3U, + kRDC_Mem_MRC0_4 = 4U, + kRDC_Mem_MRC0_5 = 5U, + kRDC_Mem_MRC0_6 = 6U, + kRDC_Mem_MRC0_7 = 7U, + kRDC_Mem_MRC1_0 = 8U, /**< PCIE2. Region resolution 4KB. */ + kRDC_Mem_MRC1_1 = 9U, + kRDC_Mem_MRC1_2 = 10U, + kRDC_Mem_MRC1_3 = 11U, + kRDC_Mem_MRC2_0 = 12U, /**< QSPI. Region resolution 4KB. */ + kRDC_Mem_MRC2_1 = 13U, + kRDC_Mem_MRC2_2 = 14U, + kRDC_Mem_MRC2_3 = 15U, + kRDC_Mem_MRC2_4 = 16U, + kRDC_Mem_MRC2_5 = 17U, + kRDC_Mem_MRC2_6 = 18U, + kRDC_Mem_MRC2_7 = 19U, + kRDC_Mem_MRC3_0 = 20U, /**< PCIE1. Region resolution 4KB. */ + kRDC_Mem_MRC3_1 = 21U, + kRDC_Mem_MRC3_2 = 22U, + kRDC_Mem_MRC3_3 = 23U, + kRDC_Mem_MRC4_0 = 24U, /**< OCRAM. Region resolution 128B. */ + kRDC_Mem_MRC4_1 = 25U, + kRDC_Mem_MRC4_2 = 26U, + kRDC_Mem_MRC4_3 = 27U, + kRDC_Mem_MRC4_4 = 28U, + kRDC_Mem_MRC5_0 = 29U, /**< OCRAM_S. Region resolution 128B. */ + kRDC_Mem_MRC5_1 = 30U, + kRDC_Mem_MRC5_2 = 31U, + kRDC_Mem_MRC5_3 = 32U, + kRDC_Mem_MRC5_4 = 33U, + kRDC_Mem_MRC6_0 = 34U, /**< TCM. Region resolution 128B. */ + kRDC_Mem_MRC6_1 = 35U, + kRDC_Mem_MRC6_2 = 36U, + kRDC_Mem_MRC6_3 = 37U, + kRDC_Mem_MRC6_4 = 38U, + kRDC_Mem_MRC7_0 = 39U, /**< GIC. Region resolution 4KB. */ + kRDC_Mem_MRC7_1 = 40U, + kRDC_Mem_MRC7_2 = 41U, + kRDC_Mem_MRC7_3 = 42U, + kRDC_Mem_MRC8_0 = 43U, /**< USBMIX. Region resolution 4KB. */ + kRDC_Mem_MRC8_1 = 44U, + kRDC_Mem_MRC8_2 = 45U, + kRDC_Mem_MRC8_3 = 46U, + kRDC_Mem_MRC9_0 = 47U, /**< GPU. Region resolution 4KB. */ + kRDC_Mem_MRC9_1 = 48U, + kRDC_Mem_MRC9_2 = 49U, + kRDC_Mem_MRC9_3 = 50U, + kRDC_Mem_MRC10_0 = 51U, /**< VPU(Decoder). Region resolution 4KB. */ + kRDC_Mem_MRC10_1 = 52U, + kRDC_Mem_MRC10_2 = 53U, + kRDC_Mem_MRC10_3 = 54U, + kRDC_Mem_MRC11_0 = 55U, /**< DEBUG(DAP). Region resolution 4KB. */ + kRDC_Mem_MRC11_1 = 56U, + kRDC_Mem_MRC11_2 = 57U, + kRDC_Mem_MRC11_3 = 58U, + kRDC_Mem_MRC12_0 = 59U, /**< DDRC(REG). Region resolution 4KB. */ + kRDC_Mem_MRC12_1 = 60U, + kRDC_Mem_MRC12_2 = 61U, + kRDC_Mem_MRC12_3 = 62U, + kRDC_Mem_MRC12_4 = 63U, +} rdc_mem_t; + +typedef enum _rdc_periph +{ + kRDC_Periph_GPIO1 = 0U, /**< GPIO1 RDC Peripheral */ + kRDC_Periph_GPIO2 = 1U, /**< GPIO2 RDC Peripheral */ + kRDC_Periph_GPIO3 = 2U, /**< GPIO3 RDC Peripheral */ + kRDC_Periph_GPIO4 = 3U, /**< GPIO4 RDC Peripheral */ + kRDC_Periph_GPIO5 = 4U, /**< GPIO5 RDC Peripheral */ + kRDC_Periph_ANA_TSENSOR = 6U, /**< ANA_TSENSOR RDC Peripheral */ + kRDC_Periph_ANA_OSC = 7U, /**< ANA_OSC RDC Peripheral */ + kRDC_Periph_WDOG1 = 8U, /**< WDOG1 RDC Peripheral */ + kRDC_Periph_WDOG2 = 9U, /**< WDOG2 RDC Peripheral */ + kRDC_Periph_WDOG3 = 10U, /**< WDOG3 RDC Peripheral */ + kRDC_Periph_SDMA2 = 12U, /**< SDMA2 RDC Peripheral */ + kRDC_Periph_GPT1 = 13U, /**< GPT1 RDC Peripheral */ + kRDC_Periph_GPT2 = 14U, /**< GPT2 RDC Peripheral */ + kRDC_Periph_GPT3 = 15U, /**< GPT3 RDC Peripheral */ + kRDC_Periph_ROMCP = 17U, /**< ROMCP RDC Peripheral */ + kRDC_Periph_LCDIF = 18U, /**< LCDIF RDC Peripheral */ + kRDC_Periph_IOMUXC = 19U, /**< IOMUXC RDC Peripheral */ + kRDC_Periph_IOMUXC_GPR = 20U, /**< IOMUXC_GPR RDC Peripheral */ + kRDC_Periph_OCOTP_CTRL = 21U, /**< OCOTP_CTRL RDC Peripheral */ + kRDC_Periph_ANA_PLL = 22U, /**< ANA_PLL RDC Peripheral */ + kRDC_Periph_SNVS_HP = 23U, /**< SNVS_HP GPR RDC Peripheral */ + kRDC_Periph_CCM = 24U, /**< CCM RDC Peripheral */ + kRDC_Periph_SRC = 25U, /**< SRC RDC Peripheral */ + kRDC_Periph_GPC = 26U, /**< GPC RDC Peripheral */ + kRDC_Periph_SEMAPHORE1 = 27U, /**< SEMAPHORE1 RDC Peripheral */ + kRDC_Periph_SEMAPHORE2 = 28U, /**< SEMAPHORE2 RDC Peripheral */ + kRDC_Periph_RDC = 29U, /**< RDC RDC Peripheral */ + kRDC_Periph_CSU = 30U, /**< CSU RDC Peripheral */ + kRDC_Periph_DC_MST0 = 32U, /**< DC_MST0 RDC Peripheral */ + kRDC_Periph_DC_MST1 = 33U, /**< DC_MST1 RDC Peripheral */ + kRDC_Periph_DC_MST2 = 34U, /**< DC_MST2 RDC Peripheral */ + kRDC_Periph_DC_MST3 = 35U, /**< DC_MST3 RDC Peripheral */ + kRDC_Periph_HDMI_SEC = 36U, /**< HDMI_SEC RDC Peripheral */ + kRDC_Periph_PWM1 = 38U, /**< PWM1 RDC Peripheral */ + kRDC_Periph_PWM2 = 39U, /**< PWM2 RDC Peripheral */ + kRDC_Periph_PWM3 = 40U, /**< PWM3 RDC Peripheral */ + kRDC_Periph_PWM4 = 41U, /**< PWM4 RDC Peripheral */ + kRDC_Periph_SYS_COUNTER_RD = 42U, /**< System counter read RDC Peripheral */ + kRDC_Periph_SYS_COUNTER_CMP = 43U, /**< System counter compare RDC Peripheral */ + kRDC_Periph_SYS_COUNTER_CTRL = 44U, /**< System counter control RDC Peripheral */ + kRDC_Periph_HDMI_CTRL = 45U, /**< HDMI_CTRL RDC Peripheral */ + kRDC_Periph_GPT6 = 46U, /**< GPT6 RDC Peripheral */ + kRDC_Periph_GPT5 = 47U, /**< GPT5 RDC Peripheral */ + kRDC_Periph_GPT4 = 48U, /**< GPT4 RDC Peripheral */ + kRDC_Periph_TZASC = 56U, /**< TZASC RDC Peripheral */ + kRDC_Periph_MTR = 59U, /**< MTR RDC Peripheral */ + kRDC_Periph_PERFMON1 = 60U, /**< PERFMON1 RDC Peripheral */ + kRDC_Periph_PERFMON2 = 61U, /**< PERFMON2 RDC Peripheral */ + kRDC_Periph_PLATFORM_CTRL = 62U, /**< PLATFORM_CTRL RDC Peripheral */ + kRDC_Periph_QOSC = 63U, /**< QOSC RDC Peripheral */ + kRDC_Periph_MIPI_PHY = 64U, /**< MIPI_PHY RDC Peripheral */ + kRDC_Periph_MIPI_DSI = 65U, /**< MIPI_DSI RDC Peripheral */ + kRDC_Periph_I2C1 = 66U, /**< I2C1 RDC Peripheral */ + kRDC_Periph_I2C2 = 67U, /**< I2C2 RDC Peripheral */ + kRDC_Periph_I2C3 = 68U, /**< I2C3 RDC Peripheral */ + kRDC_Periph_I2C4 = 69U, /**< I2C4 RDC Peripheral */ + kRDC_Periph_UART4 = 70U, /**< UART4 RDC Peripheral */ + kRDC_Periph_MIPI_CSI1 = 71U, /**< MIPI_CSI1 RDC Peripheral */ + kRDC_Periph_MIPI_CSI_PHY1 = 72U, /**< MIPI_CSI_PHY1 RDC Peripheral */ + kRDC_Periph_CSI1 = 73U, /**< CSI1 RDC Peripheral */ + kRDC_Periph_MU_A = 74U, /**< MU_A RDC Peripheral */ + kRDC_Periph_MU_B = 75U, /**< MU_B RDC Peripheral */ + kRDC_Periph_SEMAPHORE_HS = 76U, /**< SEMAPHORE_HS RDC Peripheral */ + kRDC_Periph_SAI1 = 78U, /**< SAI1 RDC Peripheral */ + kRDC_Periph_SAI6 = 80U, /**< SAI6 RDC Peripheral */ + kRDC_Periph_SAI5 = 81U, /**< SAI5 RDC Peripheral */ + kRDC_Periph_SAI4 = 82U, /**< SAI4 RDC Peripheral */ + kRDC_Periph_USDHC1 = 84U, /**< USDHC1 RDC Peripheral */ + kRDC_Periph_USDHC2 = 85U, /**< USDHC2 RDC Peripheral */ + kRDC_Periph_MIPI_CSI2 = 86U, /**< MIPI_CSI2 RDC Peripheral */ + kRDC_Periph_MIPI_CSI_PHY2 = 87U, /**< MIPI_CSI_PHY2 RDC Peripheral */ + kRDC_Periph_CSI2 = 88U, /**< CSI2 RDC Peripheral */ + kRDC_Periph_SPBA2 = 90U, /**< SPBA2 RDC Peripheral */ + kRDC_Periph_QSPI = 91U, /**< QSPI RDC Peripheral */ + kRDC_Periph_SDMA1 = 93U, /**< SDMA1 RDC Peripheral */ + kRDC_Periph_ENET1 = 94U, /**< ENET1 RDC Peripheral */ + kRDC_Periph_SPDIF1 = 97U, /**< SPDIF1 RDC Peripheral */ + kRDC_Periph_ECSPI1 = 98U, /**< ECSPI1 RDC Peripheral */ + kRDC_Periph_ECSPI2 = 99U, /**< ECSPI2 RDC Peripheral */ + kRDC_Periph_ECSPI3 = 100U, /**< ECSPI3 RDC Peripheral */ + kRDC_Periph_UART1 = 102U, /**< UART1 RDC Peripheral */ + kRDC_Periph_UART3 = 104U, /**< UART3 RDC Peripheral */ + kRDC_Periph_UART2 = 105U, /**< UART2 RDC Peripheral */ + kRDC_Periph_SPDIF2 = 106U, /**< SPDIF2 RDC Peripheral */ + kRDC_Periph_SAI2 = 107U, /**< SAI2 RDC Peripheral */ + kRDC_Periph_SAI3 = 108U, /**< SAI3 RDC Peripheral */ + kRDC_Periph_SPBA1 = 111U, /**< SPBA1 RDC Peripheral */ + kRDC_Periph_CAAM = 114U, /**< CAAM RDC Peripheral */ +} rdc_periph_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer + * @{ + */ + +/** AIPSTZ - Register Layout Typedef */ +typedef struct { + __IO uint32_t MPR; /**< MPR, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t OPACR; /**< OPACR, offset: 0x40 */ + __IO uint32_t OPACR1; /**< OPACR1, offset: 0x44 */ + __IO uint32_t OPACR2; /**< OPACR2, offset: 0x48 */ + __IO uint32_t OPACR3; /**< OPACR3, offset: 0x4C */ + __IO uint32_t OPACR4; /**< OPACR4, offset: 0x50 */ +} AIPSTZ_Type; + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks + * @{ + */ + +/*! @name MPR - MPR */ +/*! @{ */ + +#define AIPSTZ_MPR_MPROT5_MASK (0xF00U) +#define AIPSTZ_MPR_MPROT5_SHIFT (8U) +/*! MPROT5 - MPROT5. + */ +#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) + +#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) +#define AIPSTZ_MPR_MPROT3_SHIFT (16U) +/*! MPROT3 - MPROT3. + */ +#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) + +#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) +#define AIPSTZ_MPR_MPROT2_SHIFT (20U) +/*! MPROT2 - MPROT2. + */ +#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) + +#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) +#define AIPSTZ_MPR_MPROT1_SHIFT (24U) +/*! MPROT1 - MPROT1. + */ +#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) + +#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) +#define AIPSTZ_MPR_MPROT0_SHIFT (28U) +/*! MPROT0 - MPROT0. + */ +#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) +/*! @} */ + +/*! @name OPACR - OPACR */ +/*! @{ */ + +#define AIPSTZ_OPACR_OPAC7_MASK (0xFU) +#define AIPSTZ_OPACR_OPAC7_SHIFT (0U) +/*! OPAC7 - OPAC7. + */ +#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) + +#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) +#define AIPSTZ_OPACR_OPAC6_SHIFT (4U) +/*! OPAC6 - OPAC6. + */ +#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) + +#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) +#define AIPSTZ_OPACR_OPAC5_SHIFT (8U) +/*! OPAC5 - OPAC5. + */ +#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) + +#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) +#define AIPSTZ_OPACR_OPAC4_SHIFT (12U) +/*! OPAC4 - OPAC4. + */ +#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) + +#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) +#define AIPSTZ_OPACR_OPAC3_SHIFT (16U) +/*! OPAC3 - OPAC3. + */ +#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) + +#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) +#define AIPSTZ_OPACR_OPAC2_SHIFT (20U) +/*! OPAC2 - OPAC2. + */ +#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) + +#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) +#define AIPSTZ_OPACR_OPAC1_SHIFT (24U) +/*! OPAC1 - OPAC1. + */ +#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) + +#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) +#define AIPSTZ_OPACR_OPAC0_SHIFT (28U) +/*! OPAC0 - OPAC0. + */ +#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) +/*! @} */ + +/*! @name OPACR1 - OPACR1 */ +/*! @{ */ + +#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) +#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) +/*! OPAC15 - OPAC15. + */ +#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) + +#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) +#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) +/*! OPAC14 - OPAC14. + */ +#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) + +#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) +#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) +/*! OPAC13 - OPAC13. + */ +#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) + +#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) +#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) +/*! OPAC12 - OPAC12. + */ +#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) + +#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) +#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) +/*! OPAC11 - OPAC11. + */ +#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) + +#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) +#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) +/*! OPAC10 - OPAC10. + */ +#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) + +#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) +#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) +/*! OPAC9 - OPAC9. + */ +#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) + +#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) +#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) +/*! OPAC8 - OPAC8. + */ +#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) +/*! @} */ + +/*! @name OPACR2 - OPACR2 */ +/*! @{ */ + +#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) +#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) +/*! OPAC23 - OPAC23. + */ +#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) + +#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) +#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) +/*! OPAC22 - OPAC22. + */ +#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) + +#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) +#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) +/*! OPAC21 - OPAC21. + */ +#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) + +#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) +#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) +/*! OPAC20 - OPAC20. + */ +#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) + +#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) +#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) +/*! OPAC19 - OPAC19. + */ +#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) + +#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) +#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) +/*! OPAC18 - OPAC18. + */ +#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) + +#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) +#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) +/*! OPAC17 - OPAC17. + */ +#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) + +#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) +#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) +/*! OPAC16 - OPAC16. + */ +#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) +/*! @} */ + +/*! @name OPACR3 - OPACR3 */ +/*! @{ */ + +#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) +#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) +/*! OPAC31 - OPAC31. + */ +#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) + +#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) +#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) +/*! OPAC30 - OPAC30. + */ +#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) + +#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) +#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) +/*! OPAC29 - OPAC29. + */ +#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) + +#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) +#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) +/*! OPAC28 - OPAC28. + */ +#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) + +#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) +#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) +/*! OPAC27 - OPAC27. + */ +#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) + +#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) +#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) +/*! OPAC26 - OPAC26. + */ +#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) + +#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) +#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) +/*! OPAC25 - OPAC25. + */ +#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) + +#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) +#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) +/*! OPAC24 - OPAC24. + */ +#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) +/*! @} */ + +/*! @name OPACR4 - OPACR4 */ +/*! @{ */ + +#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) +#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) +/*! OPAC33 - OPAC33. + */ +#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) + +#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) +#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) +/*! OPAC32 - OPAC32. + */ +#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AIPSTZ_Register_Masks */ + + +/* AIPSTZ - Peripheral instance base addresses */ +/** Peripheral AIPSTZ1 base address */ +#define AIPSTZ1_BASE (0x301F0000u) +/** Peripheral AIPSTZ1 base pointer */ +#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) +/** Peripheral AIPSTZ2 base address */ +#define AIPSTZ2_BASE (0x305F0000u) +/** Peripheral AIPSTZ2 base pointer */ +#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) +/** Peripheral AIPSTZ3 base address */ +#define AIPSTZ3_BASE (0x309F0000u) +/** Peripheral AIPSTZ3 base pointer */ +#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) +/** Peripheral AIPSTZ4 base address */ +#define AIPSTZ4_BASE (0x32DF0000u) +/** Peripheral AIPSTZ4 base pointer */ +#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE) +/** Array initializer of AIPSTZ peripheral base addresses */ +#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE } +/** Array initializer of AIPSTZ peripheral base pointers */ +#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 } + +/*! + * @} + */ /* end of group AIPSTZ_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- APBH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer + * @{ + */ + +/** APBH - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */ + __IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */ + __IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */ + __IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */ + __IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */ + __IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */ + __IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */ + __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */ + __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */ + __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */ + __I uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */ + uint8_t RESERVED_2[156]; + __I uint32_t CH0_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x100 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CH0_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x110 */ + uint8_t RESERVED_4[12]; + __I uint32_t CH0_CMD; /**< APBH DMA Channel n Command Register, offset: 0x120 */ + uint8_t RESERVED_5[12]; + __I uint32_t CH0_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x130 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CH0_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x140 */ + uint8_t RESERVED_7[12]; + __I uint32_t CH0_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x150 */ + uint8_t RESERVED_8[12]; + __I uint32_t CH0_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x160 */ + uint8_t RESERVED_9[12]; + __I uint32_t CH1_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x170 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CH1_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x180 */ + uint8_t RESERVED_11[12]; + __I uint32_t CH1_CMD; /**< APBH DMA Channel n Command Register, offset: 0x190 */ + uint8_t RESERVED_12[12]; + __I uint32_t CH1_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x1A0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CH1_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x1B0 */ + uint8_t RESERVED_14[12]; + __I uint32_t CH1_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1C0 */ + uint8_t RESERVED_15[12]; + __I uint32_t CH1_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1D0 */ + uint8_t RESERVED_16[12]; + __I uint32_t CH2_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x1E0 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH2_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x1F0 */ + uint8_t RESERVED_18[12]; + __I uint32_t CH2_CMD; /**< APBH DMA Channel n Command Register, offset: 0x200 */ + uint8_t RESERVED_19[12]; + __I uint32_t CH2_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x210 */ + uint8_t RESERVED_20[12]; + __IO uint32_t CH2_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x220 */ + uint8_t RESERVED_21[12]; + __I uint32_t CH2_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x230 */ + uint8_t RESERVED_22[12]; + __I uint32_t CH2_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x240 */ + uint8_t RESERVED_23[12]; + __I uint32_t CH3_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x250 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CH3_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x260 */ + uint8_t RESERVED_25[12]; + __I uint32_t CH3_CMD; /**< APBH DMA Channel n Command Register, offset: 0x270 */ + uint8_t RESERVED_26[12]; + __I uint32_t CH3_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x280 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CH3_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x290 */ + uint8_t RESERVED_28[12]; + __I uint32_t CH3_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2A0 */ + uint8_t RESERVED_29[12]; + __I uint32_t CH3_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2B0 */ + uint8_t RESERVED_30[12]; + __I uint32_t CH4_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x2C0 */ + uint8_t RESERVED_31[12]; + __IO uint32_t CH4_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x2D0 */ + uint8_t RESERVED_32[12]; + __I uint32_t CH4_CMD; /**< APBH DMA Channel n Command Register, offset: 0x2E0 */ + uint8_t RESERVED_33[12]; + __I uint32_t CH4_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x2F0 */ + uint8_t RESERVED_34[12]; + __IO uint32_t CH4_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x300 */ + uint8_t RESERVED_35[12]; + __I uint32_t CH4_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x310 */ + uint8_t RESERVED_36[12]; + __I uint32_t CH4_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x320 */ + uint8_t RESERVED_37[12]; + __I uint32_t CH5_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x330 */ + uint8_t RESERVED_38[12]; + __IO uint32_t CH5_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x340 */ + uint8_t RESERVED_39[12]; + __I uint32_t CH5_CMD; /**< APBH DMA Channel n Command Register, offset: 0x350 */ + uint8_t RESERVED_40[12]; + __I uint32_t CH5_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x360 */ + uint8_t RESERVED_41[12]; + __IO uint32_t CH5_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x370 */ + uint8_t RESERVED_42[12]; + __I uint32_t CH5_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x380 */ + uint8_t RESERVED_43[12]; + __I uint32_t CH5_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x390 */ + uint8_t RESERVED_44[12]; + __I uint32_t CH6_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x3A0 */ + uint8_t RESERVED_45[12]; + __IO uint32_t CH6_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x3B0 */ + uint8_t RESERVED_46[12]; + __I uint32_t CH6_CMD; /**< APBH DMA Channel n Command Register, offset: 0x3C0 */ + uint8_t RESERVED_47[12]; + __I uint32_t CH6_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x3D0 */ + uint8_t RESERVED_48[12]; + __IO uint32_t CH6_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x3E0 */ + uint8_t RESERVED_49[12]; + __I uint32_t CH6_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x3F0 */ + uint8_t RESERVED_50[12]; + __I uint32_t CH6_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x400 */ + uint8_t RESERVED_51[12]; + __I uint32_t CH7_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x410 */ + uint8_t RESERVED_52[12]; + __IO uint32_t CH7_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x420 */ + uint8_t RESERVED_53[12]; + __I uint32_t CH7_CMD; /**< APBH DMA Channel n Command Register, offset: 0x430 */ + uint8_t RESERVED_54[12]; + __I uint32_t CH7_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x440 */ + uint8_t RESERVED_55[12]; + __IO uint32_t CH7_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x450 */ + uint8_t RESERVED_56[12]; + __I uint32_t CH7_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x460 */ + uint8_t RESERVED_57[12]; + __I uint32_t CH7_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x470 */ + uint8_t RESERVED_58[12]; + __I uint32_t CH8_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x480 */ + uint8_t RESERVED_59[12]; + __IO uint32_t CH8_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x490 */ + uint8_t RESERVED_60[12]; + __I uint32_t CH8_CMD; /**< APBH DMA Channel n Command Register, offset: 0x4A0 */ + uint8_t RESERVED_61[12]; + __I uint32_t CH8_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x4B0 */ + uint8_t RESERVED_62[12]; + __IO uint32_t CH8_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x4C0 */ + uint8_t RESERVED_63[12]; + __I uint32_t CH8_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4D0 */ + uint8_t RESERVED_64[12]; + __I uint32_t CH8_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4E0 */ + uint8_t RESERVED_65[12]; + __I uint32_t CH9_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x4F0 */ + uint8_t RESERVED_66[12]; + __IO uint32_t CH9_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x500 */ + uint8_t RESERVED_67[12]; + __I uint32_t CH9_CMD; /**< APBH DMA Channel n Command Register, offset: 0x510 */ + uint8_t RESERVED_68[12]; + __I uint32_t CH9_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x520 */ + uint8_t RESERVED_69[12]; + __IO uint32_t CH9_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x530 */ + uint8_t RESERVED_70[12]; + __I uint32_t CH9_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x540 */ + uint8_t RESERVED_71[12]; + __I uint32_t CH9_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x550 */ + uint8_t RESERVED_72[12]; + __I uint32_t CH10_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x560 */ + uint8_t RESERVED_73[12]; + __IO uint32_t CH10_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x570 */ + uint8_t RESERVED_74[12]; + __I uint32_t CH10_CMD; /**< APBH DMA Channel n Command Register, offset: 0x580 */ + uint8_t RESERVED_75[12]; + __I uint32_t CH10_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x590 */ + uint8_t RESERVED_76[12]; + __IO uint32_t CH10_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x5A0 */ + uint8_t RESERVED_77[12]; + __I uint32_t CH10_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5B0 */ + uint8_t RESERVED_78[12]; + __I uint32_t CH10_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5C0 */ + uint8_t RESERVED_79[12]; + __I uint32_t CH11_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x5D0 */ + uint8_t RESERVED_80[12]; + __IO uint32_t CH11_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x5E0 */ + uint8_t RESERVED_81[12]; + __I uint32_t CH11_CMD; /**< APBH DMA Channel n Command Register, offset: 0x5F0 */ + uint8_t RESERVED_82[12]; + __I uint32_t CH11_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x600 */ + uint8_t RESERVED_83[12]; + __IO uint32_t CH11_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x610 */ + uint8_t RESERVED_84[12]; + __I uint32_t CH11_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x620 */ + uint8_t RESERVED_85[12]; + __I uint32_t CH11_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x630 */ + uint8_t RESERVED_86[12]; + __I uint32_t CH12_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x640 */ + uint8_t RESERVED_87[12]; + __IO uint32_t CH12_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x650 */ + uint8_t RESERVED_88[12]; + __I uint32_t CH12_CMD; /**< APBH DMA Channel n Command Register, offset: 0x660 */ + uint8_t RESERVED_89[12]; + __I uint32_t CH12_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x670 */ + uint8_t RESERVED_90[12]; + __IO uint32_t CH12_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x680 */ + uint8_t RESERVED_91[12]; + __I uint32_t CH12_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x690 */ + uint8_t RESERVED_92[12]; + __I uint32_t CH12_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x6A0 */ + uint8_t RESERVED_93[12]; + __I uint32_t CH13_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x6B0 */ + uint8_t RESERVED_94[12]; + __IO uint32_t CH13_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x6C0 */ + uint8_t RESERVED_95[12]; + __I uint32_t CH13_CMD; /**< APBH DMA Channel n Command Register, offset: 0x6D0 */ + uint8_t RESERVED_96[12]; + __I uint32_t CH13_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x6E0 */ + uint8_t RESERVED_97[12]; + __IO uint32_t CH13_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x6F0 */ + uint8_t RESERVED_98[12]; + __I uint32_t CH13_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x700 */ + uint8_t RESERVED_99[12]; + __I uint32_t CH13_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x710 */ + uint8_t RESERVED_100[12]; + __I uint32_t CH14_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x720 */ + uint8_t RESERVED_101[12]; + __IO uint32_t CH14_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x730 */ + uint8_t RESERVED_102[12]; + __I uint32_t CH14_CMD; /**< APBH DMA Channel n Command Register, offset: 0x740 */ + uint8_t RESERVED_103[12]; + __I uint32_t CH14_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x750 */ + uint8_t RESERVED_104[12]; + __IO uint32_t CH14_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x760 */ + uint8_t RESERVED_105[12]; + __I uint32_t CH14_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x770 */ + uint8_t RESERVED_106[12]; + __I uint32_t CH14_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x780 */ + uint8_t RESERVED_107[12]; + __I uint32_t CH15_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x790 */ + uint8_t RESERVED_108[12]; + __IO uint32_t CH15_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x7A0 */ + uint8_t RESERVED_109[12]; + __I uint32_t CH15_CMD; /**< APBH DMA Channel n Command Register, offset: 0x7B0 */ + uint8_t RESERVED_110[12]; + __I uint32_t CH15_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x7C0 */ + uint8_t RESERVED_111[12]; + __IO uint32_t CH15_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x7D0 */ + uint8_t RESERVED_112[12]; + __I uint32_t CH15_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7E0 */ + uint8_t RESERVED_113[12]; + __I uint32_t CH15_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7F0 */ + uint8_t RESERVED_114[12]; + __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */ +} APBH_Type; + +/* ---------------------------------------------------------------------------- + -- APBH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Register_Masks APBH Register Masks + * @{ + */ + +/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */ +/*! @{ */ + +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U) +/*! CLKGATE_CHANNEL + * 0b0000000000000001..NAND0 + * 0b0000000000000010..NAND1 + * 0b0000000000000100..NAND2 + * 0b0000000000001000..NAND3 + * 0b0000000000010000..NAND4 + * 0b0000000000100000..NAND5 + * 0b0000000001000000..NAND6 + * 0b0000000010000000..NAND7 + * 0b0000000100000000..SSP + */ +#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK) + +#define APBH_CTRL0_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_RSVD0_SHIFT (16U) +#define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK) + +#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK) + +#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK) + +#define APBH_CTRL0_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK) + +#define APBH_CTRL0_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_SFTRST_SHIFT (31U) +#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */ +/*! @{ */ + +#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U) +/*! CLKGATE_CHANNEL + * 0b0000000000000001..NAND0 + * 0b0000000000000010..NAND1 + * 0b0000000000000100..NAND2 + * 0b0000000000001000..NAND3 + * 0b0000000000010000..NAND4 + * 0b0000000000100000..NAND5 + * 0b0000000001000000..NAND6 + * 0b0000000010000000..NAND7 + * 0b0000000100000000..SSP + */ +#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK) + +#define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_SET_RSVD0_SHIFT (16U) +#define APBH_CTRL0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK) + +#define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_SET_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK) + +#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_SET_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK) + +#define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_SET_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK) + +#define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_SET_SFTRST_SHIFT (31U) +#define APBH_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */ +/*! @{ */ + +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U) +/*! CLKGATE_CHANNEL + * 0b0000000000000001..NAND0 + * 0b0000000000000010..NAND1 + * 0b0000000000000100..NAND2 + * 0b0000000000001000..NAND3 + * 0b0000000000010000..NAND4 + * 0b0000000000100000..NAND5 + * 0b0000000001000000..NAND6 + * 0b0000000010000000..NAND7 + * 0b0000000100000000..SSP + */ +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK) + +#define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_CLR_RSVD0_SHIFT (16U) +#define APBH_CTRL0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK) + +#define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_CLR_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK) + +#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_CLR_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK) + +#define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK) + +#define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_CLR_SFTRST_SHIFT (31U) +#define APBH_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */ +/*! @{ */ + +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U) +/*! CLKGATE_CHANNEL + * 0b0000000000000001..NAND0 + * 0b0000000000000010..NAND1 + * 0b0000000000000100..NAND2 + * 0b0000000000001000..NAND3 + * 0b0000000000010000..NAND4 + * 0b0000000000100000..NAND5 + * 0b0000000001000000..NAND6 + * 0b0000000010000000..NAND7 + * 0b0000000100000000..SSP + */ +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK) + +#define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_TOG_RSVD0_SHIFT (16U) +#define APBH_CTRL0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK) + +#define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_TOG_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK) + +#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_TOG_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK) + +#define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK) + +#define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_TOG_SFTRST_SHIFT (31U) +#define APBH_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */ +/*! @{ */ + +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK) +/*! @} */ + +/*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */ +/*! @{ */ + +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK) +/*! @} */ + +/*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */ +/*! @{ */ + +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK) +/*! @} */ + +/*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */ +/*! @{ */ + +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK) + +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK) + +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK) +/*! @} */ + +/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */ +/*! @{ */ + +#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U) +/*! CH0_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U) +/*! CH1_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U) +/*! CH2_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U) +/*! CH3_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U) +/*! CH4_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U) +/*! CH5_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U) +/*! CH6_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U) +/*! CH7_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U) +/*! CH8_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U) +/*! CH9_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U) +/*! CH10_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U) +/*! CH11_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U) +/*! CH12_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U) +/*! CH13_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U) +/*! CH14_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U) +/*! CH15_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK) +/*! @} */ + +/*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */ +/*! @{ */ + +#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK) + +#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U) +/*! CH0_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U) +/*! CH1_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U) +/*! CH2_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U) +/*! CH3_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U) +/*! CH4_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U) +/*! CH5_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U) +/*! CH6_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U) +/*! CH7_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U) +/*! CH8_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U) +/*! CH9_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U) +/*! CH10_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U) +/*! CH11_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U) +/*! CH12_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U) +/*! CH13_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U) +/*! CH14_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK) + +#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U) +/*! CH15_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK) +/*! @} */ + +/*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */ +/*! @{ */ + +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK) + +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U) +/*! CH0_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U) +/*! CH1_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U) +/*! CH2_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U) +/*! CH3_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U) +/*! CH4_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U) +/*! CH5_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U) +/*! CH6_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U) +/*! CH7_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U) +/*! CH8_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U) +/*! CH9_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U) +/*! CH10_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U) +/*! CH11_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U) +/*! CH12_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U) +/*! CH13_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U) +/*! CH14_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK) + +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U) +/*! CH15_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK) +/*! @} */ + +/*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */ +/*! @{ */ + +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK) + +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U) +/*! CH0_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U) +/*! CH1_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U) +/*! CH2_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U) +/*! CH3_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U) +/*! CH4_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U) +/*! CH5_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U) +/*! CH6_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U) +/*! CH7_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U) +/*! CH8_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U) +/*! CH9_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U) +/*! CH10_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U) +/*! CH11_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U) +/*! CH12_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U) +/*! CH13_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U) +/*! CH14_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK) + +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U) +/*! CH15_ERROR_STATUS + * 0b0..An early termination from the device causes error IRQ. + * 0b1..An AHB bus error causes error IRQ. + */ +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK) +/*! @} */ + +/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */ +/*! @{ */ + +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U) +/*! FREEZE_CHANNEL + * 0b0000000000000001..NAND0 + * 0b0000000000000010..NAND1 + * 0b0000000000000100..NAND2 + * 0b0000000000001000..NAND3 + * 0b0000000000010000..NAND4 + * 0b0000000000100000..NAND5 + * 0b0000000001000000..NAND6 + * 0b0000000010000000..NAND7 + * 0b0000000100000000..SSP + */ +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK) + +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U) +/*! RESET_CHANNEL + * 0b0000000000000001..NAND0 + * 0b0000000000000010..NAND1 + * 0b0000000000000100..NAND2 + * 0b0000000000001000..NAND3 + * 0b0000000000010000..NAND4 + * 0b0000000000100000..NAND5 + * 0b0000000001000000..NAND6 + * 0b0000000010000000..NAND7 + * 0b0000000100000000..SSP + */ +#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK) +/*! @} */ + +/*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */ +/*! @{ */ + +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U) +/*! FREEZE_CHANNEL + * 0b0000000000000001..NAND0 + * 0b0000000000000010..NAND1 + * 0b0000000000000100..NAND2 + * 0b0000000000001000..NAND3 + * 0b0000000000010000..NAND4 + * 0b0000000000100000..NAND5 + * 0b0000000001000000..NAND6 + * 0b0000000010000000..NAND7 + * 0b0000000100000000..SSP + */ +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK) + +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U) +/*! RESET_CHANNEL + * 0b0000000000000001..NAND0 + * 0b0000000000000010..NAND1 + * 0b0000000000000100..NAND2 + * 0b0000000000001000..NAND3 + * 0b0000000000010000..NAND4 + * 0b0000000000100000..NAND5 + * 0b0000000001000000..NAND6 + * 0b0000000010000000..NAND7 + * 0b0000000100000000..SSP + */ +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK) +/*! @} */ + +/*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */ +/*! @{ */ + +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U) +/*! FREEZE_CHANNEL + * 0b0000000000000001..NAND0 + * 0b0000000000000010..NAND1 + * 0b0000000000000100..NAND2 + * 0b0000000000001000..NAND3 + * 0b0000000000010000..NAND4 + * 0b0000000000100000..NAND5 + * 0b0000000001000000..NAND6 + * 0b0000000010000000..NAND7 + * 0b0000000100000000..SSP + */ +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK) + +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U) +/*! RESET_CHANNEL + * 0b0000000000000001..NAND0 + * 0b0000000000000010..NAND1 + * 0b0000000000000100..NAND2 + * 0b0000000000001000..NAND3 + * 0b0000000000010000..NAND4 + * 0b0000000000100000..NAND5 + * 0b0000000001000000..NAND6 + * 0b0000000010000000..NAND7 + * 0b0000000100000000..SSP + */ +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK) +/*! @} */ + +/*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */ +/*! @{ */ + +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U) +/*! FREEZE_CHANNEL + * 0b0000000000000001..NAND0 + * 0b0000000000000010..NAND1 + * 0b0000000000000100..NAND2 + * 0b0000000000001000..NAND3 + * 0b0000000000010000..NAND4 + * 0b0000000000100000..NAND5 + * 0b0000000001000000..NAND6 + * 0b0000000010000000..NAND7 + * 0b0000000100000000..SSP + */ +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK) + +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U) +/*! RESET_CHANNEL + * 0b0000000000000001..NAND0 + * 0b0000000000000010..NAND1 + * 0b0000000000000100..NAND2 + * 0b0000000000001000..NAND3 + * 0b0000000000010000..NAND4 + * 0b0000000000100000..NAND5 + * 0b0000000001000000..NAND6 + * 0b0000000010000000..NAND7 + * 0b0000000100000000..SSP + */ +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK) +/*! @} */ + +/*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */ +/*! @{ */ + +#define APBH_DEVSEL_CH0_MASK (0x3U) +#define APBH_DEVSEL_CH0_SHIFT (0U) +#define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK) + +#define APBH_DEVSEL_CH1_MASK (0xCU) +#define APBH_DEVSEL_CH1_SHIFT (2U) +#define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK) + +#define APBH_DEVSEL_CH2_MASK (0x30U) +#define APBH_DEVSEL_CH2_SHIFT (4U) +#define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK) + +#define APBH_DEVSEL_CH3_MASK (0xC0U) +#define APBH_DEVSEL_CH3_SHIFT (6U) +#define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK) + +#define APBH_DEVSEL_CH4_MASK (0x300U) +#define APBH_DEVSEL_CH4_SHIFT (8U) +#define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK) + +#define APBH_DEVSEL_CH5_MASK (0xC00U) +#define APBH_DEVSEL_CH5_SHIFT (10U) +#define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK) + +#define APBH_DEVSEL_CH6_MASK (0x3000U) +#define APBH_DEVSEL_CH6_SHIFT (12U) +#define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK) + +#define APBH_DEVSEL_CH7_MASK (0xC000U) +#define APBH_DEVSEL_CH7_SHIFT (14U) +#define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK) + +#define APBH_DEVSEL_CH8_MASK (0x30000U) +#define APBH_DEVSEL_CH8_SHIFT (16U) +#define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK) + +#define APBH_DEVSEL_CH9_MASK (0xC0000U) +#define APBH_DEVSEL_CH9_SHIFT (18U) +#define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK) + +#define APBH_DEVSEL_CH10_MASK (0x300000U) +#define APBH_DEVSEL_CH10_SHIFT (20U) +#define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK) + +#define APBH_DEVSEL_CH11_MASK (0xC00000U) +#define APBH_DEVSEL_CH11_SHIFT (22U) +#define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK) + +#define APBH_DEVSEL_CH12_MASK (0x3000000U) +#define APBH_DEVSEL_CH12_SHIFT (24U) +#define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK) + +#define APBH_DEVSEL_CH13_MASK (0xC000000U) +#define APBH_DEVSEL_CH13_SHIFT (26U) +#define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK) + +#define APBH_DEVSEL_CH14_MASK (0x30000000U) +#define APBH_DEVSEL_CH14_SHIFT (28U) +#define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK) + +#define APBH_DEVSEL_CH15_MASK (0xC0000000U) +#define APBH_DEVSEL_CH15_SHIFT (30U) +#define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK) +/*! @} */ + +/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */ +/*! @{ */ + +#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U) +#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U) +#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK) + +#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU) +#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U) +#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK) + +#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U) +#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U) +#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK) + +#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U) +#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U) +#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK) + +#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U) +#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U) +#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK) + +#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U) +#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U) +#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK) + +#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U) +#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U) +#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK) + +#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U) +#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U) +#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK) + +#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U) +#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U) +/*! CH8 + * 0b00..BURST0 + * 0b01..BURST4 + * 0b10..BURST8 + */ +#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK) + +#define APBH_DMA_BURST_SIZE_CH9_MASK (0xC0000U) +#define APBH_DMA_BURST_SIZE_CH9_SHIFT (18U) +#define APBH_DMA_BURST_SIZE_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK) + +#define APBH_DMA_BURST_SIZE_CH10_MASK (0x300000U) +#define APBH_DMA_BURST_SIZE_CH10_SHIFT (20U) +#define APBH_DMA_BURST_SIZE_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK) + +#define APBH_DMA_BURST_SIZE_CH11_MASK (0xC00000U) +#define APBH_DMA_BURST_SIZE_CH11_SHIFT (22U) +#define APBH_DMA_BURST_SIZE_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK) + +#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3000000U) +#define APBH_DMA_BURST_SIZE_CH12_SHIFT (24U) +#define APBH_DMA_BURST_SIZE_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK) + +#define APBH_DMA_BURST_SIZE_CH13_MASK (0xC000000U) +#define APBH_DMA_BURST_SIZE_CH13_SHIFT (26U) +#define APBH_DMA_BURST_SIZE_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK) + +#define APBH_DMA_BURST_SIZE_CH14_MASK (0x30000000U) +#define APBH_DMA_BURST_SIZE_CH14_SHIFT (28U) +#define APBH_DMA_BURST_SIZE_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK) + +#define APBH_DMA_BURST_SIZE_CH15_MASK (0xC0000000U) +#define APBH_DMA_BURST_SIZE_CH15_SHIFT (30U) +#define APBH_DMA_BURST_SIZE_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK) +/*! @} */ + +/*! @name DEBUG - AHB to APBH DMA Debug Register */ +/*! @{ */ + +#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U) +#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U) +#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK) +/*! @} */ + +/*! @name CH0_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH0_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH0_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH0_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH0_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH0_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH0_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH0_CMD_COMMAND_MASK (0x3U) +#define APBH_CH0_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH0_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_COMMAND_SHIFT)) & APBH_CH0_CMD_COMMAND_MASK) + +#define APBH_CH0_CMD_CHAIN_MASK (0x4U) +#define APBH_CH0_CMD_CHAIN_SHIFT (2U) +#define APBH_CH0_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CHAIN_SHIFT)) & APBH_CH0_CMD_CHAIN_MASK) + +#define APBH_CH0_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH0_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH0_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_IRQONCMPLT_SHIFT)) & APBH_CH0_CMD_IRQONCMPLT_MASK) + +#define APBH_CH0_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH0_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH0_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDLOCK_SHIFT)) & APBH_CH0_CMD_NANDLOCK_MASK) + +#define APBH_CH0_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH0_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH0_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH0_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH0_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH0_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH0_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_SEMAPHORE_SHIFT)) & APBH_CH0_CMD_SEMAPHORE_MASK) + +#define APBH_CH0_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH0_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH0_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH0_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH0_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH0_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH0_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH0_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH0_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH0_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH0_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CMDWORDS_SHIFT)) & APBH_CH0_CMD_CMDWORDS_MASK) + +#define APBH_CH0_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH0_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH0_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_XFER_COUNT_SHIFT)) & APBH_CH0_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH0_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH0_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH0_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH0_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_BAR_ADDRESS_SHIFT)) & APBH_CH0_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH0_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH0_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH0_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH0_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH0_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH0_SEMA_PHORE_SHIFT (16U) +#define APBH_CH0_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_PHORE_SHIFT)) & APBH_CH0_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH0_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH0_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH0_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH0_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH0_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH0_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH0_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH0_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RSVD1_SHIFT)) & APBH_CH0_DEBUG1_RSVD1_MASK) + +#define APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH0_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH0_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH0_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_LOCK_SHIFT)) & APBH_CH0_DEBUG1_LOCK_MASK) + +#define APBH_CH0_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH0_DEBUG1_READY_SHIFT (26U) +#define APBH_CH0_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_READY_SHIFT)) & APBH_CH0_DEBUG1_READY_MASK) + +#define APBH_CH0_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH0_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH0_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_SENSE_SHIFT)) & APBH_CH0_DEBUG1_SENSE_MASK) + +#define APBH_CH0_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH0_DEBUG1_END_SHIFT (28U) +#define APBH_CH0_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_END_SHIFT)) & APBH_CH0_DEBUG1_END_MASK) + +#define APBH_CH0_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH0_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH0_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_KICK_SHIFT)) & APBH_CH0_DEBUG1_KICK_MASK) + +#define APBH_CH0_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH0_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH0_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_BURST_SHIFT)) & APBH_CH0_DEBUG1_BURST_MASK) + +#define APBH_CH0_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH0_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH0_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_REQ_SHIFT)) & APBH_CH0_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH0_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH0_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH0_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH0_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH0_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH0_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH0_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH1_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH1_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH1_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH1_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH1_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH1_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH1_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH1_CMD_COMMAND_MASK (0x3U) +#define APBH_CH1_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH1_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_COMMAND_SHIFT)) & APBH_CH1_CMD_COMMAND_MASK) + +#define APBH_CH1_CMD_CHAIN_MASK (0x4U) +#define APBH_CH1_CMD_CHAIN_SHIFT (2U) +#define APBH_CH1_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CHAIN_SHIFT)) & APBH_CH1_CMD_CHAIN_MASK) + +#define APBH_CH1_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH1_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH1_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_IRQONCMPLT_SHIFT)) & APBH_CH1_CMD_IRQONCMPLT_MASK) + +#define APBH_CH1_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH1_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH1_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDLOCK_SHIFT)) & APBH_CH1_CMD_NANDLOCK_MASK) + +#define APBH_CH1_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH1_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH1_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH1_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH1_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH1_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH1_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_SEMAPHORE_SHIFT)) & APBH_CH1_CMD_SEMAPHORE_MASK) + +#define APBH_CH1_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH1_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH1_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH1_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH1_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH1_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH1_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH1_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH1_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH1_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH1_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CMDWORDS_SHIFT)) & APBH_CH1_CMD_CMDWORDS_MASK) + +#define APBH_CH1_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH1_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH1_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_XFER_COUNT_SHIFT)) & APBH_CH1_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH1_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH1_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH1_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH1_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_BAR_ADDRESS_SHIFT)) & APBH_CH1_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH1_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH1_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH1_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH1_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH1_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH1_SEMA_PHORE_SHIFT (16U) +#define APBH_CH1_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_PHORE_SHIFT)) & APBH_CH1_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH1_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH1_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH1_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH1_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH1_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH1_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH1_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH1_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RSVD1_SHIFT)) & APBH_CH1_DEBUG1_RSVD1_MASK) + +#define APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH1_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH1_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH1_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_LOCK_SHIFT)) & APBH_CH1_DEBUG1_LOCK_MASK) + +#define APBH_CH1_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH1_DEBUG1_READY_SHIFT (26U) +#define APBH_CH1_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_READY_SHIFT)) & APBH_CH1_DEBUG1_READY_MASK) + +#define APBH_CH1_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH1_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH1_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_SENSE_SHIFT)) & APBH_CH1_DEBUG1_SENSE_MASK) + +#define APBH_CH1_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH1_DEBUG1_END_SHIFT (28U) +#define APBH_CH1_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_END_SHIFT)) & APBH_CH1_DEBUG1_END_MASK) + +#define APBH_CH1_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH1_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH1_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_KICK_SHIFT)) & APBH_CH1_DEBUG1_KICK_MASK) + +#define APBH_CH1_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH1_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH1_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_BURST_SHIFT)) & APBH_CH1_DEBUG1_BURST_MASK) + +#define APBH_CH1_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH1_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH1_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_REQ_SHIFT)) & APBH_CH1_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH1_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH1_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH1_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH1_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH1_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH1_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH1_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH2_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH2_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH2_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH2_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH2_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH2_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH2_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH2_CMD_COMMAND_MASK (0x3U) +#define APBH_CH2_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH2_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_COMMAND_SHIFT)) & APBH_CH2_CMD_COMMAND_MASK) + +#define APBH_CH2_CMD_CHAIN_MASK (0x4U) +#define APBH_CH2_CMD_CHAIN_SHIFT (2U) +#define APBH_CH2_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CHAIN_SHIFT)) & APBH_CH2_CMD_CHAIN_MASK) + +#define APBH_CH2_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH2_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH2_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_IRQONCMPLT_SHIFT)) & APBH_CH2_CMD_IRQONCMPLT_MASK) + +#define APBH_CH2_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH2_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH2_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDLOCK_SHIFT)) & APBH_CH2_CMD_NANDLOCK_MASK) + +#define APBH_CH2_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH2_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH2_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH2_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH2_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH2_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH2_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_SEMAPHORE_SHIFT)) & APBH_CH2_CMD_SEMAPHORE_MASK) + +#define APBH_CH2_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH2_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH2_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH2_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH2_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH2_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH2_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH2_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH2_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH2_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH2_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CMDWORDS_SHIFT)) & APBH_CH2_CMD_CMDWORDS_MASK) + +#define APBH_CH2_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH2_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH2_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_XFER_COUNT_SHIFT)) & APBH_CH2_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH2_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH2_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH2_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH2_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_BAR_ADDRESS_SHIFT)) & APBH_CH2_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH2_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH2_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH2_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH2_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH2_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH2_SEMA_PHORE_SHIFT (16U) +#define APBH_CH2_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_PHORE_SHIFT)) & APBH_CH2_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH2_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH2_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH2_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH2_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH2_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH2_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH2_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH2_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RSVD1_SHIFT)) & APBH_CH2_DEBUG1_RSVD1_MASK) + +#define APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH2_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH2_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH2_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_LOCK_SHIFT)) & APBH_CH2_DEBUG1_LOCK_MASK) + +#define APBH_CH2_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH2_DEBUG1_READY_SHIFT (26U) +#define APBH_CH2_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_READY_SHIFT)) & APBH_CH2_DEBUG1_READY_MASK) + +#define APBH_CH2_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH2_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH2_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_SENSE_SHIFT)) & APBH_CH2_DEBUG1_SENSE_MASK) + +#define APBH_CH2_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH2_DEBUG1_END_SHIFT (28U) +#define APBH_CH2_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_END_SHIFT)) & APBH_CH2_DEBUG1_END_MASK) + +#define APBH_CH2_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH2_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH2_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_KICK_SHIFT)) & APBH_CH2_DEBUG1_KICK_MASK) + +#define APBH_CH2_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH2_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH2_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_BURST_SHIFT)) & APBH_CH2_DEBUG1_BURST_MASK) + +#define APBH_CH2_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH2_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH2_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_REQ_SHIFT)) & APBH_CH2_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH2_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH2_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH2_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH2_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH2_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH2_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH2_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH3_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH3_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH3_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH3_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH3_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH3_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH3_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH3_CMD_COMMAND_MASK (0x3U) +#define APBH_CH3_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH3_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_COMMAND_SHIFT)) & APBH_CH3_CMD_COMMAND_MASK) + +#define APBH_CH3_CMD_CHAIN_MASK (0x4U) +#define APBH_CH3_CMD_CHAIN_SHIFT (2U) +#define APBH_CH3_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CHAIN_SHIFT)) & APBH_CH3_CMD_CHAIN_MASK) + +#define APBH_CH3_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH3_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH3_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_IRQONCMPLT_SHIFT)) & APBH_CH3_CMD_IRQONCMPLT_MASK) + +#define APBH_CH3_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH3_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH3_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDLOCK_SHIFT)) & APBH_CH3_CMD_NANDLOCK_MASK) + +#define APBH_CH3_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH3_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH3_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH3_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH3_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH3_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH3_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_SEMAPHORE_SHIFT)) & APBH_CH3_CMD_SEMAPHORE_MASK) + +#define APBH_CH3_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH3_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH3_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH3_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH3_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH3_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH3_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH3_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH3_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH3_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH3_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CMDWORDS_SHIFT)) & APBH_CH3_CMD_CMDWORDS_MASK) + +#define APBH_CH3_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH3_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH3_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_XFER_COUNT_SHIFT)) & APBH_CH3_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH3_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH3_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH3_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH3_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_BAR_ADDRESS_SHIFT)) & APBH_CH3_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH3_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH3_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH3_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH3_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH3_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH3_SEMA_PHORE_SHIFT (16U) +#define APBH_CH3_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_PHORE_SHIFT)) & APBH_CH3_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH3_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH3_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH3_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH3_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH3_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH3_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH3_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH3_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RSVD1_SHIFT)) & APBH_CH3_DEBUG1_RSVD1_MASK) + +#define APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH3_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH3_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH3_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_LOCK_SHIFT)) & APBH_CH3_DEBUG1_LOCK_MASK) + +#define APBH_CH3_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH3_DEBUG1_READY_SHIFT (26U) +#define APBH_CH3_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_READY_SHIFT)) & APBH_CH3_DEBUG1_READY_MASK) + +#define APBH_CH3_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH3_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH3_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_SENSE_SHIFT)) & APBH_CH3_DEBUG1_SENSE_MASK) + +#define APBH_CH3_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH3_DEBUG1_END_SHIFT (28U) +#define APBH_CH3_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_END_SHIFT)) & APBH_CH3_DEBUG1_END_MASK) + +#define APBH_CH3_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH3_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH3_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_KICK_SHIFT)) & APBH_CH3_DEBUG1_KICK_MASK) + +#define APBH_CH3_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH3_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH3_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_BURST_SHIFT)) & APBH_CH3_DEBUG1_BURST_MASK) + +#define APBH_CH3_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH3_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH3_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_REQ_SHIFT)) & APBH_CH3_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH3_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH3_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH3_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH3_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH3_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH3_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH3_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH4_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH4_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH4_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH4_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH4_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH4_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH4_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH4_CMD_COMMAND_MASK (0x3U) +#define APBH_CH4_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH4_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_COMMAND_SHIFT)) & APBH_CH4_CMD_COMMAND_MASK) + +#define APBH_CH4_CMD_CHAIN_MASK (0x4U) +#define APBH_CH4_CMD_CHAIN_SHIFT (2U) +#define APBH_CH4_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CHAIN_SHIFT)) & APBH_CH4_CMD_CHAIN_MASK) + +#define APBH_CH4_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH4_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH4_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_IRQONCMPLT_SHIFT)) & APBH_CH4_CMD_IRQONCMPLT_MASK) + +#define APBH_CH4_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH4_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH4_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDLOCK_SHIFT)) & APBH_CH4_CMD_NANDLOCK_MASK) + +#define APBH_CH4_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH4_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH4_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH4_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH4_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH4_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH4_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_SEMAPHORE_SHIFT)) & APBH_CH4_CMD_SEMAPHORE_MASK) + +#define APBH_CH4_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH4_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH4_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH4_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH4_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH4_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH4_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH4_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH4_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH4_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH4_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CMDWORDS_SHIFT)) & APBH_CH4_CMD_CMDWORDS_MASK) + +#define APBH_CH4_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH4_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH4_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_XFER_COUNT_SHIFT)) & APBH_CH4_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH4_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH4_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH4_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH4_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_BAR_ADDRESS_SHIFT)) & APBH_CH4_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH4_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH4_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH4_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH4_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH4_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH4_SEMA_PHORE_SHIFT (16U) +#define APBH_CH4_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_PHORE_SHIFT)) & APBH_CH4_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH4_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH4_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH4_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH4_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH4_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH4_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH4_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH4_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RSVD1_SHIFT)) & APBH_CH4_DEBUG1_RSVD1_MASK) + +#define APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH4_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH4_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH4_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_LOCK_SHIFT)) & APBH_CH4_DEBUG1_LOCK_MASK) + +#define APBH_CH4_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH4_DEBUG1_READY_SHIFT (26U) +#define APBH_CH4_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_READY_SHIFT)) & APBH_CH4_DEBUG1_READY_MASK) + +#define APBH_CH4_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH4_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH4_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_SENSE_SHIFT)) & APBH_CH4_DEBUG1_SENSE_MASK) + +#define APBH_CH4_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH4_DEBUG1_END_SHIFT (28U) +#define APBH_CH4_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_END_SHIFT)) & APBH_CH4_DEBUG1_END_MASK) + +#define APBH_CH4_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH4_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH4_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_KICK_SHIFT)) & APBH_CH4_DEBUG1_KICK_MASK) + +#define APBH_CH4_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH4_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH4_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_BURST_SHIFT)) & APBH_CH4_DEBUG1_BURST_MASK) + +#define APBH_CH4_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH4_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH4_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_REQ_SHIFT)) & APBH_CH4_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH4_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH4_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH4_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH4_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH4_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH4_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH4_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH5_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH5_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH5_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH5_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH5_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH5_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH5_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH5_CMD_COMMAND_MASK (0x3U) +#define APBH_CH5_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH5_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_COMMAND_SHIFT)) & APBH_CH5_CMD_COMMAND_MASK) + +#define APBH_CH5_CMD_CHAIN_MASK (0x4U) +#define APBH_CH5_CMD_CHAIN_SHIFT (2U) +#define APBH_CH5_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CHAIN_SHIFT)) & APBH_CH5_CMD_CHAIN_MASK) + +#define APBH_CH5_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH5_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH5_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_IRQONCMPLT_SHIFT)) & APBH_CH5_CMD_IRQONCMPLT_MASK) + +#define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH5_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH5_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK) + +#define APBH_CH5_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH5_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH5_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH5_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH5_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH5_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH5_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_SEMAPHORE_SHIFT)) & APBH_CH5_CMD_SEMAPHORE_MASK) + +#define APBH_CH5_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH5_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH5_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH5_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH5_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH5_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH5_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH5_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH5_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH5_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH5_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CMDWORDS_SHIFT)) & APBH_CH5_CMD_CMDWORDS_MASK) + +#define APBH_CH5_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH5_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH5_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_XFER_COUNT_SHIFT)) & APBH_CH5_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH5_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH5_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH5_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH5_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_BAR_ADDRESS_SHIFT)) & APBH_CH5_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH5_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH5_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH5_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH5_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH5_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH5_SEMA_PHORE_SHIFT (16U) +#define APBH_CH5_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_PHORE_SHIFT)) & APBH_CH5_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH5_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH5_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH5_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH5_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH5_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH5_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH5_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH5_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RSVD1_SHIFT)) & APBH_CH5_DEBUG1_RSVD1_MASK) + +#define APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH5_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH5_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH5_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_LOCK_SHIFT)) & APBH_CH5_DEBUG1_LOCK_MASK) + +#define APBH_CH5_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH5_DEBUG1_READY_SHIFT (26U) +#define APBH_CH5_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_READY_SHIFT)) & APBH_CH5_DEBUG1_READY_MASK) + +#define APBH_CH5_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH5_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH5_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_SENSE_SHIFT)) & APBH_CH5_DEBUG1_SENSE_MASK) + +#define APBH_CH5_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH5_DEBUG1_END_SHIFT (28U) +#define APBH_CH5_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_END_SHIFT)) & APBH_CH5_DEBUG1_END_MASK) + +#define APBH_CH5_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH5_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH5_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_KICK_SHIFT)) & APBH_CH5_DEBUG1_KICK_MASK) + +#define APBH_CH5_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH5_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH5_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_BURST_SHIFT)) & APBH_CH5_DEBUG1_BURST_MASK) + +#define APBH_CH5_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH5_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH5_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_REQ_SHIFT)) & APBH_CH5_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH5_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH5_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH5_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH5_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH5_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH5_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH5_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH6_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH6_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH6_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH6_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH6_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH6_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH6_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH6_CMD_COMMAND_MASK (0x3U) +#define APBH_CH6_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH6_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_COMMAND_SHIFT)) & APBH_CH6_CMD_COMMAND_MASK) + +#define APBH_CH6_CMD_CHAIN_MASK (0x4U) +#define APBH_CH6_CMD_CHAIN_SHIFT (2U) +#define APBH_CH6_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CHAIN_SHIFT)) & APBH_CH6_CMD_CHAIN_MASK) + +#define APBH_CH6_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH6_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH6_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_IRQONCMPLT_SHIFT)) & APBH_CH6_CMD_IRQONCMPLT_MASK) + +#define APBH_CH6_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH6_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH6_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDLOCK_SHIFT)) & APBH_CH6_CMD_NANDLOCK_MASK) + +#define APBH_CH6_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH6_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH6_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH6_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH6_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH6_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH6_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_SEMAPHORE_SHIFT)) & APBH_CH6_CMD_SEMAPHORE_MASK) + +#define APBH_CH6_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH6_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH6_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH6_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH6_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH6_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH6_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH6_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH6_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH6_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH6_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CMDWORDS_SHIFT)) & APBH_CH6_CMD_CMDWORDS_MASK) + +#define APBH_CH6_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH6_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH6_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_XFER_COUNT_SHIFT)) & APBH_CH6_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH6_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH6_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH6_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH6_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_BAR_ADDRESS_SHIFT)) & APBH_CH6_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH6_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH6_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH6_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH6_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH6_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH6_SEMA_PHORE_SHIFT (16U) +#define APBH_CH6_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_PHORE_SHIFT)) & APBH_CH6_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH6_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH6_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH6_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH6_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH6_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH6_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH6_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH6_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RSVD1_SHIFT)) & APBH_CH6_DEBUG1_RSVD1_MASK) + +#define APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH6_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH6_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH6_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_LOCK_SHIFT)) & APBH_CH6_DEBUG1_LOCK_MASK) + +#define APBH_CH6_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH6_DEBUG1_READY_SHIFT (26U) +#define APBH_CH6_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_READY_SHIFT)) & APBH_CH6_DEBUG1_READY_MASK) + +#define APBH_CH6_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH6_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH6_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_SENSE_SHIFT)) & APBH_CH6_DEBUG1_SENSE_MASK) + +#define APBH_CH6_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH6_DEBUG1_END_SHIFT (28U) +#define APBH_CH6_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_END_SHIFT)) & APBH_CH6_DEBUG1_END_MASK) + +#define APBH_CH6_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH6_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH6_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_KICK_SHIFT)) & APBH_CH6_DEBUG1_KICK_MASK) + +#define APBH_CH6_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH6_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH6_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_BURST_SHIFT)) & APBH_CH6_DEBUG1_BURST_MASK) + +#define APBH_CH6_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH6_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH6_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_REQ_SHIFT)) & APBH_CH6_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH6_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH6_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH6_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH6_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH6_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH6_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH6_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH7_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH7_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH7_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH7_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH7_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH7_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH7_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH7_CMD_COMMAND_MASK (0x3U) +#define APBH_CH7_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH7_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_COMMAND_SHIFT)) & APBH_CH7_CMD_COMMAND_MASK) + +#define APBH_CH7_CMD_CHAIN_MASK (0x4U) +#define APBH_CH7_CMD_CHAIN_SHIFT (2U) +#define APBH_CH7_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CHAIN_SHIFT)) & APBH_CH7_CMD_CHAIN_MASK) + +#define APBH_CH7_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH7_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH7_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_IRQONCMPLT_SHIFT)) & APBH_CH7_CMD_IRQONCMPLT_MASK) + +#define APBH_CH7_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH7_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH7_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDLOCK_SHIFT)) & APBH_CH7_CMD_NANDLOCK_MASK) + +#define APBH_CH7_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH7_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH7_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH7_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH7_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH7_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH7_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_SEMAPHORE_SHIFT)) & APBH_CH7_CMD_SEMAPHORE_MASK) + +#define APBH_CH7_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH7_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH7_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH7_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH7_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH7_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH7_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH7_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH7_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH7_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH7_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CMDWORDS_SHIFT)) & APBH_CH7_CMD_CMDWORDS_MASK) + +#define APBH_CH7_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH7_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH7_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_XFER_COUNT_SHIFT)) & APBH_CH7_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH7_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH7_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH7_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH7_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_BAR_ADDRESS_SHIFT)) & APBH_CH7_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH7_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH7_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH7_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH7_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH7_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH7_SEMA_PHORE_SHIFT (16U) +#define APBH_CH7_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_PHORE_SHIFT)) & APBH_CH7_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH7_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH7_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH7_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH7_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH7_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH7_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH7_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH7_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RSVD1_SHIFT)) & APBH_CH7_DEBUG1_RSVD1_MASK) + +#define APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH7_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH7_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH7_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_LOCK_SHIFT)) & APBH_CH7_DEBUG1_LOCK_MASK) + +#define APBH_CH7_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH7_DEBUG1_READY_SHIFT (26U) +#define APBH_CH7_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_READY_SHIFT)) & APBH_CH7_DEBUG1_READY_MASK) + +#define APBH_CH7_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH7_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH7_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_SENSE_SHIFT)) & APBH_CH7_DEBUG1_SENSE_MASK) + +#define APBH_CH7_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH7_DEBUG1_END_SHIFT (28U) +#define APBH_CH7_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_END_SHIFT)) & APBH_CH7_DEBUG1_END_MASK) + +#define APBH_CH7_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH7_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH7_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_KICK_SHIFT)) & APBH_CH7_DEBUG1_KICK_MASK) + +#define APBH_CH7_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH7_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH7_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_BURST_SHIFT)) & APBH_CH7_DEBUG1_BURST_MASK) + +#define APBH_CH7_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH7_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH7_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_REQ_SHIFT)) & APBH_CH7_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH7_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH7_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH7_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH7_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH7_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH7_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH7_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH8_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH8_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH8_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH8_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH8_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH8_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH8_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH8_CMD_COMMAND_MASK (0x3U) +#define APBH_CH8_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH8_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_COMMAND_SHIFT)) & APBH_CH8_CMD_COMMAND_MASK) + +#define APBH_CH8_CMD_CHAIN_MASK (0x4U) +#define APBH_CH8_CMD_CHAIN_SHIFT (2U) +#define APBH_CH8_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CHAIN_SHIFT)) & APBH_CH8_CMD_CHAIN_MASK) + +#define APBH_CH8_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH8_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH8_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_IRQONCMPLT_SHIFT)) & APBH_CH8_CMD_IRQONCMPLT_MASK) + +#define APBH_CH8_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH8_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH8_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDLOCK_SHIFT)) & APBH_CH8_CMD_NANDLOCK_MASK) + +#define APBH_CH8_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH8_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH8_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH8_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH8_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH8_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH8_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_SEMAPHORE_SHIFT)) & APBH_CH8_CMD_SEMAPHORE_MASK) + +#define APBH_CH8_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH8_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH8_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH8_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH8_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH8_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH8_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH8_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH8_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH8_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH8_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CMDWORDS_SHIFT)) & APBH_CH8_CMD_CMDWORDS_MASK) + +#define APBH_CH8_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH8_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH8_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_XFER_COUNT_SHIFT)) & APBH_CH8_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH8_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH8_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH8_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH8_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_BAR_ADDRESS_SHIFT)) & APBH_CH8_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH8_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH8_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH8_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH8_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH8_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH8_SEMA_PHORE_SHIFT (16U) +#define APBH_CH8_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_PHORE_SHIFT)) & APBH_CH8_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH8_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH8_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH8_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH8_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH8_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH8_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH8_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH8_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RSVD1_SHIFT)) & APBH_CH8_DEBUG1_RSVD1_MASK) + +#define APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH8_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH8_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH8_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_LOCK_SHIFT)) & APBH_CH8_DEBUG1_LOCK_MASK) + +#define APBH_CH8_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH8_DEBUG1_READY_SHIFT (26U) +#define APBH_CH8_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_READY_SHIFT)) & APBH_CH8_DEBUG1_READY_MASK) + +#define APBH_CH8_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH8_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH8_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_SENSE_SHIFT)) & APBH_CH8_DEBUG1_SENSE_MASK) + +#define APBH_CH8_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH8_DEBUG1_END_SHIFT (28U) +#define APBH_CH8_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_END_SHIFT)) & APBH_CH8_DEBUG1_END_MASK) + +#define APBH_CH8_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH8_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH8_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_KICK_SHIFT)) & APBH_CH8_DEBUG1_KICK_MASK) + +#define APBH_CH8_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH8_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH8_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_BURST_SHIFT)) & APBH_CH8_DEBUG1_BURST_MASK) + +#define APBH_CH8_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH8_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH8_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_REQ_SHIFT)) & APBH_CH8_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH8_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH8_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH8_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH8_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH8_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH8_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH8_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH9_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH9_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH9_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH9_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH9_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH9_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH9_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH9_CMD_COMMAND_MASK (0x3U) +#define APBH_CH9_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH9_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_COMMAND_SHIFT)) & APBH_CH9_CMD_COMMAND_MASK) + +#define APBH_CH9_CMD_CHAIN_MASK (0x4U) +#define APBH_CH9_CMD_CHAIN_SHIFT (2U) +#define APBH_CH9_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CHAIN_SHIFT)) & APBH_CH9_CMD_CHAIN_MASK) + +#define APBH_CH9_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH9_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH9_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_IRQONCMPLT_SHIFT)) & APBH_CH9_CMD_IRQONCMPLT_MASK) + +#define APBH_CH9_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH9_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH9_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDLOCK_SHIFT)) & APBH_CH9_CMD_NANDLOCK_MASK) + +#define APBH_CH9_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH9_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH9_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH9_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH9_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH9_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH9_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_SEMAPHORE_SHIFT)) & APBH_CH9_CMD_SEMAPHORE_MASK) + +#define APBH_CH9_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH9_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH9_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH9_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH9_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH9_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH9_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH9_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH9_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH9_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH9_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CMDWORDS_SHIFT)) & APBH_CH9_CMD_CMDWORDS_MASK) + +#define APBH_CH9_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH9_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH9_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_XFER_COUNT_SHIFT)) & APBH_CH9_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH9_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH9_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH9_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH9_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_BAR_ADDRESS_SHIFT)) & APBH_CH9_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH9_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH9_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH9_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH9_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH9_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH9_SEMA_PHORE_SHIFT (16U) +#define APBH_CH9_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_PHORE_SHIFT)) & APBH_CH9_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH9_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH9_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH9_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH9_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH9_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH9_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH9_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH9_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RSVD1_SHIFT)) & APBH_CH9_DEBUG1_RSVD1_MASK) + +#define APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH9_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH9_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH9_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_LOCK_SHIFT)) & APBH_CH9_DEBUG1_LOCK_MASK) + +#define APBH_CH9_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH9_DEBUG1_READY_SHIFT (26U) +#define APBH_CH9_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_READY_SHIFT)) & APBH_CH9_DEBUG1_READY_MASK) + +#define APBH_CH9_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH9_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH9_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_SENSE_SHIFT)) & APBH_CH9_DEBUG1_SENSE_MASK) + +#define APBH_CH9_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH9_DEBUG1_END_SHIFT (28U) +#define APBH_CH9_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_END_SHIFT)) & APBH_CH9_DEBUG1_END_MASK) + +#define APBH_CH9_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH9_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH9_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_KICK_SHIFT)) & APBH_CH9_DEBUG1_KICK_MASK) + +#define APBH_CH9_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH9_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH9_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_BURST_SHIFT)) & APBH_CH9_DEBUG1_BURST_MASK) + +#define APBH_CH9_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH9_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH9_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_REQ_SHIFT)) & APBH_CH9_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH9_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH9_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH9_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH9_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH9_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH9_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH9_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH10_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH10_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH10_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH10_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH10_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH10_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH10_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH10_CMD_COMMAND_MASK (0x3U) +#define APBH_CH10_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH10_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_COMMAND_SHIFT)) & APBH_CH10_CMD_COMMAND_MASK) + +#define APBH_CH10_CMD_CHAIN_MASK (0x4U) +#define APBH_CH10_CMD_CHAIN_SHIFT (2U) +#define APBH_CH10_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CHAIN_SHIFT)) & APBH_CH10_CMD_CHAIN_MASK) + +#define APBH_CH10_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH10_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH10_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_IRQONCMPLT_SHIFT)) & APBH_CH10_CMD_IRQONCMPLT_MASK) + +#define APBH_CH10_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH10_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH10_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDLOCK_SHIFT)) & APBH_CH10_CMD_NANDLOCK_MASK) + +#define APBH_CH10_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH10_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH10_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH10_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH10_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH10_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH10_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_SEMAPHORE_SHIFT)) & APBH_CH10_CMD_SEMAPHORE_MASK) + +#define APBH_CH10_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH10_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH10_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH10_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH10_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH10_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH10_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH10_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH10_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH10_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH10_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CMDWORDS_SHIFT)) & APBH_CH10_CMD_CMDWORDS_MASK) + +#define APBH_CH10_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH10_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH10_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_XFER_COUNT_SHIFT)) & APBH_CH10_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH10_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH10_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH10_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH10_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_BAR_ADDRESS_SHIFT)) & APBH_CH10_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH10_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH10_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH10_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH10_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH10_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH10_SEMA_PHORE_SHIFT (16U) +#define APBH_CH10_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_PHORE_SHIFT)) & APBH_CH10_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH10_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH10_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH10_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH10_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH10_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH10_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH10_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH10_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RSVD1_SHIFT)) & APBH_CH10_DEBUG1_RSVD1_MASK) + +#define APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH10_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH10_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH10_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_LOCK_SHIFT)) & APBH_CH10_DEBUG1_LOCK_MASK) + +#define APBH_CH10_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH10_DEBUG1_READY_SHIFT (26U) +#define APBH_CH10_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_READY_SHIFT)) & APBH_CH10_DEBUG1_READY_MASK) + +#define APBH_CH10_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH10_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH10_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_SENSE_SHIFT)) & APBH_CH10_DEBUG1_SENSE_MASK) + +#define APBH_CH10_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH10_DEBUG1_END_SHIFT (28U) +#define APBH_CH10_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_END_SHIFT)) & APBH_CH10_DEBUG1_END_MASK) + +#define APBH_CH10_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH10_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH10_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_KICK_SHIFT)) & APBH_CH10_DEBUG1_KICK_MASK) + +#define APBH_CH10_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH10_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH10_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_BURST_SHIFT)) & APBH_CH10_DEBUG1_BURST_MASK) + +#define APBH_CH10_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH10_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH10_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_REQ_SHIFT)) & APBH_CH10_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH10_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH10_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH10_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH10_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH10_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH10_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH10_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH11_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH11_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH11_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH11_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH11_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH11_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH11_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH11_CMD_COMMAND_MASK (0x3U) +#define APBH_CH11_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH11_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_COMMAND_SHIFT)) & APBH_CH11_CMD_COMMAND_MASK) + +#define APBH_CH11_CMD_CHAIN_MASK (0x4U) +#define APBH_CH11_CMD_CHAIN_SHIFT (2U) +#define APBH_CH11_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CHAIN_SHIFT)) & APBH_CH11_CMD_CHAIN_MASK) + +#define APBH_CH11_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH11_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH11_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_IRQONCMPLT_SHIFT)) & APBH_CH11_CMD_IRQONCMPLT_MASK) + +#define APBH_CH11_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH11_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH11_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDLOCK_SHIFT)) & APBH_CH11_CMD_NANDLOCK_MASK) + +#define APBH_CH11_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH11_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH11_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH11_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH11_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH11_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH11_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_SEMAPHORE_SHIFT)) & APBH_CH11_CMD_SEMAPHORE_MASK) + +#define APBH_CH11_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH11_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH11_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH11_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH11_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH11_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH11_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH11_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH11_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH11_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH11_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CMDWORDS_SHIFT)) & APBH_CH11_CMD_CMDWORDS_MASK) + +#define APBH_CH11_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH11_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH11_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_XFER_COUNT_SHIFT)) & APBH_CH11_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH11_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH11_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH11_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH11_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_BAR_ADDRESS_SHIFT)) & APBH_CH11_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH11_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH11_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH11_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH11_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH11_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH11_SEMA_PHORE_SHIFT (16U) +#define APBH_CH11_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_PHORE_SHIFT)) & APBH_CH11_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH11_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH11_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH11_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH11_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH11_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH11_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH11_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH11_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RSVD1_SHIFT)) & APBH_CH11_DEBUG1_RSVD1_MASK) + +#define APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH11_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH11_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH11_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_LOCK_SHIFT)) & APBH_CH11_DEBUG1_LOCK_MASK) + +#define APBH_CH11_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH11_DEBUG1_READY_SHIFT (26U) +#define APBH_CH11_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_READY_SHIFT)) & APBH_CH11_DEBUG1_READY_MASK) + +#define APBH_CH11_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH11_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH11_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_SENSE_SHIFT)) & APBH_CH11_DEBUG1_SENSE_MASK) + +#define APBH_CH11_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH11_DEBUG1_END_SHIFT (28U) +#define APBH_CH11_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_END_SHIFT)) & APBH_CH11_DEBUG1_END_MASK) + +#define APBH_CH11_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH11_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH11_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_KICK_SHIFT)) & APBH_CH11_DEBUG1_KICK_MASK) + +#define APBH_CH11_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH11_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH11_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_BURST_SHIFT)) & APBH_CH11_DEBUG1_BURST_MASK) + +#define APBH_CH11_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH11_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH11_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_REQ_SHIFT)) & APBH_CH11_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH11_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH11_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH11_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH11_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH11_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH11_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH11_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH12_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH12_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH12_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH12_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH12_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH12_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH12_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH12_CMD_COMMAND_MASK (0x3U) +#define APBH_CH12_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH12_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_COMMAND_SHIFT)) & APBH_CH12_CMD_COMMAND_MASK) + +#define APBH_CH12_CMD_CHAIN_MASK (0x4U) +#define APBH_CH12_CMD_CHAIN_SHIFT (2U) +#define APBH_CH12_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CHAIN_SHIFT)) & APBH_CH12_CMD_CHAIN_MASK) + +#define APBH_CH12_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH12_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH12_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_IRQONCMPLT_SHIFT)) & APBH_CH12_CMD_IRQONCMPLT_MASK) + +#define APBH_CH12_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH12_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH12_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDLOCK_SHIFT)) & APBH_CH12_CMD_NANDLOCK_MASK) + +#define APBH_CH12_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH12_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH12_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH12_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH12_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH12_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH12_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_SEMAPHORE_SHIFT)) & APBH_CH12_CMD_SEMAPHORE_MASK) + +#define APBH_CH12_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH12_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH12_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH12_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH12_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH12_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH12_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH12_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH12_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH12_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH12_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CMDWORDS_SHIFT)) & APBH_CH12_CMD_CMDWORDS_MASK) + +#define APBH_CH12_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH12_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH12_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_XFER_COUNT_SHIFT)) & APBH_CH12_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH12_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH12_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH12_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH12_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_BAR_ADDRESS_SHIFT)) & APBH_CH12_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH12_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH12_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH12_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH12_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH12_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH12_SEMA_PHORE_SHIFT (16U) +#define APBH_CH12_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_PHORE_SHIFT)) & APBH_CH12_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH12_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH12_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH12_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH12_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH12_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH12_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH12_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH12_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RSVD1_SHIFT)) & APBH_CH12_DEBUG1_RSVD1_MASK) + +#define APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH12_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH12_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH12_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_LOCK_SHIFT)) & APBH_CH12_DEBUG1_LOCK_MASK) + +#define APBH_CH12_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH12_DEBUG1_READY_SHIFT (26U) +#define APBH_CH12_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_READY_SHIFT)) & APBH_CH12_DEBUG1_READY_MASK) + +#define APBH_CH12_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH12_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH12_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_SENSE_SHIFT)) & APBH_CH12_DEBUG1_SENSE_MASK) + +#define APBH_CH12_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH12_DEBUG1_END_SHIFT (28U) +#define APBH_CH12_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_END_SHIFT)) & APBH_CH12_DEBUG1_END_MASK) + +#define APBH_CH12_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH12_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH12_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_KICK_SHIFT)) & APBH_CH12_DEBUG1_KICK_MASK) + +#define APBH_CH12_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH12_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH12_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_BURST_SHIFT)) & APBH_CH12_DEBUG1_BURST_MASK) + +#define APBH_CH12_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH12_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH12_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_REQ_SHIFT)) & APBH_CH12_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH12_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH12_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH12_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH12_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH12_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH12_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH12_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH13_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH13_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH13_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH13_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH13_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH13_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH13_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH13_CMD_COMMAND_MASK (0x3U) +#define APBH_CH13_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH13_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_COMMAND_SHIFT)) & APBH_CH13_CMD_COMMAND_MASK) + +#define APBH_CH13_CMD_CHAIN_MASK (0x4U) +#define APBH_CH13_CMD_CHAIN_SHIFT (2U) +#define APBH_CH13_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CHAIN_SHIFT)) & APBH_CH13_CMD_CHAIN_MASK) + +#define APBH_CH13_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH13_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH13_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_IRQONCMPLT_SHIFT)) & APBH_CH13_CMD_IRQONCMPLT_MASK) + +#define APBH_CH13_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH13_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH13_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDLOCK_SHIFT)) & APBH_CH13_CMD_NANDLOCK_MASK) + +#define APBH_CH13_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH13_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH13_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH13_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH13_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH13_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH13_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_SEMAPHORE_SHIFT)) & APBH_CH13_CMD_SEMAPHORE_MASK) + +#define APBH_CH13_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH13_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH13_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH13_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH13_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH13_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH13_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH13_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH13_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH13_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH13_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CMDWORDS_SHIFT)) & APBH_CH13_CMD_CMDWORDS_MASK) + +#define APBH_CH13_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH13_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH13_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_XFER_COUNT_SHIFT)) & APBH_CH13_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH13_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH13_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH13_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH13_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_BAR_ADDRESS_SHIFT)) & APBH_CH13_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH13_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH13_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH13_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH13_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH13_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH13_SEMA_PHORE_SHIFT (16U) +#define APBH_CH13_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_PHORE_SHIFT)) & APBH_CH13_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH13_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH13_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH13_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH13_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH13_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH13_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH13_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH13_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RSVD1_SHIFT)) & APBH_CH13_DEBUG1_RSVD1_MASK) + +#define APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH13_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH13_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH13_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_LOCK_SHIFT)) & APBH_CH13_DEBUG1_LOCK_MASK) + +#define APBH_CH13_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH13_DEBUG1_READY_SHIFT (26U) +#define APBH_CH13_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_READY_SHIFT)) & APBH_CH13_DEBUG1_READY_MASK) + +#define APBH_CH13_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH13_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH13_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_SENSE_SHIFT)) & APBH_CH13_DEBUG1_SENSE_MASK) + +#define APBH_CH13_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH13_DEBUG1_END_SHIFT (28U) +#define APBH_CH13_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_END_SHIFT)) & APBH_CH13_DEBUG1_END_MASK) + +#define APBH_CH13_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH13_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH13_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_KICK_SHIFT)) & APBH_CH13_DEBUG1_KICK_MASK) + +#define APBH_CH13_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH13_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH13_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_BURST_SHIFT)) & APBH_CH13_DEBUG1_BURST_MASK) + +#define APBH_CH13_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH13_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH13_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_REQ_SHIFT)) & APBH_CH13_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH13_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH13_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH13_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH13_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH13_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH13_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH13_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH14_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH14_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH14_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH14_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH14_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH14_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH14_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH14_CMD_COMMAND_MASK (0x3U) +#define APBH_CH14_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH14_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_COMMAND_SHIFT)) & APBH_CH14_CMD_COMMAND_MASK) + +#define APBH_CH14_CMD_CHAIN_MASK (0x4U) +#define APBH_CH14_CMD_CHAIN_SHIFT (2U) +#define APBH_CH14_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CHAIN_SHIFT)) & APBH_CH14_CMD_CHAIN_MASK) + +#define APBH_CH14_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH14_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH14_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_IRQONCMPLT_SHIFT)) & APBH_CH14_CMD_IRQONCMPLT_MASK) + +#define APBH_CH14_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH14_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH14_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDLOCK_SHIFT)) & APBH_CH14_CMD_NANDLOCK_MASK) + +#define APBH_CH14_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH14_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH14_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH14_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH14_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH14_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH14_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_SEMAPHORE_SHIFT)) & APBH_CH14_CMD_SEMAPHORE_MASK) + +#define APBH_CH14_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH14_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH14_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH14_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH14_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH14_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH14_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH14_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH14_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH14_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH14_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CMDWORDS_SHIFT)) & APBH_CH14_CMD_CMDWORDS_MASK) + +#define APBH_CH14_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH14_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH14_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_XFER_COUNT_SHIFT)) & APBH_CH14_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH14_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH14_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH14_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH14_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_BAR_ADDRESS_SHIFT)) & APBH_CH14_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH14_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH14_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH14_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH14_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH14_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH14_SEMA_PHORE_SHIFT (16U) +#define APBH_CH14_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_PHORE_SHIFT)) & APBH_CH14_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH14_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH14_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH14_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH14_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH14_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH14_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH14_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH14_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RSVD1_SHIFT)) & APBH_CH14_DEBUG1_RSVD1_MASK) + +#define APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH14_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH14_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH14_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_LOCK_SHIFT)) & APBH_CH14_DEBUG1_LOCK_MASK) + +#define APBH_CH14_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH14_DEBUG1_READY_SHIFT (26U) +#define APBH_CH14_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_READY_SHIFT)) & APBH_CH14_DEBUG1_READY_MASK) + +#define APBH_CH14_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH14_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH14_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_SENSE_SHIFT)) & APBH_CH14_DEBUG1_SENSE_MASK) + +#define APBH_CH14_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH14_DEBUG1_END_SHIFT (28U) +#define APBH_CH14_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_END_SHIFT)) & APBH_CH14_DEBUG1_END_MASK) + +#define APBH_CH14_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH14_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH14_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_KICK_SHIFT)) & APBH_CH14_DEBUG1_KICK_MASK) + +#define APBH_CH14_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH14_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH14_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_BURST_SHIFT)) & APBH_CH14_DEBUG1_BURST_MASK) + +#define APBH_CH14_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH14_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH14_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_REQ_SHIFT)) & APBH_CH14_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH14_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH14_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH14_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH14_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH14_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH14_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH14_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name CH15_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +/*! @{ */ + +#define APBH_CH15_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH15_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_CURCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH15_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +/*! @{ */ + +#define APBH_CH15_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH15_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_NXTCMDAR_CMD_ADDR_MASK) +/*! @} */ + +/*! @name CH15_CMD - APBH DMA Channel n Command Register */ +/*! @{ */ + +#define APBH_CH15_CMD_COMMAND_MASK (0x3U) +#define APBH_CH15_CMD_COMMAND_SHIFT (0U) +/*! COMMAND + * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. + * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained + * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain + * pointer if the peripheral sense line is false. + */ +#define APBH_CH15_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_COMMAND_SHIFT)) & APBH_CH15_CMD_COMMAND_MASK) + +#define APBH_CH15_CMD_CHAIN_MASK (0x4U) +#define APBH_CH15_CMD_CHAIN_SHIFT (2U) +#define APBH_CH15_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CHAIN_SHIFT)) & APBH_CH15_CMD_CHAIN_MASK) + +#define APBH_CH15_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH15_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH15_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_IRQONCMPLT_SHIFT)) & APBH_CH15_CMD_IRQONCMPLT_MASK) + +#define APBH_CH15_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH15_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH15_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDLOCK_SHIFT)) & APBH_CH15_CMD_NANDLOCK_MASK) + +#define APBH_CH15_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH15_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH15_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH15_CMD_NANDWAIT4READY_MASK) + +#define APBH_CH15_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH15_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH15_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_SEMAPHORE_SHIFT)) & APBH_CH15_CMD_SEMAPHORE_MASK) + +#define APBH_CH15_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH15_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH15_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH15_CMD_WAIT4ENDCMD_MASK) + +#define APBH_CH15_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH15_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH15_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH15_CMD_HALTONTERMINATE_MASK) + +#define APBH_CH15_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH15_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH15_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CMDWORDS_SHIFT)) & APBH_CH15_CMD_CMDWORDS_MASK) + +#define APBH_CH15_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH15_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH15_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_XFER_COUNT_SHIFT)) & APBH_CH15_CMD_XFER_COUNT_MASK) +/*! @} */ + +/*! @name CH15_BAR - APBH DMA Channel n Buffer Address Register */ +/*! @{ */ + +#define APBH_CH15_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH15_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH15_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_BAR_ADDRESS_SHIFT)) & APBH_CH15_BAR_ADDRESS_MASK) +/*! @} */ + +/*! @name CH15_SEMA - APBH DMA Channel n Semaphore Register */ +/*! @{ */ + +#define APBH_CH15_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH15_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH15_SEMA_INCREMENT_SEMA_MASK) + +#define APBH_CH15_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH15_SEMA_PHORE_SHIFT (16U) +#define APBH_CH15_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_PHORE_SHIFT)) & APBH_CH15_SEMA_PHORE_MASK) +/*! @} */ + +/*! @name CH15_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH15_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH15_DEBUG1_STATEMACHINE_SHIFT (0U) +/*! STATEMACHINE + * 0b00000..This is the idle state of the DMA state machine. + * 0b00001..State in which the DMA is waiting to receive the first word of a command. + * 0b00010..State in which the DMA is waiting to receive the third word of a command. + * 0b00011..State in which the DMA is waiting to receive the second word of a command. + * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. + * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. + * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the + * PIO words when PIO count is greater than 1. + * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. + * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and + * effectively halts. A channel reset is required to exit this state + * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. + * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device + * indicates that the external device is ready. + */ +#define APBH_CH15_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH15_DEBUG1_STATEMACHINE_MASK) + +#define APBH_CH15_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH15_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH15_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RSVD1_SHIFT)) & APBH_CH15_DEBUG1_RSVD1_MASK) + +#define APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK) + +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK) + +#define APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK) + +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK) + +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK) + +#define APBH_CH15_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH15_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH15_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_LOCK_SHIFT)) & APBH_CH15_DEBUG1_LOCK_MASK) + +#define APBH_CH15_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH15_DEBUG1_READY_SHIFT (26U) +#define APBH_CH15_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_READY_SHIFT)) & APBH_CH15_DEBUG1_READY_MASK) + +#define APBH_CH15_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH15_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH15_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_SENSE_SHIFT)) & APBH_CH15_DEBUG1_SENSE_MASK) + +#define APBH_CH15_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH15_DEBUG1_END_SHIFT (28U) +#define APBH_CH15_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_END_SHIFT)) & APBH_CH15_DEBUG1_END_MASK) + +#define APBH_CH15_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH15_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH15_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_KICK_SHIFT)) & APBH_CH15_DEBUG1_KICK_MASK) + +#define APBH_CH15_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH15_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH15_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_BURST_SHIFT)) & APBH_CH15_DEBUG1_BURST_MASK) + +#define APBH_CH15_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH15_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH15_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_REQ_SHIFT)) & APBH_CH15_DEBUG1_REQ_MASK) +/*! @} */ + +/*! @name CH15_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +/*! @{ */ + +#define APBH_CH15_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH15_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH15_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_AHB_BYTES_MASK) + +#define APBH_CH15_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH15_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH15_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_APB_BYTES_MASK) +/*! @} */ + +/*! @name VERSION - APBH Bridge Version Register */ +/*! @{ */ + +#define APBH_VERSION_STEP_MASK (0xFFFFU) +#define APBH_VERSION_STEP_SHIFT (0U) +#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK) + +#define APBH_VERSION_MINOR_MASK (0xFF0000U) +#define APBH_VERSION_MINOR_SHIFT (16U) +#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK) + +#define APBH_VERSION_MAJOR_MASK (0xFF000000U) +#define APBH_VERSION_MAJOR_SHIFT (24U) +#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group APBH_Register_Masks */ + + +/* APBH - Peripheral instance base addresses */ +/** Peripheral APBH base address */ +#define APBH_BASE (0x33000000u) +/** Peripheral APBH base pointer */ +#define APBH ((APBH_Type *)APBH_BASE) +/** Array initializer of APBH peripheral base addresses */ +#define APBH_BASE_ADDRS { APBH_BASE } +/** Array initializer of APBH peripheral base pointers */ +#define APBH_BASE_PTRS { APBH } +/** Interrupt vectors for the APBH peripheral type */ +#define APBH_IRQS { APBHDMA_IRQn } + +/*! + * @} + */ /* end of group APBH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BCH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer + * @{ + */ + +/** BCH - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */ + __I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */ + __I uint32_t STATUS0_SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */ + __I uint32_t STATUS0_CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */ + __I uint32_t STATUS0_TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */ + __IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */ + __IO uint32_t MODE_SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */ + __IO uint32_t MODE_CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */ + __IO uint32_t MODE_TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */ + __IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */ + __IO uint32_t ENCODEPTR_SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */ + __IO uint32_t ENCODEPTR_CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */ + __IO uint32_t ENCODEPTR_TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */ + __IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */ + __IO uint32_t DATAPTR_SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */ + __IO uint32_t DATAPTR_CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */ + __IO uint32_t DATAPTR_TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */ + __IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */ + __IO uint32_t METAPTR_SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */ + __IO uint32_t METAPTR_CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */ + __IO uint32_t METAPTR_TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */ + uint8_t RESERVED_0[16]; + __IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */ + __IO uint32_t LAYOUTSELECT_SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */ + __IO uint32_t LAYOUTSELECT_CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */ + __IO uint32_t LAYOUTSELECT_TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */ + __IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */ + __IO uint32_t FLASH0LAYOUT0_SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */ + __IO uint32_t FLASH0LAYOUT0_CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */ + __IO uint32_t FLASH0LAYOUT0_TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */ + __IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */ + __IO uint32_t FLASH0LAYOUT1_SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */ + __IO uint32_t FLASH0LAYOUT1_CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */ + __IO uint32_t FLASH0LAYOUT1_TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */ + __IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */ + __IO uint32_t FLASH1LAYOUT0_SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */ + __IO uint32_t FLASH1LAYOUT0_CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */ + __IO uint32_t FLASH1LAYOUT0_TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */ + __IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */ + __IO uint32_t FLASH1LAYOUT1_SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */ + __IO uint32_t FLASH1LAYOUT1_CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */ + __IO uint32_t FLASH1LAYOUT1_TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */ + __IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */ + __IO uint32_t FLASH2LAYOUT0_SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */ + __IO uint32_t FLASH2LAYOUT0_CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */ + __IO uint32_t FLASH2LAYOUT0_TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */ + __IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */ + __IO uint32_t FLASH2LAYOUT1_SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */ + __IO uint32_t FLASH2LAYOUT1_CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */ + __IO uint32_t FLASH2LAYOUT1_TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */ + __IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */ + __IO uint32_t FLASH3LAYOUT0_SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */ + __IO uint32_t FLASH3LAYOUT0_CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */ + __IO uint32_t FLASH3LAYOUT0_TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */ + __IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */ + __IO uint32_t FLASH3LAYOUT1_SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */ + __IO uint32_t FLASH3LAYOUT1_CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */ + __IO uint32_t FLASH3LAYOUT1_TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */ + __IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */ + __IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */ + __IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */ + __IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */ + __I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */ + __I uint32_t DBGKESREAD_SET; /**< KES Debug Read Register, offset: 0x114 */ + __I uint32_t DBGKESREAD_CLR; /**< KES Debug Read Register, offset: 0x118 */ + __I uint32_t DBGKESREAD_TOG; /**< KES Debug Read Register, offset: 0x11C */ + __I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */ + __I uint32_t DBGCSFEREAD_SET; /**< Chien Search Debug Read Register, offset: 0x124 */ + __I uint32_t DBGCSFEREAD_CLR; /**< Chien Search Debug Read Register, offset: 0x128 */ + __I uint32_t DBGCSFEREAD_TOG; /**< Chien Search Debug Read Register, offset: 0x12C */ + __I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */ + __I uint32_t DBGSYNDGENREAD_SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */ + __I uint32_t DBGSYNDGENREAD_CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */ + __I uint32_t DBGSYNDGENREAD_TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */ + __I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */ + __I uint32_t DBGAHBMREAD_SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */ + __I uint32_t DBGAHBMREAD_CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */ + __I uint32_t DBGAHBMREAD_TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */ + __I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */ + __I uint32_t BLOCKNAME_SET; /**< Block Name Register, offset: 0x154 */ + __I uint32_t BLOCKNAME_CLR; /**< Block Name Register, offset: 0x158 */ + __I uint32_t BLOCKNAME_TOG; /**< Block Name Register, offset: 0x15C */ + __I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */ + __I uint32_t VERSION_SET; /**< BCH Version Register, offset: 0x164 */ + __I uint32_t VERSION_CLR; /**< BCH Version Register, offset: 0x168 */ + __I uint32_t VERSION_TOG; /**< BCH Version Register, offset: 0x16C */ + __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */ + __IO uint32_t DEBUG1_SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */ + __IO uint32_t DEBUG1_CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */ + __IO uint32_t DEBUG1_TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */ +} BCH_Type; + +/* ---------------------------------------------------------------------------- + -- BCH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Register_Masks BCH Register Masks + * @{ + */ + +/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */ +/*! @{ */ + +#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK) + +#define BCH_CTRL_RSVD0_MASK (0x2U) +#define BCH_CTRL_RSVD0_SHIFT (1U) +/*! RSVD0 - This field is reserved. + */ +#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK) + +#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK) + +#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK) + +#define BCH_CTRL_RSVD1_MASK (0xF0U) +#define BCH_CTRL_RSVD1_SHIFT (4U) +/*! RSVD1 - This field is reserved. + */ +#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK) + +#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK) + +#define BCH_CTRL_RSVD2_MASK (0x200U) +#define BCH_CTRL_RSVD2_SHIFT (9U) +/*! RSVD2 - This field is reserved. + */ +#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK) + +#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK) + +#define BCH_CTRL_RSVD3_MASK (0xF800U) +#define BCH_CTRL_RSVD3_SHIFT (11U) +/*! RSVD3 - This field is reserved. + */ +#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK) + +#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK) + +#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK) + +#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK) + +#define BCH_CTRL_RSVD4_MASK (0x300000U) +#define BCH_CTRL_RSVD4_SHIFT (20U) +/*! RSVD4 - This field is reserved. + */ +#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK) + +#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK) + +#define BCH_CTRL_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_RSVD5_SHIFT (23U) +/*! RSVD5 - This field is reserved. + */ +#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK) + +#define BCH_CTRL_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_CLKGATE_SHIFT (30U) +/*! CLKGATE + * 0b0..Allow BCH to operate normally. + * 0b1..Do not clock BCH gates in order to minimize power consumption. + */ +#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK) + +#define BCH_CTRL_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_SFTRST_SHIFT (31U) +/*! SFTRST + * 0b0..Allow BCH to operate normally. + * 0b1..Hold BCH in reset. + */ +#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */ +/*! @{ */ + +#define BCH_CTRL_SET_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_SET_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK) + +#define BCH_CTRL_SET_RSVD0_MASK (0x2U) +#define BCH_CTRL_SET_RSVD0_SHIFT (1U) +/*! RSVD0 - This field is reserved. + */ +#define BCH_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK) + +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK) + +#define BCH_CTRL_SET_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK) + +#define BCH_CTRL_SET_RSVD1_MASK (0xF0U) +#define BCH_CTRL_SET_RSVD1_SHIFT (4U) +/*! RSVD1 - This field is reserved. + */ +#define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK) + +#define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK) + +#define BCH_CTRL_SET_RSVD2_MASK (0x200U) +#define BCH_CTRL_SET_RSVD2_SHIFT (9U) +/*! RSVD2 - This field is reserved. + */ +#define BCH_CTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK) + +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK) + +#define BCH_CTRL_SET_RSVD3_MASK (0xF800U) +#define BCH_CTRL_SET_RSVD3_SHIFT (11U) +/*! RSVD3 - This field is reserved. + */ +#define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK) + +#define BCH_CTRL_SET_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_SET_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_SET_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK) + +#define BCH_CTRL_SET_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_SET_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_SET_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK) + +#define BCH_CTRL_SET_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_SET_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_SET_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK) + +#define BCH_CTRL_SET_RSVD4_MASK (0x300000U) +#define BCH_CTRL_SET_RSVD4_SHIFT (20U) +/*! RSVD4 - This field is reserved. + */ +#define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK) + +#define BCH_CTRL_SET_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_SET_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK) + +#define BCH_CTRL_SET_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_SET_RSVD5_SHIFT (23U) +/*! RSVD5 - This field is reserved. + */ +#define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK) + +#define BCH_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_SET_CLKGATE_SHIFT (30U) +/*! CLKGATE + * 0b0..Allow BCH to operate normally. + * 0b1..Do not clock BCH gates in order to minimize power consumption. + */ +#define BCH_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK) + +#define BCH_CTRL_SET_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_SET_SFTRST_SHIFT (31U) +/*! SFTRST + * 0b0..Allow BCH to operate normally. + * 0b1..Hold BCH in reset. + */ +#define BCH_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */ +/*! @{ */ + +#define BCH_CTRL_CLR_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_CLR_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK) + +#define BCH_CTRL_CLR_RSVD0_MASK (0x2U) +#define BCH_CTRL_CLR_RSVD0_SHIFT (1U) +/*! RSVD0 - This field is reserved. + */ +#define BCH_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK) + +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK) + +#define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK) + +#define BCH_CTRL_CLR_RSVD1_MASK (0xF0U) +#define BCH_CTRL_CLR_RSVD1_SHIFT (4U) +/*! RSVD1 - This field is reserved. + */ +#define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK) + +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK) + +#define BCH_CTRL_CLR_RSVD2_MASK (0x200U) +#define BCH_CTRL_CLR_RSVD2_SHIFT (9U) +/*! RSVD2 - This field is reserved. + */ +#define BCH_CTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK) + +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK) + +#define BCH_CTRL_CLR_RSVD3_MASK (0xF800U) +#define BCH_CTRL_CLR_RSVD3_SHIFT (11U) +/*! RSVD3 - This field is reserved. + */ +#define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK) + +#define BCH_CTRL_CLR_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_CLR_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_CLR_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK) + +#define BCH_CTRL_CLR_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_CLR_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_CLR_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK) + +#define BCH_CTRL_CLR_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_CLR_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK) + +#define BCH_CTRL_CLR_RSVD4_MASK (0x300000U) +#define BCH_CTRL_CLR_RSVD4_SHIFT (20U) +/*! RSVD4 - This field is reserved. + */ +#define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK) + +#define BCH_CTRL_CLR_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_CLR_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK) + +#define BCH_CTRL_CLR_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_CLR_RSVD5_SHIFT (23U) +/*! RSVD5 - This field is reserved. + */ +#define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK) + +#define BCH_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_CLR_CLKGATE_SHIFT (30U) +/*! CLKGATE + * 0b0..Allow BCH to operate normally. + * 0b1..Do not clock BCH gates in order to minimize power consumption. + */ +#define BCH_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK) + +#define BCH_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_CLR_SFTRST_SHIFT (31U) +/*! SFTRST + * 0b0..Allow BCH to operate normally. + * 0b1..Hold BCH in reset. + */ +#define BCH_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */ +/*! @{ */ + +#define BCH_CTRL_TOG_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_TOG_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK) + +#define BCH_CTRL_TOG_RSVD0_MASK (0x2U) +#define BCH_CTRL_TOG_RSVD0_SHIFT (1U) +/*! RSVD0 - This field is reserved. + */ +#define BCH_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK) + +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK) + +#define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK) + +#define BCH_CTRL_TOG_RSVD1_MASK (0xF0U) +#define BCH_CTRL_TOG_RSVD1_SHIFT (4U) +/*! RSVD1 - This field is reserved. + */ +#define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK) + +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK) + +#define BCH_CTRL_TOG_RSVD2_MASK (0x200U) +#define BCH_CTRL_TOG_RSVD2_SHIFT (9U) +/*! RSVD2 - This field is reserved. + */ +#define BCH_CTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK) + +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK) + +#define BCH_CTRL_TOG_RSVD3_MASK (0xF800U) +#define BCH_CTRL_TOG_RSVD3_SHIFT (11U) +/*! RSVD3 - This field is reserved. + */ +#define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK) + +#define BCH_CTRL_TOG_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_TOG_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_TOG_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK) + +#define BCH_CTRL_TOG_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_TOG_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_TOG_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK) + +#define BCH_CTRL_TOG_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_TOG_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK) + +#define BCH_CTRL_TOG_RSVD4_MASK (0x300000U) +#define BCH_CTRL_TOG_RSVD4_SHIFT (20U) +/*! RSVD4 - This field is reserved. + */ +#define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK) + +#define BCH_CTRL_TOG_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_TOG_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK) + +#define BCH_CTRL_TOG_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_TOG_RSVD5_SHIFT (23U) +/*! RSVD5 - This field is reserved. + */ +#define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK) + +#define BCH_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_TOG_CLKGATE_SHIFT (30U) +/*! CLKGATE + * 0b0..Allow BCH to operate normally. + * 0b1..Do not clock BCH gates in order to minimize power consumption. + */ +#define BCH_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK) + +#define BCH_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_TOG_SFTRST_SHIFT (31U) +/*! SFTRST + * 0b0..Allow BCH to operate normally. + * 0b1..Hold BCH in reset. + */ +#define BCH_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */ +/*! @{ */ + +#define BCH_STATUS0_RSVD0_MASK (0x3U) +#define BCH_STATUS0_RSVD0_SHIFT (0U) +/*! RSVD0 - This field is reserved. + */ +#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK) + +#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK) + +#define BCH_STATUS0_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK) + +#define BCH_STATUS0_ALLONES_MASK (0x10U) +#define BCH_STATUS0_ALLONES_SHIFT (4U) +#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK) + +#define BCH_STATUS0_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_RSVD1_SHIFT (5U) +/*! RSVD1 - This field is reserved. + */ +#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK) + +#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U) +/*! STATUS_BLK0 + * 0b00000000..No errors found on block. + * 0b00000001..One error found on block. + * 0b00000010..One errors found on block. + * 0b00000011..One errors found on block. + * 0b00000100..One errors found on block. + * 0b11111110..Block exhibited uncorrectable errors. + * 0b11111111..Page is erased. + */ +#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK) + +#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK) + +#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_HANDLE_SHIFT (20U) +#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK) +/*! @} */ + +/*! @name STATUS0_SET - Hardware ECC Accelerator Status Register 0 */ +/*! @{ */ + +#define BCH_STATUS0_SET_RSVD0_MASK (0x3U) +#define BCH_STATUS0_SET_RSVD0_SHIFT (0U) +/*! RSVD0 - This field is reserved. + */ +#define BCH_STATUS0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD0_SHIFT)) & BCH_STATUS0_SET_RSVD0_MASK) + +#define BCH_STATUS0_SET_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_SET_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_SET_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_SET_UNCORRECTABLE_MASK) + +#define BCH_STATUS0_SET_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_SET_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_SET_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_CORRECTED_SHIFT)) & BCH_STATUS0_SET_CORRECTED_MASK) + +#define BCH_STATUS0_SET_ALLONES_MASK (0x10U) +#define BCH_STATUS0_SET_ALLONES_SHIFT (4U) +#define BCH_STATUS0_SET_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_ALLONES_SHIFT)) & BCH_STATUS0_SET_ALLONES_MASK) + +#define BCH_STATUS0_SET_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_SET_RSVD1_SHIFT (5U) +/*! RSVD1 - This field is reserved. + */ +#define BCH_STATUS0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD1_SHIFT)) & BCH_STATUS0_SET_RSVD1_MASK) + +#define BCH_STATUS0_SET_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_SET_STATUS_BLK0_SHIFT (8U) +/*! STATUS_BLK0 + * 0b00000000..No errors found on block. + * 0b00000001..One error found on block. + * 0b00000010..One errors found on block. + * 0b00000011..One errors found on block. + * 0b00000100..One errors found on block. + * 0b11111110..Block exhibited uncorrectable errors. + * 0b11111111..Page is erased. + */ +#define BCH_STATUS0_SET_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_STATUS_BLK0_SHIFT)) & BCH_STATUS0_SET_STATUS_BLK0_MASK) + +#define BCH_STATUS0_SET_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_SET_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_SET_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_COMPLETED_CE_SHIFT)) & BCH_STATUS0_SET_COMPLETED_CE_MASK) + +#define BCH_STATUS0_SET_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_SET_HANDLE_SHIFT (20U) +#define BCH_STATUS0_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_HANDLE_SHIFT)) & BCH_STATUS0_SET_HANDLE_MASK) +/*! @} */ + +/*! @name STATUS0_CLR - Hardware ECC Accelerator Status Register 0 */ +/*! @{ */ + +#define BCH_STATUS0_CLR_RSVD0_MASK (0x3U) +#define BCH_STATUS0_CLR_RSVD0_SHIFT (0U) +/*! RSVD0 - This field is reserved. + */ +#define BCH_STATUS0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD0_SHIFT)) & BCH_STATUS0_CLR_RSVD0_MASK) + +#define BCH_STATUS0_CLR_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_CLR_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_CLR_UNCORRECTABLE_MASK) + +#define BCH_STATUS0_CLR_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_CLR_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_CLR_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_CORRECTED_SHIFT)) & BCH_STATUS0_CLR_CORRECTED_MASK) + +#define BCH_STATUS0_CLR_ALLONES_MASK (0x10U) +#define BCH_STATUS0_CLR_ALLONES_SHIFT (4U) +#define BCH_STATUS0_CLR_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_ALLONES_SHIFT)) & BCH_STATUS0_CLR_ALLONES_MASK) + +#define BCH_STATUS0_CLR_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_CLR_RSVD1_SHIFT (5U) +/*! RSVD1 - This field is reserved. + */ +#define BCH_STATUS0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD1_SHIFT)) & BCH_STATUS0_CLR_RSVD1_MASK) + +#define BCH_STATUS0_CLR_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_CLR_STATUS_BLK0_SHIFT (8U) +/*! STATUS_BLK0 + * 0b00000000..No errors found on block. + * 0b00000001..One error found on block. + * 0b00000010..One errors found on block. + * 0b00000011..One errors found on block. + * 0b00000100..One errors found on block. + * 0b11111110..Block exhibited uncorrectable errors. + * 0b11111111..Page is erased. + */ +#define BCH_STATUS0_CLR_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_STATUS_BLK0_SHIFT)) & BCH_STATUS0_CLR_STATUS_BLK0_MASK) + +#define BCH_STATUS0_CLR_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_CLR_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_CLR_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_COMPLETED_CE_SHIFT)) & BCH_STATUS0_CLR_COMPLETED_CE_MASK) + +#define BCH_STATUS0_CLR_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_CLR_HANDLE_SHIFT (20U) +#define BCH_STATUS0_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_HANDLE_SHIFT)) & BCH_STATUS0_CLR_HANDLE_MASK) +/*! @} */ + +/*! @name STATUS0_TOG - Hardware ECC Accelerator Status Register 0 */ +/*! @{ */ + +#define BCH_STATUS0_TOG_RSVD0_MASK (0x3U) +#define BCH_STATUS0_TOG_RSVD0_SHIFT (0U) +/*! RSVD0 - This field is reserved. + */ +#define BCH_STATUS0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD0_SHIFT)) & BCH_STATUS0_TOG_RSVD0_MASK) + +#define BCH_STATUS0_TOG_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_TOG_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_TOG_UNCORRECTABLE_MASK) + +#define BCH_STATUS0_TOG_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_TOG_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_TOG_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_CORRECTED_SHIFT)) & BCH_STATUS0_TOG_CORRECTED_MASK) + +#define BCH_STATUS0_TOG_ALLONES_MASK (0x10U) +#define BCH_STATUS0_TOG_ALLONES_SHIFT (4U) +#define BCH_STATUS0_TOG_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_ALLONES_SHIFT)) & BCH_STATUS0_TOG_ALLONES_MASK) + +#define BCH_STATUS0_TOG_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_TOG_RSVD1_SHIFT (5U) +/*! RSVD1 - This field is reserved. + */ +#define BCH_STATUS0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD1_SHIFT)) & BCH_STATUS0_TOG_RSVD1_MASK) + +#define BCH_STATUS0_TOG_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_TOG_STATUS_BLK0_SHIFT (8U) +/*! STATUS_BLK0 + * 0b00000000..No errors found on block. + * 0b00000001..One error found on block. + * 0b00000010..One errors found on block. + * 0b00000011..One errors found on block. + * 0b00000100..One errors found on block. + * 0b11111110..Block exhibited uncorrectable errors. + * 0b11111111..Page is erased. + */ +#define BCH_STATUS0_TOG_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_STATUS_BLK0_SHIFT)) & BCH_STATUS0_TOG_STATUS_BLK0_MASK) + +#define BCH_STATUS0_TOG_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_TOG_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_TOG_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_COMPLETED_CE_SHIFT)) & BCH_STATUS0_TOG_COMPLETED_CE_MASK) + +#define BCH_STATUS0_TOG_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_TOG_HANDLE_SHIFT (20U) +#define BCH_STATUS0_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_HANDLE_SHIFT)) & BCH_STATUS0_TOG_HANDLE_MASK) +/*! @} */ + +/*! @name MODE - Hardware ECC Accelerator Mode Register */ +/*! @{ */ + +#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK) + +#define BCH_MODE_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_RSVD_SHIFT (8U) +/*! RSVD - This field is reserved. + */ +#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK) +/*! @} */ + +/*! @name MODE_SET - Hardware ECC Accelerator Mode Register */ +/*! @{ */ + +#define BCH_MODE_SET_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_SET_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_SET_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_SET_ERASE_THRESHOLD_MASK) + +#define BCH_MODE_SET_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_SET_RSVD_SHIFT (8U) +/*! RSVD - This field is reserved. + */ +#define BCH_MODE_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_RSVD_SHIFT)) & BCH_MODE_SET_RSVD_MASK) +/*! @} */ + +/*! @name MODE_CLR - Hardware ECC Accelerator Mode Register */ +/*! @{ */ + +#define BCH_MODE_CLR_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_CLR_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_CLR_ERASE_THRESHOLD_MASK) + +#define BCH_MODE_CLR_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_CLR_RSVD_SHIFT (8U) +/*! RSVD - This field is reserved. + */ +#define BCH_MODE_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_RSVD_SHIFT)) & BCH_MODE_CLR_RSVD_MASK) +/*! @} */ + +/*! @name MODE_TOG - Hardware ECC Accelerator Mode Register */ +/*! @{ */ + +#define BCH_MODE_TOG_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_TOG_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_TOG_ERASE_THRESHOLD_MASK) + +#define BCH_MODE_TOG_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_TOG_RSVD_SHIFT (8U) +/*! RSVD - This field is reserved. + */ +#define BCH_MODE_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_RSVD_SHIFT)) & BCH_MODE_TOG_RSVD_MASK) +/*! @} */ + +/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */ +/*! @{ */ + +#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK) +/*! @} */ + +/*! @name ENCODEPTR_SET - Hardware BCH ECC Loopback Encode Buffer Register */ +/*! @{ */ + +#define BCH_ENCODEPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_SET_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_SET_ADDR_SHIFT)) & BCH_ENCODEPTR_SET_ADDR_MASK) +/*! @} */ + +/*! @name ENCODEPTR_CLR - Hardware BCH ECC Loopback Encode Buffer Register */ +/*! @{ */ + +#define BCH_ENCODEPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_CLR_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_CLR_ADDR_SHIFT)) & BCH_ENCODEPTR_CLR_ADDR_MASK) +/*! @} */ + +/*! @name ENCODEPTR_TOG - Hardware BCH ECC Loopback Encode Buffer Register */ +/*! @{ */ + +#define BCH_ENCODEPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_TOG_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_TOG_ADDR_SHIFT)) & BCH_ENCODEPTR_TOG_ADDR_MASK) +/*! @} */ + +/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */ +/*! @{ */ + +#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_ADDR_SHIFT (0U) +#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK) +/*! @} */ + +/*! @name DATAPTR_SET - Hardware BCH ECC Loopback Data Buffer Register */ +/*! @{ */ + +#define BCH_DATAPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_SET_ADDR_SHIFT (0U) +#define BCH_DATAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_SET_ADDR_SHIFT)) & BCH_DATAPTR_SET_ADDR_MASK) +/*! @} */ + +/*! @name DATAPTR_CLR - Hardware BCH ECC Loopback Data Buffer Register */ +/*! @{ */ + +#define BCH_DATAPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_CLR_ADDR_SHIFT (0U) +#define BCH_DATAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_CLR_ADDR_SHIFT)) & BCH_DATAPTR_CLR_ADDR_MASK) +/*! @} */ + +/*! @name DATAPTR_TOG - Hardware BCH ECC Loopback Data Buffer Register */ +/*! @{ */ + +#define BCH_DATAPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_TOG_ADDR_SHIFT (0U) +#define BCH_DATAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_TOG_ADDR_SHIFT)) & BCH_DATAPTR_TOG_ADDR_MASK) +/*! @} */ + +/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */ +/*! @{ */ + +#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_ADDR_SHIFT (0U) +#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK) +/*! @} */ + +/*! @name METAPTR_SET - Hardware BCH ECC Loopback Metadata Buffer Register */ +/*! @{ */ + +#define BCH_METAPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_SET_ADDR_SHIFT (0U) +#define BCH_METAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_SET_ADDR_SHIFT)) & BCH_METAPTR_SET_ADDR_MASK) +/*! @} */ + +/*! @name METAPTR_CLR - Hardware BCH ECC Loopback Metadata Buffer Register */ +/*! @{ */ + +#define BCH_METAPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_CLR_ADDR_SHIFT (0U) +#define BCH_METAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_CLR_ADDR_SHIFT)) & BCH_METAPTR_CLR_ADDR_MASK) +/*! @} */ + +/*! @name METAPTR_TOG - Hardware BCH ECC Loopback Metadata Buffer Register */ +/*! @{ */ + +#define BCH_METAPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_TOG_ADDR_SHIFT (0U) +#define BCH_METAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_TOG_ADDR_SHIFT)) & BCH_METAPTR_TOG_ADDR_MASK) +/*! @} */ + +/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */ +/*! @{ */ + +#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK) +/*! @} */ + +/*! @name LAYOUTSELECT_SET - Hardware ECC Accelerator Layout Select Register */ +/*! @{ */ + +#define BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_SET_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK) + +#define BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK) +/*! @} */ + +/*! @name LAYOUTSELECT_CLR - Hardware ECC Accelerator Layout Select Register */ +/*! @{ */ + +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK) + +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK) +/*! @} */ + +/*! @name LAYOUTSELECT_TOG - Hardware ECC Accelerator Layout Select Register */ +/*! @{ */ + +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK) + +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK) +/*! @} */ + +/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK) + +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK) + +#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK) + +#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK) + +#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH0LAYOUT0_SET - Hardware BCH ECC Flash 0 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK) + +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK) + +#define BCH_FLASH0LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH0LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_SET_ECC0_MASK) + +#define BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK) + +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH0LAYOUT0_CLR - Hardware BCH ECC Flash 0 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK) + +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK) + +#define BCH_FLASH0LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH0LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_ECC0_MASK) + +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK) + +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH0LAYOUT0_TOG - Hardware BCH ECC Flash 0 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK) + +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK) + +#define BCH_FLASH0LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH0LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_ECC0_MASK) + +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK) + +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK) + +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK) + +#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK) + +#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH0LAYOUT1_SET - Hardware BCH ECC Flash 0 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK) + +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK) + +#define BCH_FLASH0LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH0LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_SET_ECCN_MASK) + +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH0LAYOUT1_CLR - Hardware BCH ECC Flash 0 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK) + +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK) + +#define BCH_FLASH0LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH0LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_ECCN_MASK) + +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH0LAYOUT1_TOG - Hardware BCH ECC Flash 0 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK) + +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK) + +#define BCH_FLASH0LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH0LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_ECCN_MASK) + +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK) + +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK) + +#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK) + +#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK) + +#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH1LAYOUT0_SET - Hardware BCH ECC Flash 1 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK) + +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK) + +#define BCH_FLASH1LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH1LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_SET_ECC0_MASK) + +#define BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK) + +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH1LAYOUT0_CLR - Hardware BCH ECC Flash 1 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK) + +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK) + +#define BCH_FLASH1LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH1LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_ECC0_MASK) + +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK) + +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH1LAYOUT0_TOG - Hardware BCH ECC Flash 1 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK) + +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK) + +#define BCH_FLASH1LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH1LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_ECC0_MASK) + +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK) + +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK) + +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK) + +#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK) + +#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH1LAYOUT1_SET - Hardware BCH ECC Flash 1 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK) + +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK) + +#define BCH_FLASH1LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH1LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_SET_ECCN_MASK) + +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH1LAYOUT1_CLR - Hardware BCH ECC Flash 1 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK) + +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK) + +#define BCH_FLASH1LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH1LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_ECCN_MASK) + +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH1LAYOUT1_TOG - Hardware BCH ECC Flash 1 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK) + +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK) + +#define BCH_FLASH1LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH1LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_ECCN_MASK) + +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK) + +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK) + +#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK) + +#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK) + +#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH2LAYOUT0_SET - Hardware BCH ECC Flash 2 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK) + +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK) + +#define BCH_FLASH2LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH2LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_SET_ECC0_MASK) + +#define BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK) + +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH2LAYOUT0_CLR - Hardware BCH ECC Flash 2 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK) + +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK) + +#define BCH_FLASH2LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH2LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_ECC0_MASK) + +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK) + +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH2LAYOUT0_TOG - Hardware BCH ECC Flash 2 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK) + +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK) + +#define BCH_FLASH2LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH2LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_ECC0_MASK) + +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK) + +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK) + +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK) + +#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK) + +#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH2LAYOUT1_SET - Hardware BCH ECC Flash 2 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK) + +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK) + +#define BCH_FLASH2LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH2LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_SET_ECCN_MASK) + +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH2LAYOUT1_CLR - Hardware BCH ECC Flash 2 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK) + +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK) + +#define BCH_FLASH2LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH2LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_ECCN_MASK) + +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH2LAYOUT1_TOG - Hardware BCH ECC Flash 2 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK) + +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK) + +#define BCH_FLASH2LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH2LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_ECCN_MASK) + +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK) + +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK) + +#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK) + +#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK) + +#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH3LAYOUT0_SET - Hardware BCH ECC Flash 3 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK) + +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK) + +#define BCH_FLASH3LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH3LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_SET_ECC0_MASK) + +#define BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK) + +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH3LAYOUT0_CLR - Hardware BCH ECC Flash 3 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK) + +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK) + +#define BCH_FLASH3LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH3LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_ECC0_MASK) + +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK) + +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH3LAYOUT0_TOG - Hardware BCH ECC Flash 3 Layout 0 Register */ +/*! @{ */ + +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK) + +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK) + +#define BCH_FLASH3LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT (11U) +/*! ECC0 + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH3LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_ECC0_MASK) + +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK) + +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK) +/*! @} */ + +/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK) + +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK) + +#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK) + +#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH3LAYOUT1_SET - Hardware BCH ECC Flash 3 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK) + +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK) + +#define BCH_FLASH3LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH3LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_SET_ECCN_MASK) + +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH3LAYOUT1_CLR - Hardware BCH ECC Flash 3 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK) + +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK) + +#define BCH_FLASH3LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH3LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_ECCN_MASK) + +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name FLASH3LAYOUT1_TOG - Hardware BCH ECC Flash 3 Layout 1 Register */ +/*! @{ */ + +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK) + +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK) + +#define BCH_FLASH3LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT (11U) +/*! ECCN + * 0b00000..No ECC to be performed + * 0b00001..ECC 2 to be performed + * 0b00010..ECC 4 to be performed + * 0b11110..ECC 60 to be performed + * 0b11111..ECC 62 to be performed + */ +#define BCH_FLASH3LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_ECCN_MASK) + +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK) +/*! @} */ + +/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */ +/*! @{ */ + +#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK) + +#define BCH_DEBUG0_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_RSVD0_SHIFT (6U) +/*! RSVD0 - This field is reserved. + */ +#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK) + +#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U) +/*! BM_KES_TEST_BYPASS + * 0b0..Bus master address generator for SYND_GEN writes operates normally. + * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. + */ +#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK) + +#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U) +/*! KES_DEBUG_STALL + * 0b0..KES FSM proceeds to next block supplied by bus master. + * 0b1..KES FSM waits after current equations are solved and the search engine is started. + */ +#define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK) + +#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK) + +#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U) +/*! KES_STANDALONE + * 0b0..Bus master address generator for SYND_GEN writes operates normally. + * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. + */ +#define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK) + +#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK) + +#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U) +/*! KES_DEBUG_MODE4K + * 0b1..Mode is set for 4K NAND pages. + * 0b1..Mode is set for 2K NAND pages. + */ +#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK) + +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +/*! KES_DEBUG_PAYLOAD_FLAG + * 0b1..Payload is set for 512 bytes data block. + * 0b1..Payload is set for 65 or 19 bytes auxiliary block. + */ +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK) + +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK) + +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +/*! KES_DEBUG_SYNDROME_SYMBOL + * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. + * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. + */ +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK) + +#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_RSVD1_SHIFT (25U) +/*! RSVD1 - This field is reserved. + */ +#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */ +/*! @{ */ + +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK) + +#define BCH_DEBUG0_SET_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_SET_RSVD0_SHIFT (6U) +/*! RSVD0 - This field is reserved. + */ +#define BCH_DEBUG0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK) + +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT (8U) +/*! BM_KES_TEST_BYPASS + * 0b0..Bus master address generator for SYND_GEN writes operates normally. + * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. + */ +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK) + +#define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT (9U) +/*! KES_DEBUG_STALL + * 0b0..KES FSM proceeds to next block supplied by bus master. + * 0b1..KES FSM waits after current equations are solved and the search engine is started. + */ +#define BCH_DEBUG0_SET_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK) + +#define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK) + +#define BCH_DEBUG0_SET_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT (11U) +/*! KES_STANDALONE + * 0b0..Bus master address generator for SYND_GEN writes operates normally. + * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. + */ +#define BCH_DEBUG0_SET_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK) + +#define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK) + +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT (13U) +/*! KES_DEBUG_MODE4K + * 0b1..Mode is set for 4K NAND pages. + * 0b1..Mode is set for 2K NAND pages. + */ +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK) + +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +/*! KES_DEBUG_PAYLOAD_FLAG + * 0b1..Payload is set for 512 bytes data block. + * 0b1..Payload is set for 65 or 19 bytes auxiliary block. + */ +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK) + +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK) + +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +/*! KES_DEBUG_SYNDROME_SYMBOL + * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. + * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. + */ +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK) + +#define BCH_DEBUG0_SET_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_SET_RSVD1_SHIFT (25U) +/*! RSVD1 - This field is reserved. + */ +#define BCH_DEBUG0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */ +/*! @{ */ + +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK) + +#define BCH_DEBUG0_CLR_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_CLR_RSVD0_SHIFT (6U) +/*! RSVD0 - This field is reserved. + */ +#define BCH_DEBUG0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK) + +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT (8U) +/*! BM_KES_TEST_BYPASS + * 0b0..Bus master address generator for SYND_GEN writes operates normally. + * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. + */ +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK) + +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT (9U) +/*! KES_DEBUG_STALL + * 0b0..KES FSM proceeds to next block supplied by bus master. + * 0b1..KES FSM waits after current equations are solved and the search engine is started. + */ +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK) + +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK) + +#define BCH_DEBUG0_CLR_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT (11U) +/*! KES_STANDALONE + * 0b0..Bus master address generator for SYND_GEN writes operates normally. + * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. + */ +#define BCH_DEBUG0_CLR_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK) + +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK) + +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT (13U) +/*! KES_DEBUG_MODE4K + * 0b1..Mode is set for 4K NAND pages. + * 0b1..Mode is set for 2K NAND pages. + */ +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK) + +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +/*! KES_DEBUG_PAYLOAD_FLAG + * 0b1..Payload is set for 512 bytes data block. + * 0b1..Payload is set for 65 or 19 bytes auxiliary block. + */ +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK) + +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK) + +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +/*! KES_DEBUG_SYNDROME_SYMBOL + * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. + * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. + */ +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK) + +#define BCH_DEBUG0_CLR_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_CLR_RSVD1_SHIFT (25U) +/*! RSVD1 - This field is reserved. + */ +#define BCH_DEBUG0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */ +/*! @{ */ + +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK) + +#define BCH_DEBUG0_TOG_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_TOG_RSVD0_SHIFT (6U) +/*! RSVD0 - This field is reserved. + */ +#define BCH_DEBUG0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK) + +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT (8U) +/*! BM_KES_TEST_BYPASS + * 0b0..Bus master address generator for SYND_GEN writes operates normally. + * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. + */ +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK) + +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT (9U) +/*! KES_DEBUG_STALL + * 0b0..KES FSM proceeds to next block supplied by bus master. + * 0b1..KES FSM waits after current equations are solved and the search engine is started. + */ +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK) + +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK) + +#define BCH_DEBUG0_TOG_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT (11U) +/*! KES_STANDALONE + * 0b0..Bus master address generator for SYND_GEN writes operates normally. + * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. + */ +#define BCH_DEBUG0_TOG_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK) + +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK) + +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT (13U) +/*! KES_DEBUG_MODE4K + * 0b1..Mode is set for 4K NAND pages. + * 0b1..Mode is set for 2K NAND pages. + */ +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK) + +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +/*! KES_DEBUG_PAYLOAD_FLAG + * 0b1..Payload is set for 512 bytes data block. + * 0b1..Payload is set for 65 or 19 bytes auxiliary block. + */ +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK) + +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK) + +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +/*! KES_DEBUG_SYNDROME_SYMBOL + * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. + * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. + */ +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK) + +#define BCH_DEBUG0_TOG_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_TOG_RSVD1_SHIFT (25U) +/*! RSVD1 - This field is reserved. + */ +#define BCH_DEBUG0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK) +/*! @} */ + +/*! @name DBGKESREAD - KES Debug Read Register */ +/*! @{ */ + +#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK) +/*! @} */ + +/*! @name DBGKESREAD_SET - KES Debug Read Register */ +/*! @{ */ + +#define BCH_DBGKESREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_SET_VALUES_SHIFT)) & BCH_DBGKESREAD_SET_VALUES_MASK) +/*! @} */ + +/*! @name DBGKESREAD_CLR - KES Debug Read Register */ +/*! @{ */ + +#define BCH_DBGKESREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_CLR_VALUES_SHIFT)) & BCH_DBGKESREAD_CLR_VALUES_MASK) +/*! @} */ + +/*! @name DBGKESREAD_TOG - KES Debug Read Register */ +/*! @{ */ + +#define BCH_DBGKESREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_TOG_VALUES_SHIFT)) & BCH_DBGKESREAD_TOG_VALUES_MASK) +/*! @} */ + +/*! @name DBGCSFEREAD - Chien Search Debug Read Register */ +/*! @{ */ + +#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK) +/*! @} */ + +/*! @name DBGCSFEREAD_SET - Chien Search Debug Read Register */ +/*! @{ */ + +#define BCH_DBGCSFEREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_SET_VALUES_SHIFT)) & BCH_DBGCSFEREAD_SET_VALUES_MASK) +/*! @} */ + +/*! @name DBGCSFEREAD_CLR - Chien Search Debug Read Register */ +/*! @{ */ + +#define BCH_DBGCSFEREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_CLR_VALUES_SHIFT)) & BCH_DBGCSFEREAD_CLR_VALUES_MASK) +/*! @} */ + +/*! @name DBGCSFEREAD_TOG - Chien Search Debug Read Register */ +/*! @{ */ + +#define BCH_DBGCSFEREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_TOG_VALUES_SHIFT)) & BCH_DBGCSFEREAD_TOG_VALUES_MASK) +/*! @} */ + +/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */ +/*! @{ */ + +#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK) +/*! @} */ + +/*! @name DBGSYNDGENREAD_SET - Syndrome Generator Debug Read Register */ +/*! @{ */ + +#define BCH_DBGSYNDGENREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_SET_VALUES_MASK) +/*! @} */ + +/*! @name DBGSYNDGENREAD_CLR - Syndrome Generator Debug Read Register */ +/*! @{ */ + +#define BCH_DBGSYNDGENREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_CLR_VALUES_MASK) +/*! @} */ + +/*! @name DBGSYNDGENREAD_TOG - Syndrome Generator Debug Read Register */ +/*! @{ */ + +#define BCH_DBGSYNDGENREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_TOG_VALUES_MASK) +/*! @} */ + +/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */ +/*! @{ */ + +#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK) +/*! @} */ + +/*! @name DBGAHBMREAD_SET - Bus Master and ECC Controller Debug Read Register */ +/*! @{ */ + +#define BCH_DBGAHBMREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_SET_VALUES_SHIFT)) & BCH_DBGAHBMREAD_SET_VALUES_MASK) +/*! @} */ + +/*! @name DBGAHBMREAD_CLR - Bus Master and ECC Controller Debug Read Register */ +/*! @{ */ + +#define BCH_DBGAHBMREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_CLR_VALUES_SHIFT)) & BCH_DBGAHBMREAD_CLR_VALUES_MASK) +/*! @} */ + +/*! @name DBGAHBMREAD_TOG - Bus Master and ECC Controller Debug Read Register */ +/*! @{ */ + +#define BCH_DBGAHBMREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_TOG_VALUES_SHIFT)) & BCH_DBGAHBMREAD_TOG_VALUES_MASK) +/*! @} */ + +/*! @name BLOCKNAME - Block Name Register */ +/*! @{ */ + +#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK) +/*! @} */ + +/*! @name BLOCKNAME_SET - Block Name Register */ +/*! @{ */ + +#define BCH_BLOCKNAME_SET_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_SET_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_SET_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_SET_NAME_SHIFT)) & BCH_BLOCKNAME_SET_NAME_MASK) +/*! @} */ + +/*! @name BLOCKNAME_CLR - Block Name Register */ +/*! @{ */ + +#define BCH_BLOCKNAME_CLR_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_CLR_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_CLR_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_CLR_NAME_SHIFT)) & BCH_BLOCKNAME_CLR_NAME_MASK) +/*! @} */ + +/*! @name BLOCKNAME_TOG - Block Name Register */ +/*! @{ */ + +#define BCH_BLOCKNAME_TOG_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_TOG_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_TOG_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_TOG_NAME_SHIFT)) & BCH_BLOCKNAME_TOG_NAME_MASK) +/*! @} */ + +/*! @name VERSION - BCH Version Register */ +/*! @{ */ + +#define BCH_VERSION_STEP_MASK (0xFFFFU) +#define BCH_VERSION_STEP_SHIFT (0U) +#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK) + +#define BCH_VERSION_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_MINOR_SHIFT (16U) +#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK) + +#define BCH_VERSION_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_MAJOR_SHIFT (24U) +#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name VERSION_SET - BCH Version Register */ +/*! @{ */ + +#define BCH_VERSION_SET_STEP_MASK (0xFFFFU) +#define BCH_VERSION_SET_STEP_SHIFT (0U) +#define BCH_VERSION_SET_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_STEP_SHIFT)) & BCH_VERSION_SET_STEP_MASK) + +#define BCH_VERSION_SET_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_SET_MINOR_SHIFT (16U) +#define BCH_VERSION_SET_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MINOR_SHIFT)) & BCH_VERSION_SET_MINOR_MASK) + +#define BCH_VERSION_SET_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_SET_MAJOR_SHIFT (24U) +#define BCH_VERSION_SET_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MAJOR_SHIFT)) & BCH_VERSION_SET_MAJOR_MASK) +/*! @} */ + +/*! @name VERSION_CLR - BCH Version Register */ +/*! @{ */ + +#define BCH_VERSION_CLR_STEP_MASK (0xFFFFU) +#define BCH_VERSION_CLR_STEP_SHIFT (0U) +#define BCH_VERSION_CLR_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_STEP_SHIFT)) & BCH_VERSION_CLR_STEP_MASK) + +#define BCH_VERSION_CLR_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_CLR_MINOR_SHIFT (16U) +#define BCH_VERSION_CLR_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MINOR_SHIFT)) & BCH_VERSION_CLR_MINOR_MASK) + +#define BCH_VERSION_CLR_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_CLR_MAJOR_SHIFT (24U) +#define BCH_VERSION_CLR_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MAJOR_SHIFT)) & BCH_VERSION_CLR_MAJOR_MASK) +/*! @} */ + +/*! @name VERSION_TOG - BCH Version Register */ +/*! @{ */ + +#define BCH_VERSION_TOG_STEP_MASK (0xFFFFU) +#define BCH_VERSION_TOG_STEP_SHIFT (0U) +#define BCH_VERSION_TOG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_STEP_SHIFT)) & BCH_VERSION_TOG_STEP_MASK) + +#define BCH_VERSION_TOG_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_TOG_MINOR_SHIFT (16U) +#define BCH_VERSION_TOG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MINOR_SHIFT)) & BCH_VERSION_TOG_MINOR_MASK) + +#define BCH_VERSION_TOG_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_TOG_MAJOR_SHIFT (24U) +#define BCH_VERSION_TOG_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MAJOR_SHIFT)) & BCH_VERSION_TOG_MAJOR_MASK) +/*! @} */ + +/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */ +/*! @{ */ + +#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK) + +#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_RSVD_SHIFT (9U) +/*! RSVD - This field is reserved. + */ +#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK) + +#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U) +/*! DEBUG1_PREERASECHK + * 0b0..Turn off pre-erase check + * 0b1..Turn on pre-erase check + */ +#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK) +/*! @} */ + +/*! @name DEBUG1_SET - Hardware BCH ECC Debug Register 1 */ +/*! @{ */ + +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK) + +#define BCH_DEBUG1_SET_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_SET_RSVD_SHIFT (9U) +/*! RSVD - This field is reserved. + */ +#define BCH_DEBUG1_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_RSVD_SHIFT)) & BCH_DEBUG1_SET_RSVD_MASK) + +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT (31U) +/*! DEBUG1_PREERASECHK + * 0b0..Turn off pre-erase check + * 0b1..Turn on pre-erase check + */ +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK) +/*! @} */ + +/*! @name DEBUG1_CLR - Hardware BCH ECC Debug Register 1 */ +/*! @{ */ + +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK) + +#define BCH_DEBUG1_CLR_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_CLR_RSVD_SHIFT (9U) +/*! RSVD - This field is reserved. + */ +#define BCH_DEBUG1_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_RSVD_SHIFT)) & BCH_DEBUG1_CLR_RSVD_MASK) + +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT (31U) +/*! DEBUG1_PREERASECHK + * 0b0..Turn off pre-erase check + * 0b1..Turn on pre-erase check + */ +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK) +/*! @} */ + +/*! @name DEBUG1_TOG - Hardware BCH ECC Debug Register 1 */ +/*! @{ */ + +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK) + +#define BCH_DEBUG1_TOG_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_TOG_RSVD_SHIFT (9U) +/*! RSVD - This field is reserved. + */ +#define BCH_DEBUG1_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_RSVD_SHIFT)) & BCH_DEBUG1_TOG_RSVD_MASK) + +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT (31U) +/*! DEBUG1_PREERASECHK + * 0b0..Turn off pre-erase check + * 0b1..Turn on pre-erase check + */ +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BCH_Register_Masks */ + + +/* BCH - Peripheral instance base addresses */ +/** Peripheral BCH base address */ +#define BCH_BASE (0x33004000u) +/** Peripheral BCH base pointer */ +#define BCH ((BCH_Type *)BCH_BASE) +/** Array initializer of BCH peripheral base addresses */ +#define BCH_BASE_ADDRS { BCH_BASE } +/** Array initializer of BCH peripheral base pointers */ +#define BCH_BASE_PTRS { BCH } +/** Interrupt vectors for the BCH peripheral type */ +#define BCH_IRQS { BCH_IRQn } + +/*! + * @} + */ /* end of group BCH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BLK_CTL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTL_Peripheral_Access_Layer BLK_CTL Peripheral Access Layer + * @{ + */ + +/** BLK_CTL - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< Reset Control, offset: 0x0 */ + __IO uint32_t SET; /**< Reset Control, offset: 0x4 */ + __IO uint32_t CLR; /**< Reset Control, offset: 0x8 */ + __IO uint32_t TOG; /**< Reset Control, offset: 0xC */ + } RESET_CTRL; + struct { /* offset: 0x10 */ + __IO uint32_t RW; /**< Control, offset: 0x10 */ + __IO uint32_t SET; /**< Control, offset: 0x14 */ + __IO uint32_t CLR; /**< Control, offset: 0x18 */ + __IO uint32_t TOG; /**< Control, offset: 0x1C */ + } CONTROL0; + struct { /* offset: 0x20 */ + __IO uint32_t RW; /**< Spare Control0, offset: 0x20 */ + __IO uint32_t SET; /**< Spare Control0, offset: 0x24 */ + __IO uint32_t CLR; /**< Spare Control0, offset: 0x28 */ + __IO uint32_t TOG; /**< Spare Control0, offset: 0x2C */ + } SPARE_CTRL0; + struct { /* offset: 0x30 */ + __IO uint32_t RW; /**< Spare Control1, offset: 0x30 */ + __IO uint32_t SET; /**< Spare Control1, offset: 0x34 */ + __IO uint32_t CLR; /**< Spare Control1, offset: 0x38 */ + __IO uint32_t TOG; /**< Spare Control1, offset: 0x3C */ + } SPARE_CTRL1; + struct { /* offset: 0x40 */ + __I uint32_t RW; /**< Spare Status0, offset: 0x40 */ + __I uint32_t SET; /**< Spare Status0, offset: 0x44 */ + __I uint32_t CLR; /**< Spare Status0, offset: 0x48 */ + __I uint32_t TOG; /**< Spare Status0, offset: 0x4C */ + } SPARE_STATUS0; +} BLK_CTL_Type; + +/* ---------------------------------------------------------------------------- + -- BLK_CTL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTL_Register_Masks BLK_CTL Register Masks + * @{ + */ + +/*! @name RESET_CTRL - Reset Control */ +/*! @{ */ + +#define BLK_CTL_RESET_CTRL_B_CLK_RESETN_MASK (0x1U) +#define BLK_CTL_RESET_CTRL_B_CLK_RESETN_SHIFT (0U) +/*! B_CLK_RESETN - b_clk domain modules resetn + */ +#define BLK_CTL_RESET_CTRL_B_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_B_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_B_CLK_RESETN_MASK) + +#define BLK_CTL_RESET_CTRL_APB_CLK_RESETN_MASK (0x2U) +#define BLK_CTL_RESET_CTRL_APB_CLK_RESETN_SHIFT (1U) +/*! APB_CLK_RESETN - apb_clk domain modules resetn + */ +#define BLK_CTL_RESET_CTRL_APB_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_APB_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_APB_CLK_RESETN_MASK) + +#define BLK_CTL_RESET_CTRL_P_CLK_RESETN_MASK (0x4U) +#define BLK_CTL_RESET_CTRL_P_CLK_RESETN_SHIFT (2U) +/*! P_CLK_RESETN - p_clk domain modules resetn + */ +#define BLK_CTL_RESET_CTRL_P_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_P_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_P_CLK_RESETN_MASK) + +#define BLK_CTL_RESET_CTRL_RTR_CLK_RESETN_MASK (0x8U) +#define BLK_CTL_RESET_CTRL_RTR_CLK_RESETN_SHIFT (3U) +/*! RTR_CLK_RESETN - rtr_clk domain modules resetn + */ +#define BLK_CTL_RESET_CTRL_RTR_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_RTR_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_RTR_CLK_RESETN_MASK) + +#define BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN_MASK (0xFF0000U) +#define BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN_SHIFT (16U) +/*! SPARE_CLK_RESETN - spare clk domain resetn + */ +#define BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN_MASK) +/*! @} */ + +/*! @name CONTROL0 - Control */ +/*! @{ */ + +#define BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL_MASK (0x30U) +#define BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL_SHIFT (4U) +/*! DISPMIX_REFCLK_SEL - Display Subsystem Reference Clock Select + */ +#define BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL_SHIFT)) & BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL_MASK) + +#define BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL_MASK (0x100U) +#define BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL_SHIFT (8U) +/*! DISPMIX_PIXCLK_SEL - Display Subsystem Pixel Clock Select + */ +#define BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL_SHIFT)) & BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL_MASK) +/*! @} */ + +/*! @name SPARE_CTRL0 - Spare Control0 */ +/*! @{ */ + +#define BLK_CTL_SPARE_CTRL0_SPARE_CTRL_MASK (0xFFFFFFFFU) +#define BLK_CTL_SPARE_CTRL0_SPARE_CTRL_SHIFT (0U) +/*! SPARE_CTRL - SPARE Control + */ +#define BLK_CTL_SPARE_CTRL0_SPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_SPARE_CTRL0_SPARE_CTRL_SHIFT)) & BLK_CTL_SPARE_CTRL0_SPARE_CTRL_MASK) +/*! @} */ + +/*! @name SPARE_CTRL1 - Spare Control1 */ +/*! @{ */ + +#define BLK_CTL_SPARE_CTRL1_SPARE_CTRL_MASK (0xFFFFFFFFU) +#define BLK_CTL_SPARE_CTRL1_SPARE_CTRL_SHIFT (0U) +/*! SPARE_CTRL - SPARE Control + */ +#define BLK_CTL_SPARE_CTRL1_SPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_SPARE_CTRL1_SPARE_CTRL_SHIFT)) & BLK_CTL_SPARE_CTRL1_SPARE_CTRL_MASK) +/*! @} */ + +/*! @name SPARE_STATUS0 - Spare Status0 */ +/*! @{ */ + +#define BLK_CTL_SPARE_STATUS0_SPARE_STATUS_MASK (0xFFFFFFFFU) +#define BLK_CTL_SPARE_STATUS0_SPARE_STATUS_SHIFT (0U) +/*! SPARE_STATUS - SPARE Control + */ +#define BLK_CTL_SPARE_STATUS0_SPARE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_SPARE_STATUS0_SPARE_STATUS_SHIFT)) & BLK_CTL_SPARE_STATUS0_SPARE_STATUS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BLK_CTL_Register_Masks */ + + +/* BLK_CTL - Peripheral instance base addresses */ +/** Peripheral DCSS__BLK_CTL base address */ +#define DCSS__BLK_CTL_BASE (0x32E2F000u) +/** Peripheral DCSS__BLK_CTL base pointer */ +#define DCSS__BLK_CTL ((BLK_CTL_Type *)DCSS__BLK_CTL_BASE) +/** Array initializer of BLK_CTL peripheral base addresses */ +#define BLK_CTL_BASE_ADDRS { DCSS__BLK_CTL_BASE } +/** Array initializer of BLK_CTL peripheral base pointers */ +#define BLK_CTL_BASE_PTRS { DCSS__BLK_CTL } + +/*! + * @} + */ /* end of group BLK_CTL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer + * @{ + */ + +/** CCM - Register Layout Typedef */ +typedef struct { + __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */ + __IO uint32_t GPR0_SET; /**< General Purpose Register, offset: 0x4 */ + __IO uint32_t GPR0_CLR; /**< General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR0_TOG; /**< General Purpose Register, offset: 0xC */ + uint8_t RESERVED_0[2032]; + struct { /* offset: 0x800, array step: 0x10 */ + __IO uint32_t PLL_CTRL; /**< CCM PLL Control Register, array offset: 0x800, array step: 0x10 */ + __IO uint32_t PLL_CTRL_SET; /**< CCM PLL Control Register, array offset: 0x804, array step: 0x10 */ + __IO uint32_t PLL_CTRL_CLR; /**< CCM PLL Control Register, array offset: 0x808, array step: 0x10 */ + __IO uint32_t PLL_CTRL_TOG; /**< CCM PLL Control Register, array offset: 0x80C, array step: 0x10 */ + } PLL_CTRL[39]; + uint8_t RESERVED_1[13712]; + struct { /* offset: 0x4000, array step: 0x10 */ + __IO uint32_t CCGR; /**< CCM Clock Gating Register, array offset: 0x4000, array step: 0x10 */ + __IO uint32_t CCGR_SET; /**< CCM Clock Gating Register, array offset: 0x4004, array step: 0x10 */ + __IO uint32_t CCGR_CLR; /**< CCM Clock Gating Register, array offset: 0x4008, array step: 0x10 */ + __IO uint32_t CCGR_TOG; /**< CCM Clock Gating Register, array offset: 0x400C, array step: 0x10 */ + } CCGR[191]; + uint8_t RESERVED_2[13328]; + struct { /* offset: 0x8000, array step: 0x80 */ + __IO uint32_t TARGET_ROOT; /**< Target Register, array offset: 0x8000, array step: 0x80 */ + __IO uint32_t TARGET_ROOT_SET; /**< Target Register, array offset: 0x8004, array step: 0x80 */ + __IO uint32_t TARGET_ROOT_CLR; /**< Target Register, array offset: 0x8008, array step: 0x80 */ + __IO uint32_t TARGET_ROOT_TOG; /**< Target Register, array offset: 0x800C, array step: 0x80 */ + __IO uint32_t MISC; /**< Miscellaneous Register, array offset: 0x8010, array step: 0x80 */ + __IO uint32_t MISC_ROOT_SET; /**< Miscellaneous Register, array offset: 0x8014, array step: 0x80 */ + __IO uint32_t MISC_ROOT_CLR; /**< Miscellaneous Register, array offset: 0x8018, array step: 0x80 */ + __IO uint32_t MISC_ROOT_TOG; /**< Miscellaneous Register, array offset: 0x801C, array step: 0x80 */ + __IO uint32_t POST; /**< Post Divider Register, array offset: 0x8020, array step: 0x80 */ + __IO uint32_t POST_ROOT_SET; /**< Post Divider Register, array offset: 0x8024, array step: 0x80 */ + __IO uint32_t POST_ROOT_CLR; /**< Post Divider Register, array offset: 0x8028, array step: 0x80 */ + __IO uint32_t POST_ROOT_TOG; /**< Post Divider Register, array offset: 0x802C, array step: 0x80 */ + __IO uint32_t PRE; /**< Pre Divider Register, array offset: 0x8030, array step: 0x80 */ + __IO uint32_t PRE_ROOT_SET; /**< Pre Divider Register, array offset: 0x8034, array step: 0x80 */ + __IO uint32_t PRE_ROOT_CLR; /**< Pre Divider Register, array offset: 0x8038, array step: 0x80 */ + __IO uint32_t PRE_ROOT_TOG; /**< Pre Divider Register, array offset: 0x803C, array step: 0x80 */ + uint8_t RESERVED_0[48]; + __IO uint32_t ACCESS_CTRL; /**< Access Control Register, array offset: 0x8070, array step: 0x80 */ + __IO uint32_t ACCESS_CTRL_ROOT_SET; /**< Access Control Register, array offset: 0x8074, array step: 0x80 */ + __IO uint32_t ACCESS_CTRL_ROOT_CLR; /**< Access Control Register, array offset: 0x8078, array step: 0x80 */ + __IO uint32_t ACCESS_CTRL_ROOT_TOG; /**< Access Control Register, array offset: 0x807C, array step: 0x80 */ + } ROOT[142]; +} CCM_Type; + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/*! @name GPR0 - General Purpose Register */ +/*! @{ */ + +#define CCM_GPR0_GP0_MASK (0xFFFFFFFFU) +#define CCM_GPR0_GP0_SHIFT (0U) +#define CCM_GPR0_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_GP0_SHIFT)) & CCM_GPR0_GP0_MASK) +/*! @} */ + +/*! @name GPR0_SET - General Purpose Register */ +/*! @{ */ + +#define CCM_GPR0_SET_GP0_MASK (0xFFFFFFFFU) +#define CCM_GPR0_SET_GP0_SHIFT (0U) +#define CCM_GPR0_SET_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_SET_GP0_SHIFT)) & CCM_GPR0_SET_GP0_MASK) +/*! @} */ + +/*! @name GPR0_CLR - General Purpose Register */ +/*! @{ */ + +#define CCM_GPR0_CLR_GP0_MASK (0xFFFFFFFFU) +#define CCM_GPR0_CLR_GP0_SHIFT (0U) +#define CCM_GPR0_CLR_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_CLR_GP0_SHIFT)) & CCM_GPR0_CLR_GP0_MASK) +/*! @} */ + +/*! @name GPR0_TOG - General Purpose Register */ +/*! @{ */ + +#define CCM_GPR0_TOG_GP0_MASK (0xFFFFFFFFU) +#define CCM_GPR0_TOG_GP0_SHIFT (0U) +#define CCM_GPR0_TOG_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_TOG_GP0_SHIFT)) & CCM_GPR0_TOG_GP0_MASK) +/*! @} */ + +/*! @name PLL_CTRL - CCM PLL Control Register */ +/*! @{ */ + +#define CCM_PLL_CTRL_SETTING0_MASK (0x3U) +#define CCM_PLL_CTRL_SETTING0_SHIFT (0U) +/*! SETTING0 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING0_SHIFT)) & CCM_PLL_CTRL_SETTING0_MASK) + +#define CCM_PLL_CTRL_SETTING1_MASK (0x30U) +#define CCM_PLL_CTRL_SETTING1_SHIFT (4U) +/*! SETTING1 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING1_SHIFT)) & CCM_PLL_CTRL_SETTING1_MASK) + +#define CCM_PLL_CTRL_SETTING2_MASK (0x300U) +#define CCM_PLL_CTRL_SETTING2_SHIFT (8U) +/*! SETTING2 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING2_SHIFT)) & CCM_PLL_CTRL_SETTING2_MASK) + +#define CCM_PLL_CTRL_SETTING3_MASK (0x3000U) +#define CCM_PLL_CTRL_SETTING3_SHIFT (12U) +/*! SETTING3 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING3_SHIFT)) & CCM_PLL_CTRL_SETTING3_MASK) +/*! @} */ + +/* The count of CCM_PLL_CTRL */ +#define CCM_PLL_CTRL_COUNT (39U) + +/*! @name PLL_CTRL_SET - CCM PLL Control Register */ +/*! @{ */ + +#define CCM_PLL_CTRL_SET_SETTING0_MASK (0x3U) +#define CCM_PLL_CTRL_SET_SETTING0_SHIFT (0U) +/*! SETTING0 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_SET_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING0_SHIFT)) & CCM_PLL_CTRL_SET_SETTING0_MASK) + +#define CCM_PLL_CTRL_SET_SETTING1_MASK (0x30U) +#define CCM_PLL_CTRL_SET_SETTING1_SHIFT (4U) +/*! SETTING1 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_SET_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING1_SHIFT)) & CCM_PLL_CTRL_SET_SETTING1_MASK) + +#define CCM_PLL_CTRL_SET_SETTING2_MASK (0x300U) +#define CCM_PLL_CTRL_SET_SETTING2_SHIFT (8U) +/*! SETTING2 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_SET_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING2_SHIFT)) & CCM_PLL_CTRL_SET_SETTING2_MASK) + +#define CCM_PLL_CTRL_SET_SETTING3_MASK (0x3000U) +#define CCM_PLL_CTRL_SET_SETTING3_SHIFT (12U) +/*! SETTING3 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_SET_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING3_SHIFT)) & CCM_PLL_CTRL_SET_SETTING3_MASK) +/*! @} */ + +/* The count of CCM_PLL_CTRL_SET */ +#define CCM_PLL_CTRL_SET_COUNT (39U) + +/*! @name PLL_CTRL_CLR - CCM PLL Control Register */ +/*! @{ */ + +#define CCM_PLL_CTRL_CLR_SETTING0_MASK (0x3U) +#define CCM_PLL_CTRL_CLR_SETTING0_SHIFT (0U) +/*! SETTING0 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_CLR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING0_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING0_MASK) + +#define CCM_PLL_CTRL_CLR_SETTING1_MASK (0x30U) +#define CCM_PLL_CTRL_CLR_SETTING1_SHIFT (4U) +/*! SETTING1 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_CLR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING1_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING1_MASK) + +#define CCM_PLL_CTRL_CLR_SETTING2_MASK (0x300U) +#define CCM_PLL_CTRL_CLR_SETTING2_SHIFT (8U) +/*! SETTING2 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_CLR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING2_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING2_MASK) + +#define CCM_PLL_CTRL_CLR_SETTING3_MASK (0x3000U) +#define CCM_PLL_CTRL_CLR_SETTING3_SHIFT (12U) +/*! SETTING3 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_CLR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING3_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING3_MASK) +/*! @} */ + +/* The count of CCM_PLL_CTRL_CLR */ +#define CCM_PLL_CTRL_CLR_COUNT (39U) + +/*! @name PLL_CTRL_TOG - CCM PLL Control Register */ +/*! @{ */ + +#define CCM_PLL_CTRL_TOG_SETTING0_MASK (0x3U) +#define CCM_PLL_CTRL_TOG_SETTING0_SHIFT (0U) +/*! SETTING0 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_TOG_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING0_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING0_MASK) + +#define CCM_PLL_CTRL_TOG_SETTING1_MASK (0x30U) +#define CCM_PLL_CTRL_TOG_SETTING1_SHIFT (4U) +/*! SETTING1 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_TOG_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING1_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING1_MASK) + +#define CCM_PLL_CTRL_TOG_SETTING2_MASK (0x300U) +#define CCM_PLL_CTRL_TOG_SETTING2_SHIFT (8U) +/*! SETTING2 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_TOG_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING2_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING2_MASK) + +#define CCM_PLL_CTRL_TOG_SETTING3_MASK (0x3000U) +#define CCM_PLL_CTRL_TOG_SETTING3_SHIFT (12U) +/*! SETTING3 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_PLL_CTRL_TOG_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING3_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING3_MASK) +/*! @} */ + +/* The count of CCM_PLL_CTRL_TOG */ +#define CCM_PLL_CTRL_TOG_COUNT (39U) + +/*! @name CCGR - CCM Clock Gating Register */ +/*! @{ */ + +#define CCM_CCGR_SETTING0_MASK (0x3U) +#define CCM_CCGR_SETTING0_SHIFT (0U) +/*! SETTING0 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING0_SHIFT)) & CCM_CCGR_SETTING0_MASK) + +#define CCM_CCGR_SETTING1_MASK (0x30U) +#define CCM_CCGR_SETTING1_SHIFT (4U) +/*! SETTING1 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING1_SHIFT)) & CCM_CCGR_SETTING1_MASK) + +#define CCM_CCGR_SETTING2_MASK (0x300U) +#define CCM_CCGR_SETTING2_SHIFT (8U) +/*! SETTING2 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING2_SHIFT)) & CCM_CCGR_SETTING2_MASK) + +#define CCM_CCGR_SETTING3_MASK (0x3000U) +#define CCM_CCGR_SETTING3_SHIFT (12U) +/*! SETTING3 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING3_SHIFT)) & CCM_CCGR_SETTING3_MASK) +/*! @} */ + +/* The count of CCM_CCGR */ +#define CCM_CCGR_COUNT (191U) + +/*! @name CCGR_SET - CCM Clock Gating Register */ +/*! @{ */ + +#define CCM_CCGR_SET_SETTING0_MASK (0x3U) +#define CCM_CCGR_SET_SETTING0_SHIFT (0U) +/*! SETTING0 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_SET_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING0_SHIFT)) & CCM_CCGR_SET_SETTING0_MASK) + +#define CCM_CCGR_SET_SETTING1_MASK (0x30U) +#define CCM_CCGR_SET_SETTING1_SHIFT (4U) +/*! SETTING1 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_SET_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING1_SHIFT)) & CCM_CCGR_SET_SETTING1_MASK) + +#define CCM_CCGR_SET_SETTING2_MASK (0x300U) +#define CCM_CCGR_SET_SETTING2_SHIFT (8U) +/*! SETTING2 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_SET_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING2_SHIFT)) & CCM_CCGR_SET_SETTING2_MASK) + +#define CCM_CCGR_SET_SETTING3_MASK (0x3000U) +#define CCM_CCGR_SET_SETTING3_SHIFT (12U) +/*! SETTING3 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_SET_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING3_SHIFT)) & CCM_CCGR_SET_SETTING3_MASK) +/*! @} */ + +/* The count of CCM_CCGR_SET */ +#define CCM_CCGR_SET_COUNT (191U) + +/*! @name CCGR_CLR - CCM Clock Gating Register */ +/*! @{ */ + +#define CCM_CCGR_CLR_SETTING0_MASK (0x3U) +#define CCM_CCGR_CLR_SETTING0_SHIFT (0U) +/*! SETTING0 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_CLR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING0_SHIFT)) & CCM_CCGR_CLR_SETTING0_MASK) + +#define CCM_CCGR_CLR_SETTING1_MASK (0x30U) +#define CCM_CCGR_CLR_SETTING1_SHIFT (4U) +/*! SETTING1 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_CLR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING1_SHIFT)) & CCM_CCGR_CLR_SETTING1_MASK) + +#define CCM_CCGR_CLR_SETTING2_MASK (0x300U) +#define CCM_CCGR_CLR_SETTING2_SHIFT (8U) +/*! SETTING2 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_CLR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING2_SHIFT)) & CCM_CCGR_CLR_SETTING2_MASK) + +#define CCM_CCGR_CLR_SETTING3_MASK (0x3000U) +#define CCM_CCGR_CLR_SETTING3_SHIFT (12U) +/*! SETTING3 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_CLR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING3_SHIFT)) & CCM_CCGR_CLR_SETTING3_MASK) +/*! @} */ + +/* The count of CCM_CCGR_CLR */ +#define CCM_CCGR_CLR_COUNT (191U) + +/*! @name CCGR_TOG - CCM Clock Gating Register */ +/*! @{ */ + +#define CCM_CCGR_TOG_SETTING0_MASK (0x3U) +#define CCM_CCGR_TOG_SETTING0_SHIFT (0U) +/*! SETTING0 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_TOG_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING0_SHIFT)) & CCM_CCGR_TOG_SETTING0_MASK) + +#define CCM_CCGR_TOG_SETTING1_MASK (0x30U) +#define CCM_CCGR_TOG_SETTING1_SHIFT (4U) +/*! SETTING1 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_TOG_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING1_SHIFT)) & CCM_CCGR_TOG_SETTING1_MASK) + +#define CCM_CCGR_TOG_SETTING2_MASK (0x300U) +#define CCM_CCGR_TOG_SETTING2_SHIFT (8U) +/*! SETTING2 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_TOG_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING2_SHIFT)) & CCM_CCGR_TOG_SETTING2_MASK) + +#define CCM_CCGR_TOG_SETTING3_MASK (0x3000U) +#define CCM_CCGR_TOG_SETTING3_SHIFT (12U) +/*! SETTING3 + * 0b00..Domain clocks not needed + * 0b01..Domain clocks needed when in RUN + * 0b10..Domain clocks needed when in RUN and WAIT + * 0b11..Domain clocks needed all the time + */ +#define CCM_CCGR_TOG_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING3_SHIFT)) & CCM_CCGR_TOG_SETTING3_MASK) +/*! @} */ + +/* The count of CCM_CCGR_TOG */ +#define CCM_CCGR_TOG_COUNT (191U) + +/*! @name TARGET_ROOT - Target Register */ +/*! @{ */ + +#define CCM_TARGET_ROOT_POST_PODF_MASK (0x3FU) +#define CCM_TARGET_ROOT_POST_PODF_SHIFT (0U) +/*! POST_PODF + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b111111..Divide by 64 + */ +#define CCM_TARGET_ROOT_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_POST_PODF_MASK) + +#define CCM_TARGET_ROOT_PRE_PODF_MASK (0x70000U) +#define CCM_TARGET_ROOT_PRE_PODF_SHIFT (16U) +/*! PRE_PODF + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_TARGET_ROOT_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_PRE_PODF_MASK) + +#define CCM_TARGET_ROOT_MUX_MASK (0x7000000U) +#define CCM_TARGET_ROOT_MUX_SHIFT (24U) +#define CCM_TARGET_ROOT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_MUX_SHIFT)) & CCM_TARGET_ROOT_MUX_MASK) + +#define CCM_TARGET_ROOT_ENABLE_MASK (0x10000000U) +#define CCM_TARGET_ROOT_ENABLE_SHIFT (28U) +/*! ENABLE + * 0b0..clock root is OFF + * 0b1..clock root is ON + */ +#define CCM_TARGET_ROOT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_ENABLE_SHIFT)) & CCM_TARGET_ROOT_ENABLE_MASK) +/*! @} */ + +/* The count of CCM_TARGET_ROOT */ +#define CCM_TARGET_ROOT_COUNT (142U) + +/*! @name TARGET_ROOT_SET - Target Register */ +/*! @{ */ + +#define CCM_TARGET_ROOT_SET_POST_PODF_MASK (0x3FU) +#define CCM_TARGET_ROOT_SET_POST_PODF_SHIFT (0U) +/*! POST_PODF + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b111111..Divide by 64 + */ +#define CCM_TARGET_ROOT_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_POST_PODF_MASK) + +#define CCM_TARGET_ROOT_SET_PRE_PODF_MASK (0x70000U) +#define CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT (16U) +/*! PRE_PODF + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_TARGET_ROOT_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_PRE_PODF_MASK) + +#define CCM_TARGET_ROOT_SET_MUX_MASK (0x7000000U) +#define CCM_TARGET_ROOT_SET_MUX_SHIFT (24U) +#define CCM_TARGET_ROOT_SET_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_MUX_SHIFT)) & CCM_TARGET_ROOT_SET_MUX_MASK) + +#define CCM_TARGET_ROOT_SET_ENABLE_MASK (0x10000000U) +#define CCM_TARGET_ROOT_SET_ENABLE_SHIFT (28U) +/*! ENABLE + * 0b0..clock root is OFF + * 0b1..clock root is ON + */ +#define CCM_TARGET_ROOT_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_ENABLE_SHIFT)) & CCM_TARGET_ROOT_SET_ENABLE_MASK) +/*! @} */ + +/* The count of CCM_TARGET_ROOT_SET */ +#define CCM_TARGET_ROOT_SET_COUNT (142U) + +/*! @name TARGET_ROOT_CLR - Target Register */ +/*! @{ */ + +#define CCM_TARGET_ROOT_CLR_POST_PODF_MASK (0x3FU) +#define CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT (0U) +/*! POST_PODF + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b111111..Divide by 64 + */ +#define CCM_TARGET_ROOT_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_POST_PODF_MASK) + +#define CCM_TARGET_ROOT_CLR_PRE_PODF_MASK (0x70000U) +#define CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT (16U) +/*! PRE_PODF + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_TARGET_ROOT_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_PRE_PODF_MASK) + +#define CCM_TARGET_ROOT_CLR_MUX_MASK (0x7000000U) +#define CCM_TARGET_ROOT_CLR_MUX_SHIFT (24U) +#define CCM_TARGET_ROOT_CLR_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_MUX_SHIFT)) & CCM_TARGET_ROOT_CLR_MUX_MASK) + +#define CCM_TARGET_ROOT_CLR_ENABLE_MASK (0x10000000U) +#define CCM_TARGET_ROOT_CLR_ENABLE_SHIFT (28U) +/*! ENABLE + * 0b0..clock root is OFF + * 0b1..clock root is ON + */ +#define CCM_TARGET_ROOT_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_ENABLE_SHIFT)) & CCM_TARGET_ROOT_CLR_ENABLE_MASK) +/*! @} */ + +/* The count of CCM_TARGET_ROOT_CLR */ +#define CCM_TARGET_ROOT_CLR_COUNT (142U) + +/*! @name TARGET_ROOT_TOG - Target Register */ +/*! @{ */ + +#define CCM_TARGET_ROOT_TOG_POST_PODF_MASK (0x3FU) +#define CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT (0U) +/*! POST_PODF + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b111111..Divide by 64 + */ +#define CCM_TARGET_ROOT_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_POST_PODF_MASK) + +#define CCM_TARGET_ROOT_TOG_PRE_PODF_MASK (0x70000U) +#define CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT (16U) +/*! PRE_PODF + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_TARGET_ROOT_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_PRE_PODF_MASK) + +#define CCM_TARGET_ROOT_TOG_MUX_MASK (0x7000000U) +#define CCM_TARGET_ROOT_TOG_MUX_SHIFT (24U) +#define CCM_TARGET_ROOT_TOG_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_MUX_SHIFT)) & CCM_TARGET_ROOT_TOG_MUX_MASK) + +#define CCM_TARGET_ROOT_TOG_ENABLE_MASK (0x10000000U) +#define CCM_TARGET_ROOT_TOG_ENABLE_SHIFT (28U) +/*! ENABLE + * 0b0..clock root is OFF + * 0b1..clock root is ON + */ +#define CCM_TARGET_ROOT_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_ENABLE_SHIFT)) & CCM_TARGET_ROOT_TOG_ENABLE_MASK) +/*! @} */ + +/* The count of CCM_TARGET_ROOT_TOG */ +#define CCM_TARGET_ROOT_TOG_COUNT (142U) + +/*! @name MISC - Miscellaneous Register */ +/*! @{ */ + +#define CCM_MISC_AUTHEN_FAIL_MASK (0x1U) +#define CCM_MISC_AUTHEN_FAIL_SHIFT (0U) +#define CCM_MISC_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_AUTHEN_FAIL_SHIFT)) & CCM_MISC_AUTHEN_FAIL_MASK) + +#define CCM_MISC_TIMEOUT_MASK (0x10U) +#define CCM_MISC_TIMEOUT_SHIFT (4U) +#define CCM_MISC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_TIMEOUT_SHIFT)) & CCM_MISC_TIMEOUT_MASK) + +#define CCM_MISC_VIOLATE_MASK (0x100U) +#define CCM_MISC_VIOLATE_SHIFT (8U) +#define CCM_MISC_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_VIOLATE_SHIFT)) & CCM_MISC_VIOLATE_MASK) +/*! @} */ + +/* The count of CCM_MISC */ +#define CCM_MISC_COUNT (142U) + +/*! @name MISC_ROOT_SET - Miscellaneous Register */ +/*! @{ */ + +#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK (0x1U) +#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT (0U) +#define CCM_MISC_ROOT_SET_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK) + +#define CCM_MISC_ROOT_SET_TIMEOUT_MASK (0x10U) +#define CCM_MISC_ROOT_SET_TIMEOUT_SHIFT (4U) +#define CCM_MISC_ROOT_SET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_SET_TIMEOUT_MASK) + +#define CCM_MISC_ROOT_SET_VIOLATE_MASK (0x100U) +#define CCM_MISC_ROOT_SET_VIOLATE_SHIFT (8U) +#define CCM_MISC_ROOT_SET_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_VIOLATE_SHIFT)) & CCM_MISC_ROOT_SET_VIOLATE_MASK) +/*! @} */ + +/* The count of CCM_MISC_ROOT_SET */ +#define CCM_MISC_ROOT_SET_COUNT (142U) + +/*! @name MISC_ROOT_CLR - Miscellaneous Register */ +/*! @{ */ + +#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK (0x1U) +#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT (0U) +#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK) + +#define CCM_MISC_ROOT_CLR_TIMEOUT_MASK (0x10U) +#define CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT (4U) +#define CCM_MISC_ROOT_CLR_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_CLR_TIMEOUT_MASK) + +#define CCM_MISC_ROOT_CLR_VIOLATE_MASK (0x100U) +#define CCM_MISC_ROOT_CLR_VIOLATE_SHIFT (8U) +#define CCM_MISC_ROOT_CLR_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_VIOLATE_SHIFT)) & CCM_MISC_ROOT_CLR_VIOLATE_MASK) +/*! @} */ + +/* The count of CCM_MISC_ROOT_CLR */ +#define CCM_MISC_ROOT_CLR_COUNT (142U) + +/*! @name MISC_ROOT_TOG - Miscellaneous Register */ +/*! @{ */ + +#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK (0x1U) +#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT (0U) +#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK) + +#define CCM_MISC_ROOT_TOG_TIMEOUT_MASK (0x10U) +#define CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT (4U) +#define CCM_MISC_ROOT_TOG_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_TOG_TIMEOUT_MASK) + +#define CCM_MISC_ROOT_TOG_VIOLATE_MASK (0x100U) +#define CCM_MISC_ROOT_TOG_VIOLATE_SHIFT (8U) +#define CCM_MISC_ROOT_TOG_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_VIOLATE_SHIFT)) & CCM_MISC_ROOT_TOG_VIOLATE_MASK) +/*! @} */ + +/* The count of CCM_MISC_ROOT_TOG */ +#define CCM_MISC_ROOT_TOG_COUNT (142U) + +/*! @name POST - Post Divider Register */ +/*! @{ */ + +#define CCM_POST_POST_PODF_MASK (0x3FU) +#define CCM_POST_POST_PODF_SHIFT (0U) +/*! POST_PODF + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b111111..Divide by 64 + */ +#define CCM_POST_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_POST_PODF_SHIFT)) & CCM_POST_POST_PODF_MASK) + +#define CCM_POST_BUSY1_MASK (0x80U) +#define CCM_POST_BUSY1_SHIFT (7U) +#define CCM_POST_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY1_SHIFT)) & CCM_POST_BUSY1_MASK) + +#define CCM_POST_SELECT_MASK (0x10000000U) +#define CCM_POST_SELECT_SHIFT (28U) +/*! SELECT + * 0b0..select branch A + * 0b1..select branch B + */ +#define CCM_POST_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_SELECT_SHIFT)) & CCM_POST_SELECT_MASK) + +#define CCM_POST_BUSY2_MASK (0x80000000U) +#define CCM_POST_BUSY2_SHIFT (31U) +#define CCM_POST_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY2_SHIFT)) & CCM_POST_BUSY2_MASK) +/*! @} */ + +/* The count of CCM_POST */ +#define CCM_POST_COUNT (142U) + +/*! @name POST_ROOT_SET - Post Divider Register */ +/*! @{ */ + +#define CCM_POST_ROOT_SET_POST_PODF_MASK (0x3FU) +#define CCM_POST_ROOT_SET_POST_PODF_SHIFT (0U) +/*! POST_PODF + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b111111..Divide by 64 + */ +#define CCM_POST_ROOT_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_POST_PODF_SHIFT)) & CCM_POST_ROOT_SET_POST_PODF_MASK) + +#define CCM_POST_ROOT_SET_BUSY1_MASK (0x80U) +#define CCM_POST_ROOT_SET_BUSY1_SHIFT (7U) +#define CCM_POST_ROOT_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY1_SHIFT)) & CCM_POST_ROOT_SET_BUSY1_MASK) + +#define CCM_POST_ROOT_SET_SELECT_MASK (0x10000000U) +#define CCM_POST_ROOT_SET_SELECT_SHIFT (28U) +/*! SELECT + * 0b0..select branch A + * 0b1..select branch B + */ +#define CCM_POST_ROOT_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_SELECT_SHIFT)) & CCM_POST_ROOT_SET_SELECT_MASK) + +#define CCM_POST_ROOT_SET_BUSY2_MASK (0x80000000U) +#define CCM_POST_ROOT_SET_BUSY2_SHIFT (31U) +#define CCM_POST_ROOT_SET_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY2_SHIFT)) & CCM_POST_ROOT_SET_BUSY2_MASK) +/*! @} */ + +/* The count of CCM_POST_ROOT_SET */ +#define CCM_POST_ROOT_SET_COUNT (142U) + +/*! @name POST_ROOT_CLR - Post Divider Register */ +/*! @{ */ + +#define CCM_POST_ROOT_CLR_POST_PODF_MASK (0x3FU) +#define CCM_POST_ROOT_CLR_POST_PODF_SHIFT (0U) +/*! POST_PODF + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b111111..Divide by 64 + */ +#define CCM_POST_ROOT_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_POST_PODF_SHIFT)) & CCM_POST_ROOT_CLR_POST_PODF_MASK) + +#define CCM_POST_ROOT_CLR_BUSY1_MASK (0x80U) +#define CCM_POST_ROOT_CLR_BUSY1_SHIFT (7U) +#define CCM_POST_ROOT_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY1_SHIFT)) & CCM_POST_ROOT_CLR_BUSY1_MASK) + +#define CCM_POST_ROOT_CLR_SELECT_MASK (0x10000000U) +#define CCM_POST_ROOT_CLR_SELECT_SHIFT (28U) +/*! SELECT + * 0b0..select branch A + * 0b1..select branch B + */ +#define CCM_POST_ROOT_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_SELECT_SHIFT)) & CCM_POST_ROOT_CLR_SELECT_MASK) + +#define CCM_POST_ROOT_CLR_BUSY2_MASK (0x80000000U) +#define CCM_POST_ROOT_CLR_BUSY2_SHIFT (31U) +#define CCM_POST_ROOT_CLR_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY2_SHIFT)) & CCM_POST_ROOT_CLR_BUSY2_MASK) +/*! @} */ + +/* The count of CCM_POST_ROOT_CLR */ +#define CCM_POST_ROOT_CLR_COUNT (142U) + +/*! @name POST_ROOT_TOG - Post Divider Register */ +/*! @{ */ + +#define CCM_POST_ROOT_TOG_POST_PODF_MASK (0x3FU) +#define CCM_POST_ROOT_TOG_POST_PODF_SHIFT (0U) +/*! POST_PODF + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b111111..Divide by 64 + */ +#define CCM_POST_ROOT_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_POST_PODF_SHIFT)) & CCM_POST_ROOT_TOG_POST_PODF_MASK) + +#define CCM_POST_ROOT_TOG_BUSY1_MASK (0x80U) +#define CCM_POST_ROOT_TOG_BUSY1_SHIFT (7U) +#define CCM_POST_ROOT_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY1_SHIFT)) & CCM_POST_ROOT_TOG_BUSY1_MASK) + +#define CCM_POST_ROOT_TOG_SELECT_MASK (0x10000000U) +#define CCM_POST_ROOT_TOG_SELECT_SHIFT (28U) +/*! SELECT + * 0b0..select branch A + * 0b1..select branch B + */ +#define CCM_POST_ROOT_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_SELECT_SHIFT)) & CCM_POST_ROOT_TOG_SELECT_MASK) + +#define CCM_POST_ROOT_TOG_BUSY2_MASK (0x80000000U) +#define CCM_POST_ROOT_TOG_BUSY2_SHIFT (31U) +#define CCM_POST_ROOT_TOG_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY2_SHIFT)) & CCM_POST_ROOT_TOG_BUSY2_MASK) +/*! @} */ + +/* The count of CCM_POST_ROOT_TOG */ +#define CCM_POST_ROOT_TOG_COUNT (142U) + +/*! @name PRE - Pre Divider Register */ +/*! @{ */ + +#define CCM_PRE_PRE_PODF_B_MASK (0x7U) +#define CCM_PRE_PRE_PODF_B_SHIFT (0U) +/*! PRE_PODF_B + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_PRE_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_B_SHIFT)) & CCM_PRE_PRE_PODF_B_MASK) + +#define CCM_PRE_BUSY0_MASK (0x8U) +#define CCM_PRE_BUSY0_SHIFT (3U) +#define CCM_PRE_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY0_SHIFT)) & CCM_PRE_BUSY0_MASK) + +#define CCM_PRE_MUX_B_MASK (0x700U) +#define CCM_PRE_MUX_B_SHIFT (8U) +#define CCM_PRE_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_B_SHIFT)) & CCM_PRE_MUX_B_MASK) + +#define CCM_PRE_EN_B_MASK (0x1000U) +#define CCM_PRE_EN_B_SHIFT (12U) +/*! EN_B + * 0b0..Clock shutdown + * 0b1..Clock ON + */ +#define CCM_PRE_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_B_SHIFT)) & CCM_PRE_EN_B_MASK) + +#define CCM_PRE_BUSY1_MASK (0x8000U) +#define CCM_PRE_BUSY1_SHIFT (15U) +#define CCM_PRE_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY1_SHIFT)) & CCM_PRE_BUSY1_MASK) + +#define CCM_PRE_PRE_PODF_A_MASK (0x70000U) +#define CCM_PRE_PRE_PODF_A_SHIFT (16U) +/*! PRE_PODF_A + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_PRE_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_A_SHIFT)) & CCM_PRE_PRE_PODF_A_MASK) + +#define CCM_PRE_BUSY3_MASK (0x80000U) +#define CCM_PRE_BUSY3_SHIFT (19U) +#define CCM_PRE_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY3_SHIFT)) & CCM_PRE_BUSY3_MASK) + +#define CCM_PRE_MUX_A_MASK (0x7000000U) +#define CCM_PRE_MUX_A_SHIFT (24U) +#define CCM_PRE_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_A_SHIFT)) & CCM_PRE_MUX_A_MASK) + +#define CCM_PRE_EN_A_MASK (0x10000000U) +#define CCM_PRE_EN_A_SHIFT (28U) +/*! EN_A + * 0b0..Clock shutdown + * 0b1..clock ON + */ +#define CCM_PRE_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_A_SHIFT)) & CCM_PRE_EN_A_MASK) + +#define CCM_PRE_BUSY4_MASK (0x80000000U) +#define CCM_PRE_BUSY4_SHIFT (31U) +#define CCM_PRE_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY4_SHIFT)) & CCM_PRE_BUSY4_MASK) +/*! @} */ + +/* The count of CCM_PRE */ +#define CCM_PRE_COUNT (142U) + +/*! @name PRE_ROOT_SET - Pre Divider Register */ +/*! @{ */ + +#define CCM_PRE_ROOT_SET_PRE_PODF_B_MASK (0x7U) +#define CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT (0U) +/*! PRE_PODF_B + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_PRE_ROOT_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_B_MASK) + +#define CCM_PRE_ROOT_SET_BUSY0_MASK (0x8U) +#define CCM_PRE_ROOT_SET_BUSY0_SHIFT (3U) +#define CCM_PRE_ROOT_SET_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY0_SHIFT)) & CCM_PRE_ROOT_SET_BUSY0_MASK) + +#define CCM_PRE_ROOT_SET_MUX_B_MASK (0x700U) +#define CCM_PRE_ROOT_SET_MUX_B_SHIFT (8U) +#define CCM_PRE_ROOT_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_B_SHIFT)) & CCM_PRE_ROOT_SET_MUX_B_MASK) + +#define CCM_PRE_ROOT_SET_EN_B_MASK (0x1000U) +#define CCM_PRE_ROOT_SET_EN_B_SHIFT (12U) +/*! EN_B + * 0b0..Clock shutdown + * 0b1..Clock ON + */ +#define CCM_PRE_ROOT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_B_SHIFT)) & CCM_PRE_ROOT_SET_EN_B_MASK) + +#define CCM_PRE_ROOT_SET_BUSY1_MASK (0x8000U) +#define CCM_PRE_ROOT_SET_BUSY1_SHIFT (15U) +#define CCM_PRE_ROOT_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY1_SHIFT)) & CCM_PRE_ROOT_SET_BUSY1_MASK) + +#define CCM_PRE_ROOT_SET_PRE_PODF_A_MASK (0x70000U) +#define CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT (16U) +/*! PRE_PODF_A + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_PRE_ROOT_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_A_MASK) + +#define CCM_PRE_ROOT_SET_BUSY3_MASK (0x80000U) +#define CCM_PRE_ROOT_SET_BUSY3_SHIFT (19U) +#define CCM_PRE_ROOT_SET_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY3_SHIFT)) & CCM_PRE_ROOT_SET_BUSY3_MASK) + +#define CCM_PRE_ROOT_SET_MUX_A_MASK (0x7000000U) +#define CCM_PRE_ROOT_SET_MUX_A_SHIFT (24U) +#define CCM_PRE_ROOT_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_A_SHIFT)) & CCM_PRE_ROOT_SET_MUX_A_MASK) + +#define CCM_PRE_ROOT_SET_EN_A_MASK (0x10000000U) +#define CCM_PRE_ROOT_SET_EN_A_SHIFT (28U) +/*! EN_A + * 0b0..Clock shutdown + * 0b1..clock ON + */ +#define CCM_PRE_ROOT_SET_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_A_SHIFT)) & CCM_PRE_ROOT_SET_EN_A_MASK) + +#define CCM_PRE_ROOT_SET_BUSY4_MASK (0x80000000U) +#define CCM_PRE_ROOT_SET_BUSY4_SHIFT (31U) +#define CCM_PRE_ROOT_SET_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY4_SHIFT)) & CCM_PRE_ROOT_SET_BUSY4_MASK) +/*! @} */ + +/* The count of CCM_PRE_ROOT_SET */ +#define CCM_PRE_ROOT_SET_COUNT (142U) + +/*! @name PRE_ROOT_CLR - Pre Divider Register */ +/*! @{ */ + +#define CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK (0x7U) +#define CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT (0U) +/*! PRE_PODF_B + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_PRE_ROOT_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK) + +#define CCM_PRE_ROOT_CLR_BUSY0_MASK (0x8U) +#define CCM_PRE_ROOT_CLR_BUSY0_SHIFT (3U) +#define CCM_PRE_ROOT_CLR_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY0_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY0_MASK) + +#define CCM_PRE_ROOT_CLR_MUX_B_MASK (0x700U) +#define CCM_PRE_ROOT_CLR_MUX_B_SHIFT (8U) +#define CCM_PRE_ROOT_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_B_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_B_MASK) + +#define CCM_PRE_ROOT_CLR_EN_B_MASK (0x1000U) +#define CCM_PRE_ROOT_CLR_EN_B_SHIFT (12U) +/*! EN_B + * 0b0..Clock shutdown + * 0b1..Clock ON + */ +#define CCM_PRE_ROOT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_B_SHIFT)) & CCM_PRE_ROOT_CLR_EN_B_MASK) + +#define CCM_PRE_ROOT_CLR_BUSY1_MASK (0x8000U) +#define CCM_PRE_ROOT_CLR_BUSY1_SHIFT (15U) +#define CCM_PRE_ROOT_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY1_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY1_MASK) + +#define CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK (0x70000U) +#define CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT (16U) +/*! PRE_PODF_A + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_PRE_ROOT_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK) + +#define CCM_PRE_ROOT_CLR_BUSY3_MASK (0x80000U) +#define CCM_PRE_ROOT_CLR_BUSY3_SHIFT (19U) +#define CCM_PRE_ROOT_CLR_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY3_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY3_MASK) + +#define CCM_PRE_ROOT_CLR_MUX_A_MASK (0x7000000U) +#define CCM_PRE_ROOT_CLR_MUX_A_SHIFT (24U) +#define CCM_PRE_ROOT_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_A_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_A_MASK) + +#define CCM_PRE_ROOT_CLR_EN_A_MASK (0x10000000U) +#define CCM_PRE_ROOT_CLR_EN_A_SHIFT (28U) +/*! EN_A + * 0b0..Clock shutdown + * 0b1..clock ON + */ +#define CCM_PRE_ROOT_CLR_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_A_SHIFT)) & CCM_PRE_ROOT_CLR_EN_A_MASK) + +#define CCM_PRE_ROOT_CLR_BUSY4_MASK (0x80000000U) +#define CCM_PRE_ROOT_CLR_BUSY4_SHIFT (31U) +#define CCM_PRE_ROOT_CLR_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY4_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY4_MASK) +/*! @} */ + +/* The count of CCM_PRE_ROOT_CLR */ +#define CCM_PRE_ROOT_CLR_COUNT (142U) + +/*! @name PRE_ROOT_TOG - Pre Divider Register */ +/*! @{ */ + +#define CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK (0x7U) +#define CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT (0U) +/*! PRE_PODF_B + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_PRE_ROOT_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK) + +#define CCM_PRE_ROOT_TOG_BUSY0_MASK (0x8U) +#define CCM_PRE_ROOT_TOG_BUSY0_SHIFT (3U) +#define CCM_PRE_ROOT_TOG_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY0_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY0_MASK) + +#define CCM_PRE_ROOT_TOG_MUX_B_MASK (0x700U) +#define CCM_PRE_ROOT_TOG_MUX_B_SHIFT (8U) +#define CCM_PRE_ROOT_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_B_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_B_MASK) + +#define CCM_PRE_ROOT_TOG_EN_B_MASK (0x1000U) +#define CCM_PRE_ROOT_TOG_EN_B_SHIFT (12U) +/*! EN_B + * 0b0..Clock shutdown + * 0b1..Clock ON + */ +#define CCM_PRE_ROOT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_B_SHIFT)) & CCM_PRE_ROOT_TOG_EN_B_MASK) + +#define CCM_PRE_ROOT_TOG_BUSY1_MASK (0x8000U) +#define CCM_PRE_ROOT_TOG_BUSY1_SHIFT (15U) +#define CCM_PRE_ROOT_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY1_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY1_MASK) + +#define CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK (0x70000U) +#define CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT (16U) +/*! PRE_PODF_A + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_PRE_ROOT_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK) + +#define CCM_PRE_ROOT_TOG_BUSY3_MASK (0x80000U) +#define CCM_PRE_ROOT_TOG_BUSY3_SHIFT (19U) +#define CCM_PRE_ROOT_TOG_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY3_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY3_MASK) + +#define CCM_PRE_ROOT_TOG_MUX_A_MASK (0x7000000U) +#define CCM_PRE_ROOT_TOG_MUX_A_SHIFT (24U) +#define CCM_PRE_ROOT_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_A_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_A_MASK) + +#define CCM_PRE_ROOT_TOG_EN_A_MASK (0x10000000U) +#define CCM_PRE_ROOT_TOG_EN_A_SHIFT (28U) +/*! EN_A + * 0b0..Clock shutdown + * 0b1..clock ON + */ +#define CCM_PRE_ROOT_TOG_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_A_SHIFT)) & CCM_PRE_ROOT_TOG_EN_A_MASK) + +#define CCM_PRE_ROOT_TOG_BUSY4_MASK (0x80000000U) +#define CCM_PRE_ROOT_TOG_BUSY4_SHIFT (31U) +#define CCM_PRE_ROOT_TOG_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY4_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY4_MASK) +/*! @} */ + +/* The count of CCM_PRE_ROOT_TOG */ +#define CCM_PRE_ROOT_TOG_COUNT (142U) + +/*! @name ACCESS_CTRL - Access Control Register */ +/*! @{ */ + +#define CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK (0xFU) +#define CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT (0U) +#define CCM_ACCESS_CTRL_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK) + +#define CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK (0xF0U) +#define CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT (4U) +#define CCM_ACCESS_CTRL_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK) + +#define CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK (0xF00U) +#define CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT (8U) +#define CCM_ACCESS_CTRL_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK) + +#define CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK (0xF000U) +#define CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT (12U) +#define CCM_ACCESS_CTRL_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK) + +#define CCM_ACCESS_CTRL_OWNER_ID_MASK (0x30000U) +#define CCM_ACCESS_CTRL_OWNER_ID_SHIFT (16U) +/*! OWNER_ID + * 0b00..domaino + * 0b01..domain1 + * 0b10..domain2 + * 0b11..domain3 + */ +#define CCM_ACCESS_CTRL_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_OWNER_ID_MASK) + +#define CCM_ACCESS_CTRL_MUTEX_MASK (0x100000U) +#define CCM_ACCESS_CTRL_MUTEX_SHIFT (20U) +/*! MUTEX + * 0b0..Semaphore is free to take + * 0b1..Semaphore is taken + */ +#define CCM_ACCESS_CTRL_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_MUTEX_MASK) + +#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK (0x1000000U) +#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT (24U) +/*! DOMAIN0_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK (0x2000000U) +#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT (25U) +/*! DOMAIN1_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK (0x4000000U) +#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT (26U) +/*! DOMAIN2_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK (0x8000000U) +#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT (27U) +/*! DOMAIN3_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_SEMA_EN_MASK (0x10000000U) +#define CCM_ACCESS_CTRL_SEMA_EN_SHIFT (28U) +/*! SEMA_EN + * 0b0..Disable + * 0b1..Enable + */ +#define CCM_ACCESS_CTRL_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_SEMA_EN_MASK) + +#define CCM_ACCESS_CTRL_LOCK_MASK (0x80000000U) +#define CCM_ACCESS_CTRL_LOCK_SHIFT (31U) +/*! LOCK + * 0b0..Access control inactive + * 0b1..Access control active + */ +#define CCM_ACCESS_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_LOCK_SHIFT)) & CCM_ACCESS_CTRL_LOCK_MASK) +/*! @} */ + +/* The count of CCM_ACCESS_CTRL */ +#define CCM_ACCESS_CTRL_COUNT (142U) + +/*! @name ACCESS_CTRL_ROOT_SET - Access Control Register */ +/*! @{ */ + +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK (0xFU) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT (0U) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK) + +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK (0xF0U) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT (4U) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK) + +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK (0xF00U) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT (8U) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK) + +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK (0xF000U) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT (12U) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK) + +#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK (0x30000U) +#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT (16U) +/*! OWNER_ID + * 0b00..domaino + * 0b01..domain1 + * 0b10..domain2 + * 0b11..domain3 + */ +#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK) + +#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK (0x100000U) +#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT (20U) +/*! MUTEX + * 0b0..Semaphore is free to take + * 0b1..Semaphore is taken + */ +#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK) + +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK (0x1000000U) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT (24U) +/*! DOMAIN0_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK (0x2000000U) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT (25U) +/*! DOMAIN1_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK (0x4000000U) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT (26U) +/*! DOMAIN2_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK (0x8000000U) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT (27U) +/*! DOMAIN3_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK (0x10000000U) +#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT (28U) +/*! SEMA_EN + * 0b0..Disable + * 0b1..Enable + */ +#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK) + +#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK (0x80000000U) +#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT (31U) +/*! LOCK + * 0b0..Access control inactive + * 0b1..Access control active + */ +#define CCM_ACCESS_CTRL_ROOT_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK) +/*! @} */ + +/* The count of CCM_ACCESS_CTRL_ROOT_SET */ +#define CCM_ACCESS_CTRL_ROOT_SET_COUNT (142U) + +/*! @name ACCESS_CTRL_ROOT_CLR - Access Control Register */ +/*! @{ */ + +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK (0xFU) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT (0U) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK) + +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK (0xF0U) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT (4U) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK) + +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK (0xF00U) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT (8U) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK) + +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK (0xF000U) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT (12U) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK) + +#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK (0x30000U) +#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT (16U) +/*! OWNER_ID + * 0b00..domaino + * 0b01..domain1 + * 0b10..domain2 + * 0b11..domain3 + */ +#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK) + +#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK (0x100000U) +#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT (20U) +/*! MUTEX + * 0b0..Semaphore is free to take + * 0b1..Semaphore is taken + */ +#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK) + +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK (0x1000000U) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT (24U) +/*! DOMAIN0_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK (0x2000000U) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT (25U) +/*! DOMAIN1_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK (0x4000000U) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT (26U) +/*! DOMAIN2_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK (0x8000000U) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT (27U) +/*! DOMAIN3_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK (0x10000000U) +#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT (28U) +/*! SEMA_EN + * 0b0..Disable + * 0b1..Enable + */ +#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK) + +#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK (0x80000000U) +#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT (31U) +/*! LOCK + * 0b0..Access control inactive + * 0b1..Access control active + */ +#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK) +/*! @} */ + +/* The count of CCM_ACCESS_CTRL_ROOT_CLR */ +#define CCM_ACCESS_CTRL_ROOT_CLR_COUNT (142U) + +/*! @name ACCESS_CTRL_ROOT_TOG - Access Control Register */ +/*! @{ */ + +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK (0xFU) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT (0U) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK) + +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK (0xF0U) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT (4U) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK) + +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK (0xF00U) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT (8U) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK) + +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK (0xF000U) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT (12U) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK) + +#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK (0x30000U) +#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT (16U) +/*! OWNER_ID + * 0b00..domaino + * 0b01..domain1 + * 0b10..domain2 + * 0b11..domain3 + */ +#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK) + +#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK (0x100000U) +#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT (20U) +/*! MUTEX + * 0b0..Semaphore is free to take + * 0b1..Semaphore is taken + */ +#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK) + +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK (0x1000000U) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT (24U) +/*! DOMAIN0_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK (0x2000000U) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT (25U) +/*! DOMAIN1_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK (0x4000000U) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT (26U) +/*! DOMAIN2_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK (0x8000000U) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT (27U) +/*! DOMAIN3_WHITELIST + * 0b0..Domain cannot change the setting + * 0b1..Domain can change the setting + */ +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK) + +#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK (0x10000000U) +#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT (28U) +/*! SEMA_EN + * 0b0..Disable + * 0b1..Enable + */ +#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK) + +#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK (0x80000000U) +#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT (31U) +/*! LOCK + * 0b0..Access control inactive + * 0b1..Access control active + */ +#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK) +/*! @} */ + +/* The count of CCM_ACCESS_CTRL_ROOT_TOG */ +#define CCM_ACCESS_CTRL_ROOT_TOG_COUNT (142U) + + +/*! + * @} + */ /* end of group CCM_Register_Masks */ + + +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM base address */ +#define CCM_BASE (0x30380000u) +/** Peripheral CCM base pointer */ +#define CCM ((CCM_Type *)CCM_BASE) +/** Array initializer of CCM peripheral base addresses */ +#define CCM_BASE_ADDRS { CCM_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM } +/** Interrupt vectors for the CCM peripheral type */ +#define CCM_IRQS { CCM_IRQ1_IRQn, CCM_IRQ2_IRQn } + +/*! + * @} + */ /* end of group CCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer + * @{ + */ + +/** CCM_ANALOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t AUDIO_PLL1_CFG0; /**< AUDIO PLL1 Configuration 0 Register, offset: 0x0 */ + __IO uint32_t AUDIO_PLL1_CFG1; /**< AUDIO PLL1 Configuration 1 Register, offset: 0x4 */ + __IO uint32_t AUDIO_PLL2_CFG0; /**< AUDIO PLL2 Configuration 0 Register, offset: 0x8 */ + __IO uint32_t AUDIO_PLL2_CFG1; /**< AUDIO PLL2 Configuration 1 Register, offset: 0xC */ + __IO uint32_t VIDEO_PLL1_CFG0; /**< VIDEO PLL Configuration 0 Register, offset: 0x10 */ + __IO uint32_t VIDEO_PLL1_CFG1; /**< VIDEO PLL Configuration 1 Register, offset: 0x14 */ + __IO uint32_t GPU_PLL_CFG0; /**< GPU PLL Configuration 0 Register, offset: 0x18 */ + __IO uint32_t GPU_PLL_CFG1; /**< GPU PLL Configuration 1 Register, offset: 0x1C */ + __IO uint32_t VPU_PLL_CFG0; /**< VPU PLL Configuration 0 Register, offset: 0x20 */ + __IO uint32_t VPU_PLL_CFG1; /**< VPU PLL Configuration 1 Register, offset: 0x24 */ + __IO uint32_t ARM_PLL_CFG0; /**< ARM PLL Configuration 0 Register, offset: 0x28 */ + __IO uint32_t ARM_PLL_CFG1; /**< ARM PLL Configuration 1 Register, offset: 0x2C */ + __IO uint32_t SYS_PLL1_CFG0; /**< System PLL Configuration 0 Register, offset: 0x30 */ + __IO uint32_t SYS_PLL1_CFG1; /**< System_PLL Configuration 1 Register, offset: 0x34 */ + __IO uint32_t SYS_PLL1_CFG2; /**< System_PLL Configuration 2 Register, offset: 0x38 */ + __IO uint32_t SYS_PLL2_CFG0; /**< System PLL Configuration 0 Register, offset: 0x3C */ + __IO uint32_t SYS_PLL2_CFG1; /**< System_PLL Configuration 1 Register, offset: 0x40 */ + __IO uint32_t SYS_PLL2_CFG2; /**< System_PLL Configuration 2 Register, offset: 0x44 */ + __IO uint32_t SYS_PLL3_CFG0; /**< System PLL Configuration 0 Register, offset: 0x48 */ + __IO uint32_t SYS_PLL3_CFG1; /**< System_PLL Configuration 1 Register, offset: 0x4C */ + __IO uint32_t SYS_PLL3_CFG2; /**< System_PLL Configuration 2 Register, offset: 0x50 */ + __IO uint32_t VIDEO_PLL2_CFG0; /**< VIDEO PLL2 Configuration 0 Register, offset: 0x54 */ + __IO uint32_t VIDEO_PLL2_CFG1; /**< VIDEO PLL2 Configuration 1 Register, offset: 0x58 */ + __IO uint32_t VIDEO_PLL2_CFG2; /**< VIDEO PLL2 Configuration 2 Register, offset: 0x5C */ + __IO uint32_t DRAM_PLL_CFG0; /**< DRAM PLL Configuration 0 Register, offset: 0x60 */ + __IO uint32_t DRAM_PLL_CFG1; /**< DRAM PLL Configuration 1 Register, offset: 0x64 */ + __IO uint32_t DRAM_PLL_CFG2; /**< DRAM PLL Configuration 2 Register, offset: 0x68 */ + __I uint32_t DIGPROG; /**< DIGPROG Register, offset: 0x6C */ + __IO uint32_t OSC_MISC_CFG; /**< Osc Misc Configuration Register, offset: 0x70 */ + __IO uint32_t PLLOUT_MONITOR_CFG; /**< PLLOUT Monitor Configuration Register, offset: 0x74 */ + __IO uint32_t FRAC_PLLOUT_DIV_CFG; /**< Fractional PLLOUT Divider Configuration Register, offset: 0x78 */ + __IO uint32_t SCCG_PLLOUT_DIV_CFG; /**< SCCG PLLOUT Divider Configuration Register, offset: 0x7C */ +} CCM_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/*! @name AUDIO_PLL1_CFG0 - AUDIO PLL1 Configuration 0 Register */ +/*! @{ */ + +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK) + +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK) + +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK (0x800U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_SHIFT (11U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK) + +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_SHIFT (12U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK) + +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U) +/*! PLL_COUNTCLK_SEL + * 0b0..25M_REF_CLK + * 0b1..27M_REF_CLK + */ +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK) + +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_MASK (0x4000U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_SHIFT (14U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_MASK) + +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL_MASK (0x8000U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL_SHIFT (15U) +/*! PLL_LOCK_SEL + * 0b0..Select PLL lock output + * 0b1..Select maximum lock time counter output + */ +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL_MASK) + +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK (0x30000U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT (16U) +/*! PLL_REFCLK_SEL + * 0b00..25M_REF_CLK + * 0b01..27M_REF_CLK + * 0b10..HDMI_PHY_27M_CLK + * 0b11..CLK_P_N + */ +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK) + +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT (18U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE_MASK) + +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_MASK (0x80000U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_SHIFT (19U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_MASK) + +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK) + +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_MASK (0x200000U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_SHIFT (21U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_MASK) + +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SHIFT (31U) +#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_MASK) +/*! @} */ + +/*! @name AUDIO_PLL1_CFG1 - AUDIO PLL1 Configuration 1 Register */ +/*! @{ */ + +#define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU) +#define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT (0U) +#define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK) + +#define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U) +#define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U) +#define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK) +/*! @} */ + +/*! @name AUDIO_PLL2_CFG0 - AUDIO PLL2 Configuration 0 Register */ +/*! @{ */ + +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL_MASK) + +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL_MASK) + +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK_MASK (0x800U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK_SHIFT (11U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK_MASK) + +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL_SHIFT (12U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL_MASK) + +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U) +/*! PLL_COUNTCLK_SEL + * 0b0..25M_REF_CLK + * 0b1..27M_REF_CLK + */ +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK) + +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_MASK (0x4000U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_SHIFT (14U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_MASK) + +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL_MASK (0x8000U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL_SHIFT (15U) +/*! PLL_LOCK_SEL + * 0b0..Select PLL lock output + * 0b1..Select maximum lock time counter output + */ +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL_MASK) + +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL_MASK (0x30000U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT (16U) +/*! PLL_REFCLK_SEL + * 0b00..25M_REF_CLK + * 0b01..27M_REF_CLK + * 0b10..HDMI_PHY_27M_CLK + * 0b11..CLK_P_N + */ +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL_MASK) + +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT (18U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE_MASK) + +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_MASK (0x80000U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_SHIFT (19U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_MASK) + +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK) + +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_MASK (0x200000U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_SHIFT (21U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_MASK) + +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SHIFT (31U) +#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_MASK) +/*! @} */ + +/*! @name AUDIO_PLL2_CFG1 - AUDIO PLL2 Configuration 1 Register */ +/*! @{ */ + +#define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU) +#define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL_SHIFT (0U) +#define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL_MASK) + +#define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U) +#define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U) +#define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL_MASK) +/*! @} */ + +/*! @name VIDEO_PLL1_CFG0 - VIDEO PLL Configuration 0 Register */ +/*! @{ */ + +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK) + +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK) + +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK (0x800U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK_SHIFT (11U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK) + +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL_SHIFT (12U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK) + +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U) +/*! PLL_COUNTCLK_SEL + * 0b0..25M_REF_CLK + * 0b1..27M_REF_CLK + */ +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK) + +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_MASK (0x4000U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_SHIFT (14U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_MASK) + +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL_MASK (0x8000U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL_SHIFT (15U) +/*! PLL_LOCK_SEL + * 0b0..Select PLL lock output + * 0b1..Select maximum lock time counter output + */ +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL_MASK) + +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL_MASK (0x30000U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT (16U) +/*! PLL_REFCLK_SEL + * 0b00..25M_REF_CLK + * 0b01..27M_REF_CLK + * 0b10..HDMI_PHY_27M_CLK + * 0b11..CLK_P_N + */ +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL_MASK) + +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT (18U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE_MASK) + +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_MASK (0x80000U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_SHIFT (19U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_MASK) + +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK) + +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_MASK (0x200000U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_SHIFT (21U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_MASK) + +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SHIFT (31U) +#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_MASK) +/*! @} */ + +/*! @name VIDEO_PLL1_CFG1 - VIDEO PLL Configuration 1 Register */ +/*! @{ */ + +#define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU) +#define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT (0U) +#define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK) + +#define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U) +#define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U) +#define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK) +/*! @} */ + +/*! @name GPU_PLL_CFG0 - GPU PLL Configuration 0 Register */ +/*! @{ */ + +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK) + +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK) + +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK_MASK (0x800U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT (11U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK_MASK) + +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT (12U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL_MASK) + +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U) +/*! PLL_COUNTCLK_SEL + * 0b0..25M_REF_CLK + * 0b1..27M_REF_CLK + */ +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL_MASK) + +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_MASK (0x4000U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_SHIFT (14U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_MASK) + +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL_MASK (0x8000U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL_SHIFT (15U) +/*! PLL_LOCK_SEL + * 0b0..Select PLL lock output + * 0b1..Select maximum lock time counter output + */ +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL_MASK) + +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL_MASK (0x30000U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL_SHIFT (16U) +/*! PLL_REFCLK_SEL + * 0b00..25M_REF_CLK + * 0b01..27M_REF_CLK + * 0b10..HDMI_PHY_27M_CLK + * 0b11..CLK_P_N + */ +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL_MASK) + +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT (18U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE_MASK) + +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_MASK (0x80000U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_SHIFT (19U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_MASK) + +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK) + +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_MASK (0x200000U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_SHIFT (21U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_MASK) + +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SHIFT (31U) +#define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_MASK) +/*! @} */ + +/*! @name GPU_PLL_CFG1 - GPU PLL Configuration 1 Register */ +/*! @{ */ + +#define CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU) +#define CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT (0U) +#define CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL_MASK) + +#define CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U) +#define CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U) +#define CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK) +/*! @} */ + +/*! @name VPU_PLL_CFG0 - VPU PLL Configuration 0 Register */ +/*! @{ */ + +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK) + +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK) + +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK_MASK (0x800U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT (11U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK_MASK) + +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT (12U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL_MASK) + +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U) +/*! PLL_COUNTCLK_SEL + * 0b0..25M_REF_CLK + * 0b1..27M_REF_CLK + */ +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL_MASK) + +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_MASK (0x4000U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_SHIFT (14U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_MASK) + +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL_MASK (0x8000U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL_SHIFT (15U) +/*! PLL_LOCK_SEL + * 0b0..Select PLL lock output + * 0b1..Select maximum lock time counter output + */ +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL_MASK) + +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL_MASK (0x30000U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL_SHIFT (16U) +/*! PLL_REFCLK_SEL + * 0b00..25M_REF_CLK + * 0b01..27M_REF_CLK + * 0b10..HDMI_PHY_27M_CLK + * 0b11..CLK_P_N + */ +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL_MASK) + +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT (18U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE_MASK) + +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_MASK (0x80000U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_SHIFT (19U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_MASK) + +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK) + +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_MASK (0x200000U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_SHIFT (21U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_MASK) + +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SHIFT (31U) +#define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_MASK) +/*! @} */ + +/*! @name VPU_PLL_CFG1 - VPU PLL Configuration 1 Register */ +/*! @{ */ + +#define CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU) +#define CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT (0U) +#define CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL_MASK) + +#define CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U) +#define CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U) +#define CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK) +/*! @} */ + +/*! @name ARM_PLL_CFG0 - ARM PLL Configuration 0 Register */ +/*! @{ */ + +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK) + +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK) + +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK_MASK (0x800U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT (11U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK_MASK) + +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT (12U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL_MASK) + +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U) +/*! PLL_COUNTCLK_SEL + * 0b0..25M_REF_CLK + * 0b1..27M_REF_CLK + */ +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL_MASK) + +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_MASK (0x4000U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_SHIFT (14U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_MASK) + +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL_MASK (0x8000U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL_SHIFT (15U) +/*! PLL_LOCK_SEL + * 0b0..Select PLL lock output + * 0b1..Select maximum lock time counter output + */ +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL_MASK) + +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL_MASK (0x30000U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL_SHIFT (16U) +/*! PLL_REFCLK_SEL + * 0b00..25M_REF_CLK + * 0b01..27M_REF_CLK + * 0b10..HDMI_PHY_27M_CLK + * 0b11..CLK_P_N + */ +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL_MASK) + +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT (18U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE_MASK) + +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_MASK (0x80000U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_SHIFT (19U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_MASK) + +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK) + +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_MASK (0x200000U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_SHIFT (21U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_MASK) + +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SHIFT (31U) +#define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_MASK) +/*! @} */ + +/*! @name ARM_PLL_CFG1 - ARM PLL Configuration 1 Register */ +/*! @{ */ + +#define CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU) +#define CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT (0U) +#define CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL_MASK) + +#define CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U) +#define CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U) +#define CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK) +/*! @} */ + +/*! @name SYS_PLL1_CFG0 - System PLL Configuration 0 Register */ +/*! @{ */ + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK (0x3U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT (0U) +/*! PLL_REFCLK_SEL + * 0b00..25M_REF_CLK + * 0b01..27M_REF_CLK + * 0b10..HDMI_PHY_27M_CLK + * 0b11..CLK_P_N + */ +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U) +/*! PLL_COUNTCLK_SEL + * 0b0..25M_REF_CLK + * 0b1..27M_REF_CLK + */ +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL_MASK (0x8U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL_SHIFT (3U) +/*! PLL_LOCK_SEL + * 0b0..Select PLL lock output + * 0b1..Select maximum lock time counter output + */ +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_MASK (0x10U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_SHIFT (4U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_MASK (0x20U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_SHIFT (5U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE_MASK (0x40U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT (6U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_MASK (0x80U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_SHIFT (7U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE_MASK (0x100U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE_SHIFT (8U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_MASK (0x200U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_SHIFT (9U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE_MASK (0x400U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE_SHIFT (10U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_MASK (0x800U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_SHIFT (11U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE_MASK (0x1000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE_SHIFT (12U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_MASK (0x2000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_SHIFT (13U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE_MASK (0x4000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE_SHIFT (14U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_MASK (0x8000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_SHIFT (15U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE_MASK (0x10000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE_SHIFT (16U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_MASK (0x20000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_SHIFT (17U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE_MASK (0x40000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE_SHIFT (18U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_MASK (0x80000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_SHIFT (19U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE_MASK (0x100000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE_SHIFT (20U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_MASK (0x200000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_SHIFT (21U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE_MASK (0x400000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE_SHIFT (22U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_MASK (0x800000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_SHIFT (23U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK (0x1000000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT (24U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_MASK (0x2000000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_SHIFT (25U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SHIFT (31U) +#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_MASK) +/*! @} */ + +/*! @name SYS_PLL1_CFG1 - System_PLL Configuration 1 Register */ +/*! @{ */ + +#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_MASK (0x1U) +#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_SHIFT (0U) +#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF_MASK (0x1EU) +#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF_SHIFT (1U) +#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD_MASK (0xE0U) +#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD_SHIFT (5U) +/*! PLL_SSMD + * 0b000..0.25 + * 0b001..0.5 + * 0b010..0.75 + * 0b011..1.0 + * 0b100..1.5 + * 0b101..2.0 + * 0b110..3.0 + * 0b111..4.0 + */ +#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS_MASK (0x100U) +#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS_SHIFT (8U) +/*! PLL_SSDS + * 0b0..Center Spread + * 0b1..Down Spread + */ +#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS_MASK) +/*! @} */ + +/*! @name SYS_PLL1_CFG2 - System_PLL Configuration 2 Register */ +/*! @{ */ + +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE_MASK (0x1U) +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE_SHIFT (0U) +/*! PLL_FILTER_RANGE + * 0b0..25 to 35 MHz + * 0b1..35 to 54 MHz + */ +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU) +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U) +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U) +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U) +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U) +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U) +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U) +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_SHIFT (19U) +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK) + +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK (0xE000000U) +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_SHIFT (25U) +#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK) +/*! @} */ + +/*! @name SYS_PLL2_CFG0 - System PLL Configuration 0 Register */ +/*! @{ */ + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL_MASK (0x3U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT (0U) +/*! PLL_REFCLK_SEL + * 0b00..25M_REF_CLK + * 0b01..27M_REF_CLK + * 0b10..HDMI_PHY_27M_CLK + * 0b11..CLK_P_N + */ +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U) +/*! PLL_COUNTCLK_SEL + * 0b0..25M_REF_CLK + * 0b1..27M_REF_CLK + */ +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL_MASK (0x8U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL_SHIFT (3U) +/*! PLL_LOCK_SEL + * 0b0..Select PLL lock output + * 0b1..Select maximum lock time counter output + */ +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_MASK (0x10U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_SHIFT (4U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_MASK (0x20U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_SHIFT (5U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE_MASK (0x40U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT (6U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_MASK (0x80U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_SHIFT (7U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE_MASK (0x100U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE_SHIFT (8U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_MASK (0x200U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_SHIFT (9U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE_MASK (0x400U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE_SHIFT (10U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_MASK (0x800U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_SHIFT (11U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE_MASK (0x1000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE_SHIFT (12U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_MASK (0x2000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_SHIFT (13U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE_MASK (0x4000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE_SHIFT (14U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_MASK (0x8000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_SHIFT (15U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE_MASK (0x10000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE_SHIFT (16U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_MASK (0x20000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_SHIFT (17U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE_MASK (0x40000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE_SHIFT (18U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_MASK (0x80000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_SHIFT (19U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE_MASK (0x100000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE_SHIFT (20U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_MASK (0x200000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_SHIFT (21U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE_MASK (0x400000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE_SHIFT (22U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_MASK (0x800000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_SHIFT (23U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK (0x1000000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT (24U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_MASK (0x2000000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_SHIFT (25U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SHIFT (31U) +#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_MASK) +/*! @} */ + +/*! @name SYS_PLL2_CFG1 - System_PLL Configuration 1 Register */ +/*! @{ */ + +#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE_MASK (0x1U) +#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE_SHIFT (0U) +#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF_MASK (0x1EU) +#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF_SHIFT (1U) +#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD_MASK (0xE0U) +#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD_SHIFT (5U) +/*! PLL_SSMD + * 0b000..0.25 + * 0b001..0.5 + * 0b010..0.75 + * 0b011..1.0 + * 0b100..1.5 + * 0b101..2.0 + * 0b110..3.0 + * 0b111..4.0 + */ +#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS_MASK (0x100U) +#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS_SHIFT (8U) +/*! PLL_SSDS + * 0b0..Center Spread + * 0b1..Down Spread + */ +#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS_MASK) +/*! @} */ + +/*! @name SYS_PLL2_CFG2 - System_PLL Configuration 2 Register */ +/*! @{ */ + +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE_MASK (0x1U) +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE_SHIFT (0U) +/*! PLL_FILTER_RANGE + * 0b0..25 to 35 MHz + * 0b1..35 to 54 MHz + */ +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU) +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U) +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U) +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U) +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U) +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U) +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U) +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2_SHIFT (19U) +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2_MASK) + +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1_MASK (0xE000000U) +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1_SHIFT (25U) +#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1_MASK) +/*! @} */ + +/*! @name SYS_PLL3_CFG0 - System PLL Configuration 0 Register */ +/*! @{ */ + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL_MASK (0x3U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL_SHIFT (0U) +/*! PLL_REFCLK_SEL + * 0b00..25M_REF_CLK + * 0b01..27M_REF_CLK + * 0b10..HDMI_PHY_27M_CLK + * 0b11..CLK_P_N + */ +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U) +/*! PLL_COUNTCLK_SEL + * 0b0..25M_REF_CLK + * 0b1..27M_REF_CLK + */ +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL_MASK (0x8U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL_SHIFT (3U) +/*! PLL_LOCK_SEL + * 0b0..Select PLL lock output + * 0b1..Select maximum lock time counter output + */ +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_MASK (0x10U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_SHIFT (4U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_MASK (0x20U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_SHIFT (5U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE_MASK (0x40U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE_SHIFT (6U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_MASK (0x80U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_SHIFT (7U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE_MASK (0x100U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE_SHIFT (8U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE_MASK (0x200U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE_SHIFT (9U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE_MASK (0x400U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE_SHIFT (10U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE_MASK (0x800U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE_SHIFT (11U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE_MASK (0x1000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE_SHIFT (12U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE_MASK (0x2000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE_SHIFT (13U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE_MASK (0x4000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE_SHIFT (14U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE_MASK (0x8000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE_SHIFT (15U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE_MASK (0x10000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE_SHIFT (16U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE_MASK (0x20000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE_SHIFT (17U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE_MASK (0x40000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE_SHIFT (18U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE_MASK (0x80000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE_SHIFT (19U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE_MASK (0x100000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE_SHIFT (20U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE_MASK (0x200000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE_SHIFT (21U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE_MASK (0x400000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE_SHIFT (22U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE_MASK (0x800000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE_SHIFT (23U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE_MASK (0x1000000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE_SHIFT (24U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_MASK (0x2000000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_SHIFT (25U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SHIFT (31U) +#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_MASK) +/*! @} */ + +/*! @name SYS_PLL3_CFG1 - System_PLL Configuration 1 Register */ +/*! @{ */ + +#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE_MASK (0x1U) +#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE_SHIFT (0U) +#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF_MASK (0x1EU) +#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF_SHIFT (1U) +#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD_MASK (0xE0U) +#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD_SHIFT (5U) +/*! PLL_SSMD + * 0b000..0.25 + * 0b001..0.5 + * 0b010..0.75 + * 0b011..1.0 + * 0b100..1.5 + * 0b101..2.0 + * 0b110..3.0 + * 0b111..4.0 + */ +#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS_MASK (0x100U) +#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS_SHIFT (8U) +/*! PLL_SSDS + * 0b0..Center Spread + * 0b1..Down Spread + */ +#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS_MASK) +/*! @} */ + +/*! @name SYS_PLL3_CFG2 - System_PLL Configuration 2 Register */ +/*! @{ */ + +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE_MASK (0x1U) +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE_SHIFT (0U) +/*! PLL_FILTER_RANGE + * 0b0..25 to 35 MHz + * 0b1..35 to 54 MHz + */ +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU) +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U) +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U) +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U) +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U) +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U) +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U) +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2_SHIFT (19U) +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2_MASK) + +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1_MASK (0xE000000U) +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1_SHIFT (25U) +#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1_MASK) +/*! @} */ + +/*! @name VIDEO_PLL2_CFG0 - VIDEO PLL2 Configuration 0 Register */ +/*! @{ */ + +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL_MASK (0x3U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT (0U) +/*! PLL_REFCLK_SEL + * 0b00..25M_REF_CLK + * 0b01..27M_REF_CLK + * 0b10..HDMI_PHY_27M_CLK + * 0b11..CLK_P_N + */ +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U) +/*! PLL_COUNTCLK_SEL + * 0b0..25M_REF_CLK + * 0b1..27M_REF_CLK + */ +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL_MASK (0x8U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL_SHIFT (3U) +/*! PLL_LOCK_SEL + * 0b0..Select PLL lock output + * 0b1..Select maximum lock time counter output + */ +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_MASK (0x10U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_SHIFT (4U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_MASK (0x20U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_SHIFT (5U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE_MASK (0x40U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT (6U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_MASK (0x80U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_SHIFT (7U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT (8U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_MASK (0x200U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_SHIFT (9U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SHIFT (31U) +#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_MASK) +/*! @} */ + +/*! @name VIDEO_PLL2_CFG1 - VIDEO PLL2 Configuration 1 Register */ +/*! @{ */ + +#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE_MASK (0x1U) +#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE_SHIFT (0U) +#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF_MASK (0x1EU) +#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF_SHIFT (1U) +#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD_MASK (0xE0U) +#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD_SHIFT (5U) +/*! PLL_SSMD + * 0b000..0.25 + * 0b001..0.5 + * 0b010..0.75 + * 0b011..1.0 + * 0b100..1.5 + * 0b101..2.0 + * 0b110..3.0 + * 0b111..4.0 + */ +#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS_MASK (0x100U) +#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS_SHIFT (8U) +/*! PLL_SSDS + * 0b0..Center Spread + * 0b1..Down Spread + */ +#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS_MASK) +/*! @} */ + +/*! @name VIDEO_PLL2_CFG2 - VIDEO PLL2 Configuration 2 Register */ +/*! @{ */ + +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE_MASK (0x1U) +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE_SHIFT (0U) +/*! PLL_FILTER_RANGE + * 0b0..25 to 35 MHz + * 0b1..35 to 54 MHz + */ +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU) +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U) +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U) +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U) +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U) +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U) +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U) +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2_SHIFT (19U) +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2_MASK) + +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1_MASK (0xE000000U) +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1_SHIFT (25U) +#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1_MASK) +/*! @} */ + +/*! @name DRAM_PLL_CFG0 - DRAM PLL Configuration 0 Register */ +/*! @{ */ + +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL_MASK (0x3U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL_SHIFT (0U) +/*! PLL_REFCLK_SEL + * 0b00..25M_REF_CLK + * 0b01..27M_REF_CLK + * 0b10..HDMI_PHY_27M_CLK + * 0b11..CLK_P_N + */ +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U) +/*! PLL_COUNTCLK_SEL + * 0b0..25M_REF_CLK + * 0b1..27M_REF_CLK + */ +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL_MASK (0x8U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL_SHIFT (3U) +/*! PLL_LOCK_SEL + * 0b0..Select PLL lock output + * 0b1..Select maximum lock time counter output + */ +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_MASK (0x10U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_SHIFT (4U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_MASK (0x20U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_SHIFT (5U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE_MASK (0x40U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT (6U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_MASK (0x80U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_SHIFT (7U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT (8U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_MASK (0x200U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_SHIFT (9U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SHIFT (31U) +#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_MASK) +/*! @} */ + +/*! @name DRAM_PLL_CFG1 - DRAM PLL Configuration 1 Register */ +/*! @{ */ + +#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE_MASK (0x1U) +#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE_SHIFT (0U) +#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF_MASK (0x1EU) +#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF_SHIFT (1U) +#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD_MASK (0xE0U) +#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD_SHIFT (5U) +/*! PLL_SSMD + * 0b000..0.25 + * 0b001..0.5 + * 0b010..0.75 + * 0b011..1.0 + * 0b100..1.5 + * 0b101..2.0 + * 0b110..3.0 + * 0b111..4.0 + */ +#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS_MASK (0x100U) +#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS_SHIFT (8U) +/*! PLL_SSDS + * 0b0..Center Spread + * 0b1..Down Spread + */ +#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS_MASK) +/*! @} */ + +/*! @name DRAM_PLL_CFG2 - DRAM PLL Configuration 2 Register */ +/*! @{ */ + +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE_MASK (0x1U) +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE_SHIFT (0U) +/*! PLL_FILTER_RANGE + * 0b0..25 to 35 MHz + * 0b1..35 to 54 MHz + */ +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU) +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U) +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U) +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U) +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U) +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U) +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U) +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2_SHIFT (19U) +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2_MASK) + +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1_MASK (0xE000000U) +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1_SHIFT (25U) +#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1_MASK) +/*! @} */ + +/*! @name DIGPROG - DIGPROG Register */ +/*! @{ */ + +#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK (0xFFU) +#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT (0U) +#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK) + +#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U) +#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT (8U) +#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK) + +#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U) +#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT (16U) +#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK) +/*! @} */ + +/*! @name OSC_MISC_CFG - Osc Misc Configuration Register */ +/*! @{ */ + +#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK (0x1U) +#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT (0U) +/*! OSC_32K_SEL + * 0b0..25M_REF_CLK_DIV800 + * 0b1..RTC + */ +#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK) + +#define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE_MASK (0x2U) +#define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE_SHIFT (1U) +#define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE_MASK) + +#define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_MASK (0x4U) +#define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_SHIFT (2U) +#define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_MASK) + +#define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE_MASK (0x8U) +#define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE_SHIFT (3U) +#define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE_MASK) + +#define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_MASK (0x10U) +#define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_SHIFT (4U) +#define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_MASK) +/*! @} */ + +/*! @name PLLOUT_MONITOR_CFG - PLLOUT Monitor Configuration Register */ +/*! @{ */ + +#define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL_MASK (0xFU) +#define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL_SHIFT)) & CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL_MASK) + +#define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE_MASK (0x10U) +#define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE_SHIFT (4U) +#define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE_SHIFT)) & CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE_MASK) +/*! @} */ + +/*! @name FRAC_PLLOUT_DIV_CFG - Fractional PLLOUT Divider Configuration Register */ +/*! @{ */ + +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL_MASK (0x7U) +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL_SHIFT (0U) +/*! AUDIO_PLL1_DIV_VAL + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL_MASK) + +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL_MASK (0x70U) +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL_SHIFT (4U) +/*! AUDIO_PLL2_DIV_VAL + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL_MASK) + +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL_MASK (0x700U) +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL_SHIFT (8U) +/*! VIDEO_PLL1_DIV_VAL + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL_MASK) + +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL_MASK (0x7000U) +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL_SHIFT (12U) +/*! GPU_PLL_DIV_VAL + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL_MASK) + +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL_MASK (0x70000U) +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL_SHIFT (16U) +/*! VPU_PLL_DIV_VAL + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL_MASK) + +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL_MASK (0x700000U) +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL_SHIFT (20U) +/*! ARM_PLL_DIV_VAL + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL_MASK) +/*! @} */ + +/*! @name SCCG_PLLOUT_DIV_CFG - SCCG PLLOUT Divider Configuration Register */ +/*! @{ */ + +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL_MASK (0x7U) +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL_SHIFT (0U) +/*! SYSTEM_PLL1_DIV_VAL + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL_MASK) + +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL_MASK (0x70U) +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL_SHIFT (4U) +/*! SYSTEM_PLL2_DIV_VAL + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL_MASK) + +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL_MASK (0x700U) +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL_SHIFT (8U) +/*! SYSTEM_PLL3_DIV_VAL + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL_MASK) + +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL_MASK (0x7000U) +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL_SHIFT (12U) +/*! DRAM_PLL_DIV_VAL + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL_MASK) + +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL_MASK (0x70000U) +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL_SHIFT (16U) +/*! VIDEO_PLL2_DIV_VAL + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Masks */ + + +/* CCM_ANALOG - Peripheral instance base addresses */ +/** Peripheral CCM_ANALOG base address */ +#define CCM_ANALOG_BASE (0x30360000u) +/** Peripheral CCM_ANALOG base pointer */ +#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) +/** Array initializer of CCM_ANALOG peripheral base addresses */ +#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } +/** Array initializer of CCM_ANALOG peripheral base pointers */ +#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } + +/*! + * @} + */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTX_LD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTX_LD_Peripheral_Access_Layer CTX_LD Peripheral Access Layer + * @{ + */ + +/** CTX_LD - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< Control status register for Context Loader., offset: 0x0 */ + __IO uint32_t SET; /**< Control status register for Context Loader., offset: 0x4 */ + __IO uint32_t CLR; /**< Control status register for Context Loader., offset: 0x8 */ + __IO uint32_t TOG; /**< Control status register for Context Loader., offset: 0xC */ + } CTRL_STATUS; + __IO uint32_t DB_BASE_ADDR; /**< DRAM addr for double buffered register fetch., offset: 0x10 */ + __IO uint32_t DB_COUNT; /**< Double buffer register count, offset: 0x14 */ + __IO uint32_t SB_BASE_ADDR; /**< DRAM addr for single buffered registers., offset: 0x18 */ + __IO uint32_t SB_COUNT; /**< Single buffer register count, offset: 0x1C */ + __I uint32_t AHB_ERR_ADDR; /**< AHB address with error response., offset: 0x20 */ +} CTX_LD_Type; + +/* ---------------------------------------------------------------------------- + -- CTX_LD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTX_LD_Register_Masks CTX_LD Register Masks + * @{ + */ + +/*! @name CTRL_STATUS - Control status register for Context Loader. */ +/*! @{ */ + +#define CTX_LD_CTRL_STATUS_ENABLE_MASK (0x1U) +#define CTX_LD_CTRL_STATUS_ENABLE_SHIFT (0U) +/*! ENABLE - Enable/Busy + */ +#define CTX_LD_CTRL_STATUS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_ENABLE_SHIFT)) & CTX_LD_CTRL_STATUS_ENABLE_MASK) + +#define CTX_LD_CTRL_STATUS_ARB_SEL_MASK (0x2U) +#define CTX_LD_CTRL_STATUS_ARB_SEL_SHIFT (1U) +/*! ARB_SEL - Arbitration select + */ +#define CTX_LD_CTRL_STATUS_ARB_SEL(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_ARB_SEL_SHIFT)) & CTX_LD_CTRL_STATUS_ARB_SEL_MASK) + +#define CTX_LD_CTRL_STATUS_RD_ERR_EN_MASK (0x4U) +#define CTX_LD_CTRL_STATUS_RD_ERR_EN_SHIFT (2U) +/*! RD_ERR_EN - AXI read error IRQ enable + */ +#define CTX_LD_CTRL_STATUS_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_RD_ERR_EN_SHIFT)) & CTX_LD_CTRL_STATUS_RD_ERR_EN_MASK) + +#define CTX_LD_CTRL_STATUS_DB_COMP_EN_MASK (0x8U) +#define CTX_LD_CTRL_STATUS_DB_COMP_EN_SHIFT (3U) +/*! DB_COMP_EN - Double buffer region loading complete IRQ enable + */ +#define CTX_LD_CTRL_STATUS_DB_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_DB_COMP_EN_SHIFT)) & CTX_LD_CTRL_STATUS_DB_COMP_EN_MASK) + +#define CTX_LD_CTRL_STATUS_SB_HP_COMP_EN_MASK (0x10U) +#define CTX_LD_CTRL_STATUS_SB_HP_COMP_EN_SHIFT (4U) +/*! SB_HP_COMP_EN - Single buffer high priority region loading complete IRQ enable + */ +#define CTX_LD_CTRL_STATUS_SB_HP_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_HP_COMP_EN_SHIFT)) & CTX_LD_CTRL_STATUS_SB_HP_COMP_EN_MASK) + +#define CTX_LD_CTRL_STATUS_SB_LP_COMP_EN_MASK (0x20U) +#define CTX_LD_CTRL_STATUS_SB_LP_COMP_EN_SHIFT (5U) +/*! SB_LP_COMP_EN - Single buffer low priority region loading complete IRQ enable + */ +#define CTX_LD_CTRL_STATUS_SB_LP_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_LP_COMP_EN_SHIFT)) & CTX_LD_CTRL_STATUS_SB_LP_COMP_EN_MASK) + +#define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN_MASK (0x40U) +#define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN_SHIFT (6U) +/*! DB_PEND_SB_REC_EN - Double/single region overlap interrupt enable + */ +#define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN_SHIFT)) & CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN_MASK) + +#define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN_MASK (0x80U) +#define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN_SHIFT (7U) +/*! SB_PEND_DISP_ACTIVE_EN - Single/active region overlap interrupt enable. + */ +#define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN_SHIFT)) & CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN_MASK) + +#define CTX_LD_CTRL_STATUS_AHB_ERR_EN_MASK (0x100U) +#define CTX_LD_CTRL_STATUS_AHB_ERR_EN_SHIFT (8U) +/*! AHB_ERR_EN - AHB error IRQ enable + */ +#define CTX_LD_CTRL_STATUS_AHB_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_AHB_ERR_EN_SHIFT)) & CTX_LD_CTRL_STATUS_AHB_ERR_EN_MASK) + +#define CTX_LD_CTRL_STATUS_RD_ERR_MASK (0x10000U) +#define CTX_LD_CTRL_STATUS_RD_ERR_SHIFT (16U) +/*! RD_ERR - AXI read error + */ +#define CTX_LD_CTRL_STATUS_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_RD_ERR_SHIFT)) & CTX_LD_CTRL_STATUS_RD_ERR_MASK) + +#define CTX_LD_CTRL_STATUS_DB_COMP_MASK (0x20000U) +#define CTX_LD_CTRL_STATUS_DB_COMP_SHIFT (17U) +/*! DB_COMP - Double buffer region loading complete + */ +#define CTX_LD_CTRL_STATUS_DB_COMP(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_DB_COMP_SHIFT)) & CTX_LD_CTRL_STATUS_DB_COMP_MASK) + +#define CTX_LD_CTRL_STATUS_SB_HP_COMP_MASK (0x40000U) +#define CTX_LD_CTRL_STATUS_SB_HP_COMP_SHIFT (18U) +/*! SB_HP_COMP - Single buffer high priority region loading complete + */ +#define CTX_LD_CTRL_STATUS_SB_HP_COMP(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_HP_COMP_SHIFT)) & CTX_LD_CTRL_STATUS_SB_HP_COMP_MASK) + +#define CTX_LD_CTRL_STATUS_SB_LP_COMP_MASK (0x80000U) +#define CTX_LD_CTRL_STATUS_SB_LP_COMP_SHIFT (19U) +/*! SB_LP_COMP - Single buffer low priority region loading complete IRQ enable + */ +#define CTX_LD_CTRL_STATUS_SB_LP_COMP(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_LP_COMP_SHIFT)) & CTX_LD_CTRL_STATUS_SB_LP_COMP_MASK) + +#define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_MASK (0x100000U) +#define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_SHIFT (20U) +/*! DB_PEND_SB_REC - Double/single region overlap + */ +#define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_SHIFT)) & CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_MASK) + +#define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_MASK (0x200000U) +#define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_SHIFT (21U) +/*! SB_PEND_DISP_ACTIVE - Single/active region overlap + */ +#define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_SHIFT)) & CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_MASK) + +#define CTX_LD_CTRL_STATUS_AHB_ERR_MASK (0x400000U) +#define CTX_LD_CTRL_STATUS_AHB_ERR_SHIFT (22U) +/*! AHB_ERR - AHB error + */ +#define CTX_LD_CTRL_STATUS_AHB_ERR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_AHB_ERR_SHIFT)) & CTX_LD_CTRL_STATUS_AHB_ERR_MASK) +/*! @} */ + +/*! @name DB_BASE_ADDR - DRAM addr for double buffered register fetch. */ +/*! @{ */ + +#define CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR_MASK (0xFFFFFFFFU) +#define CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR_SHIFT (0U) +/*! DB_BASE_ADDR - Double buffered registers base address. + */ +#define CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR_SHIFT)) & CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR_MASK) +/*! @} */ + +/*! @name DB_COUNT - Double buffer register count */ +/*! @{ */ + +#define CTX_LD_DB_COUNT_DB_COUNT_MASK (0xFFFFU) +#define CTX_LD_DB_COUNT_DB_COUNT_SHIFT (0U) +/*! DB_COUNT - Double buffered region fetch count + */ +#define CTX_LD_DB_COUNT_DB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_DB_COUNT_DB_COUNT_SHIFT)) & CTX_LD_DB_COUNT_DB_COUNT_MASK) +/*! @} */ + +/*! @name SB_BASE_ADDR - DRAM addr for single buffered registers. */ +/*! @{ */ + +#define CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR_MASK (0xFFFFFFFFU) +#define CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR_SHIFT (0U) +/*! SB_BASE_ADDR - Single buffered register base address. + */ +#define CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR_SHIFT)) & CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR_MASK) +/*! @} */ + +/*! @name SB_COUNT - Single buffer register count */ +/*! @{ */ + +#define CTX_LD_SB_COUNT_HP_COUNT_MASK (0xFFFFU) +#define CTX_LD_SB_COUNT_HP_COUNT_SHIFT (0U) +/*! HP_COUNT - Single buffered high priority region fetch count + */ +#define CTX_LD_SB_COUNT_HP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_SB_COUNT_HP_COUNT_SHIFT)) & CTX_LD_SB_COUNT_HP_COUNT_MASK) + +#define CTX_LD_SB_COUNT_LP_COUNT_MASK (0xFFFF0000U) +#define CTX_LD_SB_COUNT_LP_COUNT_SHIFT (16U) +/*! LP_COUNT - Single buffered low priority region fetch count + */ +#define CTX_LD_SB_COUNT_LP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_SB_COUNT_LP_COUNT_SHIFT)) & CTX_LD_SB_COUNT_LP_COUNT_MASK) +/*! @} */ + +/*! @name AHB_ERR_ADDR - AHB address with error response. */ +/*! @{ */ + +#define CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR_MASK (0xFFFFFFFFU) +#define CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR_SHIFT (0U) +/*! AHB_ERR_ADDR - AHB error address. + */ +#define CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR_SHIFT)) & CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CTX_LD_Register_Masks */ + + +/* CTX_LD - Peripheral instance base addresses */ +/** Peripheral DCSS__CTX_LD base address */ +#define DCSS__CTX_LD_BASE (0x32E23000u) +/** Peripheral DCSS__CTX_LD base pointer */ +#define DCSS__CTX_LD ((CTX_LD_Type *)DCSS__CTX_LD_BASE) +/** Array initializer of CTX_LD peripheral base addresses */ +#define CTX_LD_BASE_ADDRS { DCSS__CTX_LD_BASE } +/** Array initializer of CTX_LD peripheral base pointers */ +#define CTX_LD_BASE_PTRS { DCSS__CTX_LD } + +/*! + * @} + */ /* end of group CTX_LD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DDRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer + * @{ + */ + +/** DDRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MSTR; /**< Master Register0, offset: 0x0 */ + __I uint32_t STAT; /**< Operating Mode Status Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MRCTRL0; /**< Mode Register Read/Write Control Register 0., offset: 0x10 */ + __IO uint32_t MRCTRL1; /**< Mode Register Read/Write Control Register 1, offset: 0x14 */ + __I uint32_t MRSTAT; /**< Mode Register Read/Write Status Register, offset: 0x18 */ + __IO uint32_t MRCTRL2; /**< Mode Register Read/Write Control Register 2, offset: 0x1C */ + __IO uint32_t DERATEEN; /**< Temperature Derate Enable Register, offset: 0x20 */ + __IO uint32_t DERATEINT; /**< Temperature Derate Interval Register, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t PWRCTL; /**< Low Power Control Register, offset: 0x30 */ + __IO uint32_t PWRTMG; /**< Low Power Timing Register, offset: 0x34 */ + __IO uint32_t HWLPCTL; /**< Hardware Low Power Control Register, offset: 0x38 */ + uint8_t RESERVED_2[20]; + __IO uint32_t RFSHCTL0; /**< Refresh Control Register 0, offset: 0x50 */ + __IO uint32_t RFSHCTL1; /**< Refresh Control Register 1, offset: 0x54 */ + uint8_t RESERVED_3[8]; + __IO uint32_t RFSHCTL3; /**< Refresh Control Register 3, offset: 0x60 */ + __IO uint32_t RFSHTMG; /**< Refresh Timing Register, offset: 0x64 */ + uint8_t RESERVED_4[88]; + __IO uint32_t CRCPARCTL0; /**< CRC Parity Control Register0, offset: 0xC0 */ + __IO uint32_t CRCPARCTL1; /**< CRC Parity Control Register1, offset: 0xC4 */ + uint8_t RESERVED_5[4]; + __I uint32_t CRCPARSTAT; /**< CRC Parity Status Register, offset: 0xCC */ + __IO uint32_t INIT0; /**< SDRAM Initialization Register 0, offset: 0xD0 */ + __IO uint32_t INIT1; /**< SDRAM Initialization Register 1, offset: 0xD4 */ + __IO uint32_t INIT2; /**< SDRAM Initialization Register 2, offset: 0xD8 */ + __IO uint32_t INIT3; /**< SDRAM Initialization Register 3, offset: 0xDC */ + __IO uint32_t INIT4; /**< SDRAM Initialization Register 4, offset: 0xE0 */ + __IO uint32_t INIT5; /**< SDRAM Initialization Register 5, offset: 0xE4 */ + __IO uint32_t INIT6; /**< SDRAM Initialization Register 6, offset: 0xE8 */ + __IO uint32_t INIT7; /**< SDRAM Initialization Register 7, offset: 0xEC */ + __IO uint32_t DIMMCTL; /**< DIMM Control Register, offset: 0xF0 */ + __IO uint32_t RANKCTL; /**< Rank Control Register, offset: 0xF4 */ + uint8_t RESERVED_6[8]; + __IO uint32_t DRAMTMG0; /**< SDRAM Timing Register 0, offset: 0x100 */ + __IO uint32_t DRAMTMG1; /**< SDRAM Timing Register 1, offset: 0x104 */ + __IO uint32_t DRAMTMG2; /**< SDRAM Timing Register 2, offset: 0x108 */ + __IO uint32_t DRAMTMG3; /**< SDRAM Timing Register 3, offset: 0x10C */ + __IO uint32_t DRAMTMG4; /**< SDRAM Timing Register 4, offset: 0x110 */ + __IO uint32_t DRAMTMG5; /**< SDRAM Timing Register 5, offset: 0x114 */ + __IO uint32_t DRAMTMG6; /**< SDRAM Timing Register 6, offset: 0x118 */ + __IO uint32_t DRAMTMG7; /**< SDRAM Timing Register 7, offset: 0x11C */ + __IO uint32_t DRAMTMG8; /**< SDRAM Timing Register 8, offset: 0x120 */ + __IO uint32_t DRAMTMG9; /**< SDRAM Timing Register 9, offset: 0x124 */ + __IO uint32_t DRAMTMG10; /**< SDRAM Timing Register 10, offset: 0x128 */ + __IO uint32_t DRAMTMG11; /**< SDRAM Timing Register 11, offset: 0x12C */ + __IO uint32_t DRAMTMG12; /**< SDRAM Timing Register 12, offset: 0x130 */ + __IO uint32_t DRAMTMG13; /**< SDRAM Timing Register 13, offset: 0x134 */ + __IO uint32_t DRAMTMG14; /**< SDRAM Timing Register 14, offset: 0x138 */ + __IO uint32_t DRAMTMG15; /**< SDRAM Timing Register 15, offset: 0x13C */ + uint8_t RESERVED_7[64]; + __IO uint32_t ZQCTL0; /**< ZQ Control Register 0, offset: 0x180 */ + __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ + __IO uint32_t ZQCTL2; /**< ZQ Control Register 2, offset: 0x188 */ + __I uint32_t ZQSTAT; /**< ZQ Status Register, offset: 0x18C */ + __IO uint32_t DFITMG0; /**< DFI Timing Register 0, offset: 0x190 */ + __IO uint32_t DFITMG1; /**< DFI Timing Register 1, offset: 0x194 */ + __IO uint32_t DFILPCFG0; /**< DFI Low Power Configuration Register 0, offset: 0x198 */ + __IO uint32_t DFILPCFG1; /**< DFI Low Power Configuration Register 1, offset: 0x19C */ + __IO uint32_t DFIUPD0; /**< DFI Update Register 0, offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /**< DFI Update Register 1, offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /**< DFI Update Register 2, offset: 0x1A8 */ + uint8_t RESERVED_8[4]; + __IO uint32_t DFIMISC; /**< DFI Miscellaneous Control Register, offset: 0x1B0 */ + __IO uint32_t DFITMG2; /**< DFI Timing Register 2, offset: 0x1B4 */ + __IO uint32_t DFITMG3; /**< DFI Timing Register 3, offset: 0x1B8 */ + __I uint32_t DFISTAT; /**< DFI Status Register, offset: 0x1BC */ + __IO uint32_t DBICTL; /**< DM/DBI Control Register, offset: 0x1C0 */ + uint8_t RESERVED_9[60]; + __IO uint32_t ADDRMAP0; /**< Address Map Register 0, offset: 0x200 */ + __IO uint32_t ADDRMAP1; /**< Address Map Register 1, offset: 0x204 */ + __IO uint32_t ADDRMAP2; /**< Address Map Register 2, offset: 0x208 */ + __IO uint32_t ADDRMAP3; /**< Address Map Register 3, offset: 0x20C */ + __IO uint32_t ADDRMAP4; /**< Address Map Register 4, offset: 0x210 */ + __IO uint32_t ADDRMAP5; /**< Address Map Register 5, offset: 0x214 */ + __IO uint32_t ADDRMAP6; /**< Address Map Register 6, offset: 0x218 */ + __IO uint32_t ADDRMAP7; /**< Address Map Register 7, offset: 0x21C */ + __IO uint32_t ADDRMAP8; /**< Address Map Register 8, offset: 0x220 */ + __IO uint32_t ADDRMAP9; /**< Address Map Register 9, offset: 0x224 */ + __IO uint32_t ADDRMAP10; /**< Address Map Register 10, offset: 0x228 */ + __IO uint32_t ADDRMAP11; /**< Address Map Register 11, offset: 0x22C */ + uint8_t RESERVED_10[16]; + __IO uint32_t ODTCFG; /**< ODT Configuration Register, offset: 0x240 */ + __IO uint32_t ODTMAP; /**< ODT/Rank Map Register, offset: 0x244 */ + uint8_t RESERVED_11[8]; + __IO uint32_t SCHED; /**< Scheduler Control Register, offset: 0x250 */ + __IO uint32_t SCHED1; /**< Scheduler Control Register 1, offset: 0x254 */ + uint8_t RESERVED_12[4]; + __IO uint32_t PERFHPR1; /**< High Priority Read CAM Register 1, offset: 0x25C */ + uint8_t RESERVED_13[4]; + __IO uint32_t PERFLPR1; /**< Low Priority Read CAM Register 1, offset: 0x264 */ + uint8_t RESERVED_14[4]; + __IO uint32_t PERFWR1; /**< Write CAM Register 1, offset: 0x26C */ + uint8_t RESERVED_15[144]; + __IO uint32_t DBG0; /**< Debug Register 0, offset: 0x300 */ + __IO uint32_t DBG1; /**< Debug Register 1, offset: 0x304 */ + __I uint32_t DBGCAM; /**< CAM Debug Register, offset: 0x308 */ + __IO uint32_t DBGCMD; /**< Command Debug Register, offset: 0x30C */ + __I uint32_t DBGSTAT; /**< Status Debug Register, offset: 0x310 */ + uint8_t RESERVED_16[12]; + __IO uint32_t SWCTL; /**< Software Register Programming Control Enable, offset: 0x320 */ + __I uint32_t SWSTAT; /**< Software Register Programming Control Status, offset: 0x324 */ + uint8_t RESERVED_17[68]; + __IO uint32_t POISONCFG; /**< AXI Poison Configuration Register., offset: 0x36C */ + __I uint32_t POISONSTAT; /**< AXI Poison Status Register, offset: 0x370 */ + uint8_t RESERVED_18[136]; + __I uint32_t PSTAT; /**< Port Status Register, offset: 0x3FC */ + __IO uint32_t PCCFG; /**< Port Common Configuration Register, offset: 0x400 */ + __IO uint32_t PCFGR_0; /**< Port n Configuration Read Register, offset: 0x404 */ + __IO uint32_t PCFGW_0; /**< Port n Configuration Write Register, offset: 0x408 */ + uint8_t RESERVED_19[132]; + __IO uint32_t PCTRL_0; /**< Port n Control Register, offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /**< Port n Read QoS Configuration Register 0, offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /**< Port n Read QoS Configuration Register 1, offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /**< Port n Write QoS Configuration Register 0, offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */ + uint8_t RESERVED_20[7036]; + __IO uint32_t DERATEEN_SHADOW; /**< [SHADOW] Temperature Derate Enable Register, offset: 0x2020 */ + __IO uint32_t DERATEINT_SHADOW; /**< [SHADOW] Temperature Derate Interval Register, offset: 0x2024 */ + uint8_t RESERVED_21[40]; + __IO uint32_t RFSHCTL0_SHADOW; /**< [SHADOW] Refresh Control Register 0, offset: 0x2050 */ + uint8_t RESERVED_22[16]; + __IO uint32_t RFSHTMG_SHADOW; /**< [SHADOW] Refresh Timing Register, offset: 0x2064 */ + uint8_t RESERVED_23[116]; + __IO uint32_t INIT3_SHADOW; /**< [SHADOW] SDRAM Initialization Register 3, offset: 0x20DC */ + __IO uint32_t INIT4_SHADOW; /**< [SHADOW] SDRAM Initialization Register 4, offset: 0x20E0 */ + uint8_t RESERVED_24[4]; + __IO uint32_t INIT6_SHADOW; /**< [SHADOW] SDRAM Initialization Register 6, offset: 0x20E8 */ + __IO uint32_t INIT7_SHADOW; /**< [SHADOW] SDRAM Initialization Register 7, offset: 0x20EC */ + uint8_t RESERVED_25[16]; + __IO uint32_t DRAMTMG0_SHADOW; /**< [SHADOW] SDRAM Timing Register 0, offset: 0x2100 */ + __IO uint32_t DRAMTMG1_SHADOW; /**< [SHADOW] SDRAM Timing Register 1, offset: 0x2104 */ + __IO uint32_t DRAMTMG2_SHADOW; /**< [SHADOW] SDRAM Timing Register 2, offset: 0x2108 */ + __IO uint32_t DRAMTMG3_SHADOW; /**< [SHADOW] SDRAM Timing Register 3, offset: 0x210C */ + __IO uint32_t DRAMTMG4_SHADOW; /**< [SHADOW] SDRAM Timing Register 4, offset: 0x2110 */ + __IO uint32_t DRAMTMG5_SHADOW; /**< [SHADOW] SDRAM Timing Register 5, offset: 0x2114 */ + __IO uint32_t DRAMTMG6_SHADOW; /**< [SHADOW] SDRAM Timing Register 6, offset: 0x2118 */ + __IO uint32_t DRAMTMG7_SHADOW; /**< [SHADOW] SDRAM Timing Register 7, offset: 0x211C */ + __IO uint32_t DRAMTMG8_SHADOW; /**< [SHADOW] SDRAM Timing Register 8, offset: 0x2120 */ + __IO uint32_t DRAMTMG9_SHADOW; /**< [SHADOW] SDRAM Timing Register 9, offset: 0x2124 */ + __IO uint32_t DRAMTMG10_SHADOW; /**< [SHADOW] SDRAM Timing Register 10, offset: 0x2128 */ + __IO uint32_t DRAMTMG11_SHADOW; /**< [SHADOW] SDRAM Timing Register 11, offset: 0x212C */ + __IO uint32_t DRAMTMG12_SHADOW; /**< [SHADOW] SDRAM Timing Register 12, offset: 0x2130 */ + __IO uint32_t DRAMTMG13_SHADOW; /**< [SHADOW] SDRAM Timing Register 13, offset: 0x2134 */ + __IO uint32_t DRAMTMG14_SHADOW; /**< [SHADOW] SDRAM Timing Register 14, offset: 0x2138 */ + __IO uint32_t DRAMTMG15_SHADOW; /**< [SHADOW] SDRAM Timing Register 15, offset: 0x213C */ + uint8_t RESERVED_26[64]; + __IO uint32_t ZQCTL0_SHADOW; /**< [SHADOW] ZQ Control Register 0, offset: 0x2180 */ + uint8_t RESERVED_27[12]; + __IO uint32_t DFITMG0_SHADOW; /**< [SHADOW] DFI Timing Register 0, offset: 0x2190 */ + __IO uint32_t DFITMG1_SHADOW; /**< [SHADOW] DFI Timing Register 1, offset: 0x2194 */ + uint8_t RESERVED_28[28]; + __IO uint32_t DFITMG2_SHADOW; /**< [SHADOW] DFI Timing Register 2, offset: 0x21B4 */ + __IO uint32_t DFITMG3_SHADOW; /**< [SHADOW] DFI Timing Register 3, offset: 0x21B8 */ + uint8_t RESERVED_29[132]; + __IO uint32_t ODTCFG_SHADOW; /**< [SHADOW] ODT Configuration Register, offset: 0x2240 */ +} DDRC_Type; + +/* ---------------------------------------------------------------------------- + -- DDRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Register_Masks DDRC Register Masks + * @{ + */ + +/*! @name MSTR - Master Register0 */ +/*! @{ */ + +#define DDRC_MSTR_ddr3_MASK (0x1U) +#define DDRC_MSTR_ddr3_SHIFT (0U) +/*! ddr3 - Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only + * present in designs that support DDR3. + */ +#define DDRC_MSTR_ddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr3_SHIFT)) & DDRC_MSTR_ddr3_MASK) + +#define DDRC_MSTR_lpddr2_MASK (0x4U) +#define DDRC_MSTR_lpddr2_SHIFT (2U) +/*! lpddr2 - Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use + * Present only in designs configured to support LPDDR2. + */ +#define DDRC_MSTR_lpddr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr2_SHIFT)) & DDRC_MSTR_lpddr2_MASK) + +#define DDRC_MSTR_lpddr3_MASK (0x8U) +#define DDRC_MSTR_lpddr3_SHIFT (3U) +/*! lpddr3 - Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use + * Present only in designs configured to support LPDDR3. + */ +#define DDRC_MSTR_lpddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr3_SHIFT)) & DDRC_MSTR_lpddr3_MASK) + +#define DDRC_MSTR_ddr4_MASK (0x10U) +#define DDRC_MSTR_ddr4_SHIFT (4U) +/*! ddr4 - Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present + * only in designs configured to support DDR4. + */ +#define DDRC_MSTR_ddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr4_SHIFT)) & DDRC_MSTR_ddr4_MASK) + +#define DDRC_MSTR_lpddr4_MASK (0x20U) +#define DDRC_MSTR_lpddr4_SHIFT (5U) +/*! lpddr4 - Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use + * Present only in designs configured to support LPDDR4. + */ +#define DDRC_MSTR_lpddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr4_SHIFT)) & DDRC_MSTR_lpddr4_MASK) + +#define DDRC_MSTR_burstchop_MASK (0x200U) +#define DDRC_MSTR_burstchop_SHIFT (9U) +/*! burstchop - When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for Reads + * is exercised only in HIF configurations (DDRC_INCL_ARB not set) and if in full bus width mode + * (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. Burst Chop for Writes is + * exercised only if Partial Writes enabled (DDRC_PARTIAL_WR=1) and if CRC is disabled + * (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), + * burst chop is not supported, and this bit must be set to '0'. BC4 (fixed) mode is not supported. + */ +#define DDRC_MSTR_burstchop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burstchop_SHIFT)) & DDRC_MSTR_burstchop_MASK) + +#define DDRC_MSTR_en_2t_timing_mode_MASK (0x400U) +#define DDRC_MSTR_en_2t_timing_mode_SHIFT (10U) +/*! en_2t_timing_mode - If 1, then DDRC uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all + * command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is + * asserted on the second cycle of the command Note: 2T timing is not supported in + * LPDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE + * is set Note: 2T timing is not supported in DDR4 geardown mode. Note: 2T timing is not supported + * in Shared-AC dual channel mode and the register value is don't care. + */ +#define DDRC_MSTR_en_2t_timing_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_en_2t_timing_mode_SHIFT)) & DDRC_MSTR_en_2t_timing_mode_MASK) + +#define DDRC_MSTR_geardown_mode_MASK (0x800U) +#define DDRC_MSTR_geardown_mode_SHIFT (11U) +/*! geardown_mode - 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in + * normal mode (1N). This register can be changed, only when the Controller is in self-refresh + * mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode is not supported + * if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: Geardown mode is not supported + * if the configuration parameter DDRC_SHARED_AC is set (in Shared-AC mode) and the register value + * is don't care + */ +#define DDRC_MSTR_geardown_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_geardown_mode_SHIFT)) & DDRC_MSTR_geardown_mode_MASK) + +#define DDRC_MSTR_data_bus_width_MASK (0x3000U) +#define DDRC_MSTR_data_bus_width_SHIFT (12U) +/*! data_bus_width - Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus + * width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 - + * Reserved. Note that half bus width mode is only supported when the SDRAM bus width is a + * multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple + * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus + * width (excluding any ECC width). + */ +#define DDRC_MSTR_data_bus_width(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_data_bus_width_SHIFT)) & DDRC_MSTR_data_bus_width_MASK) + +#define DDRC_MSTR_dll_off_mode_MASK (0x8000U) +#define DDRC_MSTR_dll_off_mode_SHIFT (15U) +/*! dll_off_mode - Set to 1 when the DDRC and DRAM has to be put in DLL-off mode for low frequency + * operation. Set to 0 to put DDRC and DRAM in DLL-on mode for normal frequency operation. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), dll_off_mode is not + * supported, and this bit must be set to '0'. + */ +#define DDRC_MSTR_dll_off_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_dll_off_mode_SHIFT)) & DDRC_MSTR_dll_off_mode_MASK) + +#define DDRC_MSTR_burst_rdwr_MASK (0xF0000U) +#define DDRC_MSTR_burst_rdwr_SHIFT (16U) +/*! burst_rdwr - SDRAM burst length used + * 0b0001..Burst length of 2 (only supported for mDDR) + * 0b0010..Burst length of 4 + * 0b0100..Burst length of 8 + * 0b1000..Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) + */ +#define DDRC_MSTR_burst_rdwr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burst_rdwr_SHIFT)) & DDRC_MSTR_burst_rdwr_MASK) + +#define DDRC_MSTR_frequency_ratio_MASK (0x400000U) +#define DDRC_MSTR_frequency_ratio_SHIFT (22U) +/*! frequency_ratio - Selects the Frequency Ratio + * 0b0..1:2 Mode + * 0b1..1:1 Mode + */ +#define DDRC_MSTR_frequency_ratio(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_ratio_SHIFT)) & DDRC_MSTR_frequency_ratio_MASK) + +#define DDRC_MSTR_active_ranks_MASK (0x3000000U) +#define DDRC_MSTR_active_ranks_SHIFT (24U) +/*! active_ranks - Only present for multi-rank configurations. Each bit represents one rank. For + * two-rank configurations, only bits[25:24] are present. + */ +#define DDRC_MSTR_active_ranks(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_active_ranks_SHIFT)) & DDRC_MSTR_active_ranks_MASK) + +#define DDRC_MSTR_frequency_mode_MASK (0x20000000U) +#define DDRC_MSTR_frequency_mode_SHIFT (29U) +/*! frequency_mode - Choose which registers are used. + * 0b0..Original Registers + * 0b1..Shadow Registers + */ +#define DDRC_MSTR_frequency_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_mode_SHIFT)) & DDRC_MSTR_frequency_mode_MASK) + +#define DDRC_MSTR_device_config_MASK (0xC0000000U) +#define DDRC_MSTR_device_config_SHIFT (30U) +/*! device_config - Indicates the configuration of the device used in the system. + * 0b00..x4 device + * 0b01..x8 device + * 0b10..x16 device + * 0b11..x32 device + */ +#define DDRC_MSTR_device_config(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_device_config_SHIFT)) & DDRC_MSTR_device_config_MASK) +/*! @} */ + +/*! @name STAT - Operating Mode Status Register */ +/*! @{ */ + +#define DDRC_STAT_operating_mode_MASK (0x7U) +#define DDRC_STAT_operating_mode_SHIFT (0U) +/*! operating_mode - Operating mode + */ +#define DDRC_STAT_operating_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_operating_mode_SHIFT)) & DDRC_STAT_operating_mode_MASK) + +#define DDRC_STAT_selfref_type_MASK (0x30U) +#define DDRC_STAT_selfref_type_SHIFT (4U) +/*! selfref_type - Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if + * it was under Automatic Self Refresh control only or not. + * 0b00..SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by + * CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is + * in-progress. + * 0b11..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self + * Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error. + * 0b10..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under + * Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software + * (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity + */ +#define DDRC_STAT_selfref_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_type_SHIFT)) & DDRC_STAT_selfref_type_MASK) + +#define DDRC_STAT_selfref_state_MASK (0x300U) +#define DDRC_STAT_selfref_state_SHIFT (8U) +/*! selfref_state - Self refresh state. This indicates self refresh or self refresh power down state + * for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh. + * 0b00..SDRAM is not in Self Refresh. + * 0b01..Self refresh 1 + * 0b10..Self refresh power down + * 0b11..Self refresh + */ +#define DDRC_STAT_selfref_state(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_state_SHIFT)) & DDRC_STAT_selfref_state_MASK) +/*! @} */ + +/*! @name MRCTRL0 - Mode Register Read/Write Control Register 0. */ +/*! @{ */ + +#define DDRC_MRCTRL0_mr_type_MASK (0x1U) +#define DDRC_MRCTRL0_mr_type_SHIFT (0U) +/*! mr_type - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. + * 0b0..Write + * 0b1..Read + */ +#define DDRC_MRCTRL0_mr_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_type_SHIFT)) & DDRC_MRCTRL0_mr_type_MASK) + +#define DDRC_MRCTRL0_mpr_en_MASK (0x2U) +#define DDRC_MRCTRL0_mpr_en_SHIFT (1U) +/*! mpr_en - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4). + * 0b0..MRS + * 0b1..WR/RD for MPR + */ +#define DDRC_MRCTRL0_mpr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mpr_en_SHIFT)) & DDRC_MRCTRL0_mpr_en_MASK) + +#define DDRC_MRCTRL0_pda_en_MASK (0x4U) +#define DDRC_MRCTRL0_pda_en_SHIFT (2U) +/*! pda_en - Indicates whether the mode register operation is MRS in PDA mode or not. Note that when + * pba_mode=1, PBA access is initiated instead of PDA access. + * 0b0..MRS + * 0b1..MRS in Per DRAM Addressability + */ +#define DDRC_MRCTRL0_pda_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pda_en_SHIFT)) & DDRC_MRCTRL0_pda_en_MASK) + +#define DDRC_MRCTRL0_sw_init_int_MASK (0x8U) +#define DDRC_MRCTRL0_sw_init_int_SHIFT (3U) +/*! sw_init_int - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before + * automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the + * DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to + * program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4 + * independent channel mode, note that this must be programmed to both channels beforehand. Note that + * this must be cleared to 0 after completing Software operation. Otherwise, SDRAM + * initialization routine will not re-start. + * 0b0..Software intervention is not allowed + * 0b1..Software intervention is allowed + */ +#define DDRC_MRCTRL0_sw_init_int(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_sw_init_int_SHIFT)) & DDRC_MRCTRL0_sw_init_int_MASK) + +#define DDRC_MRCTRL0_mr_rank_MASK (0x30U) +#define DDRC_MRCTRL0_mr_rank_SHIFT (4U) +/*! mr_rank - Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access + * all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which + * implement address mirroring, it may be necessary to access ranks individually. Examples (assume + * DDRC is configured for 4 ranks): 0x1 - select rank 0 only select rank 1 only select ranks 0 + * and 2 select ranks 1 and 3 select ranks 0, 1, 2 and 3 + */ +#define DDRC_MRCTRL0_mr_rank(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_rank_SHIFT)) & DDRC_MRCTRL0_mr_rank_MASK) + +#define DDRC_MRCTRL0_mr_addr_MASK (0xF000U) +#define DDRC_MRCTRL0_mr_addr_SHIFT (12U) +/*! mr_addr - Address of the mode register that is to be written to. + * 0b0000..MR0 + * 0b0001..MR1 + * 0b0010..MR2 + * 0b0011..MR3 + * 0b0100..MR4 + * 0b0101..MR5 + * 0b0110..MR6 + * 0b0111..MR7 + */ +#define DDRC_MRCTRL0_mr_addr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_addr_SHIFT)) & DDRC_MRCTRL0_mr_addr_MASK) + +#define DDRC_MRCTRL0_pba_mode_MASK (0x40000000U) +#define DDRC_MRCTRL0_pba_mode_SHIFT (30U) +/*! pba_mode - Indicates whether PBA access is executed. When setting this bit to 1 along with + * setting pda_en to 1, DDRC initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability + * mode - 1 - Per Buffer Addressability mode The completion of PBA access is confirmed by + * MRSTAT.pda_done in the same way as PDA. + */ +#define DDRC_MRCTRL0_pba_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pba_mode_SHIFT)) & DDRC_MRCTRL0_pba_mode_MASK) + +#define DDRC_MRCTRL0_mr_wr_MASK (0x80000000U) +#define DDRC_MRCTRL0_mr_wr_SHIFT (31U) +/*! mr_wr - Setting this register bit to 1 triggers a mode register read or write operation. When + * the MR operation is complete, the DDRC automatically clears this bit. The other register fields + * of this register must be written in a separate APB transaction, before setting this mr_wr bit. + * It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. + */ +#define DDRC_MRCTRL0_mr_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_wr_SHIFT)) & DDRC_MRCTRL0_mr_wr_MASK) +/*! @} */ + +/*! @name MRCTRL1 - Mode Register Read/Write Control Register 1 */ +/*! @{ */ + +#define DDRC_MRCTRL1_mr_data_MASK (0x3FFFFU) +#define DDRC_MRCTRL1_mr_data_SHIFT (0U) +/*! mr_data - Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For + * LPDDR2/LPDDR3/LPDDR4, MRCTRL1[15:0] are interpreted as [15:8] MR Address [7:0] MR data for writes, + * don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all + * other configurations. + */ +#define DDRC_MRCTRL1_mr_data(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL1_mr_data_SHIFT)) & DDRC_MRCTRL1_mr_data_MASK) +/*! @} */ + +/*! @name MRSTAT - Mode Register Read/Write Status Register */ +/*! @{ */ + +#define DDRC_MRSTAT_mr_wr_busy_MASK (0x1U) +#define DDRC_MRSTAT_mr_wr_busy_SHIFT (0U) +/*! mr_wr_busy - The SoC core may initiate a MR write operation only if this signal is low. This + * signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the + * MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when + * 'MRSTAT.mr_wr_busy' is high. + * 0b0..Indicates that the SoC core can initiate a mode register write operation + * 0b1..Indicates that mode register write operation is in progress + */ +#define DDRC_MRSTAT_mr_wr_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_mr_wr_busy_SHIFT)) & DDRC_MRSTAT_mr_wr_busy_MASK) + +#define DDRC_MRSTAT_pda_done_MASK (0x100U) +#define DDRC_MRSTAT_pda_done_SHIFT (8U) +/*! pda_done - The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is + * low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode + * are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is + * recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to + * perform PDA operation next time + * 0b0..Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet. + * 0b1..Indicates that mode register write operation related to PDA/PBA has competed. + */ +#define DDRC_MRSTAT_pda_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_pda_done_SHIFT)) & DDRC_MRSTAT_pda_done_MASK) +/*! @} */ + +/*! @name MRCTRL2 - Mode Register Read/Write Control Register 2 */ +/*! @{ */ + +#define DDRC_MRCTRL2_mr_device_sel_MASK (0xFFFFFFFFU) +#define DDRC_MRCTRL2_mr_device_sel_SHIFT (0U) +/*! mr_device_sel - Indicates the device(s) to be selected during the MRS that happens in PDA mode. + * Each bit is associated with one device. For example, bit[0] corresponds to Device 0, bit[1] to + * Device 1 etc. A '1' should be programmed to indicate that the MRS command should be applied + * to that device. A '0' indicates that the MRS commands should be skipped for that device. + */ +#define DDRC_MRCTRL2_mr_device_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL2_mr_device_sel_SHIFT)) & DDRC_MRCTRL2_mr_device_sel_MASK) +/*! @} */ + +/*! @name DERATEEN - Temperature Derate Enable Register */ +/*! @{ */ + +#define DDRC_DERATEEN_derate_enable_MASK (0x1U) +#define DDRC_DERATEEN_derate_enable_SHIFT (0U) +/*! derate_enable - Enables derating. Present only in designs configured to support + * LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. + * 0b0..Timing parameter derating is disabled + * 0b1..Timing parameter derating is enabled using MR4 read value. + */ +#define DDRC_DERATEEN_derate_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_enable_SHIFT)) & DDRC_DERATEEN_derate_enable_MASK) + +#define DDRC_DERATEEN_derate_value_MASK (0x2U) +#define DDRC_DERATEEN_derate_value_SHIFT (1U) +/*! derate_value - Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 + * Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a + * core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this + * register field should be set to 1; otherwise it should be set to 0. + * 0b0..Derating uses +1 + * 0b1..Derating uses +2 + */ +#define DDRC_DERATEEN_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_value_SHIFT)) & DDRC_DERATEEN_derate_value_MASK) + +#define DDRC_DERATEEN_derate_byte_MASK (0xF0U) +#define DDRC_DERATEEN_derate_byte_SHIFT (4U) +/*! derate_byte - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 + * Indicates which byte of the MRR data is used for derating. The maximum valid value depends on + * MEMC_DRAM_TOTAL_DATA_WIDTH. + */ +#define DDRC_DERATEEN_derate_byte(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_byte_SHIFT)) & DDRC_DERATEEN_derate_byte_MASK) + +#define DDRC_DERATEEN_rc_derate_value_MASK (0x300U) +#define DDRC_DERATEEN_rc_derate_value_SHIFT (8U) +/*! rc_derate_value - Derate value of tRC for LPDDR4. Present only in designs configured to support + * LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the + * core_ddrc_core_clk period, and rounding up the next integer. + * 0b00..Derating uses +1 + * 0b01..Derating uses +2 + * 0b10..Derating uses +3 + * 0b11..Derating uses +4 + */ +#define DDRC_DERATEEN_rc_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_rc_derate_value_SHIFT)) & DDRC_DERATEEN_rc_derate_value_MASK) +/*! @} */ + +/*! @name DERATEINT - Temperature Derate Interval Register */ +/*! @{ */ + +#define DDRC_DERATEINT_mr4_read_interval_MASK (0xFFFFFFFFU) +#define DDRC_DERATEINT_mr4_read_interval_SHIFT (0U) +/*! mr4_read_interval - Interval between two MR4 reads, used to derate the timing parameters. + * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to + * zero. Unit: DFI clock cycle. + */ +#define DDRC_DERATEINT_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_mr4_read_interval_MASK) +/*! @} */ + +/*! @name PWRCTL - Low Power Control Register */ +/*! @{ */ + +#define DDRC_PWRCTL_selfref_en_MASK (0x1U) +#define DDRC_PWRCTL_selfref_en_SHIFT (0U) +/*! selfref_en - If true then the DDRC puts the SDRAM into Self Refresh after a programmable number + * of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit + * may be re-programmed during the course of normal operation. + */ +#define DDRC_PWRCTL_selfref_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_en_SHIFT)) & DDRC_PWRCTL_selfref_en_MASK) + +#define DDRC_PWRCTL_powerdown_en_MASK (0x2U) +#define DDRC_PWRCTL_powerdown_en_SHIFT (1U) +/*! powerdown_en - If true then the DDRC goes into power-down after a programmable number of cycles + * "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). This register bit may be + * re-programmed during the course of normal operation. + */ +#define DDRC_PWRCTL_powerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_powerdown_en_SHIFT)) & DDRC_PWRCTL_powerdown_en_MASK) + +#define DDRC_PWRCTL_deeppowerdown_en_MASK (0x4U) +#define DDRC_PWRCTL_deeppowerdown_en_SHIFT (2U) +/*! deeppowerdown_en - When this is 1, DDRC puts the SDRAM into deep power-down mode when the + * transaction store is empty. This register must be reset to '0' to bring DDRC out of deep power-down + * mode. Controller performs automatic SDRAM initialization on deep power-down exit. Present only + * in designs configured to support mDDR or LPDDR2 or LPDDR3. For + * non-mDDR/non-LPDDR2/non-LPDDR3, this register should not be set to 1. FOR PERFORMANCE ONLY. + */ +#define DDRC_PWRCTL_deeppowerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_deeppowerdown_en_SHIFT)) & DDRC_PWRCTL_deeppowerdown_en_MASK) + +#define DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK (0x8U) +#define DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT (3U) +/*! en_dfi_dram_clk_disable - Enable the assertion of dfi_dram_clk_disable whenever a clock is not + * required by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. Assertion of + * dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DDR4, can + * be asserted in following: in Self Refresh in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, + * can be asserted in following: in Self Refresh in Power Down in Deep Power Down during Normal + * operation (Clock Stop) In LPDDR4, can be asserted in following: in Self Refresh Power Down in + * Power Down during Normal operation (Clock Stop) + */ +#define DDRC_PWRCTL_en_dfi_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT)) & DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK) + +#define DDRC_PWRCTL_mpsm_en_MASK (0x10U) +#define DDRC_PWRCTL_mpsm_en_SHIFT (4U) +/*! mpsm_en - When this is 1, the DDRC puts the SDRAM into maximum power saving mode when the + * transaction store is empty. This register must be reset to '0' to bring DDRC out of maximum power + * saving mode. Present only in designs configured to support DDR4. For non-DDR4, this register + * should not be set to 1. Note that MPSM is not supported when using a DDR PHY, if the PHY + * parameter DDRC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to + * toggle. FOR PERFORMANCE ONLY. + */ +#define DDRC_PWRCTL_mpsm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_mpsm_en_SHIFT)) & DDRC_PWRCTL_mpsm_en_MASK) + +#define DDRC_PWRCTL_selfref_sw_MASK (0x20U) +#define DDRC_PWRCTL_selfref_sw_SHIFT (5U) +/*! selfref_sw - A value of 1 to this register causes system to move to Self Refresh state + * immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software + * Entry/Exit to Self Refresh. + * 0b0..Software Exit from Self Refresh + * 0b1..Software Entry to Self Refresh + */ +#define DDRC_PWRCTL_selfref_sw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_sw_SHIFT)) & DDRC_PWRCTL_selfref_sw_MASK) + +#define DDRC_PWRCTL_stay_in_selfref_MASK (0x40U) +#define DDRC_PWRCTL_stay_in_selfref_SHIFT (6U) +/*! stay_in_selfref - Self refresh state is an intermediate state to enter to Self refresh power + * down state or exit Self refresh power down state for LPDDR4. This register controls transition + * from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow + * transition from Self refresh state + * 0b0.. + * 0b1.. + */ +#define DDRC_PWRCTL_stay_in_selfref(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_stay_in_selfref_SHIFT)) & DDRC_PWRCTL_stay_in_selfref_MASK) +/*! @} */ + +/*! @name PWRTMG - Low Power Timing Register */ +/*! @{ */ + +#define DDRC_PWRTMG_powerdown_to_x32_MASK (0x1FU) +#define DDRC_PWRTMG_powerdown_to_x32_SHIFT (0U) +/*! powerdown_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC + * automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there + * are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. Unit: + * Multiples of 32 DFI clocks FOR PERFORMANCE ONLY. + */ +#define DDRC_PWRTMG_powerdown_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_powerdown_to_x32_SHIFT)) & DDRC_PWRTMG_powerdown_to_x32_MASK) + +#define DDRC_PWRTMG_t_dpd_x4096_MASK (0xFF00U) +#define DDRC_PWRTMG_t_dpd_x4096_SHIFT (8U) +/*! t_dpd_x4096 - Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as + * mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is + * de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Multiples of 4096 DFI + * clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + * ONLY. + */ +#define DDRC_PWRTMG_t_dpd_x4096(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_t_dpd_x4096_SHIFT)) & DDRC_PWRTMG_t_dpd_x4096_MASK) + +#define DDRC_PWRTMG_selfref_to_x32_MASK (0xFF0000U) +#define DDRC_PWRTMG_selfref_to_x32_SHIFT (16U) +/*! selfref_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC + * automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there + * are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. Unit: + * Multiples of 32 DFI clocks. FOR PERFORMANCE ONLY. + */ +#define DDRC_PWRTMG_selfref_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_selfref_to_x32_SHIFT)) & DDRC_PWRTMG_selfref_to_x32_MASK) +/*! @} */ + +/*! @name HWLPCTL - Hardware Low Power Control Register */ +/*! @{ */ + +#define DDRC_HWLPCTL_hw_lp_en_MASK (0x1U) +#define DDRC_HWLPCTL_hw_lp_en_SHIFT (0U) +/*! hw_lp_en - Enable for Hardware Low Power Interface. + */ +#define DDRC_HWLPCTL_hw_lp_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_en_MASK) + +#define DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK (0x2U) +#define DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT (1U) +/*! hw_lp_exit_idle_en - When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be + * used to exit from the automatic clock stop, automatic power down or automatic self-refresh + * modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power + * Interface and/or Software (PWRCTL.selfref_sw). + */ +#define DDRC_HWLPCTL_hw_lp_exit_idle_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK) + +#define DDRC_HWLPCTL_hw_lp_idle_x32_MASK (0xFFF0000U) +#define DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT (16U) +/*! hw_lp_idle_x32 - Hardware idle period. The cactive_ddrc output is driven low if the DDRC command + * channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The + * DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware + * idle function is disabled when hw_lp_idle_x32=0. Unit: Multiples of 32 DFI clocks. FOR + * PERFORMANCE ONLY. + */ +#define DDRC_HWLPCTL_hw_lp_idle_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT)) & DDRC_HWLPCTL_hw_lp_idle_x32_MASK) +/*! @} */ + +/*! @name RFSHCTL0 - Refresh Control Register 0 */ +/*! @{ */ + +#define DDRC_RFSHCTL0_per_bank_refresh_MASK (0x4U) +#define DDRC_RFSHCTL0_per_bank_refresh_SHIFT (2U) +/*! per_bank_refresh - Per bank refresh allows traffic to flow to other banks. Per bank refresh is + * not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. + * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 + * 0b1..Per bank refresh + * 0b0..All bank refresh + */ +#define DDRC_RFSHCTL0_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_per_bank_refresh_MASK) + +#define DDRC_RFSHCTL0_refresh_burst_MASK (0x1F0U) +#define DDRC_RFSHCTL0_refresh_burst_SHIFT (4U) +/*! refresh_burst - The programmed value + 1 is the number of refresh timeouts that is allowed to + * accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to + * perform a refresh is a one-time penalty that must be paid for each group of refreshes. + * Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. + * Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases + * the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2 + * refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of + * DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not + * per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh + * feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X + * mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care + * must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated + * due to a PHY-initiated update occurring shortly before a refresh burst was due. In this + * situation, the refresh burst will be delayed until the PHY-initiated update is complete. + */ +#define DDRC_RFSHCTL0_refresh_burst(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_refresh_burst_MASK) + +#define DDRC_RFSHCTL0_refresh_to_x32_MASK (0x1F000U) +#define DDRC_RFSHCTL0_refresh_to_x32_SHIFT (12U) +/*! refresh_to_x32 - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, + * but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be + * performed. A speculative refresh is a refresh performed at a time when refresh would be + * useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time + * determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since + * the last refresh, then a speculative refresh is performed. Speculative refreshes continues + * successively until there are no refreshes pending or until new reads or writes are issued to the + * DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks. + */ +#define DDRC_RFSHCTL0_refresh_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_refresh_to_x32_MASK) + +#define DDRC_RFSHCTL0_refresh_margin_MASK (0xF00000U) +#define DDRC_RFSHCTL0_refresh_margin_SHIFT (20U) +/*! refresh_margin - Threshold value in number of DFI clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this threshold is reached. It is + * recommended that this not be changed from the default value, currently shown as 0x2. It must + * always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, + * internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled + * (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to + * RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks. + */ +#define DDRC_RFSHCTL0_refresh_margin(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_refresh_margin_MASK) +/*! @} */ + +/*! @name RFSHCTL1 - Refresh Control Register 1 */ +/*! @{ */ + +#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK (0xFFFU) +#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT (0U) +/*! refresh_timer0_start_value_x32 - Refresh timer start for rank 0 (only present in multi-rank + * configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to + * proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples + * of 32 DFI clock cycles. FOR PERFORMANCE ONLY. + */ +#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK) + +#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK (0xFFF0000U) +#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT (16U) +/*! refresh_timer1_start_value_x32 - Refresh timer start for rank 1 (only present in multi-rank + * configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to + * proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples + * of 32 DFI clock cycles. FOR PERFORMANCE ONLY. + */ +#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK) +/*! @} */ + +/*! @name RFSHCTL3 - Refresh Control Register 3 */ +/*! @{ */ + +#define DDRC_RFSHCTL3_dis_auto_refresh_MASK (0x1U) +#define DDRC_RFSHCTL3_dis_auto_refresh_SHIFT (0U) +/*! dis_auto_refresh - When '1', disable auto-refresh generated by the DDRC. When auto-refresh is + * disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh, + * reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis_auto_refresh + * transitions from 0 to 1, any pending refreshes are immediately scheduled by the DDRC. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is + * not supported, and this bit must be set to '0'. (DDR4 only) If FGR mode is enabled + * (RFSHCTL3.refresh_mode > 0), disable auto-refresh is not supported, and this bit must be set to '0'. This + * register field is changeable on the fly. + */ +#define DDRC_RFSHCTL3_dis_auto_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_dis_auto_refresh_SHIFT)) & DDRC_RFSHCTL3_dis_auto_refresh_MASK) + +#define DDRC_RFSHCTL3_refresh_update_level_MASK (0x2U) +#define DDRC_RFSHCTL3_refresh_update_level_SHIFT (1U) +/*! refresh_update_level - Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + * the refresh register(s) have been updated. refresh_update_level must not be toggled when the + * DDRC is in reset (core_ddrc_rstn = 0). The refresh register(s) are automatically updated when + * exiting reset. + */ +#define DDRC_RFSHCTL3_refresh_update_level(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_update_level_SHIFT)) & DDRC_RFSHCTL3_refresh_update_level_MASK) + +#define DDRC_RFSHCTL3_refresh_mode_MASK (0x70U) +#define DDRC_RFSHCTL3_refresh_mode_SHIFT (4U) +/*! refresh_mode - Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - + * 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not + * supported) - Everything else - reserved Note: Only Fixed 1x mode is supported if + * RFSHCTL3.dis_auto_refresh = 1. Note: The on-the-fly modes are not supported in this version of the DDRC. + * Note: This must be set up while the Controller is in reset or while the Controller is in + * self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic + * register will be supported in future version of the DDRC. Note: This register field has effect only + * if a DDR4 SDRAM device is in use (MSTR.ddr4 = 1). + */ +#define DDRC_RFSHCTL3_refresh_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_mode_SHIFT)) & DDRC_RFSHCTL3_refresh_mode_MASK) +/*! @} */ + +/*! @name RFSHTMG - Refresh Timing Register */ +/*! @{ */ + +#define DDRC_RFSHTMG_t_rfc_min_MASK (0x3FFU) +#define DDRC_RFSHTMG_t_rfc_min_SHIFT (0U) +/*! t_rfc_min - tRFC (min): Minimum time from refresh to refresh or activate. When the controller is + * operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller + * is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In + * LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations + * is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is + * equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending + * on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the + * appropriate value from the spec based on the 'refresh_mode' and the device density that is used. + * Unit: Clocks. + */ +#define DDRC_RFSHTMG_t_rfc_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_t_rfc_min_MASK) + +#define DDRC_RFSHTMG_lpddr3_trefbw_en_MASK (0x8000U) +#define DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT (15U) +/*! lpddr3_trefbw_en - Used only when LPDDR3 memory type is connected. Should only be changed when + * DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 + * devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW + * parameter not used - 1 - tREFBW parameter used + */ +#define DDRC_RFSHTMG_lpddr3_trefbw_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_lpddr3_trefbw_en_MASK) + +#define DDRC_RFSHTMG_t_rfc_nom_x32_MASK (0xFFF0000U) +#define DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT (16U) +/*! t_rfc_nom_x32 - tREFI: Average time interval between refreshes per rank (Specification: 7.8us + * for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For + * LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register + * should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode, + * program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending + * on the refresh mode. The user should program the appropriate value from the spec based on the + * value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be + * greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or + * DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed + * 2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode: + * RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks. + */ +#define DDRC_RFSHTMG_t_rfc_nom_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_t_rfc_nom_x32_MASK) +/*! @} */ + +/*! @name CRCPARCTL0 - CRC Parity Control Register0 */ +/*! @{ */ + +#define DDRC_CRCPARCTL0_dfi_alert_err_int_en_MASK (0x1U) +#define DDRC_CRCPARCTL0_dfi_alert_err_int_en_SHIFT (0U) +/*! dfi_alert_err_int_en - Interrupt enable bit for DFI alert error. If this bit is set, any + * parity/CRC error detected on the dfi_alert_n input will result in an interrupt being set on + * CRCPARSTAT.dfi_alert_err_int. + */ +#define DDRC_CRCPARCTL0_dfi_alert_err_int_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CRCPARCTL0_dfi_alert_err_int_en_SHIFT)) & DDRC_CRCPARCTL0_dfi_alert_err_int_en_MASK) + +#define DDRC_CRCPARCTL0_dfi_alert_err_int_clr_MASK (0x2U) +#define DDRC_CRCPARCTL0_dfi_alert_err_int_clr_SHIFT (1U) +/*! dfi_alert_err_int_clr - Interrupt clear bit for DFI alert error. If this bit is set, the alert + * error interrupt on CRCPARSTAT.dfi_alert_err_int will be cleared. When the clear operation is + * complete, the DDRC automatically clears this bit. + */ +#define DDRC_CRCPARCTL0_dfi_alert_err_int_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CRCPARCTL0_dfi_alert_err_int_clr_SHIFT)) & DDRC_CRCPARCTL0_dfi_alert_err_int_clr_MASK) + +#define DDRC_CRCPARCTL0_dfi_alert_err_cnt_clr_MASK (0x4U) +#define DDRC_CRCPARCTL0_dfi_alert_err_cnt_clr_SHIFT (2U) +/*! dfi_alert_err_cnt_clr - DFI alert error count clear. Clear bit for DFI alert error counter. + * Asserting this bit will clear the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the + * clear operation is complete, the DDRC automatically clears this bit. + */ +#define DDRC_CRCPARCTL0_dfi_alert_err_cnt_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CRCPARCTL0_dfi_alert_err_cnt_clr_SHIFT)) & DDRC_CRCPARCTL0_dfi_alert_err_cnt_clr_MASK) +/*! @} */ + +/*! @name CRCPARCTL1 - CRC Parity Control Register1 */ +/*! @{ */ + +#define DDRC_CRCPARCTL1_parity_enable_MASK (0x1U) +#define DDRC_CRCPARCTL1_parity_enable_SHIFT (0U) +/*! parity_enable - C/A Parity enable register. If RCD's parity error detection or SDRAM's parity + * detection is enabled, this register should be 1. + * 0b0..Disable generation of C/A parity and disable detection of C/A parity error + * 0b1..Enable generation of C/A parity and detection of C/A parity error + */ +#define DDRC_CRCPARCTL1_parity_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CRCPARCTL1_parity_enable_SHIFT)) & DDRC_CRCPARCTL1_parity_enable_MASK) + +#define DDRC_CRCPARCTL1_crc_enable_MASK (0x10U) +#define DDRC_CRCPARCTL1_crc_enable_SHIFT (4U) +/*! crc_enable - CRC enable Register. The setting of this register should match the CRC mode register setting in the DRAM. + * 0b0..isable generation of CRC + * 0b1..Enable generation of CRC + */ +#define DDRC_CRCPARCTL1_crc_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CRCPARCTL1_crc_enable_SHIFT)) & DDRC_CRCPARCTL1_crc_enable_MASK) + +#define DDRC_CRCPARCTL1_crc_inc_dm_MASK (0x80U) +#define DDRC_CRCPARCTL1_crc_inc_dm_SHIFT (7U) +/*! crc_inc_dm - CRC Calculation setting register. Present only in designs configured to support DDR4. + * 0b0..CRC not includes DM signal + * 0b1..CRC includes DM signal + */ +#define DDRC_CRCPARCTL1_crc_inc_dm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CRCPARCTL1_crc_inc_dm_SHIFT)) & DDRC_CRCPARCTL1_crc_inc_dm_MASK) + +#define DDRC_CRCPARCTL1_caparity_disable_before_sr_MASK (0x1000U) +#define DDRC_CRCPARCTL1_caparity_disable_before_sr_SHIFT (12U) +/*! caparity_disable_before_sr - If DDR4-SDRAM's CA parity is enabled by INIT6.mr5[2:0]!=0 and this + * register is set to 1, CA parity is automatically disabled before Self-Refresh entry and + * enabled after Self-Refresh exit by issuing MR5. - 1: CA parity is disabled before Self-Refresh entry + * - 0: CA parity is not disabled before Self-Refresh entry If Geardown is used by + * MSTR.geardown_mode=1, this register must be set to 1. If this register set to 0, DRAMTMG5.t_ckesr and + * DRAMTMG5.t_cksre must be increased by PL(Parity latency) + * 0b0..CA parity is not disabled before Self-Refresh entry + * 0b1..CA parity is disabled before Self-Refresh entry + */ +#define DDRC_CRCPARCTL1_caparity_disable_before_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CRCPARCTL1_caparity_disable_before_sr_SHIFT)) & DDRC_CRCPARCTL1_caparity_disable_before_sr_MASK) +/*! @} */ + +/*! @name CRCPARSTAT - CRC Parity Status Register */ +/*! @{ */ + +#define DDRC_CRCPARSTAT_dfi_alert_err_cnt_MASK (0xFFFFU) +#define DDRC_CRCPARSTAT_dfi_alert_err_cnt_SHIFT (0U) +/*! dfi_alert_err_cnt - DFI alert error count. If a parity/CRC error is detected on dfi_alert_n, + * this counter be incremented. This is independent of the setting of + * CRCPARCTL0.dfi_alert_err_int_en. It will saturate at 0xFFFF, and can be cleared by asserting + * CRCPARCTL0.dfi_alert_err_cnt_clr. + */ +#define DDRC_CRCPARSTAT_dfi_alert_err_cnt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CRCPARSTAT_dfi_alert_err_cnt_SHIFT)) & DDRC_CRCPARSTAT_dfi_alert_err_cnt_MASK) + +#define DDRC_CRCPARSTAT_dfi_alert_err_int_MASK (0x10000U) +#define DDRC_CRCPARSTAT_dfi_alert_err_int_SHIFT (16U) +/*! dfi_alert_err_int - DFI alert error interrupt. If a parity/CRC error is detected on dfi_alert_n, + * and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit will be + * set. It will remain set until cleared by CRCPARCTL0.dfi_alert_err_int_clr + */ +#define DDRC_CRCPARSTAT_dfi_alert_err_int(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CRCPARSTAT_dfi_alert_err_int_SHIFT)) & DDRC_CRCPARSTAT_dfi_alert_err_int_MASK) +/*! @} */ + +/*! @name INIT0 - SDRAM Initialization Register 0 */ +/*! @{ */ + +#define DDRC_INIT0_pre_cke_x1024_MASK (0xFFFU) +#define DDRC_INIT0_pre_cke_x1024_SHIFT (0U) +/*! pre_cke_x1024 - Cycles to wait after reset before driving CKE high to start the SDRAM + * initialization sequence. Unit: 1024 DFI clock cycles. DDR2 specifications typically require this to be + * programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 + * ms (min) When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC + * spec value divided by 2, and round it up to the next integer value. For DDR3/DDR4 RDIMMs, this + * should include the time needed to satisfy tSTAB + */ +#define DDRC_INIT0_pre_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_pre_cke_x1024_SHIFT)) & DDRC_INIT0_pre_cke_x1024_MASK) + +#define DDRC_INIT0_post_cke_x1024_MASK (0x3FF0000U) +#define DDRC_INIT0_post_cke_x1024_SHIFT (16U) +/*! post_cke_x1024 - Cycles to wait after driving CKE high to start the SDRAM initialization + * sequence. Unit: 1024 DFI clock cycles. DDR2 typically requires a 400 ns delay, requiring this value + * to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be + * programmed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. + * When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec + * value divided by 2, and round it up to the next integer value. + */ +#define DDRC_INIT0_post_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_post_cke_x1024_SHIFT)) & DDRC_INIT0_post_cke_x1024_MASK) + +#define DDRC_INIT0_skip_dram_init_MASK (0xC0000000U) +#define DDRC_INIT0_skip_dram_init_SHIFT (30U) +/*! skip_dram_init - If lower bit is enabled the SDRAM initialization routine is skipped. The upper + * bit decides what state the controller starts up in when reset is removed - 00 - SDRAM + * Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after + * power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after + * power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run + * after power-up. + * 0b00..SDRAM Initialization routine is run after power-up + * 0b01..SDRAM Initialization routine is skipped after power-up + * 0b10..SDRAM Initialization routine is run after power-up + * 0b11..SDRAM Initialization routine is skipped after power-up + */ +#define DDRC_INIT0_skip_dram_init(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_skip_dram_init_SHIFT)) & DDRC_INIT0_skip_dram_init_MASK) +/*! @} */ + +/*! @name INIT1 - SDRAM Initialization Register 1 */ +/*! @{ */ + +#define DDRC_INIT1_pre_ocd_x32_MASK (0xFU) +#define DDRC_INIT1_pre_ocd_x32_SHIFT (0U) +/*! pre_ocd_x32 - Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a + * global timer that pulses every 32 DFI clock cycles. There is no known specific requirement for + * this; it may be set to zero. + */ +#define DDRC_INIT1_pre_ocd_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_pre_ocd_x32_SHIFT)) & DDRC_INIT1_pre_ocd_x32_MASK) + +#define DDRC_INIT1_dram_rstn_x1024_MASK (0x1FF0000U) +#define DDRC_INIT1_dram_rstn_x1024_SHIFT (16U) +/*! dram_rstn_x1024 - Number of cycles to assert SDRAM reset signal during init sequence. This is + * only present for designs supporting DDR3, DDR4 or LPDDR4 devices. For use with a DDR PHY, this + * should be set to a minimum of 1. When the controller is operating in 1:2 frequency ratio mode, + * program this to JEDEC spec value divided by 2, and round it up to the next integer value. + * Unit: 1024 DFI clock cycles. + */ +#define DDRC_INIT1_dram_rstn_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_dram_rstn_x1024_SHIFT)) & DDRC_INIT1_dram_rstn_x1024_MASK) +/*! @} */ + +/*! @name INIT2 - SDRAM Initialization Register 2 */ +/*! @{ */ + +#define DDRC_INIT2_min_stable_clock_x1_MASK (0xFU) +#define DDRC_INIT2_min_stable_clock_x1_SHIFT (0U) +/*! min_stable_clock_x1 - Time to wait after the first CKE high, tINIT2. Present only in designs + * configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the + * controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by + * 2, and round it up to the next integer value. Unit: DFI clock cycles. + */ +#define DDRC_INIT2_min_stable_clock_x1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_min_stable_clock_x1_SHIFT)) & DDRC_INIT2_min_stable_clock_x1_MASK) + +#define DDRC_INIT2_idle_after_reset_x32_MASK (0xFF00U) +#define DDRC_INIT2_idle_after_reset_x32_SHIFT (8U) +/*! idle_after_reset_x32 - Idle time after the reset command, tINIT4. Present only in designs + * configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode, program + * this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 32 DFI + * clock cycles. + */ +#define DDRC_INIT2_idle_after_reset_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_idle_after_reset_x32_SHIFT)) & DDRC_INIT2_idle_after_reset_x32_MASK) +/*! @} */ + +/*! @name INIT3 - SDRAM Initialization Register 3 */ +/*! @{ */ + +#define DDRC_INIT3_emr_MASK (0xFFFFU) +#define DDRC_INIT3_emr_SHIFT (0U) +/*! emr - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this + * register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1 + * register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by + * the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - + * Value to write to MR2 register + */ +#define DDRC_INIT3_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_emr_SHIFT)) & DDRC_INIT3_emr_MASK) + +#define DDRC_INIT3_mr_MASK (0xFFFF0000U) +#define DDRC_INIT3_mr_SHIFT (16U) +/*! mr - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The + * DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to + * write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register + */ +#define DDRC_INIT3_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_mr_SHIFT)) & DDRC_INIT3_mr_MASK) +/*! @} */ + +/*! @name INIT4 - SDRAM Initialization Register 4 */ +/*! @{ */ + +#define DDRC_INIT4_emr3_MASK (0xFFFFU) +#define DDRC_INIT4_emr3_SHIFT (0U) +/*! emr3 - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register + * mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register + */ +#define DDRC_INIT4_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr3_SHIFT)) & DDRC_INIT4_emr3_MASK) + +#define DDRC_INIT4_emr2_MASK (0xFFFF0000U) +#define DDRC_INIT4_emr2_SHIFT (16U) +/*! emr2 - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register + * LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused + */ +#define DDRC_INIT4_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr2_SHIFT)) & DDRC_INIT4_emr2_MASK) +/*! @} */ + +/*! @name INIT5 - SDRAM Initialization Register 5 */ +/*! @{ */ + +#define DDRC_INIT5_max_auto_init_x1024_MASK (0x3FFU) +#define DDRC_INIT5_max_auto_init_x1024_SHIFT (0U) +/*! max_auto_init_x1024 - Maximum duration of the auto initialization, tINIT5. Present only in + * designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: 1024 DFI + * clock cycles. + */ +#define DDRC_INIT5_max_auto_init_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_max_auto_init_x1024_SHIFT)) & DDRC_INIT5_max_auto_init_x1024_MASK) + +#define DDRC_INIT5_dev_zqinit_x32_MASK (0xFF0000U) +#define DDRC_INIT5_dev_zqinit_x32_SHIFT (16U) +/*! dev_zqinit_x32 - ZQ initial calibration, tZQINIT. Present only in designs configured to support + * DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires + * 1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the controller is operating in 1:2 + * frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the + * next integer value. Unit: 32 DFI clock cycles. + */ +#define DDRC_INIT5_dev_zqinit_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_dev_zqinit_x32_SHIFT)) & DDRC_INIT5_dev_zqinit_x32_MASK) +/*! @} */ + +/*! @name INIT6 - SDRAM Initialization Register 6 */ +/*! @{ */ + +#define DDRC_INIT6_mr5_MASK (0xFFFFU) +#define DDRC_INIT6_mr5_SHIFT (0U) +/*! mr5 - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. + */ +#define DDRC_INIT6_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr5_SHIFT)) & DDRC_INIT6_mr5_MASK) + +#define DDRC_INIT6_mr4_MASK (0xFFFF0000U) +#define DDRC_INIT6_mr4_SHIFT (16U) +/*! mr4 - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. + */ +#define DDRC_INIT6_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr4_SHIFT)) & DDRC_INIT6_mr4_MASK) +/*! @} */ + +/*! @name INIT7 - SDRAM Initialization Register 7 */ +/*! @{ */ + +#define DDRC_INIT7_mr6_MASK (0xFFFF0000U) +#define DDRC_INIT7_mr6_SHIFT (16U) +/*! mr6 - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. + */ +#define DDRC_INIT7_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_mr6_SHIFT)) & DDRC_INIT7_mr6_MASK) +/*! @} */ + +/*! @name DIMMCTL - DIMM Control Register */ +/*! @{ */ + +#define DDRC_DIMMCTL_dimm_stagger_cs_en_MASK (0x1U) +#define DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT (0U) +/*! dimm_stagger_cs_en - Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and + * LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. + * Even if this bit is set it does not take care of software driven MR commands (via + * MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate. + * 0b0..Do not stagger accesses + * 0b1..(non-DDR4) Send all commands to even and odd ranks separately. (DDR4) Send MRS commands to each ranks separately. + */ +#define DDRC_DIMMCTL_dimm_stagger_cs_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT)) & DDRC_DIMMCTL_dimm_stagger_cs_en_MASK) + +#define DDRC_DIMMCTL_dimm_addr_mirr_en_MASK (0x2U) +#define DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT (1U) +/*! dimm_addr_mirr_en - Address Mirroring Enable (for multi-rank UDIMM implementations and + * multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address + * mirroring for odd ranks, which means that the following address, bank address and bank group + * bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for + * the DDR4. Setting this bit ensures that, for mode register accesses during the automatic + * initialization routine, these bits are swapped within the DDRC to compensate for this + * UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 + * UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular + * DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of + * software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 + * SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 + * because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1. + * 0b0..Do not implement address mirroring + * 0b1..For odd ranks, implement address mirroring for MRS commands to during initialization and for any + * automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring) + */ +#define DDRC_DIMMCTL_dimm_addr_mirr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT)) & DDRC_DIMMCTL_dimm_addr_mirr_en_MASK) + +#define DDRC_DIMMCTL_dimm_output_inv_en_MASK (0x4U) +#define DDRC_DIMMCTL_dimm_output_inv_en_SHIFT (2U) +/*! dimm_output_inv_en - Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4 + * RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the + * following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, + * A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the + * DDRC during the automatic initialization routine and enabling of a particular DDR4 feature, + * separate A-side and B-side mode register accesses are generated. For B-side mode register + * accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It + * is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect + * on the address of any other memory accesses, or of software-driven mode register accesses. + * 0b0..Do not implement output inversion for B-side DRAMs. + * 0b1..Implement output inversion for B-side DRAMs. + */ +#define DDRC_DIMMCTL_dimm_output_inv_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_output_inv_en_SHIFT)) & DDRC_DIMMCTL_dimm_output_inv_en_MASK) + +#define DDRC_DIMMCTL_mrs_a17_en_MASK (0x8U) +#define DDRC_DIMMCTL_mrs_a17_en_SHIFT (3U) +/*! mrs_a17_en - Enable for A17 bit of MRS command. A17 bit of the mode register address is + * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs + * which do not have A17 are attached and the Output Inversion are enabled, this must be set to + * 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on + * the address of any other memory accesses, or of software-driven mode register accesses. + * 0b0..Disabled + * 0b1..Enabled + */ +#define DDRC_DIMMCTL_mrs_a17_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_a17_en_SHIFT)) & DDRC_DIMMCTL_mrs_a17_en_MASK) + +#define DDRC_DIMMCTL_mrs_bg1_en_MASK (0x10U) +#define DDRC_DIMMCTL_mrs_bg1_en_SHIFT (4U) +/*! mrs_bg1_en - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is + * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs + * which do not have BG1 are attached and both the CA parity and the Output Inversion are + * enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: + * This has no effect on the address of any other memory accesses, or of software-driven mode + * register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0 + * of odd ranks. + * 0b0..Disabled + * 0b1..Enabled + */ +#define DDRC_DIMMCTL_mrs_bg1_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_bg1_en_SHIFT)) & DDRC_DIMMCTL_mrs_bg1_en_MASK) + +#define DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK (0x20U) +#define DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT (5U) +/*! dimm_dis_bg_mirroring - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + * BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs + * with x16 devices. + * 0b0..BG0 and BG1 are swapped if address mirroring is enabled. + * 0b1..BG0 and BG1 are NOT swapped. + */ +#define DDRC_DIMMCTL_dimm_dis_bg_mirroring(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT)) & DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK) + +#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK (0x40U) +#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT (6U) +/*! lrdimm_bcom_cmd_prot - Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM + * commands defined in the Data Buffer specification. When using DDR4 LRDIMM, this bit must be set + * to 1. Otherwise, this bit must be set to 0. + */ +#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT)) & DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK) +/*! @} */ + +/*! @name RANKCTL - Rank Control Register */ +/*! @{ */ + +#define DDRC_RANKCTL_max_rank_rd_MASK (0xFU) +#define DDRC_RANKCTL_max_rank_rd_SHIFT (0U) +/*! max_rank_rd - Only present for multi-rank configurations. Background: Reads to the same rank can + * be performed back-to-back. Reads to different ranks require additional gap dictated by the + * register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus contention as well as to + * give PHY enough time to switch the delay when changing ranks. The DDRC arbitrates for bus + * access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles + * (determined by the value on RANKCTL.diff_rank_rd_gap register) in which only reads from the + * same rank are eligible to be scheduled. This prevents reads from other ranks from having fair + * access to the data bus. This parameter represents the maximum number of reads that can be + * scheduled consecutively to the same rank. After this number is reached, a delay equal to + * RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be + * scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. This + * feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on + * the same rank as long as commands are available for it. Minimum programmable value is 0 (feature + * disabled) and maximum programmable value is 0xF. FOR PERFORMANCE ONLY. + */ +#define DDRC_RANKCTL_max_rank_rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_max_rank_rd_SHIFT)) & DDRC_RANKCTL_max_rank_rd_MASK) + +#define DDRC_RANKCTL_diff_rank_rd_gap_MASK (0xF0U) +#define DDRC_RANKCTL_diff_rank_rd_gap_SHIFT (4U) +/*! diff_rank_rd_gap - Only present for multi-rank configurations. Indicates the number of clocks of + * gap in data responses when performing consecutive reads to different ranks. This is used to + * switch the delays in the PHY to match the rank requirements. This value should consider both + * PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for + * value of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased + * by 1. If read postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT + * requirement: The value programmed in this register takes care of the ODT switch off timing requirement + * when switching ranks during reads. When the controller is operating in 1:1 mode, program this + * to the larger of PHY requirement or ODT requirement. When the controller is operating in 1:2 + * mode, program this to the larger value divided by two and round it up to the next integer. + * Note that, if using DDR4-LRDIMM, refer to TRDRD timing requirements in JEDEC DDR4 Data Buffer + * (DDR4DB01) Specification. + */ +#define DDRC_RANKCTL_diff_rank_rd_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_rd_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_rd_gap_MASK) + +#define DDRC_RANKCTL_diff_rank_wr_gap_MASK (0xF00U) +#define DDRC_RANKCTL_diff_rank_wr_gap_SHIFT (8U) +/*! diff_rank_wr_gap - Only present for multi-rank configurations. Indicates the number of clocks of + * gap in data responses when performing consecutive writes to different ranks. This is used to + * switch the delays in the PHY to match the rank requirements. This value should consider both + * PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for + * value of tphy_wrcsgap) If CRC feature is enabled, should be increased by 1. If write preamble + * is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If write postamble is set to + * 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed in this + * register takes care of the ODT switch off timing requirement when switching ranks during writes. + * For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 When the controller is operating in + * 1:1 mode, program this to the larger of PHY requirement or ODT requirement. When the + * controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to + * the next integer. Note that, if using DDR4-LRDIMM, refer to TWRWR timing requirements in + * JEDEC DDR4 Data Buffer (DDR4DB01) Specification. + */ +#define DDRC_RANKCTL_diff_rank_wr_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_wr_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_wr_gap_MASK) +/*! @} */ + +/*! @name DRAMTMG0 - SDRAM Timing Register 0 */ +/*! @{ */ + +#define DDRC_DRAMTMG0_t_ras_min_MASK (0x3FU) +#define DDRC_DRAMTMG0_t_ras_min_SHIFT (0U) +/*! t_ras_min - tRAS(min): Minimum time between activate and precharge to the same bank. When the + * controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding + * up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, + * program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks + */ +#define DDRC_DRAMTMG0_t_ras_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_t_ras_min_MASK) + +#define DDRC_DRAMTMG0_t_ras_max_MASK (0x7F00U) +#define DDRC_DRAMTMG0_t_ras_max_SHIFT (8U) +/*! t_ras_max - tRAS(max): Maximum time between activate and precharge to same bank. This is the + * maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. + * When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2. + * No rounding up. Unit: Multiples of 1024 clocks. + */ +#define DDRC_DRAMTMG0_t_ras_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_t_ras_max_MASK) + +#define DDRC_DRAMTMG0_t_faw_MASK (0x3F0000U) +#define DDRC_DRAMTMG0_t_faw_SHIFT (16U) +/*! t_faw - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank + * design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller + * is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next + * integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency + * mode. Unit: Clocks + */ +#define DDRC_DRAMTMG0_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_faw_SHIFT)) & DDRC_DRAMTMG0_t_faw_MASK) + +#define DDRC_DRAMTMG0_wr2pre_MASK (0x7F000000U) +#define DDRC_DRAMTMG0_wr2pre_SHIFT (24U) +/*! wr2pre - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + * + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower + * frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in + * the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. + * - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra + * cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2 + * frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller + * is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2 + * and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it + * may be necessary to adjust the value of this parameter to compensate for the extra cycle of + * latency through the LRDIMM. + */ +#define DDRC_DRAMTMG0_wr2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_wr2pre_SHIFT)) & DDRC_DRAMTMG0_wr2pre_MASK) +/*! @} */ + +/*! @name DRAMTMG1 - SDRAM Timing Register 1 */ +/*! @{ */ + +#define DDRC_DRAMTMG1_t_rc_MASK (0x7FU) +#define DDRC_DRAMTMG1_t_rc_SHIFT (0U) +/*! t_rc - tRC: Minimum time between activates to same bank. When the controller is operating in 1:2 + * frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit: + * Clocks. + */ +#define DDRC_DRAMTMG1_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_rc_SHIFT)) & DDRC_DRAMTMG1_t_rc_MASK) + +#define DDRC_DRAMTMG1_rd2pre_MASK (0x3F00U) +#define DDRC_DRAMTMG1_rd2pre_SHIFT (8U) +/*! rd2pre - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, + * 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4) + * or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: + * LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 + * - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously, + * use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode, + * divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T + * mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. + * Unit: Clocks. + */ +#define DDRC_DRAMTMG1_rd2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_rd2pre_SHIFT)) & DDRC_DRAMTMG1_rd2pre_MASK) + +#define DDRC_DRAMTMG1_t_xp_MASK (0x1F0000U) +#define DDRC_DRAMTMG1_t_xp_SHIFT (16U) +/*! t_xp - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be + * programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used, + * set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program + * this to (tXP/2) and round it up to the next integer value. Units: Clocks + */ +#define DDRC_DRAMTMG1_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_xp_SHIFT)) & DDRC_DRAMTMG1_t_xp_MASK) +/*! @} */ + +/*! @name DRAMTMG2 - SDRAM Timing Register 2 */ +/*! @{ */ + +#define DDRC_DRAMTMG2_wr2rd_MASK (0x3FU) +#define DDRC_DRAMTMG2_wr2rd_SHIFT (0U) +/*! wr2rd - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from + * write command to read command for same bank group. In others, minimum time from write command to + * read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and + * global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL + * = burst length. This must match the value programmed in the BL bit of the mode register to + * the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes + * directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. + * When the controller is operating in 1:2 mode, divide the value calculated using the above + * equation by 2, and round it up to next integer. + */ +#define DDRC_DRAMTMG2_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_wr2rd_SHIFT)) & DDRC_DRAMTMG2_wr2rd_MASK) + +#define DDRC_DRAMTMG2_rd2wr_MASK (0x3F00U) +#define DDRC_DRAMTMG2_rd2wr_SHIFT (8U) +/*! rd2wr - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + * + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + * + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + + * RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. + * Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see + * the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: - + * WL = write latency - BL = burst length. This must match the value programmed in the BL bit of + * the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write + * preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to + * LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated + * tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the + * value calculated using the above equation by 2, and round it up to next integer. Note that, + * depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter + * to compensate for the extra cycle of latency through the LRDIMM. + */ +#define DDRC_DRAMTMG2_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_rd2wr_SHIFT)) & DDRC_DRAMTMG2_rd2wr_MASK) + +#define DDRC_DRAMTMG2_read_latency_MASK (0x3F0000U) +#define DDRC_DRAMTMG2_read_latency_SHIFT (16U) +/*! read_latency - Set to RL Time from read command to read data on SDRAM interface. This must be + * set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust + * the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When + * the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the + * above equation by 2, and round it up to next integer. This register field is not required for + * DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in + * DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks + */ +#define DDRC_DRAMTMG2_read_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_read_latency_SHIFT)) & DDRC_DRAMTMG2_read_latency_MASK) + +#define DDRC_DRAMTMG2_write_latency_MASK (0x3F000000U) +#define DDRC_DRAMTMG2_write_latency_SHIFT (24U) +/*! write_latency - Set to WL Time from write command to write data on SDRAM interface. This must be + * set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if + * using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra + * cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio + * mode, divide the value calculated using the above equation by 2, and round it up to next + * integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), + * as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those + * protocols Unit: clocks + */ +#define DDRC_DRAMTMG2_write_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_write_latency_SHIFT)) & DDRC_DRAMTMG2_write_latency_MASK) +/*! @} */ + +/*! @name DRAMTMG3 - SDRAM Timing Register 3 */ +/*! @{ */ + +#define DDRC_DRAMTMG3_t_mod_MASK (0x3FFU) +#define DDRC_DRAMTMG3_t_mod_SHIFT (0U) +/*! t_mod - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and + * following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. + * Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to + * next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using + * RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to + * compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip. + * Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller + * is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if + * controller is operating in 1:2 frequency ratio mode. + */ +#define DDRC_DRAMTMG3_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mod_SHIFT)) & DDRC_DRAMTMG3_t_mod_MASK) + +#define DDRC_DRAMTMG3_t_mrd_MASK (0x3F000U) +#define DDRC_DRAMTMG3_t_mrd_SHIFT (12U) +/*! t_mrd - tMRD: Cycles to wait after a mode register write or read. Depending on the connected + * SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS + * command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is + * operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer + * value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. + */ +#define DDRC_DRAMTMG3_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrd_SHIFT)) & DDRC_DRAMTMG3_t_mrd_MASK) + +#define DDRC_DRAMTMG3_t_mrw_MASK (0x3FF00000U) +#define DDRC_DRAMTMG3_t_mrw_SHIFT (20U) +/*! t_mrw - Time to wait after a mode register write or read (MRW or MRR). Present only in designs + * configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 + * typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, + * this register is used for the time from a MRW/MRR to all other commands. When the controller + * is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and + * round it up to the next integer value. For LDPDR3, this register is used for the time from a + * MRW/MRR to a MRW/MRR. + */ +#define DDRC_DRAMTMG3_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrw_SHIFT)) & DDRC_DRAMTMG3_t_mrw_MASK) +/*! @} */ + +/*! @name DRAMTMG4 - SDRAM Timing Register 4 */ +/*! @{ */ + +#define DDRC_DRAMTMG4_t_rp_MASK (0x1FU) +#define DDRC_DRAMTMG4_t_rp_SHIFT (0U) +/*! t_rp - tRP: Minimum time from precharge to activate of same bank. When the controller is + * operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is + * operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + + * 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set + * to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. + */ +#define DDRC_DRAMTMG4_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rp_SHIFT)) & DDRC_DRAMTMG4_t_rp_MASK) + +#define DDRC_DRAMTMG4_t_rrd_MASK (0xF00U) +#define DDRC_DRAMTMG4_t_rrd_SHIFT (8U) +/*! t_rrd - DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank + * group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller + * is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it + * up to the next integer value. Unit: Clocks. + */ +#define DDRC_DRAMTMG4_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rrd_SHIFT)) & DDRC_DRAMTMG4_t_rrd_MASK) + +#define DDRC_DRAMTMG4_t_ccd_MASK (0xF0000U) +#define DDRC_DRAMTMG4_t_ccd_SHIFT (16U) +/*! t_ccd - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank + * group. Others: tCCD: This is the minimum time between two reads or two writes. When the + * controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it + * up to the next integer value. Unit: clocks. + */ +#define DDRC_DRAMTMG4_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_ccd_SHIFT)) & DDRC_DRAMTMG4_t_ccd_MASK) + +#define DDRC_DRAMTMG4_t_rcd_MASK (0x1F000000U) +#define DDRC_DRAMTMG4_t_rcd_SHIFT (24U) +/*! t_rcd - tRCD - tAL: Minimum time from activate to read or write command to same bank. When the + * controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round + * it up to the next integer value. Minimum value allowed for this register is 1, which implies + * minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio + * mode. Unit: Clocks. + */ +#define DDRC_DRAMTMG4_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rcd_SHIFT)) & DDRC_DRAMTMG4_t_rcd_MASK) +/*! @} */ + +/*! @name DRAMTMG5 - SDRAM Timing Register 5 */ +/*! @{ */ + +#define DDRC_DRAMTMG5_t_cke_MASK (0x1FU) +#define DDRC_DRAMTMG5_t_cke_SHIFT (0U) +/*! t_cke - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - + * LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of + * tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When + * the controller is operating in 1:2 frequency ratio mode, program this to (value described + * above)/2 and round it up to the next integer value. Unit: Clocks. + */ +#define DDRC_DRAMTMG5_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cke_SHIFT)) & DDRC_DRAMTMG5_t_cke_MASK) + +#define DDRC_DRAMTMG5_t_ckesr_MASK (0x3F00U) +#define DDRC_DRAMTMG5_t_ckesr_SHIFT (8U) +/*! t_ckesr - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing + * in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR + * - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity + * latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased + * by PL. When the controller is operating in 1:2 frequency ratio mode, program this to + * recommended value divided by two and round it up to next integer. + */ +#define DDRC_DRAMTMG5_t_ckesr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_t_ckesr_MASK) + +#define DDRC_DRAMTMG5_t_cksre_MASK (0xF0000U) +#define DDRC_DRAMTMG5_t_cksre_SHIFT (16U) +/*! t_cksre - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. + * Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - + * LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+ + * PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should + * be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program + * this to recommended value divided by two and round it up to next integer. + */ +#define DDRC_DRAMTMG5_t_cksre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksre_SHIFT)) & DDRC_DRAMTMG5_t_cksre_MASK) + +#define DDRC_DRAMTMG5_t_cksrx_MASK (0xF000000U) +#define DDRC_DRAMTMG5_t_cksrx_SHIFT (24U) +/*! t_cksrx - This is the time before Self Refresh Exit that CK is maintained as a valid clock + * before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 - + * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the + * controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by + * two and round it up to next integer. + */ +#define DDRC_DRAMTMG5_t_cksrx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_t_cksrx_MASK) +/*! @} */ + +/*! @name DRAMTMG6 - SDRAM Timing Register 6 */ +/*! @{ */ + +#define DDRC_DRAMTMG6_t_ckcsx_MASK (0xFU) +#define DDRC_DRAMTMG6_t_ckcsx_SHIFT (0U) +/*! t_ckcsx - This is the time before Clock Stop Exit that CK is maintained as a valid clock before + * issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop + * Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 + * When the controller is operating in 1:2 frequency ratio mode, program this to recommended value + * divided by two and round it up to next integer. This is only present for designs supporting + * mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_DRAMTMG6_t_ckcsx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_t_ckcsx_MASK) + +#define DDRC_DRAMTMG6_t_ckdpdx_MASK (0xF0000U) +#define DDRC_DRAMTMG6_t_ckdpdx_SHIFT (16U) +/*! t_ckdpdx - This is the time before Deep Power Down Exit that CK is maintained as a valid clock + * before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR: + * 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, + * program this to recommended value divided by two and round it up to next integer. This is only + * present for designs supporting mDDR or LPDDR2 devices. + */ +#define DDRC_DRAMTMG6_t_ckdpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_t_ckdpdx_MASK) + +#define DDRC_DRAMTMG6_t_ckdpde_MASK (0xF000000U) +#define DDRC_DRAMTMG6_t_ckdpde_SHIFT (24U) +/*! t_ckdpde - This is the time after Deep Power Down Entry that CK is maintained as a valid clock. + * Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - + * LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to + * recommended value divided by two and round it up to next integer. This is only present for designs + * supporting mDDR or LPDDR2/LPDDR3 devices. + */ +#define DDRC_DRAMTMG6_t_ckdpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_t_ckdpde_MASK) +/*! @} */ + +/*! @name DRAMTMG7 - SDRAM Timing Register 7 */ +/*! @{ */ + +#define DDRC_DRAMTMG7_t_ckpdx_MASK (0xFU) +#define DDRC_DRAMTMG7_t_ckpdx_SHIFT (0U) +/*! t_ckpdx - This is the time before Power Down Exit that CK is maintained as a valid clock before + * issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 - + * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the + * same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode, + * program this to recommended value divided by two and round it up to next integer. This is only + * present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_DRAMTMG7_t_ckpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_t_ckpdx_MASK) + +#define DDRC_DRAMTMG7_t_ckpde_MASK (0xF00U) +#define DDRC_DRAMTMG7_t_ckpde_SHIFT (8U) +/*! t_ckpde - This is the time after Power Down Entry that CK is maintained as a valid clock. + * Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 + * - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as + * DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this + * to recommended value divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_DRAMTMG7_t_ckpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_t_ckpde_MASK) +/*! @} */ + +/*! @name DRAMTMG8 - SDRAM Timing Register 8 */ +/*! @{ */ + +#define DDRC_DRAMTMG8_t_xs_x32_MASK (0x7FU) +#define DDRC_DRAMTMG8_t_xs_x32_SHIFT (0U) +/*! t_xs_x32 - tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is + * operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round + * up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and + * DDR4 SDRAMs. + */ +#define DDRC_DRAMTMG8_t_xs_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_x32_MASK) + +#define DDRC_DRAMTMG8_t_xs_dll_x32_MASK (0x7F00U) +#define DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT (8U) +/*! t_xs_dll_x32 - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller + * is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and + * round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and + * DDR4 SDRAMs. + */ +#define DDRC_DRAMTMG8_t_xs_dll_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_dll_x32_MASK) + +#define DDRC_DRAMTMG8_t_xs_abort_x32_MASK (0x7F0000U) +#define DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT (16U) +/*! t_xs_abort_x32 - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self + * Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the + * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Ensure this is less than or equal to t_xs_x32. + */ +#define DDRC_DRAMTMG8_t_xs_abort_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_abort_x32_MASK) + +#define DDRC_DRAMTMG8_t_xs_fast_x32_MASK (0x7F000000U) +#define DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT (24U) +/*! t_xs_fast_x32 - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown + * mode). When the controller is operating in 1:2 frequency ratio mode, program this to the + * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: + * This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to + * t_xs_x32. + */ +#define DDRC_DRAMTMG8_t_xs_fast_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_fast_x32_MASK) +/*! @} */ + +/*! @name DRAMTMG9 - SDRAM Timing Register 9 */ +/*! @{ */ + +#define DDRC_DRAMTMG9_wr2rd_s_MASK (0x3FU) +#define DDRC_DRAMTMG9_wr2rd_s_SHIFT (0U) +/*! wr2rd_s - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different + * bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and + * global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where: + * - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value + * programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read + * command delay for different bank group. This comes directly from the SDRAM specification. When + * the controller is operating in 1:2 mode, divide the value calculated using the above equation + * by 2, and round it up to next integer. + */ +#define DDRC_DRAMTMG9_wr2rd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_wr2rd_s_MASK) + +#define DDRC_DRAMTMG9_t_rrd_s_MASK (0xF00U) +#define DDRC_DRAMTMG9_t_rrd_s_SHIFT (8U) +/*! t_rrd_s - tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank + * group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2) + * and round it up to the next integer value. Present only in designs configured to support DDR4. + * Unit: Clocks. + */ +#define DDRC_DRAMTMG9_t_rrd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_t_rrd_s_MASK) + +#define DDRC_DRAMTMG9_t_ccd_s_MASK (0x70000U) +#define DDRC_DRAMTMG9_t_ccd_s_SHIFT (16U) +/*! t_ccd_s - tCCD_S: This is the minimum time between two reads or two writes for different bank + * group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When + * the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round + * it up to the next integer value. Present only in designs configured to support DDR4. Unit: + * clocks. + */ +#define DDRC_DRAMTMG9_t_ccd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_t_ccd_s_MASK) + +#define DDRC_DRAMTMG9_ddr4_wr_preamble_MASK (0x40000000U) +#define DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT (30U) +/*! ddr4_wr_preamble - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 + */ +#define DDRC_DRAMTMG9_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_ddr4_wr_preamble_MASK) +/*! @} */ + +/*! @name DRAMTMG10 - SDRAM Timing Register 10 */ +/*! @{ */ + +#define DDRC_DRAMTMG10_t_gear_hold_MASK (0x3U) +#define DDRC_DRAMTMG10_t_gear_hold_SHIFT (0U) +/*! t_gear_hold - Geardown hold time. Minimum value of this register is 1. Zero is invalid. For + * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in + * 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer + * value. Unit: Clocks + */ +#define DDRC_DRAMTMG10_t_gear_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_t_gear_hold_MASK) + +#define DDRC_DRAMTMG10_t_gear_setup_MASK (0xCU) +#define DDRC_DRAMTMG10_t_gear_setup_SHIFT (2U) +/*! t_gear_setup - Geardown setup time. Minimum value of this register is 1. Zero is invalid. For + * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in + * 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer + * value. Unit: Clocks + */ +#define DDRC_DRAMTMG10_t_gear_setup(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_t_gear_setup_MASK) + +#define DDRC_DRAMTMG10_t_cmd_gear_MASK (0x1F00U) +#define DDRC_DRAMTMG10_t_cmd_gear_SHIFT (8U) +/*! t_cmd_gear - Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is + * defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for + * this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2) + * and round it up to the next integer value. Unit: Clocks + */ +#define DDRC_DRAMTMG10_t_cmd_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_t_cmd_gear_MASK) + +#define DDRC_DRAMTMG10_t_sync_gear_MASK (0x1F0000U) +#define DDRC_DRAMTMG10_t_sync_gear_SHIFT (16U) +/*! t_sync_gear - Indicates the time between MRS command and the sync pulse time. This must be even + * number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK + * tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28 + * When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up + * to the next integer value. Unit: Clocks + */ +#define DDRC_DRAMTMG10_t_sync_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_t_sync_gear_MASK) +/*! @} */ + +/*! @name DRAMTMG11 - SDRAM Timing Register 11 */ +/*! @{ */ + +#define DDRC_DRAMTMG11_t_ckmpe_MASK (0x1FU) +#define DDRC_DRAMTMG11_t_ckmpe_SHIFT (0U) +/*! t_ckmpe - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs + * configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio + * mode, divide the value calculated using the above equation by 2, and round it up to next + * integer. + */ +#define DDRC_DRAMTMG11_t_ckmpe(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_t_ckmpe_MASK) + +#define DDRC_DRAMTMG11_t_mpx_s_MASK (0x300U) +#define DDRC_DRAMTMG11_t_mpx_s_SHIFT (8U) +/*! t_mpx_s - tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2 + * frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: Clocks. + */ +#define DDRC_DRAMTMG11_t_mpx_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_t_mpx_s_MASK) + +#define DDRC_DRAMTMG11_t_mpx_lh_MASK (0x1F0000U) +#define DDRC_DRAMTMG11_t_mpx_lh_SHIFT (16U) +/*! t_mpx_lh - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the + * controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present + * only in designs configured to support DDR4. Unit: clocks. + */ +#define DDRC_DRAMTMG11_t_mpx_lh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_t_mpx_lh_MASK) + +#define DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK (0x7F000000U) +#define DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT (24U) +/*! post_mpsm_gap_x32 - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. + * When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and + * round it up to the next integer value. Present only in designs configured to support DDR4. + * Unit: Multiples of 32 clocks. + */ +#define DDRC_DRAMTMG11_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK) +/*! @} */ + +/*! @name DRAMTMG12 - SDRAM Timing Register 12 */ +/*! @{ */ + +#define DDRC_DRAMTMG12_t_mrd_pda_MASK (0x1FU) +#define DDRC_DRAMTMG12_t_mrd_pda_SHIFT (0U) +/*! t_mrd_pda - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the + * controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up + * to the next integer value. + */ +#define DDRC_DRAMTMG12_t_mrd_pda(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_t_mrd_pda_MASK) + +#define DDRC_DRAMTMG12_t_ckehcmd_MASK (0xF00U) +#define DDRC_DRAMTMG12_t_ckehcmd_SHIFT (8U) +/*! t_ckehcmd - tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is + * operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next + * integer value. + */ +#define DDRC_DRAMTMG12_t_ckehcmd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_t_ckehcmd_MASK) + +#define DDRC_DRAMTMG12_t_cmdcke_MASK (0x30000U) +#define DDRC_DRAMTMG12_t_cmdcke_SHIFT (16U) +/*! t_cmdcke - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE + * or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to + * (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value. + */ +#define DDRC_DRAMTMG12_t_cmdcke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_t_cmdcke_MASK) +/*! @} */ + +/*! @name DRAMTMG13 - SDRAM Timing Register 13 */ +/*! @{ */ + +#define DDRC_DRAMTMG13_t_ppd_MASK (0x7U) +#define DDRC_DRAMTMG13_t_ppd_SHIFT (0U) +/*! t_ppd - LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the + * controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to + * the next integer value. Unit: Clocks. + */ +#define DDRC_DRAMTMG13_t_ppd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ppd_SHIFT)) & DDRC_DRAMTMG13_t_ppd_MASK) + +#define DDRC_DRAMTMG13_t_ccd_mw_MASK (0x3F0000U) +#define DDRC_DRAMTMG13_t_ccd_mw_SHIFT (16U) +/*! t_ccd_mw - LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write + * command for same bank. When the controller is operating in 1:2 frequency ratio mode, program + * this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks. + */ +#define DDRC_DRAMTMG13_t_ccd_mw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_t_ccd_mw_MASK) + +#define DDRC_DRAMTMG13_odtloff_MASK (0x7F000000U) +#define DDRC_DRAMTMG13_odtloff_SHIFT (24U) +/*! odtloff - LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When + * the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round + * it up to the next integer value. Unit: Clocks. + */ +#define DDRC_DRAMTMG13_odtloff(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_odtloff_SHIFT)) & DDRC_DRAMTMG13_odtloff_MASK) +/*! @} */ + +/*! @name DRAMTMG14 - SDRAM Timing Register 14 */ +/*! @{ */ + +#define DDRC_DRAMTMG14_t_xsr_MASK (0xFFFU) +#define DDRC_DRAMTMG14_t_xsr_SHIFT (0U) +/*! t_xsr - tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2 + * frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. + * Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode. + */ +#define DDRC_DRAMTMG14_t_xsr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_t_xsr_SHIFT)) & DDRC_DRAMTMG14_t_xsr_MASK) +/*! @} */ + +/*! @name DRAMTMG15 - SDRAM Timing Register 15 */ +/*! @{ */ + +#define DDRC_DRAMTMG15_t_stab_x32_MASK (0xFFU) +#define DDRC_DRAMTMG15_t_stab_x32_SHIFT (0U) +/*! t_stab_x32 - tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 + * RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the + * clock must be stable for a time specified by tSTAB - in the case of input clock frequency + * change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for + * DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to + * recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock + * cycles. + */ +#define DDRC_DRAMTMG15_t_stab_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_t_stab_x32_MASK) + +#define DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK (0x80000000U) +#define DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT (31U) +/*! en_dfi_lp_t_stab - Enable DFI tSTAB + * 0b0..Disable using tSTAB when exiting DFI LP + * 0b1..Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. + */ +#define DDRC_DRAMTMG15_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK) +/*! @} */ + +/*! @name ZQCTL0 - ZQ Control Register 0 */ +/*! @{ */ + +#define DDRC_ZQCTL0_t_zq_short_nop_MASK (0x3FFU) +#define DDRC_ZQCTL0_t_zq_short_nop_SHIFT (0U) +/*! t_zq_short_nop - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles + * of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. + * When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and + * round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or + * LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_ZQCTL0_t_zq_short_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_short_nop_MASK) + +#define DDRC_ZQCTL0_t_zq_long_nop_MASK (0x7FF0000U) +#define DDRC_ZQCTL0_t_zq_long_nop_SHIFT (16U) +/*! t_zq_long_nop - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI + * clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is + * issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program + * this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to + * tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it + * up to the next integer value. This is only present for designs supporting DDR3/DDR4 or + * LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_ZQCTL0_t_zq_long_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_long_nop_MASK) + +#define DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK (0x10000000U) +#define DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT (28U) +/*! dis_mpsmx_zqcl - Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC + * configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting + * MPSM mode. + * 0b0..Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. + * This is only present for designs supporting DDR4 devices. + * 0b1..Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. + */ +#define DDRC_ZQCTL0_dis_mpsmx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK) + +#define DDRC_ZQCTL0_zq_resistor_shared_MASK (0x20000000U) +#define DDRC_ZQCTL0_zq_resistor_shared_SHIFT (29U) +/*! zq_resistor_shared - ZQ resistor sharing + * 0b0..ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * 0b1..Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are + * sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that + * commands to different ranks do not overlap. + */ +#define DDRC_ZQCTL0_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_zq_resistor_shared_MASK) + +#define DDRC_ZQCTL0_dis_srx_zqcl_MASK (0x40000000U) +#define DDRC_ZQCTL0_dis_srx_zqcl_SHIFT (30U) +/*! dis_srx_zqcl - Disable ZQCL/MPC + * 0b0..Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable + * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting + * DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * 0b1..Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable + * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. + */ +#define DDRC_ZQCTL0_dis_srx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_srx_zqcl_MASK) + +#define DDRC_ZQCTL0_dis_auto_zq_MASK (0x80000000U) +#define DDRC_ZQCTL0_dis_auto_zq_SHIFT (31U) +/*! dis_auto_zq - Disable Auto ZQCS/MPC + * 0b0..Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024. + * 0b1..Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used + * instead to issue ZQ calibration request from APB module. + */ +#define DDRC_ZQCTL0_dis_auto_zq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_dis_auto_zq_MASK) +/*! @} */ + +/*! @name ZQCTL1 - ZQ Control Register 1 */ +/*! @{ */ + +#define DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK (0xFFFFFU) +#define DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT (0U) +/*! t_zq_short_interval_x1024 - Average interval to wait between automatically issuing ZQCS (ZQ + * calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. + * Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 DFI clock cycles. This is only present for designs + * supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_ZQCTL1_t_zq_short_interval_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT)) & DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK) + +#define DDRC_ZQCTL1_t_zq_reset_nop_MASK (0x3FF00000U) +#define DDRC_ZQCTL1_t_zq_reset_nop_SHIFT (20U) +/*! t_zq_reset_nop - tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ + * calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency + * ratio mode, program this to tZQReset/2 and round it up to the next integer value. This is only + * present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_ZQCTL1_t_zq_reset_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_reset_nop_SHIFT)) & DDRC_ZQCTL1_t_zq_reset_nop_MASK) +/*! @} */ + +/*! @name ZQCTL2 - ZQ Control Register 2 */ +/*! @{ */ + +#define DDRC_ZQCTL2_zq_reset_MASK (0x1U) +#define DDRC_ZQCTL2_zq_reset_SHIFT (0U) +/*! zq_reset - Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset + * operation is complete, the DDRC automatically clears this bit. It is recommended NOT to set this + * signal if in Init, Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down + * operating modes. This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_ZQCTL2_zq_reset(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL2_zq_reset_SHIFT)) & DDRC_ZQCTL2_zq_reset_MASK) +/*! @} */ + +/*! @name ZQSTAT - ZQ Status Register */ +/*! @{ */ + +#define DDRC_ZQSTAT_zq_reset_busy_MASK (0x1U) +#define DDRC_ZQSTAT_zq_reset_busy_SHIFT (0U) +/*! zq_reset_busy - SoC core may initiate a ZQ Reset operation only if this signal is low. This + * signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ + * Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended + * not to perform ZQ Reset commands when this signal is high. + * 0b0..Indicates that the SoC core can initiate a ZQ Reset operation + * 0b1..Indicates that ZQ Reset operation is in progress + */ +#define DDRC_ZQSTAT_zq_reset_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQSTAT_zq_reset_busy_SHIFT)) & DDRC_ZQSTAT_zq_reset_busy_MASK) +/*! @} */ + +/*! @name DFITMG0 - DFI Timing Register 0 */ +/*! @{ */ + +#define DDRC_DFITMG0_dfi_tphy_wrlat_MASK (0x3FU) +#define DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT (0U) +/*! dfi_tphy_wrlat - Write latency Number of clocks from the write command to write data enable + * (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY + * specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be + * necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for + * the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY + * clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr. + */ +#define DDRC_DFITMG0_dfi_tphy_wrlat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrlat_MASK) + +#define DDRC_DFITMG0_dfi_tphy_wrdata_MASK (0x3F00U) +#define DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT (8U) +/*! dfi_tphy_wrdata - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to + * when the associated write data is driven on the dfi_wrdata signal. This corresponds to the + * DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max + * supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on + * DFITMG0.dfi_wrdata_use_sdr. + */ +#define DDRC_DFITMG0_dfi_tphy_wrdata(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrdata_MASK) + +#define DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK (0x8000U) +#define DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT (15U) +/*! dfi_wrdata_use_sdr - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using + * HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat + * is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in + * DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of + * HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification + * for correct value. + */ +#define DDRC_DFITMG0_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK) + +#define DDRC_DFITMG0_dfi_t_rddata_en_MASK (0x7F0000U) +#define DDRC_DFITMG0_dfi_t_rddata_en_SHIFT (16U) +/*! dfi_t_rddata_en - Time from the assertion of a read command on the DFI interface to the + * assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds + * to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it + * may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to + * compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or + * DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr. + */ +#define DDRC_DFITMG0_dfi_t_rddata_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_dfi_t_rddata_en_MASK) + +#define DDRC_DFITMG0_dfi_rddata_use_sdr_MASK (0x800000U) +#define DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT (23U) +/*! dfi_rddata_use_sdr - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated + * using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in + * DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI + * clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct + * value. + */ +#define DDRC_DFITMG0_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_rddata_use_sdr_MASK) + +#define DDRC_DFITMG0_dfi_t_ctrl_delay_MASK (0x1F000000U) +#define DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT (24U) +/*! dfi_t_ctrl_delay - Specifies the number of DFI clock cycles after an assertion or de-assertion + * of the DFI control signals that the control signals at the PHY-DRAM interface reflect the + * assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing + * parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it + * is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms + * of DFI clock. + */ +#define DDRC_DFITMG0_dfi_t_ctrl_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_dfi_t_ctrl_delay_MASK) +/*! @} */ + +/*! @name DFITMG1 - DFI Timing Register 1 */ +/*! @{ */ + +#define DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK (0x1FU) +#define DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT (0U) +/*! dfi_t_dram_clk_enable - Specifies the number of DFI clock cycles from the de-assertion of the + * dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the + * DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not + * phase aligned, this timing parameter should be rounded up to the next integer value. + */ +#define DDRC_DFITMG1_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK) + +#define DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK (0x1F00U) +#define DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT (8U) +/*! dfi_t_dram_clk_disable - Specifies the number of DFI clock cycles from the assertion of the + * dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM + * boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, + * this timing parameter should be rounded up to the next integer value. + */ +#define DDRC_DFITMG1_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK) + +#define DDRC_DFITMG1_dfi_t_wrdata_delay_MASK (0x1F0000U) +#define DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT (16U) +/*! dfi_t_wrdata_delay - Specifies the number of DFI clock cycles between when the dfi_wrdata_en + * signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. + * This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for + * correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI + * 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be + * programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 + * and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: + * Clocks + */ +#define DDRC_DFITMG1_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_dfi_t_wrdata_delay_MASK) + +#define DDRC_DFITMG1_dfi_t_parin_lat_MASK (0x3000000U) +#define DDRC_DFITMG1_dfi_t_parin_lat_SHIFT (24U) +/*! dfi_t_parin_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. + */ +#define DDRC_DFITMG1_dfi_t_parin_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_parin_lat_MASK) + +#define DDRC_DFITMG1_dfi_t_cmd_lat_MASK (0xF0000000U) +#define DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT (28U) +/*! dfi_t_cmd_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used for CAL mode, should be + * set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY + * can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 + */ +#define DDRC_DFITMG1_dfi_t_cmd_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_cmd_lat_MASK) +/*! @} */ + +/*! @name DFILPCFG0 - DFI Low Power Configuration Register 0 */ +/*! @{ */ + +#define DDRC_DFILPCFG0_dfi_lp_en_pd_MASK (0x1U) +#define DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT (0U) +/*! dfi_lp_en_pd - Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled + */ +#define DDRC_DFILPCFG0_dfi_lp_en_pd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_pd_MASK) + +#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK (0xF0U) +#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT (4U) +/*! dfi_lp_wakeup_pd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down + * mode is entered. Determines the DFI's tlp_wakeup time: + * 0b0000..16 cycles + * 0b0001..32 cycles + * 0b0010..64 cycles + * 0b0011..128 cycles + * 0b0100..256 cycles + * 0b0101..512 cycles + * 0b0110..1024 cycles + * 0b0111..2048 cycles + * 0b1000..4096 cycles + * 0b1001..8192 cycles + * 0b1010..16384 cycles + * 0b1011..32768 cycles + * 0b1100..65536 cycles + * 0b1101..131072 cycles + * 0b1110..262144 cycles + * 0b1111..Unlimited cycles + */ +#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK) + +#define DDRC_DFILPCFG0_dfi_lp_en_sr_MASK (0x100U) +#define DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT (8U) +/*! dfi_lp_en_sr - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled + * 0b0..Disabled + * 0b1..Enabled + */ +#define DDRC_DFILPCFG0_dfi_lp_en_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_sr_MASK) + +#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK (0xF000U) +#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT (12U) +/*! dfi_lp_wakeup_sr - Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh + * mode is entered. Determines the DFI's tlp_wakeup time: + * 0b0000..16 cycles + * 0b0001..32 cycles + * 0b0010..64 cycles + * 0b0011..128 cycles + * 0b0100..256 cycles + * 0b0101..512 cycles + * 0b0110..1024 cycles + * 0b0111..2048 cycles + * 0b1000..4096 cycles + * 0b1001..8192 cycles + * 0b1010..16384 cycles + * 0b1011..32768 cycles + * 0b1100..65536 cycles + * 0b1101..131072 cycles + * 0b1110..262144 cycles + * 0b1111..Unlimited cycles + */ +#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK) + +#define DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK (0x10000U) +#define DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT (16U) +/*! dfi_lp_en_dpd - Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - + * 0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3 + * devices. + */ +#define DDRC_DFILPCFG0_dfi_lp_en_dpd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK) + +#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK (0xF00000U) +#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT (20U) +/*! dfi_lp_wakeup_dpd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power + * Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs + * supporting mDDR or LPDDR2/LPDDR3 devices. + * 0b0000..16 cycles + * 0b0001..32 cycles + * 0b0010..64 cycles + * 0b0011..128 cycles + * 0b0100..256 cycles + * 0b0101..512 cycles + * 0b0110..1024 cycles + * 0b0111..2048 cycles + * 0b1000..4096 cycles + * 0b1001..8192 cycles + * 0b1010..16384 cycles + * 0b1011..32768 cycles + * 0b1100..65536 cycles + * 0b1101..131072 cycles + * 0b1110..262144 cycles + * 0b1111..Unlimited cycles + */ +#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK) + +#define DDRC_DFILPCFG0_dfi_tlp_resp_MASK (0x1F000000U) +#define DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT (24U) +/*! dfi_tlp_resp - Setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both + * Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 + * specification onwards, recommends using a fixed value of 7 always. + */ +#define DDRC_DFILPCFG0_dfi_tlp_resp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT)) & DDRC_DFILPCFG0_dfi_tlp_resp_MASK) +/*! @} */ + +/*! @name DFILPCFG1 - DFI Low Power Configuration Register 1 */ +/*! @{ */ + +#define DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK (0x1U) +#define DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT (0U) +/*! dfi_lp_en_mpsm - Enables DFI Low Power interface handshaking during Maximum Power Saving Mode + * Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4 + * devices. + */ +#define DDRC_DFILPCFG1_dfi_lp_en_mpsm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK) + +#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK (0xF0U) +#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT (4U) +/*! dfi_lp_wakeup_mpsm - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum + * Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: + * 0b0000..16 cycles + * 0b0001..32 cycles + * 0b0010..64 cycles + * 0b0011..128 cycles + * 0b0100..256 cycles + * 0b0101..512 cycles + * 0b0110..1024 cycles + * 0b0111..2048 cycles + * 0b1000..4096 cycles + * 0b1001..8192 cycles + * 0b1010..16384 cycles + * 0b1011..32768 cycles + * 0b1100..65536 cycles + * 0b1101..131072 cycles + * 0b1110..262144 cycles + * 0b1111..Unlimited cycles + */ +#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK) +/*! @} */ + +/*! @name DFIUPD0 - DFI Update Register 0 */ +/*! @{ */ + +#define DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK (0x3FFU) +#define DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT (0U) +/*! dfi_t_ctrlup_min - Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req + * signal must be asserted. The DDRC expects the PHY to respond within this time. If the PHY does + * not respond, the DDRC will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest + * value to assign to this variable is 0x3. + */ +#define DDRC_DFIUPD0_dfi_t_ctrlup_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK) + +#define DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK (0x3FF0000U) +#define DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT (16U) +/*! dfi_t_ctrlup_max - Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req + * signal can assert. Lowest value to assign to this variable is 0x40. + */ +#define DDRC_DFIUPD0_dfi_t_ctrlup_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK) + +#define DDRC_DFIUPD0_ctrlupd_pre_srx_MASK (0x20000000U) +#define DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT (29U) +/*! ctrlupd_pre_srx - Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1 + * : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact, + * because no dfi_ctrlupd_req will be issued when SRX. + * 0b0..send ctrlupd after SRX + * 0b1..send ctrlupd before SRX + */ +#define DDRC_DFIUPD0_ctrlupd_pre_srx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT)) & DDRC_DFIUPD0_ctrlupd_pre_srx_MASK) + +#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK (0x40000000U) +#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT (30U) +/*! dis_auto_ctrlupd_srx - Auto ctrlupd request generation + * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit. + * 0b0..DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx. + */ +#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK) + +#define DDRC_DFIUPD0_dis_auto_ctrlupd_MASK (0x80000000U) +#define DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT (31U) +/*! dis_auto_ctrlupd - automatic dfi_ctrlupd_req generation by the DDRC + * 0b0..DDRC issues dfi_ctrlupd_req periodically. + * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req + * signal using register reg_ddrc_ctrlupd. + */ +#define DDRC_DFIUPD0_dis_auto_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_MASK) +/*! @} */ + +/*! @name DFIUPD1 - DFI Update Register 1 */ +/*! @{ */ + +#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK (0xFFU) +#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT (0U) +/*! dfi_t_ctrlupd_interval_max_x1024 - This is the maximum amount of time between DDRC initiated DFI + * update requests. This timer resets with each update request; when the timer expires + * dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this + * idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used + * to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain + * calibration over PVT, but frequent updates may impact performance. Minimum allowed value for + * this field is 1. Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be + * greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 DFI clock cycles + */ +#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT)) & DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK) + +#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK (0xFF0000U) +#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT (16U) +/*! dfi_t_ctrlupd_interval_min_x1024 - This is the minimum amount of time between DDRC initiated DFI + * update requests (which is executed whenever the DDRC is idle). Set this number higher to + * reduce the frequency of update requests, which can have a small impact on the latency of the first + * read request when the DDRC is idle. Minimum allowed value for this field is 1. Unit: 1024 DFI + * clock cycles + */ +#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT)) & DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK) +/*! @} */ + +/*! @name DFIUPD2 - DFI Update Register 2 */ +/*! @{ */ + +#define DDRC_DFIUPD2_dfi_phyupd_en_MASK (0x80000000U) +#define DDRC_DFIUPD2_dfi_phyupd_en_SHIFT (31U) +/*! dfi_phyupd_en - Enables the support for acknowledging PHY-initiated updates: + * 0b0..Disabled + * 0b1..Enabled + */ +#define DDRC_DFIUPD2_dfi_phyupd_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD2_dfi_phyupd_en_SHIFT)) & DDRC_DFIUPD2_dfi_phyupd_en_MASK) +/*! @} */ + +/*! @name DFIMISC - DFI Miscellaneous Control Register */ +/*! @{ */ + +#define DDRC_DFIMISC_dfi_init_complete_en_MASK (0x1U) +#define DDRC_DFIMISC_dfi_init_complete_en_SHIFT (0U) +/*! dfi_init_complete_en - PHY initialization complete enable signal. When asserted the + * dfi_init_complete signal can be used to trigger SDRAM initialisation + */ +#define DDRC_DFIMISC_dfi_init_complete_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_complete_en_SHIFT)) & DDRC_DFIMISC_dfi_init_complete_en_MASK) + +#define DDRC_DFIMISC_phy_dbi_mode_MASK (0x2U) +#define DDRC_DFIMISC_phy_dbi_mode_SHIFT (1U) +/*! phy_dbi_mode - DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4. + * 0b0..DDRC implements DBI functionality. + * 0b1..PHY implements DBI functionality. + */ +#define DDRC_DFIMISC_phy_dbi_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_phy_dbi_mode_SHIFT)) & DDRC_DFIMISC_phy_dbi_mode_MASK) + +#define DDRC_DFIMISC_dfi_data_cs_polarity_MASK (0x4U) +#define DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT (2U) +/*! dfi_data_cs_polarity - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. + * 0b0..Signals are active low + * 0b1..Signals are active high + */ +#define DDRC_DFIMISC_dfi_data_cs_polarity(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT)) & DDRC_DFIMISC_dfi_data_cs_polarity_MASK) + +#define DDRC_DFIMISC_ctl_idle_en_MASK (0x10U) +#define DDRC_DFIMISC_ctl_idle_en_SHIFT (4U) +/*! ctl_idle_en - Enables support of ctl_idle signal, which is non-DFI related pin specific to + * certain PHYs. See signal description of ctl_idle signal for further details of ctl_idle + * functionality. + */ +#define DDRC_DFIMISC_ctl_idle_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_ctl_idle_en_SHIFT)) & DDRC_DFIMISC_ctl_idle_en_MASK) + +#define DDRC_DFIMISC_dfi_init_start_MASK (0x20U) +#define DDRC_DFIMISC_dfi_init_start_SHIFT (5U) +/*! dfi_init_start - PHY init start request signal.When asserted it triggers the PHY init start request + */ +#define DDRC_DFIMISC_dfi_init_start(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_start_SHIFT)) & DDRC_DFIMISC_dfi_init_start_MASK) + +#define DDRC_DFIMISC_dfi_frequency_MASK (0x1F00U) +#define DDRC_DFIMISC_dfi_frequency_SHIFT (8U) +/*! dfi_frequency - Indicates the operating frequency of the system. The number of supported + * frequencies and the mapping of signal values to clock frequencies are defined by the PHY. + */ +#define DDRC_DFIMISC_dfi_frequency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_frequency_SHIFT)) & DDRC_DFIMISC_dfi_frequency_MASK) +/*! @} */ + +/*! @name DFITMG2 - DFI Timing Register 2 */ +/*! @{ */ + +#define DDRC_DFITMG2_dfi_tphy_wrcslat_MASK (0x3FU) +#define DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT (0U) +/*! dfi_tphy_wrcslat - Number of DFI PHY clock cycles between when a write command is sent on the + * DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds + * to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. + */ +#define DDRC_DFITMG2_dfi_tphy_wrcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_wrcslat_MASK) + +#define DDRC_DFITMG2_dfi_tphy_rdcslat_MASK (0x7F00U) +#define DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT (8U) +/*! dfi_tphy_rdcslat - Number of DFI PHY clock cycles between when a read command is sent on the DFI + * control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds + * to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. + */ +#define DDRC_DFITMG2_dfi_tphy_rdcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_rdcslat_MASK) +/*! @} */ + +/*! @name DFITMG3 - DFI Timing Register 3 */ +/*! @{ */ + +#define DDRC_DFITMG3_dfi_t_geardown_delay_MASK (0x1FU) +#define DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT (0U) +/*! dfi_t_geardown_delay - The delay from dfi_geardown_en assertion to the time of the PHY being + * ready to receive commands. Refer to PHY specification for correct value. When the controller is + * operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to + * the next integer value. Unit: Clocks + */ +#define DDRC_DFITMG3_dfi_t_geardown_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT)) & DDRC_DFITMG3_dfi_t_geardown_delay_MASK) +/*! @} */ + +/*! @name DFISTAT - DFI Status Register */ +/*! @{ */ + +#define DDRC_DFISTAT_dfi_init_complete_MASK (0x1U) +#define DDRC_DFISTAT_dfi_init_complete_SHIFT (0U) +/*! dfi_init_complete - The status flag register which announces when the DFI initialization has + * been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete + * flag is polled to know when the initialization is done. + */ +#define DDRC_DFISTAT_dfi_init_complete(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_init_complete_SHIFT)) & DDRC_DFISTAT_dfi_init_complete_MASK) + +#define DDRC_DFISTAT_dfi_lp_ack_MASK (0x2U) +#define DDRC_DFISTAT_dfi_lp_ack_SHIFT (1U) +/*! dfi_lp_ack - Stores the value of the dfi_lp_ack input to the controller. + */ +#define DDRC_DFISTAT_dfi_lp_ack(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_lp_ack_SHIFT)) & DDRC_DFISTAT_dfi_lp_ack_MASK) +/*! @} */ + +/*! @name DBICTL - DM/DBI Control Register */ +/*! @{ */ + +#define DDRC_DBICTL_dm_en_MASK (0x1U) +#define DDRC_DBICTL_dm_en_SHIFT (0U) +/*! dm_en - DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode + * register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal + * must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity + * from this signal + * 0b0..DM is disabled + * 0b1..DM is enabled + */ +#define DDRC_DBICTL_dm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_dm_en_SHIFT)) & DDRC_DBICTL_dm_en_MASK) + +#define DDRC_DBICTL_wr_dbi_en_MASK (0x2U) +#define DDRC_DBICTL_wr_dbi_en_SHIFT (1U) +/*! wr_dbi_en - This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11. + * When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7] + * 0b0..Write DBI is disabled + * 0b1..Write DBI is enabled. + */ +#define DDRC_DBICTL_wr_dbi_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_wr_dbi_en_SHIFT)) & DDRC_DBICTL_wr_dbi_en_MASK) + +#define DDRC_DBICTL_rd_dbi_en_MASK (0x4U) +#define DDRC_DBICTL_rd_dbi_en_SHIFT (2U) +/*! rd_dbi_en - Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is + * enabled. This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A12. When + * x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6] + */ +#define DDRC_DBICTL_rd_dbi_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_rd_dbi_en_SHIFT)) & DDRC_DBICTL_rd_dbi_en_MASK) +/*! @} */ + +/*! @name ADDRMAP0 - Address Map Register 0 */ +/*! @{ */ + +#define DDRC_ADDRMAP0_addrmap_cs_bit0_MASK (0x1FU) +#define DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT (0U) +/*! addrmap_cs_bit0 - Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 28, + * and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base + * to the value of this field. If set to 31, rank address bit 0 is set to 0. + */ +#define DDRC_ADDRMAP0_addrmap_cs_bit0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT)) & DDRC_ADDRMAP0_addrmap_cs_bit0_MASK) +/*! @} */ + +/*! @name ADDRMAP1 - Address Map Register 1 */ +/*! @{ */ + +#define DDRC_ADDRMAP1_addrmap_bank_b0_MASK (0x1FU) +#define DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT (0U) +/*! addrmap_bank_b0 - Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 31 + * Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined + * by adding the internal base to the value of this field. + */ +#define DDRC_ADDRMAP1_addrmap_bank_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b0_MASK) + +#define DDRC_ADDRMAP1_addrmap_bank_b1_MASK (0x1F00U) +#define DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT (8U) +/*! addrmap_bank_b1 - Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 31 + * Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined + * by adding the internal base to the value of this field. + */ +#define DDRC_ADDRMAP1_addrmap_bank_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b1_MASK) + +#define DDRC_ADDRMAP1_addrmap_bank_b2_MASK (0x1F0000U) +#define DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT (16U) +/*! addrmap_bank_b2 - Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 30 + * and 31 Internal Base: 4 The selected HIF address bit is determined by adding the internal base + * to the value of this field. If set to 31, bank address bit 2 is set to 0. + */ +#define DDRC_ADDRMAP1_addrmap_bank_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b2_MASK) +/*! @} */ + +/*! @name ADDRMAP2 - Address Map Register 2 */ +/*! @{ */ + +#define DDRC_ADDRMAP2_addrmap_col_b2_MASK (0xFU) +#define DDRC_ADDRMAP2_addrmap_col_b2_SHIFT (0U) +/*! addrmap_col_b2 - - Full bus width mode: Selects the HIF address bit used as column address bit + * 2. - Half bus width mode: Selects the HIF address bit used as column address bit 3. - Quarter + * bus width mode: Selects the HIF address bit used as column address bit 4. Valid Range: 0 to 7 + * Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=8, it is required to + * program this to 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and - + * PCCFG.bl_exp_mode==1 and either - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 or - In LPDDR4 and + * ADDRMAP1.addrmap_bank_b0==0 If DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to + * 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and - PCCFG.bl_exp_mode==1 + * and - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 Otherwise, if MEMC_BURST_LENGTH=8 and Full Bus + * Width (MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to + * column address bit 2. If MEMC_BURST_LENGTH=16 and Full Bus Width (MSTR.data_bus_width==00), it + * is recommended to program this to 0 so that HIF[2] maps to column address bit 2. If + * MEMC_BURST_LENGTH=16 and Half Bus Width (MSTR.data_bus_width==01), it is recommended to program this to 0 + * so that HIF[2] maps to column address bit 3. + */ +#define DDRC_ADDRMAP2_addrmap_col_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b2_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b2_MASK) + +#define DDRC_ADDRMAP2_addrmap_col_b3_MASK (0xF00U) +#define DDRC_ADDRMAP2_addrmap_col_b3_SHIFT (8U) +/*! addrmap_col_b3 - - Full bus width mode: Selects the HIF address bit used as column address bit + * 3. - Half bus width mode: Selects the HIF address bit used as column address bit 4. - Quarter + * bus width mode: Selects the HIF address bit used as column address bit 5. Valid Range: 0 to 7 + * Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if DDRC_INCL_ARB=1, MEMC_BURST_LENGTH=16, Full bus width + * (MSTR.data_bus_width=00) and BL16 (MSTR.burst_rdwr=1000), it is recommended to program this to 0. + */ +#define DDRC_ADDRMAP2_addrmap_col_b3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b3_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b3_MASK) + +#define DDRC_ADDRMAP2_addrmap_col_b4_MASK (0xF0000U) +#define DDRC_ADDRMAP2_addrmap_col_b4_SHIFT (16U) +/*! addrmap_col_b4 - - Full bus width mode: Selects the HIF address bit used as column address bit + * 4. - Half bus width mode: Selects the HIF address bit used as column address bit 5. - Quarter + * bus width mode: Selects the HIF address bit used as column address bit 6. Valid Range: 0 to 7, + * and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base + * to the value of this field. If set to 15, this column address bit is set to 0. + */ +#define DDRC_ADDRMAP2_addrmap_col_b4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b4_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b4_MASK) + +#define DDRC_ADDRMAP2_addrmap_col_b5_MASK (0xF000000U) +#define DDRC_ADDRMAP2_addrmap_col_b5_SHIFT (24U) +/*! addrmap_col_b5 - - Full bus width mode: Selects the HIF address bit used as column address bit + * 5. - Half bus width mode: Selects the HIF address bit used as column address bit 6. - Quarter + * bus width mode: Selects the HIF address bit used as column address bit 7 . Valid Range: 0 to 7, + * and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal + * base to the value of this field. If set to 15, this column address bit is set to 0. + */ +#define DDRC_ADDRMAP2_addrmap_col_b5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b5_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b5_MASK) +/*! @} */ + +/*! @name ADDRMAP3 - Address Map Register 3 */ +/*! @{ */ + +#define DDRC_ADDRMAP3_addrmap_col_b6_MASK (0xFU) +#define DDRC_ADDRMAP3_addrmap_col_b6_SHIFT (0U) +/*! addrmap_col_b6 - - Full bus width mode: Selects the HIF address bit used as column address bit + * 6. - Half bus width mode: Selects the HIF address bit used as column address bit 7. - Quarter + * bus width mode: Selects the HIF address bit used as column address bit 8. Valid Range: 0 to 7, + * and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base + * to the value of this field. If set to 15, this column address bit is set to 0. + */ +#define DDRC_ADDRMAP3_addrmap_col_b6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b6_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b6_MASK) + +#define DDRC_ADDRMAP3_addrmap_col_b7_MASK (0xF00U) +#define DDRC_ADDRMAP3_addrmap_col_b7_SHIFT (8U) +/*! addrmap_col_b7 - - Full bus width mode: Selects the HIF address bit used as column address bit + * 7. - Half bus width mode: Selects the HIF address bit used as column address bit 8. - Quarter + * bus width mode: Selects the HIF address bit used as column address bit 9. Valid Range: 0 to 7, + * and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base + * to the value of this field. If set to 15, this column address bit is set to 0. + */ +#define DDRC_ADDRMAP3_addrmap_col_b7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b7_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b7_MASK) + +#define DDRC_ADDRMAP3_addrmap_col_b8_MASK (0xF0000U) +#define DDRC_ADDRMAP3_addrmap_col_b8_SHIFT (16U) +/*! addrmap_col_b8 - - Full bus width mode: Selects the HIF address bit used as column address bit + * 8. - Half bus width mode: Selects the HIF address bit used as column address bit 9. - Quarter + * bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 + * mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 15, this column address bit + * is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for + * indicating auto-precharge, and hence no source address bit can be mapped to column address + * bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence + * column bit 10 is used. + */ +#define DDRC_ADDRMAP3_addrmap_col_b8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b8_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b8_MASK) + +#define DDRC_ADDRMAP3_addrmap_col_b9_MASK (0xF000000U) +#define DDRC_ADDRMAP3_addrmap_col_b9_SHIFT (24U) +/*! addrmap_col_b9 - - Full bus width mode: Selects the HIF address bit used as column address bit + * 9. - Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in + * LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as column address + * bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + * HIF address bit is determined by adding the internal base to the value of this field. If set to + * 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column + * address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be + * mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + * auto-precharge in the CA bus and hence column bit 10 is used. + */ +#define DDRC_ADDRMAP3_addrmap_col_b9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b9_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b9_MASK) +/*! @} */ + +/*! @name ADDRMAP4 - Address Map Register 4 */ +/*! @{ */ + +#define DDRC_ADDRMAP4_addrmap_col_b10_MASK (0xFU) +#define DDRC_ADDRMAP4_addrmap_col_b10_SHIFT (0U) +/*! addrmap_col_b10 - - Full bus width mode: Selects the HIF address bit used as column address bit + * 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the HIF address bit used as + * column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. To make it + * unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + * address bit is determined by adding the internal base to the value of this field. If set to + * 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column + * address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be + * mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge + * in the CA bus and hence column bit 10 is used. + */ +#define DDRC_ADDRMAP4_addrmap_col_b10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b10_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b10_MASK) + +#define DDRC_ADDRMAP4_addrmap_col_b11_MASK (0xF00U) +#define DDRC_ADDRMAP4_addrmap_col_b11_SHIFT (8U) +/*! addrmap_col_b11 - - Full bus width mode: Selects the HIF address bit used as column address bit + * 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To make it unused, this should + * be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must be tied to + * 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by + * adding the internal base to the value of this field. If set to 15, this column address bit is + * set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for + * indicating auto-precharge, and hence no source address bit can be mapped to column address bit + * 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column + * bit 10 is used. + */ +#define DDRC_ADDRMAP4_addrmap_col_b11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b11_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b11_MASK) +/*! @} */ + +/*! @name ADDRMAP5 - Address Map Register 5 */ +/*! @{ */ + +#define DDRC_ADDRMAP5_addrmap_row_b0_MASK (0xFU) +#define DDRC_ADDRMAP5_addrmap_row_b0_SHIFT (0U) +/*! addrmap_row_b0 - Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 + * Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by + * adding the internal base to the value of this field. + */ +#define DDRC_ADDRMAP5_addrmap_row_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b0_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b0_MASK) + +#define DDRC_ADDRMAP5_addrmap_row_b1_MASK (0xF00U) +#define DDRC_ADDRMAP5_addrmap_row_b1_SHIFT (8U) +/*! addrmap_row_b1 - Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 + * Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by + * adding the internal base to the value of this field. + */ +#define DDRC_ADDRMAP5_addrmap_row_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b1_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b1_MASK) + +#define DDRC_ADDRMAP5_addrmap_row_b2_10_MASK (0xF0000U) +#define DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT (16U) +/*! addrmap_row_b2_10 - Selects the HIF address bits used as row address bits 2 to 10. Valid Range: + * 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for + * row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF address bit + * for each of the row address bits is determined by adding the internal base to the value of this + * field. When value 15 is used the values of row address bits 2 to 10 are defined by registers + * ADDRMAP9, ADDRMAP10, ADDRMAP11. + */ +#define DDRC_ADDRMAP5_addrmap_row_b2_10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b2_10_MASK) + +#define DDRC_ADDRMAP5_addrmap_row_b11_MASK (0xF000000U) +#define DDRC_ADDRMAP5_addrmap_row_b11_SHIFT (24U) +/*! addrmap_row_b11 - Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, + * and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal + * base to the value of this field. If set to 15, row address bit 11 is set to 0. + */ +#define DDRC_ADDRMAP5_addrmap_row_b11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b11_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b11_MASK) +/*! @} */ + +/*! @name ADDRMAP6 - Address Map Register 6 */ +/*! @{ */ + +#define DDRC_ADDRMAP6_addrmap_row_b12_MASK (0xFU) +#define DDRC_ADDRMAP6_addrmap_row_b12_SHIFT (0U) +/*! addrmap_row_b12 - Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, + * and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal + * base to the value of this field. If set to 15, row address bit 12 is set to 0. + */ +#define DDRC_ADDRMAP6_addrmap_row_b12(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b12_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b12_MASK) + +#define DDRC_ADDRMAP6_addrmap_row_b13_MASK (0xF00U) +#define DDRC_ADDRMAP6_addrmap_row_b13_SHIFT (8U) +/*! addrmap_row_b13 - Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, + * and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal + * base to the value of this field. If set to 15, row address bit 13 is set to 0. + */ +#define DDRC_ADDRMAP6_addrmap_row_b13(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b13_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b13_MASK) + +#define DDRC_ADDRMAP6_addrmap_row_b14_MASK (0xF0000U) +#define DDRC_ADDRMAP6_addrmap_row_b14_SHIFT (16U) +/*! addrmap_row_b14 - Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, + * and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal + * base to the value of this field. If set to 15, row address bit 14 is set to 0. + */ +#define DDRC_ADDRMAP6_addrmap_row_b14(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b14_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b14_MASK) + +#define DDRC_ADDRMAP6_addrmap_row_b15_MASK (0xF000000U) +#define DDRC_ADDRMAP6_addrmap_row_b15_SHIFT (24U) +/*! addrmap_row_b15 - Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, + * and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal + * base to the value of this field. If set to 15, row address bit 15 is set to 0. + */ +#define DDRC_ADDRMAP6_addrmap_row_b15(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b15_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b15_MASK) + +#define DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK (0x80000000U) +#define DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT (31U) +/*! lpddr3_6gb_12gb - Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - + * LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as + * invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present only in designs + * configured to support LPDDR3. + */ +#define DDRC_ADDRMAP6_lpddr3_6gb_12gb(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT)) & DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK) +/*! @} */ + +/*! @name ADDRMAP7 - Address Map Register 7 */ +/*! @{ */ + +#define DDRC_ADDRMAP7_addrmap_row_b16_MASK (0xFU) +#define DDRC_ADDRMAP7_addrmap_row_b16_SHIFT (0U) +/*! addrmap_row_b16 - Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, + * and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal + * base to the value of this field. If set to 15, row address bit 16 is set to 0. + */ +#define DDRC_ADDRMAP7_addrmap_row_b16(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b16_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b16_MASK) + +#define DDRC_ADDRMAP7_addrmap_row_b17_MASK (0xF00U) +#define DDRC_ADDRMAP7_addrmap_row_b17_SHIFT (8U) +/*! addrmap_row_b17 - Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11, + * and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal + * base to the value of this field. If set to 15, row address bit 17 is set to 0. + */ +#define DDRC_ADDRMAP7_addrmap_row_b17(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b17_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b17_MASK) +/*! @} */ + +/*! @name ADDRMAP8 - Address Map Register 8 */ +/*! @{ */ + +#define DDRC_ADDRMAP8_addrmap_bg_b0_MASK (0x1FU) +#define DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT (0U) +/*! addrmap_bg_b0 - Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to + * 31 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is + * determined by adding the internal base to the value of this field. + */ +#define DDRC_ADDRMAP8_addrmap_bg_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b0_MASK) + +#define DDRC_ADDRMAP8_addrmap_bg_b1_MASK (0x3F00U) +#define DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT (8U) +/*! addrmap_bg_b1 - Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to + * 31, and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address + * bits is determined by adding the internal base to the value of this field. If set to 63, bank + * group address bit 1 is set to 0. + */ +#define DDRC_ADDRMAP8_addrmap_bg_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b1_MASK) +/*! @} */ + +/*! @name ADDRMAP9 - Address Map Register 9 */ +/*! @{ */ + +#define DDRC_ADDRMAP9_addrmap_row_b2_MASK (0xFU) +#define DDRC_ADDRMAP9_addrmap_row_b2_SHIFT (0U) +/*! addrmap_row_b2 - Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 + * Internal Base: 8 The selected HIF address bit for each of the row address bits is determined by + * adding the internal base to the value of this field. This register field is used only when + * ADDRMAP5.addrmap_row_b2_10 is set to value 15. + */ +#define DDRC_ADDRMAP9_addrmap_row_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b2_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b2_MASK) + +#define DDRC_ADDRMAP9_addrmap_row_b3_MASK (0xF00U) +#define DDRC_ADDRMAP9_addrmap_row_b3_SHIFT (8U) +/*! addrmap_row_b3 - Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 + * Internal Base: 9 The selected HIF address bit for each of the row address bits is determined by + * adding the internal base to the value of this field. This register field is used only when + * ADDRMAP5.addrmap_row_b2_10 is set to value 15. + */ +#define DDRC_ADDRMAP9_addrmap_row_b3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b3_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b3_MASK) + +#define DDRC_ADDRMAP9_addrmap_row_b4_MASK (0xF0000U) +#define DDRC_ADDRMAP9_addrmap_row_b4_SHIFT (16U) +/*! addrmap_row_b4 - Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 + * Internal Base: 10 The selected HIF address bit for each of the row address bits is determined by + * adding the internal base to the value of this field. This register field is used only when + * ADDRMAP5.addrmap_row_b2_10 is set to value 15. + */ +#define DDRC_ADDRMAP9_addrmap_row_b4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b4_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b4_MASK) + +#define DDRC_ADDRMAP9_addrmap_row_b5_MASK (0xF000000U) +#define DDRC_ADDRMAP9_addrmap_row_b5_SHIFT (24U) +/*! addrmap_row_b5 - Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 + * Internal Base: 11 The selected HIF address bit for each of the row address bits is determined by + * adding the internal base to the value of this field. This register field is used only when + * ADDRMAP5.addrmap_row_b2_10 is set to value 15. + */ +#define DDRC_ADDRMAP9_addrmap_row_b5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b5_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b5_MASK) +/*! @} */ + +/*! @name ADDRMAP10 - Address Map Register 10 */ +/*! @{ */ + +#define DDRC_ADDRMAP10_addrmap_row_b6_MASK (0xFU) +#define DDRC_ADDRMAP10_addrmap_row_b6_SHIFT (0U) +/*! addrmap_row_b6 - Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 + * Internal Base: 12 The selected HIF address bit for each of the row address bits is determined by + * adding the internal base to the value of this field. This register field is used only when + * ADDRMAP5.addrmap_row_b2_10 is set to value 15. + */ +#define DDRC_ADDRMAP10_addrmap_row_b6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b6_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b6_MASK) + +#define DDRC_ADDRMAP10_addrmap_row_b7_MASK (0xF00U) +#define DDRC_ADDRMAP10_addrmap_row_b7_SHIFT (8U) +/*! addrmap_row_b7 - Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 + * Internal Base: 13 The selected HIF address bit for each of the row address bits is determined by + * adding the internal base to the value of this field. This register field is used only when + * ADDRMAP5.addrmap_row_b2_10 is set to value 15. + */ +#define DDRC_ADDRMAP10_addrmap_row_b7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b7_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b7_MASK) + +#define DDRC_ADDRMAP10_addrmap_row_b8_MASK (0xF0000U) +#define DDRC_ADDRMAP10_addrmap_row_b8_SHIFT (16U) +/*! addrmap_row_b8 - Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 + * Internal Base: 14 The selected HIF address bit for each of the row address bits is determined by + * adding the internal base to the value of this field. This register field is used only when + * ADDRMAP5.addrmap_row_b2_10 is set to value 15. + */ +#define DDRC_ADDRMAP10_addrmap_row_b8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b8_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b8_MASK) + +#define DDRC_ADDRMAP10_addrmap_row_b9_MASK (0xF000000U) +#define DDRC_ADDRMAP10_addrmap_row_b9_SHIFT (24U) +/*! addrmap_row_b9 - Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 + * Internal Base: 15 The selected HIF address bit for each of the row address bits is determined by + * adding the internal base to the value of this field. This register field is used only when + * ADDRMAP5.addrmap_row_b2_10 is set to value 15. + */ +#define DDRC_ADDRMAP10_addrmap_row_b9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b9_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b9_MASK) +/*! @} */ + +/*! @name ADDRMAP11 - Address Map Register 11 */ +/*! @{ */ + +#define DDRC_ADDRMAP11_addrmap_row_b10_MASK (0xFU) +#define DDRC_ADDRMAP11_addrmap_row_b10_SHIFT (0U) +/*! addrmap_row_b10 - Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 + * Internal Base: 16 The selected HIF address bit for each of the row address bits is determined + * by adding the internal base to the value of this field. This register field is used only when + * ADDRMAP5.addrmap_row_b2_10 is set to value 15. + */ +#define DDRC_ADDRMAP11_addrmap_row_b10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP11_addrmap_row_b10_SHIFT)) & DDRC_ADDRMAP11_addrmap_row_b10_MASK) +/*! @} */ + +/*! @name ODTCFG - ODT Configuration Register */ +/*! @{ */ + +#define DDRC_ODTCFG_rd_odt_delay_MASK (0x7CU) +#define DDRC_ODTCFG_rd_odt_delay_SHIFT (2U) +/*! rd_odt_delay - The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT + * values associated with that command. ODT setting must remain constant for the entire time that + * DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 + * (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL - + * CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL + * mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write + * preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does + * not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) + */ +#define DDRC_ODTCFG_rd_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_rd_odt_delay_MASK) + +#define DDRC_ODTCFG_rd_odt_hold_MASK (0xF00U) +#define DDRC_ODTCFG_rd_odt_hold_SHIFT (8U) +/*! rd_odt_hold - DFI PHY clock cycles to hold ODT for a read command. The minimum supported value + * is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not + * DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK + * write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - + * RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK) + */ +#define DDRC_ODTCFG_rd_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_rd_odt_hold_MASK) + +#define DDRC_ODTCFG_wr_odt_delay_MASK (0x1F0000U) +#define DDRC_ODTCFG_wr_odt_delay_SHIFT (16U) +/*! wr_odt_delay - The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant for the entire time that + * DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + + * AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT + * for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: + * - WL - 1 - RU(tODTon(max)/tCK)) + */ +#define DDRC_ODTCFG_wr_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_wr_odt_delay_MASK) + +#define DDRC_ODTCFG_wr_odt_hold_MASK (0xF000000U) +#define DDRC_ODTCFG_wr_odt_hold_SHIFT (24U) +/*! wr_odt_hold - DFI PHY clock cycles to hold ODT for a write command. The minimum supported value + * is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066) + * - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: + * 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) + * CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) + */ +#define DDRC_ODTCFG_wr_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_wr_odt_hold_MASK) +/*! @} */ + +/*! @name ODTMAP - ODT/Rank Map Register */ +/*! @{ */ + +#define DDRC_ODTMAP_rank0_wr_odt_MASK (0x3U) +#define DDRC_ODTMAP_rank0_wr_odt_SHIFT (0U) +/*! rank0_wr_odt - Indicates which remote ODTs must be turned on during a write to rank 0. Each rank + * has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. + * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each + * rank, set its bit to 1 to enable its ODT. + */ +#define DDRC_ODTMAP_rank0_wr_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_wr_odt_SHIFT)) & DDRC_ODTMAP_rank0_wr_odt_MASK) + +#define DDRC_ODTMAP_rank0_rd_odt_MASK (0x30U) +#define DDRC_ODTMAP_rank0_rd_odt_SHIFT (4U) +/*! rank0_rd_odt - Indicates which remote ODTs must be turned on during a read from rank 0. Each + * rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. + * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each + * rank, set its bit to 1 to enable its ODT. + */ +#define DDRC_ODTMAP_rank0_rd_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_rd_odt_SHIFT)) & DDRC_ODTMAP_rank0_rd_odt_MASK) + +#define DDRC_ODTMAP_rank1_wr_odt_MASK (0x300U) +#define DDRC_ODTMAP_rank1_wr_odt_SHIFT (8U) +/*! rank1_wr_odt - Indicates which remote ODTs must be turned on during a write to rank 1. Each rank + * has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. + * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each + * rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks + */ +#define DDRC_ODTMAP_rank1_wr_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_wr_odt_SHIFT)) & DDRC_ODTMAP_rank1_wr_odt_MASK) + +#define DDRC_ODTMAP_rank1_rd_odt_MASK (0x3000U) +#define DDRC_ODTMAP_rank1_rd_odt_SHIFT (12U) +/*! rank1_rd_odt - Indicates which remote ODTs must be turned on during a read from rank 1. Each + * rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. + * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each + * rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more + * ranks + */ +#define DDRC_ODTMAP_rank1_rd_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_rd_odt_SHIFT)) & DDRC_ODTMAP_rank1_rd_odt_MASK) +/*! @} */ + +/*! @name SCHED - Scheduler Control Register */ +/*! @{ */ + +#define DDRC_SCHED_force_low_pri_n_MASK (0x1U) +#define DDRC_SCHED_force_low_pri_n_SHIFT (0U) +/*! force_low_pri_n - Active low signal. When asserted ('0'), all incoming transactions are forced + * to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read + * commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all + * Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. + * Forcing the incoming transactions to low priority implicitly turns off Bypass path for read + * commands. FOR PERFORMANCE ONLY. + */ +#define DDRC_SCHED_force_low_pri_n(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_force_low_pri_n_SHIFT)) & DDRC_SCHED_force_low_pri_n_MASK) + +#define DDRC_SCHED_prefer_write_MASK (0x2U) +#define DDRC_SCHED_prefer_write_SHIFT (1U) +/*! prefer_write - If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. + */ +#define DDRC_SCHED_prefer_write(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_prefer_write_SHIFT)) & DDRC_SCHED_prefer_write_MASK) + +#define DDRC_SCHED_pageclose_MASK (0x4U) +#define DDRC_SCHED_pageclose_SHIFT (2U) +/*! pageclose - If true, bank is kept open only while there are page hit transactions available in + * the CAM to that bank. The last read or write command in the CAM with a bank and page hit will + * be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and + * SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued + * in some cases where there is a mode switch between Write and Read or between LPR and HPR. The + * Read and Write commands that are executed as part of the ECC scrub requests are also executed + * without auto-precharge. If false, the bank remains open until there is a need to close it (to + * open a different page, or for page timeout or refresh timeout) - also known as open page + * policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF + * interface (hif_cmd_autopre). The pageclose feature provids a midway between Open and Close page + * policies. FOR PERFORMANCE ONLY. + */ +#define DDRC_SCHED_pageclose(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_pageclose_SHIFT)) & DDRC_SCHED_pageclose_MASK) + +#define DDRC_SCHED_lpr_num_entries_MASK (0x1F00U) +#define DDRC_SCHED_lpr_num_entries_SHIFT (8U) +/*! lpr_num_entries - Number of entries in the low priority transaction store is this value + 1. + * (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high + * priority transaction store. Setting this to maximum value allocates all entries to low + * priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and + * the rest to high priority transaction store. Note: In ECC configurations, the numbers of + * write and low priority read credits issued is one less than in the non-ECC case. One entry each is + * reserved in the write and low-priority read CAMs for storing the RMW requests arising out of + * single bit error correction RMW operation. + */ +#define DDRC_SCHED_lpr_num_entries(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_lpr_num_entries_SHIFT)) & DDRC_SCHED_lpr_num_entries_MASK) + +#define DDRC_SCHED_go2critical_hysteresis_MASK (0xFF0000U) +#define DDRC_SCHED_go2critical_hysteresis_SHIFT (16U) +/*! go2critical_hysteresis - UNUSED + */ +#define DDRC_SCHED_go2critical_hysteresis(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_go2critical_hysteresis_SHIFT)) & DDRC_SCHED_go2critical_hysteresis_MASK) + +#define DDRC_SCHED_rdwr_idle_gap_MASK (0x7F000000U) +#define DDRC_SCHED_rdwr_idle_gap_SHIFT (24U) +/*! rdwr_idle_gap - When the preferred transaction store is empty for these many clock cycles, + * switch to the alternate transaction store if it is non-empty. The read transaction store (both high + * and low priority) is the default preferred transaction store and the write transaction store + * is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal + * value for this register. When set to 0x0, the transaction store switching will happen + * immediately when the switching conditions become true. FOR PERFORMANCE ONLY + */ +#define DDRC_SCHED_rdwr_idle_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_rdwr_idle_gap_SHIFT)) & DDRC_SCHED_rdwr_idle_gap_MASK) +/*! @} */ + +/*! @name SCHED1 - Scheduler Control Register 1 */ +/*! @{ */ + +#define DDRC_SCHED1_pageclose_timer_MASK (0xFFU) +#define DDRC_SCHED1_pageclose_timer_SHIFT (0U) +/*! pageclose_timer - This field works in conjunction with SCHED.pageclose. It only has meaning if + * SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be + * scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes + * an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for + * details of when this may happen. If SCHED.pageclose==1 and pageclose_timer>0, then an + * auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit. + * Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per + * bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page + * hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a + * page hit. Once the timer has reached zero, an explcit precharge will be attempted to be + * scheduled. + */ +#define DDRC_SCHED1_pageclose_timer(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED1_pageclose_timer_SHIFT)) & DDRC_SCHED1_pageclose_timer_MASK) +/*! @} */ + +/*! @name PERFHPR1 - High Priority Read CAM Register 1 */ +/*! @{ */ + +#define DDRC_PERFHPR1_hpr_max_starve_MASK (0xFFFFU) +#define DDRC_PERFHPR1_hpr_max_starve_SHIFT (0U) +/*! hpr_max_starve - Number of DFI clocks that the HPR queue can be starved before it goes critical. + * The minimum valid functional value for this register is 0x1. Programming it to 0x0 will + * disable the starvation functionality; during normal operation, this function should not be disabled + * as it will cause excessive latencies. FOR PERFORMANCE ONLY. + */ +#define DDRC_PERFHPR1_hpr_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_max_starve_SHIFT)) & DDRC_PERFHPR1_hpr_max_starve_MASK) + +#define DDRC_PERFHPR1_hpr_xact_run_length_MASK (0xFF000000U) +#define DDRC_PERFHPR1_hpr_xact_run_length_SHIFT (24U) +/*! hpr_xact_run_length - Number of transactions that are serviced once the HPR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions available. Unit: + * Transaction. FOR PERFORMANCE ONLY. + */ +#define DDRC_PERFHPR1_hpr_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_xact_run_length_SHIFT)) & DDRC_PERFHPR1_hpr_xact_run_length_MASK) +/*! @} */ + +/*! @name PERFLPR1 - Low Priority Read CAM Register 1 */ +/*! @{ */ + +#define DDRC_PERFLPR1_lpr_max_starve_MASK (0xFFFFU) +#define DDRC_PERFLPR1_lpr_max_starve_SHIFT (0U) +/*! lpr_max_starve - Number of DFI clocks that the LPR queue can be starved before it goes critical. + * The minimum valid functional value for this register is 0x1. Programming it to 0x0 will + * disable the starvation functionality; during normal operation, this function should not be disabled + * as it will cause excessive latencies. FOR PERFORMANCE ONLY. + */ +#define DDRC_PERFLPR1_lpr_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_max_starve_SHIFT)) & DDRC_PERFLPR1_lpr_max_starve_MASK) + +#define DDRC_PERFLPR1_lpr_xact_run_length_MASK (0xFF000000U) +#define DDRC_PERFLPR1_lpr_xact_run_length_SHIFT (24U) +/*! lpr_xact_run_length - Number of transactions that are serviced once the LPR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions available. Unit: + * Transaction. FOR PERFORMANCE ONLY. + */ +#define DDRC_PERFLPR1_lpr_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_xact_run_length_SHIFT)) & DDRC_PERFLPR1_lpr_xact_run_length_MASK) +/*! @} */ + +/*! @name PERFWR1 - Write CAM Register 1 */ +/*! @{ */ + +#define DDRC_PERFWR1_w_max_starve_MASK (0xFFFFU) +#define DDRC_PERFWR1_w_max_starve_SHIFT (0U) +/*! w_max_starve - Number of DFI clocks that the WR queue can be starved before it goes critical. + * The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable + * the starvation functionality; during normal operation, this function should not be disabled as + * it will cause excessive latencies. FOR PERFORMANCE ONLY. + */ +#define DDRC_PERFWR1_w_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_max_starve_SHIFT)) & DDRC_PERFWR1_w_max_starve_MASK) + +#define DDRC_PERFWR1_w_xact_run_length_MASK (0xFF000000U) +#define DDRC_PERFWR1_w_xact_run_length_SHIFT (24U) +/*! w_xact_run_length - Number of transactions that are serviced once the WR queue goes critical is + * the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction. + * FOR PERFORMANCE ONLY. + */ +#define DDRC_PERFWR1_w_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_xact_run_length_SHIFT)) & DDRC_PERFWR1_w_xact_run_length_MASK) +/*! @} */ + +/*! @name DBG0 - Debug Register 0 */ +/*! @{ */ + +#define DDRC_DBG0_dis_wc_MASK (0x1U) +#define DDRC_DBG0_dis_wc_SHIFT (0U) +/*! dis_wc - When 1, disable write combine. FOR DEBUG ONLY + */ +#define DDRC_DBG0_dis_wc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_wc_SHIFT)) & DDRC_DBG0_dis_wc_MASK) + +#define DDRC_DBG0_dis_rd_bypass_MASK (0x2U) +#define DDRC_DBG0_dis_rd_bypass_SHIFT (1U) +/*! dis_rd_bypass - Only present in designs supporting read bypass. When 1, disable bypass path for + * high priority read page hits FOR DEBUG ONLY. + */ +#define DDRC_DBG0_dis_rd_bypass(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_rd_bypass_SHIFT)) & DDRC_DBG0_dis_rd_bypass_MASK) + +#define DDRC_DBG0_dis_act_bypass_MASK (0x4U) +#define DDRC_DBG0_dis_act_bypass_SHIFT (2U) +/*! dis_act_bypass - Only present in designs supporting activate bypass. When 1, disable bypass path + * for high priority read activates FOR DEBUG ONLY. + */ +#define DDRC_DBG0_dis_act_bypass(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_act_bypass_SHIFT)) & DDRC_DBG0_dis_act_bypass_MASK) + +#define DDRC_DBG0_dis_collision_page_opt_MASK (0x10U) +#define DDRC_DBG0_dis_collision_page_opt_SHIFT (4U) +/*! dis_collision_page_opt - When this is set to '0', auto-precharge is disabled for the flushed + * command in a collision case. Collision cases are write followed by read to same address, read + * followed by write to same address, or write followed by write to same address with DBG0.dis_wc + * bit = 1 (where same address comparisons exclude the two address bits representing critical + * word). FOR DEBUG ONLY. + */ +#define DDRC_DBG0_dis_collision_page_opt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_collision_page_opt_SHIFT)) & DDRC_DBG0_dis_collision_page_opt_MASK) +/*! @} */ + +/*! @name DBG1 - Debug Register 1 */ +/*! @{ */ + +#define DDRC_DBG1_dis_dq_MASK (0x1U) +#define DDRC_DBG1_dis_dq_SHIFT (0U) +/*! dis_dq - When 1, DDRC will not de-queue any transactions from the CAM. Bypass is also disabled. + * All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this + * is asserted. This bit may be used to prevent reads or writes being issued by the DDRC, which + * makes it safe to modify certain register fields associated with reads and writes (see User + * Guide for details). After setting this bit, it is strongly recommended to poll + * DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which + * affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. This bit + * is intended to be switched on-the-fly. + */ +#define DDRC_DBG1_dis_dq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_dq_SHIFT)) & DDRC_DBG1_dis_dq_MASK) + +#define DDRC_DBG1_dis_hif_MASK (0x2U) +#define DDRC_DBG1_dis_hif_SHIFT (1U) +/*! dis_hif - When 1, DDRC asserts the HIF command signal hif_cmd_stall. DDRC will ignore the + * hif_cmd_valid and all other associated request signals. This bit is intended to be switched + * on-the-fly. + */ +#define DDRC_DBG1_dis_hif(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_hif_SHIFT)) & DDRC_DBG1_dis_hif_MASK) +/*! @} */ + +/*! @name DBGCAM - CAM Debug Register */ +/*! @{ */ + +#define DDRC_DBGCAM_dbg_hpr_q_depth_MASK (0x3FU) +#define DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT (0U) +/*! dbg_hpr_q_depth - High priority read queue depth FOR DEBUG ONLY + */ +#define DDRC_DBGCAM_dbg_hpr_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_hpr_q_depth_MASK) + +#define DDRC_DBGCAM_dbg_lpr_q_depth_MASK (0x3F00U) +#define DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT (8U) +/*! dbg_lpr_q_depth - Low priority read queue depth The last entry of Lpr queue is reserved for ECC + * SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG + * ONLY + */ +#define DDRC_DBGCAM_dbg_lpr_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_lpr_q_depth_MASK) + +#define DDRC_DBGCAM_dbg_w_q_depth_MASK (0x3F0000U) +#define DDRC_DBGCAM_dbg_w_q_depth_SHIFT (16U) +/*! dbg_w_q_depth - Write queue depth The last entry of WR queue is reserved for ECC SCRUB + * operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY + */ +#define DDRC_DBGCAM_dbg_w_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_w_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_w_q_depth_MASK) + +#define DDRC_DBGCAM_dbg_stall_MASK (0x1000000U) +#define DDRC_DBGCAM_dbg_stall_SHIFT (24U) +/*! dbg_stall - Stall FOR DEBUG ONLY + */ +#define DDRC_DBGCAM_dbg_stall(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_SHIFT)) & DDRC_DBGCAM_dbg_stall_MASK) + +#define DDRC_DBGCAM_dbg_rd_q_empty_MASK (0x2000000U) +#define DDRC_DBGCAM_dbg_rd_q_empty_SHIFT (25U) +/*! dbg_rd_q_empty - When 1, all the Read command queues and Read data buffers inside DDRC are + * empty. This register is to be used for debug purpose. An example use-case scenario: When Controller + * enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have + * executed all the commands in its queues and the write and read data drained. Hence this register + * should be 1 at that time. FOR DEBUG ONLY + */ +#define DDRC_DBGCAM_dbg_rd_q_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_rd_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_rd_q_empty_MASK) + +#define DDRC_DBGCAM_dbg_wr_q_empty_MASK (0x4000000U) +#define DDRC_DBGCAM_dbg_wr_q_empty_SHIFT (26U) +/*! dbg_wr_q_empty - When 1, all the Write command queues and Write data buffers inside DDRC are + * empty. This register is to be used for debug purpose. An example use-case scenario: When + * Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have + * executed all the commands in its queues and the write and read data drained. Hence this register + * should be 1 at that time. FOR DEBUG ONLY + */ +#define DDRC_DBGCAM_dbg_wr_q_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_wr_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_wr_q_empty_MASK) + +#define DDRC_DBGCAM_rd_data_pipeline_empty_MASK (0x10000000U) +#define DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT (28U) +/*! rd_data_pipeline_empty - This bit indicates that the read data pipeline on the DFI interface is + * empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to + * ensure that all remaining commands/data have completed. + */ +#define DDRC_DBGCAM_rd_data_pipeline_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT)) & DDRC_DBGCAM_rd_data_pipeline_empty_MASK) + +#define DDRC_DBGCAM_wr_data_pipeline_empty_MASK (0x20000000U) +#define DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT (29U) +/*! wr_data_pipeline_empty - This bit indicates that the write data pipeline on the DFI interface is + * empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to + * ensure that all remaining commands/data have completed. + */ +#define DDRC_DBGCAM_wr_data_pipeline_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT)) & DDRC_DBGCAM_wr_data_pipeline_empty_MASK) + +#define DDRC_DBGCAM_dbg_stall_wr_MASK (0x40000000U) +#define DDRC_DBGCAM_dbg_stall_wr_SHIFT (30U) +/*! dbg_stall_wr - Stall for Write channel FOR DEBUG ONLY + */ +#define DDRC_DBGCAM_dbg_stall_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_wr_SHIFT)) & DDRC_DBGCAM_dbg_stall_wr_MASK) + +#define DDRC_DBGCAM_dbg_stall_rd_MASK (0x80000000U) +#define DDRC_DBGCAM_dbg_stall_rd_SHIFT (31U) +/*! dbg_stall_rd - Stall for Read channel FOR DEBUG ONLY + */ +#define DDRC_DBGCAM_dbg_stall_rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_rd_SHIFT)) & DDRC_DBGCAM_dbg_stall_rd_MASK) +/*! @} */ + +/*! @name DBGCMD - Command Debug Register */ +/*! @{ */ + +#define DDRC_DBGCMD_rank0_refresh_MASK (0x1U) +#define DDRC_DBGCMD_rank0_refresh_SHIFT (0U) +/*! rank0_refresh - Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank + * 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When + * DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent + * to rank index 0. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is + * recommended NOT to set this register bit if in Init or Deep power-down operating modes or + * Maximum Power Saving Mode. + */ +#define DDRC_DBGCMD_rank0_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank0_refresh_SHIFT)) & DDRC_DBGCMD_rank0_refresh_MASK) + +#define DDRC_DBGCMD_rank1_refresh_MASK (0x2U) +#define DDRC_DBGCMD_rank1_refresh_SHIFT (1U) +/*! rank1_refresh - Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank + * 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When + * DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent + * to rank index 1. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is + * recommended NOT to set this register bit if in Init or Deep power-down operating modes or + * Maximum Power Saving Mode. + */ +#define DDRC_DBGCMD_rank1_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank1_refresh_SHIFT)) & DDRC_DBGCMD_rank1_refresh_MASK) + +#define DDRC_DBGCMD_zq_calib_short_MASK (0x10U) +#define DDRC_DBGCMD_zq_calib_short_SHIFT (4U) +/*! zq_calib_short - Setting this register bit to 1 indicates to the DDRC to issue a ZQCS (ZQ + * calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the + * DDRC, the bit is automatically cleared. This operation can be performed only when + * ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register + * bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep + * power-down operating modes and Maximum Power Saving Mode. + */ +#define DDRC_DBGCMD_zq_calib_short(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_zq_calib_short_SHIFT)) & DDRC_DBGCMD_zq_calib_short_MASK) + +#define DDRC_DBGCMD_ctrlupd_MASK (0x20U) +#define DDRC_DBGCMD_ctrlupd_SHIFT (5U) +/*! ctrlupd - Setting this register bit to 1 indicates to the DDRC to issue a dfi_ctrlupd_req to the + * PHY. When this request is stored in the DDRC, the bit is automatically cleared. This + * operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. + */ +#define DDRC_DBGCMD_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_ctrlupd_SHIFT)) & DDRC_DBGCMD_ctrlupd_MASK) +/*! @} */ + +/*! @name DBGSTAT - Status Debug Register */ +/*! @{ */ + +#define DDRC_DBGSTAT_rank0_refresh_busy_MASK (0x1U) +#define DDRC_DBGSTAT_rank0_refresh_busy_SHIFT (0U) +/*! rank0_refresh_busy - SoC core may initiate a rank0_refresh operation (refresh operation to rank + * 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh + * is set to one. It goes low when the rank0_refresh operation is stored in the DDRC. It is + * recommended not to perform rank0_refresh operations when this signal is high. - 0 - Indicates that + * the SoC core can initiate a rank0_refresh operation - 1 - Indicates that rank0_refresh + * operation has not been stored yet in the DDRC + */ +#define DDRC_DBGSTAT_rank0_refresh_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank0_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank0_refresh_busy_MASK) + +#define DDRC_DBGSTAT_rank1_refresh_busy_MASK (0x2U) +#define DDRC_DBGSTAT_rank1_refresh_busy_SHIFT (1U) +/*! rank1_refresh_busy - SoC core may initiate a rank1_refresh operation (refresh operation to rank + * 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh + * is set to one. It goes low when the rank1_refresh operation is stored in the DDRC. It is + * recommended not to perform rank1_refresh operations when this signal is high. - 0 - Indicates that + * the SoC core can initiate a rank1_refresh operation - 1 - Indicates that rank1_refresh + * operation has not been stored yet in the DDRC + */ +#define DDRC_DBGSTAT_rank1_refresh_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank1_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank1_refresh_busy_MASK) + +#define DDRC_DBGSTAT_zq_calib_short_busy_MASK (0x10U) +#define DDRC_DBGSTAT_zq_calib_short_busy_SHIFT (4U) +/*! zq_calib_short_busy - SoC core may initiate a ZQCS (ZQ calibration short) operation only if this + * signal is low. This signal goes high in the clock after the DDRC accepts the ZQCS request. It + * goes low when the ZQCS operation is initiated in the DDRC. It is recommended not to perform + * ZQCS operations when this signal is high. - 0 - Indicates that the SoC core can initiate a ZQCS + * operation - 1 - Indicates that ZQCS operation has not been initiated yet in the DDRC + */ +#define DDRC_DBGSTAT_zq_calib_short_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_zq_calib_short_busy_SHIFT)) & DDRC_DBGSTAT_zq_calib_short_busy_MASK) + +#define DDRC_DBGSTAT_ctrlupd_busy_MASK (0x20U) +#define DDRC_DBGSTAT_ctrlupd_busy_SHIFT (5U) +/*! ctrlupd_busy - SoC core may initiate a ctrlupd operation only if this signal is low. This signal + * goes high in the clock after the DDRC accepts the ctrlupd request. It goes low when the + * ctrlupd operation is initiated in the DDRC. It is recommended not to perform ctrlupd operations + * when this signal is high. - 0 - Indicates that the SoC core can initiate a ctrlupd operation - 1 + * - Indicates that ctrlupd operation has not been initiated yet in the DDRC + */ +#define DDRC_DBGSTAT_ctrlupd_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_ctrlupd_busy_SHIFT)) & DDRC_DBGSTAT_ctrlupd_busy_MASK) +/*! @} */ + +/*! @name SWCTL - Software Register Programming Control Enable */ +/*! @{ */ + +#define DDRC_SWCTL_sw_done_MASK (0x1U) +#define DDRC_SWCTL_sw_done_SHIFT (0U) +/*! sw_done - Enable quasi-dynamic register programming outside reset. Program register to 0 to + * enable quasi-dynamic programming. Set back register to 1 once programming is done. + */ +#define DDRC_SWCTL_sw_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SWCTL_sw_done_SHIFT)) & DDRC_SWCTL_sw_done_MASK) +/*! @} */ + +/*! @name SWSTAT - Software Register Programming Control Status */ +/*! @{ */ + +#define DDRC_SWSTAT_sw_done_ack_MASK (0x1U) +#define DDRC_SWSTAT_sw_done_ack_SHIFT (0U) +/*! sw_done_ack - Register programming done. This register is the echo of SWCTL.sw_done. Wait for + * sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure + * that the correct registers values are propagated to the destination clock domains. + */ +#define DDRC_SWSTAT_sw_done_ack(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SWSTAT_sw_done_ack_SHIFT)) & DDRC_SWSTAT_sw_done_ack_MASK) +/*! @} */ + +/*! @name POISONCFG - AXI Poison Configuration Register. */ +/*! @{ */ + +#define DDRC_POISONCFG_wr_poison_slverr_en_MASK (0x1U) +#define DDRC_POISONCFG_wr_poison_slverr_en_SHIFT (0U) +/*! wr_poison_slverr_en - If set to 1, enables SLVERR response for write transaction poisoning + */ +#define DDRC_POISONCFG_wr_poison_slverr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_slverr_en_SHIFT)) & DDRC_POISONCFG_wr_poison_slverr_en_MASK) + +#define DDRC_POISONCFG_wr_poison_intr_en_MASK (0x10U) +#define DDRC_POISONCFG_wr_poison_intr_en_SHIFT (4U) +/*! wr_poison_intr_en - If set to 1, enables interrupts for write transaction poisoning + */ +#define DDRC_POISONCFG_wr_poison_intr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_en_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_en_MASK) + +#define DDRC_POISONCFG_wr_poison_intr_clr_MASK (0x100U) +#define DDRC_POISONCFG_wr_poison_intr_clr_SHIFT (8U) +/*! wr_poison_intr_clr - Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for + * correct value to propagate to core logic and clear the interrupts. + */ +#define DDRC_POISONCFG_wr_poison_intr_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_clr_MASK) + +#define DDRC_POISONCFG_rd_poison_slverr_en_MASK (0x10000U) +#define DDRC_POISONCFG_rd_poison_slverr_en_SHIFT (16U) +/*! rd_poison_slverr_en - If set to 1, enables SLVERR response for read transaction poisoning + */ +#define DDRC_POISONCFG_rd_poison_slverr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_slverr_en_SHIFT)) & DDRC_POISONCFG_rd_poison_slverr_en_MASK) + +#define DDRC_POISONCFG_rd_poison_intr_en_MASK (0x100000U) +#define DDRC_POISONCFG_rd_poison_intr_en_SHIFT (20U) +/*! rd_poison_intr_en - If set to 1, enables interrupts for read transaction poisoning + */ +#define DDRC_POISONCFG_rd_poison_intr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_en_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_en_MASK) + +#define DDRC_POISONCFG_rd_poison_intr_clr_MASK (0x1000000U) +#define DDRC_POISONCFG_rd_poison_intr_clr_SHIFT (24U) +/*! rd_poison_intr_clr - Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for + * correct value to propagate to core logic and clear the interrupts. + */ +#define DDRC_POISONCFG_rd_poison_intr_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_clr_MASK) +/*! @} */ + +/*! @name POISONSTAT - AXI Poison Status Register */ +/*! @{ */ + +#define DDRC_POISONSTAT_wr_poison_intr_0_MASK (0x1U) +#define DDRC_POISONSTAT_wr_poison_intr_0_SHIFT (0U) +/*! wr_poison_intr_0 - Write transaction poisoning error interrupt for port 0. This register is a + * APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is + * poisoned on the corresponding AXI port's write address channel. Bit 0 corresponds to Port 0, and + * so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB + * clock. + */ +#define DDRC_POISONSTAT_wr_poison_intr_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_wr_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_wr_poison_intr_0_MASK) + +#define DDRC_POISONSTAT_rd_poison_intr_0_MASK (0x10000U) +#define DDRC_POISONSTAT_rd_poison_intr_0_SHIFT (16U) +/*! rd_poison_intr_0 - Read transaction poisoning error interrupt for port 0. This register is a APB + * clock copy (double register synchronizer) of the interrupt asserted when a transaction is + * poisoned on the corresponding AXI port's read address channel. Bit 0 corresponds to Port 0, and + * so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. + */ +#define DDRC_POISONSTAT_rd_poison_intr_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_rd_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_rd_poison_intr_0_MASK) +/*! @} */ + +/*! @name PSTAT - Port Status Register */ +/*! @{ */ + +#define DDRC_PSTAT_rd_port_busy_0_MASK (0x1U) +#define DDRC_PSTAT_rd_port_busy_0_SHIFT (0U) +/*! rd_port_busy_0 - Indicates if there are outstanding reads for AXI port 0. + */ +#define DDRC_PSTAT_rd_port_busy_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_rd_port_busy_0_SHIFT)) & DDRC_PSTAT_rd_port_busy_0_MASK) + +#define DDRC_PSTAT_wr_port_busy_0_MASK (0x10000U) +#define DDRC_PSTAT_wr_port_busy_0_SHIFT (16U) +/*! wr_port_busy_0 - Indicates if there are outstanding writes for AXI port 0. + */ +#define DDRC_PSTAT_wr_port_busy_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_wr_port_busy_0_SHIFT)) & DDRC_PSTAT_wr_port_busy_0_MASK) +/*! @} */ + +/*! @name PCCFG - Port Common Configuration Register */ +/*! @{ */ + +#define DDRC_PCCFG_go2critical_en_MASK (0x1U) +#define DDRC_PCCFG_go2critical_en_SHIFT (0U) +/*! go2critical_en - If set to 1 (enabled), sets co_gs_go2critical_wr and + * co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from + * AXI master. If set to 0 (disabled), co_gs_go2critical_wr and + * co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0. + */ +#define DDRC_PCCFG_go2critical_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_go2critical_en_SHIFT)) & DDRC_PCCFG_go2critical_en_MASK) + +#define DDRC_PCCFG_pagematch_limit_MASK (0x10U) +#define DDRC_PCCFG_pagematch_limit_SHIFT (4U) +/*! pagematch_limit - Page match four limit. If set to 1, limits the number of consecutive same page + * DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is + * enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC + * transactions. + */ +#define DDRC_PCCFG_pagematch_limit(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_pagematch_limit_SHIFT)) & DDRC_PCCFG_pagematch_limit_MASK) + +#define DDRC_PCCFG_bl_exp_mode_MASK (0x100U) +#define DDRC_PCCFG_bl_exp_mode_SHIFT (8U) +/*! bl_exp_mode - Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every + * AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then + * XPI will use half of the memory burst length as a unit. This applies to both reads and + * writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in + * cases where Partial Writes is enabled (DDRC_PARTIAL_WR=1), in order to avoid or minimize t_ccd_l + * penalty in DDR4 and t_ccd_mw penalty in LPDDR4. Hence, bl_exp_mode=1 is only recommended if + * DDR4 or LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the + * following cases: - DDRC_PARTIAL_WR=0 - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01, + * MEMC_BURST_LENGTH=8 and MSTR.burst_rdwr=1000 (LPDDR4 only) - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01, + * MEMC_BURST_LENGTH=4 and MSTR.burst_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or + * CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Data Channel + * Interleave is enabled + */ +#define DDRC_PCCFG_bl_exp_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_bl_exp_mode_SHIFT)) & DDRC_PCCFG_bl_exp_mode_MASK) +/*! @} */ + +/*! @name PCFGR_0 - Port n Configuration Read Register */ +/*! @{ */ + +#define DDRC_PCFGR_0_rd_port_priority_MASK (0x3FFU) +#define DDRC_PCFGR_0_rd_port_priority_SHIFT (0U) +/*! rd_port_priority - Determines the initial load value of read aging counters. These counters will + * be parallel loaded after reset, or after each grant to the corresponding port. The aging + * counters down-count every clock cycle where the port is requesting but not granted. The higher + * significant 5-bits of the read aging counter sets the priority of the read channel of a given + * port. Port's priority will increase as the higher significant 5-bits of the counter starts to + * decrease. When the aging counter becomes 0, the corresponding port channel will have the highest + * priority level (timeout condition - Priority0). For multi-port configurations, the aging + * counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are + * enabled (timeout is still applicable). For single port configurations, the aging counters are + * only used when they timeout (become 0) to force read-write direction switching. In this case, + * external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read + * priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by + * command basis. Note: The two LSBs of this register field are tied internally to 2'b00. + */ +#define DDRC_PCFGR_0_rd_port_priority(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_priority_SHIFT)) & DDRC_PCFGR_0_rd_port_priority_MASK) + +#define DDRC_PCFGR_0_rd_port_aging_en_MASK (0x1000U) +#define DDRC_PCFGR_0_rd_port_aging_en_SHIFT (12U) +/*! rd_port_aging_en - If set to 1, enables aging function for the read channel of the port. + */ +#define DDRC_PCFGR_0_rd_port_aging_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_aging_en_SHIFT)) & DDRC_PCFGR_0_rd_port_aging_en_MASK) + +#define DDRC_PCFGR_0_rd_port_urgent_en_MASK (0x2000U) +#define DDRC_PCFGR_0_rd_port_urgent_en_SHIFT (13U) +/*! rd_port_urgent_en - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled + * and arurgent is asserted by the master, that port becomes the highest priority and + * co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in + * PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is + * independent of address handshaking (it is not associated with any particular command). + */ +#define DDRC_PCFGR_0_rd_port_urgent_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_urgent_en_SHIFT)) & DDRC_PCFGR_0_rd_port_urgent_en_MASK) + +#define DDRC_PCFGR_0_rd_port_pagematch_en_MASK (0x4000U) +#define DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT (14U) +/*! rd_port_pagematch_en - If set to 1, enables the Page Match feature. If enabled, once a + * requesting port is granted, the port is continued to be granted if the following immediate commands are + * to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit + * register. + */ +#define DDRC_PCFGR_0_rd_port_pagematch_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT)) & DDRC_PCFGR_0_rd_port_pagematch_en_MASK) + +#define DDRC_PCFGR_0_rdwr_ordered_en_MASK (0x10000U) +#define DDRC_PCFGR_0_rdwr_ordered_en_SHIFT (16U) +/*! rdwr_ordered_en - Enable ordered read/writes. If set to 1, preserves the ordering between read + * transaction and write transaction issued to the same address, on a given port. In other words, + * the controller ensures that all same address read and write commands from the application port + * interface are transported to the DFI interface in the order of acceptance. This feature is + * useful in cases where software coherency is desired for masters issuing back-to-back read/write + * transactions without waiting for write/read responses. Note that this register has an effect + * only if necessary logic is instantiated via the DDRC_RDWR_ORDERED_n parameter. + */ +#define DDRC_PCFGR_0_rdwr_ordered_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rdwr_ordered_en_SHIFT)) & DDRC_PCFGR_0_rdwr_ordered_en_MASK) +/*! @} */ + +/*! @name PCFGW_0 - Port n Configuration Write Register */ +/*! @{ */ + +#define DDRC_PCFGW_0_wr_port_priority_MASK (0x3FFU) +#define DDRC_PCFGW_0_wr_port_priority_SHIFT (0U) +/*! wr_port_priority - Determines the initial load value of write aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresponding port. The aging + * counters down-count every clock cycle where the port is requesting but not granted. The higher + * significant 5-bits of the write aging counter sets the initial priority of the write channel of + * a given port. Port's priority will increase as the higher significant 5-bits of the counter + * starts to decrease. When the aging counter becomes 0, the corresponding port channel will have + * the highest priority level. For multi-port configurations, the aging counters cannot be used to + * set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is + * still applicable). For single port configurations, the aging counters are only used when they + * timeout (become 0) to force read-write direction switching. Note: The two LSBs of this register + * field are tied internally to 2'b00. + */ +#define DDRC_PCFGW_0_wr_port_priority(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_priority_SHIFT)) & DDRC_PCFGW_0_wr_port_priority_MASK) + +#define DDRC_PCFGW_0_wr_port_aging_en_MASK (0x1000U) +#define DDRC_PCFGW_0_wr_port_aging_en_SHIFT (12U) +/*! wr_port_aging_en - If set to 1, enables aging function for the write channel of the port. + */ +#define DDRC_PCFGW_0_wr_port_aging_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_aging_en_SHIFT)) & DDRC_PCFGW_0_wr_port_aging_en_MASK) + +#define DDRC_PCFGW_0_wr_port_urgent_en_MASK (0x2000U) +#define DDRC_PCFGW_0_wr_port_urgent_en_SHIFT (13U) +/*! wr_port_urgent_en - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled + * and awurgent is asserted by the master, that port becomes the highest priority and + * co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that + * awurgent signal can be asserted anytime and as long as required which is independent of address + * handshaking (it is not associated with any particular command). + */ +#define DDRC_PCFGW_0_wr_port_urgent_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_urgent_en_SHIFT)) & DDRC_PCFGW_0_wr_port_urgent_en_MASK) + +#define DDRC_PCFGW_0_wr_port_pagematch_en_MASK (0x4000U) +#define DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT (14U) +/*! wr_port_pagematch_en - If set to 1, enables the Page Match feature. If enabled, once a + * requesting port is granted, the port is continued to be granted if the following immediate commands are + * to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit + * register. + */ +#define DDRC_PCFGW_0_wr_port_pagematch_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT)) & DDRC_PCFGW_0_wr_port_pagematch_en_MASK) +/*! @} */ + +/*! @name PCTRL_0 - Port n Control Register */ +/*! @{ */ + +#define DDRC_PCTRL_0_port_en_MASK (0x1U) +#define DDRC_PCTRL_0_port_en_SHIFT (0U) +/*! port_en - Enables AXI port n. + */ +#define DDRC_PCTRL_0_port_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCTRL_0_port_en_SHIFT)) & DDRC_PCTRL_0_port_en_MASK) +/*! @} */ + +/*! @name PCFGQOS0_0 - Port n Read QoS Configuration Register 0 */ +/*! @{ */ + +#define DDRC_PCFGQOS0_0_rqos_map_level1_MASK (0xFU) +#define DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT (0U) +/*! rqos_map_level1 - Separation level1 indicating the end of region0 mapping; start of region0 is + * 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which + * corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where + * the higher the value corresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + */ +#define DDRC_PCFGQOS0_0_rqos_map_level1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_level1_MASK) + +#define DDRC_PCFGQOS0_0_rqos_map_region0_MASK (0x30000U) +#define DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT (16U) +/*! rqos_map_region0 - This bitfield indicates the traffic class of region 0. Valid values are: 0: + * LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address + * queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support is disabled + * (DDRC_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + */ +#define DDRC_PCFGQOS0_0_rqos_map_region0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region0_MASK) + +#define DDRC_PCFGQOS0_0_rqos_map_region1_MASK (0x300000U) +#define DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT (20U) +/*! rqos_map_region1 - This bitfield indicates the traffic class of region 1. Valid values are: 0 : + * LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address + * queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled + * (DDRC_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + */ +#define DDRC_PCFGQOS0_0_rqos_map_region1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region1_MASK) +/*! @} */ + +/*! @name PCFGQOS1_0 - Port n Read QoS Configuration Register 1 */ +/*! @{ */ + +#define DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK (0x7FFU) +#define DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT (0U) +/*! rqos_map_timeoutb - Specifies the timeout value for transactions mapped to the blue address queue. + */ +#define DDRC_PCFGQOS1_0_rqos_map_timeoutb(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK) + +#define DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK (0x7FF0000U) +#define DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT (16U) +/*! rqos_map_timeoutr - Specifies the timeout value for transactions mapped to the red address queue. + */ +#define DDRC_PCFGQOS1_0_rqos_map_timeoutr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK) +/*! @} */ + +/*! @name PCFGWQOS0_0 - Port n Write QoS Configuration Register 0 */ +/*! @{ */ + +#define DDRC_PCFGWQOS0_0_wqos_map_level_MASK (0xFU) +#define DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT (0U) +/*! wqos_map_level - Separation level indicating the end of region0 mapping; start of region0 is 0. + * Possible values for level1 are 0 to 14 which corresponds to awqos. Note that for PA, awqos + * values are used directly as port priorities, where the higher the value corresponds to higher + * port priority. + */ +#define DDRC_PCFGWQOS0_0_wqos_map_level(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_level_MASK) + +#define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) +#define DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT (16U) +/*! wqos_map_region0 - This bitfield indicates the traffic class of region 0. Valid values are: 0: + * NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region0 is set + * to 1 (VPW), VPW traffic is aliased to NPW traffic. + */ +#define DDRC_PCFGWQOS0_0_wqos_map_region0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK) + +#define DDRC_PCFGWQOS0_0_wqos_map_region1_MASK (0x300000U) +#define DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT (20U) +/*! wqos_map_region1 - This bitfield indicates the traffic class of region 1. Valid values are: 0: + * NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region 1 is + * set to 1 (VPW), VPW traffic is aliased to LPW traffic. + */ +#define DDRC_PCFGWQOS0_0_wqos_map_region1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region1_MASK) +/*! @} */ + +/*! @name PCFGWQOS1_0 - Port n Write QoS Configuration Register 1 */ +/*! @{ */ + +#define DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK (0x7FFU) +#define DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT (0U) +/*! wqos_map_timeout - Specifies the timeout value for write transactions. + */ +#define DDRC_PCFGWQOS1_0_wqos_map_timeout(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT)) & DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK) +/*! @} */ + +/*! @name DERATEEN_SHADOW - [SHADOW] Temperature Derate Enable Register */ +/*! @{ */ + +#define DDRC_DERATEEN_SHADOW_derate_enable_MASK (0x1U) +#define DDRC_DERATEEN_SHADOW_derate_enable_SHIFT (0U) +/*! derate_enable - Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing + * parameter derating is enabled using MR4 read value. Present only in designs configured to support + * LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. + */ +#define DDRC_DERATEEN_SHADOW_derate_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_enable_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_enable_MASK) + +#define DDRC_DERATEEN_SHADOW_derate_value_MASK (0x2U) +#define DDRC_DERATEEN_SHADOW_derate_value_SHIFT (1U) +/*! derate_value - Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in + * designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as + * derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of + * core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it + * should be set to 0. + */ +#define DDRC_DERATEEN_SHADOW_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_value_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_value_MASK) + +#define DDRC_DERATEEN_SHADOW_derate_byte_MASK (0xF0U) +#define DDRC_DERATEEN_SHADOW_derate_byte_SHIFT (4U) +/*! derate_byte - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 + * Indicates which byte of the MRR data is used for derating. The maximum valid value depends on + * MEMC_DRAM_TOTAL_DATA_WIDTH. + */ +#define DDRC_DERATEEN_SHADOW_derate_byte(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_byte_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_byte_MASK) + +#define DDRC_DERATEEN_SHADOW_rc_derate_value_MASK (0x300U) +#define DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT (8U) +/*! rc_derate_value - Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. + * - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in designs configured to support + * LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by + * the core_ddrc_core_clk period, and rounding up the next integer. + */ +#define DDRC_DERATEEN_SHADOW_rc_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT)) & DDRC_DERATEEN_SHADOW_rc_derate_value_MASK) +/*! @} */ + +/*! @name DERATEINT_SHADOW - [SHADOW] Temperature Derate Interval Register */ +/*! @{ */ + +#define DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK (0xFFFFFFFFU) +#define DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT (0U) +/*! mr4_read_interval - Interval between two MR4 reads, used to derate the timing parameters. + * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to + * zero. Unit: DFI clock cycle. + */ +#define DDRC_DERATEINT_SHADOW_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK) +/*! @} */ + +/*! @name RFSHCTL0_SHADOW - [SHADOW] Refresh Control Register 0 */ +/*! @{ */ + +#define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK (0x4U) +#define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT (2U) +/*! per_bank_refresh - - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + * traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should + * be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support + * LPDDR2/LPDDR3/LPDDR4 + */ +#define DDRC_RFSHCTL0_SHADOW_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK) + +#define DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK (0x1F0U) +#define DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT (4U) +/*! refresh_burst - The programmed value + 1 is the number of refresh timeouts that is allowed to + * accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to + * perform a refresh is a one-time penalty that must be paid for each group of refreshes. + * Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. + * Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases + * the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2 + * refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of + * DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not + * per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh + * feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X + * mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care + * must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated + * due to a PHY-initiated update occurring shortly before a refresh burst was due. In this + * situation, the refresh burst will be delayed until the PHY-initiated update is complete. + */ +#define DDRC_RFSHCTL0_SHADOW_refresh_burst(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK) + +#define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK (0x1F000U) +#define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT (12U) +/*! refresh_to_x32 - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, + * but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be + * performed. A speculative refresh is a refresh performed at a time when refresh would be + * useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time + * determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since + * the last refresh, then a speculative refresh is performed. Speculative refreshes continues + * successively until there are no refreshes pending or until new reads or writes are issued to the + * DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks. + */ +#define DDRC_RFSHCTL0_SHADOW_refresh_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK) + +#define DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK (0xF00000U) +#define DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT (20U) +/*! refresh_margin - Threshold value in number of DFI clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this threshold is reached. It is + * recommended that this not be changed from the default value, currently shown as 0x2. It must + * always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, + * internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled + * (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to + * RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks. + */ +#define DDRC_RFSHCTL0_SHADOW_refresh_margin(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK) +/*! @} */ + +/*! @name RFSHTMG_SHADOW - [SHADOW] Refresh Timing Register */ +/*! @{ */ + +#define DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK (0x3FFU) +#define DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT (0U) +/*! t_rfc_min - tRFC (min): Minimum time from refresh to refresh or activate. When the controller is + * operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller + * is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In + * LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations + * is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is + * equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending + * on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the + * appropriate value from the spec based on the 'refresh_mode' and the device density that is used. + * Unit: Clocks. + */ +#define DDRC_RFSHTMG_SHADOW_t_rfc_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK) + +#define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK (0x8000U) +#define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT (15U) +/*! lpddr3_trefbw_en - Used only when LPDDR3 memory type is connected. Should only be changed when + * DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 + * devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW + * parameter not used - 1 - tREFBW parameter used + */ +#define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK) + +#define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK (0xFFF0000U) +#define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT (16U) +/*! t_rfc_nom_x32 - tREFI: Average time interval between refreshes per rank (Specification: 7.8us + * for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For + * LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register + * should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode, + * program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending + * on the refresh mode. The user should program the appropriate value from the spec based on the + * value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be + * greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or + * DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed + * 2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode: + * RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks. + */ +#define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK) +/*! @} */ + +/*! @name INIT3_SHADOW - [SHADOW] SDRAM Initialization Register 3 */ +/*! @{ */ + +#define DDRC_INIT3_SHADOW_emr_MASK (0xFFFFU) +#define DDRC_INIT3_SHADOW_emr_SHIFT (0U) +/*! emr - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this + * register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1 + * register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by + * the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - + * Value to write to MR2 register + */ +#define DDRC_INIT3_SHADOW_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_emr_SHIFT)) & DDRC_INIT3_SHADOW_emr_MASK) + +#define DDRC_INIT3_SHADOW_mr_MASK (0xFFFF0000U) +#define DDRC_INIT3_SHADOW_mr_SHIFT (16U) +/*! mr - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The + * DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to + * write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register + */ +#define DDRC_INIT3_SHADOW_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_mr_SHIFT)) & DDRC_INIT3_SHADOW_mr_MASK) +/*! @} */ + +/*! @name INIT4_SHADOW - [SHADOW] SDRAM Initialization Register 4 */ +/*! @{ */ + +#define DDRC_INIT4_SHADOW_emr3_MASK (0xFFFFU) +#define DDRC_INIT4_SHADOW_emr3_SHIFT (0U) +/*! emr3 - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register + * mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register + */ +#define DDRC_INIT4_SHADOW_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr3_SHIFT)) & DDRC_INIT4_SHADOW_emr3_MASK) + +#define DDRC_INIT4_SHADOW_emr2_MASK (0xFFFF0000U) +#define DDRC_INIT4_SHADOW_emr2_SHIFT (16U) +/*! emr2 - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register + * LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused + */ +#define DDRC_INIT4_SHADOW_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr2_SHIFT)) & DDRC_INIT4_SHADOW_emr2_MASK) +/*! @} */ + +/*! @name INIT6_SHADOW - [SHADOW] SDRAM Initialization Register 6 */ +/*! @{ */ + +#define DDRC_INIT6_SHADOW_mr5_MASK (0xFFFFU) +#define DDRC_INIT6_SHADOW_mr5_SHIFT (0U) +/*! mr5 - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. + */ +#define DDRC_INIT6_SHADOW_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr5_SHIFT)) & DDRC_INIT6_SHADOW_mr5_MASK) + +#define DDRC_INIT6_SHADOW_mr4_MASK (0xFFFF0000U) +#define DDRC_INIT6_SHADOW_mr4_SHIFT (16U) +/*! mr4 - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. + */ +#define DDRC_INIT6_SHADOW_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr4_SHIFT)) & DDRC_INIT6_SHADOW_mr4_MASK) +/*! @} */ + +/*! @name INIT7_SHADOW - [SHADOW] SDRAM Initialization Register 7 */ +/*! @{ */ + +#define DDRC_INIT7_SHADOW_mr6_MASK (0xFFFF0000U) +#define DDRC_INIT7_SHADOW_mr6_SHIFT (16U) +/*! mr6 - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. + */ +#define DDRC_INIT7_SHADOW_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_SHADOW_mr6_SHIFT)) & DDRC_INIT7_SHADOW_mr6_MASK) +/*! @} */ + +/*! @name DRAMTMG0_SHADOW - [SHADOW] SDRAM Timing Register 0 */ +/*! @{ */ + +#define DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK (0x3FU) +#define DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT (0U) +/*! t_ras_min - tRAS(min): Minimum time between activate and precharge to the same bank. When the + * controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding + * up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, + * program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks + */ +#define DDRC_DRAMTMG0_SHADOW_t_ras_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK) + +#define DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK (0x7F00U) +#define DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT (8U) +/*! t_ras_max - tRAS(max): Maximum time between activate and precharge to same bank. This is the + * maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. + * When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2. + * No rounding up. Unit: Multiples of 1024 clocks. + */ +#define DDRC_DRAMTMG0_SHADOW_t_ras_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK) + +#define DDRC_DRAMTMG0_SHADOW_t_faw_MASK (0x3F0000U) +#define DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT (16U) +/*! t_faw - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank + * design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller + * is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next + * integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency + * mode. Unit: Clocks + */ +#define DDRC_DRAMTMG0_SHADOW_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_faw_MASK) + +#define DDRC_DRAMTMG0_SHADOW_wr2pre_MASK (0x7F000000U) +#define DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT (24U) +/*! wr2pre - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + * + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower + * frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in + * the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. + * - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra + * cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2 + * frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller + * is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2 + * and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it + * may be necessary to adjust the value of this parameter to compensate for the extra cycle of + * latency through the LRDIMM. + */ +#define DDRC_DRAMTMG0_SHADOW_wr2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT)) & DDRC_DRAMTMG0_SHADOW_wr2pre_MASK) +/*! @} */ + +/*! @name DRAMTMG1_SHADOW - [SHADOW] SDRAM Timing Register 1 */ +/*! @{ */ + +#define DDRC_DRAMTMG1_SHADOW_t_rc_MASK (0x7FU) +#define DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT (0U) +/*! t_rc - tRC: Minimum time between activates to same bank. When the controller is operating in 1:2 + * frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit: + * Clocks. + */ +#define DDRC_DRAMTMG1_SHADOW_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_rc_MASK) + +#define DDRC_DRAMTMG1_SHADOW_rd2pre_MASK (0x3F00U) +#define DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT (8U) +/*! rd2pre - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, + * 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4) + * or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: + * LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 + * - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously, + * use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode, + * divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T + * mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. + * Unit: Clocks. + */ +#define DDRC_DRAMTMG1_SHADOW_rd2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT)) & DDRC_DRAMTMG1_SHADOW_rd2pre_MASK) + +#define DDRC_DRAMTMG1_SHADOW_t_xp_MASK (0x1F0000U) +#define DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT (16U) +/*! t_xp - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be + * programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used, + * set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program + * this to (tXP/2) and round it up to the next integer value. Units: Clocks + */ +#define DDRC_DRAMTMG1_SHADOW_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_xp_MASK) +/*! @} */ + +/*! @name DRAMTMG2_SHADOW - [SHADOW] SDRAM Timing Register 2 */ +/*! @{ */ + +#define DDRC_DRAMTMG2_SHADOW_wr2rd_MASK (0x3FU) +#define DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT (0U) +/*! wr2rd - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from + * write command to read command for same bank group. In others, minimum time from write command to + * read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and + * global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL + * = burst length. This must match the value programmed in the BL bit of the mode register to + * the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes + * directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. + * When the controller is operating in 1:2 mode, divide the value calculated using the above + * equation by 2, and round it up to next integer. + */ +#define DDRC_DRAMTMG2_SHADOW_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT)) & DDRC_DRAMTMG2_SHADOW_wr2rd_MASK) + +#define DDRC_DRAMTMG2_SHADOW_rd2wr_MASK (0x3F00U) +#define DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT (8U) +/*! rd2wr - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + * + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + * + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + + * RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. + * Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see + * the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: - + * WL = write latency - BL = burst length. This must match the value programmed in the BL bit of + * the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write + * preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to + * LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated + * tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the + * value calculated using the above equation by 2, and round it up to next integer. Note that, + * depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter + * to compensate for the extra cycle of latency through the LRDIMM. + */ +#define DDRC_DRAMTMG2_SHADOW_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT)) & DDRC_DRAMTMG2_SHADOW_rd2wr_MASK) + +#define DDRC_DRAMTMG2_SHADOW_read_latency_MASK (0x3F0000U) +#define DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT (16U) +/*! read_latency - Set to RL Time from read command to read data on SDRAM interface. This must be + * set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust + * the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When + * the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the + * above equation by 2, and round it up to next integer. This register field is not required for + * DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in + * DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks + */ +#define DDRC_DRAMTMG2_SHADOW_read_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT)) & DDRC_DRAMTMG2_SHADOW_read_latency_MASK) + +#define DDRC_DRAMTMG2_SHADOW_write_latency_MASK (0x3F000000U) +#define DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT (24U) +/*! write_latency - Set to WL Time from write command to write data on SDRAM interface. This must be + * set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if + * using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra + * cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio + * mode, divide the value calculated using the above equation by 2, and round it up to next + * integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), + * as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those + * protocols Unit: clocks + */ +#define DDRC_DRAMTMG2_SHADOW_write_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT)) & DDRC_DRAMTMG2_SHADOW_write_latency_MASK) +/*! @} */ + +/*! @name DRAMTMG3_SHADOW - [SHADOW] SDRAM Timing Register 3 */ +/*! @{ */ + +#define DDRC_DRAMTMG3_SHADOW_t_mod_MASK (0x3FFU) +#define DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT (0U) +/*! t_mod - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and + * following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. + * Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to + * next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using + * RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to + * compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip. + * Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller + * is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if + * controller is operating in 1:2 frequency ratio mode. + */ +#define DDRC_DRAMTMG3_SHADOW_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mod_MASK) + +#define DDRC_DRAMTMG3_SHADOW_t_mrd_MASK (0x3F000U) +#define DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT (12U) +/*! t_mrd - tMRD: Cycles to wait after a mode register write or read. Depending on the connected + * SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS + * command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is + * operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer + * value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. + */ +#define DDRC_DRAMTMG3_SHADOW_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrd_MASK) + +#define DDRC_DRAMTMG3_SHADOW_t_mrw_MASK (0x3FF00000U) +#define DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT (20U) +/*! t_mrw - Time to wait after a mode register write or read (MRW or MRR). Present only in designs + * configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 + * typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, + * this register is used for the time from a MRW/MRR to all other commands. When the controller + * is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and + * round it up to the next integer value. For LDPDR3, this register is used for the time from a + * MRW/MRR to a MRW/MRR. + */ +#define DDRC_DRAMTMG3_SHADOW_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrw_MASK) +/*! @} */ + +/*! @name DRAMTMG4_SHADOW - [SHADOW] SDRAM Timing Register 4 */ +/*! @{ */ + +#define DDRC_DRAMTMG4_SHADOW_t_rp_MASK (0x1FU) +#define DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT (0U) +/*! t_rp - tRP: Minimum time from precharge to activate of same bank. When the controller is + * operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is + * operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + + * 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set + * to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. + */ +#define DDRC_DRAMTMG4_SHADOW_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rp_MASK) + +#define DDRC_DRAMTMG4_SHADOW_t_rrd_MASK (0xF00U) +#define DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT (8U) +/*! t_rrd - DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank + * group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller + * is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it + * up to the next integer value. Unit: Clocks. + */ +#define DDRC_DRAMTMG4_SHADOW_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rrd_MASK) + +#define DDRC_DRAMTMG4_SHADOW_t_ccd_MASK (0xF0000U) +#define DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT (16U) +/*! t_ccd - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank + * group. Others: tCCD: This is the minimum time between two reads or two writes. When the + * controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it + * up to the next integer value. Unit: clocks. + */ +#define DDRC_DRAMTMG4_SHADOW_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_ccd_MASK) + +#define DDRC_DRAMTMG4_SHADOW_t_rcd_MASK (0x1F000000U) +#define DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT (24U) +/*! t_rcd - tRCD - tAL: Minimum time from activate to read or write command to same bank. When the + * controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round + * it up to the next integer value. Minimum value allowed for this register is 1, which implies + * minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio + * mode. Unit: Clocks. + */ +#define DDRC_DRAMTMG4_SHADOW_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rcd_MASK) +/*! @} */ + +/*! @name DRAMTMG5_SHADOW - [SHADOW] SDRAM Timing Register 5 */ +/*! @{ */ + +#define DDRC_DRAMTMG5_SHADOW_t_cke_MASK (0x1FU) +#define DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT (0U) +/*! t_cke - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - + * LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of + * tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When + * the controller is operating in 1:2 frequency ratio mode, program this to (value described + * above)/2 and round it up to the next integer value. Unit: Clocks. + */ +#define DDRC_DRAMTMG5_SHADOW_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cke_MASK) + +#define DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK (0x3F00U) +#define DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT (8U) +/*! t_ckesr - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing + * in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR + * - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity + * latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased + * by PL. When the controller is operating in 1:2 frequency ratio mode, program this to + * recommended value divided by two and round it up to next integer. + */ +#define DDRC_DRAMTMG5_SHADOW_t_ckesr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK) + +#define DDRC_DRAMTMG5_SHADOW_t_cksre_MASK (0xF0000U) +#define DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT (16U) +/*! t_cksre - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. + * Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - + * LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+ + * PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should + * be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program + * this to recommended value divided by two and round it up to next integer. + */ +#define DDRC_DRAMTMG5_SHADOW_t_cksre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksre_MASK) + +#define DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK (0xF000000U) +#define DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT (24U) +/*! t_cksrx - This is the time before Self Refresh Exit that CK is maintained as a valid clock + * before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 - + * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the + * controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by + * two and round it up to next integer. + */ +#define DDRC_DRAMTMG5_SHADOW_t_cksrx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK) +/*! @} */ + +/*! @name DRAMTMG6_SHADOW - [SHADOW] SDRAM Timing Register 6 */ +/*! @{ */ + +#define DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK (0xFU) +#define DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT (0U) +/*! t_ckcsx - This is the time before Clock Stop Exit that CK is maintained as a valid clock before + * issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop + * Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 + * When the controller is operating in 1:2 frequency ratio mode, program this to recommended value + * divided by two and round it up to next integer. This is only present for designs supporting + * mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_DRAMTMG6_SHADOW_t_ckcsx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK) + +#define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK (0xF0000U) +#define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT (16U) +/*! t_ckdpdx - This is the time before Deep Power Down Exit that CK is maintained as a valid clock + * before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR: + * 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, + * program this to recommended value divided by two and round it up to next integer. This is only + * present for designs supporting mDDR or LPDDR2 devices. + */ +#define DDRC_DRAMTMG6_SHADOW_t_ckdpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK) + +#define DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK (0xF000000U) +#define DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT (24U) +/*! t_ckdpde - This is the time after Deep Power Down Entry that CK is maintained as a valid clock. + * Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - + * LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to + * recommended value divided by two and round it up to next integer. This is only present for designs + * supporting mDDR or LPDDR2/LPDDR3 devices. + */ +#define DDRC_DRAMTMG6_SHADOW_t_ckdpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK) +/*! @} */ + +/*! @name DRAMTMG7_SHADOW - [SHADOW] SDRAM Timing Register 7 */ +/*! @{ */ + +#define DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK (0xFU) +#define DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT (0U) +/*! t_ckpdx - This is the time before Power Down Exit that CK is maintained as a valid clock before + * issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 - + * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the + * same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode, + * program this to recommended value divided by two and round it up to next integer. This is only + * present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_DRAMTMG7_SHADOW_t_ckpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK) + +#define DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK (0xF00U) +#define DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT (8U) +/*! t_ckpde - This is the time after Power Down Entry that CK is maintained as a valid clock. + * Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 + * - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as + * DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this + * to recommended value divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_DRAMTMG7_SHADOW_t_ckpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK) +/*! @} */ + +/*! @name DRAMTMG8_SHADOW - [SHADOW] SDRAM Timing Register 8 */ +/*! @{ */ + +#define DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK (0x7FU) +#define DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT (0U) +/*! t_xs_x32 - tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is + * operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round + * up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and + * DDR4 SDRAMs. + */ +#define DDRC_DRAMTMG8_SHADOW_t_xs_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK) + +#define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK (0x7F00U) +#define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT (8U) +/*! t_xs_dll_x32 - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller + * is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and + * round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and + * DDR4 SDRAMs. + */ +#define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK) + +#define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK (0x7F0000U) +#define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT (16U) +/*! t_xs_abort_x32 - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self + * Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the + * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Ensure this is less than or equal to t_xs_x32. + */ +#define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK) + +#define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK (0x7F000000U) +#define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT (24U) +/*! t_xs_fast_x32 - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown + * mode). When the controller is operating in 1:2 frequency ratio mode, program this to the + * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: + * This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to + * t_xs_x32. + */ +#define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK) +/*! @} */ + +/*! @name DRAMTMG9_SHADOW - [SHADOW] SDRAM Timing Register 9 */ +/*! @{ */ + +#define DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK (0x3FU) +#define DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT (0U) +/*! wr2rd_s - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different + * bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and + * global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where: + * - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value + * programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read + * command delay for different bank group. This comes directly from the SDRAM specification. When + * the controller is operating in 1:2 mode, divide the value calculated using the above equation + * by 2, and round it up to next integer. + */ +#define DDRC_DRAMTMG9_SHADOW_wr2rd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK) + +#define DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK (0xF00U) +#define DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT (8U) +/*! t_rrd_s - tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank + * group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2) + * and round it up to the next integer value. Present only in designs configured to support DDR4. + * Unit: Clocks. + */ +#define DDRC_DRAMTMG9_SHADOW_t_rrd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK) + +#define DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK (0x70000U) +#define DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT (16U) +/*! t_ccd_s - tCCD_S: This is the minimum time between two reads or two writes for different bank + * group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When + * the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round + * it up to the next integer value. Present only in designs configured to support DDR4. Unit: + * clocks. + */ +#define DDRC_DRAMTMG9_SHADOW_t_ccd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK) + +#define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK (0x40000000U) +#define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT (30U) +/*! ddr4_wr_preamble - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 + */ +#define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK) +/*! @} */ + +/*! @name DRAMTMG10_SHADOW - [SHADOW] SDRAM Timing Register 10 */ +/*! @{ */ + +#define DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK (0x3U) +#define DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT (0U) +/*! t_gear_hold - Geardown hold time. Minimum value of this register is 1. Zero is invalid. For + * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in + * 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer + * value. Unit: Clocks + */ +#define DDRC_DRAMTMG10_SHADOW_t_gear_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK) + +#define DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK (0xCU) +#define DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT (2U) +/*! t_gear_setup - Geardown setup time. Minimum value of this register is 1. Zero is invalid. For + * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in + * 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer + * value. Unit: Clocks + */ +#define DDRC_DRAMTMG10_SHADOW_t_gear_setup(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK) + +#define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK (0x1F00U) +#define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT (8U) +/*! t_cmd_gear - Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is + * defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for + * this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2) + * and round it up to the next integer value. Unit: Clocks + */ +#define DDRC_DRAMTMG10_SHADOW_t_cmd_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK) + +#define DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK (0x1F0000U) +#define DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT (16U) +/*! t_sync_gear - Indicates the time between MRS command and the sync pulse time. This must be even + * number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK + * tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28 + * When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up + * to the next integer value. Unit: Clocks + */ +#define DDRC_DRAMTMG10_SHADOW_t_sync_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK) +/*! @} */ + +/*! @name DRAMTMG11_SHADOW - [SHADOW] SDRAM Timing Register 11 */ +/*! @{ */ + +#define DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK (0x1FU) +#define DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT (0U) +/*! t_ckmpe - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs + * configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio + * mode, divide the value calculated using the above equation by 2, and round it up to next + * integer. + */ +#define DDRC_DRAMTMG11_SHADOW_t_ckmpe(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK) + +#define DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK (0x300U) +#define DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT (8U) +/*! t_mpx_s - tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2 + * frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: Clocks. + */ +#define DDRC_DRAMTMG11_SHADOW_t_mpx_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK) + +#define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK (0x1F0000U) +#define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT (16U) +/*! t_mpx_lh - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the + * controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present + * only in designs configured to support DDR4. Unit: clocks. + */ +#define DDRC_DRAMTMG11_SHADOW_t_mpx_lh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK) + +#define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK (0x7F000000U) +#define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT (24U) +/*! post_mpsm_gap_x32 - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. + * When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and + * round it up to the next integer value. Present only in designs configured to support DDR4. + * Unit: Multiples of 32 clocks. + */ +#define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK) +/*! @} */ + +/*! @name DRAMTMG12_SHADOW - [SHADOW] SDRAM Timing Register 12 */ +/*! @{ */ + +#define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK (0x1FU) +#define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT (0U) +/*! t_mrd_pda - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the + * controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up + * to the next integer value. + */ +#define DDRC_DRAMTMG12_SHADOW_t_mrd_pda(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK) + +#define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK (0xF00U) +#define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT (8U) +/*! t_ckehcmd - tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is + * operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next + * integer value. + */ +#define DDRC_DRAMTMG12_SHADOW_t_ckehcmd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK) + +#define DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK (0x30000U) +#define DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT (16U) +/*! t_cmdcke - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE + * or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to + * (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value. + */ +#define DDRC_DRAMTMG12_SHADOW_t_cmdcke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK) +/*! @} */ + +/*! @name DRAMTMG13_SHADOW - [SHADOW] SDRAM Timing Register 13 */ +/*! @{ */ + +#define DDRC_DRAMTMG13_SHADOW_t_ppd_MASK (0x7U) +#define DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT (0U) +/*! t_ppd - LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the + * controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to + * the next integer value. Unit: Clocks. + */ +#define DDRC_DRAMTMG13_SHADOW_t_ppd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ppd_MASK) + +#define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK (0x3F0000U) +#define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT (16U) +/*! t_ccd_mw - LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write + * command for same bank. When the controller is operating in 1:2 frequency ratio mode, program + * this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks. + */ +#define DDRC_DRAMTMG13_SHADOW_t_ccd_mw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK) + +#define DDRC_DRAMTMG13_SHADOW_odtloff_MASK (0x7F000000U) +#define DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT (24U) +/*! odtloff - LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When + * the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round + * it up to the next integer value. Unit: Clocks. + */ +#define DDRC_DRAMTMG13_SHADOW_odtloff(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT)) & DDRC_DRAMTMG13_SHADOW_odtloff_MASK) +/*! @} */ + +/*! @name DRAMTMG14_SHADOW - [SHADOW] SDRAM Timing Register 14 */ +/*! @{ */ + +#define DDRC_DRAMTMG14_SHADOW_t_xsr_MASK (0xFFFU) +#define DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT (0U) +/*! t_xsr - tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2 + * frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. + * Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode. + */ +#define DDRC_DRAMTMG14_SHADOW_t_xsr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT)) & DDRC_DRAMTMG14_SHADOW_t_xsr_MASK) +/*! @} */ + +/*! @name DRAMTMG15_SHADOW - [SHADOW] SDRAM Timing Register 15 */ +/*! @{ */ + +#define DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK (0xFFU) +#define DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT (0U) +/*! t_stab_x32 - tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 + * RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the + * clock must be stable for a time specified by tSTAB - in the case of input clock frequency + * change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for + * DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to + * recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock + * cycles. + */ +#define DDRC_DRAMTMG15_SHADOW_t_stab_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK) + +#define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK (0x80000000U) +#define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT (31U) +/*! en_dfi_lp_t_stab - - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is + * stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when + * exiting DFI LP + */ +#define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK) +/*! @} */ + +/*! @name ZQCTL0_SHADOW - [SHADOW] ZQ Control Register 0 */ +/*! @{ */ + +#define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK (0x3FFU) +#define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT (0U) +/*! t_zq_short_nop - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles + * of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. + * When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and + * round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or + * LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_ZQCTL0_SHADOW_t_zq_short_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK) + +#define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK (0x7FF0000U) +#define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT (16U) +/*! t_zq_long_nop - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI + * clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is + * issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program + * this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to + * tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it + * up to the next integer value. This is only present for designs supporting DDR3/DDR4 or + * LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_ZQCTL0_SHADOW_t_zq_long_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK) + +#define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK (0x10000000U) +#define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT (28U) +/*! dis_mpsmx_zqcl - - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only + * applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL command at Maximum Power Saving + * Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting + * DDR4 devices. Note: Do not issue ZQCL command at Maximum Power Save Mode exit if the + * DDRC_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after + * exiting MPSM mode. + */ +#define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK) + +#define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK (0x20000000U) +#define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT (29U) +/*! zq_resistor_shared - - 1 - Denotes that ZQ resistor is shared between ranks. Means + * ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. - 0 - + * ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or + * LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_ZQCTL0_SHADOW_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK) + +#define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK (0x40000000U) +#define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT (30U) +/*! dis_srx_zqcl - - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at + * Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - + * Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only + * applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for + * designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK) + +#define DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK (0x80000000U) +#define DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT (31U) +/*! dis_auto_zq - - 1 - Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register + * DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. - 0 - + * Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024. + * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + */ +#define DDRC_ZQCTL0_SHADOW_dis_auto_zq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK) +/*! @} */ + +/*! @name DFITMG0_SHADOW - [SHADOW] DFI Timing Register 0 */ +/*! @{ */ + +#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK (0x3FU) +#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT (0U) +/*! dfi_tphy_wrlat - Write latency Number of clocks from the write command to write data enable + * (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY + * specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be + * necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for + * the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY + * clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr. + */ +#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK) + +#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK (0x3F00U) +#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT (8U) +/*! dfi_tphy_wrdata - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to + * when the associated write data is driven on the dfi_wrdata signal. This corresponds to the + * DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max + * supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on + * DFITMG0.dfi_wrdata_use_sdr. + */ +#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK) + +#define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK (0x8000U) +#define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT (15U) +/*! dfi_wrdata_use_sdr - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using + * HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat + * is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in + * DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of + * HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification + * for correct value. + */ +#define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK) + +#define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK (0x7F0000U) +#define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT (16U) +/*! dfi_t_rddata_en - Time from the assertion of a read command on the DFI interface to the + * assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds + * to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it + * may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to + * compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or + * DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr. + */ +#define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK) + +#define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK (0x800000U) +#define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT (23U) +/*! dfi_rddata_use_sdr - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated + * using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in + * DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI + * clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct + * value. + */ +#define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK) + +#define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK (0x1F000000U) +#define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT (24U) +/*! dfi_t_ctrl_delay - Specifies the number of DFI clock cycles after an assertion or de-assertion + * of the DFI control signals that the control signals at the PHY-DRAM interface reflect the + * assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing + * parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it + * is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms + * of DFI clock. + */ +#define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK) +/*! @} */ + +/*! @name DFITMG1_SHADOW - [SHADOW] DFI Timing Register 1 */ +/*! @{ */ + +#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK (0x1FU) +#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT (0U) +/*! dfi_t_dram_clk_enable - Specifies the number of DFI clock cycles from the de-assertion of the + * dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the + * DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not + * phase aligned, this timing parameter should be rounded up to the next integer value. + */ +#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK) + +#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK (0x1F00U) +#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT (8U) +/*! dfi_t_dram_clk_disable - Specifies the number of DFI clock cycles from the assertion of the + * dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM + * boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, + * this timing parameter should be rounded up to the next integer value. + */ +#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK) + +#define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK (0x1F0000U) +#define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT (16U) +/*! dfi_t_wrdata_delay - Specifies the number of DFI clock cycles between when the dfi_wrdata_en + * signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. + * This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for + * correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI + * 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be + * programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 + * and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: + * Clocks + */ +#define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK) + +#define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK (0x3000000U) +#define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT (24U) +/*! dfi_t_parin_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. + */ +#define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK) + +#define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK (0xF0000000U) +#define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT (28U) +/*! dfi_t_cmd_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used for CAL mode, should be + * set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY + * can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 + */ +#define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK) +/*! @} */ + +/*! @name DFITMG2_SHADOW - [SHADOW] DFI Timing Register 2 */ +/*! @{ */ + +#define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK (0x3FU) +#define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT (0U) +/*! dfi_tphy_wrcslat - Number of DFI PHY clock cycles between when a write command is sent on the + * DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds + * to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. + */ +#define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT)) & DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK) + +#define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK (0x7F00U) +#define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT (8U) +/*! dfi_tphy_rdcslat - Number of DFI PHY clock cycles between when a read command is sent on the DFI + * control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds + * to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. + */ +#define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT)) & DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK) +/*! @} */ + +/*! @name DFITMG3_SHADOW - [SHADOW] DFI Timing Register 3 */ +/*! @{ */ + +#define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK (0x1FU) +#define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT (0U) +/*! dfi_t_geardown_delay - The delay from dfi_geardown_en assertion to the time of the PHY being + * ready to receive commands. Refer to PHY specification for correct value. When the controller is + * operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to + * the next integer value. Unit: Clocks + */ +#define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT)) & DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK) +/*! @} */ + +/*! @name ODTCFG_SHADOW - [SHADOW] ODT Configuration Register */ +/*! @{ */ + +#define DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK (0x7CU) +#define DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT (2U) +/*! rd_odt_delay - The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT + * values associated with that command. ODT setting must remain constant for the entire time that + * DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 + * (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL - + * CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL + * mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write + * preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does + * not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) + */ +#define DDRC_ODTCFG_SHADOW_rd_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK) + +#define DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK (0xF00U) +#define DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT (8U) +/*! rd_odt_hold - DFI PHY clock cycles to hold ODT for a read command. The minimum supported value + * is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not + * DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK + * write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - + * RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK) + */ +#define DDRC_ODTCFG_SHADOW_rd_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK) + +#define DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK (0x1F0000U) +#define DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT (16U) +/*! wr_odt_delay - The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant for the entire time that + * DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + + * AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT + * for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: + * - WL - 1 - RU(tODTon(max)/tCK)) + */ +#define DDRC_ODTCFG_SHADOW_wr_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK) + +#define DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK (0xF000000U) +#define DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT (24U) +/*! wr_odt_hold - DFI PHY clock cycles to hold ODT for a write command. The minimum supported value + * is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066) + * - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: + * 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) + * CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) + */ +#define DDRC_ODTCFG_SHADOW_wr_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DDRC_Register_Masks */ + + +/* DDRC - Peripheral instance base addresses */ +/** Peripheral DDRC base address */ +#define DDRC_BASE (0x3D400000u) +/** Peripheral DDRC base pointer */ +#define DDRC ((DDRC_Type *)DDRC_BASE) +/** Array initializer of DDRC peripheral base addresses */ +#define DDRC_BASE_ADDRS { DDRC_BASE } +/** Array initializer of DDRC peripheral base pointers */ +#define DDRC_BASE_PTRS { DDRC } + +/*! + * @} + */ /* end of group DDRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DEC400D Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DEC400D_Peripheral_Access_Layer DEC400D Peripheral Access Layer + * @{ + */ + +/** DEC400D - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[36]; + __I uint32_t GCCHIPREV; /**< Revision ID, offset: 0x24 */ + __I uint32_t GCCHIPDATE; /**< Release Date, offset: 0x28 */ + uint8_t RESERVED_1[108]; + __I uint32_t GCREGHICHIPPATCHREV; /**< Patch Revision, offset: 0x98 */ + uint8_t RESERVED_2[12]; + __I uint32_t GCPRODUCTID; /**< Product ID, offset: 0xA8 */ + uint8_t RESERVED_3[1876]; + __IO uint32_t GCREGAHBDECREADCONFIG[32]; /**< Decode Read Configuration, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_4[128]; + __IO uint32_t GCREGAHBDECREADBUFFERBASE[32]; /**< Decode Read Buffer Base, array offset: 0x900, array step: 0x4 */ + __IO uint32_t GCREGAHBDECREADCACHEBASE[32]; /**< Decode Read Cache Base, array offset: 0x980, array step: 0x4 */ + uint8_t RESERVED_5[256]; + __IO uint32_t GCREGAHBDECCONTROL; /**< Dec400D Control, offset: 0xB00 */ + __I uint32_t GCREGAHBDECINTRACKNOWLEDGE; /**< Interrupt Acknowledge, offset: 0xB04 */ + __IO uint32_t GCREGAHBDECINTRENBL; /**< Interrupt Enable, offset: 0xB08 */ + __I uint32_t GCREGAHBDECTILESTATUSDEBUG; /**< Tile Status Module Debug, offset: 0xB0C */ + uint8_t RESERVED_6[4]; + __I uint32_t GCREGAHBDECDECODERDEBUG; /**< Decompression Module Debug, offset: 0xB14 */ + __I uint32_t GCREGAHBDECTOTALREADSIN; /**< Total Reads In, offset: 0xB18 */ + uint8_t RESERVED_7[4]; + __I uint32_t GCREGAHBDECTOTALREADBURSTSIN; /**< Total Read Data Count, offset: 0xB20 */ + uint8_t RESERVED_8[4]; + __I uint32_t GCREGAHBDECTOTALREADREQIN; /**< Total Read Request In, offset: 0xB28 */ + uint8_t RESERVED_9[4]; + __I uint32_t GCREGAHBDECTOTALREADLASTSIN; /**< Total Input Read Last Number, offset: 0xB30 */ + uint8_t RESERVED_10[4]; + __I uint32_t GCREGAHBDECTOTALREADSOUT; /**< Total Reads Out, offset: 0xB38 */ + uint8_t RESERVED_11[4]; + __I uint32_t GCREGAHBDECTOTALREADBURSTSOUT; /**< Total Read Bursts Out, offset: 0xB40 */ + uint8_t RESERVED_12[4]; + __I uint32_t GCREGAHBDECTOTALREADREQOUT; /**< Total Read Request Out, offset: 0xB48 */ + uint8_t RESERVED_13[4]; + __I uint32_t GCREGAHBDECTOTALREADLASTSOUT; /**< Total Read Last Out, offset: 0xB50 */ + uint8_t RESERVED_14[4]; + __I uint32_t GCREGAHBDECDEBUG0; /**< Debug Register 0, offset: 0xB58 */ + __I uint32_t GCREGAHBDECDEBUG1; /**< Debug Register 1, offset: 0xB5C */ + __I uint32_t GCREGAHBDECDEBUG2; /**< Debug register 2, offset: 0xB60 */ + __I uint32_t GCREGAHBDECDEBUG3; /**< Debug Register 3, offset: 0xB64 */ + __IO uint32_t GCREGAHBDECCONTROLEX; /**< GCREGAHBDECCONTROLEX, offset: 0xB68 */ + __IO uint32_t GCREGAHBDECSTATECOMMIT; /**< GCREGAHBDECSTATECOMMIT, offset: 0xB6C */ + __I uint32_t GCREGAHBDECSTATELOCK; /**< GCREGAHBDECSTATELOCK, offset: 0xB70 */ + uint8_t RESERVED_15[140]; + __IO uint32_t GCREGAHBDECREADEXCONFIG[32]; /**< Decode Read Extra Configuration, array offset: 0xC00, array step: 0x4 */ + __IO uint32_t GCREGAHBDECREADSTRIDE[32]; /**< Decoder Read Stride, array offset: 0xC80, array step: 0x4 */ + uint8_t RESERVED_16[256]; + __IO uint32_t GCREGAHBDECREADBUFFEREND[32]; /**< Decoder Read Buffer End, array offset: 0xE00, array step: 0x4 */ +} DEC400D_Type; + +/* ---------------------------------------------------------------------------- + -- DEC400D Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DEC400D_Register_Masks DEC400D Register Masks + * @{ + */ + +/*! @name GCCHIPREV - Revision ID */ +/*! @{ */ + +#define DEC400D_GCCHIPREV_GCCHIPREV_MASK (0xFFFFFFFFU) +#define DEC400D_GCCHIPREV_GCCHIPREV_SHIFT (0U) +/*! GCCHIPREV - Revision ID + */ +#define DEC400D_GCCHIPREV_GCCHIPREV(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCCHIPREV_GCCHIPREV_SHIFT)) & DEC400D_GCCHIPREV_GCCHIPREV_MASK) +/*! @} */ + +/*! @name GCCHIPDATE - Release Date */ +/*! @{ */ + +#define DEC400D_GCCHIPDATE_GCCHIPDATE_MASK (0xFFFFFFFFU) +#define DEC400D_GCCHIPDATE_GCCHIPDATE_SHIFT (0U) +/*! GCCHIPDATE - Date + */ +#define DEC400D_GCCHIPDATE_GCCHIPDATE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCCHIPDATE_GCCHIPDATE_SHIFT)) & DEC400D_GCCHIPDATE_GCCHIPDATE_MASK) +/*! @} */ + +/*! @name GCREGHICHIPPATCHREV - Patch Revision */ +/*! @{ */ + +#define DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV_SHIFT (0U) +/*! GCREGHICHIPPATCHREV - Product ID + */ +#define DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV_SHIFT)) & DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV_MASK) +/*! @} */ + +/*! @name GCPRODUCTID - Product ID */ +/*! @{ */ + +#define DEC400D_GCPRODUCTID_GCPRODUCTID_MASK (0xFFFFFFFFU) +#define DEC400D_GCPRODUCTID_GCPRODUCTID_SHIFT (0U) +/*! GCPRODUCTID - Product ID + */ +#define DEC400D_GCPRODUCTID_GCPRODUCTID(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCPRODUCTID_GCPRODUCTID_SHIFT)) & DEC400D_GCPRODUCTID_GCPRODUCTID_MASK) +/*! @} */ + +/*! @name GCREGAHBDECREADCONFIG - Decode Read Configuration */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE_MASK (0x1U) +#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE_SHIFT (0U) +/*! COMPRESSION_ENABLE - Compression Enable + * 0b0..Disable + * 0b1..Enable + */ +#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE_MASK) + +#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT_MASK (0xF8U) +#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT_SHIFT (3U) +/*! COMPRESSION_FORMAT - Compression Format + * 0b00000..ARGB8 + */ +#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT_MASK) + +#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE_MASK (0x30000U) +#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE_SHIFT (16U) +/*! COMPRESSION_ALIGN_MODE - Compression Align Mode + * 0b00..ALIGN1_BYTE + * 0b01..ALIGN16_BYTE + * 0b10..ALIGN32_BYTE + * 0b11..ALIGN64_BYTE + */ +#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE_MASK) + +#define DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE_MASK (0x1C00000U) +#define DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE_SHIFT (22U) +/*! TILE_ALIGN_MODE - Tile Align Mode + * 0b000..TILE1_ALIGN + * 0b001..TILE2_ALIGN + * 0b010..TILE4_ALIGN + * 0b011..CBSR_ALIGN + */ +#define DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE_MASK) + +#define DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE_MASK (0x3E000000U) +#define DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE_SHIFT (25U) +/*! TILE_MODE - Tile Mode + * 0b00000..TILE8X8_XMAJOR + * 0b00001..TILE8X8_YMAJOR + * 0b00010..TILE16X4 + * 0b00011..TILE8X4 + * 0b00100..TILE4X8 + * 0b00101..TILE4X4 + * 0b00110..RASTER16X4 + * 0b00111..TILE64X4 + * 0b01000..TILE32X4 + * 0b01001..RASTER256X1 + * 0b01010..RASTER128X1 + * 0b01011..RASTER64X4 + * 0b01100..RASTER256X2 + * 0b01101..RASTER128X2 + * 0b01110..RASTER128X4 + * 0b01111..RASTER64X1 + */ +#define DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE_MASK) +/*! @} */ + +/* The count of DEC400D_GCREGAHBDECREADCONFIG */ +#define DEC400D_GCREGAHBDECREADCONFIG_COUNT (32U) + +/*! @name GCREGAHBDECREADBUFFERBASE - Decode Read Buffer Base */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS_SHIFT (0U) +/*! BUFFER_ADDRESS - Base address for pixel buffer for read ID. + */ +#define DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS_SHIFT)) & DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS_MASK) +/*! @} */ + +/* The count of DEC400D_GCREGAHBDECREADBUFFERBASE */ +#define DEC400D_GCREGAHBDECREADBUFFERBASE_COUNT (32U) + +/*! @name GCREGAHBDECREADCACHEBASE - Decode Read Cache Base */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS_SHIFT (0U) +/*! CACHE_ADDRESS - Base address for tile status buffer for read ID. + */ +#define DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS_SHIFT)) & DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS_MASK) +/*! @} */ + +/* The count of DEC400D_GCREGAHBDECREADCACHEBASE */ +#define DEC400D_GCREGAHBDECREADCACHEBASE_COUNT (32U) + +/*! @name GCREGAHBDECCONTROL - Dec400D Control */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECCONTROL_FLUSH_MASK (0x1U) +#define DEC400D_GCREGAHBDECCONTROL_FLUSH_SHIFT (0U) +/*! FLUSH - Flush tile status cache. + * 0b0..Disable + * 0b1..Enable + */ +#define DEC400D_GCREGAHBDECCONTROL_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_FLUSH_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_FLUSH_MASK) + +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION_MASK (0x2U) +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION_SHIFT (1U) +/*! DISABLE_COMPRESSION - Bypass compression for all streams. + * 0b0..Disable + * 0b1..Enable + */ +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION_MASK) + +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING_MASK (0x4U) +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT (2U) +/*! DISABLE_RAM_CLOCK_GATING - Disable clock gating for RAMs. + * 0b0..Disable + * 0b1..Enable + */ +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING_MASK) + +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS_MASK (0x8U) +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT (3U) +/*! DISABLE_DEBUG_REGISTERS - Disable debug registers. + * 0b0..Disable + * 0b1..Enable + */ +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS_MASK) + +#define DEC400D_GCREGAHBDECCONTROL_SOFT_RESET_MASK (0x10U) +#define DEC400D_GCREGAHBDECCONTROL_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft reset the Dec400D. + * 0b0..Disable + * 0b1..Enable + */ +#define DEC400D_GCREGAHBDECCONTROL_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_SOFT_RESET_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_SOFT_RESET_MASK) + +#define DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID_MASK (0x7C0U) +#define DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID_SHIFT (6U) +/*! TILE_STATUS_READ_ID - Tile status cache's AXI read ID. + */ +#define DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID_MASK) + +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH_MASK (0x10000U) +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH_SHIFT (16U) +/*! DISABLE_HW_FLUSH - Tile status cache flush through frame end pin is disabled. + * 0b0..Disable + * 0b1..Enable + */ +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH_MASK) + +#define DEC400D_GCREGAHBDECCONTROL_CLK_DIS_MASK (0x20000U) +#define DEC400D_GCREGAHBDECCONTROL_CLK_DIS_SHIFT (17U) +/*! CLK_DIS - Disable clock. + * 0b0..Disable + * 0b1..Enable + */ +#define DEC400D_GCREGAHBDECCONTROL_CLK_DIS(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_CLK_DIS_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_CLK_DIS_MASK) + +#define DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID_MASK (0xFC0000U) +#define DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID_SHIFT (18U) +/*! SW_FLUSH_ID - ID of tile status flush. + */ +#define DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID_MASK) + +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING_MASK (0x40000000U) +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING_SHIFT (30U) +/*! DISABLE_MODULE_CLOCK_GATING - Disable clock gating for sub modules + * 0b0..Disable + * 0b1..Enable + */ +#define DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING_MASK) +/*! @} */ + +/*! @name GCREGAHBDECINTRACKNOWLEDGE - Interrupt Acknowledge */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC_SHIFT (0U) +/*! INTR_VEC - Interrupt vector + */ +#define DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC_SHIFT)) & DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC_MASK) +/*! @} */ + +/*! @name GCREGAHBDECINTRENBL - Interrupt Enable */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC_SHIFT (0U) +/*! INTR_ENBL_VEC - Interrupt enable vector + */ +#define DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC_SHIFT)) & DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC_MASK) +/*! @} */ + +/*! @name GCREGAHBDECTILESTATUSDEBUG - Tile Status Module Debug */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG_SHIFT (0U) +/*! TILE_DEBUG - Debug + */ +#define DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG_SHIFT)) & DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG_MASK) +/*! @} */ + +/*! @name GCREGAHBDECDECODERDEBUG - Decompression Module Debug */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG_SHIFT (0U) +/*! DEC_DEBUG - Debug + */ +#define DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG_SHIFT)) & DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG_MASK) +/*! @} */ + +/*! @name GCREGAHBDECTOTALREADSIN - Total Reads In */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT_SHIFT (0U) +/*! RDIN_COUNT - Count + */ +#define DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT_MASK) +/*! @} */ + +/*! @name GCREGAHBDECTOTALREADBURSTSIN - Total Read Data Count */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT_SHIFT (0U) +/*! RDIN_BURST_COUNT - Count + */ +#define DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT_MASK) +/*! @} */ + +/*! @name GCREGAHBDECTOTALREADREQIN - Total Read Request In */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT_SHIFT (0U) +/*! RDIN_REQ_COUNT - Count + */ +#define DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT_MASK) +/*! @} */ + +/*! @name GCREGAHBDECTOTALREADLASTSIN - Total Input Read Last Number */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT_SHIFT (0U) +/*! RDIN_LAST_COUNT - Count + */ +#define DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT_MASK) +/*! @} */ + +/*! @name GCREGAHBDECTOTALREADSOUT - Total Reads Out */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT_SHIFT (0U) +/*! RDOUT_COUNT - Count + */ +#define DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT_MASK) +/*! @} */ + +/*! @name GCREGAHBDECTOTALREADBURSTSOUT - Total Read Bursts Out */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT_SHIFT (0U) +/*! RDOUT_BURST_COUNT - Count + */ +#define DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT_MASK) +/*! @} */ + +/*! @name GCREGAHBDECTOTALREADREQOUT - Total Read Request Out */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT_SHIFT (0U) +/*! RDOUT_REQ_COUNT - Count + */ +#define DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT_MASK) +/*! @} */ + +/*! @name GCREGAHBDECTOTALREADLASTSOUT - Total Read Last Out */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT_SHIFT (0U) +/*! RDOUT_LAST_COUNT - Count + */ +#define DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT_MASK) +/*! @} */ + +/*! @name GCREGAHBDECDEBUG0 - Debug Register 0 */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECDEBUG0_DEBUG0_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECDEBUG0_DEBUG0_SHIFT (0U) +/*! DEBUG0 - Debug register 0 + */ +#define DEC400D_GCREGAHBDECDEBUG0_DEBUG0(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDEBUG0_DEBUG0_SHIFT)) & DEC400D_GCREGAHBDECDEBUG0_DEBUG0_MASK) +/*! @} */ + +/*! @name GCREGAHBDECDEBUG1 - Debug Register 1 */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECDEBUG1_DEBUG1_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECDEBUG1_DEBUG1_SHIFT (0U) +/*! DEBUG1 - Debug 1 + */ +#define DEC400D_GCREGAHBDECDEBUG1_DEBUG1(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDEBUG1_DEBUG1_SHIFT)) & DEC400D_GCREGAHBDECDEBUG1_DEBUG1_MASK) +/*! @} */ + +/*! @name GCREGAHBDECDEBUG2 - Debug register 2 */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECDEBUG2_DEBUG2_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECDEBUG2_DEBUG2_SHIFT (0U) +/*! DEBUG2 - Debug 2 + */ +#define DEC400D_GCREGAHBDECDEBUG2_DEBUG2(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDEBUG2_DEBUG2_SHIFT)) & DEC400D_GCREGAHBDECDEBUG2_DEBUG2_MASK) +/*! @} */ + +/*! @name GCREGAHBDECDEBUG3 - Debug Register 3 */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECDEBUG3_DEBUG3_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECDEBUG3_DEBUG3_SHIFT (0U) +/*! DEBUG3 - Debug 3 + */ +#define DEC400D_GCREGAHBDECDEBUG3_DEBUG3(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDEBUG3_DEBUG3_SHIFT)) & DEC400D_GCREGAHBDECDEBUG3_DEBUG3_MASK) +/*! @} */ + +/*! @name GCREGAHBDECCONTROLEX - GCREGAHBDECCONTROLEX */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX_SHIFT (0U) +/*! GCREGAHBDECCONTROLEX - GCREGAHBDECCONTROLEX + */ +#define DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX_SHIFT)) & DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX_MASK) +/*! @} */ + +/*! @name GCREGAHBDECSTATECOMMIT - GCREGAHBDECSTATECOMMIT */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT_SHIFT (0U) +/*! GCREGAHBDECSTATECOMMIT - GCREGAHBDECSTATECOMMIT + */ +#define DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT_SHIFT)) & DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT_MASK) +/*! @} */ + +/*! @name GCREGAHBDECSTATELOCK - GCREGAHBDECSTATELOCK */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK_SHIFT (0U) +/*! GCREGAHBDECSTATELOCK - GCREGAHBDECSTATELOCK + */ +#define DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK_SHIFT)) & DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK_MASK) +/*! @} */ + +/*! @name GCREGAHBDECREADEXCONFIG - Decode Read Extra Configuration */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH_MASK (0xFFF8U) +#define DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH_SHIFT (3U) +/*! CBSR_WIDTH - CBSR width + */ +#define DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH_MASK) + +#define DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH_MASK (0x70000U) +#define DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH_SHIFT (16U) +/*! BIT_DEPTH - Bit depth + * 0b000..8 bit + * 0b001..10 bit + * 0b010..12 bit + * 0b011..16 bit + */ +#define DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH_MASK) + +#define DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y_MASK (0x80000U) +#define DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y_SHIFT (19U) +/*! TILE_Y - Tile Y + * 0b0..Disable + * 0b1..Enable + */ +#define DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y_MASK) + +#define DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE_MASK (0x1F00000U) +#define DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE_SHIFT (20U) +/*! STREAM_MODE - Stream mode + * 0b00000..Default + * 0b00001..ISA_STREAM0 + * 0b00010..ISA_STREAM1 + * 0b00011..ISA_STREAM2 + * 0b00100..ISA_STREAM3 + * 0b00101..TNR_STREAM_Y + * 0b00110..TNR_STREAM_UV + * 0b00111..GDC_STREAM_Y + * 0b01000..GDC_STREAM_U + * 0b01001..GDC_STREAM_V + * 0b01010..VPU_SRC_Y + * 0b01011..VPR_SRC_UV + * 0b01100..VPU_REF_Y + * 0b01101..VPU_REF_UV + * 0b01110..XYZ_STREAM_AY + * 0b01111..XYZ_STREAM_AU + * 0b10000..XYZ_STREAM_AV + * 0b10001..XYZ_STREAM_BY + * 0b10010..XYZ_STREAM_BU + * 0b10011..XYZ_STREAM_BV + */ +#define DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE_MASK) + +#define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE_MASK (0x4000000U) +#define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE_SHIFT (26U) +/*! TS_CACHE_READ_MODE - TS cache read mode + * 0b0..Disable + * 0b1..Enable + */ +#define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE_MASK) + +#define DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT_MASK (0x8000000U) +#define DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT_SHIFT (27U) +/*! PIXEL_CACHE_REPLACEMENT - Pixel cache replacement + * 0b0..LRU + * 0b1..FIFO + */ +#define DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT_MASK) + +#define DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010_MASK (0x10000000U) +#define DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010_SHIFT (28U) +/*! INTEL_P010 - Intel's P010 format + * 0b0..Disable + * 0b1..Enable + */ +#define DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010_MASK) + +#define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT_MASK (0x20000000U) +#define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT_SHIFT (29U) +/*! TS_CACHE_REPLACEMENT - TS cache replacement + * 0b0..LRU + * 0b1..FIFO + */ +#define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT_MASK) +/*! @} */ + +/* The count of DEC400D_GCREGAHBDECREADEXCONFIG */ +#define DEC400D_GCREGAHBDECREADEXCONFIG_COUNT (32U) + +/*! @name GCREGAHBDECREADSTRIDE - Decoder Read Stride */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECREADSTRIDE_STRIDE_MASK (0x3FFFFU) +#define DEC400D_GCREGAHBDECREADSTRIDE_STRIDE_SHIFT (0U) +/*! STRIDE - Surface stride + */ +#define DEC400D_GCREGAHBDECREADSTRIDE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADSTRIDE_STRIDE_SHIFT)) & DEC400D_GCREGAHBDECREADSTRIDE_STRIDE_MASK) +/*! @} */ + +/* The count of DEC400D_GCREGAHBDECREADSTRIDE */ +#define DEC400D_GCREGAHBDECREADSTRIDE_COUNT (32U) + +/*! @name GCREGAHBDECREADBUFFEREND - Decoder Read Buffer End */ +/*! @{ */ + +#define DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END_MASK (0xFFFFFFFFU) +#define DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END_SHIFT (0U) +/*! RD_BUFF_END - Address + */ +#define DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END_SHIFT)) & DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END_MASK) +/*! @} */ + +/* The count of DEC400D_GCREGAHBDECREADBUFFEREND */ +#define DEC400D_GCREGAHBDECREADBUFFEREND_COUNT (32U) + + +/*! + * @} + */ /* end of group DEC400D_Register_Masks */ + + +/* DEC400D - Peripheral instance base addresses */ +/** Peripheral DCSS__DEC400D base address */ +#define DCSS__DEC400D_BASE (0x32E15000u) +/** Peripheral DCSS__DEC400D base pointer */ +#define DCSS__DEC400D ((DEC400D_Type *)DCSS__DEC400D_BASE) +/** Array initializer of DEC400D peripheral base addresses */ +#define DEC400D_BASE_ADDRS { DCSS__DEC400D_BASE } +/** Array initializer of DEC400D peripheral base pointers */ +#define DEC400D_BASE_PTRS { DCSS__DEC400D } + +/*! + * @} + */ /* end of group DEC400D_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DPR_Peripheral_Access_Layer DPR Peripheral Access Layer + * @{ + */ + +/** DPR - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< System Control 0, offset: 0x0 */ + __IO uint32_t SET; /**< System Control 0, offset: 0x4 */ + __IO uint32_t CLR; /**< System Control 0, offset: 0x8 */ + __IO uint32_t TOG; /**< System Control 0, offset: 0xC */ + } SYSTEM_CTRL0; + uint8_t RESERVED_0[16]; + struct { /* offset: 0x20 */ + __IO uint32_t RW; /**< Interrupt Mask, offset: 0x20 */ + __IO uint32_t SET; /**< Interrupt Mask, offset: 0x24 */ + __IO uint32_t CLR; /**< Interrupt Mask, offset: 0x28 */ + __IO uint32_t TOG; /**< Interrupt Mask, offset: 0x2C */ + } IRQ_MASK; + struct { /* offset: 0x30 */ + __I uint32_t RW; /**< Status Register of Masked IRQ, offset: 0x30 */ + __I uint32_t SET; /**< Status Register of Masked IRQ, offset: 0x34 */ + __I uint32_t CLR; /**< Status Register of Masked IRQ, offset: 0x38 */ + __I uint32_t TOG; /**< Status Register of Masked IRQ, offset: 0x3C */ + } IRQ_MASK_STATUS; + struct { /* offset: 0x40 */ + __IO uint32_t RW; /**< Status of Non-Masked IRQ, offset: 0x40 */ + __IO uint32_t SET; /**< Status of Non-Masked IRQ, offset: 0x44 */ + __IO uint32_t CLR; /**< Status of Non-Masked IRQ, offset: 0x48 */ + __IO uint32_t TOG; /**< Status of Non-Masked IRQ, offset: 0x4C */ + } IRQ_NONMASK_STATUS; + struct { /* offset: 0x50 */ + __IO uint32_t RW; /**< Mode Control 0, offset: 0x50 */ + __IO uint32_t SET; /**< Mode Control 0, offset: 0x54 */ + __IO uint32_t CLR; /**< Mode Control 0, offset: 0x58 */ + __IO uint32_t TOG; /**< Mode Control 0, offset: 0x5C */ + } MODE_CTRL0; + uint8_t RESERVED_1[16]; + struct { /* offset: 0x70 */ + __IO uint32_t RW; /**< Frame Control 0, offset: 0x70 */ + __IO uint32_t SET; /**< Frame Control 0, offset: 0x74 */ + __IO uint32_t CLR; /**< Frame Control 0, offset: 0x78 */ + __IO uint32_t TOG; /**< Frame Control 0, offset: 0x7C */ + } FRAME_CTRL0; + uint8_t RESERVED_2[16]; + struct { /* offset: 0x90 */ + __IO uint32_t RW; /**< Frame 1-Plane Control 0, offset: 0x90 */ + __IO uint32_t SET; /**< Frame 1-Plane Control 0, offset: 0x94 */ + __IO uint32_t CLR; /**< Frame 1-Plane Control 0, offset: 0x98 */ + __IO uint32_t TOG; /**< Frame 1-Plane Control 0, offset: 0x9C */ + } FRAME_1P_CTRL0; + struct { /* offset: 0xA0 */ + __IO uint32_t RW; /**< Frame 1-Plane Pix X Control, offset: 0xA0 */ + __IO uint32_t SET; /**< Frame 1-Plane Pix X Control, offset: 0xA4 */ + __IO uint32_t CLR; /**< Frame 1-Plane Pix X Control, offset: 0xA8 */ + __IO uint32_t TOG; /**< Frame 1-Plane Pix X Control, offset: 0xAC */ + } FRAME_1P_PIX_X_CTRL; + struct { /* offset: 0xB0 */ + __IO uint32_t RW; /**< Frame 1-Plane Pix Y Control, offset: 0xB0 */ + __IO uint32_t SET; /**< Frame 1-Plane Pix Y Control, offset: 0xB4 */ + __IO uint32_t CLR; /**< Frame 1-Plane Pix Y Control, offset: 0xB8 */ + __IO uint32_t TOG; /**< Frame 1-Plane Pix Y Control, offset: 0xBC */ + } FRAME_1P_PIX_Y_CTRL; + struct { /* offset: 0xC0 */ + __IO uint32_t RW; /**< Frame 1-Plane Base Address Control 0, offset: 0xC0 */ + __IO uint32_t SET; /**< Frame 1-Plane Base Address Control 0, offset: 0xC4 */ + __IO uint32_t CLR; /**< Frame 1-Plane Base Address Control 0, offset: 0xC8 */ + __IO uint32_t TOG; /**< Frame 1-Plane Base Address Control 0, offset: 0xCC */ + } FRAME_1P_BASE_ADDR_CTRL0; + uint8_t RESERVED_3[16]; + struct { /* offset: 0xE0 */ + __IO uint32_t RW; /**< Frame 2-Plane Control 0, offset: 0xE0 */ + __IO uint32_t SET; /**< Frame 2-Plane Control 0, offset: 0xE4 */ + __IO uint32_t CLR; /**< Frame 2-Plane Control 0, offset: 0xE8 */ + __IO uint32_t TOG; /**< Frame 2-Plane Control 0, offset: 0xEC */ + } FRAME_2P_CTRL0; + struct { /* offset: 0xF0 */ + __IO uint32_t RW; /**< Frame 2-Plane Pix X Control, offset: 0xF0 */ + __IO uint32_t SET; /**< Frame 2-Plane Pix X Control, offset: 0xF4 */ + __IO uint32_t CLR; /**< Frame 2-Plane Pix X Control, offset: 0xF8 */ + __IO uint32_t TOG; /**< Frame 2-Plane Pix X Control, offset: 0xFC */ + } FRAME_2P_PIX_X_CTRL; + struct { /* offset: 0x100 */ + __IO uint32_t RW; /**< Frame 2-Plane Pix Y Control, offset: 0x100 */ + __IO uint32_t SET; /**< Frame 2-Plane Pix Y Control, offset: 0x104 */ + __IO uint32_t CLR; /**< Frame 2-Plane Pix Y Control, offset: 0x108 */ + __IO uint32_t TOG; /**< Frame 2-Plane Pix Y Control, offset: 0x10C */ + } FRAME_2P_PIX_Y_CTRL; + struct { /* offset: 0x110 */ + __IO uint32_t RW; /**< Frame 2-Plane Base Address Control 0, offset: 0x110 */ + __IO uint32_t SET; /**< Frame 2-Plane Base Address Control 0, offset: 0x114 */ + __IO uint32_t CLR; /**< Frame 2-Plane Base Address Control 0, offset: 0x118 */ + __IO uint32_t TOG; /**< Frame 2-Plane Base Address Control 0, offset: 0x11C */ + } FRAME_2P_BASE_ADDR_CTRL0; + uint8_t RESERVED_4[224]; + struct { /* offset: 0x200 */ + __IO uint32_t RW; /**< RTRAM Control 0, offset: 0x200 */ + __IO uint32_t SET; /**< RTRAM Control 0, offset: 0x204 */ + __IO uint32_t CLR; /**< RTRAM Control 0, offset: 0x208 */ + __IO uint32_t TOG; /**< RTRAM Control 0, offset: 0x20C */ + } RTRAM_CTRL0; +} DPR_Type; + +/* ---------------------------------------------------------------------------- + -- DPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DPR_Register_Masks DPR Register Masks + * @{ + */ + +/*! @name SYSTEM_CTRL0 - System Control 0 */ +/*! @{ */ + +#define DPR_SYSTEM_CTRL0_RUN_EN_MASK (0x1U) +#define DPR_SYSTEM_CTRL0_RUN_EN_SHIFT (0U) +/*! RUN_EN - Run Enable + */ +#define DPR_SYSTEM_CTRL0_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_RUN_EN_SHIFT)) & DPR_SYSTEM_CTRL0_RUN_EN_MASK) + +#define DPR_SYSTEM_CTRL0_SOFT_RESET_MASK (0x2U) +#define DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT (1U) +/*! SOFT_RESET - Soft Reset + */ +#define DPR_SYSTEM_CTRL0_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT)) & DPR_SYSTEM_CTRL0_SOFT_RESET_MASK) + +#define DPR_SYSTEM_CTRL0_REPEAT_EN_MASK (0x4U) +#define DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT (2U) +/*! REPEAT_EN - Repeat Enable + */ +#define DPR_SYSTEM_CTRL0_REPEAT_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT)) & DPR_SYSTEM_CTRL0_REPEAT_EN_MASK) + +#define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK (0x8U) +#define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT (3U) +/*! SHADOW_LOAD_EN - Shadow Load Enable + */ +#define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT)) & DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK) + +#define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK (0x10U) +#define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT (4U) +/*! SW_SHADOW_LOAD_SEL - Software Shadow Load Select + */ +#define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT)) & DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK) + +#define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK (0x10000U) +#define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT (16U) +/*! BCMD2AXI_MSTR_ID_CTRL - Buscmd To AXI Master ID Control + */ +#define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT)) & DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK) +/*! @} */ + +/*! @name IRQ_MASK - Interrupt Mask */ +/*! @{ */ + +#define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK (0x1U) +#define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT (0U) +/*! IRQ_DPR_CTRL_DONE - DPR Control Done IRQ Mask + */ +#define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK) + +#define DPR_IRQ_MASK_IRQ_DPR_RUN_MASK (0x2U) +#define DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT (1U) +/*! IRQ_DPR_RUN - DPR Run IRQ Mask + */ +#define DPR_IRQ_MASK_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_RUN_MASK) + +#define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK (0x4U) +#define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT (2U) +/*! IRQ_DPR_SHADOW_LOADED_MASK - DPR Shadow Loaded IRQ Mask + */ +#define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK) + +#define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK (0x8U) +#define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT (3U) +/*! IRQ_AXI_READ_ERROR - AXI Read Error IRQ Mask + */ +#define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK) + +#define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U) +#define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U) +/*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow IRQ Mask + */ +#define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK) + +#define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U) +#define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U) +/*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow IRQ Mask + */ +#define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK) + +#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U) +#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U) +/*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer ready IRQ error Mask + */ +#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK) + +#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U) +#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U) +/*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer ready IRQ error Mask + */ +#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK) +/*! @} */ + +/*! @name IRQ_MASK_STATUS - Status Register of Masked IRQ */ +/*! @{ */ + +#define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U) +#define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U) +/*! IRQ_DPR_CTRL_DONE - DPR Control Done Masked IRQ + */ +#define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK) + +#define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK (0x2U) +#define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT (1U) +/*! IRQ_DPR_RUN - DPR Run Masked IRQ + */ +#define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK) + +#define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK (0x4U) +#define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT (2U) +/*! IRQ_DPR_SHADOW_LOADED - DPR Shadow Loaded Masked IRQ + */ +#define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK) + +#define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U) +#define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U) +/*! IRQ_AXI_READ_ERROR - AXI Read Error Masked IRQ + */ +#define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK) + +#define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U) +#define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U) +/*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow Masked IRQ + */ +#define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK) + +#define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U) +#define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U) +/*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow Masked IRQ + */ +#define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK) + +#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U) +#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U) +/*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer error Masked IRQ + */ +#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK) + +#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U) +#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U) +/*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer error Masked IRQ + */ +#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK) +/*! @} */ + +/*! @name IRQ_NONMASK_STATUS - Status of Non-Masked IRQ */ +/*! @{ */ + +#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U) +#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U) +/*! IRQ_DPR_CTRL_DONE - DPR Control Done Non-Masked IRQ + */ +#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK) + +#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK (0x2U) +#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT (1U) +/*! IRQ_DPR_RUN - DPR Run Non-Masked IRQ + */ +#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK) + +#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK (0x4U) +#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT (2U) +/*! IRQ_DPR_SHADOW_LOADED_NMSTAT - DPR Shadow Loaded Non-Masked IRQ + */ +#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK) + +#define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U) +#define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U) +/*! IRQ_AXI_READ_ERROR - AXI Read Error Non-Masked IRQ + */ +#define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK) + +#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U) +#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U) +/*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow Non-Masked IRQ + */ +#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK) + +#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U) +#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U) +/*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow Non-Masked IRQ + */ +#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK) + +#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U) +#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U) +/*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer ready error Non-Masked IRQ + */ +#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK) + +#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U) +#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U) +/*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer ready error Non-Masked IRQ + */ +#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK) +/*! @} */ + +/*! @name MODE_CTRL0 - Mode Control 0 */ +/*! @{ */ + +#define DPR_MODE_CTRL0_RTR_3BUF_EN_MASK (0x1U) +#define DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT (0U) +/*! RTR_3BUF_EN - RTRAM Buffer Implementation + */ +#define DPR_MODE_CTRL0_RTR_3BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_3BUF_EN_MASK) + +#define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK (0x2U) +#define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT (1U) +/*! RTR_4LINE_BUF_EN - RTRAM Lines Per Buffer + */ +#define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK) + +#define DPR_MODE_CTRL0_TILE_TYPE_MASK (0x1CU) +#define DPR_MODE_CTRL0_TILE_TYPE_SHIFT (2U) +/*! TILE_TYPE - Tile Type + */ +#define DPR_MODE_CTRL0_TILE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_TILE_TYPE_SHIFT)) & DPR_MODE_CTRL0_TILE_TYPE_MASK) + +#define DPR_MODE_CTRL0_YUV_EN_MASK (0x40U) +#define DPR_MODE_CTRL0_YUV_EN_SHIFT (6U) +/*! YUV_EN - YUV Enable + */ +#define DPR_MODE_CTRL0_YUV_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_YUV_EN_SHIFT)) & DPR_MODE_CTRL0_YUV_EN_MASK) + +#define DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK (0x80U) +#define DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT (7U) +/*! COMP_2PLANE_EN - Component 2-Plane Enable + */ +#define DPR_MODE_CTRL0_COMP_2PLANE_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT)) & DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK) + +#define DPR_MODE_CTRL0_PIX_SIZE_MASK (0x300U) +#define DPR_MODE_CTRL0_PIX_SIZE_SHIFT (8U) +/*! PIX_SIZE - Pixel Size + */ +#define DPR_MODE_CTRL0_PIX_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_SIZE_SHIFT)) & DPR_MODE_CTRL0_PIX_SIZE_MASK) + +#define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK (0x400U) +#define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT (10U) +/*! PIX_LUMA_UV_SWAP - Pixel luma/UV position Swap + */ +#define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK) + +#define DPR_MODE_CTRL0_PIX_UV_SWAP_MASK (0x800U) +#define DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT (11U) +/*! PIX_UV_SWAP - Pixel UV Swap + */ +#define DPR_MODE_CTRL0_PIX_UV_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_UV_SWAP_MASK) + +#define DPR_MODE_CTRL0_B_COMP_SEL_MASK (0x3000U) +#define DPR_MODE_CTRL0_B_COMP_SEL_SHIFT (12U) +/*! B_COMP_SEL - B Component Select + */ +#define DPR_MODE_CTRL0_B_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_B_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_B_COMP_SEL_MASK) + +#define DPR_MODE_CTRL0_G_COMP_SEL_MASK (0xC000U) +#define DPR_MODE_CTRL0_G_COMP_SEL_SHIFT (14U) +/*! G_COMP_SEL - G Component Select + */ +#define DPR_MODE_CTRL0_G_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_G_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_G_COMP_SEL_MASK) + +#define DPR_MODE_CTRL0_R_COMP_SEL_MASK (0x30000U) +#define DPR_MODE_CTRL0_R_COMP_SEL_SHIFT (16U) +/*! R_COMP_SEL - R Component Select + */ +#define DPR_MODE_CTRL0_R_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_R_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_R_COMP_SEL_MASK) + +#define DPR_MODE_CTRL0_A_COMP_SEL_MASK (0xC0000U) +#define DPR_MODE_CTRL0_A_COMP_SEL_SHIFT (18U) +/*! A_COMP_SEL - A Component Select + */ +#define DPR_MODE_CTRL0_A_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_A_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_A_COMP_SEL_MASK) +/*! @} */ + +/*! @name FRAME_CTRL0 - Frame Control 0 */ +/*! @{ */ + +#define DPR_FRAME_CTRL0_HFLIP_EN_MASK (0x1U) +#define DPR_FRAME_CTRL0_HFLIP_EN_SHIFT (0U) +/*! HFLIP_EN - Horizontal Flip Enable + */ +#define DPR_FRAME_CTRL0_HFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_HFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_HFLIP_EN_MASK) + +#define DPR_FRAME_CTRL0_VFLIP_EN_MASK (0x2U) +#define DPR_FRAME_CTRL0_VFLIP_EN_SHIFT (1U) +/*! VFLIP_EN - Vertical Flip Enable + */ +#define DPR_FRAME_CTRL0_VFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_VFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_VFLIP_EN_MASK) + +#define DPR_FRAME_CTRL0_ROT_ENC_MASK (0xCU) +#define DPR_FRAME_CTRL0_ROT_ENC_SHIFT (2U) +/*! ROT_ENC - Encoded Rotation + */ +#define DPR_FRAME_CTRL0_ROT_ENC(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_ENC_SHIFT)) & DPR_FRAME_CTRL0_ROT_ENC_MASK) + +#define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK (0x10U) +#define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT (4U) +/*! ROT_FLIP_ORDER_EN - Rotation Flip Order + */ +#define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT)) & DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK) + +#define DPR_FRAME_CTRL0_PITCH_MASK (0xFFFF0000U) +#define DPR_FRAME_CTRL0_PITCH_SHIFT (16U) +/*! PITCH - Image Pitch + */ +#define DPR_FRAME_CTRL0_PITCH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_PITCH_SHIFT)) & DPR_FRAME_CTRL0_PITCH_MASK) +/*! @} */ + +/*! @name FRAME_1P_CTRL0 - Frame 1-Plane Control 0 */ +/*! @{ */ + +#define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK (0x7U) +#define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT (0U) +/*! MAX_BYTES_PREQ - Max Bytes Per Request + */ +#define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK) +/*! @} */ + +/*! @name FRAME_1P_PIX_X_CTRL - Frame 1-Plane Pix X Control */ +/*! @{ */ + +#define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK (0xFFFFU) +#define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT (0U) +/*! NUM_X_PIX_WIDE - Number of Pixels Wide in X-direction + */ +#define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT)) & DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK) + +#define DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X_MASK (0xFFFF0000U) +#define DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X_SHIFT (16U) +/*! CROP_ULC_X - Starting Coordinate of Cropped Image X (1-Plane or 2-Plane Luma) + */ +#define DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X_SHIFT)) & DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X_MASK) +/*! @} */ + +/*! @name FRAME_1P_PIX_Y_CTRL - Frame 1-Plane Pix Y Control */ +/*! @{ */ + +#define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK (0xFFFFU) +#define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT (0U) +/*! NUM_Y_PIX_HIGH - Number of Pixels High in Y-direction + */ +#define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT)) & DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK) + +#define DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y_MASK (0xFFFF0000U) +#define DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y_SHIFT (16U) +/*! CROP_ULC_Y - Starting Coordinate of Cropped Image Y (1-Plane or 2-Plane Luma) + */ +#define DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y_SHIFT)) & DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y_MASK) +/*! @} */ + +/*! @name FRAME_1P_BASE_ADDR_CTRL0 - Frame 1-Plane Base Address Control 0 */ +/*! @{ */ + +#define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU) +#define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U) +/*! BASE_ADDR - Base Address + */ +#define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK) +/*! @} */ + +/*! @name FRAME_2P_CTRL0 - Frame 2-Plane Control 0 */ +/*! @{ */ + +#define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK (0x7U) +#define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT (0U) +/*! MAX_BYTES_PREQ - Max Bytes Per Request + */ +#define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK) +/*! @} */ + +/*! @name FRAME_2P_PIX_X_CTRL - Frame 2-Plane Pix X Control */ +/*! @{ */ + +#define DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK (0xFFFFU) +#define DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT (0U) +/*! NUM_X_PIX_WIDE - Number of Pixels Wide in X-direction + */ +#define DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT)) & DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK) + +#define DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X_MASK (0xFFFF0000U) +#define DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X_SHIFT (16U) +/*! CROP_ULC_X - Starting Coordinate of Cropped Image X (2-Plane UV) + */ +#define DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X_SHIFT)) & DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X_MASK) +/*! @} */ + +/*! @name FRAME_2P_PIX_Y_CTRL - Frame 2-Plane Pix Y Control */ +/*! @{ */ + +#define DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK (0xFFFFU) +#define DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT (0U) +/*! NUM_Y_PIX_HIGH - Number of Pixels High in Y-direction + */ +#define DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT)) & DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK) + +#define DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y_MASK (0xFFFF0000U) +#define DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y_SHIFT (16U) +/*! CROP_ULC_Y - Starting Coordinate of Cropped Image Y (2-Plane UV) + */ +#define DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y_SHIFT)) & DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y_MASK) +/*! @} */ + +/*! @name FRAME_2P_BASE_ADDR_CTRL0 - Frame 2-Plane Base Address Control 0 */ +/*! @{ */ + +#define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU) +#define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U) +/*! BASE_ADDR - Base Address + */ +#define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK) +/*! @} */ + +/*! @name RTRAM_CTRL0 - RTRAM Control 0 */ +/*! @{ */ + +#define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK (0x1U) +#define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT (0U) +/*! NUM_ROWS_ACTIVE - Number of Rows Active + */ +#define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT)) & DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK) + +#define DPR_RTRAM_CTRL0_THRES_HIGH_MASK (0xEU) +#define DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT (1U) +/*! THRES_HIGH - Threshold High + */ +#define DPR_RTRAM_CTRL0_THRES_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT)) & DPR_RTRAM_CTRL0_THRES_HIGH_MASK) + +#define DPR_RTRAM_CTRL0_THRES_LOW_MASK (0x70U) +#define DPR_RTRAM_CTRL0_THRES_LOW_SHIFT (4U) +/*! THRES_LOW - Threshold Low + */ +#define DPR_RTRAM_CTRL0_THRES_LOW(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_LOW_SHIFT)) & DPR_RTRAM_CTRL0_THRES_LOW_MASK) + +#define DPR_RTRAM_CTRL0_ABORT_SEL_MASK (0x80U) +#define DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT (7U) +/*! ABORT_SEL - Abort Select + */ +#define DPR_RTRAM_CTRL0_ABORT_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT)) & DPR_RTRAM_CTRL0_ABORT_SEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DPR_Register_Masks */ + + +/* DPR - Peripheral instance base addresses */ +/** Peripheral DCSS__DPR1 base address */ +#define DCSS__DPR1_BASE (0x32E18000u) +/** Peripheral DCSS__DPR1 base pointer */ +#define DCSS__DPR1 ((DPR_Type *)DCSS__DPR1_BASE) +/** Peripheral DCSS__DPR2 base address */ +#define DCSS__DPR2_BASE (0x32E19000u) +/** Peripheral DCSS__DPR2 base pointer */ +#define DCSS__DPR2 ((DPR_Type *)DCSS__DPR2_BASE) +/** Peripheral DCSS__DPR3 base address */ +#define DCSS__DPR3_BASE (0x32E1A000u) +/** Peripheral DCSS__DPR3 base pointer */ +#define DCSS__DPR3 ((DPR_Type *)DCSS__DPR3_BASE) +/** Array initializer of DPR peripheral base addresses */ +#define DPR_BASE_ADDRS { 0u, DCSS__DPR1_BASE, DCSS__DPR2_BASE, DCSS__DPR3_BASE } +/** Array initializer of DPR peripheral base pointers */ +#define DPR_BASE_PTRS { (DPR_Type *)0u, DCSS__DPR1, DCSS__DPR2, DCSS__DPR3 } + +/*! + * @} + */ /* end of group DPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DTG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DTG_Peripheral_Access_Layer DTG Peripheral Access Layer + * @{ + */ + +/** DTG - Register Layout Typedef */ +typedef struct { + __IO uint32_t TC_CONTROL_STATUS; /**< Timing Controller Control Register, offset: 0x0 */ + __IO uint32_t TC_DTG_REG1; /**< DTG lower right corner locations, offset: 0x4 */ + __IO uint32_t TC_DISPLAY_REG2; /**< Display Register: TOP Window Coordinates for Active display area, offset: 0x8 */ + __IO uint32_t TC_DISPLAY_REG3; /**< Display Register: BOTTOM Window Coordinates for Active display area, offset: 0xC */ + __IO uint32_t TC_CH1_REG4; /**< Channel 1 window Register: TOP Window Coordinates for channel1, offset: 0x10 */ + __IO uint32_t TC_CH1_REG5; /**< Channel_1 window Register: BOTTOM Window Coordinates for channel_1 window, offset: 0x14 */ + __IO uint32_t TC_CH2_REG6; /**< Channel 2 window Register: TOP Window Coordinates for channel_2, offset: 0x18 */ + __IO uint32_t TC_CH2_REG7; /**< Channel_2 window Register: BOTTOM Window Coordinates for channel_2 pixel window, offset: 0x1C */ + __IO uint32_t TC_CH3_REG8; /**< Channel 3 window Register: TOP Window Coordinates for channel_3, offset: 0x20 */ + __IO uint32_t TC_CH3_REG9; /**< Channel_3 window Register: BOTTOM Window Coordinates for channel_3 pixel window, offset: 0x24 */ + __IO uint32_t TC_CTX_LD_REG10; /**< Context Loader Register: Coordinates in the raster table where the context loader is started., offset: 0x28 */ + __IO uint32_t TC_CH1_BKRND_REG11; /**< Channel_1 background pixel color., offset: 0x2C */ + __IO uint32_t TC_CH2_BKRND_REG12; /**< Channel_2 background pixel color., offset: 0x30 */ + uint8_t RESERVED_0[4]; + __IO uint32_t BLENDER_DBY_EOTF_RANGEINV; /**< DBY MODE Blender control., offset: 0x38 */ + __IO uint32_t BLENDER_DBY_EOTF_RANGEMIN; /**< DBY MODE Blender control., offset: 0x3C */ + __IO uint32_t BLENDER_DBY_BDP; /**< DBY MODE blender control., offset: 0x40 */ + __IO uint32_t BLENDER_BKRND_I_GRAPHICS; /**< Backgound pixel color component sent to blender. Used when no valid pixels, offset: 0x44 */ + __IO uint32_t BLENDER_BKRND_P_GRAPHICS; /**< Backgound pixel color component sent to blender. Used when no valid pixels, offset: 0x48 */ + __IO uint32_t BLENDER_BKRND_T_GRAPHICS; /**< Backgound pixel color component sent to blender. Used when no valid pixels, offset: 0x4C */ + __IO uint32_t TC_LINE1_INT_REG13; /**< LINE1 interrupt control: Coordinate where line1 interrupt is asserted, offset: 0x50 */ + __IO uint32_t TC_LINE2_INT_REG14; /**< LINE2 interrupt control: Coordinate where line2 interrupt is asserted, offset: 0x54 */ + __IO uint32_t TC_ALPHA_DEFAULT_REG15; /**< default alpha, offset: 0x58 */ + __I uint32_t TC_INTERRUPT_STATUS; /**< Timing Controller interrupt status, offset: 0x5C */ + __IO uint32_t TC_INTRERRUPT_CONTROL_REG17; /**< Timing Controller interrupt control., offset: 0x60 */ + __IO uint32_t TC_CH3_BKRND_REG18; /**< Channel_3 background pixel color., offset: 0x64 */ + __IO uint32_t TC_INTRERRUPT_MASK; /**< Timing Controller interrupt masks, offset: 0x68 */ + __IO uint32_t TC_LINE3_INT_REG; /**< LINE3 interrupt control: Coordinate where line3 interrupt is asserted, offset: 0x6C */ + __IO uint32_t TC_LINE4_INT_REG; /**< LINE4 interrupt control: Coordinate where line4 interrupt is asserted, offset: 0x70 */ + __IO uint32_t TC_OL_DE_CONTROL_REG; /**< For DBY Mode: Controls the assertion and de-assertion DE signal (Overlay channel)., offset: 0x74 */ + __IO uint32_t TC_BL_DE_CONTROL_REG; /**< For DBY Mode: Controls the assertion and de-assertion DE signal (Base layer (BL) channel)., offset: 0x78 */ + __IO uint32_t TC_EL_DE_CONTROL_REG; /**< For DBY Mode: Controls the assertion and de-assertion DE signal (Enhancement layer (EL) channel)., offset: 0x7C */ +} DTG_Type; + +/* ---------------------------------------------------------------------------- + -- DTG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DTG_Register_Masks DTG Register Masks + * @{ + */ + +/*! @name TC_CONTROL_STATUS - Timing Controller Control Register */ +/*! @{ */ + +#define DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE_MASK (0x1U) +#define DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE_SHIFT (0U) +#define DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE_MASK) + +#define DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE_MASK (0x2U) +#define DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE_SHIFT (1U) +#define DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE_MASK) + +#define DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE_MASK (0x4U) +#define DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE_SHIFT (2U) +#define DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE_MASK) + +#define DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE_MASK (0x8U) +#define DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE_SHIFT (3U) +#define DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE_MASK) + +#define DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT_MASK (0x80U) +#define DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT_SHIFT (7U) +#define DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT_MASK) + +#define DTG_TC_CONTROL_STATUS_TC_GO_MASK (0x100U) +#define DTG_TC_CONTROL_STATUS_TC_GO_SHIFT (8U) +#define DTG_TC_CONTROL_STATUS_TC_GO(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_GO_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_GO_MASK) + +#define DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE_MASK (0x200U) +#define DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE_SHIFT (9U) +#define DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE_MASK) + +#define DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL_MASK (0x400U) +#define DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL_SHIFT (10U) +#define DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL_MASK) + +#define DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP_MASK (0x7000U) +#define DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP_SHIFT (12U) +#define DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP_MASK) + +#define DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA_MASK (0xFF000000U) +#define DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA_SHIFT (24U) +#define DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA_MASK) +/*! @} */ + +/*! @name TC_DTG_REG1 - DTG lower right corner locations */ +/*! @{ */ + +#define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X_MASK (0x1FFFU) +#define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X_SHIFT (0U) +#define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X_SHIFT)) & DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X_MASK) + +#define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y_MASK (0x1FFF0000U) +#define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y_SHIFT (16U) +#define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y_MASK) +/*! @} */ + +/*! @name TC_DISPLAY_REG2 - Display Register: TOP Window Coordinates for Active display area */ +/*! @{ */ + +#define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X_MASK (0x1FFFU) +#define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X_SHIFT (0U) +#define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X_SHIFT)) & DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X_MASK) + +#define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y_MASK (0x1FFF0000U) +#define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y_SHIFT (16U) +#define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y_SHIFT)) & DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y_MASK) +/*! @} */ + +/*! @name TC_DISPLAY_REG3 - Display Register: BOTTOM Window Coordinates for Active display area */ +/*! @{ */ + +#define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X_MASK (0x1FFFU) +#define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X_SHIFT (0U) +#define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X_SHIFT)) & DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X_MASK) + +#define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y_MASK (0x1FFF0000U) +#define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y_SHIFT (16U) +#define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y_MASK) +/*! @} */ + +/*! @name TC_CH1_REG4 - Channel 1 window Register: TOP Window Coordinates for channel1 */ +/*! @{ */ + +#define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X_MASK (0x1FFFU) +#define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X_SHIFT (0U) +#define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X_SHIFT)) & DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X_MASK) + +#define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y_MASK (0x1FFF0000U) +#define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y_SHIFT (16U) +#define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y_SHIFT)) & DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y_MASK) +/*! @} */ + +/*! @name TC_CH1_REG5 - Channel_1 window Register: BOTTOM Window Coordinates for channel_1 window */ +/*! @{ */ + +#define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X_MASK (0x1FFFU) +#define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X_SHIFT (0U) +#define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X_SHIFT)) & DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X_MASK) + +#define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y_MASK (0x1FFF0000U) +#define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y_SHIFT (16U) +#define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y_MASK) +/*! @} */ + +/*! @name TC_CH2_REG6 - Channel 2 window Register: TOP Window Coordinates for channel_2 */ +/*! @{ */ + +#define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X_MASK (0x1FFFU) +#define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X_SHIFT (0U) +#define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X_SHIFT)) & DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X_MASK) + +#define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y_MASK (0x1FFF0000U) +#define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y_SHIFT (16U) +#define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y_SHIFT)) & DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y_MASK) +/*! @} */ + +/*! @name TC_CH2_REG7 - Channel_2 window Register: BOTTOM Window Coordinates for channel_2 pixel window */ +/*! @{ */ + +#define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X_MASK (0x1FFFU) +#define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X_SHIFT (0U) +#define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X_SHIFT)) & DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X_MASK) + +#define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y_MASK (0x1FFF0000U) +#define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y_SHIFT (16U) +#define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y_MASK) +/*! @} */ + +/*! @name TC_CH3_REG8 - Channel 3 window Register: TOP Window Coordinates for channel_3 */ +/*! @{ */ + +#define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X_MASK (0x1FFFU) +#define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X_SHIFT (0U) +#define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X_SHIFT)) & DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X_MASK) + +#define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y_MASK (0x1FFF0000U) +#define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y_SHIFT (16U) +#define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y_SHIFT)) & DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y_MASK) +/*! @} */ + +/*! @name TC_CH3_REG9 - Channel_3 window Register: BOTTOM Window Coordinates for channel_3 pixel window */ +/*! @{ */ + +#define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X_MASK (0x1FFFU) +#define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X_SHIFT (0U) +#define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X_SHIFT)) & DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X_MASK) + +#define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y_MASK (0x1FFF0000U) +#define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y_SHIFT (16U) +#define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y_MASK) +/*! @} */ + +/*! @name TC_CTX_LD_REG10 - Context Loader Register: Coordinates in the raster table where the context loader is started. */ +/*! @{ */ + +#define DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT_MASK (0x1FFFU) +#define DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT_SHIFT (0U) +#define DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT_SHIFT)) & DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT_MASK) + +#define DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT_MASK (0x1FFF0000U) +#define DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT_SHIFT (16U) +#define DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT_SHIFT)) & DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT_MASK) +/*! @} */ + +/*! @name TC_CH1_BKRND_REG11 - Channel_1 background pixel color. */ +/*! @{ */ + +#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3_MASK (0x3FFU) +#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3_SHIFT (0U) +#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3_SHIFT)) & DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3_MASK) + +#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2_MASK (0xFFC00U) +#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2_SHIFT (10U) +#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2_SHIFT)) & DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2_MASK) + +#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1_MASK (0x3FF00000U) +#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1_SHIFT (20U) +#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1_SHIFT)) & DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1_MASK) +/*! @} */ + +/*! @name TC_CH2_BKRND_REG12 - Channel_2 background pixel color. */ +/*! @{ */ + +#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3_MASK (0x3FFU) +#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3_SHIFT (0U) +#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3_SHIFT)) & DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3_MASK) + +#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2_MASK (0xFFC00U) +#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2_SHIFT (10U) +#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2_SHIFT)) & DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2_MASK) + +#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1_MASK (0x3FF00000U) +#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1_SHIFT (20U) +#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1_SHIFT)) & DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1_MASK) +/*! @} */ + +/*! @name BLENDER_DBY_EOTF_RANGEINV - DBY MODE Blender control. */ +/*! @{ */ + +#define DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV_MASK (0x1FFFFU) +#define DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV_SHIFT (0U) +#define DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV_SHIFT)) & DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV_MASK) +/*! @} */ + +/*! @name BLENDER_DBY_EOTF_RANGEMIN - DBY MODE Blender control. */ +/*! @{ */ + +#define DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN_MASK (0x1FFFFU) +#define DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN_SHIFT (0U) +#define DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN_SHIFT)) & DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN_MASK) +/*! @} */ + +/*! @name BLENDER_DBY_BDP - DBY MODE blender control. */ +/*! @{ */ + +#define DTG_BLENDER_DBY_BDP_BLENDER_BDP_MASK (0x1FU) +#define DTG_BLENDER_DBY_BDP_BLENDER_BDP_SHIFT (0U) +#define DTG_BLENDER_DBY_BDP_BLENDER_BDP(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_DBY_BDP_BLENDER_BDP_SHIFT)) & DTG_BLENDER_DBY_BDP_BLENDER_BDP_MASK) +/*! @} */ + +/*! @name BLENDER_BKRND_I_GRAPHICS - Backgound pixel color component sent to blender. Used when no valid pixels */ +/*! @{ */ + +#define DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP_MASK (0xFFFFFFFU) +#define DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP_SHIFT (0U) +#define DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP_SHIFT)) & DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP_MASK) +/*! @} */ + +/*! @name BLENDER_BKRND_P_GRAPHICS - Backgound pixel color component sent to blender. Used when no valid pixels */ +/*! @{ */ + +#define DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP_MASK (0xFFFFFFFU) +#define DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP_SHIFT (0U) +#define DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP_SHIFT)) & DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP_MASK) +/*! @} */ + +/*! @name BLENDER_BKRND_T_GRAPHICS - Backgound pixel color component sent to blender. Used when no valid pixels */ +/*! @{ */ + +#define DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP_MASK (0xFFFFFFFU) +#define DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP_SHIFT (0U) +#define DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP_SHIFT)) & DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP_MASK) +/*! @} */ + +/*! @name TC_LINE1_INT_REG13 - LINE1 interrupt control: Coordinate where line1 interrupt is asserted */ +/*! @{ */ + +#define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X_MASK (0x1FFFU) +#define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X_SHIFT (0U) +#define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X_SHIFT)) & DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X_MASK) + +#define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y_MASK (0x1FFF0000U) +#define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y_SHIFT (16U) +#define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y_SHIFT)) & DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y_MASK) +/*! @} */ + +/*! @name TC_LINE2_INT_REG14 - LINE2 interrupt control: Coordinate where line2 interrupt is asserted */ +/*! @{ */ + +#define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X_MASK (0x1FFFU) +#define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X_SHIFT (0U) +#define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X_SHIFT)) & DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X_MASK) + +#define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y_MASK (0x1FFF0000U) +#define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y_SHIFT (16U) +#define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y_SHIFT)) & DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y_MASK) +/*! @} */ + +/*! @name TC_ALPHA_DEFAULT_REG15 - default alpha */ +/*! @{ */ + +#define DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF_MASK (0xFFU) +#define DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF_SHIFT (0U) +#define DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF_SHIFT)) & DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF_MASK) +/*! @} */ + +/*! @name TC_INTERRUPT_STATUS - Timing Controller interrupt status */ +/*! @{ */ + +#define DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT_MASK (0x1U) +#define DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT_SHIFT (0U) +#define DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT_MASK) + +#define DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT_MASK (0x2U) +#define DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT_SHIFT (1U) +#define DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT_MASK) + +#define DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT_MASK (0x4U) +#define DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT_SHIFT (2U) +#define DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT_MASK) + +#define DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT_MASK (0x8U) +#define DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT_SHIFT (3U) +#define DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT_MASK) + +#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT_MASK (0x10U) +#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT_SHIFT (4U) +#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT_MASK) + +#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT_MASK (0x20U) +#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT_SHIFT (5U) +#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT_MASK) + +#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT_MASK (0x40U) +#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT_SHIFT (6U) +#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT_MASK) +/*! @} */ + +/*! @name TC_INTRERRUPT_CONTROL_REG17 - Timing Controller interrupt control. */ +/*! @{ */ + +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR_MASK (0x1U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR_SHIFT (0U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR_MASK) + +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR_MASK (0x2U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR_SHIFT (1U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR_MASK) + +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR_MASK (0x4U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR_SHIFT (2U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR_MASK) + +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR_MASK (0x8U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR_SHIFT (3U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR_MASK) + +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR_MASK (0x10U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR_SHIFT (4U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR_MASK) + +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR_MASK (0x20U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR_SHIFT (5U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR_MASK) + +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR_MASK (0x40U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR_SHIFT (6U) +#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR_MASK) +/*! @} */ + +/*! @name TC_CH3_BKRND_REG18 - Channel_3 background pixel color. */ +/*! @{ */ + +#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3_MASK (0x3FFU) +#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3_SHIFT (0U) +#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3_SHIFT)) & DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3_MASK) + +#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2_MASK (0xFFC00U) +#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2_SHIFT (10U) +#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2_SHIFT)) & DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2_MASK) + +#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1_MASK (0x3FF00000U) +#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1_SHIFT (20U) +#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1_SHIFT)) & DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1_MASK) +/*! @} */ + +/*! @name TC_INTRERRUPT_MASK - Timing Controller interrupt masks */ +/*! @{ */ + +#define DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK_MASK (0x1U) +#define DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK_SHIFT (0U) +#define DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK_MASK) + +#define DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK_MASK (0x2U) +#define DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK_SHIFT (1U) +#define DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK_MASK) + +#define DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK_MASK (0x4U) +#define DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK_SHIFT (2U) +#define DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK_MASK) + +#define DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK_MASK (0x8U) +#define DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK_SHIFT (3U) +#define DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK_MASK) + +#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK_MASK (0x10U) +#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK_SHIFT (4U) +#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK_MASK) + +#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK_MASK (0x20U) +#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK_SHIFT (5U) +#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK_MASK) + +#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK_MASK (0x40U) +#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK_SHIFT (6U) +#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK_MASK) +/*! @} */ + +/*! @name TC_LINE3_INT_REG - LINE3 interrupt control: Coordinate where line3 interrupt is asserted */ +/*! @{ */ + +#define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X_MASK (0x1FFFU) +#define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X_SHIFT (0U) +#define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X_SHIFT)) & DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X_MASK) + +#define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y_MASK (0x1FFF0000U) +#define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y_SHIFT (16U) +#define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y_SHIFT)) & DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y_MASK) +/*! @} */ + +/*! @name TC_LINE4_INT_REG - LINE4 interrupt control: Coordinate where line4 interrupt is asserted */ +/*! @{ */ + +#define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X_MASK (0x1FFFU) +#define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X_SHIFT (0U) +#define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X_SHIFT)) & DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X_MASK) + +#define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y_MASK (0x1FFF0000U) +#define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y_SHIFT (16U) +#define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y_SHIFT)) & DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y_MASK) +/*! @} */ + +/*! @name TC_OL_DE_CONTROL_REG - For DBY Mode: Controls the assertion and de-assertion DE signal (Overlay channel). */ +/*! @{ */ + +#define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK (0x1FFFU) +#define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT (0U) +#define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT)) & DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK) + +#define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK (0x1FFF0000U) +#define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT (16U) +#define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT)) & DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK) + +#define DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK (0x80000000U) +#define DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT (31U) +#define DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT)) & DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK) +/*! @} */ + +/*! @name TC_BL_DE_CONTROL_REG - For DBY Mode: Controls the assertion and de-assertion DE signal (Base layer (BL) channel). */ +/*! @{ */ + +#define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK (0x1FFFU) +#define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT (0U) +#define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT)) & DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK) + +#define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK (0x1FFF0000U) +#define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT (16U) +#define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT)) & DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK) + +#define DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK (0x80000000U) +#define DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT (31U) +#define DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT)) & DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK) +/*! @} */ + +/*! @name TC_EL_DE_CONTROL_REG - For DBY Mode: Controls the assertion and de-assertion DE signal (Enhancement layer (EL) channel). */ +/*! @{ */ + +#define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK (0x1FFFU) +#define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT (0U) +#define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT)) & DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK) + +#define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK (0x1FFF0000U) +#define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT (16U) +#define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT)) & DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK) + +#define DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK (0x80000000U) +#define DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT (31U) +#define DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT)) & DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DTG_Register_Masks */ + + +/* DTG - Peripheral instance base addresses */ +/** Peripheral DCSS__DTG base address */ +#define DCSS__DTG_BASE (0x32E20000u) +/** Peripheral DCSS__DTG base pointer */ +#define DCSS__DTG ((DTG_Type *)DCSS__DTG_BASE) +/** Array initializer of DTG peripheral base addresses */ +#define DTG_BASE_ADDRS { DCSS__DTG_BASE } +/** Array initializer of DTG peripheral base pointers */ +#define DTG_BASE_PTRS { DCSS__DTG } + +/*! + * @} + */ /* end of group DTG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DTRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DTRC_Peripheral_Access_Layer DTRC Peripheral Access Layer + * @{ + */ + +/** DTRC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __IO uint32_t FDYDSADDR; /**< Luma video data start address, array offset: 0x0, array step: 0x60 */ + __IO uint32_t FDCDSADDR; /**< Chroma video data start address, array offset: 0x4, array step: 0x60 */ + __IO uint32_t FDYTSADDR; /**< Luma table data start address, array offset: 0x8, array step: 0x60 */ + __IO uint32_t FDCTSADDR; /**< Chroma table data start address, array offset: 0xC, array step: 0x60 */ + __IO uint32_t FSIZE; /**< Frame size, array offset: 0x10, array step: 0x60 */ + __IO uint32_t FSYSSA; /**< Luma data slave start address, array offset: 0x14, array step: 0x60 */ + __IO uint32_t FSYSEA; /**< Luma data slave end address, array offset: 0x18, array step: 0x60 */ + __IO uint32_t FSUVSSA; /**< Chroma data slave start address, array offset: 0x1C, array step: 0x60 */ + __IO uint32_t FSUVSEA; /**< Chroma data slave end address, array offset: 0x20, array step: 0x60 */ + __IO uint32_t FCROPORIG; /**< Cropped picture origin, array offset: 0x24, array step: 0x60 */ + __IO uint32_t FCROPSIZE; /**< Cropped picture size, array offset: 0x28, array step: 0x60 */ + __IO uint32_t FDCTL; /**< Frame data control, array offset: 0x2C, array step: 0x60 */ + uint8_t RESERVED_0[48]; + } FRAME_REGISTERS[2]; + __IO uint32_t DTRCINTEN; /**< DTRC Interrupt enables, offset: 0xC0 */ + __IO uint32_t FDINTR; /**< DTRC Interrupt Requests, offset: 0xC4 */ + __IO uint32_t DTCTRL; /**< DTRC Control, offset: 0xC8 */ + __IO uint32_t ARIDR; /**< ARIDR, offset: 0xCC */ + __IO uint32_t DTID2DDR; /**< DTID2DDR, offset: 0xD0 */ + __I uint32_t DTRCCONFIG; /**< DTRCCONFIG, offset: 0xD4 */ + __I uint32_t DTRCVERSION; /**< DTRC Version, offset: 0xD8 */ + uint8_t RESERVED_0[20]; + __IO uint32_t PFCTRL; /**< Performance counter control, offset: 0xF0 */ + __IO uint32_t PFCR; /**< Performance counter, offset: 0xF4 */ + __IO uint32_t TOCR; /**< Time Out Cycles, offset: 0xF8 */ +} DTRC_Type; + +/* ---------------------------------------------------------------------------- + -- DTRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DTRC_Register_Masks DTRC Register Masks + * @{ + */ + +/*! @name FDYDSADDR - Luma video data start address */ +/*! @{ */ + +#define DTRC_FDYDSADDR_F0DYDSADDR_MASK (0xFFFFFFFFU) +#define DTRC_FDYDSADDR_F0DYDSADDR_SHIFT (0U) +/*! F0DYDSADDR - Luma video data start address + */ +#define DTRC_FDYDSADDR_F0DYDSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDYDSADDR_F0DYDSADDR_SHIFT)) & DTRC_FDYDSADDR_F0DYDSADDR_MASK) + +#define DTRC_FDYDSADDR_F1DYDSADDR_MASK (0xFFFFFFFFU) +#define DTRC_FDYDSADDR_F1DYDSADDR_SHIFT (0U) +/*! F1DYDSADDR - Luma video data start address + */ +#define DTRC_FDYDSADDR_F1DYDSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDYDSADDR_F1DYDSADDR_SHIFT)) & DTRC_FDYDSADDR_F1DYDSADDR_MASK) +/*! @} */ + +/* The count of DTRC_FDYDSADDR */ +#define DTRC_FDYDSADDR_COUNT (2U) + +/*! @name FDCDSADDR - Chroma video data start address */ +/*! @{ */ + +#define DTRC_FDCDSADDR_F0DCDSADDR_MASK (0xFFFFFFFFU) +#define DTRC_FDCDSADDR_F0DCDSADDR_SHIFT (0U) +/*! F0DCDSADDR - Chroma video data start address + */ +#define DTRC_FDCDSADDR_F0DCDSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCDSADDR_F0DCDSADDR_SHIFT)) & DTRC_FDCDSADDR_F0DCDSADDR_MASK) + +#define DTRC_FDCDSADDR_F1DCDSADDR_MASK (0xFFFFFFFFU) +#define DTRC_FDCDSADDR_F1DCDSADDR_SHIFT (0U) +/*! F1DCDSADDR - Chroma video data start address + */ +#define DTRC_FDCDSADDR_F1DCDSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCDSADDR_F1DCDSADDR_SHIFT)) & DTRC_FDCDSADDR_F1DCDSADDR_MASK) +/*! @} */ + +/* The count of DTRC_FDCDSADDR */ +#define DTRC_FDCDSADDR_COUNT (2U) + +/*! @name FDYTSADDR - Luma table data start address */ +/*! @{ */ + +#define DTRC_FDYTSADDR_F0DYTSADDR_MASK (0xFFFFFFFFU) +#define DTRC_FDYTSADDR_F0DYTSADDR_SHIFT (0U) +/*! F0DYTSADDR - Luma table data start address + */ +#define DTRC_FDYTSADDR_F0DYTSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDYTSADDR_F0DYTSADDR_SHIFT)) & DTRC_FDYTSADDR_F0DYTSADDR_MASK) + +#define DTRC_FDYTSADDR_F1DYTSADDR_MASK (0xFFFFFFFFU) +#define DTRC_FDYTSADDR_F1DYTSADDR_SHIFT (0U) +/*! F1DYTSADDR - Luma table data start address + */ +#define DTRC_FDYTSADDR_F1DYTSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDYTSADDR_F1DYTSADDR_SHIFT)) & DTRC_FDYTSADDR_F1DYTSADDR_MASK) +/*! @} */ + +/* The count of DTRC_FDYTSADDR */ +#define DTRC_FDYTSADDR_COUNT (2U) + +/*! @name FDCTSADDR - Chroma table data start address */ +/*! @{ */ + +#define DTRC_FDCTSADDR_F0DCTSADDR_MASK (0xFFFFFFFFU) +#define DTRC_FDCTSADDR_F0DCTSADDR_SHIFT (0U) +/*! F0DCTSADDR - Chroma table data start address + */ +#define DTRC_FDCTSADDR_F0DCTSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTSADDR_F0DCTSADDR_SHIFT)) & DTRC_FDCTSADDR_F0DCTSADDR_MASK) + +#define DTRC_FDCTSADDR_F1DCTSADDR_MASK (0xFFFFFFFFU) +#define DTRC_FDCTSADDR_F1DCTSADDR_SHIFT (0U) +/*! F1DCTSADDR - Chroma table data start address + */ +#define DTRC_FDCTSADDR_F1DCTSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTSADDR_F1DCTSADDR_SHIFT)) & DTRC_FDCTSADDR_F1DCTSADDR_MASK) +/*! @} */ + +/* The count of DTRC_FDCTSADDR */ +#define DTRC_FDCTSADDR_COUNT (2U) + +/*! @name FSIZE - Frame size */ +/*! @{ */ + +#define DTRC_FSIZE_F0WIDTH_MASK (0x3FFU) +#define DTRC_FSIZE_F0WIDTH_SHIFT (0U) +/*! F0WIDTH - Frame width + */ +#define DTRC_FSIZE_F0WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSIZE_F0WIDTH_SHIFT)) & DTRC_FSIZE_F0WIDTH_MASK) + +#define DTRC_FSIZE_F1WIDTH_MASK (0x3FFU) +#define DTRC_FSIZE_F1WIDTH_SHIFT (0U) +/*! F1WIDTH - Frame width + */ +#define DTRC_FSIZE_F1WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSIZE_F1WIDTH_SHIFT)) & DTRC_FSIZE_F1WIDTH_MASK) + +#define DTRC_FSIZE_F0HEIGHT_MASK (0x3FF0000U) +#define DTRC_FSIZE_F0HEIGHT_SHIFT (16U) +/*! F0HEIGHT - Frame height + */ +#define DTRC_FSIZE_F0HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSIZE_F0HEIGHT_SHIFT)) & DTRC_FSIZE_F0HEIGHT_MASK) + +#define DTRC_FSIZE_F1HEIGHT_MASK (0x3FF0000U) +#define DTRC_FSIZE_F1HEIGHT_SHIFT (16U) +/*! F1HEIGHT - Frame height + */ +#define DTRC_FSIZE_F1HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSIZE_F1HEIGHT_SHIFT)) & DTRC_FSIZE_F1HEIGHT_MASK) +/*! @} */ + +/* The count of DTRC_FSIZE */ +#define DTRC_FSIZE_COUNT (2U) + +/*! @name FSYSSA - Luma data slave start address */ +/*! @{ */ + +#define DTRC_FSYSSA_F0YSTRBYPASS_MASK (0x1U) +#define DTRC_FSYSSA_F0YSTRBYPASS_SHIFT (0U) +/*! F0YSTRBYPASS - Luma Start Tile to Raster scan Bypass + * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. + * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. + */ +#define DTRC_FSYSSA_F0YSTRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSSA_F0YSTRBYPASS_SHIFT)) & DTRC_FSYSSA_F0YSTRBYPASS_MASK) + +#define DTRC_FSYSSA_F1YSTRBYPASS_MASK (0x1U) +#define DTRC_FSYSSA_F1YSTRBYPASS_SHIFT (0U) +/*! F1YSTRBYPASS - Luma Start Tile to Raster scan Bypass + * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. + * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. + */ +#define DTRC_FSYSSA_F1YSTRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSSA_F1YSTRBYPASS_SHIFT)) & DTRC_FSYSSA_F1YSTRBYPASS_MASK) + +#define DTRC_FSYSSA_F0SYSSA_MASK (0xFFFFFFF0U) +#define DTRC_FSYSSA_F0SYSSA_SHIFT (4U) +/*! F0SYSSA - Luma data slave start address + */ +#define DTRC_FSYSSA_F0SYSSA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSSA_F0SYSSA_SHIFT)) & DTRC_FSYSSA_F0SYSSA_MASK) + +#define DTRC_FSYSSA_F1SYSSA_MASK (0xFFFFFFF0U) +#define DTRC_FSYSSA_F1SYSSA_SHIFT (4U) +/*! F1SYSSA - Luma data slave start address + */ +#define DTRC_FSYSSA_F1SYSSA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSSA_F1SYSSA_SHIFT)) & DTRC_FSYSSA_F1SYSSA_MASK) +/*! @} */ + +/* The count of DTRC_FSYSSA */ +#define DTRC_FSYSSA_COUNT (2U) + +/*! @name FSYSEA - Luma data slave end address */ +/*! @{ */ + +#define DTRC_FSYSEA_F0YETRBYPASS_MASK (0x1U) +#define DTRC_FSYSEA_F0YETRBYPASS_SHIFT (0U) +/*! F0YETRBYPASS - End Tile to Raster scan Bypass + * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. + * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. + */ +#define DTRC_FSYSEA_F0YETRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSEA_F0YETRBYPASS_SHIFT)) & DTRC_FSYSEA_F0YETRBYPASS_MASK) + +#define DTRC_FSYSEA_F1YETRBYPASS_MASK (0x1U) +#define DTRC_FSYSEA_F1YETRBYPASS_SHIFT (0U) +/*! F1YETRBYPASS - End Tile to Raster scan Bypass + * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. + * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. + */ +#define DTRC_FSYSEA_F1YETRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSEA_F1YETRBYPASS_SHIFT)) & DTRC_FSYSEA_F1YETRBYPASS_MASK) + +#define DTRC_FSYSEA_F0SYSEA_MASK (0xFFFFFFF0U) +#define DTRC_FSYSEA_F0SYSEA_SHIFT (4U) +/*! F0SYSEA - Luma data slave end address + */ +#define DTRC_FSYSEA_F0SYSEA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSEA_F0SYSEA_SHIFT)) & DTRC_FSYSEA_F0SYSEA_MASK) + +#define DTRC_FSYSEA_F1SYSEA_MASK (0xFFFFFFF0U) +#define DTRC_FSYSEA_F1SYSEA_SHIFT (4U) +/*! F1SYSEA - Luma data slave end address + */ +#define DTRC_FSYSEA_F1SYSEA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSEA_F1SYSEA_SHIFT)) & DTRC_FSYSEA_F1SYSEA_MASK) +/*! @} */ + +/* The count of DTRC_FSYSEA */ +#define DTRC_FSYSEA_COUNT (2U) + +/*! @name FSUVSSA - Chroma data slave start address */ +/*! @{ */ + +#define DTRC_FSUVSSA_F0CSTRBYPASS_MASK (0x1U) +#define DTRC_FSUVSSA_F0CSTRBYPASS_SHIFT (0U) +/*! F0CSTRBYPASS - Chroma Start Tile to Raster scan Bypass + * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. + * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. + */ +#define DTRC_FSUVSSA_F0CSTRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSSA_F0CSTRBYPASS_SHIFT)) & DTRC_FSUVSSA_F0CSTRBYPASS_MASK) + +#define DTRC_FSUVSSA_F1CSTRBYPASS_MASK (0x1U) +#define DTRC_FSUVSSA_F1CSTRBYPASS_SHIFT (0U) +/*! F1CSTRBYPASS - Chroma Start Tile to Raster scan Bypass + * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. + * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. + */ +#define DTRC_FSUVSSA_F1CSTRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSSA_F1CSTRBYPASS_SHIFT)) & DTRC_FSUVSSA_F1CSTRBYPASS_MASK) + +#define DTRC_FSUVSSA_F0SUVSSA_MASK (0xFFFFFFF0U) +#define DTRC_FSUVSSA_F0SUVSSA_SHIFT (4U) +/*! F0SUVSSA - Chroma data slave start address + */ +#define DTRC_FSUVSSA_F0SUVSSA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSSA_F0SUVSSA_SHIFT)) & DTRC_FSUVSSA_F0SUVSSA_MASK) + +#define DTRC_FSUVSSA_F1SUVSSA_MASK (0xFFFFFFF0U) +#define DTRC_FSUVSSA_F1SUVSSA_SHIFT (4U) +/*! F1SUVSSA - Chroma data slave start address + */ +#define DTRC_FSUVSSA_F1SUVSSA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSSA_F1SUVSSA_SHIFT)) & DTRC_FSUVSSA_F1SUVSSA_MASK) +/*! @} */ + +/* The count of DTRC_FSUVSSA */ +#define DTRC_FSUVSSA_COUNT (2U) + +/*! @name FSUVSEA - Chroma data slave end address */ +/*! @{ */ + +#define DTRC_FSUVSEA_F0CETRBYPASS_MASK (0x1U) +#define DTRC_FSUVSEA_F0CETRBYPASS_SHIFT (0U) +/*! F0CETRBYPASS - End Tile to Raster scan Bypass + * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. + * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. + */ +#define DTRC_FSUVSEA_F0CETRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSEA_F0CETRBYPASS_SHIFT)) & DTRC_FSUVSEA_F0CETRBYPASS_MASK) + +#define DTRC_FSUVSEA_F1CETRBYPASS_MASK (0x1U) +#define DTRC_FSUVSEA_F1CETRBYPASS_SHIFT (0U) +/*! F1CETRBYPASS - End Tile to Raster scan Bypass + * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. + * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. + */ +#define DTRC_FSUVSEA_F1CETRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSEA_F1CETRBYPASS_SHIFT)) & DTRC_FSUVSEA_F1CETRBYPASS_MASK) + +#define DTRC_FSUVSEA_F0SUVSEA_MASK (0xFFFFFFF0U) +#define DTRC_FSUVSEA_F0SUVSEA_SHIFT (4U) +/*! F0SUVSEA - Chroma data slave end address + */ +#define DTRC_FSUVSEA_F0SUVSEA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSEA_F0SUVSEA_SHIFT)) & DTRC_FSUVSEA_F0SUVSEA_MASK) + +#define DTRC_FSUVSEA_F1SUVSEA_MASK (0xFFFFFFF0U) +#define DTRC_FSUVSEA_F1SUVSEA_SHIFT (4U) +/*! F1SUVSEA - Chroma data slave end address + */ +#define DTRC_FSUVSEA_F1SUVSEA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSEA_F1SUVSEA_SHIFT)) & DTRC_FSUVSEA_F1SUVSEA_MASK) +/*! @} */ + +/* The count of DTRC_FSUVSEA */ +#define DTRC_FSUVSEA_COUNT (2U) + +/*! @name FCROPORIG - Cropped picture origin */ +/*! @{ */ + +#define DTRC_FCROPORIG_F0CROPORIGX_MASK (0x1FFFU) +#define DTRC_FCROPORIG_F0CROPORIGX_SHIFT (0U) +/*! F0CROPORIGX - Cropped picture x origin + */ +#define DTRC_FCROPORIG_F0CROPORIGX(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPORIG_F0CROPORIGX_SHIFT)) & DTRC_FCROPORIG_F0CROPORIGX_MASK) + +#define DTRC_FCROPORIG_F1CROPORIGX_MASK (0x1FFFU) +#define DTRC_FCROPORIG_F1CROPORIGX_SHIFT (0U) +/*! F1CROPORIGX - Cropped picture x origin + */ +#define DTRC_FCROPORIG_F1CROPORIGX(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPORIG_F1CROPORIGX_SHIFT)) & DTRC_FCROPORIG_F1CROPORIGX_MASK) + +#define DTRC_FCROPORIG_F0CROPORIGY_MASK (0x1FFF0000U) +#define DTRC_FCROPORIG_F0CROPORIGY_SHIFT (16U) +/*! F0CROPORIGY - Cropped picture y origin + */ +#define DTRC_FCROPORIG_F0CROPORIGY(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPORIG_F0CROPORIGY_SHIFT)) & DTRC_FCROPORIG_F0CROPORIGY_MASK) + +#define DTRC_FCROPORIG_F1CROPORIGY_MASK (0x1FFF0000U) +#define DTRC_FCROPORIG_F1CROPORIGY_SHIFT (16U) +/*! F1CROPORIGY - Cropped picture y origin + */ +#define DTRC_FCROPORIG_F1CROPORIGY(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPORIG_F1CROPORIGY_SHIFT)) & DTRC_FCROPORIG_F1CROPORIGY_MASK) +/*! @} */ + +/* The count of DTRC_FCROPORIG */ +#define DTRC_FCROPORIG_COUNT (2U) + +/*! @name FCROPSIZE - Cropped picture size */ +/*! @{ */ + +#define DTRC_FCROPSIZE_F0CROPWIDTH_MASK (0x1FFFU) +#define DTRC_FCROPSIZE_F0CROPWIDTH_SHIFT (0U) +/*! F0CROPWIDTH - Cropped picture width + */ +#define DTRC_FCROPSIZE_F0CROPWIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPSIZE_F0CROPWIDTH_SHIFT)) & DTRC_FCROPSIZE_F0CROPWIDTH_MASK) + +#define DTRC_FCROPSIZE_F1CROPWIDTH_MASK (0x1FFFU) +#define DTRC_FCROPSIZE_F1CROPWIDTH_SHIFT (0U) +/*! F1CROPWIDTH - Cropped picture width + */ +#define DTRC_FCROPSIZE_F1CROPWIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPSIZE_F1CROPWIDTH_SHIFT)) & DTRC_FCROPSIZE_F1CROPWIDTH_MASK) + +#define DTRC_FCROPSIZE_F0CROPHEIGHT_MASK (0x1FFF0000U) +#define DTRC_FCROPSIZE_F0CROPHEIGHT_SHIFT (16U) +/*! F0CROPHEIGHT - Cropped picture height + */ +#define DTRC_FCROPSIZE_F0CROPHEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPSIZE_F0CROPHEIGHT_SHIFT)) & DTRC_FCROPSIZE_F0CROPHEIGHT_MASK) + +#define DTRC_FCROPSIZE_F1CROPHEIGHT_MASK (0x1FFF0000U) +#define DTRC_FCROPSIZE_F1CROPHEIGHT_SHIFT (16U) +/*! F1CROPHEIGHT - Cropped picture height + */ +#define DTRC_FCROPSIZE_F1CROPHEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPSIZE_F1CROPHEIGHT_SHIFT)) & DTRC_FCROPSIZE_F1CROPHEIGHT_MASK) +/*! @} */ + +/* The count of DTRC_FCROPSIZE */ +#define DTRC_FCROPSIZE_COUNT (2U) + +/*! @name FDCTL - Frame data control */ +/*! @{ */ + +#define DTRC_FDCTL_F0FRAMECFG_MASK (0x1U) +#define DTRC_FDCTL_F0FRAMECFG_SHIFT (0U) +/*! F0FRAMECFG - Frame configuration ready + * 0b0..Frame 0 configuration is not ready. + * 0b1..Frame 0 configuration is ready and decompress can start for the frame. All other configuration, such as + * main8/main10 are updated before setting this bit to 1. If there is no G1/G2 video transaction, set this bit + * to 0. + */ +#define DTRC_FDCTL_F0FRAMECFG(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F0FRAMECFG_SHIFT)) & DTRC_FDCTL_F0FRAMECFG_MASK) + +#define DTRC_FDCTL_F1FRAMECFG_MASK (0x1U) +#define DTRC_FDCTL_F1FRAMECFG_SHIFT (0U) +/*! F1FRAMECFG - Frame configuration ready + * 0b0..Frame 0 configuration is not ready. + * 0b1..Frame 0 configuration is ready and decompress can start for the frame. All other configuration, such as + * main8/main10 are updated before setting this bit to 1. If there is no G1/G2 video transaction, set this bit + * to 0. + */ +#define DTRC_FDCTL_F1FRAMECFG(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F1FRAMECFG_SHIFT)) & DTRC_FDCTL_F1FRAMECFG_MASK) + +#define DTRC_FDCTL_F0PIXELBITDEPTH_MASK (0x2U) +#define DTRC_FDCTL_F0PIXELBITDEPTH_SHIFT (1U) +/*! F0PIXELBITDEPTH - Pixel bit depth + * 0b0..10-bit pixel depth + * 0b1..8-bit pixel depth + */ +#define DTRC_FDCTL_F0PIXELBITDEPTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F0PIXELBITDEPTH_SHIFT)) & DTRC_FDCTL_F0PIXELBITDEPTH_MASK) + +#define DTRC_FDCTL_F1PIXELBITDEPTH_MASK (0x2U) +#define DTRC_FDCTL_F1PIXELBITDEPTH_SHIFT (1U) +/*! F1PIXELBITDEPTH - Pixel bit depth + * 0b0..10-bit pixel depth + * 0b1..8-bit pixel depth + */ +#define DTRC_FDCTL_F1PIXELBITDEPTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F1PIXELBITDEPTH_SHIFT)) & DTRC_FDCTL_F1PIXELBITDEPTH_MASK) + +#define DTRC_FDCTL_F0DECOMPRESS_MASK (0x20000U) +#define DTRC_FDCTL_F0DECOMPRESS_SHIFT (17U) +/*! F0DECOMPRESS - Decompress bypass + * 0b0..G2 reference frame is compressed. + * 0b1..G2/G1 reference frame is not compressed. + */ +#define DTRC_FDCTL_F0DECOMPRESS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F0DECOMPRESS_SHIFT)) & DTRC_FDCTL_F0DECOMPRESS_MASK) + +#define DTRC_FDCTL_F1DECOMPRESS_MASK (0x20000U) +#define DTRC_FDCTL_F1DECOMPRESS_SHIFT (17U) +/*! F1DECOMPRESS - Decompress bypass + * 0b0..G2 reference frame is compressed. + * 0b1..G2/G1 reference frame is not compressed. + */ +#define DTRC_FDCTL_F1DECOMPRESS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F1DECOMPRESS_SHIFT)) & DTRC_FDCTL_F1DECOMPRESS_MASK) + +#define DTRC_FDCTL_F0CROPENABLE_MASK (0x40000U) +#define DTRC_FDCTL_F0CROPENABLE_SHIFT (18U) +/*! F0CROPENABLE - Cropped enable + */ +#define DTRC_FDCTL_F0CROPENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F0CROPENABLE_SHIFT)) & DTRC_FDCTL_F0CROPENABLE_MASK) + +#define DTRC_FDCTL_F1CROPENABLE_MASK (0x40000U) +#define DTRC_FDCTL_F1CROPENABLE_SHIFT (18U) +/*! F1CROPENABLE - Cropped enable + */ +#define DTRC_FDCTL_F1CROPENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F1CROPENABLE_SHIFT)) & DTRC_FDCTL_F1CROPENABLE_MASK) +/*! @} */ + +/* The count of DTRC_FDCTL */ +#define DTRC_FDCTL_COUNT (2U) + +/*! @name DTRCINTEN - DTRC Interrupt enables */ +/*! @{ */ + +#define DTRC_DTRCINTEN_FRAMEFETCHDONE_EN_MASK (0x1U) +#define DTRC_DTRCINTEN_FRAMEFETCHDONE_EN_SHIFT (0U) +/*! FRAMEFETCHDONE_EN - Frame fetch done interrupt enable + * 0b0..Frame fetch done interrupt disabled. + * 0b1..Frame fetch done interrupt enabled. + */ +#define DTRC_DTRCINTEN_FRAMEFETCHDONE_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_FRAMEFETCHDONE_EN_SHIFT)) & DTRC_DTRCINTEN_FRAMEFETCHDONE_EN_MASK) + +#define DTRC_DTRCINTEN_BUSERROR_EN_MASK (0x2U) +#define DTRC_DTRCINTEN_BUSERROR_EN_SHIFT (1U) +/*! BUSERROR_EN - Bus error interrupt enable + * 0b0..Bus error interrupt disabled. + * 0b1..Bus error interrupt enabled. + */ +#define DTRC_DTRCINTEN_BUSERROR_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_BUSERROR_EN_SHIFT)) & DTRC_DTRCINTEN_BUSERROR_EN_MASK) + +#define DTRC_DTRCINTEN_TIMEOUT_EN_MASK (0x4U) +#define DTRC_DTRCINTEN_TIMEOUT_EN_SHIFT (2U) +/*! TIMEOUT_EN - Time out enable + * 0b0..Time out disabled. + * 0b1..Time out enabled. + */ +#define DTRC_DTRCINTEN_TIMEOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_TIMEOUT_EN_SHIFT)) & DTRC_DTRCINTEN_TIMEOUT_EN_MASK) + +#define DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN_MASK (0x8U) +#define DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN_SHIFT (3U) +/*! SLFRAMEFETCHDONE_EN - Slave frame fetch done + * 0b0..Slave frame fetch done disabled. + * 0b1..Slave frame fetch done enabled. + */ +#define DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN_SHIFT)) & DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN_MASK) + +#define DTRC_DTRCINTEN_HOTRESETFINISH_EN_MASK (0x10U) +#define DTRC_DTRCINTEN_HOTRESETFINISH_EN_SHIFT (4U) +/*! HOTRESETFINISH_EN - Hot reset finish + * 0b0..Hot reset finish disabled. + * 0b1..Hot reset finish enabled. + */ +#define DTRC_DTRCINTEN_HOTRESETFINISH_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_HOTRESETFINISH_EN_SHIFT)) & DTRC_DTRCINTEN_HOTRESETFINISH_EN_MASK) +/*! @} */ + +/*! @name FDINTR - DTRC Interrupt Requests */ +/*! @{ */ + +#define DTRC_FDINTR_FRAMEFETCHDONE_MASK (0x1U) +#define DTRC_FDINTR_FRAMEFETCHDONE_SHIFT (0U) +/*! FRAMEFETCHDONE - Frame fetch done interrupt + */ +#define DTRC_FDINTR_FRAMEFETCHDONE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_FRAMEFETCHDONE_SHIFT)) & DTRC_FDINTR_FRAMEFETCHDONE_MASK) + +#define DTRC_FDINTR_BUSERROR_MASK (0x2U) +#define DTRC_FDINTR_BUSERROR_SHIFT (1U) +/*! BUSERROR - Bus error interrupt + */ +#define DTRC_FDINTR_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_BUSERROR_SHIFT)) & DTRC_FDINTR_BUSERROR_MASK) + +#define DTRC_FDINTR_TIMEOUT_MASK (0x4U) +#define DTRC_FDINTR_TIMEOUT_SHIFT (2U) +/*! TIMEOUT - Time out interrupt + */ +#define DTRC_FDINTR_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_TIMEOUT_SHIFT)) & DTRC_FDINTR_TIMEOUT_MASK) + +#define DTRC_FDINTR_SLFRAMEFETCHDONE_MASK (0x8U) +#define DTRC_FDINTR_SLFRAMEFETCHDONE_SHIFT (3U) +/*! SLFRAMEFETCHDONE - Slave frame fetch done interrupt + */ +#define DTRC_FDINTR_SLFRAMEFETCHDONE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_SLFRAMEFETCHDONE_SHIFT)) & DTRC_FDINTR_SLFRAMEFETCHDONE_MASK) + +#define DTRC_FDINTR_HOTRESETFINISH_MASK (0x10U) +#define DTRC_FDINTR_HOTRESETFINISH_SHIFT (4U) +/*! HOTRESETFINISH - Hot reset finish interrupt + */ +#define DTRC_FDINTR_HOTRESETFINISH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_HOTRESETFINISH_SHIFT)) & DTRC_FDINTR_HOTRESETFINISH_MASK) +/*! @} */ + +/*! @name DTCTRL - DTRC Control */ +/*! @{ */ + +#define DTRC_DTCTRL_ARIDRCFG_MASK (0x3U) +#define DTRC_DTCTRL_ARIDRCFG_SHIFT (0U) +/*! ARIDRCFG - ARIDR configuration + * 0b00..All ARID is de-tiled. + * 0b01..ARID in ARIDR is de-tiled, and others are bypass. NOTE: ARID[0] specify decode luma or chroma, so 4 + * ARIDs in ARIDR should include both of ARID[0] ==1 and ARID[0] ==0. + * 0b10..ARID in ARIDR is bypass_de-tile, and others are de-tiled. + * 0b11..Same as 2'b01. + */ +#define DTRC_DTCTRL_ARIDRCFG(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_ARIDRCFG_SHIFT)) & DTRC_DTCTRL_ARIDRCFG_MASK) + +#define DTRC_DTCTRL_HOTRESETTRIG_MASK (0x4U) +#define DTRC_DTCTRL_HOTRESETTRIG_SHIFT (2U) +/*! HOTRESETTRIG - Hot reset trigger + */ +#define DTRC_DTCTRL_HOTRESETTRIG(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_HOTRESETTRIG_SHIFT)) & DTRC_DTCTRL_HOTRESETTRIG_MASK) + +#define DTRC_DTCTRL_G1G2DATA_MASK (0x8U) +#define DTRC_DTCTRL_G1G2DATA_SHIFT (3U) +/*! G1G2DATA - G2 or G1 source data + * 0b0..The source data is G2 data. + * 0b1..The source data is G1 tile data + */ +#define DTRC_DTCTRL_G1G2DATA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_G1G2DATA_SHIFT)) & DTRC_DTCTRL_G1G2DATA_MASK) + +#define DTRC_DTCTRL_AXIMAXBURSTL_MASK (0xFF0U) +#define DTRC_DTCTRL_AXIMAXBURSTL_SHIFT (4U) +/*! AXIMAXBURSTL - Maximum burst length of AXI master port + */ +#define DTRC_DTCTRL_AXIMAXBURSTL(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_AXIMAXBURSTL_SHIFT)) & DTRC_DTCTRL_AXIMAXBURSTL_MASK) + +#define DTRC_DTCTRL_BYTESWAP_SLRAST_MASK (0xF000U) +#define DTRC_DTCTRL_BYTESWAP_SLRAST_SHIFT (12U) +/*! BYTESWAP_SLRAST - Byte swap mode for slave interface raster scan data + */ +#define DTRC_DTCTRL_BYTESWAP_SLRAST(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_BYTESWAP_SLRAST_SHIFT)) & DTRC_DTCTRL_BYTESWAP_SLRAST_MASK) + +#define DTRC_DTCTRL_BYTESWAP_MCOMPTILE_MASK (0xF0000U) +#define DTRC_DTCTRL_BYTESWAP_MCOMPTILE_SHIFT (16U) +/*! BYTESWAP_MCOMPTILE - Byte swap mode for master interface compressed data and tiled data + */ +#define DTRC_DTCTRL_BYTESWAP_MCOMPTILE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_BYTESWAP_MCOMPTILE_SHIFT)) & DTRC_DTCTRL_BYTESWAP_MCOMPTILE_MASK) + +#define DTRC_DTCTRL_BYTESWAP_MTABLE_MASK (0xF00000U) +#define DTRC_DTCTRL_BYTESWAP_MTABLE_SHIFT (20U) +/*! BYTESWAP_MTABLE - Byte swap mode for master interface table data + */ +#define DTRC_DTCTRL_BYTESWAP_MTABLE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_BYTESWAP_MTABLE_SHIFT)) & DTRC_DTCTRL_BYTESWAP_MTABLE_MASK) + +#define DTRC_DTCTRL_BYTESWAP_M_NONG1G2_MASK (0xF000000U) +#define DTRC_DTCTRL_BYTESWAP_M_NONG1G2_SHIFT (24U) +/*! BYTESWAP_M_NONG1G2 - Byte swap mode for master interface non-G1/G2 data + */ +#define DTRC_DTCTRL_BYTESWAP_M_NONG1G2(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_BYTESWAP_M_NONG1G2_SHIFT)) & DTRC_DTCTRL_BYTESWAP_M_NONG1G2_MASK) + +#define DTRC_DTCTRL_MERGEG1G2_ARIDEN_MASK (0x10000000U) +#define DTRC_DTCTRL_MERGEG1G2_ARIDEN_SHIFT (28U) +/*! MERGEG1G2_ARIDEN - Merge G2/G1 ARID enable + * 0b0..G2/G1 transactions at AXI master interface use different id for table/chroma and data/luma according to DTID2DDR definition. + * 0b1..All G2/G1 transactions at AXI master interface use the same id configured in DTID2DDR[15:8] Please note + * that DTID2DDR[15:8] and DTID2DDR[7:0] still need to be set the same way as when DTCTRL[28] is 0. + */ +#define DTRC_DTCTRL_MERGEG1G2_ARIDEN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_MERGEG1G2_ARIDEN_SHIFT)) & DTRC_DTCTRL_MERGEG1G2_ARIDEN_MASK) + +#define DTRC_DTCTRL_RAST_ENDIAN_MASK (0x20000000U) +#define DTRC_DTCTRL_RAST_ENDIAN_SHIFT (29U) +/*! RAST_ENDIAN - Raster endian mode + * 0b0..10-bit output format is little-endian. Byte swap setting of DTCTRL[15:12] is used. + * 0b1..10-bit output format is big-endian. Byte swap setting of DTCTRL[15:12] is ignored. + */ +#define DTRC_DTCTRL_RAST_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_RAST_ENDIAN_SHIFT)) & DTRC_DTCTRL_RAST_ENDIAN_MASK) + +#define DTRC_DTCTRL_ADDR_ARID_MASK (0x40000000U) +#define DTRC_DTCTRL_ADDR_ARID_SHIFT (30U) +/*! ADDR_ARID - ADDR_ARID + * 0b0..By ARID (See bit[1:0] of this register). + * 0b1..By ARADDR + */ +#define DTRC_DTCTRL_ADDR_ARID(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_ADDR_ARID_SHIFT)) & DTRC_DTCTRL_ADDR_ARID_MASK) + +#define DTRC_DTCTRL_FRBUFF_PTR_MASK (0x80000000U) +#define DTRC_DTCTRL_FRBUFF_PTR_SHIFT (31U) +/*! FRBUFF_PTR - FRBUFF_PTR + * 0b0..Configure frame 0 registers. + * 0b1..Configure frame 1 registers. + */ +#define DTRC_DTCTRL_FRBUFF_PTR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_FRBUFF_PTR_SHIFT)) & DTRC_DTCTRL_FRBUFF_PTR_MASK) +/*! @} */ + +/*! @name ARIDR - ARIDR */ +/*! @{ */ + +#define DTRC_ARIDR_ARIDR_MASK (0xFFFFFFFFU) +#define DTRC_ARIDR_ARIDR_SHIFT (0U) +/*! ARIDR - ARIDR + */ +#define DTRC_ARIDR_ARIDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_ARIDR_ARIDR_SHIFT)) & DTRC_ARIDR_ARIDR_MASK) +/*! @} */ + +/*! @name DTID2DDR - DTID2DDR */ +/*! @{ */ + +#define DTRC_DTID2DDR_ARID_COMPR_MASK (0xFFU) +#define DTRC_DTID2DDR_ARID_COMPR_SHIFT (0U) +/*! ARID_COMPR - ARID_COMPR + */ +#define DTRC_DTID2DDR_ARID_COMPR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTID2DDR_ARID_COMPR_SHIFT)) & DTRC_DTID2DDR_ARID_COMPR_MASK) + +#define DTRC_DTID2DDR_ARID_TABLE_MASK (0xFF00U) +#define DTRC_DTID2DDR_ARID_TABLE_SHIFT (8U) +/*! ARID_TABLE - ARID_TABLE + */ +#define DTRC_DTID2DDR_ARID_TABLE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTID2DDR_ARID_TABLE_SHIFT)) & DTRC_DTID2DDR_ARID_TABLE_MASK) +/*! @} */ + +/*! @name DTRCCONFIG - DTRCCONFIG */ +/*! @{ */ + +#define DTRC_DTRCCONFIG_G1G2_KEEPORDER_MASK (0x2U) +#define DTRC_DTRCCONFIG_G1G2_KEEPORDER_SHIFT (1U) +/*! G1G2_KEEPORDER - G1G2_KEEPORDER + * 0b0..Not supported. DTRC sends out data transactions as soon as they are ready regardless of the address + * transactions order, The master connected to AXI slave interface must recognize the data transactions by the RID. + * 0b1..Supported, DTRC ensure return read data from a sequence of read transactions in the same order in which it received the address. + */ +#define DTRC_DTRCCONFIG_G1G2_KEEPORDER(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCCONFIG_G1G2_KEEPORDER_SHIFT)) & DTRC_DTRCCONFIG_G1G2_KEEPORDER_MASK) + +#define DTRC_DTRCCONFIG_AXI_MAXBURSTL_MASK (0x4U) +#define DTRC_DTRCCONFIG_AXI_MAXBURSTL_SHIFT (2U) +/*! AXI_MAXBURSTL - AXI_MAXBURSTL + * 0b0..Not supported. + * 0b1..Supported. DTRC sends the G1/G2 relating requests with ARLEN <= (the maximum burst length - 1). The + * maximum burst length is set by DTCTRL[16:8]. + */ +#define DTRC_DTRCCONFIG_AXI_MAXBURSTL(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCCONFIG_AXI_MAXBURSTL_SHIFT)) & DTRC_DTRCCONFIG_AXI_MAXBURSTL_MASK) + +#define DTRC_DTRCCONFIG_G1TILE_INPUT_MASK (0x8U) +#define DTRC_DTRCCONFIG_G1TILE_INPUT_SHIFT (3U) +/*! G1TILE_INPUT - G1TILE_INPUT + * 0b0..Not supported. + * 0b1..Supported. + */ +#define DTRC_DTRCCONFIG_G1TILE_INPUT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCCONFIG_G1TILE_INPUT_SHIFT)) & DTRC_DTRCCONFIG_G1TILE_INPUT_MASK) + +#define DTRC_DTRCCONFIG_MAX_PIC_WIDTH_MASK (0x30U) +#define DTRC_DTRCCONFIG_MAX_PIC_WIDTH_SHIFT (4U) +/*! MAX_PIC_WIDTH - MAX_PIC_WIDTH + * 0b00..4096 + * 0b01..1920 + * 0b10..Reserved. + * 0b11..Reserved. + */ +#define DTRC_DTRCCONFIG_MAX_PIC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCCONFIG_MAX_PIC_WIDTH_SHIFT)) & DTRC_DTRCCONFIG_MAX_PIC_WIDTH_MASK) +/*! @} */ + +/*! @name DTRCVERSION - DTRC Version */ +/*! @{ */ + +#define DTRC_DTRCVERSION_CUST_VERSION_MASK (0xFU) +#define DTRC_DTRCVERSION_CUST_VERSION_SHIFT (0U) +/*! CUST_VERSION - CUST_VERSION + */ +#define DTRC_DTRCVERSION_CUST_VERSION(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCVERSION_CUST_VERSION_SHIFT)) & DTRC_DTRCVERSION_CUST_VERSION_MASK) + +#define DTRC_DTRCVERSION_MINOR_MASK (0x3F0U) +#define DTRC_DTRCVERSION_MINOR_SHIFT (4U) +/*! MINOR - MINOR + */ +#define DTRC_DTRCVERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCVERSION_MINOR_SHIFT)) & DTRC_DTRCVERSION_MINOR_MASK) + +#define DTRC_DTRCVERSION_MAJOR_MASK (0xFC00U) +#define DTRC_DTRCVERSION_MAJOR_SHIFT (10U) +/*! MAJOR - MAJOR + */ +#define DTRC_DTRCVERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCVERSION_MAJOR_SHIFT)) & DTRC_DTRCVERSION_MAJOR_MASK) +/*! @} */ + +/*! @name PFCTRL - Performance counter control */ +/*! @{ */ + +#define DTRC_PFCTRL_PFC_EN_MASK (0x1U) +#define DTRC_PFCTRL_PFC_EN_SHIFT (0U) +/*! PFC_EN - PFC_EN + * 0b0..Performance Counter disabled. + * 0b1..Performance Counter enabled. + */ +#define DTRC_PFCTRL_PFC_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_PFCTRL_PFC_EN_SHIFT)) & DTRC_PFCTRL_PFC_EN_MASK) +/*! @} */ + +/*! @name PFCR - Performance counter */ +/*! @{ */ + +#define DTRC_PFCR_PFCR_MASK (0xFFFFFFFFU) +#define DTRC_PFCR_PFCR_SHIFT (0U) +/*! PFCR - Performance Counter + */ +#define DTRC_PFCR_PFCR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_PFCR_PFCR_SHIFT)) & DTRC_PFCR_PFCR_MASK) +/*! @} */ + +/*! @name TOCR - Time Out Cycles */ +/*! @{ */ + +#define DTRC_TOCR_TOCR_MASK (0xFFFFFFFFU) +#define DTRC_TOCR_TOCR_SHIFT (0U) +/*! TOCR - Time Out Cycles + */ +#define DTRC_TOCR_TOCR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_TOCR_TOCR_SHIFT)) & DTRC_TOCR_TOCR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DTRC_Register_Masks */ + + +/* DTRC - Peripheral instance base addresses */ +/** Peripheral DCSS__DTRC1 base address */ +#define DCSS__DTRC1_BASE (0x32E16000u) +/** Peripheral DCSS__DTRC1 base pointer */ +#define DCSS__DTRC1 ((DTRC_Type *)DCSS__DTRC1_BASE) +/** Peripheral DCSS__DTRC2 base address */ +#define DCSS__DTRC2_BASE (0x32E17000u) +/** Peripheral DCSS__DTRC2 base pointer */ +#define DCSS__DTRC2 ((DTRC_Type *)DCSS__DTRC2_BASE) +/** Array initializer of DTRC peripheral base addresses */ +#define DTRC_BASE_ADDRS { 0u, DCSS__DTRC1_BASE, DCSS__DTRC2_BASE } +/** Array initializer of DTRC peripheral base pointers */ +#define DTRC_BASE_PTRS { (DTRC_Type *)0u, DCSS__DTRC1, DCSS__DTRC2 } + +/*! + * @} + */ /* end of group DTRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ECSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer + * @{ + */ + +/** ECSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t RXDATA; /**< Receive Data Register, offset: 0x0 */ + __O uint32_t TXDATA; /**< Transmit Data Register, offset: 0x4 */ + __IO uint32_t CONREG; /**< Control Register, offset: 0x8 */ + __IO uint32_t CONFIGREG; /**< Config Register, offset: 0xC */ + __IO uint32_t INTREG; /**< Interrupt Control Register, offset: 0x10 */ + __IO uint32_t DMAREG; /**< DMA Control Register, offset: 0x14 */ + __IO uint32_t STATREG; /**< Status Register, offset: 0x18 */ + __IO uint32_t PERIODREG; /**< Sample Period Control Register, offset: 0x1C */ + __IO uint32_t TESTREG; /**< Test Control Register, offset: 0x20 */ + uint8_t RESERVED_0[28]; + __O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */ +} ECSPI_Type; + +/* ---------------------------------------------------------------------------- + -- ECSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Register_Masks ECSPI Register Masks + * @{ + */ + +/*! @name RXDATA - Receive Data Register */ +/*! @{ */ + +#define ECSPI_RXDATA_ECSPI_RXDATA_MASK (0xFFFFFFFFU) +#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT (0U) +#define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_RXDATA_ECSPI_RXDATA_SHIFT)) & ECSPI_RXDATA_ECSPI_RXDATA_MASK) +/*! @} */ + +/*! @name TXDATA - Transmit Data Register */ +/*! @{ */ + +#define ECSPI_TXDATA_ECSPI_TXDATA_MASK (0xFFFFFFFFU) +#define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT (0U) +#define ECSPI_TXDATA_ECSPI_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TXDATA_ECSPI_TXDATA_SHIFT)) & ECSPI_TXDATA_ECSPI_TXDATA_MASK) +/*! @} */ + +/*! @name CONREG - Control Register */ +/*! @{ */ + +#define ECSPI_CONREG_EN_MASK (0x1U) +#define ECSPI_CONREG_EN_SHIFT (0U) +/*! EN + * 0b0..Disable the block. + * 0b1..Enable the block. + */ +#define ECSPI_CONREG_EN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_EN_SHIFT)) & ECSPI_CONREG_EN_MASK) + +#define ECSPI_CONREG_HT_MASK (0x2U) +#define ECSPI_CONREG_HT_SHIFT (1U) +/*! HT + * 0b0..Disable HT mode. + * 0b1..Enable HT mode. + */ +#define ECSPI_CONREG_HT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_HT_SHIFT)) & ECSPI_CONREG_HT_MASK) + +#define ECSPI_CONREG_XCH_MASK (0x4U) +#define ECSPI_CONREG_XCH_SHIFT (2U) +/*! XCH + * 0b0..Idle. + * 0b1..Initiates exchange (write) or busy (read). + */ +#define ECSPI_CONREG_XCH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_XCH_SHIFT)) & ECSPI_CONREG_XCH_MASK) + +#define ECSPI_CONREG_SMC_MASK (0x8U) +#define ECSPI_CONREG_SMC_SHIFT (3U) +/*! SMC + * 0b0..SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or + * multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL + * descriptions. + * 0b1..Immediately starts a SPI burst when data is written in TXFIFO. + */ +#define ECSPI_CONREG_SMC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_SMC_SHIFT)) & ECSPI_CONREG_SMC_MASK) + +#define ECSPI_CONREG_CHANNEL_MODE_MASK (0xF0U) +#define ECSPI_CONREG_CHANNEL_MODE_SHIFT (4U) +/*! CHANNEL_MODE + * 0b0000..Slave mode. + * 0b0001..Master mode. + */ +#define ECSPI_CONREG_CHANNEL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_MODE_SHIFT)) & ECSPI_CONREG_CHANNEL_MODE_MASK) + +#define ECSPI_CONREG_POST_DIVIDER_MASK (0xF00U) +#define ECSPI_CONREG_POST_DIVIDER_SHIFT (8U) +/*! POST_DIVIDER + * 0b0000..Divide by 1. + * 0b0001..Divide by 2. + * 0b0010..Divide by 4. + * 0b1110..Divide by 2 14 . + * 0b1111..Divide by 2 15 . + */ +#define ECSPI_CONREG_POST_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_POST_DIVIDER_SHIFT)) & ECSPI_CONREG_POST_DIVIDER_MASK) + +#define ECSPI_CONREG_PRE_DIVIDER_MASK (0xF000U) +#define ECSPI_CONREG_PRE_DIVIDER_SHIFT (12U) +/*! PRE_DIVIDER + * 0b0000..Divide by 1. + * 0b0001..Divide by 2. + * 0b0010..Divide by 3. + * 0b1101..Divide by 14. + * 0b1110..Divide by 15. + * 0b1111..Divide by 16. + */ +#define ECSPI_CONREG_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_PRE_DIVIDER_SHIFT)) & ECSPI_CONREG_PRE_DIVIDER_MASK) + +#define ECSPI_CONREG_DRCTL_MASK (0x30000U) +#define ECSPI_CONREG_DRCTL_SHIFT (16U) +/*! DRCTL + * 0b00..The SPI_RDY signal is a don't care. + * 0b01..Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered). + * 0b10..Burst will be triggered by a low level of the SPI_RDY signal (level-triggered). + * 0b11..Reserved. + */ +#define ECSPI_CONREG_DRCTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_DRCTL_SHIFT)) & ECSPI_CONREG_DRCTL_MASK) + +#define ECSPI_CONREG_CHANNEL_SELECT_MASK (0xC0000U) +#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT (18U) +/*! CHANNEL_SELECT + * 0b00..Channel 0 is selected. Chip Select 0 (SS0) will be asserted. + * 0b01..Channel 1 is selected. Chip Select 1 (SS1) will be asserted. + * 0b10..Channel 2 is selected. Chip Select 2 (SS2) will be asserted. + * 0b11..Channel 3 is selected. Chip Select 3 (SS3) will be asserted. + */ +#define ECSPI_CONREG_CHANNEL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_SELECT_SHIFT)) & ECSPI_CONREG_CHANNEL_SELECT_MASK) + +#define ECSPI_CONREG_BURST_LENGTH_MASK (0xFFF00000U) +#define ECSPI_CONREG_BURST_LENGTH_SHIFT (20U) +/*! BURST_LENGTH + * 0b000000000000..A SPI burst contains the 1 LSB in a word. + * 0b000000000001..A SPI burst contains the 2 LSB in a word. + * 0b000000000010..A SPI burst contains the 3 LSB in a word. + * 0b000000011111..A SPI burst contains all 32 bits in a word. + * 0b000000100000..A SPI burst contains the 1 LSB in first word and all 32 bits in second word. + * 0b000000100001..A SPI burst contains the 2 LSB in first word and all 32 bits in second word. + * 0b111111111110..A SPI burst contains the 31 LSB in first word and 2^7 -1 words. + * 0b111111111111..A SPI burst contains 2^7 words. + */ +#define ECSPI_CONREG_BURST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_BURST_LENGTH_SHIFT)) & ECSPI_CONREG_BURST_LENGTH_MASK) +/*! @} */ + +/*! @name CONFIGREG - Config Register */ +/*! @{ */ + +#define ECSPI_CONFIGREG_SCLK_PHA_MASK (0xFU) +#define ECSPI_CONFIGREG_SCLK_PHA_SHIFT (0U) +/*! SCLK_PHA + * 0b0000..Phase 0 operation. + * 0b0001..Phase 1 operation. + */ +#define ECSPI_CONFIGREG_SCLK_PHA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_PHA_SHIFT)) & ECSPI_CONFIGREG_SCLK_PHA_MASK) + +#define ECSPI_CONFIGREG_SCLK_POL_MASK (0xF0U) +#define ECSPI_CONFIGREG_SCLK_POL_SHIFT (4U) +/*! SCLK_POL + * 0b0000..Active high polarity (0 = Idle). + * 0b0001..Active low polarity (1 = Idle). + */ +#define ECSPI_CONFIGREG_SCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_POL_SHIFT)) & ECSPI_CONFIGREG_SCLK_POL_MASK) + +#define ECSPI_CONFIGREG_SS_CTL_MASK (0xF00U) +#define ECSPI_CONFIGREG_SS_CTL_SHIFT (8U) +/*! SS_CTL + * 0b0000..In master mode - only one SPI burst will be transmitted. + * 0b0001..In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be + * transmitted. The SPI transfer will automatically stop when the TXFIFO is empty. + * 0b0000..In slave mode - an SPI burst is completed when the number of bits received in the shift register is + * equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of the first + * received word are valid. All bits subsequent to the first received word in RXFIFO are valid. + * 0b0001..Reserved + */ +#define ECSPI_CONFIGREG_SS_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_CTL_SHIFT)) & ECSPI_CONFIGREG_SS_CTL_MASK) + +#define ECSPI_CONFIGREG_SS_POL_MASK (0xF000U) +#define ECSPI_CONFIGREG_SS_POL_SHIFT (12U) +/*! SS_POL + * 0b0000..Active low. + * 0b0001..Active high. + */ +#define ECSPI_CONFIGREG_SS_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_POL_SHIFT)) & ECSPI_CONFIGREG_SS_POL_MASK) + +#define ECSPI_CONFIGREG_DATA_CTL_MASK (0xF0000U) +#define ECSPI_CONFIGREG_DATA_CTL_SHIFT (16U) +/*! DATA_CTL + * 0b0000..Stay high. + * 0b0001..Stay low. + */ +#define ECSPI_CONFIGREG_DATA_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_DATA_CTL_SHIFT)) & ECSPI_CONFIGREG_DATA_CTL_MASK) + +#define ECSPI_CONFIGREG_SCLK_CTL_MASK (0xF00000U) +#define ECSPI_CONFIGREG_SCLK_CTL_SHIFT (20U) +/*! SCLK_CTL + * 0b0000..Stay low. + * 0b0001..Stay high. + */ +#define ECSPI_CONFIGREG_SCLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_CTL_SHIFT)) & ECSPI_CONFIGREG_SCLK_CTL_MASK) + +#define ECSPI_CONFIGREG_HT_LENGTH_MASK (0x1F000000U) +#define ECSPI_CONFIGREG_HT_LENGTH_SHIFT (24U) +#define ECSPI_CONFIGREG_HT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_HT_LENGTH_SHIFT)) & ECSPI_CONFIGREG_HT_LENGTH_MASK) +/*! @} */ + +/*! @name INTREG - Interrupt Control Register */ +/*! @{ */ + +#define ECSPI_INTREG_TEEN_MASK (0x1U) +#define ECSPI_INTREG_TEEN_SHIFT (0U) +/*! TEEN + * 0b0..Disable + * 0b1..Enable + */ +#define ECSPI_INTREG_TEEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TEEN_SHIFT)) & ECSPI_INTREG_TEEN_MASK) + +#define ECSPI_INTREG_TDREN_MASK (0x2U) +#define ECSPI_INTREG_TDREN_SHIFT (1U) +/*! TDREN + * 0b0..Disable + * 0b1..Enable + */ +#define ECSPI_INTREG_TDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TDREN_SHIFT)) & ECSPI_INTREG_TDREN_MASK) + +#define ECSPI_INTREG_TFEN_MASK (0x4U) +#define ECSPI_INTREG_TFEN_SHIFT (2U) +/*! TFEN + * 0b0..Disable + * 0b1..Enable + */ +#define ECSPI_INTREG_TFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TFEN_SHIFT)) & ECSPI_INTREG_TFEN_MASK) + +#define ECSPI_INTREG_RREN_MASK (0x8U) +#define ECSPI_INTREG_RREN_SHIFT (3U) +/*! RREN + * 0b0..Disable + * 0b1..Enable + */ +#define ECSPI_INTREG_RREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RREN_SHIFT)) & ECSPI_INTREG_RREN_MASK) + +#define ECSPI_INTREG_RDREN_MASK (0x10U) +#define ECSPI_INTREG_RDREN_SHIFT (4U) +/*! RDREN + * 0b0..Disable + * 0b1..Enable + */ +#define ECSPI_INTREG_RDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RDREN_SHIFT)) & ECSPI_INTREG_RDREN_MASK) + +#define ECSPI_INTREG_RFEN_MASK (0x20U) +#define ECSPI_INTREG_RFEN_SHIFT (5U) +/*! RFEN + * 0b0..Disable + * 0b1..Enable + */ +#define ECSPI_INTREG_RFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RFEN_SHIFT)) & ECSPI_INTREG_RFEN_MASK) + +#define ECSPI_INTREG_ROEN_MASK (0x40U) +#define ECSPI_INTREG_ROEN_SHIFT (6U) +/*! ROEN + * 0b0..Disable + * 0b1..Enable + */ +#define ECSPI_INTREG_ROEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_ROEN_SHIFT)) & ECSPI_INTREG_ROEN_MASK) + +#define ECSPI_INTREG_TCEN_MASK (0x80U) +#define ECSPI_INTREG_TCEN_SHIFT (7U) +/*! TCEN + * 0b0..Disable + * 0b1..Enable + */ +#define ECSPI_INTREG_TCEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TCEN_SHIFT)) & ECSPI_INTREG_TCEN_MASK) +/*! @} */ + +/*! @name DMAREG - DMA Control Register */ +/*! @{ */ + +#define ECSPI_DMAREG_TX_THRESHOLD_MASK (0x3FU) +#define ECSPI_DMAREG_TX_THRESHOLD_SHIFT (0U) +#define ECSPI_DMAREG_TX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_TX_THRESHOLD_MASK) + +#define ECSPI_DMAREG_TEDEN_MASK (0x80U) +#define ECSPI_DMAREG_TEDEN_SHIFT (7U) +/*! TEDEN + * 0b0..Disable + * 0b1..Enable + */ +#define ECSPI_DMAREG_TEDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TEDEN_SHIFT)) & ECSPI_DMAREG_TEDEN_MASK) + +#define ECSPI_DMAREG_RX_THRESHOLD_MASK (0x3F0000U) +#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT (16U) +#define ECSPI_DMAREG_RX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_RX_THRESHOLD_MASK) + +#define ECSPI_DMAREG_RXDEN_MASK (0x800000U) +#define ECSPI_DMAREG_RXDEN_SHIFT (23U) +/*! RXDEN + * 0b0..Disable + * 0b1..Enable + */ +#define ECSPI_DMAREG_RXDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXDEN_SHIFT)) & ECSPI_DMAREG_RXDEN_MASK) + +#define ECSPI_DMAREG_RX_DMA_LENGTH_MASK (0x3F000000U) +#define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT (24U) +#define ECSPI_DMAREG_RX_DMA_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT)) & ECSPI_DMAREG_RX_DMA_LENGTH_MASK) + +#define ECSPI_DMAREG_RXTDEN_MASK (0x80000000U) +#define ECSPI_DMAREG_RXTDEN_SHIFT (31U) +/*! RXTDEN + * 0b0..Disable + * 0b1..Enable + */ +#define ECSPI_DMAREG_RXTDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXTDEN_SHIFT)) & ECSPI_DMAREG_RXTDEN_MASK) +/*! @} */ + +/*! @name STATREG - Status Register */ +/*! @{ */ + +#define ECSPI_STATREG_TE_MASK (0x1U) +#define ECSPI_STATREG_TE_SHIFT (0U) +/*! TE + * 0b0..TXFIFO contains one or more words. + * 0b1..TXFIFO is empty. + */ +#define ECSPI_STATREG_TE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TE_SHIFT)) & ECSPI_STATREG_TE_MASK) + +#define ECSPI_STATREG_TDR_MASK (0x2U) +#define ECSPI_STATREG_TDR_SHIFT (1U) +/*! TDR + * 0b0..Number of valid data slots in TXFIFO is greater than TX_THRESHOLD. + * 0b1..Number of valid data slots in TXFIFO is not greater than TX_THRESHOLD. + */ +#define ECSPI_STATREG_TDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TDR_SHIFT)) & ECSPI_STATREG_TDR_MASK) + +#define ECSPI_STATREG_TF_MASK (0x4U) +#define ECSPI_STATREG_TF_SHIFT (2U) +/*! TF + * 0b0..TXFIFO is not Full. + * 0b1..TXFIFO is Full. + */ +#define ECSPI_STATREG_TF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TF_SHIFT)) & ECSPI_STATREG_TF_MASK) + +#define ECSPI_STATREG_RR_MASK (0x8U) +#define ECSPI_STATREG_RR_SHIFT (3U) +/*! RR + * 0b0..No valid data in RXFIFO. + * 0b1..More than 1 word in RXFIFO. + */ +#define ECSPI_STATREG_RR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RR_SHIFT)) & ECSPI_STATREG_RR_MASK) + +#define ECSPI_STATREG_RDR_MASK (0x10U) +#define ECSPI_STATREG_RDR_SHIFT (4U) +/*! RDR + * 0b0..When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + * 0b1..When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists. + * 0b0..When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + * 0b1..When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD. + */ +#define ECSPI_STATREG_RDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RDR_SHIFT)) & ECSPI_STATREG_RDR_MASK) + +#define ECSPI_STATREG_RF_MASK (0x20U) +#define ECSPI_STATREG_RF_SHIFT (5U) +/*! RF + * 0b0..Not Full. + * 0b1..Full. + */ +#define ECSPI_STATREG_RF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RF_SHIFT)) & ECSPI_STATREG_RF_MASK) + +#define ECSPI_STATREG_RO_MASK (0x40U) +#define ECSPI_STATREG_RO_SHIFT (6U) +/*! RO + * 0b0..RXFIFO has no overflow. + * 0b1..RXFIFO has overflowed. + */ +#define ECSPI_STATREG_RO(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RO_SHIFT)) & ECSPI_STATREG_RO_MASK) + +#define ECSPI_STATREG_TC_MASK (0x80U) +#define ECSPI_STATREG_TC_SHIFT (7U) +/*! TC + * 0b0..Transfer in progress. + * 0b1..Transfer completed. + */ +#define ECSPI_STATREG_TC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TC_SHIFT)) & ECSPI_STATREG_TC_MASK) +/*! @} */ + +/*! @name PERIODREG - Sample Period Control Register */ +/*! @{ */ + +#define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK (0x7FFFU) +#define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT (0U) +/*! SAMPLE_PERIOD + * 0b000000000000000..0 wait states inserted + * 0b000000000000001..1 wait state inserted + * 0b111111111111110..32766 wait states inserted + * 0b111111111111111..32767 wait states inserted + */ +#define ECSPI_PERIODREG_SAMPLE_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT)) & ECSPI_PERIODREG_SAMPLE_PERIOD_MASK) + +#define ECSPI_PERIODREG_CSRC_MASK (0x8000U) +#define ECSPI_PERIODREG_CSRC_SHIFT (15U) +/*! CSRC + * 0b0..SPI Clock (SCLK) + * 0b1..Low-Frequency Reference Clock (32.768 KHz) + */ +#define ECSPI_PERIODREG_CSRC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSRC_SHIFT)) & ECSPI_PERIODREG_CSRC_MASK) + +#define ECSPI_PERIODREG_CSD_CTL_MASK (0x3F0000U) +#define ECSPI_PERIODREG_CSD_CTL_SHIFT (16U) +#define ECSPI_PERIODREG_CSD_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSD_CTL_SHIFT)) & ECSPI_PERIODREG_CSD_CTL_MASK) +/*! @} */ + +/*! @name TESTREG - Test Control Register */ +/*! @{ */ + +#define ECSPI_TESTREG_TXCNT_MASK (0x7FU) +#define ECSPI_TESTREG_TXCNT_SHIFT (0U) +#define ECSPI_TESTREG_TXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_TXCNT_SHIFT)) & ECSPI_TESTREG_TXCNT_MASK) + +#define ECSPI_TESTREG_RXCNT_MASK (0x7F00U) +#define ECSPI_TESTREG_RXCNT_SHIFT (8U) +#define ECSPI_TESTREG_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_RXCNT_SHIFT)) & ECSPI_TESTREG_RXCNT_MASK) + +#define ECSPI_TESTREG_LBC_MASK (0x80000000U) +#define ECSPI_TESTREG_LBC_SHIFT (31U) +/*! LBC + * 0b0..Not connected. + * 0b1..Transmitter and receiver sections internally connected for Loopback. + */ +#define ECSPI_TESTREG_LBC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_LBC_SHIFT)) & ECSPI_TESTREG_LBC_MASK) +/*! @} */ + +/*! @name MSGDATA - Message Data Register */ +/*! @{ */ + +#define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK (0xFFFFFFFFU) +#define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT (0U) +#define ECSPI_MSGDATA_ECSPI_MSGDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT)) & ECSPI_MSGDATA_ECSPI_MSGDATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ECSPI_Register_Masks */ + + +/* ECSPI - Peripheral instance base addresses */ +/** Peripheral ECSPI1 base address */ +#define ECSPI1_BASE (0x30820000u) +/** Peripheral ECSPI1 base pointer */ +#define ECSPI1 ((ECSPI_Type *)ECSPI1_BASE) +/** Peripheral ECSPI2 base address */ +#define ECSPI2_BASE (0x30830000u) +/** Peripheral ECSPI2 base pointer */ +#define ECSPI2 ((ECSPI_Type *)ECSPI2_BASE) +/** Peripheral ECSPI3 base address */ +#define ECSPI3_BASE (0x30840000u) +/** Peripheral ECSPI3 base pointer */ +#define ECSPI3 ((ECSPI_Type *)ECSPI3_BASE) +/** Array initializer of ECSPI peripheral base addresses */ +#define ECSPI_BASE_ADDRS { 0u, ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE } +/** Array initializer of ECSPI peripheral base pointers */ +#define ECSPI_BASE_PTRS { (ECSPI_Type *)0u, ECSPI1, ECSPI2, ECSPI3 } +/** Interrupt vectors for the ECSPI peripheral type */ +#define ECSPI_IRQS { NotAvail_IRQn, ECSPI1_IRQn, ECSPI2_IRQn, ECSPI3_IRQn } + +/*! + * @} + */ /* end of group ECSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ + __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */ + uint8_t RESERVED_2[12]; + __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ + __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ + uint8_t RESERVED_6[60]; + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ + uint8_t RESERVED_7[28]; + __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ + __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ + __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ + __IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */ + uint8_t RESERVED_8[4]; + __IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_9[12]; + __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ + __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ + __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ + __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ + uint8_t RESERVED_10[28]; + __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ + uint8_t RESERVED_11[24]; + __IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */ + __IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */ + __IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */ + __IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */ + __IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */ + __IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */ + uint8_t RESERVED_12[8]; + __IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */ + uint8_t RESERVED_13[4]; + __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ + __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ + __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ + __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ + __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ + __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ + __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ + __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ + __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ + __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ + __IO uint32_t RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */ + uint8_t RESERVED_15[8]; + __IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */ + __IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */ + __IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */ + __IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */ + __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */ + __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */ + uint8_t RESERVED_16[12]; + uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ + __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ + __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ + __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ + __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ + __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ + __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ + __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ + __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ + __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ + __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ + __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ + __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ + __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ + __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ + __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ + __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ + uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ + __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ + __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ + __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ + __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ + __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ + __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ + __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ + __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ + __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ + __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ + uint8_t RESERVED_17[12]; + __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ + __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ + __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ + __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ + __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ + __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ + __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ + __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ + uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ + __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ + __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ + __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ + __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ + __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ + __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ + __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ + __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ + __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ + __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ + __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ + __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ + __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ + uint8_t RESERVED_18[284]; + __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_19[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/*! @name EIR - Interrupt Event Register */ +/*! @{ */ + +#define ENET_EIR_RXB1_MASK (0x1U) +#define ENET_EIR_RXB1_SHIFT (0U) +/*! RXB1 - Receive buffer interrupt, class 1 + */ +#define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK) + +#define ENET_EIR_RXF1_MASK (0x2U) +#define ENET_EIR_RXF1_SHIFT (1U) +/*! RXF1 - Receive frame interrupt, class 1 + */ +#define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK) + +#define ENET_EIR_TXB1_MASK (0x4U) +#define ENET_EIR_TXB1_SHIFT (2U) +/*! TXB1 - Transmit buffer interrupt, class 1 + */ +#define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK) + +#define ENET_EIR_TXF1_MASK (0x8U) +#define ENET_EIR_TXF1_SHIFT (3U) +/*! TXF1 - Transmit frame interrupt, class 1 + */ +#define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK) + +#define ENET_EIR_RXB2_MASK (0x10U) +#define ENET_EIR_RXB2_SHIFT (4U) +/*! RXB2 - Receive buffer interrupt, class 2 + */ +#define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK) + +#define ENET_EIR_RXF2_MASK (0x20U) +#define ENET_EIR_RXF2_SHIFT (5U) +/*! RXF2 - Receive frame interrupt, class 2 + */ +#define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK) + +#define ENET_EIR_TXB2_MASK (0x40U) +#define ENET_EIR_TXB2_SHIFT (6U) +/*! TXB2 - Transmit buffer interrupt, class 2 + */ +#define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK) + +#define ENET_EIR_TXF2_MASK (0x80U) +#define ENET_EIR_TXF2_SHIFT (7U) +/*! TXF2 - Transmit frame interrupt, class 2 + */ +#define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK) + +#define ENET_EIR_RXFLUSH_0_MASK (0x1000U) +#define ENET_EIR_RXFLUSH_0_SHIFT (12U) +#define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK) + +#define ENET_EIR_RXFLUSH_1_MASK (0x2000U) +#define ENET_EIR_RXFLUSH_1_SHIFT (13U) +#define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK) + +#define ENET_EIR_RXFLUSH_2_MASK (0x4000U) +#define ENET_EIR_RXFLUSH_2_SHIFT (14U) +#define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK) + +#define ENET_EIR_TS_TIMER_MASK (0x8000U) +#define ENET_EIR_TS_TIMER_SHIFT (15U) +/*! TS_TIMER - Timestamp Timer + */ +#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) + +#define ENET_EIR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIR_TS_AVAIL_SHIFT (16U) +/*! TS_AVAIL - Transmit Timestamp Available + */ +#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) + +#define ENET_EIR_WAKEUP_MASK (0x20000U) +#define ENET_EIR_WAKEUP_SHIFT (17U) +/*! WAKEUP - Node Wakeup Request Indication + */ +#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) + +#define ENET_EIR_PLR_MASK (0x40000U) +#define ENET_EIR_PLR_SHIFT (18U) +/*! PLR - Payload Receive Error + */ +#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) + +#define ENET_EIR_UN_MASK (0x80000U) +#define ENET_EIR_UN_SHIFT (19U) +/*! UN - Transmit FIFO Underrun + */ +#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) + +#define ENET_EIR_RL_MASK (0x100000U) +#define ENET_EIR_RL_SHIFT (20U) +/*! RL - Collision Retry Limit + */ +#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) + +#define ENET_EIR_LC_MASK (0x200000U) +#define ENET_EIR_LC_SHIFT (21U) +/*! LC - Late Collision + */ +#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) + +#define ENET_EIR_EBERR_MASK (0x400000U) +#define ENET_EIR_EBERR_SHIFT (22U) +/*! EBERR - Ethernet Bus Error + */ +#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) + +#define ENET_EIR_MII_MASK (0x800000U) +#define ENET_EIR_MII_SHIFT (23U) +/*! MII - MII Interrupt. + */ +#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) + +#define ENET_EIR_RXB_MASK (0x1000000U) +#define ENET_EIR_RXB_SHIFT (24U) +/*! RXB - Receive Buffer Interrupt + */ +#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) + +#define ENET_EIR_RXF_MASK (0x2000000U) +#define ENET_EIR_RXF_SHIFT (25U) +/*! RXF - Receive Frame Interrupt + */ +#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) + +#define ENET_EIR_TXB_MASK (0x4000000U) +#define ENET_EIR_TXB_SHIFT (26U) +/*! TXB - Transmit Buffer Interrupt + */ +#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) + +#define ENET_EIR_TXF_MASK (0x8000000U) +#define ENET_EIR_TXF_SHIFT (27U) +/*! TXF - Transmit Frame Interrupt + */ +#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) + +#define ENET_EIR_GRA_MASK (0x10000000U) +#define ENET_EIR_GRA_SHIFT (28U) +/*! GRA - Graceful Stop Complete + */ +#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) + +#define ENET_EIR_BABT_MASK (0x20000000U) +#define ENET_EIR_BABT_SHIFT (29U) +/*! BABT - Babbling Transmit Error + */ +#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) + +#define ENET_EIR_BABR_MASK (0x40000000U) +#define ENET_EIR_BABR_SHIFT (30U) +/*! BABR - Babbling Receive Error + */ +#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) +/*! @} */ + +/*! @name EIMR - Interrupt Mask Register */ +/*! @{ */ + +#define ENET_EIMR_RXB1_MASK (0x1U) +#define ENET_EIMR_RXB1_SHIFT (0U) +/*! RXB1 - Receive buffer interrupt, class 1 + */ +#define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK) + +#define ENET_EIMR_RXF1_MASK (0x2U) +#define ENET_EIMR_RXF1_SHIFT (1U) +/*! RXF1 - Receive frame interrupt, class 1 + */ +#define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK) + +#define ENET_EIMR_TXB1_MASK (0x4U) +#define ENET_EIMR_TXB1_SHIFT (2U) +/*! TXB1 - Transmit buffer interrupt, class 1 + */ +#define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK) + +#define ENET_EIMR_TXF1_MASK (0x8U) +#define ENET_EIMR_TXF1_SHIFT (3U) +/*! TXF1 - Transmit frame interrupt, class 1 + */ +#define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK) + +#define ENET_EIMR_RXB2_MASK (0x10U) +#define ENET_EIMR_RXB2_SHIFT (4U) +/*! RXB2 - Receive buffer interrupt, class 2 + */ +#define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK) + +#define ENET_EIMR_RXF2_MASK (0x20U) +#define ENET_EIMR_RXF2_SHIFT (5U) +/*! RXF2 - Receive frame interrupt, class 2 + */ +#define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK) + +#define ENET_EIMR_TXB2_MASK (0x40U) +#define ENET_EIMR_TXB2_SHIFT (6U) +/*! TXB2 - Transmit buffer interrupt, class 2 + */ +#define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK) + +#define ENET_EIMR_TXF2_MASK (0x80U) +#define ENET_EIMR_TXF2_SHIFT (7U) +/*! TXF2 - Transmit frame interrupt, class 2 + */ +#define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK) + +#define ENET_EIMR_RXFLUSH_0_MASK (0x1000U) +#define ENET_EIMR_RXFLUSH_0_SHIFT (12U) +#define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK) + +#define ENET_EIMR_RXFLUSH_1_MASK (0x2000U) +#define ENET_EIMR_RXFLUSH_1_SHIFT (13U) +#define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK) + +#define ENET_EIMR_RXFLUSH_2_MASK (0x4000U) +#define ENET_EIMR_RXFLUSH_2_SHIFT (14U) +#define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK) + +#define ENET_EIMR_TS_TIMER_MASK (0x8000U) +#define ENET_EIMR_TS_TIMER_SHIFT (15U) +/*! TS_TIMER - TS_TIMER Interrupt Mask + */ +#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) + +#define ENET_EIMR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIMR_TS_AVAIL_SHIFT (16U) +/*! TS_AVAIL - TS_AVAIL Interrupt Mask + */ +#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) + +#define ENET_EIMR_WAKEUP_MASK (0x20000U) +#define ENET_EIMR_WAKEUP_SHIFT (17U) +/*! WAKEUP - WAKEUP Interrupt Mask + */ +#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) + +#define ENET_EIMR_PLR_MASK (0x40000U) +#define ENET_EIMR_PLR_SHIFT (18U) +/*! PLR - PLR Interrupt Mask + */ +#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) + +#define ENET_EIMR_UN_MASK (0x80000U) +#define ENET_EIMR_UN_SHIFT (19U) +/*! UN - UN Interrupt Mask + */ +#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) + +#define ENET_EIMR_RL_MASK (0x100000U) +#define ENET_EIMR_RL_SHIFT (20U) +/*! RL - RL Interrupt Mask + */ +#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) + +#define ENET_EIMR_LC_MASK (0x200000U) +#define ENET_EIMR_LC_SHIFT (21U) +/*! LC - LC Interrupt Mask + */ +#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) + +#define ENET_EIMR_EBERR_MASK (0x400000U) +#define ENET_EIMR_EBERR_SHIFT (22U) +/*! EBERR - EBERR Interrupt Mask + */ +#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) + +#define ENET_EIMR_MII_MASK (0x800000U) +#define ENET_EIMR_MII_SHIFT (23U) +/*! MII - MII Interrupt Mask + */ +#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) + +#define ENET_EIMR_RXB_MASK (0x1000000U) +#define ENET_EIMR_RXB_SHIFT (24U) +/*! RXB - RXB Interrupt Mask + */ +#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) + +#define ENET_EIMR_RXF_MASK (0x2000000U) +#define ENET_EIMR_RXF_SHIFT (25U) +/*! RXF - RXF Interrupt Mask + */ +#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) + +#define ENET_EIMR_TXB_MASK (0x4000000U) +#define ENET_EIMR_TXB_SHIFT (26U) +/*! TXB - TXB Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) + +#define ENET_EIMR_TXF_MASK (0x8000000U) +#define ENET_EIMR_TXF_SHIFT (27U) +/*! TXF - TXF Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) + +#define ENET_EIMR_GRA_MASK (0x10000000U) +#define ENET_EIMR_GRA_SHIFT (28U) +/*! GRA - GRA Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) + +#define ENET_EIMR_BABT_MASK (0x20000000U) +#define ENET_EIMR_BABT_SHIFT (29U) +/*! BABT - BABT Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) + +#define ENET_EIMR_BABR_MASK (0x40000000U) +#define ENET_EIMR_BABR_SHIFT (30U) +/*! BABR - BABR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) +/*! @} */ + +/*! @name RDAR - Receive Descriptor Active Register - Ring 0 */ +/*! @{ */ + +#define ENET_RDAR_RDAR_MASK (0x1000000U) +#define ENET_RDAR_RDAR_SHIFT (24U) +/*! RDAR - Receive Descriptor Active + */ +#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) +/*! @} */ + +/*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */ +/*! @{ */ + +#define ENET_TDAR_TDAR_MASK (0x1000000U) +#define ENET_TDAR_TDAR_SHIFT (24U) +/*! TDAR - Transmit Descriptor Active + */ +#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) +/*! @} */ + +/*! @name ECR - Ethernet Control Register */ +/*! @{ */ + +#define ENET_ECR_RESET_MASK (0x1U) +#define ENET_ECR_RESET_SHIFT (0U) +/*! RESET - Ethernet MAC Reset + */ +#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) + +#define ENET_ECR_ETHEREN_MASK (0x2U) +#define ENET_ECR_ETHEREN_SHIFT (1U) +/*! ETHEREN - Ethernet Enable + * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + * 0b1..MAC is enabled, and reception and transmission are possible. + */ +#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) + +#define ENET_ECR_MAGICEN_MASK (0x4U) +#define ENET_ECR_MAGICEN_SHIFT (2U) +/*! MAGICEN - Magic Packet Detection Enable + * 0b0..Magic detection logic disabled. + * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + */ +#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) + +#define ENET_ECR_SLEEP_MASK (0x8U) +#define ENET_ECR_SLEEP_SHIFT (3U) +/*! SLEEP - Sleep Mode Enable + * 0b0..Normal operating mode. + * 0b1..Sleep mode. + */ +#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) + +#define ENET_ECR_EN1588_MASK (0x10U) +#define ENET_ECR_EN1588_SHIFT (4U) +/*! EN1588 - EN1588 Enable + * 0b0..Legacy FEC buffer descriptors and functions enabled. + * 0b1..Enhanced frame time-stamping functions enabled. + */ +#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) + +#define ENET_ECR_SPEED_MASK (0x20U) +#define ENET_ECR_SPEED_SHIFT (5U) +/*! SPEED + * 0b0..10/100-Mbit/s mode + * 0b1..1000-Mbit/s mode + */ +#define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK) + +#define ENET_ECR_DBGEN_MASK (0x40U) +#define ENET_ECR_DBGEN_SHIFT (6U) +/*! DBGEN - Debug Enable + * 0b0..MAC continues operation in debug mode. + * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. + */ +#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) + +#define ENET_ECR_DBSWP_MASK (0x100U) +#define ENET_ECR_DBSWP_SHIFT (8U) +/*! DBSWP - Descriptor Byte Swapping Enable + * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. + * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. + */ +#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) + +#define ENET_ECR_SVLANEN_MASK (0x200U) +#define ENET_ECR_SVLANEN_SHIFT (9U) +/*! SVLANEN - S-VLAN enable + * 0b0..Only the EtherType 0x8100 will be considered for VLAN detection. + * 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in + * receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the + * classification match comparators, RCMRn. + */ +#define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK) + +#define ENET_ECR_VLANUSE2ND_MASK (0x400U) +#define ENET_ECR_VLANUSE2ND_SHIFT (10U) +/*! VLANUSE2ND - VLAN use second tag + * 0b0..Always extract data from the first VLAN tag if it exists. + * 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A + * double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The + * second tag must be a C-VLAN + */ +#define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK) + +#define ENET_ECR_SVLANDBL_MASK (0x800U) +#define ENET_ECR_SVLANDBL_SHIFT (11U) +/*! SVLANDBL - S-VLAN double tag + */ +#define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK) +/*! @} */ + +/*! @name MMFR - MII Management Frame Register */ +/*! @{ */ + +#define ENET_MMFR_DATA_MASK (0xFFFFU) +#define ENET_MMFR_DATA_SHIFT (0U) +/*! DATA - Management Frame Data + */ +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) + +#define ENET_MMFR_TA_MASK (0x30000U) +#define ENET_MMFR_TA_SHIFT (16U) +/*! TA - Turn Around + */ +#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) + +#define ENET_MMFR_RA_MASK (0x7C0000U) +#define ENET_MMFR_RA_SHIFT (18U) +/*! RA - Register Address + */ +#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) + +#define ENET_MMFR_PA_MASK (0xF800000U) +#define ENET_MMFR_PA_SHIFT (23U) +/*! PA - PHY Address + */ +#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) + +#define ENET_MMFR_OP_MASK (0x30000000U) +#define ENET_MMFR_OP_SHIFT (28U) +/*! OP - Operation Code + */ +#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) + +#define ENET_MMFR_ST_MASK (0xC0000000U) +#define ENET_MMFR_ST_SHIFT (30U) +/*! ST - Start Of Frame Delimiter + */ +#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) +/*! @} */ + +/*! @name MSCR - MII Speed Control Register */ +/*! @{ */ + +#define ENET_MSCR_MII_SPEED_MASK (0x7EU) +#define ENET_MSCR_MII_SPEED_SHIFT (1U) +/*! MII_SPEED - MII Speed + */ +#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) + +#define ENET_MSCR_DIS_PRE_MASK (0x80U) +#define ENET_MSCR_DIS_PRE_SHIFT (7U) +/*! DIS_PRE - Disable Preamble + * 0b0..Preamble enabled. + * 0b1..Preamble (32 ones) is not prepended to the MII management frame. + */ +#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) + +#define ENET_MSCR_HOLDTIME_MASK (0x700U) +#define ENET_MSCR_HOLDTIME_SHIFT (8U) +/*! HOLDTIME - Hold time On MDIO Output + * 0b000..1 internal module clock cycle + * 0b001..2 internal module clock cycles + * 0b010..3 internal module clock cycles + * 0b111..8 internal module clock cycles + */ +#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) +/*! @} */ + +/*! @name MIBC - MIB Control Register */ +/*! @{ */ + +#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) +#define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +/*! MIB_CLEAR - MIB Clear + * 0b0..See note above. + * 0b1..All statistics counters are reset to 0. + */ +#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) + +#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) +#define ENET_MIBC_MIB_IDLE_SHIFT (30U) +/*! MIB_IDLE - MIB Idle + * 0b0..The MIB block is updating MIB counters. + * 0b1..The MIB block is not currently updating any MIB counters. + */ +#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) + +#define ENET_MIBC_MIB_DIS_MASK (0x80000000U) +#define ENET_MIBC_MIB_DIS_SHIFT (31U) +/*! MIB_DIS - Disable MIB Logic + * 0b0..MIB logic is enabled. + * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + */ +#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) +/*! @} */ + +/*! @name RCR - Receive Control Register */ +/*! @{ */ + +#define ENET_RCR_LOOP_MASK (0x1U) +#define ENET_RCR_LOOP_SHIFT (0U) +/*! LOOP - Internal Loopback + * 0b0..Loopback disabled. + * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + */ +#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) + +#define ENET_RCR_DRT_MASK (0x2U) +#define ENET_RCR_DRT_SHIFT (1U) +/*! DRT - Disable Receive On Transmit + * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + */ +#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) + +#define ENET_RCR_MII_MODE_MASK (0x4U) +#define ENET_RCR_MII_MODE_SHIFT (2U) +/*! MII_MODE - Media Independent Interface Mode + * 0b0..Reserved. + * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. + */ +#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) + +#define ENET_RCR_PROM_MASK (0x8U) +#define ENET_RCR_PROM_SHIFT (3U) +/*! PROM - Promiscuous Mode + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) + +#define ENET_RCR_BC_REJ_MASK (0x10U) +#define ENET_RCR_BC_REJ_SHIFT (4U) +/*! BC_REJ - Broadcast Frame Reject + */ +#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) + +#define ENET_RCR_FCE_MASK (0x20U) +#define ENET_RCR_FCE_SHIFT (5U) +/*! FCE - Flow Control Enable + */ +#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) + +#define ENET_RCR_RGMII_EN_MASK (0x40U) +#define ENET_RCR_RGMII_EN_SHIFT (6U) +/*! RGMII_EN - RGMII Mode Enable + * 0b0..MAC configured for non-RGMII operation + * 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If + * ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode. + */ +#define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK) + +#define ENET_RCR_RMII_MODE_MASK (0x100U) +#define ENET_RCR_RMII_MODE_SHIFT (8U) +/*! RMII_MODE - RMII Mode Enable + * 0b0..MAC configured for MII mode. + * 0b1..MAC configured for RMII operation. + */ +#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) + +#define ENET_RCR_RMII_10T_MASK (0x200U) +#define ENET_RCR_RMII_10T_SHIFT (9U) +/*! RMII_10T + * 0b0..100-Mbit/s operation. + * 0b1..10-Mbit/s operation. + */ +#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) + +#define ENET_RCR_PADEN_MASK (0x1000U) +#define ENET_RCR_PADEN_SHIFT (12U) +/*! PADEN - Enable Frame Padding Remove On Receive + * 0b0..No padding is removed on receive by the MAC. + * 0b1..Padding is removed from received frames. + */ +#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) + +#define ENET_RCR_PAUFWD_MASK (0x2000U) +#define ENET_RCR_PAUFWD_SHIFT (13U) +/*! PAUFWD - Terminate/Forward Pause Frames + * 0b0..Pause frames are terminated and discarded in the MAC. + * 0b1..Pause frames are forwarded to the user application. + */ +#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) + +#define ENET_RCR_CRCFWD_MASK (0x4000U) +#define ENET_RCR_CRCFWD_SHIFT (14U) +/*! CRCFWD - Terminate/Forward Received CRC + * 0b0..The CRC field of received frames is transmitted to the user application. + * 0b1..The CRC field is stripped from the frame. + */ +#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) + +#define ENET_RCR_CFEN_MASK (0x8000U) +#define ENET_RCR_CFEN_SHIFT (15U) +/*! CFEN - MAC Control Frame Enable + * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + */ +#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) + +#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) +#define ENET_RCR_MAX_FL_SHIFT (16U) +/*! MAX_FL - Maximum Frame Length + */ +#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) + +#define ENET_RCR_NLC_MASK (0x40000000U) +#define ENET_RCR_NLC_SHIFT (30U) +/*! NLC - Payload Length Check Disable + * 0b0..The payload length check is disabled. + * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. + */ +#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) + +#define ENET_RCR_GRS_MASK (0x80000000U) +#define ENET_RCR_GRS_SHIFT (31U) +/*! GRS - Graceful Receive Stopped + */ +#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) +/*! @} */ + +/*! @name TCR - Transmit Control Register */ +/*! @{ */ + +#define ENET_TCR_GTS_MASK (0x1U) +#define ENET_TCR_GTS_SHIFT (0U) +/*! GTS - Graceful Transmit Stop + */ +#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) + +#define ENET_TCR_FDEN_MASK (0x4U) +#define ENET_TCR_FDEN_SHIFT (2U) +/*! FDEN - Full-Duplex Enable + */ +#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) + +#define ENET_TCR_TFC_PAUSE_MASK (0x8U) +#define ENET_TCR_TFC_PAUSE_SHIFT (3U) +/*! TFC_PAUSE - Transmit Frame Control Pause + * 0b0..No PAUSE frame transmitted. + * 0b1..The MAC stops transmission of data frames after the current transmission is complete. + */ +#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) + +#define ENET_TCR_RFC_PAUSE_MASK (0x10U) +#define ENET_TCR_RFC_PAUSE_SHIFT (4U) +/*! RFC_PAUSE - Receive Frame Control Pause + */ +#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) + +#define ENET_TCR_ADDSEL_MASK (0xE0U) +#define ENET_TCR_ADDSEL_SHIFT (5U) +/*! ADDSEL - Source MAC Address Select On Transmit + * 0b000..Node MAC address programmed on PADDR1/2 registers. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + */ +#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) + +#define ENET_TCR_ADDINS_MASK (0x100U) +#define ENET_TCR_ADDINS_SHIFT (8U) +/*! ADDINS - Set MAC Address On Transmit + * 0b0..The source MAC address is not modified by the MAC. + * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + */ +#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) + +#define ENET_TCR_CRCFWD_MASK (0x200U) +#define ENET_TCR_CRCFWD_SHIFT (9U) +/*! CRCFWD - Forward Frame From Application With CRC + * 0b0..TxBD[TC] controls whether the frame has a CRC from the application. + * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + */ +#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) +/*! @} */ + +/*! @name PALR - Physical Address Lower Register */ +/*! @{ */ + +#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) +#define ENET_PALR_PADDR1_SHIFT (0U) +/*! PADDR1 - Pause Address + */ +#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) +/*! @} */ + +/*! @name PAUR - Physical Address Upper Register */ +/*! @{ */ + +#define ENET_PAUR_TYPE_MASK (0xFFFFU) +#define ENET_PAUR_TYPE_SHIFT (0U) +/*! TYPE - Type Field In PAUSE Frames + */ +#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) + +#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) +#define ENET_PAUR_PADDR2_SHIFT (16U) +#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) +/*! @} */ + +/*! @name OPD - Opcode/Pause Duration Register */ +/*! @{ */ + +#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) +#define ENET_OPD_PAUSE_DUR_SHIFT (0U) +/*! PAUSE_DUR - Pause Duration + */ +#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) + +#define ENET_OPD_OPCODE_MASK (0xFFFF0000U) +#define ENET_OPD_OPCODE_SHIFT (16U) +/*! OPCODE - Opcode Field In PAUSE Frames + */ +#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) +/*! @} */ + +/*! @name TXIC - Transmit Interrupt Coalescing Register */ +/*! @{ */ + +#define ENET_TXIC_ICTT_MASK (0xFFFFU) +#define ENET_TXIC_ICTT_SHIFT (0U) +/*! ICTT - Interrupt coalescing timer threshold + */ +#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) + +#define ENET_TXIC_ICFT_MASK (0xFF00000U) +#define ENET_TXIC_ICFT_SHIFT (20U) +/*! ICFT - Interrupt coalescing frame count threshold + */ +#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) + +#define ENET_TXIC_ICCS_MASK (0x40000000U) +#define ENET_TXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ +#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) + +#define ENET_TXIC_ICEN_MASK (0x80000000U) +#define ENET_TXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ +#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) +/*! @} */ + +/* The count of ENET_TXIC */ +#define ENET_TXIC_COUNT (3U) + +/*! @name RXIC - Receive Interrupt Coalescing Register */ +/*! @{ */ + +#define ENET_RXIC_ICTT_MASK (0xFFFFU) +#define ENET_RXIC_ICTT_SHIFT (0U) +/*! ICTT - Interrupt coalescing timer threshold + */ +#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) + +#define ENET_RXIC_ICFT_MASK (0xFF00000U) +#define ENET_RXIC_ICFT_SHIFT (20U) +/*! ICFT - Interrupt coalescing frame count threshold + */ +#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) + +#define ENET_RXIC_ICCS_MASK (0x40000000U) +#define ENET_RXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ +#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) + +#define ENET_RXIC_ICEN_MASK (0x80000000U) +#define ENET_RXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ +#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) +/*! @} */ + +/* The count of ENET_RXIC */ +#define ENET_RXIC_COUNT (3U) + +/*! @name IAUR - Descriptor Individual Upper Address Register */ +/*! @{ */ + +#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) +#define ENET_IAUR_IADDR1_SHIFT (0U) +#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) +/*! @} */ + +/*! @name IALR - Descriptor Individual Lower Address Register */ +/*! @{ */ + +#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) +#define ENET_IALR_IADDR2_SHIFT (0U) +#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) +/*! @} */ + +/*! @name GAUR - Descriptor Group Upper Address Register */ +/*! @{ */ + +#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) +#define ENET_GAUR_GADDR1_SHIFT (0U) +#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) +/*! @} */ + +/*! @name GALR - Descriptor Group Lower Address Register */ +/*! @{ */ + +#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) +#define ENET_GALR_GADDR2_SHIFT (0U) +#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) +/*! @} */ + +/*! @name TFWR - Transmit FIFO Watermark Register */ +/*! @{ */ + +#define ENET_TFWR_TFWR_MASK (0x3FU) +#define ENET_TFWR_TFWR_SHIFT (0U) +/*! TFWR - Transmit FIFO Write + * 0b000000..64 bytes written. + * 0b000001..64 bytes written. + * 0b000010..128 bytes written. + * 0b000011..192 bytes written. + * 0b111111..4032 bytes written. + */ +#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) + +#define ENET_TFWR_STRFWD_MASK (0x100U) +#define ENET_TFWR_STRFWD_SHIFT (8U) +/*! STRFWD - Store And Forward Enable + * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. + * 0b1..Enabled. + */ +#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) +/*! @} */ + +/*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */ +/*! @{ */ + +#define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR1_R_DES_START_SHIFT (3U) +#define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK) +/*! @} */ + +/*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */ +/*! @{ */ + +#define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR1_X_DES_START_SHIFT (3U) +#define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK) +/*! @} */ + +/*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */ +/*! @{ */ + +#define ENET_MRBR1_R_BUF_SIZE_MASK (0x7F0U) +#define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK) +/*! @} */ + +/*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */ +/*! @{ */ + +#define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR2_R_DES_START_SHIFT (3U) +#define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK) +/*! @} */ + +/*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */ +/*! @{ */ + +#define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR2_X_DES_START_SHIFT (3U) +#define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK) +/*! @} */ + +/*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */ +/*! @{ */ + +#define ENET_MRBR2_R_BUF_SIZE_MASK (0x7F0U) +#define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK) +/*! @} */ + +/*! @name RDSR - Receive Descriptor Ring 0 Start Register */ +/*! @{ */ + +#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR_R_DES_START_SHIFT (3U) +#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) +/*! @} */ + +/*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */ +/*! @{ */ + +#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR_X_DES_START_SHIFT (3U) +#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) +/*! @} */ + +/*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */ +/*! @{ */ + +#define ENET_MRBR_R_BUF_SIZE_MASK (0x7F0U) +#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) +/*! @} */ + +/*! @name RSFL - Receive FIFO Section Full Threshold */ +/*! @{ */ + +#define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU) +#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) +/*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold + */ +#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) +/*! @} */ + +/*! @name RSEM - Receive FIFO Section Empty Threshold */ +/*! @{ */ + +#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU) +#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) +/*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold + */ +#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) + +#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) +#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) +/*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold + */ +#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name RAEM - Receive FIFO Almost Empty Threshold */ +/*! @{ */ + +#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU) +#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) +/*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold + */ +#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name RAFL - Receive FIFO Almost Full Threshold */ +/*! @{ */ + +#define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU) +#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) +/*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold + */ +#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TSEM - Transmit FIFO Section Empty Threshold */ +/*! @{ */ + +#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU) +#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) +/*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold + */ +#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +/*! @{ */ + +#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU) +#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) +/*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold + */ +#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name TAFL - Transmit FIFO Almost Full Threshold */ +/*! @{ */ + +#define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU) +#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) +/*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold + */ +#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TIPG - Transmit Inter-Packet Gap */ +/*! @{ */ + +#define ENET_TIPG_IPG_MASK (0x1FU) +#define ENET_TIPG_IPG_SHIFT (0U) +/*! IPG - Transmit Inter-Packet Gap + */ +#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) +/*! @} */ + +/*! @name FTRL - Frame Truncation Length */ +/*! @{ */ + +#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) +#define ENET_FTRL_TRUNC_FL_SHIFT (0U) +/*! TRUNC_FL - Frame Truncation Length + */ +#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) +/*! @} */ + +/*! @name TACC - Transmit Accelerator Function Configuration */ +/*! @{ */ + +#define ENET_TACC_SHIFT16_MASK (0x1U) +#define ENET_TACC_SHIFT16_SHIFT (0U) +/*! SHIFT16 - TX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the + * frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This + * function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is + * extended to a 16-byte header. + */ +#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) + +#define ENET_TACC_IPCHK_MASK (0x8U) +#define ENET_TACC_IPCHK_SHIFT (3U) +/*! IPCHK + * 0b0..Checksum is not inserted. + * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must + * be cleared. If a non-IP frame is transmitted the frame is not modified. + */ +#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) + +#define ENET_TACC_PROCHK_MASK (0x10U) +#define ENET_TACC_PROCHK_SHIFT (4U) +/*! PROCHK + * 0b0..Checksum not inserted. + * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the + * frame. The checksum field must be cleared. The other frames are not modified. + */ +#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) +/*! @} */ + +/*! @name RACC - Receive Accelerator Function Configuration */ +/*! @{ */ + +#define ENET_RACC_PADREM_MASK (0x1U) +#define ENET_RACC_PADREM_SHIFT (0U) +/*! PADREM - Enable Padding Removal For Short IP Frames + * 0b0..Padding not removed. + * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. + */ +#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) + +#define ENET_RACC_IPDIS_MASK (0x2U) +#define ENET_RACC_IPDIS_SHIFT (1U) +/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum + * 0b0..Frames with wrong IPv4 header checksum are not discarded. + * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no + * header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in + * store and forward mode (RSFL cleared). + */ +#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) + +#define ENET_RACC_PRODIS_MASK (0x4U) +#define ENET_RACC_PRODIS_SHIFT (2U) +/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum + * 0b0..Frames with wrong checksum are not discarded. + * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame + * is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL + * cleared). + */ +#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) + +#define ENET_RACC_LINEDIS_MASK (0x40U) +#define ENET_RACC_LINEDIS_SHIFT (6U) +/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors + * 0b0..Frames with errors are not discarded. + * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + */ +#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) + +#define ENET_RACC_SHIFT16_MASK (0x80U) +#define ENET_RACC_SHIFT16_SHIFT (7U) +/*! SHIFT16 - RX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + */ +#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) +/*! @} */ + +/*! @name RCMR - Receive Classification Match Register for Class n */ +/*! @{ */ + +#define ENET_RCMR_CMP0_MASK (0x7U) +#define ENET_RCMR_CMP0_SHIFT (0U) +/*! CMP0 - Compare 0 + */ +#define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK) + +#define ENET_RCMR_CMP1_MASK (0x70U) +#define ENET_RCMR_CMP1_SHIFT (4U) +/*! CMP1 - Compare 1 + */ +#define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK) + +#define ENET_RCMR_CMP2_MASK (0x700U) +#define ENET_RCMR_CMP2_SHIFT (8U) +/*! CMP2 - Compare 2 + */ +#define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK) + +#define ENET_RCMR_CMP3_MASK (0x7000U) +#define ENET_RCMR_CMP3_SHIFT (12U) +/*! CMP3 - Compare 3 + */ +#define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK) + +#define ENET_RCMR_MATCHEN_MASK (0x10000U) +#define ENET_RCMR_MATCHEN_SHIFT (16U) +/*! MATCHEN - Match Enable + * 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert. + * 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received. + */ +#define ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK) +/*! @} */ + +/* The count of ENET_RCMR */ +#define ENET_RCMR_COUNT (2U) + +/*! @name DMACFG - DMA Class Based Configuration */ +/*! @{ */ + +#define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU) +#define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U) +/*! IDLE_SLOPE - Idle slope + */ +#define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK) + +#define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U) +#define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U) +/*! DMA_CLASS_EN - DMA class enable + * 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also + * requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2 + * queues are disabled then their frames will be placed in queue 0. + * 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic. + */ +#define ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK) + +#define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U) +#define ENET_DMACFG_CALC_NOIPG_SHIFT (17U) +/*! CALC_NOIPG - Calculate no IPG + * 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred + * for a frame when doing bandwidth calculations. This is the default. + * 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping, + * when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every + * frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames + * will become more bandwidth than large frames due to the relation of data to IPG overhead). + */ +#define ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK) +/*! @} */ + +/* The count of ENET_DMACFG */ +#define ENET_DMACFG_COUNT (2U) + +/*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */ +/*! @{ */ + +#define ENET_RDAR1_RDAR_MASK (0x1000000U) +#define ENET_RDAR1_RDAR_SHIFT (24U) +/*! RDAR - Receive Descriptor Active + */ +#define ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK) +/*! @} */ + +/*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */ +/*! @{ */ + +#define ENET_TDAR1_TDAR_MASK (0x1000000U) +#define ENET_TDAR1_TDAR_SHIFT (24U) +/*! TDAR - Transmit Descriptor Active + */ +#define ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK) +/*! @} */ + +/*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */ +/*! @{ */ + +#define ENET_RDAR2_RDAR_MASK (0x1000000U) +#define ENET_RDAR2_RDAR_SHIFT (24U) +/*! RDAR - Receive Descriptor Active + */ +#define ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK) +/*! @} */ + +/*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */ +/*! @{ */ + +#define ENET_TDAR2_TDAR_MASK (0x1000000U) +#define ENET_TDAR2_TDAR_SHIFT (24U) +/*! TDAR - Transmit Descriptor Active + */ +#define ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK) +/*! @} */ + +/*! @name QOS - QOS Scheme */ +/*! @{ */ + +#define ENET_QOS_TX_SCHEME_MASK (0x7U) +#define ENET_QOS_TX_SCHEME_SHIFT (0U) +/*! TX_SCHEME - TX scheme configuration + * 0b000..Credit-based scheme + * 0b001..Round-robin scheme + */ +#define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK) + +#define ENET_QOS_RX_FLUSH0_MASK (0x8U) +#define ENET_QOS_RX_FLUSH0_SHIFT (3U) +/*! RX_FLUSH0 - RX Flush Ring 0 + * 0b0..Disable + * 0b1..Enable + */ +#define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK) + +#define ENET_QOS_RX_FLUSH1_MASK (0x10U) +#define ENET_QOS_RX_FLUSH1_SHIFT (4U) +/*! RX_FLUSH1 - RX Flush Ring 1 + * 0b0..Disable + * 0b1..Enable + */ +#define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK) + +#define ENET_QOS_RX_FLUSH2_MASK (0x20U) +#define ENET_QOS_RX_FLUSH2_SHIFT (5U) +/*! RX_FLUSH2 - RX Flush Ring 2 + * 0b0..Disable + * 0b1..Enable + */ +#define ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK) +/*! @} */ + +/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) +/*! TXPKTS - Packet count + */ +#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) +/*! TXPKTS - Broadcast packets + */ +#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) +/*! TXPKTS - Multicast packets + */ +#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) +/*! TXPKTS - Packets with CRC/align error + */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC + */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC + */ +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of packets less than 64 bytes with bad CRC + */ +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC + */ +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit collisions + */ +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 64-byte transmit packets + */ +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 65- to 127-byte transmit packets + */ +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 128- to 255-byte transmit packets + */ +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 256- to 511-byte transmit packets + */ +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 512- to 1023-byte transmit packets + */ +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 1024- to 2047-byte transmit packets + */ +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets greater than 2048 bytes + */ +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +/*! TXOCTS - Number of transmit octets + */ +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) +/*! @} */ + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted OK + */ +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with one collision + */ +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with multiple collisions + */ +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with deferral delay + */ +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with late collision + */ +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with excessive collisions + */ +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with transmit FIFO underrun + */ +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with carrier sense error + */ +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_SQE - Reserved Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) +#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +/*! COUNT - Number of flow-control pause frames transmitted + */ +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +/*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). + */ +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +/*! COUNT - Number of packets received + */ +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +/*! COUNT - Number of receive broadcast packets + */ +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +/*! COUNT - Number of receive multicast packets + */ +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets with CRC or align error + */ +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets with less than 64 bytes and good CRC + */ +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets greater than MAX_FL and good CRC + */ +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets with less than 64 bytes and bad CRC + */ +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets greater than MAX_FL and bad CRC + */ +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +/*! COUNT - Number of 64-byte receive packets + */ +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +/*! COUNT - Number of 65- to 127-byte recieve packets + */ +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +/*! COUNT - Number of 128- to 255-byte recieve packets + */ +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +/*! COUNT - Number of 256- to 511-byte recieve packets + */ +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +/*! COUNT - Number of 512- to 1023-byte recieve packets + */ +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +/*! COUNT - Number of 1024- to 2047-byte recieve packets + */ +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +/*! COUNT - Number of greater-than-2048-byte recieve packets + */ +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +/*! COUNT - Number of receive octets + */ +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +/*! COUNT - Frame count + */ +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +/*! COUNT - Number of frames received OK + */ +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +/*! COUNT - Number of frames received with CRC error + */ +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +/*! COUNT - Number of frames received with alignment error + */ +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +/*! COUNT - Receive FIFO overflow count + */ +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +/*! COUNT - Number of flow-control pause frames received + */ +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +/*! COUNT - Number of octets for frames received without error + */ +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name ATCR - Adjustable Timer Control Register */ +/*! @{ */ + +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +/*! EN - Enable Timer + * 0b0..The timer stops at the current value. + * 0b1..The timer starts incrementing. + */ +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) + +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +/*! OFFEN - Enable One-Shot Offset Event + * 0b0..Disable. + * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared + * when the offset event is reached, so no further event occurs until the field is set again. The timer + * offset value must be set before setting this field. + */ +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) + +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +/*! OFFRST - Reset Timer On Offset Event + * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + */ +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) + +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +/*! PEREN - Enable Periodical Event + * 0b0..Disable. + * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when + * the timer wraps around according to the periodic setting ATPER. The timer period value must be set before + * setting this bit. Not all devices contain the event signal output. See the chip configuration details. + */ +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) + +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +/*! PINPER + * 0b0..Disable. + * 0b1..Enable. + */ +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) + +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +/*! RESTART - Reset Timer + */ +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) + +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +/*! CAPTURE - Capture Timer Value + * 0b0..No effect. + * 0b1..The current time is captured and can be read from the ATVR register. + */ +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) + +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +/*! SLAVE - Enable Timer Slave Mode + * 0b0..The timer is active and all configuration fields in this register are relevant. + * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except + * CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + */ +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) +/*! @} */ + +/*! @name ATVR - Timer Value Register */ +/*! @{ */ + +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) +/*! @} */ + +/*! @name ATOFF - Timer Offset Register */ +/*! @{ */ + +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) +/*! @} */ + +/*! @name ATPER - Timer Period Register */ +/*! @{ */ + +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) +/*! @} */ + +/*! @name ATCOR - Timer Correction Register */ +/*! @{ */ + +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +/*! COR - Correction Counter Wrap-Around Value + */ +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) +/*! @} */ + +/*! @name ATINC - Time-Stamping Clock Period Register */ +/*! @{ */ + +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +/*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds + */ +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) + +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +/*! INC_CORR - Correction Increment Value + */ +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) +/*! @} */ + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +/*! @{ */ + +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) +/*! @} */ + +/*! @name TGSR - Timer Global Status Register */ +/*! @{ */ + +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +/*! TF0 - Copy Of Timer Flag For Channel 0 + * 0b0..Timer Flag for Channel 0 is clear + * 0b1..Timer Flag for Channel 0 is set + */ +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) + +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +/*! TF1 - Copy Of Timer Flag For Channel 1 + * 0b0..Timer Flag for Channel 1 is clear + * 0b1..Timer Flag for Channel 1 is set + */ +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) + +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +/*! TF2 - Copy Of Timer Flag For Channel 2 + * 0b0..Timer Flag for Channel 2 is clear + * 0b1..Timer Flag for Channel 2 is set + */ +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) + +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +/*! TF3 - Copy Of Timer Flag For Channel 3 + * 0b0..Timer Flag for Channel 3 is clear + * 0b1..Timer Flag for Channel 3 is set + */ +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) +/*! @} */ + +/*! @name TCSR - Timer Control Status Register */ +/*! @{ */ + +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +/*! TDRE - Timer DMA Request Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) + +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +/*! TMODE - Timer Mode + * 0b0000..Timer Channel is disabled. + * 0b0001..Timer Channel is configured for Input Capture on rising edge. + * 0b0010..Timer Channel is configured for Input Capture on falling edge. + * 0b0011..Timer Channel is configured for Input Capture on both edges. + * 0b0100..Timer Channel is configured for Output Compare - software only. + * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. + * 0b0110..Timer Channel is configured for Output Compare - clear output on compare. + * 0b0111..Timer Channel is configured for Output Compare - set output on compare. + * 0b1000..Reserved + * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + * 0b110x..Reserved + * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. + * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle. + */ +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) + +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) + +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +/*! TF - Timer Flag + * 0b0..Input Capture or Output Compare has not occurred. + * 0b1..Input Capture or Output Compare has occurred. + */ +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) +/*! @} */ + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +/*! @{ */ + +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +/*! TCC - Timer Capture Compare + */ +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) +/*! @} */ + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET base address */ +#define ENET_BASE (0x30BE0000u) +/** Peripheral ENET base pointer */ +#define ENET ((ENET_Type *)ENET_BASE) +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS { ENET_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { ENET } +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_Transmit_IRQS { ENET_IRQn } +#define ENET_Receive_IRQS { ENET_IRQn } +#define ENET_Error_IRQS { ENET_IRQn } +#define ENET_1588_Timer_IRQS { ENET_IRQn } +#define ENET_Ts_IRQS { ENET_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer + * @{ + */ + +/** GPC - Register Layout Typedef */ +typedef struct { + __IO uint32_t LPCR_A53_BSC; /**< Basic Low power control register of A53 platform, offset: 0x0 */ + __IO uint32_t LPCR_A53_AD; /**< Advanced Low power control register of A53 platform, offset: 0x4 */ + __IO uint32_t LPCR_M4; /**< Low power control register of CPU1, offset: 0x8 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SLPCR; /**< System low power control register, offset: 0x14 */ + __IO uint32_t MST_CPU_MAPPING; /**< MASTER LPM Handshake, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MLPCR; /**< Memory low power control register, offset: 0x20 */ + __IO uint32_t PGC_ACK_SEL_A53; /**< PGC acknowledge signal selection of A53 platform, offset: 0x24 */ + __IO uint32_t PGC_ACK_SEL_M4; /**< PGC acknowledge signal selection of M4 platform, offset: 0x28 */ + __IO uint32_t MISC; /**< GPC Miscellaneous register, offset: 0x2C */ + __IO uint32_t IMR_CORE0_A53[4]; /**< IRQ masking register 1 of A53 core0..IRQ masking register 4 of A53 core0, array offset: 0x30, array step: 0x4 */ + __IO uint32_t IMR_CORE1_A53[4]; /**< IRQ masking register 1 of A53 core1..IRQ masking register 4 of A53 core1, array offset: 0x40, array step: 0x4 */ + __IO uint32_t IMR_M4[4]; /**< IRQ masking register 1 of M4..IRQ masking register 4 of M4, array offset: 0x50, array step: 0x4 */ + uint8_t RESERVED_2[16]; + __I uint32_t ISR_A53[4]; /**< IRQ status register 1 of A53..IRQ status register 4 of A53, array offset: 0x70, array step: 0x4 */ + __I uint32_t ISR_M4[4]; /**< IRQ status register 1 of M4..IRQ status register 4 of M4, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_3[32]; + __IO uint32_t SLT0_CFG; /**< Slot configure register for A53 core, offset: 0xB0 */ + __IO uint32_t SLT1_CFG; /**< Slot configure register for A53 core, offset: 0xB4 */ + __IO uint32_t SLT2_CFG; /**< Slot configure register for A53 core, offset: 0xB8 */ + __IO uint32_t SLT3_CFG; /**< Slot configure register for A53 core, offset: 0xBC */ + __IO uint32_t SLT4_CFG; /**< Slot configure register for A53 core, offset: 0xC0 */ + __IO uint32_t SLT5_CFG; /**< Slot configure register for A53 core, offset: 0xC4 */ + __IO uint32_t SLT6_CFG; /**< Slot configure register for A53 core, offset: 0xC8 */ + __IO uint32_t SLT7_CFG; /**< Slot configure register for A53 core, offset: 0xCC */ + __IO uint32_t SLT8_CFG; /**< Slot configure register for A53 core, offset: 0xD0 */ + __IO uint32_t SLT9_CFG; /**< Slot configure register for A53 core, offset: 0xD4 */ + __IO uint32_t SLT10_CFG; /**< Slot configure register for A53 core, offset: 0xD8 */ + __IO uint32_t SLT11_CFG; /**< Slot configure register for A53 core, offset: 0xDC */ + __IO uint32_t SLT12_CFG; /**< Slot configure register for A53 core, offset: 0xE0 */ + __IO uint32_t SLT13_CFG; /**< Slot configure register for A53 core, offset: 0xE4 */ + __IO uint32_t SLT14_CFG; /**< Slot configure register for A53 core, offset: 0xE8 */ + __IO uint32_t PGC_CPU_0_1_MAPPING; /**< PGC CPU mapping, offset: 0xEC */ + __IO uint32_t CPU_PGC_SW_PUP_REQ; /**< CPU PGC software power up trigger, offset: 0xF0 */ + __IO uint32_t MIX_PGC_SW_PUP_REQ; /**< MIX PGC software power up trigger, offset: 0xF4 */ + __IO uint32_t PU_PGC_SW_PUP_REQ; /**< PU PGC software up trigger, offset: 0xF8 */ + __IO uint32_t CPU_PGC_SW_PDN_REQ; /**< CPU PGC software down trigger, offset: 0xFC */ + __IO uint32_t MIX_PGC_SW_PDN_REQ; /**< MIX PGC software power down trigger, offset: 0x100 */ + __IO uint32_t PU_PGC_SW_PDN_REQ; /**< PU PGC software down trigger, offset: 0x104 */ + __IO uint32_t LPCR_A53_BSC2; /**< Basic Low power control register of A53 platform, offset: 0x108 */ + uint8_t RESERVED_4[36]; + __I uint32_t CPU_PGC_PUP_STATUS1; /**< CPU PGC software up trigger status1, offset: 0x130 */ + __I uint32_t A53_MIX_PGC_PUP_STATUS[3]; /**< A53 MIX software up trigger status register, array offset: 0x134, array step: 0x4 */ + __I uint32_t M4_MIX_PGC_PUP_STATUS[3]; /**< M4 MIX PGC software up trigger status register, array offset: 0x140, array step: 0x4 */ + __I uint32_t A53_PU_PGC_PUP_STATUS[3]; /**< A53 PU software up trigger status register, array offset: 0x14C, array step: 0x4 */ + __I uint32_t M4_PU_PGC_PUP_STATUS[3]; /**< M4 PU PGC software up trigger status register, array offset: 0x158, array step: 0x4 */ + uint8_t RESERVED_5[12]; + __IO uint32_t CPU_PGC_PDN_STATUS1; /**< CPU PGC software dn trigger status1, offset: 0x170 */ + __I uint32_t A53_MIX_PGC_PDN_STATUS[3]; /**< A53 MIX software down trigger status register, array offset: 0x174, array step: 0x4 */ + __I uint32_t M4_MIX_PGC_PDN_STATUS[3]; /**< M4 MIX PGC software power down trigger status register, array offset: 0x180, array step: 0x4 */ + __I uint32_t A53_PU_PGC_PDN_STATUS[3]; /**< A53 PU PGC software down trigger status, array offset: 0x18C, array step: 0x4 */ + __I uint32_t M4_PU_PGC_PDN_STATUS[3]; /**< M4 PU PGC software down trigger status, array offset: 0x198, array step: 0x4 */ + uint8_t RESERVED_6[12]; + __IO uint32_t A53_MIX_PDN_FLG; /**< A53 MIX PDN FLG, offset: 0x1B0 */ + __IO uint32_t A53_PU_PDN_FLG; /**< A53 PU PDN FLG, offset: 0x1B4 */ + __IO uint32_t M4_MIX_PDN_FLG; /**< M4 MIX PDN FLG, offset: 0x1B8 */ + __IO uint32_t M4_PU_PDN_FLG; /**< M4 PU PDN FLG, offset: 0x1BC */ + __IO uint32_t IMR_CORE2_A53[4]; /**< IRQ masking register 1 of A53 core2..IRQ masking register 4 of A53 core2, array offset: 0x1C0, array step: 0x4 */ + __IO uint32_t IMR_CORE3_A53[4]; /**< IRQ masking register 1 of A53 core3..IRQ masking register 4 of A53 core3, array offset: 0x1D0, array step: 0x4 */ + __IO uint32_t ACK_SEL_A53_PU; /**< PGC acknowledge signal selection of A53 platform for PUs, offset: 0x1E0 */ + __IO uint32_t ACK_SEL_M4_PU; /**< PGC acknowledge signal selection of M4 platform for PUs, offset: 0x1E4 */ + __IO uint32_t SLT15_CFG; /**< Slot configure register for A53 core, offset: 0x1E8 */ + __IO uint32_t SLT16_CFG; /**< Slot configure register for A53 core, offset: 0x1EC */ + __IO uint32_t SLT17_CFG; /**< Slot configure register for A53 core, offset: 0x1F0 */ + __IO uint32_t SLT18_CFG; /**< Slot configure register for A53 core, offset: 0x1F4 */ + __IO uint32_t SLT19_CFG; /**< Slot configure register for A53 core, offset: 0x1F8 */ + __IO uint32_t PU_PWRHSK; /**< Power handshake register, offset: 0x1FC */ + __IO uint32_t SLT_CFG_PU[20]; /**< Slot configure register for PUs, array offset: 0x200, array step: 0x4 */ +} GPC_Type; + +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/*! @name LPCR_A53_BSC - Basic Low power control register of A53 platform */ +/*! @{ */ + +#define GPC_LPCR_A53_BSC_LPM0_MASK (0x3U) +#define GPC_LPCR_A53_BSC_LPM0_SHIFT (0U) +/*! LPM0 + * 0b00..Remain in RUN mode + * 0b01..Transfer to WAIT mode + * 0b10..Transfer to STOP mode + * 0b11..Reserved + */ +#define GPC_LPCR_A53_BSC_LPM0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM0_SHIFT)) & GPC_LPCR_A53_BSC_LPM0_MASK) + +#define GPC_LPCR_A53_BSC_LPM1_MASK (0xCU) +#define GPC_LPCR_A53_BSC_LPM1_SHIFT (2U) +/*! LPM1 + * 0b00..Remain in RUN mode + * 0b01..Transfer to WAIT mode + * 0b10..Transfer to STOP mode + * 0b11..Reserved + */ +#define GPC_LPCR_A53_BSC_LPM1(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM1_SHIFT)) & GPC_LPCR_A53_BSC_LPM1_MASK) + +#define GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK_MASK (0x40U) +#define GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK_SHIFT (6U) +/*! MST_LPM_HSK_MASK - MASTER0 LPM handshake mask + * 0b0..enable MASTER0 LPM handshake, wait ACK from MASTER0 + * 0b1..disable MASKTER0 LPM handshake, mask ACK from MASTER0 + */ +#define GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK_SHIFT)) & GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK_MASK) + +#define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK (0x4000U) +#define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT (14U) +/*! CPU_CLK_ON_LPM + * 0b0..A53 clock disabled on wait/stop mode + * 0b1..A53 clock enabled on wait/stop mode + */ +#define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK) + +#define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK (0x10000U) +#define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT (16U) +/*! MASK_CORE0_WFI + * 0b0..WFI for CORE0 is not masked + * 0b1..WFI for CORE0 is masked + */ +#define GPC_LPCR_A53_BSC_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK) + +#define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK (0x20000U) +#define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT (17U) +/*! MASK_CORE1_WFI + * 0b0..WFI for CORE1 is not masked + * 0b1..WFI for CORE1 is masked + */ +#define GPC_LPCR_A53_BSC_MASK_CORE1_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK) + +#define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK (0x40000U) +#define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT (18U) +/*! MASK_CORE2_WFI + * 0b0..WFI for CORE2 is not masked + * 0b1..WFI for CORE2 is masked + */ +#define GPC_LPCR_A53_BSC_MASK_CORE2_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK) + +#define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK (0x80000U) +#define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT (19U) +/*! MASK_CORE3_WFI + * 0b0..WFI for CORE3 is not masked + * 0b1..WFI for CORE3 is masked + */ +#define GPC_LPCR_A53_BSC_MASK_CORE3_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK) + +#define GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK (0x400000U) +#define GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT (22U) +/*! IRQ_SRC_C2 + * 0b0..core2 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more specific information. + * 0b1..core2 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during low power mode when this bit is set to 1'b1. + */ +#define GPC_LPCR_A53_BSC_IRQ_SRC_C2(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK) + +#define GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK (0x800000U) +#define GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT (23U) +/*! IRQ_SRC_C3 + * 0b0..core3 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more specific information. + * 0b1..core3 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during low power mode when this bit is set to 1'b1. + */ +#define GPC_LPCR_A53_BSC_IRQ_SRC_C3(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK) + +#define GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK (0x1000000U) +#define GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT (24U) +/*! MASK_SCU_WFI + * 0b0..WFI for SCU is not masked + * 0b1..WFI for SCU is masked + */ +#define GPC_LPCR_A53_BSC_MASK_SCU_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK) + +#define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK (0x4000000U) +#define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT (26U) +/*! MASK_L2CC_WFI + * 0b0..WFI for L2 cache controller is not masked + * 0b1..WFI for L2 cache controller is masked + */ +#define GPC_LPCR_A53_BSC_MASK_L2CC_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK) + +#define GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK (0x10000000U) +#define GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT (28U) +/*! IRQ_SRC_C0 + * 0b0..core0 wakeup source from external INT[127:0], masked by IMR0 refer to "Power up process for A53 platform" for more specific information + * 0b1..core0 wakeup source from GIC(nFIQ[0]/nIRQ[0] ), SCU should not be power down during low power mode when this bit is set to 1'b1 + */ +#define GPC_LPCR_A53_BSC_IRQ_SRC_C0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK) + +#define GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK (0x20000000U) +#define GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT (29U) +/*! IRQ_SRC_C1 + * 0b0..core1 wakeup source from external INT[127:0], masked by IMR1 refer to "Power up process for A53 platform" for more specific information + * 0b1..core1 wakeup source from GIC(nFIQ[1]/nIRQ[1] ), SCU should not be power down during low power mode when this bit is set to 1'b1 + */ +#define GPC_LPCR_A53_BSC_IRQ_SRC_C1(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK) + +#define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK (0x40000000U) +#define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT (30U) +/*! IRQ_SRC_A53_WUP + * 0b0..LPM wakeup source be "OR" result of + * LPCR_A53_BSC[IRQ_SRC_C0]/LPCR_A53_BSC[IRQ_SRC_C1]/LPCR_A53_BSC[IRQ_SRC_C2]/LPCR_A53_BSC[IRQ_SRC_C3] setting + * 0b1..LPM wakeup source from external INT[127:0], masked by IMR0 + */ +#define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK) + +#define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK (0x80000000U) +#define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT (31U) +/*! MASK_DSM_TRIGGER + * 0b0..DSM trigger of A53 platform will not be masked + * 0b1..DSM trigger of A53 platform will be masked + */ +#define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK) +/*! @} */ + +/*! @name LPCR_A53_AD - Advanced Low power control register of A53 platform */ +/*! @{ */ + +#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK (0x1U) +#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT (0U) +/*! EN_C0_WFI_PDN + * 0b0..CORE0 will not be power down with WFI request + * 0b1..CORE0 will be power down with WFI request + */ +#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK) + +#define GPC_LPCR_A53_AD_EN_C0_PDN_MASK (0x2U) +#define GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT (1U) +/*! EN_C0_PDN + * 0b0..CORE0 will not be power down with low power mode request + * 0b1..CORE0 will be power down with low power mode request + */ +#define GPC_LPCR_A53_AD_EN_C0_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PDN_MASK) + +#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK (0x4U) +#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT (2U) +/*! EN_C1_WFI_PDN + * 0b0..CORE1 will not be power down with WFI request + * 0b1..CORE1 will be power down with WFI request + */ +#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK) + +#define GPC_LPCR_A53_AD_EN_C1_PDN_MASK (0x8U) +#define GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT (3U) +/*! EN_C1_PDN + * 0b0..CORE1 will not be power down with low power mode request + * 0b1..CORE1 will be power down with low power mode request + */ +#define GPC_LPCR_A53_AD_EN_C1_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PDN_MASK) + +#define GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK (0x10U) +#define GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT (4U) +/*! EN_PLAT_PDN + * 0b0..SCU and L2 cache RAM will not be power down with low power mode request + * 0b1..SCU and L2 cache RAM will be power down with low power mode request + */ +#define GPC_LPCR_A53_AD_EN_PLAT_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK) + +#define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK (0x20U) +#define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT (5U) +/*! EN_L2_WFI_PDN + * 0b0..SCU and L2 will not be power down with WFI request + * 0b1..SCU and L2 will be power down with WFI request (default) + */ +#define GPC_LPCR_A53_AD_EN_L2_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK) + +#define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK (0x100U) +#define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT (8U) +/*! EN_C0_IRQ_PUP + * 0b0..CORE0 will power up with IRQ request + * 0b1..CORE0 will not power up with IRQ request + */ +#define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK) + +#define GPC_LPCR_A53_AD_EN_C0_PUP_MASK (0x200U) +#define GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT (9U) +/*! EN_C0_PUP + * 0b0..CORE0 will power up with low power mode request + * 0b1..CORE0 will not power up with low power mode request + */ +#define GPC_LPCR_A53_AD_EN_C0_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PUP_MASK) + +#define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK (0x400U) +#define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT (10U) +/*! EN_C1_IRQ_PUP + * 0b0..CORE1 will power up with IRQ request + * 0b1..CORE1 will not power up with IRQ request + */ +#define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK) + +#define GPC_LPCR_A53_AD_EN_C1_PUP_MASK (0x800U) +#define GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT (11U) +/*! EN_C1_PUP + * 0b0..CORE1 will not power up with low power mode request (only used wake up from CPU01_OFF mode) + * 0b1..CORE1 will power up with low power mode request + */ +#define GPC_LPCR_A53_AD_EN_C1_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PUP_MASK) + +#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK (0x10000U) +#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT (16U) +/*! EN_C2_WFI_PDN + * 0b0..CORE2 will not be power down with WFI request + * 0b1..CORE2 will be power down with WFI request + */ +#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK) + +#define GPC_LPCR_A53_AD_EN_C2_PDN_MASK (0x20000U) +#define GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT (17U) +/*! EN_C2_PDN + * 0b0..CORE2 will not be power down with low power mode request + * 0b1..CORE2 will be power down with low power mode request + */ +#define GPC_LPCR_A53_AD_EN_C2_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PDN_MASK) + +#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK (0x40000U) +#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT (18U) +/*! EN_C3_WFI_PDN + * 0b0..CORE3 will not be power down with WFI request + * 0b1..CORE3 will be power down with WFI request + */ +#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK) + +#define GPC_LPCR_A53_AD_EN_C3_PDN_MASK (0x80000U) +#define GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT (19U) +/*! EN_C3_PDN + * 0b0..CORE3 will not be power down with low power mode request + * 0b1..CORE3 will be power down with low power mode request + */ +#define GPC_LPCR_A53_AD_EN_C3_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PDN_MASK) + +#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_MASK (0x100000U) +#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_SHIFT (20U) +/*! EN_C0_WFI_PDN_DIS + * 0b0..Disnable WFI power down core0 + * 0b1..Enable WFI power down core0 + */ +#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_MASK) + +#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_MASK (0x200000U) +#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_SHIFT (21U) +/*! EN_C1_WFI_PDN_DIS + * 0b0..Disnable WFI power down core1 + * 0b1..Enable WFI power down core1 + */ +#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_MASK) + +#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_MASK (0x400000U) +#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_SHIFT (22U) +/*! EN_C2_WFI_PDN_DIS + * 0b0..Disnable WFI power down core2 + * 0b1..Enable WFI power down core2 + */ +#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_MASK) + +#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_MASK (0x800000U) +#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_SHIFT (23U) +/*! EN_C3_WFI_PDN_DIS + * 0b0..Disnable WFI power down core3 + * 0b1..Enable WFI power down core3 + */ +#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_MASK) + +#define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK (0x1000000U) +#define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT (24U) +/*! EN_C2_IRQ_PUP + * 0b0..CORE2 will power up with IRQ request + * 0b1..CORE2 will not power up with IRQ request + */ +#define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK) + +#define GPC_LPCR_A53_AD_EN_C2_PUP_MASK (0x2000000U) +#define GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT (25U) +/*! EN_C2_PUP + * 0b0..CORE2 will power up with lower power mode request + * 0b1..CORE2 will not power up with low power mode request (only used wake up from CPU_OFF) + */ +#define GPC_LPCR_A53_AD_EN_C2_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PUP_MASK) + +#define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK (0x4000000U) +#define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT (26U) +/*! EN_C3_IRQ_PUP + * 0b0..CORE3 will power up with IRQ request + * 0b1..CORE3 will not power up with IRQ request + */ +#define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK) + +#define GPC_LPCR_A53_AD_EN_C3_PUP_MASK (0x8000000U) +#define GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT (27U) +/*! EN_C3_PUP + * 0b0..CORE3 will power up with lower power mode request + * 0b1..CORE3 will not power up with low power mode request (only used wake up from CPU_OFF) + */ +#define GPC_LPCR_A53_AD_EN_C3_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PUP_MASK) + +#define GPC_LPCR_A53_AD_L2PGE_MASK (0x80000000U) +#define GPC_LPCR_A53_AD_L2PGE_SHIFT (31U) +/*! L2PGE + * 0b0..L2 cache RAM will power down with SCU power domain in A53 platform (used for ALL_OFF mode) + * 0b1..L2 cache RAM will not power down with SCU power domain in A53 platform (used for ALL_OFF mode) + */ +#define GPC_LPCR_A53_AD_L2PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_L2PGE_SHIFT)) & GPC_LPCR_A53_AD_L2PGE_MASK) +/*! @} */ + +/*! @name LPCR_M4 - Low power control register of CPU1 */ +/*! @{ */ + +#define GPC_LPCR_M4_LPM0_MASK (0x3U) +#define GPC_LPCR_M4_LPM0_SHIFT (0U) +/*! LPM0 + * 0b00..Remain in RUN mode + * 0b01..Transfer to WAIT mode + * 0b10..Transfer to STOP mode + * 0b11..Reserved + */ +#define GPC_LPCR_M4_LPM0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_LPM0_SHIFT)) & GPC_LPCR_M4_LPM0_MASK) + +#define GPC_LPCR_M4_EN_M4_PDN_MASK (0x4U) +#define GPC_LPCR_M4_EN_M4_PDN_SHIFT (2U) +#define GPC_LPCR_M4_EN_M4_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_EN_M4_PDN_SHIFT)) & GPC_LPCR_M4_EN_M4_PDN_MASK) + +#define GPC_LPCR_M4_EN_M4_PUP_MASK (0x8U) +#define GPC_LPCR_M4_EN_M4_PUP_SHIFT (3U) +#define GPC_LPCR_M4_EN_M4_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_EN_M4_PUP_SHIFT)) & GPC_LPCR_M4_EN_M4_PUP_MASK) + +#define GPC_LPCR_M4_CPU_CLK_ON_LPM_MASK (0x4000U) +#define GPC_LPCR_M4_CPU_CLK_ON_LPM_SHIFT (14U) +/*! CPU_CLK_ON_LPM + * 0b0..M4 clock disabled on wait/stop mode. + * 0b1..M4 clock enabled on wait/stop mode. + */ +#define GPC_LPCR_M4_CPU_CLK_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_M4_CPU_CLK_ON_LPM_MASK) + +#define GPC_LPCR_M4_MASK_M4_WFI_MASK (0x10000U) +#define GPC_LPCR_M4_MASK_M4_WFI_SHIFT (16U) +/*! MASK_M4_WFI + * 0b0..WFI for M4 is not masked + * 0b1..WFI for M4 is masked + */ +#define GPC_LPCR_M4_MASK_M4_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_MASK_M4_WFI_SHIFT)) & GPC_LPCR_M4_MASK_M4_WFI_MASK) + +#define GPC_LPCR_M4_MASK_DSM_TRIGGER_MASK (0x80000000U) +#define GPC_LPCR_M4_MASK_DSM_TRIGGER_SHIFT (31U) +/*! MASK_DSM_TRIGGER + * 0b0..DSM trigger of M4 platform will not be masked + * 0b1..DSM trigger of M4 platform will be masked + */ +#define GPC_LPCR_M4_MASK_DSM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_M4_MASK_DSM_TRIGGER_MASK) +/*! @} */ + +/*! @name SLPCR - System low power control register */ +/*! @{ */ + +#define GPC_SLPCR_BYPASS_PMIC_READY_MASK (0x1U) +#define GPC_SLPCR_BYPASS_PMIC_READY_SHIFT (0U) +/*! BYPASS_PMIC_READY + * 0b0..Don't bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby voltage was enabled + * 0b1..Bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby voltage was enabled + */ +#define GPC_SLPCR_BYPASS_PMIC_READY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_BYPASS_PMIC_READY_SHIFT)) & GPC_SLPCR_BYPASS_PMIC_READY_MASK) + +#define GPC_SLPCR_SBYOS_MASK (0x2U) +#define GPC_SLPCR_SBYOS_SHIFT (1U) +/*! SBYOS + * 0b0..On chip oscillator will not be powered down, after next entrance to DSM. + * 0b1..On chip oscillator will be powered down, after next entrance to DSM. When returning from DSM, external + * oscillator will be enabled again, on chip oscillator will return to oscillator mode , and after oscnt count + * GPC will continue with the exit from DSM process. + */ +#define GPC_SLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_SBYOS_SHIFT)) & GPC_SLPCR_SBYOS_MASK) + +#define GPC_SLPCR_VSTBY_MASK (0x4U) +#define GPC_SLPCR_VSTBY_SHIFT (2U) +/*! VSTBY + * 0b0..Voltage will not be changed to standby voltage after next entrance to stop mode. (PMIC_STBY_REQ will remain negated - '0') + * 0b1..Voltage will be changed to standby voltage after next entrance to stop mode. + */ +#define GPC_SLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_VSTBY_SHIFT)) & GPC_SLPCR_VSTBY_MASK) + +#define GPC_SLPCR_STBY_COUNT_MASK (0x38U) +#define GPC_SLPCR_STBY_COUNT_SHIFT (3U) +/*! STBY_COUNT + * 0b000..GPC will wait 4 ckil clock cycles + * 0b001..GPC will wait 8 ckil clock cycles + * 0b010..GPC will wait 16 ckil clock cycles + * 0b011..GPC will wait 32 ckil clock cycles + * 0b100..GPC will wait 64 ckil clock cycles + * 0b101..GPC will wait 128 ckil clock cycles + * 0b110..GPC will wait 256 ckil clock cycles + * 0b111..GPC will wait 512 ckil clock cycles + */ +#define GPC_SLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_STBY_COUNT_SHIFT)) & GPC_SLPCR_STBY_COUNT_MASK) + +#define GPC_SLPCR_COSC_PWRDOWN_MASK (0x40U) +#define GPC_SLPCR_COSC_PWRDOWN_SHIFT (6U) +/*! COSC_PWRDOWN + * 0b0..On-chip oscillator will not be powered down, i.e. cosc_pwrdown = 0 + * 0b1..On-chip oscillator will be powered down, i.e. cosc_pwrdown = 1 + */ +#define GPC_SLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_PWRDOWN_SHIFT)) & GPC_SLPCR_COSC_PWRDOWN_MASK) + +#define GPC_SLPCR_COSC_EN_MASK (0x80U) +#define GPC_SLPCR_COSC_EN_SHIFT (7U) +/*! COSC_EN + * 0b0..Disable on-chip oscillator + * 0b1..Enable on-chip oscillator + */ +#define GPC_SLPCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_EN_SHIFT)) & GPC_SLPCR_COSC_EN_MASK) + +#define GPC_SLPCR_OSCCNT_MASK (0xFF00U) +#define GPC_SLPCR_OSCCNT_SHIFT (8U) +/*! OSCCNT + * 0b00000000..count 1 ckil + * 0b11111111..count 256 ckils + */ +#define GPC_SLPCR_OSCCNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_OSCCNT_SHIFT)) & GPC_SLPCR_OSCCNT_MASK) + +#define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK (0x10000U) +#define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT (16U) +#define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT)) & GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK) + +#define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK (0x20000U) +#define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT (17U) +#define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT)) & GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK) + +#define GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_MASK (0x40000U) +#define GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_SHIFT (18U) +#define GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_SHIFT)) & GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_MASK) + +#define GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_MASK (0x80000U) +#define GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_SHIFT (19U) +#define GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_SHIFT)) & GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_MASK) + +#define GPC_SLPCR_DISABLE_A53_IS_DSM_MASK (0x800000U) +#define GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT (23U) +/*! DISABLE_A53_IS_DSM + * 0b0..Enable A53 isolation signal in DSM + * 0b1..Disable A53 isolation signal in DSM + */ +#define GPC_SLPCR_DISABLE_A53_IS_DSM(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT)) & GPC_SLPCR_DISABLE_A53_IS_DSM_MASK) + +#define GPC_SLPCR_REG_BYPASS_COUNT_MASK (0x3F000000U) +#define GPC_SLPCR_REG_BYPASS_COUNT_SHIFT (24U) +/*! REG_BYPASS_COUNT + * 0b000000..no delay + * 0b000001..1 CKIL clock period delay + * 0b111111..63 CKIL clock period delay + */ +#define GPC_SLPCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_REG_BYPASS_COUNT_SHIFT)) & GPC_SLPCR_REG_BYPASS_COUNT_MASK) + +#define GPC_SLPCR_RBC_EN_MASK (0x40000000U) +#define GPC_SLPCR_RBC_EN_SHIFT (30U) +/*! RBC_EN + * 0b0..REG_BYPASS_COUNTER disabled + * 0b1..REG_BYPASS_COUNTER enabled + */ +#define GPC_SLPCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_RBC_EN_SHIFT)) & GPC_SLPCR_RBC_EN_MASK) + +#define GPC_SLPCR_EN_DSM_MASK (0x80000000U) +#define GPC_SLPCR_EN_DSM_SHIFT (31U) +/*! EN_DSM + * 0b0..DSM disabled + * 0b1..DSM enabled + */ +#define GPC_SLPCR_EN_DSM(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_DSM_SHIFT)) & GPC_SLPCR_EN_DSM_MASK) +/*! @} */ + +/*! @name MST_CPU_MAPPING - MASTER LPM Handshake */ +/*! @{ */ + +#define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK (0x1U) +#define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT (0U) +/*! MST0_CPU_MAPPING - MASTER0 CPU Mapping + * 0b0..GPC will not send out power off requirement + * 0b1..GPC will send out power off requirement + */ +#define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT)) & GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK) + +#define GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN_MASK (0xFFFFFFFEU) +#define GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN_SHIFT (1U) +#define GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN(x) (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN_SHIFT)) & GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN_MASK) +/*! @} */ + +/*! @name MLPCR - Memory low power control register */ +/*! @{ */ + +#define GPC_MLPCR_MEMLP_CTL_DIS_MASK (0x1U) +#define GPC_MLPCR_MEMLP_CTL_DIS_SHIFT (0U) +/*! MEMLP_CTL_DIS + * 0b0..Enable RAM low power control + * 0b1..Disable RAM low power control + */ +#define GPC_MLPCR_MEMLP_CTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_CTL_DIS_SHIFT)) & GPC_MLPCR_MEMLP_CTL_DIS_MASK) + +#define GPC_MLPCR_MEMLP_RET_SEL_MASK (0x2U) +#define GPC_MLPCR_MEMLP_RET_SEL_SHIFT (1U) +/*! MEMLP_RET_SEL + * 0b0..retention mode 2 + * 0b1..retention mode 1 + */ +#define GPC_MLPCR_MEMLP_RET_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_SEL_SHIFT)) & GPC_MLPCR_MEMLP_RET_SEL_MASK) + +#define GPC_MLPCR_ROMLP_PDN_DIS_MASK (0x4U) +#define GPC_MLPCR_ROMLP_PDN_DIS_SHIFT (2U) +/*! ROMLP_PDN_DIS + * 0b0..Enable ROM shut down control(should also enable RAM low power control); + * 0b1..Disable ROM shut down control + */ +#define GPC_MLPCR_ROMLP_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_ROMLP_PDN_DIS_SHIFT)) & GPC_MLPCR_ROMLP_PDN_DIS_MASK) + +#define GPC_MLPCR_MEMLP_ENT_CNT_MASK (0xFF00U) +#define GPC_MLPCR_MEMLP_ENT_CNT_SHIFT (8U) +#define GPC_MLPCR_MEMLP_ENT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_ENT_CNT_SHIFT)) & GPC_MLPCR_MEMLP_ENT_CNT_MASK) + +#define GPC_MLPCR_MEM_EXT_CNT_MASK (0xFF0000U) +#define GPC_MLPCR_MEM_EXT_CNT_SHIFT (16U) +#define GPC_MLPCR_MEM_EXT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEM_EXT_CNT_SHIFT)) & GPC_MLPCR_MEM_EXT_CNT_MASK) + +#define GPC_MLPCR_MEMLP_RET_PGEN_MASK (0xFF000000U) +#define GPC_MLPCR_MEMLP_RET_PGEN_SHIFT (24U) +#define GPC_MLPCR_MEMLP_RET_PGEN(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_PGEN_SHIFT)) & GPC_MLPCR_MEMLP_RET_PGEN_MASK) +/*! @} */ + +/*! @name PGC_ACK_SEL_A53 - PGC acknowledge signal selection of A53 platform */ +/*! @{ */ + +#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK (0x1U) +#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT (0U) +#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK) + +#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK (0x2U) +#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT (1U) +#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK) + +#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK (0x4U) +#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT (2U) +#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK) + +#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK (0x2000U) +#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT (13U) +#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK) + +#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK (0x4000U) +#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT (14U) +#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK) + +#define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK (0x8000U) +#define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT (15U) +#define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK) + +#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK (0x10000U) +#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT (16U) +#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK) + +#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK (0x20000U) +#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT (17U) +#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK) + +#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK (0x40000U) +#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT (18U) +#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK) + +#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK (0x20000000U) +#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT (29U) +#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK) + +#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK (0x40000000U) +#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT (30U) +#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK) + +#define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK (0x80000000U) +#define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT (31U) +#define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK) +/*! @} */ + +/*! @name PGC_ACK_SEL_M4 - PGC acknowledge signal selection of M4 platform */ +/*! @{ */ + +#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_MASK (0x1U) +#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_SHIFT (0U) +#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_MASK) + +#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_MASK (0x8000U) +#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_SHIFT (15U) +#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_MASK) + +#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_MASK (0x10000U) +#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_SHIFT (16U) +#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_MASK) + +#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_MASK (0x80000000U) +#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_SHIFT (31U) +#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_MASK) +/*! @} */ + +/*! @name MISC - GPC Miscellaneous register */ +/*! @{ */ + +#define GPC_MISC_M4_SLEEP_HOLD_REQ_B_MASK (0x1U) +#define GPC_MISC_M4_SLEEP_HOLD_REQ_B_SHIFT (0U) +/*! M4_SLEEP_HOLD_REQ_B + * 0b0..Hold M4 platform in sleep mode. This bit is a software control bit to M4 platform. + * 0b1..Don't hold M4 platform in sleep mode. + */ +#define GPC_MISC_M4_SLEEP_HOLD_REQ_B(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M4_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_M4_SLEEP_HOLD_REQ_B_MASK) + +#define GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK (0x2U) +#define GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT (1U) +/*! A53_SLEEP_HOLD_REQ_B + * 0b0..Hold A53 platform in sleep mode. This bit is a software control bit to A53 platform. + * 0b1..Don't hold A53 platform in sleep mode. + */ +#define GPC_MISC_A53_SLEEP_HOLD_REQ_B(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK) + +#define GPC_MISC_GPC_IRQ_MASK_MASK (0x20U) +#define GPC_MISC_GPC_IRQ_MASK_SHIFT (5U) +/*! GPC_IRQ_MASK + * 0b0..Not masked + * 0b1..Interrupt / event is masked + */ +#define GPC_MISC_GPC_IRQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_GPC_IRQ_MASK_SHIFT)) & GPC_MISC_GPC_IRQ_MASK_MASK) + +#define GPC_MISC_M4_PDN_REQ_MASK_MASK (0x100U) +#define GPC_MISC_M4_PDN_REQ_MASK_SHIFT (8U) +/*! M4_PDN_REQ_MASK + * 0b0..M4 power down request to virtual M4 PGC will be masked. + * 0b1..M4 power down request to virtual M4 PGC will not be masked. Set this bit to 1'b1 when M4 virtual PGC is used. + */ +#define GPC_MISC_M4_PDN_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M4_PDN_REQ_MASK_SHIFT)) & GPC_MISC_M4_PDN_REQ_MASK_MASK) + +#define GPC_MISC_A53_BYPASS_PUP_MASK_MASK (0x1000000U) +#define GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT (24U) +#define GPC_MISC_A53_BYPASS_PUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_A53_BYPASS_PUP_MASK_MASK) + +#define GPC_MISC_M4_BYPASS_PUP_MASK_MASK (0x2000000U) +#define GPC_MISC_M4_BYPASS_PUP_MASK_SHIFT (25U) +#define GPC_MISC_M4_BYPASS_PUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M4_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_M4_BYPASS_PUP_MASK_MASK) +/*! @} */ + +/*! @name IMR_CORE0_A53 - IRQ masking register 1 of A53 core0..IRQ masking register 4 of A53 core0 */ +/*! @{ */ + +#define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT (0U) +/*! IMR1_CORE0_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE0_A53_IMR1_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK) + +#define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT (0U) +/*! IMR2_CORE0_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE0_A53_IMR2_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK) + +#define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT (0U) +/*! IMR3_CORE0_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE0_A53_IMR3_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK) + +#define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT (0U) +/*! IMR4_CORE0_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE0_A53_IMR4_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK) +/*! @} */ + +/* The count of GPC_IMR_CORE0_A53 */ +#define GPC_IMR_CORE0_A53_COUNT (4U) + +/*! @name IMR_CORE1_A53 - IRQ masking register 1 of A53 core1..IRQ masking register 4 of A53 core1 */ +/*! @{ */ + +#define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT (0U) +/*! IMR1_CORE1_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE1_A53_IMR1_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK) + +#define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT (0U) +/*! IMR2_CORE1_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE1_A53_IMR2_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK) + +#define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT (0U) +/*! IMR3_CORE1_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE1_A53_IMR3_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK) + +#define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT (0U) +/*! IMR4_CORE1_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE1_A53_IMR4_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK) +/*! @} */ + +/* The count of GPC_IMR_CORE1_A53 */ +#define GPC_IMR_CORE1_A53_COUNT (4U) + +/*! @name IMR_M4 - IRQ masking register 1 of M4..IRQ masking register 4 of M4 */ +/*! @{ */ + +#define GPC_IMR_M4_IMR1_M4_MASK (0xFFFFFFFFU) +#define GPC_IMR_M4_IMR1_M4_SHIFT (0U) +/*! IMR1_M4 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_M4_IMR1_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M4_IMR1_M4_SHIFT)) & GPC_IMR_M4_IMR1_M4_MASK) + +#define GPC_IMR_M4_IMR2_M4_MASK (0xFFFFFFFFU) +#define GPC_IMR_M4_IMR2_M4_SHIFT (0U) +/*! IMR2_M4 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_M4_IMR2_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M4_IMR2_M4_SHIFT)) & GPC_IMR_M4_IMR2_M4_MASK) + +#define GPC_IMR_M4_IMR3_M4_MASK (0xFFFFFFFFU) +#define GPC_IMR_M4_IMR3_M4_SHIFT (0U) +/*! IMR3_M4 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_M4_IMR3_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M4_IMR3_M4_SHIFT)) & GPC_IMR_M4_IMR3_M4_MASK) + +#define GPC_IMR_M4_IMR4_M4_MASK (0xFFFFFFFFU) +#define GPC_IMR_M4_IMR4_M4_SHIFT (0U) +/*! IMR4_M4 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_M4_IMR4_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M4_IMR4_M4_SHIFT)) & GPC_IMR_M4_IMR4_M4_MASK) +/*! @} */ + +/* The count of GPC_IMR_M4 */ +#define GPC_IMR_M4_COUNT (4U) + +/*! @name ISR_A53 - IRQ status register 1 of A53..IRQ status register 4 of A53 */ +/*! @{ */ + +#define GPC_ISR_A53_ISR1_A53_MASK (0xFFFFFFFFU) +#define GPC_ISR_A53_ISR1_A53_SHIFT (0U) +#define GPC_ISR_A53_ISR1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR1_A53_SHIFT)) & GPC_ISR_A53_ISR1_A53_MASK) + +#define GPC_ISR_A53_ISR2_A53_MASK (0xFFFFFFFFU) +#define GPC_ISR_A53_ISR2_A53_SHIFT (0U) +#define GPC_ISR_A53_ISR2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR2_A53_SHIFT)) & GPC_ISR_A53_ISR2_A53_MASK) + +#define GPC_ISR_A53_ISR3_A53_MASK (0xFFFFFFFFU) +#define GPC_ISR_A53_ISR3_A53_SHIFT (0U) +#define GPC_ISR_A53_ISR3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR3_A53_SHIFT)) & GPC_ISR_A53_ISR3_A53_MASK) + +#define GPC_ISR_A53_ISR4_A53_MASK (0xFFFFFFFFU) +#define GPC_ISR_A53_ISR4_A53_SHIFT (0U) +#define GPC_ISR_A53_ISR4_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR4_A53_SHIFT)) & GPC_ISR_A53_ISR4_A53_MASK) +/*! @} */ + +/* The count of GPC_ISR_A53 */ +#define GPC_ISR_A53_COUNT (4U) + +/*! @name ISR_M4 - IRQ status register 1 of M4..IRQ status register 4 of M4 */ +/*! @{ */ + +#define GPC_ISR_M4_ISR1_M4_MASK (0xFFFFFFFFU) +#define GPC_ISR_M4_ISR1_M4_SHIFT (0U) +#define GPC_ISR_M4_ISR1_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M4_ISR1_M4_SHIFT)) & GPC_ISR_M4_ISR1_M4_MASK) + +#define GPC_ISR_M4_ISR2_M4_MASK (0xFFFFFFFFU) +#define GPC_ISR_M4_ISR2_M4_SHIFT (0U) +#define GPC_ISR_M4_ISR2_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M4_ISR2_M4_SHIFT)) & GPC_ISR_M4_ISR2_M4_MASK) + +#define GPC_ISR_M4_ISR3_M4_MASK (0xFFFFFFFFU) +#define GPC_ISR_M4_ISR3_M4_SHIFT (0U) +#define GPC_ISR_M4_ISR3_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M4_ISR3_M4_SHIFT)) & GPC_ISR_M4_ISR3_M4_MASK) + +#define GPC_ISR_M4_ISR4_M4_MASK (0xFFFFFFFFU) +#define GPC_ISR_M4_ISR4_M4_SHIFT (0U) +#define GPC_ISR_M4_ISR4_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M4_ISR4_M4_SHIFT)) & GPC_ISR_M4_ISR4_M4_MASK) +/*! @} */ + +/* The count of GPC_ISR_M4 */ +#define GPC_ISR_M4_COUNT (4U) + +/*! @name SLT0_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT1_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT2_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT3_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT4_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT5_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT6_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT7_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT8_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT9_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT10_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT11_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT12_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT13_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT14_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name PGC_CPU_0_1_MAPPING - PGC CPU mapping */ +/*! @{ */ + +#define GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN_MASK (0x1U) +#define GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN_SHIFT (0U) +#define GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_MASK (0x4U) +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_SHIFT (2U) +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN_MASK (0x8U) +#define GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN_SHIFT (3U) +#define GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_MASK (0x10U) +#define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_SHIFT (4U) +#define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN_MASK (0x20U) +#define GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN_SHIFT (5U) +#define GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_MASK (0x80U) +#define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_SHIFT (7U) +#define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN_MASK (0x100U) +#define GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN_SHIFT (8U) +#define GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_MASK (0x200U) +#define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_SHIFT (9U) +#define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN_MASK (0x400U) +#define GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN_SHIFT (10U) +#define GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN_MASK (0x800U) +#define GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN_SHIFT (11U) +#define GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN_MASK (0x1000U) +#define GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN_SHIFT (12U) +#define GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN_MASK (0x2000U) +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN_SHIFT (13U) +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN_MASK (0x4000U) +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN_SHIFT (14U) +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN_MASK (0x8000U) +#define GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN_SHIFT (15U) +#define GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN_MASK (0x10000U) +#define GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN_SHIFT (16U) +#define GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN_MASK (0x40000U) +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN_SHIFT (18U) +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN_MASK (0x80000U) +#define GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN_SHIFT (19U) +#define GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN_MASK (0x100000U) +#define GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN_SHIFT (20U) +#define GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN_MASK (0x200000U) +#define GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN_SHIFT (21U) +#define GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN_MASK (0x800000U) +#define GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN_SHIFT (23U) +#define GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN_MASK (0x1000000U) +#define GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN_SHIFT (24U) +#define GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN_MASK (0x2000000U) +#define GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN_SHIFT (25U) +#define GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN_MASK (0x4000000U) +#define GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN_SHIFT (26U) +#define GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN_MASK (0x8000000U) +#define GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN_SHIFT (27U) +#define GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN_MASK (0x10000000U) +#define GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN_SHIFT (28U) +#define GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN_MASK (0x20000000U) +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN_SHIFT (29U) +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN_MASK (0x40000000U) +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN_SHIFT (30U) +#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN_MASK) + +#define GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN_MASK (0x80000000U) +#define GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN_SHIFT (31U) +#define GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN_MASK) +/*! @} */ + +/*! @name CPU_PGC_SW_PUP_REQ - CPU PGC software power up trigger */ +/*! @{ */ + +#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK (0x1U) +#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT (0U) +#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK) + +#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK (0x2U) +#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT (1U) +#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK) + +#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK (0x4U) +#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT (2U) +#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK) + +#define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK (0x8U) +#define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT (3U) +#define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK) + +#define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x10U) +#define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (4U) +#define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK) +/*! @} */ + +/*! @name MIX_PGC_SW_PUP_REQ - MIX PGC software power up trigger */ +/*! @{ */ + +#define GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ_MASK (0x1U) +#define GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ_SHIFT (0U) +#define GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ_SHIFT)) & GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ_MASK) +/*! @} */ + +/*! @name PU_PGC_SW_PUP_REQ - PU PGC software up trigger */ +/*! @{ */ + +#define GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ_MASK (0x1U) +#define GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ_SHIFT (0U) +#define GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ_MASK) + +#define GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ_MASK (0x2U) +#define GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ_SHIFT (1U) +#define GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ_MASK) + +#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_MASK (0x4U) +#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_SHIFT (2U) +#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_MASK) + +#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ_MASK (0x8U) +#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ_SHIFT (3U) +#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ_MASK) + +#define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_MASK (0x20U) +#define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_SHIFT (5U) +#define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_MASK) + +#define GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ_MASK (0x40U) +#define GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ_SHIFT (6U) +#define GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ_MASK) + +#define GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ_MASK (0x80U) +#define GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ_SHIFT (7U) +#define GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ_MASK) + +#define GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ_MASK (0x100U) +#define GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ_SHIFT (8U) +#define GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ_MASK) + +#define GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ_MASK (0x200U) +#define GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ_SHIFT (9U) +#define GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ_MASK) + +#define GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ_MASK (0x400U) +#define GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ_SHIFT (10U) +#define GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ_MASK) + +#define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ_MASK (0x800U) +#define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ_SHIFT (11U) +#define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ_MASK) + +#define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ_MASK (0x1000U) +#define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ_SHIFT (12U) +#define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ_MASK) + +#define GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ_MASK (0x2000U) +#define GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ_SHIFT (13U) +#define GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ_MASK) +/*! @} */ + +/*! @name CPU_PGC_SW_PDN_REQ - CPU PGC software down trigger */ +/*! @{ */ + +#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK (0x1U) +#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT (0U) +#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK) + +#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK (0x2U) +#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT (1U) +#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK) + +#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ_MASK (0x4U) +#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ_SHIFT (2U) +#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ_MASK) + +#define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ_MASK (0x8U) +#define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ_SHIFT (3U) +#define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ_MASK) + +#define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x10U) +#define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (4U) +#define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK) +/*! @} */ + +/*! @name MIX_PGC_SW_PDN_REQ - MIX PGC software power down trigger */ +/*! @{ */ + +#define GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ_MASK (0x1U) +#define GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ_SHIFT (0U) +#define GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ_SHIFT)) & GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ_MASK) +/*! @} */ + +/*! @name PU_PGC_SW_PDN_REQ - PU PGC software down trigger */ +/*! @{ */ + +#define GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ_MASK (0x1U) +#define GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ_SHIFT (0U) +#define GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ_MASK) + +#define GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ_MASK (0x2U) +#define GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ_SHIFT (1U) +#define GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ_MASK) + +#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_MASK (0x4U) +#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_SHIFT (2U) +#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_MASK) + +#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ_MASK (0x8U) +#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ_SHIFT (3U) +#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ_MASK) + +#define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_MASK (0x20U) +#define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_SHIFT (5U) +#define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_MASK) + +#define GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ_MASK (0x40U) +#define GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ_SHIFT (6U) +#define GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ_MASK) + +#define GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ_MASK (0x80U) +#define GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ_SHIFT (7U) +#define GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ_MASK) + +#define GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ_MASK (0x100U) +#define GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ_SHIFT (8U) +#define GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ_MASK) + +#define GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ_MASK (0x200U) +#define GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ_SHIFT (9U) +#define GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ_MASK) + +#define GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ_MASK (0x400U) +#define GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ_SHIFT (10U) +#define GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ_MASK) + +#define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ_MASK (0x800U) +#define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ_SHIFT (11U) +#define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ_MASK) + +#define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ_MASK (0x1000U) +#define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ_SHIFT (12U) +#define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ_MASK) + +#define GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ_MASK (0x2000U) +#define GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ_SHIFT (13U) +#define GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ_MASK) +/*! @} */ + +/*! @name LPCR_A53_BSC2 - Basic Low power control register of A53 platform */ +/*! @{ */ + +#define GPC_LPCR_A53_BSC2_LPM2_MASK (0x3U) +#define GPC_LPCR_A53_BSC2_LPM2_SHIFT (0U) +/*! LPM2 + * 0b00..Remain in RUN mode + * 0b01..Transfer to WAIT mode + * 0b10..Transfer to STOP mode + * 0b11..Reserved + */ +#define GPC_LPCR_A53_BSC2_LPM2(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM2_SHIFT)) & GPC_LPCR_A53_BSC2_LPM2_MASK) + +#define GPC_LPCR_A53_BSC2_LPM3_MASK (0xCU) +#define GPC_LPCR_A53_BSC2_LPM3_SHIFT (2U) +/*! LPM3 + * 0b00..Remain in RUN mode + * 0b01..Transfer to WAIT mode + * 0b10..Transfer to STOP mode + * 0b11..Reserved + */ +#define GPC_LPCR_A53_BSC2_LPM3(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM3_SHIFT)) & GPC_LPCR_A53_BSC2_LPM3_MASK) +/*! @} */ + +/*! @name CPU_PGC_PUP_STATUS1 - CPU PGC software up trigger status1 */ +/*! @{ */ + +#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK (0x1U) +#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT (0U) +#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK) + +#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK (0x2U) +#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT (1U) +#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK) + +#define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS_MASK (0x4U) +#define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS_SHIFT (2U) +#define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS_MASK) + +#define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK (0x8U) +#define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT (3U) +#define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK) + +#define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ_MASK (0x10U) +#define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ_SHIFT (4U) +#define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ_MASK) +/*! @} */ + +/*! @name A53_MIX_PGC_PUP_STATUS - A53 MIX software up trigger status register */ +/*! @{ */ + +#define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK (0x1U) +#define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT (0U) +#define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT)) & GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK) +/*! @} */ + +/* The count of GPC_A53_MIX_PGC_PUP_STATUS */ +#define GPC_A53_MIX_PGC_PUP_STATUS_COUNT (3U) + +/*! @name M4_MIX_PGC_PUP_STATUS - M4 MIX PGC software up trigger status register */ +/*! @{ */ + +#define GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS_MASK (0x1U) +#define GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS_SHIFT (0U) +#define GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS_SHIFT)) & GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS_MASK) +/*! @} */ + +/* The count of GPC_M4_MIX_PGC_PUP_STATUS */ +#define GPC_M4_MIX_PGC_PUP_STATUS_COUNT (3U) + +/*! @name A53_PU_PGC_PUP_STATUS - A53 PU software up trigger status register */ +/*! @{ */ + +#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS_MASK (0x1U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS_SHIFT (0U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS_MASK) + +#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS_MASK (0x2U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS_SHIFT (1U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS_MASK) + +#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_MASK (0x4U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_SHIFT (2U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_MASK) + +#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS_MASK (0x8U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS_SHIFT (3U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS_MASK) + +#define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_MASK (0x20U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_SHIFT (5U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_MASK) + +#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS_MASK (0x80U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS_SHIFT (7U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS_MASK) + +#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS_MASK (0x100U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS_SHIFT (8U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS_MASK) + +#define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS_MASK (0x200U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS_SHIFT (9U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS_MASK) + +#define GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS_MASK (0x400U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS_SHIFT (10U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS_MASK) + +#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS_MASK (0x800U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS_SHIFT (11U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS_MASK) + +#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS_MASK (0x1000U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS_SHIFT (12U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS_MASK) + +#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS_MASK (0x2000U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS_SHIFT (13U) +#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS_MASK) +/*! @} */ + +/* The count of GPC_A53_PU_PGC_PUP_STATUS */ +#define GPC_A53_PU_PGC_PUP_STATUS_COUNT (3U) + +/*! @name M4_PU_PGC_PUP_STATUS - M4 PU PGC software up trigger status register */ +/*! @{ */ + +#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS_MASK (0x1U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS_SHIFT (0U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS_MASK) + +#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS_MASK (0x2U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS_SHIFT (1U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS_MASK) + +#define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS_MASK (0x4U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS_SHIFT (2U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS_MASK) + +#define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS_MASK (0x8U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS_SHIFT (3U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS_MASK) + +#define GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS_MASK (0x20U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS_SHIFT (5U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS_MASK) + +#define GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS_MASK (0x80U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS_SHIFT (7U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS_MASK) + +#define GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS_MASK (0x100U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS_SHIFT (8U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS_MASK) + +#define GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS_MASK (0x200U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS_SHIFT (9U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS_MASK) + +#define GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS_MASK (0x400U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS_SHIFT (10U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS_MASK) + +#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS_MASK (0x800U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS_SHIFT (11U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS_MASK) + +#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS_MASK (0x1000U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS_SHIFT (12U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS_MASK) + +#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS_MASK (0x2000U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS_SHIFT (13U) +#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS_MASK) +/*! @} */ + +/* The count of GPC_M4_PU_PGC_PUP_STATUS */ +#define GPC_M4_PU_PGC_PUP_STATUS_COUNT (3U) + +/*! @name CPU_PGC_PDN_STATUS1 - CPU PGC software dn trigger status1 */ +/*! @{ */ + +#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK (0x1U) +#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT (0U) +#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK) + +#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK (0x2U) +#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT (1U) +#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK) + +#define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS_MASK (0x4U) +#define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS_SHIFT (2U) +#define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS_MASK) + +#define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK (0x8U) +#define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT (3U) +#define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK) + +#define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ_MASK (0x10U) +#define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ_SHIFT (4U) +#define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ_MASK) +/*! @} */ + +/*! @name A53_MIX_PGC_PDN_STATUS - A53 MIX software down trigger status register */ +/*! @{ */ + +#define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK (0x1U) +#define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT (0U) +#define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT)) & GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK) +/*! @} */ + +/* The count of GPC_A53_MIX_PGC_PDN_STATUS */ +#define GPC_A53_MIX_PGC_PDN_STATUS_COUNT (3U) + +/*! @name M4_MIX_PGC_PDN_STATUS - M4 MIX PGC software power down trigger status register */ +/*! @{ */ + +#define GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS_MASK (0x1U) +#define GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS_SHIFT (0U) +#define GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS_SHIFT)) & GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS_MASK) +/*! @} */ + +/* The count of GPC_M4_MIX_PGC_PDN_STATUS */ +#define GPC_M4_MIX_PGC_PDN_STATUS_COUNT (3U) + +/*! @name A53_PU_PGC_PDN_STATUS - A53 PU PGC software down trigger status */ +/*! @{ */ + +#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS_MASK (0x1U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS_SHIFT (0U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS_MASK) + +#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS_MASK (0x2U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS_SHIFT (1U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS_MASK) + +#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_MASK (0x4U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_SHIFT (2U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_MASK) + +#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS_MASK (0x8U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS_SHIFT (3U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS_MASK) + +#define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_MASK (0x20U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_SHIFT (5U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_MASK) + +#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS_MASK (0x80U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS_SHIFT (7U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS_MASK) + +#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS_MASK (0x100U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS_SHIFT (8U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS_MASK) + +#define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS_MASK (0x200U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS_SHIFT (9U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS_MASK) + +#define GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS_MASK (0x400U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS_SHIFT (10U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS_MASK) + +#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS_MASK (0x800U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS_SHIFT (11U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS_MASK) + +#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS_MASK (0x1000U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS_SHIFT (12U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS_MASK) + +#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS_MASK (0x2000U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS_SHIFT (13U) +#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS_MASK) +/*! @} */ + +/* The count of GPC_A53_PU_PGC_PDN_STATUS */ +#define GPC_A53_PU_PGC_PDN_STATUS_COUNT (3U) + +/*! @name M4_PU_PGC_PDN_STATUS - M4 PU PGC software down trigger status */ +/*! @{ */ + +#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS_MASK (0x1U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS_SHIFT (0U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS_MASK) + +#define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS_MASK (0x2U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS_SHIFT (1U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS_MASK) + +#define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS_MASK (0x4U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS_SHIFT (2U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS_MASK) + +#define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS_MASK (0x8U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS_SHIFT (3U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS_MASK) + +#define GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS_MASK (0x20U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS_SHIFT (5U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS_MASK) + +#define GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS_MASK (0x80U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS_SHIFT (7U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS_MASK) + +#define GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS_MASK (0x100U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS_SHIFT (8U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS_MASK) + +#define GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS_MASK (0x200U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS_SHIFT (9U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS_MASK) + +#define GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS_MASK (0x400U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS_SHIFT (10U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS_MASK) + +#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS_MASK (0x800U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS_SHIFT (11U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS_MASK) + +#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS_MASK (0x1000U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS_SHIFT (12U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS_MASK) + +#define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS_MASK (0x2000U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS_SHIFT (13U) +#define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS_MASK) +/*! @} */ + +/* The count of GPC_M4_PU_PGC_PDN_STATUS */ +#define GPC_M4_PU_PGC_PDN_STATUS_COUNT (3U) + +/*! @name A53_MIX_PDN_FLG - A53 MIX PDN FLG */ +/*! @{ */ + +#define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK (0x1U) +#define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT (0U) +#define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT)) & GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK) +/*! @} */ + +/*! @name A53_PU_PDN_FLG - A53 PU PDN FLG */ +/*! @{ */ + +#define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK (0x3FFFU) +#define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT (0U) +#define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT)) & GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK) +/*! @} */ + +/*! @name M4_MIX_PDN_FLG - M4 MIX PDN FLG */ +/*! @{ */ + +#define GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_MASK (0x1U) +#define GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_SHIFT (0U) +#define GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_SHIFT)) & GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_MASK) +/*! @} */ + +/*! @name M4_PU_PDN_FLG - M4 PU PDN FLG */ +/*! @{ */ + +#define GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG_MASK (0x3FFFU) +#define GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG_SHIFT (0U) +#define GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG_SHIFT)) & GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG_MASK) +/*! @} */ + +/*! @name IMR_CORE2_A53 - IRQ masking register 1 of A53 core2..IRQ masking register 4 of A53 core2 */ +/*! @{ */ + +#define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT (0U) +/*! IMR1_CORE2_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE2_A53_IMR1_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK) + +#define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT (0U) +/*! IMR2_CORE2_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE2_A53_IMR2_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK) + +#define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT (0U) +/*! IMR3_CORE2_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE2_A53_IMR3_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK) + +#define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT (0U) +/*! IMR4_CORE2_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE2_A53_IMR4_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK) +/*! @} */ + +/* The count of GPC_IMR_CORE2_A53 */ +#define GPC_IMR_CORE2_A53_COUNT (4U) + +/*! @name IMR_CORE3_A53 - IRQ masking register 1 of A53 core3..IRQ masking register 4 of A53 core3 */ +/*! @{ */ + +#define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT (0U) +/*! IMR1_CORE3_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE3_A53_IMR1_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK) + +#define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT (0U) +/*! IMR2_CORE3_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE3_A53_IMR2_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK) + +#define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT (0U) +/*! IMR3_CORE3_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE3_A53_IMR3_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK) + +#define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK (0xFFFFFFFFU) +#define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT (0U) +/*! IMR4_CORE3_A53 + * 0b00000000000000000000000000000000..IRQ not masked + * 0b00000000000000000000000000000001..IRQ masked + */ +#define GPC_IMR_CORE3_A53_IMR4_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK) +/*! @} */ + +/* The count of GPC_IMR_CORE3_A53 */ +#define GPC_IMR_CORE3_A53_COUNT (4U) + +/*! @name ACK_SEL_A53_PU - PGC acknowledge signal selection of A53 platform for PUs */ +/*! @{ */ + +#define GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK_MASK (0x1U) +#define GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK_SHIFT (0U) +#define GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_MASK (0x4U) +#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_SHIFT (2U) +#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK_MASK (0x8U) +#define GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK_SHIFT (3U) +#define GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_MASK (0x10U) +#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_SHIFT (4U) +#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK_MASK (0x20U) +#define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK_SHIFT (5U) +#define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_MASK (0x80U) +#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_SHIFT (7U) +#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK_MASK (0x100U) +#define GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK_SHIFT (8U) +#define GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK_MASK (0x200U) +#define GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK_SHIFT (9U) +#define GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK_MASK (0x400U) +#define GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK_SHIFT (10U) +#define GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK_MASK (0x800U) +#define GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK_SHIFT (11U) +#define GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK_MASK (0x1000U) +#define GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK_SHIFT (12U) +#define GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK_MASK (0x2000U) +#define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK_SHIFT (13U) +#define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK_MASK (0x4000U) +#define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK_SHIFT (14U) +#define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK_MASK (0x8000U) +#define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK_SHIFT (15U) +#define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK_MASK (0x10000U) +#define GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK_SHIFT (16U) +#define GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_MASK (0x40000U) +#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_SHIFT (18U) +#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK_MASK (0x80000U) +#define GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK_SHIFT (19U) +#define GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_MASK (0x100000U) +#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_SHIFT (20U) +#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK_MASK (0x200000U) +#define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK_SHIFT (21U) +#define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_MASK (0x800000U) +#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_SHIFT (23U) +#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK_MASK (0x1000000U) +#define GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK_SHIFT (24U) +#define GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK_MASK (0x2000000U) +#define GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK_SHIFT (25U) +#define GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK_MASK (0x4000000U) +#define GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK_SHIFT (26U) +#define GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK_MASK (0x8000000U) +#define GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK_SHIFT (27U) +#define GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK_MASK (0x10000000U) +#define GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK_SHIFT (28U) +#define GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK_MASK (0x20000000U) +#define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK_SHIFT (29U) +#define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK_MASK (0x40000000U) +#define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK_SHIFT (30U) +#define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK_MASK (0x80000000U) +#define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK_SHIFT (31U) +#define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK_MASK) +/*! @} */ + +/*! @name ACK_SEL_M4_PU - PGC acknowledge signal selection of M4 platform for PUs */ +/*! @{ */ + +#define GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK_MASK (0x1U) +#define GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK_SHIFT (0U) +#define GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK_MASK (0x4U) +#define GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK_SHIFT (2U) +#define GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK_MASK (0x8U) +#define GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK_SHIFT (3U) +#define GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK_MASK (0x10U) +#define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK_SHIFT (4U) +#define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK_MASK (0x20U) +#define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK_SHIFT (5U) +#define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK_MASK (0x80U) +#define GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK_SHIFT (7U) +#define GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK_MASK (0x100U) +#define GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK_SHIFT (8U) +#define GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK_MASK (0x200U) +#define GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK_SHIFT (9U) +#define GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK_MASK (0x400U) +#define GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK_SHIFT (10U) +#define GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK_MASK (0x800U) +#define GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK_SHIFT (11U) +#define GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK_MASK (0x1000U) +#define GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK_SHIFT (12U) +#define GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK_MASK (0x2000U) +#define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK_SHIFT (13U) +#define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK_MASK (0x4000U) +#define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK_SHIFT (14U) +#define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK_MASK (0x8000U) +#define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK_SHIFT (15U) +#define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK_MASK (0x10000U) +#define GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK_SHIFT (16U) +#define GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK_MASK (0x40000U) +#define GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK_SHIFT (18U) +#define GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK_MASK (0x80000U) +#define GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK_SHIFT (19U) +#define GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK_MASK (0x100000U) +#define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK_SHIFT (20U) +#define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK_MASK (0x200000U) +#define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK_SHIFT (21U) +#define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK_MASK (0x800000U) +#define GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK_SHIFT (23U) +#define GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK_MASK (0x1000000U) +#define GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK_SHIFT (24U) +#define GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK_MASK (0x2000000U) +#define GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK_SHIFT (25U) +#define GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK_MASK (0x4000000U) +#define GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK_SHIFT (26U) +#define GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK_MASK (0x8000000U) +#define GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK_SHIFT (27U) +#define GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK_MASK (0x10000000U) +#define GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK_SHIFT (28U) +#define GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK_MASK (0x20000000U) +#define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK_SHIFT (29U) +#define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK_MASK (0x40000000U) +#define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK_SHIFT (30U) +#define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK_MASK) + +#define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK_MASK (0x80000000U) +#define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK_SHIFT (31U) +#define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK_MASK) +/*! @} */ + +/*! @name SLT15_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT16_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT17_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT18_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name SLT19_CFG - Slot configure register for A53 core */ +/*! @{ */ + +#define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/*! @name PU_PWRHSK - Power handshake register */ +/*! @{ */ + +#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK (0x1U) +#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT (0U) +#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK) + +#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK (0x2U) +#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT (1U) +#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK) + +#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ_MASK (0x4U) +#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ_SHIFT (2U) +#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ_MASK) + +#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ_MASK (0x8U) +#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ_SHIFT (3U) +#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ_MASK) + +#define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN_MASK (0x10U) +#define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN_SHIFT (4U) +#define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN_MASK) + +#define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN_MASK (0x20U) +#define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN_SHIFT (5U) +#define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN_MASK) + +#define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN_MASK (0x40U) +#define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN_SHIFT (6U) +#define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN_MASK) + +#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_MASK (0x10000U) +#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_SHIFT (16U) +#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_MASK) + +#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_MASK (0x20000U) +#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_SHIFT (17U) +#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_MASK) + +#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_MASK (0x40000U) +#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_SHIFT (18U) +#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_MASK) + +#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_MASK (0x80000U) +#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_SHIFT (19U) +#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_MASK) + +#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK_MASK (0x100000U) +#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK_SHIFT (20U) +#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK_MASK) + +#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE_MASK (0x200000U) +#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE_SHIFT (21U) +#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE_MASK) + +#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK_MASK (0x400000U) +#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK_SHIFT (22U) +#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK_MASK) + +#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE_MASK (0x800000U) +#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE_SHIFT (23U) +#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE_MASK) + +#define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN_MASK (0x1000000U) +#define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN_SHIFT (24U) +#define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN_MASK) + +#define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN_MASK (0x2000000U) +#define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN_SHIFT (25U) +#define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN_MASK) + +#define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN_MASK (0x4000000U) +#define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN_SHIFT (26U) +#define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN_MASK) +/*! @} */ + +/*! @name SLT_CFG_PU - Slot configure register for PUs */ +/*! @{ */ + +#define GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL_MASK (0x1U) +#define GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL_SHIFT (0U) +#define GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL_MASK (0x2U) +#define GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL_SHIFT (1U) +#define GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_MASK (0x4U) +#define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_SHIFT (2U) +#define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_MASK (0x8U) +#define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_SHIFT (3U) +#define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL_MASK (0x10U) +#define GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL_SHIFT (4U) +#define GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL_MASK (0x20U) +#define GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL_SHIFT (5U) +#define GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_MASK (0x40U) +#define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_SHIFT (6U) +#define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_MASK (0x80U) +#define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_SHIFT (7U) +#define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL_MASK (0x100U) +#define GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL_SHIFT (8U) +#define GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL_MASK (0x200U) +#define GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL_SHIFT (9U) +#define GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL_MASK (0x1000U) +#define GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL_SHIFT (12U) +#define GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL_MASK (0x2000U) +#define GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL_SHIFT (13U) +#define GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_MASK (0x4000U) +#define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_SHIFT (14U) +#define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_MASK (0x8000U) +#define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_SHIFT (15U) +#define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL_MASK (0x10000U) +#define GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL_SHIFT (16U) +#define GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL_MASK (0x20000U) +#define GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL_SHIFT (17U) +#define GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL_MASK (0x40000U) +#define GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL_SHIFT (18U) +#define GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL_MASK (0x80000U) +#define GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL_SHIFT (19U) +#define GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL_MASK (0x100000U) +#define GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL_SHIFT (20U) +#define GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL_MASK (0x200000U) +#define GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL_SHIFT (21U) +#define GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL_MASK (0x400000U) +#define GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL_SHIFT (22U) +#define GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL_MASK (0x800000U) +#define GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL_SHIFT (23U) +#define GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL_MASK (0x1000000U) +#define GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL_SHIFT (24U) +#define GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL_MASK (0x2000000U) +#define GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL_SHIFT (25U) +#define GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL_MASK (0x4000000U) +#define GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL_SHIFT (26U) +#define GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL_MASK (0x8000000U) +#define GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL_SHIFT (27U) +#define GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL_MASK (0x10000000U) +#define GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL_SHIFT (28U) +#define GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL_MASK (0x20000000U) +#define GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL_SHIFT (29U) +#define GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL_MASK (0x40000000U) +#define GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL_SHIFT (30U) +#define GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL_MASK) + +#define GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL_MASK (0x80000000U) +#define GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL_SHIFT (31U) +#define GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL_MASK) +/*! @} */ + +/* The count of GPC_SLT_CFG_PU */ +#define GPC_SLT_CFG_PU_COUNT (20U) + + +/*! + * @} + */ /* end of group GPC_Register_Masks */ + + +/* GPC - Peripheral instance base addresses */ +/** Peripheral GPC base address */ +#define GPC_BASE (0x303A0000u) +/** Peripheral GPC base pointer */ +#define GPC ((GPC_Type *)GPC_BASE) +/** Array initializer of GPC peripheral base addresses */ +#define GPC_BASE_ADDRS { GPC_BASE } +/** Array initializer of GPC peripheral base pointers */ +#define GPC_BASE_PTRS { GPC } +/** Interrupt vectors for the GPC peripheral type */ +#define GPC_IRQS { GPC_IRQn } + +/*! + * @} + */ /* end of group GPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC_PGC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_PGC_Peripheral_Access_Layer GPC_PGC Peripheral Access Layer + * @{ + */ + +/** GPC_PGC - Register Layout Typedef */ +typedef struct { + __IO uint32_t A53CORE0_CTRL; /**< GPC PGC Control Register, offset: 0x0 */ + __IO uint32_t A53CORE0_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x4 */ + __IO uint32_t A53CORE0_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x8 */ + __IO uint32_t A53CORE0_SR; /**< GPC PGC Status Register, offset: 0xC */ + __IO uint32_t A53CORE0_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x10 */ + uint8_t RESERVED_0[44]; + __IO uint32_t A53CORE1_CTRL; /**< GPC PGC Control Register, offset: 0x40 */ + __IO uint32_t A53CORE1_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x44 */ + __IO uint32_t A53CORE1_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x48 */ + __IO uint32_t A53CORE1_SR; /**< GPC PGC Status Register, offset: 0x4C */ + __IO uint32_t A53CORE1_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x50 */ + uint8_t RESERVED_1[44]; + __IO uint32_t A53CORE2_CTRL; /**< GPC PGC Control Register, offset: 0x80 */ + __IO uint32_t A53CORE2_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x84 */ + __IO uint32_t A53CORE2_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x88 */ + __IO uint32_t A53CORE2_SR; /**< GPC PGC Status Register, offset: 0x8C */ + __IO uint32_t A53CORE2_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x90 */ + uint8_t RESERVED_2[44]; + __IO uint32_t A53CORE3_CTRL; /**< GPC PGC Control Register, offset: 0xC0 */ + __IO uint32_t A53CORE3_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0xC4 */ + __IO uint32_t A53CORE3_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0xC8 */ + __IO uint32_t A53CORE3_SR; /**< GPC PGC Status Register, offset: 0xCC */ + __IO uint32_t A53CORE3_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0xD0 */ + uint8_t RESERVED_3[44]; + __IO uint32_t A53SCU_CTRL; /**< GPC PGC Control Register, offset: 0x100 */ + __IO uint32_t A53SCU_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x104 */ + __IO uint32_t A53SCU_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x108 */ + __IO uint32_t A53SCU_SR; /**< GPC PGC Status Register, offset: 0x10C */ + __IO uint32_t A53SCU_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x110 */ + uint8_t RESERVED_4[236]; + __IO uint32_t MIX_CTRL; /**< GPC PGC Control Register, offset: 0x200 */ + __IO uint32_t MIX_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x204 */ + __IO uint32_t MIX_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x208 */ + __IO uint32_t MIX_SR; /**< GPC PGC Status Register, offset: 0x20C */ + __IO uint32_t MIX_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x210 */ + uint8_t RESERVED_5[492]; + __IO uint32_t PU0_CTRL; /**< GPC PGC Control Register, offset: 0x400 */ + __IO uint32_t PU0_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x404 */ + __IO uint32_t PU0_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x408 */ + __IO uint32_t PU0_SR; /**< GPC PGC Status Register, offset: 0x40C */ + __IO uint32_t PU0_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x410 */ + uint8_t RESERVED_6[44]; + __IO uint32_t PU1_CTRL; /**< GPC PGC Control Register, offset: 0x440 */ + __IO uint32_t PU1_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x444 */ + __IO uint32_t PU1_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x448 */ + __IO uint32_t PU1_SR; /**< GPC PGC Status Register, offset: 0x44C */ + __IO uint32_t PU1_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x450 */ + uint8_t RESERVED_7[44]; + __IO uint32_t PU2_CTRL; /**< GPC PGC Control Register, offset: 0x480 */ + __IO uint32_t PU2_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x484 */ + __IO uint32_t PU2_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x488 */ + __IO uint32_t PU2_SR; /**< GPC PGC Status Register, offset: 0x48C */ + __IO uint32_t PU2_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x490 */ + uint8_t RESERVED_8[44]; + __IO uint32_t PU3_CTRL; /**< GPC PGC Control Register, offset: 0x4C0 */ + __IO uint32_t PU3_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x4C4 */ + __IO uint32_t PU3_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x4C8 */ + __IO uint32_t PU3_SR; /**< GPC PGC Status Register, offset: 0x4CC */ + __IO uint32_t PU3_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x4D0 */ + uint8_t RESERVED_9[44]; + __IO uint32_t PU4_CTRL; /**< GPC PGC Control Register, offset: 0x500 */ + __IO uint32_t PU4_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x504 */ + __IO uint32_t PU4_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x508 */ + __IO uint32_t PU4_SR; /**< GPC PGC Status Register, offset: 0x50C */ + __IO uint32_t PU4_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x510 */ + uint8_t RESERVED_10[44]; + __IO uint32_t PU5_CTRL; /**< GPC PGC Control Register, offset: 0x540 */ + __IO uint32_t PU5_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x544 */ + __IO uint32_t PU5_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x548 */ + __IO uint32_t PU5_SR; /**< GPC PGC Status Register, offset: 0x54C */ + __IO uint32_t PU5_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x550 */ + uint8_t RESERVED_11[44]; + __IO uint32_t PU6_CTRL; /**< GPC PGC Control Register, offset: 0x580 */ + __IO uint32_t PU6_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x584 */ + __IO uint32_t PU6_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x588 */ + __IO uint32_t PU6_SR; /**< GPC PGC Status Register, offset: 0x58C */ + __IO uint32_t PU6_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x590 */ + uint8_t RESERVED_12[44]; + __IO uint32_t PU7_CTRL; /**< GPC PGC Control Register, offset: 0x5C0 */ + __IO uint32_t PU7_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x5C4 */ + __IO uint32_t PU7_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x5C8 */ + __IO uint32_t PU7_SR; /**< GPC PGC Status Register, offset: 0x5CC */ + __IO uint32_t PU7_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x5D0 */ + uint8_t RESERVED_13[44]; + __IO uint32_t PU8_CTRL; /**< GPC PGC Control Register, offset: 0x600 */ + __IO uint32_t PU8_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x604 */ + __IO uint32_t PU8_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x608 */ + __IO uint32_t PU8_SR; /**< GPC PGC Status Register, offset: 0x60C */ + __IO uint32_t PU8_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x610 */ + uint8_t RESERVED_14[44]; + __IO uint32_t PU9_CTRL; /**< GPC PGC Control Register, offset: 0x640 */ + __IO uint32_t PU9_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x644 */ + __IO uint32_t PU9_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x648 */ + __IO uint32_t PU9_SR; /**< GPC PGC Status Register, offset: 0x64C */ + __IO uint32_t PU9_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x650 */ + uint8_t RESERVED_15[44]; + __IO uint32_t PU10_CTRL; /**< GPC PGC Control Register, offset: 0x680 */ + __IO uint32_t PU10_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x684 */ + __IO uint32_t PU10_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x688 */ + __IO uint32_t PU10_SR; /**< GPC PGC Status Register, offset: 0x68C */ + __IO uint32_t PU10_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x690 */ + uint8_t RESERVED_16[44]; + __IO uint32_t PU11_CTRL; /**< GPC PGC Control Register, offset: 0x6C0 */ + __IO uint32_t PU11_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x6C4 */ + __IO uint32_t PU11_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x6C8 */ + __IO uint32_t PU11_SR; /**< GPC PGC Status Register, offset: 0x6CC */ + __IO uint32_t PU11_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x6D0 */ + uint8_t RESERVED_17[44]; + __IO uint32_t PU12_CTRL; /**< GPC PGC Control Register, offset: 0x700 */ + __IO uint32_t PU12_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x704 */ + __IO uint32_t PU12_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x708 */ + __IO uint32_t PU12_SR; /**< GPC PGC Status Register, offset: 0x70C */ + __IO uint32_t PU12_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x710 */ + uint8_t RESERVED_18[44]; + __IO uint32_t PU13_CTRL; /**< GPC PGC Control Register, offset: 0x740 */ + __IO uint32_t PU13_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x744 */ + __IO uint32_t PU13_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x748 */ + __IO uint32_t PU13_SR; /**< GPC PGC Status Register, offset: 0x74C */ + __IO uint32_t PU13_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x750 */ +} GPC_PGC_Type; + +/* ---------------------------------------------------------------------------- + -- GPC_PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_PGC_Register_Masks GPC_PGC Register Masks + * @{ + */ + +/*! @name A53CORE0_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE0_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_A53CORE0_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_A53CORE0_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_PCR_SHIFT)) & GPC_PGC_A53CORE0_CTRL_PCR_MASK) + +#define GPC_PGC_A53CORE0_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_A53CORE0_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_A53CORE0_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53CORE0_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name A53CORE0_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE0_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_A53CORE0_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_A53CORE0_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PUPSCR_SW_SHIFT)) & GPC_PGC_A53CORE0_PUPSCR_SW_MASK) + +#define GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_A53CORE0_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_A53CORE0_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_A53CORE0_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53CORE0_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name A53CORE0_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE0_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_A53CORE0_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_A53CORE0_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_ISO_MASK) + +#define GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_A53CORE0_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_A53CORE0_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_A53CORE0_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name A53CORE0_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE0_SR_PSR_MASK (0x1U) +#define GPC_PGC_A53CORE0_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_A53CORE0_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_PSR_SHIFT)) & GPC_PGC_A53CORE0_SR_PSR_MASK) + +#define GPC_PGC_A53CORE0_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_A53CORE0_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_A53CORE0_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53CORE0_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_A53CORE0_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_A53CORE0_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_A53CORE0_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53CORE0_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name A53CORE0_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE0_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_A53CORE0_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_A53CORE0_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_AUXSW_SW2_SHIFT)) & GPC_PGC_A53CORE0_AUXSW_SW2_MASK) + +#define GPC_PGC_A53CORE0_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_A53CORE0_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_A53CORE0_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53CORE0_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name A53CORE1_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE1_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_A53CORE1_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_A53CORE1_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_PCR_SHIFT)) & GPC_PGC_A53CORE1_CTRL_PCR_MASK) + +#define GPC_PGC_A53CORE1_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_A53CORE1_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_A53CORE1_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53CORE1_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name A53CORE1_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE1_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_A53CORE1_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_A53CORE1_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PUPSCR_SW_SHIFT)) & GPC_PGC_A53CORE1_PUPSCR_SW_MASK) + +#define GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_A53CORE1_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_A53CORE1_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_A53CORE1_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53CORE1_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name A53CORE1_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE1_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_A53CORE1_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_A53CORE1_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_ISO_MASK) + +#define GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_A53CORE1_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_A53CORE1_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_A53CORE1_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name A53CORE1_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE1_SR_PSR_MASK (0x1U) +#define GPC_PGC_A53CORE1_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_A53CORE1_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_PSR_SHIFT)) & GPC_PGC_A53CORE1_SR_PSR_MASK) + +#define GPC_PGC_A53CORE1_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_A53CORE1_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_A53CORE1_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53CORE1_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_A53CORE1_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_A53CORE1_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_A53CORE1_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53CORE1_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name A53CORE1_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE1_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_A53CORE1_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_A53CORE1_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_AUXSW_SW2_SHIFT)) & GPC_PGC_A53CORE1_AUXSW_SW2_MASK) + +#define GPC_PGC_A53CORE1_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_A53CORE1_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_A53CORE1_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53CORE1_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name A53CORE2_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE2_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_A53CORE2_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_A53CORE2_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_PCR_SHIFT)) & GPC_PGC_A53CORE2_CTRL_PCR_MASK) + +#define GPC_PGC_A53CORE2_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_A53CORE2_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_A53CORE2_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53CORE2_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name A53CORE2_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE2_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_A53CORE2_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_A53CORE2_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PUPSCR_SW_SHIFT)) & GPC_PGC_A53CORE2_PUPSCR_SW_MASK) + +#define GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_A53CORE2_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_A53CORE2_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_A53CORE2_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53CORE2_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name A53CORE2_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE2_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_A53CORE2_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_A53CORE2_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_ISO_MASK) + +#define GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_A53CORE2_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_A53CORE2_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_A53CORE2_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name A53CORE2_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE2_SR_PSR_MASK (0x1U) +#define GPC_PGC_A53CORE2_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_A53CORE2_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_PSR_SHIFT)) & GPC_PGC_A53CORE2_SR_PSR_MASK) + +#define GPC_PGC_A53CORE2_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_A53CORE2_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_A53CORE2_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53CORE2_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_A53CORE2_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_A53CORE2_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_A53CORE2_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53CORE2_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name A53CORE2_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE2_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_A53CORE2_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_A53CORE2_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_AUXSW_SW2_SHIFT)) & GPC_PGC_A53CORE2_AUXSW_SW2_MASK) + +#define GPC_PGC_A53CORE2_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_A53CORE2_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_A53CORE2_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53CORE2_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name A53CORE3_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE3_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_A53CORE3_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_A53CORE3_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_PCR_SHIFT)) & GPC_PGC_A53CORE3_CTRL_PCR_MASK) + +#define GPC_PGC_A53CORE3_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_A53CORE3_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_A53CORE3_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53CORE3_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name A53CORE3_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE3_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_A53CORE3_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_A53CORE3_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PUPSCR_SW_SHIFT)) & GPC_PGC_A53CORE3_PUPSCR_SW_MASK) + +#define GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_A53CORE3_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_A53CORE3_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_A53CORE3_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53CORE3_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name A53CORE3_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE3_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_A53CORE3_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_A53CORE3_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_ISO_MASK) + +#define GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_A53CORE3_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_A53CORE3_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_A53CORE3_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name A53CORE3_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE3_SR_PSR_MASK (0x1U) +#define GPC_PGC_A53CORE3_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_A53CORE3_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_PSR_SHIFT)) & GPC_PGC_A53CORE3_SR_PSR_MASK) + +#define GPC_PGC_A53CORE3_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_A53CORE3_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_A53CORE3_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53CORE3_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_A53CORE3_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_A53CORE3_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_A53CORE3_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53CORE3_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name A53CORE3_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_A53CORE3_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_A53CORE3_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_A53CORE3_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_AUXSW_SW2_SHIFT)) & GPC_PGC_A53CORE3_AUXSW_SW2_MASK) + +#define GPC_PGC_A53CORE3_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_A53CORE3_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_A53CORE3_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53CORE3_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name A53SCU_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_A53SCU_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_A53SCU_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_A53SCU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_PCR_SHIFT)) & GPC_PGC_A53SCU_CTRL_PCR_MASK) + +#define GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_A53SCU_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name A53SCU_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_A53SCU_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_A53SCU_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_A53SCU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW_MASK) + +#define GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_A53SCU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name A53SCU_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_A53SCU_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_A53SCU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO_MASK) + +#define GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_A53SCU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name A53SCU_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_A53SCU_SR_PSR_MASK (0x1U) +#define GPC_PGC_A53SCU_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_A53SCU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PSR_SHIFT)) & GPC_PGC_A53SCU_SR_PSR_MASK) + +#define GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_A53SCU_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_A53SCU_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name A53SCU_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_A53SCU_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_A53SCU_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_A53SCU_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_SW2_SHIFT)) & GPC_PGC_A53SCU_AUXSW_SW2_MASK) + +#define GPC_PGC_A53SCU_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_A53SCU_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_A53SCU_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53SCU_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name MIX_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_MIX_CTRL_MIX_PCR_MASK (0x1U) +#define GPC_PGC_MIX_CTRL_MIX_PCR_SHIFT (0U) +/*! MIX_PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_MIX_CTRL_MIX_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_MIX_PCR_SHIFT)) & GPC_PGC_MIX_CTRL_MIX_PCR_MASK) + +#define GPC_PGC_MIX_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_MIX_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_MIX_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_MIX_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_MIX_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_MIX_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_MIX_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_MIX_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name MIX_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_MIX_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_MIX_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_MIX_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PUPSCR_SW_SHIFT)) & GPC_PGC_MIX_PUPSCR_SW_MASK) + +#define GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_MIX_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_MIX_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_MIX_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_MIX_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name MIX_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_MIX_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_MIX_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_MIX_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_ISO_SHIFT)) & GPC_PGC_MIX_PDNSCR_ISO_MASK) + +#define GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_MIX_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_MIX_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_MIX_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_MIX_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name MIX_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_MIX_SR_PSR_MASK (0x1U) +#define GPC_PGC_MIX_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_MIX_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_PSR_SHIFT)) & GPC_PGC_MIX_SR_PSR_MASK) + +#define GPC_PGC_MIX_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_MIX_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_MIX_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_MIX_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_MIX_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_MIX_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_MIX_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_MIX_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name MIX_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_MIX_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_MIX_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_MIX_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_AUXSW_SW2_SHIFT)) & GPC_PGC_MIX_AUXSW_SW2_MASK) + +#define GPC_PGC_MIX_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_MIX_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_MIX_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_MIX_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU0_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU0_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU0_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU0_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_PCR_SHIFT)) & GPC_PGC_PU0_CTRL_PCR_MASK) + +#define GPC_PGC_PU0_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU0_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU0_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU0_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU0_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU0_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU0_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU0_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU0_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU0_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU0_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU0_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PUPSCR_SW_SHIFT)) & GPC_PGC_PU0_PUPSCR_SW_MASK) + +#define GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU0_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU0_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU0_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU0_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU0_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU0_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU0_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU0_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU0_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU0_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU0_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU0_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU0_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU0_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU0_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU0_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU0_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_PSR_SHIFT)) & GPC_PGC_PU0_SR_PSR_MASK) + +#define GPC_PGC_PU0_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU0_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU0_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU0_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU0_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU0_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU0_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU0_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU0_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU0_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU0_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU0_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_AUXSW_SW2_SHIFT)) & GPC_PGC_PU0_AUXSW_SW2_MASK) + +#define GPC_PGC_PU0_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU0_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU0_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU0_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU1_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU1_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU1_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU1_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_PCR_SHIFT)) & GPC_PGC_PU1_CTRL_PCR_MASK) + +#define GPC_PGC_PU1_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU1_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU1_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU1_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU1_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU1_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU1_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU1_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU1_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU1_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU1_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU1_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PUPSCR_SW_SHIFT)) & GPC_PGC_PU1_PUPSCR_SW_MASK) + +#define GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU1_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU1_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU1_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU1_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU1_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU1_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU1_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU1_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU1_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU1_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU1_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU1_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU1_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU1_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU1_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU1_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU1_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_PSR_SHIFT)) & GPC_PGC_PU1_SR_PSR_MASK) + +#define GPC_PGC_PU1_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU1_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU1_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU1_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU1_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU1_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU1_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU1_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU1_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU1_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU1_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU1_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_AUXSW_SW2_SHIFT)) & GPC_PGC_PU1_AUXSW_SW2_MASK) + +#define GPC_PGC_PU1_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU1_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU1_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU1_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU2_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU2_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU2_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU2_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_PCR_SHIFT)) & GPC_PGC_PU2_CTRL_PCR_MASK) + +#define GPC_PGC_PU2_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU2_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU2_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU2_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU2_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU2_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU2_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU2_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU2_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU2_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU2_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU2_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PUPSCR_SW_SHIFT)) & GPC_PGC_PU2_PUPSCR_SW_MASK) + +#define GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU2_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU2_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU2_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU2_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU2_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU2_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU2_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU2_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU2_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU2_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU2_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU2_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU2_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU2_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU2_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU2_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU2_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_PSR_SHIFT)) & GPC_PGC_PU2_SR_PSR_MASK) + +#define GPC_PGC_PU2_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU2_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU2_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU2_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU2_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU2_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU2_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU2_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU2_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU2_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU2_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU2_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_AUXSW_SW2_SHIFT)) & GPC_PGC_PU2_AUXSW_SW2_MASK) + +#define GPC_PGC_PU2_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU2_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU2_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU2_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU3_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU3_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU3_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU3_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_PCR_SHIFT)) & GPC_PGC_PU3_CTRL_PCR_MASK) + +#define GPC_PGC_PU3_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU3_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU3_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU3_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU3_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU3_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU3_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU3_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU3_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU3_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU3_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU3_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PUPSCR_SW_SHIFT)) & GPC_PGC_PU3_PUPSCR_SW_MASK) + +#define GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU3_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU3_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU3_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU3_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU3_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU3_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU3_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU3_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU3_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU3_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU3_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU3_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU3_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU3_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU3_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU3_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU3_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_PSR_SHIFT)) & GPC_PGC_PU3_SR_PSR_MASK) + +#define GPC_PGC_PU3_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU3_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU3_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU3_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU3_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU3_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU3_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU3_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU3_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU3_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU3_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU3_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_AUXSW_SW2_SHIFT)) & GPC_PGC_PU3_AUXSW_SW2_MASK) + +#define GPC_PGC_PU3_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU3_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU3_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU3_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU4_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU4_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU4_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU4_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_PCR_SHIFT)) & GPC_PGC_PU4_CTRL_PCR_MASK) + +#define GPC_PGC_PU4_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU4_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU4_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU4_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU4_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU4_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU4_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU4_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU4_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU4_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU4_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU4_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PUPSCR_SW_SHIFT)) & GPC_PGC_PU4_PUPSCR_SW_MASK) + +#define GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU4_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU4_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU4_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU4_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU4_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU4_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU4_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU4_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU4_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU4_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU4_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU4_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU4_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU4_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU4_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU4_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU4_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_PSR_SHIFT)) & GPC_PGC_PU4_SR_PSR_MASK) + +#define GPC_PGC_PU4_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU4_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU4_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU4_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU4_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU4_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU4_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU4_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU4_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU4_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU4_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU4_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_AUXSW_SW2_SHIFT)) & GPC_PGC_PU4_AUXSW_SW2_MASK) + +#define GPC_PGC_PU4_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU4_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU4_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU4_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU5_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU5_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU5_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU5_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_PCR_SHIFT)) & GPC_PGC_PU5_CTRL_PCR_MASK) + +#define GPC_PGC_PU5_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU5_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU5_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU5_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU5_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU5_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU5_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU5_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU5_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU5_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU5_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU5_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PUPSCR_SW_SHIFT)) & GPC_PGC_PU5_PUPSCR_SW_MASK) + +#define GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU5_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU5_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU5_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU5_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU5_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU5_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU5_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU5_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU5_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU5_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU5_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU5_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU5_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU5_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU5_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU5_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU5_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_PSR_SHIFT)) & GPC_PGC_PU5_SR_PSR_MASK) + +#define GPC_PGC_PU5_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU5_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU5_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU5_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU5_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU5_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU5_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU5_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU5_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU5_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU5_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU5_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_AUXSW_SW2_SHIFT)) & GPC_PGC_PU5_AUXSW_SW2_MASK) + +#define GPC_PGC_PU5_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU5_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU5_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU5_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU6_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU6_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU6_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU6_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_PCR_SHIFT)) & GPC_PGC_PU6_CTRL_PCR_MASK) + +#define GPC_PGC_PU6_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU6_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU6_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU6_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU6_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU6_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU6_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU6_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU6_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU6_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU6_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU6_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PUPSCR_SW_SHIFT)) & GPC_PGC_PU6_PUPSCR_SW_MASK) + +#define GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU6_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU6_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU6_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU6_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU6_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU6_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU6_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU6_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU6_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU6_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU6_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU6_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU6_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU6_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU6_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU6_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU6_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_PSR_SHIFT)) & GPC_PGC_PU6_SR_PSR_MASK) + +#define GPC_PGC_PU6_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU6_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU6_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU6_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU6_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU6_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU6_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU6_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU6_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU6_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU6_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU6_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_AUXSW_SW2_SHIFT)) & GPC_PGC_PU6_AUXSW_SW2_MASK) + +#define GPC_PGC_PU6_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU6_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU6_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU6_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU7_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU7_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU7_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU7_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_PCR_SHIFT)) & GPC_PGC_PU7_CTRL_PCR_MASK) + +#define GPC_PGC_PU7_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU7_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU7_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU7_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU7_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU7_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU7_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU7_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU7_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU7_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU7_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU7_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PUPSCR_SW_SHIFT)) & GPC_PGC_PU7_PUPSCR_SW_MASK) + +#define GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU7_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU7_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU7_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU7_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU7_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU7_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU7_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU7_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU7_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU7_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU7_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU7_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU7_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU7_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU7_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU7_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU7_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_PSR_SHIFT)) & GPC_PGC_PU7_SR_PSR_MASK) + +#define GPC_PGC_PU7_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU7_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU7_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU7_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU7_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU7_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU7_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU7_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU7_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU7_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU7_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU7_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_AUXSW_SW2_SHIFT)) & GPC_PGC_PU7_AUXSW_SW2_MASK) + +#define GPC_PGC_PU7_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU7_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU7_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU7_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU8_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU8_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU8_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU8_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_PCR_SHIFT)) & GPC_PGC_PU8_CTRL_PCR_MASK) + +#define GPC_PGC_PU8_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU8_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU8_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU8_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU8_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU8_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU8_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU8_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU8_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU8_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU8_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU8_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PUPSCR_SW_SHIFT)) & GPC_PGC_PU8_PUPSCR_SW_MASK) + +#define GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU8_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU8_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU8_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU8_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU8_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU8_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU8_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU8_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU8_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU8_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU8_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU8_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU8_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU8_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU8_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU8_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU8_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_PSR_SHIFT)) & GPC_PGC_PU8_SR_PSR_MASK) + +#define GPC_PGC_PU8_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU8_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU8_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU8_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU8_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU8_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU8_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU8_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU8_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU8_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU8_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU8_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_AUXSW_SW2_SHIFT)) & GPC_PGC_PU8_AUXSW_SW2_MASK) + +#define GPC_PGC_PU8_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU8_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU8_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU8_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU9_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU9_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU9_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU9_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_PCR_SHIFT)) & GPC_PGC_PU9_CTRL_PCR_MASK) + +#define GPC_PGC_PU9_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU9_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU9_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU9_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU9_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU9_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU9_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU9_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU9_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU9_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU9_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU9_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PUPSCR_SW_SHIFT)) & GPC_PGC_PU9_PUPSCR_SW_MASK) + +#define GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU9_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU9_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU9_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU9_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU9_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU9_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU9_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU9_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU9_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU9_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU9_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU9_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU9_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU9_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU9_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU9_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU9_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_PSR_SHIFT)) & GPC_PGC_PU9_SR_PSR_MASK) + +#define GPC_PGC_PU9_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU9_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU9_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU9_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU9_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU9_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU9_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU9_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU9_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU9_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU9_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU9_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_AUXSW_SW2_SHIFT)) & GPC_PGC_PU9_AUXSW_SW2_MASK) + +#define GPC_PGC_PU9_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU9_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU9_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU9_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU10_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU10_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU10_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU10_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_PCR_SHIFT)) & GPC_PGC_PU10_CTRL_PCR_MASK) + +#define GPC_PGC_PU10_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU10_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU10_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU10_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU10_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU10_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU10_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU10_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU10_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU10_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU10_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU10_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PUPSCR_SW_SHIFT)) & GPC_PGC_PU10_PUPSCR_SW_MASK) + +#define GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU10_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU10_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU10_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU10_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU10_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU10_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU10_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU10_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU10_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU10_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU10_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU10_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU10_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU10_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU10_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU10_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU10_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_PSR_SHIFT)) & GPC_PGC_PU10_SR_PSR_MASK) + +#define GPC_PGC_PU10_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU10_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU10_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU10_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU10_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU10_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU10_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU10_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU10_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU10_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU10_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU10_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_AUXSW_SW2_SHIFT)) & GPC_PGC_PU10_AUXSW_SW2_MASK) + +#define GPC_PGC_PU10_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU10_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU10_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU10_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU11_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU11_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU11_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU11_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_PCR_SHIFT)) & GPC_PGC_PU11_CTRL_PCR_MASK) + +#define GPC_PGC_PU11_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU11_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU11_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU11_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU11_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU11_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU11_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU11_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU11_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU11_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU11_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU11_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PUPSCR_SW_SHIFT)) & GPC_PGC_PU11_PUPSCR_SW_MASK) + +#define GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU11_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU11_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU11_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU11_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU11_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU11_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU11_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU11_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU11_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU11_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU11_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU11_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU11_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU11_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU11_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU11_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU11_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_PSR_SHIFT)) & GPC_PGC_PU11_SR_PSR_MASK) + +#define GPC_PGC_PU11_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU11_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU11_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU11_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU11_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU11_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU11_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU11_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU11_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU11_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU11_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU11_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_AUXSW_SW2_SHIFT)) & GPC_PGC_PU11_AUXSW_SW2_MASK) + +#define GPC_PGC_PU11_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU11_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU11_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU11_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU12_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU12_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU12_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU12_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_PCR_SHIFT)) & GPC_PGC_PU12_CTRL_PCR_MASK) + +#define GPC_PGC_PU12_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU12_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU12_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU12_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU12_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU12_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU12_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU12_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU12_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU12_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU12_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU12_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PUPSCR_SW_SHIFT)) & GPC_PGC_PU12_PUPSCR_SW_MASK) + +#define GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU12_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU12_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU12_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU12_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU12_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU12_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU12_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU12_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU12_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU12_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU12_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU12_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU12_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU12_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU12_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU12_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU12_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_PSR_SHIFT)) & GPC_PGC_PU12_SR_PSR_MASK) + +#define GPC_PGC_PU12_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU12_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU12_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU12_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU12_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU12_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU12_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU12_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU12_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU12_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU12_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU12_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_AUXSW_SW2_SHIFT)) & GPC_PGC_PU12_AUXSW_SW2_MASK) + +#define GPC_PGC_PU12_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU12_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU12_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU12_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + +/*! @name PU13_CTRL - GPC PGC Control Register */ +/*! @{ */ + +#define GPC_PGC_PU13_CTRL_PCR_MASK (0x1U) +#define GPC_PGC_PU13_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define GPC_PGC_PU13_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_PCR_SHIFT)) & GPC_PGC_PU13_CTRL_PCR_MASK) + +#define GPC_PGC_PU13_CTRL_L2RSTDIS_MASK (0x7EU) +#define GPC_PGC_PU13_CTRL_L2RSTDIS_SHIFT (1U) +#define GPC_PGC_PU13_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU13_CTRL_L2RSTDIS_MASK) + +#define GPC_PGC_PU13_CTRL_DFTRAM_TCD1_MASK (0x3F00U) +#define GPC_PGC_PU13_CTRL_DFTRAM_TCD1_SHIFT (8U) +#define GPC_PGC_PU13_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU13_CTRL_DFTRAM_TCD1_MASK) + +#define GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) +#define GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) +#define GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR_MASK) + +#define GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) +#define GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) +#define GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/*! @} */ + +/*! @name PU13_PUPSCR - GPC PGC Up Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU13_PUPSCR_SW_MASK (0x3FU) +#define GPC_PGC_PU13_PUPSCR_SW_SHIFT (0U) +#define GPC_PGC_PU13_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PUPSCR_SW_SHIFT)) & GPC_PGC_PU13_PUPSCR_SW_MASK) + +#define GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) +#define GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) +#define GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU13_PUPSCR_SW2ISO_MASK (0x7FFF80U) +#define GPC_PGC_PU13_PUPSCR_SW2ISO_SHIFT (7U) +#define GPC_PGC_PU13_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU13_PUPSCR_SW2ISO_MASK) + +#define GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) +#define GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) +#define GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) +/*! @} */ + +/*! @name PU13_PDNSCR - GPC PGC Down Sequence Control Register */ +/*! @{ */ + +#define GPC_PGC_PU13_PDNSCR_ISO_MASK (0x3FU) +#define GPC_PGC_PU13_PDNSCR_ISO_SHIFT (0U) +#define GPC_PGC_PU13_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU13_PDNSCR_ISO_MASK) + +#define GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) +#define GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) +/*! PDN_WAIT_SCALL_OUT - Default 1'b0 + */ +#define GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) + +#define GPC_PGC_PU13_PDNSCR_ISO2SW_MASK (0x3F00U) +#define GPC_PGC_PU13_PDNSCR_ISO2SW_SHIFT (8U) +#define GPC_PGC_PU13_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU13_PDNSCR_ISO2SW_MASK) + +#define GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) +#define GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) +#define GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) + +#define GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) +#define GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) +#define GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/*! @} */ + +/*! @name PU13_SR - GPC PGC Status Register */ +/*! @{ */ + +#define GPC_PGC_PU13_SR_PSR_MASK (0x1U) +#define GPC_PGC_PU13_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define GPC_PGC_PU13_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_PSR_SHIFT)) & GPC_PGC_PU13_SR_PSR_MASK) + +#define GPC_PGC_PU13_SR_L2RETN_FLAG_MASK (0x2U) +#define GPC_PGC_PU13_SR_L2RETN_FLAG_SHIFT (1U) +/*! L2RETN_FLAG + * 0b0..A53 is not wakeup from L2 retention mode. + * 0b1..A53 is wakeup from L2 retention mode. + */ +#define GPC_PGC_PU13_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU13_SR_L2RETN_FLAG_MASK) + +#define GPC_PGC_PU13_SR_ALLOFF_FLAG_MASK (0x4U) +#define GPC_PGC_PU13_SR_ALLOFF_FLAG_SHIFT (2U) +/*! ALLOFF_FLAG + * 0b0..A53 is not wakeup from ALL_OFF mode. + * 0b1..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU13_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU13_SR_ALLOFF_FLAG_MASK) + +#define GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL_MASK (0x78U) +#define GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL_SHIFT (3U) +/*! PUP_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL_MASK) + +#define GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) +#define GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) +#define GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/*! @} */ + +/*! @name PU13_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ +/*! @{ */ + +#define GPC_PGC_PU13_AUXSW_SW2_MASK (0x3FU) +#define GPC_PGC_PU13_AUXSW_SW2_SHIFT (0U) +#define GPC_PGC_PU13_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_AUXSW_SW2_SHIFT)) & GPC_PGC_PU13_AUXSW_SW2_MASK) + +#define GPC_PGC_PU13_AUXSW_ISO2SW2_MASK (0x3F00U) +#define GPC_PGC_PU13_AUXSW_ISO2SW2_SHIFT (8U) +/*! ISO2SW2 + * 0b000000..A53 is not wakeup from ALL_OFF mode. + * 0b000001..A53 is wakeup from ALL_OFF mode. + */ +#define GPC_PGC_PU13_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU13_AUXSW_ISO2SW2_MASK) + +#define GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) +#define GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) +/*! PDN_CLK_DIV_SEL + * 0b0000..1 + * 0b0001..1/2 count_clk + * 0b0010..1/4 count_clk + * 0b0011..1/8 count_clk + * 0b0100..1/16 count_clk + * 0b0101..1/32 count_clk + * 0b0110..1/64 count_clk + * 0b0111..1/128 count_clk + * 0b1000..1/256 count_clk + * 0b1001..1/512 count_clk + * 0b1010..1/1024 count_clk + * 0b1011..1/2056 count_clk + * 0b1100..1/4096 count_clk + * 0b1101..1/8192 count_clk + * 0b1110..1/16384 count_clk + * 0b1111..1/32768 count_clk + */ +#define GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPC_PGC_Register_Masks */ + + +/* GPC_PGC - Peripheral instance base addresses */ +/** Peripheral GPC_PGC base address */ +#define GPC_PGC_BASE (0x303A0800u) +/** Peripheral GPC_PGC base pointer */ +#define GPC_PGC ((GPC_PGC_Type *)GPC_PGC_BASE) +/** Array initializer of GPC_PGC peripheral base addresses */ +#define GPC_PGC_BASE_ADDRS { GPC_PGC_BASE } +/** Array initializer of GPC_PGC peripheral base pointers */ +#define GPC_PGC_BASE_PTRS { GPC_PGC } + +/*! + * @} + */ /* end of group GPC_PGC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ + __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ + __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ + __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ + __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ + __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ + __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ + __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name DR - GPIO data register */ +/*! @{ */ + +#define GPIO_DR_DR_MASK (0xFFFFFFFFU) +#define GPIO_DR_DR_SHIFT (0U) +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) +/*! @} */ + +/*! @name GDIR - GPIO direction register */ +/*! @{ */ + +#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) +#define GPIO_GDIR_GDIR_SHIFT (0U) +/*! GDIR + * 0b00000000000000000000000000000000..GPIO is configured as input. + * 0b00000000000000000000000000000001..GPIO is configured as output. + */ +#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) +/*! @} */ + +/*! @name PSR - GPIO pad status register */ +/*! @{ */ + +#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) +#define GPIO_PSR_PSR_SHIFT (0U) +#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) +/*! @} */ + +/*! @name ICR1 - GPIO interrupt configuration register1 */ +/*! @{ */ + +#define GPIO_ICR1_ICR0_MASK (0x3U) +#define GPIO_ICR1_ICR0_SHIFT (0U) +/*! ICR0 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) + +#define GPIO_ICR1_ICR1_MASK (0xCU) +#define GPIO_ICR1_ICR1_SHIFT (2U) +/*! ICR1 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) + +#define GPIO_ICR1_ICR2_MASK (0x30U) +#define GPIO_ICR1_ICR2_SHIFT (4U) +/*! ICR2 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) + +#define GPIO_ICR1_ICR3_MASK (0xC0U) +#define GPIO_ICR1_ICR3_SHIFT (6U) +/*! ICR3 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) + +#define GPIO_ICR1_ICR4_MASK (0x300U) +#define GPIO_ICR1_ICR4_SHIFT (8U) +/*! ICR4 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) + +#define GPIO_ICR1_ICR5_MASK (0xC00U) +#define GPIO_ICR1_ICR5_SHIFT (10U) +/*! ICR5 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) + +#define GPIO_ICR1_ICR6_MASK (0x3000U) +#define GPIO_ICR1_ICR6_SHIFT (12U) +/*! ICR6 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) + +#define GPIO_ICR1_ICR7_MASK (0xC000U) +#define GPIO_ICR1_ICR7_SHIFT (14U) +/*! ICR7 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) + +#define GPIO_ICR1_ICR8_MASK (0x30000U) +#define GPIO_ICR1_ICR8_SHIFT (16U) +/*! ICR8 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) + +#define GPIO_ICR1_ICR9_MASK (0xC0000U) +#define GPIO_ICR1_ICR9_SHIFT (18U) +/*! ICR9 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) + +#define GPIO_ICR1_ICR10_MASK (0x300000U) +#define GPIO_ICR1_ICR10_SHIFT (20U) +/*! ICR10 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) + +#define GPIO_ICR1_ICR11_MASK (0xC00000U) +#define GPIO_ICR1_ICR11_SHIFT (22U) +/*! ICR11 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) + +#define GPIO_ICR1_ICR12_MASK (0x3000000U) +#define GPIO_ICR1_ICR12_SHIFT (24U) +/*! ICR12 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) + +#define GPIO_ICR1_ICR13_MASK (0xC000000U) +#define GPIO_ICR1_ICR13_SHIFT (26U) +/*! ICR13 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) + +#define GPIO_ICR1_ICR14_MASK (0x30000000U) +#define GPIO_ICR1_ICR14_SHIFT (28U) +/*! ICR14 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) + +#define GPIO_ICR1_ICR15_MASK (0xC0000000U) +#define GPIO_ICR1_ICR15_SHIFT (30U) +/*! ICR15 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) +/*! @} */ + +/*! @name ICR2 - GPIO interrupt configuration register2 */ +/*! @{ */ + +#define GPIO_ICR2_ICR16_MASK (0x3U) +#define GPIO_ICR2_ICR16_SHIFT (0U) +/*! ICR16 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) + +#define GPIO_ICR2_ICR17_MASK (0xCU) +#define GPIO_ICR2_ICR17_SHIFT (2U) +/*! ICR17 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) + +#define GPIO_ICR2_ICR18_MASK (0x30U) +#define GPIO_ICR2_ICR18_SHIFT (4U) +/*! ICR18 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) + +#define GPIO_ICR2_ICR19_MASK (0xC0U) +#define GPIO_ICR2_ICR19_SHIFT (6U) +/*! ICR19 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) + +#define GPIO_ICR2_ICR20_MASK (0x300U) +#define GPIO_ICR2_ICR20_SHIFT (8U) +/*! ICR20 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) + +#define GPIO_ICR2_ICR21_MASK (0xC00U) +#define GPIO_ICR2_ICR21_SHIFT (10U) +/*! ICR21 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) + +#define GPIO_ICR2_ICR22_MASK (0x3000U) +#define GPIO_ICR2_ICR22_SHIFT (12U) +/*! ICR22 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) + +#define GPIO_ICR2_ICR23_MASK (0xC000U) +#define GPIO_ICR2_ICR23_SHIFT (14U) +/*! ICR23 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) + +#define GPIO_ICR2_ICR24_MASK (0x30000U) +#define GPIO_ICR2_ICR24_SHIFT (16U) +/*! ICR24 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) + +#define GPIO_ICR2_ICR25_MASK (0xC0000U) +#define GPIO_ICR2_ICR25_SHIFT (18U) +/*! ICR25 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) + +#define GPIO_ICR2_ICR26_MASK (0x300000U) +#define GPIO_ICR2_ICR26_SHIFT (20U) +/*! ICR26 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) + +#define GPIO_ICR2_ICR27_MASK (0xC00000U) +#define GPIO_ICR2_ICR27_SHIFT (22U) +/*! ICR27 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) + +#define GPIO_ICR2_ICR28_MASK (0x3000000U) +#define GPIO_ICR2_ICR28_SHIFT (24U) +/*! ICR28 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) + +#define GPIO_ICR2_ICR29_MASK (0xC000000U) +#define GPIO_ICR2_ICR29_SHIFT (26U) +/*! ICR29 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) + +#define GPIO_ICR2_ICR30_MASK (0x30000000U) +#define GPIO_ICR2_ICR30_SHIFT (28U) +/*! ICR30 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) + +#define GPIO_ICR2_ICR31_MASK (0xC0000000U) +#define GPIO_ICR2_ICR31_SHIFT (30U) +/*! ICR31 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) +/*! @} */ + +/*! @name IMR - GPIO interrupt mask register */ +/*! @{ */ + +#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) +#define GPIO_IMR_IMR_SHIFT (0U) +/*! IMR + * 0b00000000000000000000000000000000..Interrupt n is disabled. + * 0b00000000000000000000000000000001..Interrupt n is enabled. + */ +#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) +/*! @} */ + +/*! @name ISR - GPIO interrupt status register */ +/*! @{ */ + +#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) +#define GPIO_ISR_ISR_SHIFT (0U) +#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) +/*! @} */ + +/*! @name EDGE_SEL - GPIO edge select register */ +/*! @{ */ + +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x30200000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x30210000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x30220000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x30230000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Peripheral GPIO5 base address */ +#define GPIO5_BASE (0x30240000u) +/** Peripheral GPIO5 base pointer */ +#define GPIO5 ((GPIO_Type *)GPIO5_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } +#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn } +#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPMI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer + * @{ + */ + +/** GPMI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< GPMI Control Register 0 Description, offset: 0x0 */ + __IO uint32_t CTRL0_SET; /**< GPMI Control Register 0 Description, offset: 0x4 */ + __IO uint32_t CTRL0_CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */ + __IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset: 0xC */ + __IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t ECCCTRL; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */ + __IO uint32_t ECCCTRL_SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */ + __IO uint32_t ECCCTRL_CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */ + __IO uint32_t ECCCTRL_TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */ + __IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */ + uint8_t RESERVED_2[12]; + __IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CTRL1; /**< GPMI Control Register 1 Description, offset: 0x60 */ + __IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset: 0x64 */ + __IO uint32_t CTRL1_CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */ + __IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */ + __IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */ + uint8_t RESERVED_8[12]; + __I uint32_t DEBUGr; /**< GPMI Debug Information Register Description, offset: 0xC0 */ + uint8_t RESERVED_9[12]; + __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */ + uint8_t RESERVED_11[12]; + __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */ + uint8_t RESERVED_12[12]; + __IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */ + uint8_t RESERVED_13[12]; + __IO uint32_t WRITE_DDR_DLL_CTRL; /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */ + uint8_t RESERVED_14[12]; + __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */ + uint8_t RESERVED_15[12]; + __I uint32_t WRITE_DDR_DLL_STS; /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */ +} GPMI_Type; + +/* ---------------------------------------------------------------------------- + -- GPMI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Register_Masks GPMI Register Masks + * @{ + */ + +/*! @name CTRL0 - GPMI Control Register 0 Description */ +/*! @{ */ + +#define GPMI_CTRL0_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK) + +#define GPMI_CTRL0_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT (16U) +/*! ADDRESS_INCREMENT + * 0b0..Address does not increment. + * 0b1..Increment address. + */ +#define GPMI_CTRL0_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK) + +#define GPMI_CTRL0_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK) + +#define GPMI_CTRL0_CS_MASK (0x700000U) +#define GPMI_CTRL0_CS_SHIFT (20U) +#define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK) + +#define GPMI_CTRL0_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_WORD_LENGTH_SHIFT (23U) +/*! WORD_LENGTH + * 0b0..Reserved. + * 0b1..8-bit Data Bus mode. + */ +#define GPMI_CTRL0_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK) + +#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_COMMAND_MODE_SHIFT (24U) +/*! COMMAND_MODE + * 0b00..Write mode. + * 0b01..Read Mode. + * 0b10..Read and Compare Mode (setting sense flop). + * 0b11..Wait for Ready. + */ +#define GPMI_CTRL0_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK) + +#define GPMI_CTRL0_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_UDMA_SHIFT (26U) +/*! UDMA + * 0b0..Use ATA-PIO mode on the external bus. + * 0b1..Use ATA-Ultra DMA mode on the external bus. + */ +#define GPMI_CTRL0_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK) + +#define GPMI_CTRL0_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK) + +#define GPMI_CTRL0_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_DEV_IRQ_EN_MASK) + +#define GPMI_CTRL0_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_RUN_SHIFT (29U) +#define GPMI_CTRL0_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK) + +#define GPMI_CTRL0_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK) + +#define GPMI_CTRL0_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL0_SET - GPMI Control Register 0 Description */ +/*! @{ */ + +#define GPMI_CTRL0_SET_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_SET_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_SET_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_XFER_COUNT_SHIFT)) & GPMI_CTRL0_SET_XFER_COUNT_MASK) + +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT (16U) +/*! ADDRESS_INCREMENT + * 0b0..Address does not increment. + * 0b1..Increment address. + */ +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK) + +#define GPMI_CTRL0_SET_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_SET_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_SET_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_MASK) + +#define GPMI_CTRL0_SET_CS_MASK (0x700000U) +#define GPMI_CTRL0_SET_CS_SHIFT (20U) +#define GPMI_CTRL0_SET_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CS_SHIFT)) & GPMI_CTRL0_SET_CS_MASK) + +#define GPMI_CTRL0_SET_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT (23U) +/*! WORD_LENGTH + * 0b0..Reserved. + * 0b1..8-bit Data Bus mode. + */ +#define GPMI_CTRL0_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_SET_WORD_LENGTH_MASK) + +#define GPMI_CTRL0_SET_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT (24U) +/*! COMMAND_MODE + * 0b00..Write mode. + * 0b01..Read Mode. + * 0b10..Read and Compare Mode (setting sense flop). + * 0b11..Wait for Ready. + */ +#define GPMI_CTRL0_SET_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_SET_COMMAND_MODE_MASK) + +#define GPMI_CTRL0_SET_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_SET_UDMA_SHIFT (26U) +/*! UDMA + * 0b0..Use ATA-PIO mode on the external bus. + * 0b1..Use ATA-Ultra DMA mode on the external bus. + */ +#define GPMI_CTRL0_SET_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_UDMA_SHIFT)) & GPMI_CTRL0_SET_UDMA_MASK) + +#define GPMI_CTRL0_SET_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_SET_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_SET_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_LOCK_CS_SHIFT)) & GPMI_CTRL0_SET_LOCK_CS_MASK) + +#define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_SET_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_SET_DEV_IRQ_EN_MASK) + +#define GPMI_CTRL0_SET_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_SET_RUN_SHIFT (29U) +#define GPMI_CTRL0_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_RUN_SHIFT)) & GPMI_CTRL0_SET_RUN_MASK) + +#define GPMI_CTRL0_SET_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_SET_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CLKGATE_SHIFT)) & GPMI_CTRL0_SET_CLKGATE_MASK) + +#define GPMI_CTRL0_SET_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_SET_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_SFTRST_SHIFT)) & GPMI_CTRL0_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL0_CLR - GPMI Control Register 0 Description */ +/*! @{ */ + +#define GPMI_CTRL0_CLR_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_CLR_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_XFER_COUNT_SHIFT)) & GPMI_CTRL0_CLR_XFER_COUNT_MASK) + +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT (16U) +/*! ADDRESS_INCREMENT + * 0b0..Address does not increment. + * 0b1..Increment address. + */ +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK) + +#define GPMI_CTRL0_CLR_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_CLR_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_CLR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_MASK) + +#define GPMI_CTRL0_CLR_CS_MASK (0x700000U) +#define GPMI_CTRL0_CLR_CS_SHIFT (20U) +#define GPMI_CTRL0_CLR_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CS_SHIFT)) & GPMI_CTRL0_CLR_CS_MASK) + +#define GPMI_CTRL0_CLR_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT (23U) +/*! WORD_LENGTH + * 0b0..Reserved. + * 0b1..8-bit Data Bus mode. + */ +#define GPMI_CTRL0_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_CLR_WORD_LENGTH_MASK) + +#define GPMI_CTRL0_CLR_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT (24U) +/*! COMMAND_MODE + * 0b00..Write mode. + * 0b01..Read Mode. + * 0b10..Read and Compare Mode (setting sense flop). + * 0b11..Wait for Ready. + */ +#define GPMI_CTRL0_CLR_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_CLR_COMMAND_MODE_MASK) + +#define GPMI_CTRL0_CLR_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_CLR_UDMA_SHIFT (26U) +/*! UDMA + * 0b0..Use ATA-PIO mode on the external bus. + * 0b1..Use ATA-Ultra DMA mode on the external bus. + */ +#define GPMI_CTRL0_CLR_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_UDMA_SHIFT)) & GPMI_CTRL0_CLR_UDMA_MASK) + +#define GPMI_CTRL0_CLR_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_CLR_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_CLR_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_LOCK_CS_SHIFT)) & GPMI_CTRL0_CLR_LOCK_CS_MASK) + +#define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK) + +#define GPMI_CTRL0_CLR_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_CLR_RUN_SHIFT (29U) +#define GPMI_CTRL0_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_RUN_SHIFT)) & GPMI_CTRL0_CLR_RUN_MASK) + +#define GPMI_CTRL0_CLR_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_CLR_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CLKGATE_SHIFT)) & GPMI_CTRL0_CLR_CLKGATE_MASK) + +#define GPMI_CTRL0_CLR_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_CLR_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_SFTRST_SHIFT)) & GPMI_CTRL0_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL0_TOG - GPMI Control Register 0 Description */ +/*! @{ */ + +#define GPMI_CTRL0_TOG_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_TOG_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_XFER_COUNT_SHIFT)) & GPMI_CTRL0_TOG_XFER_COUNT_MASK) + +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT (16U) +/*! ADDRESS_INCREMENT + * 0b0..Address does not increment. + * 0b1..Increment address. + */ +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK) + +#define GPMI_CTRL0_TOG_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_TOG_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_TOG_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_MASK) + +#define GPMI_CTRL0_TOG_CS_MASK (0x700000U) +#define GPMI_CTRL0_TOG_CS_SHIFT (20U) +#define GPMI_CTRL0_TOG_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CS_SHIFT)) & GPMI_CTRL0_TOG_CS_MASK) + +#define GPMI_CTRL0_TOG_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT (23U) +/*! WORD_LENGTH + * 0b0..Reserved. + * 0b1..8-bit Data Bus mode. + */ +#define GPMI_CTRL0_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_TOG_WORD_LENGTH_MASK) + +#define GPMI_CTRL0_TOG_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT (24U) +/*! COMMAND_MODE + * 0b00..Write mode. + * 0b01..Read Mode. + * 0b10..Read and Compare Mode (setting sense flop). + * 0b11..Wait for Ready. + */ +#define GPMI_CTRL0_TOG_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_TOG_COMMAND_MODE_MASK) + +#define GPMI_CTRL0_TOG_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_TOG_UDMA_SHIFT (26U) +/*! UDMA + * 0b0..Use ATA-PIO mode on the external bus. + * 0b1..Use ATA-Ultra DMA mode on the external bus. + */ +#define GPMI_CTRL0_TOG_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_UDMA_SHIFT)) & GPMI_CTRL0_TOG_UDMA_MASK) + +#define GPMI_CTRL0_TOG_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_TOG_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_TOG_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_LOCK_CS_SHIFT)) & GPMI_CTRL0_TOG_LOCK_CS_MASK) + +#define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK) + +#define GPMI_CTRL0_TOG_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_TOG_RUN_SHIFT (29U) +#define GPMI_CTRL0_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_RUN_SHIFT)) & GPMI_CTRL0_TOG_RUN_MASK) + +#define GPMI_CTRL0_TOG_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_TOG_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CLKGATE_SHIFT)) & GPMI_CTRL0_TOG_CLKGATE_MASK) + +#define GPMI_CTRL0_TOG_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_TOG_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_SFTRST_SHIFT)) & GPMI_CTRL0_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name COMPARE - GPMI Compare Register Description */ +/*! @{ */ + +#define GPMI_COMPARE_REFERENCE_MASK (0xFFFFU) +#define GPMI_COMPARE_REFERENCE_SHIFT (0U) +#define GPMI_COMPARE_REFERENCE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK) + +#define GPMI_COMPARE_MASK_MASK (0xFFFF0000U) +#define GPMI_COMPARE_MASK_SHIFT (16U) +#define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK) +/*! @} */ + +/*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */ +/*! @{ */ + +#define GPMI_ECCCTRL_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK) + +#define GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK (0x600U) +#define GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT (9U) +/*! RANDOMIZER_TYPE + * 0b00..Type 0 + * 0b01..Type 1 + */ +#define GPMI_ECCCTRL_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK) + +#define GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK (0x800U) +#define GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT (11U) +/*! RANDOMIZER_ENABLE + * 0b0..disable + * 0b1..enable + */ +#define GPMI_ECCCTRL_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK) + +#define GPMI_ECCCTRL_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK) + +#define GPMI_ECCCTRL_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK) + +#define GPMI_ECCCTRL_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK) + +#define GPMI_ECCCTRL_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK) +/*! @} */ + +/*! @name ECCCTRL_SET - GPMI Integrated ECC Control Register Description */ +/*! @{ */ + +#define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_SET_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_SET_BUFFER_MASK_MASK) + +#define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK (0x600U) +#define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT (9U) +/*! RANDOMIZER_TYPE + * 0b00..Type 0 + * 0b01..Type 1 + */ +#define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK) + +#define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK (0x800U) +#define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT (11U) +/*! RANDOMIZER_ENABLE + * 0b0..disable + * 0b1..enable + */ +#define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK) + +#define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_SET_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_SET_ENABLE_ECC_MASK) + +#define GPMI_ECCCTRL_SET_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_SET_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_SET_ECC_CMD_MASK) + +#define GPMI_ECCCTRL_SET_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_SET_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD2_SHIFT)) & GPMI_ECCCTRL_SET_RSVD2_MASK) + +#define GPMI_ECCCTRL_SET_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_SET_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_HANDLE_SHIFT)) & GPMI_ECCCTRL_SET_HANDLE_MASK) +/*! @} */ + +/*! @name ECCCTRL_CLR - GPMI Integrated ECC Control Register Description */ +/*! @{ */ + +#define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_CLR_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK) + +#define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK (0x600U) +#define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT (9U) +/*! RANDOMIZER_TYPE + * 0b00..Type 0 + * 0b01..Type 1 + */ +#define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK) + +#define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK (0x800U) +#define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT (11U) +/*! RANDOMIZER_ENABLE + * 0b0..disable + * 0b1..enable + */ +#define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK) + +#define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK) + +#define GPMI_ECCCTRL_CLR_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_CLR_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_CLR_ECC_CMD_MASK) + +#define GPMI_ECCCTRL_CLR_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_CLR_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD2_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD2_MASK) + +#define GPMI_ECCCTRL_CLR_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_CLR_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_HANDLE_SHIFT)) & GPMI_ECCCTRL_CLR_HANDLE_MASK) +/*! @} */ + +/*! @name ECCCTRL_TOG - GPMI Integrated ECC Control Register Description */ +/*! @{ */ + +#define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_TOG_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK) + +#define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK (0x600U) +#define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT (9U) +/*! RANDOMIZER_TYPE + * 0b00..Type 0 + * 0b01..Type 1 + */ +#define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK) + +#define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK (0x800U) +#define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT (11U) +/*! RANDOMIZER_ENABLE + * 0b0..disable + * 0b1..enable + */ +#define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK) + +#define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK) + +#define GPMI_ECCCTRL_TOG_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_TOG_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_TOG_ECC_CMD_MASK) + +#define GPMI_ECCCTRL_TOG_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_TOG_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD2_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD2_MASK) + +#define GPMI_ECCCTRL_TOG_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_TOG_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_HANDLE_SHIFT)) & GPMI_ECCCTRL_TOG_HANDLE_MASK) +/*! @} */ + +/*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */ +/*! @{ */ + +#define GPMI_ECCCOUNT_COUNT_MASK (0xFFFFU) +#define GPMI_ECCCOUNT_COUNT_SHIFT (0U) +#define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK) + +#define GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK (0xFF0000U) +#define GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT (16U) +#define GPMI_ECCCOUNT_RANDOMIZER_PAGE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT)) & GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK) +/*! @} */ + +/*! @name PAYLOAD - GPMI Payload Address Register Description */ +/*! @{ */ + +#define GPMI_PAYLOAD_RSVD0_MASK (0x3U) +#define GPMI_PAYLOAD_RSVD0_SHIFT (0U) +#define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK) + +#define GPMI_PAYLOAD_ADDRESS_MASK (0xFFFFFFFCU) +#define GPMI_PAYLOAD_ADDRESS_SHIFT (2U) +#define GPMI_PAYLOAD_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK) +/*! @} */ + +/*! @name AUXILIARY - GPMI Auxiliary Address Register Description */ +/*! @{ */ + +#define GPMI_AUXILIARY_RSVD0_MASK (0x3U) +#define GPMI_AUXILIARY_RSVD0_SHIFT (0U) +#define GPMI_AUXILIARY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK) + +#define GPMI_AUXILIARY_ADDRESS_MASK (0xFFFFFFFCU) +#define GPMI_AUXILIARY_ADDRESS_SHIFT (2U) +#define GPMI_AUXILIARY_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK) +/*! @} */ + +/*! @name CTRL1 - GPMI Control Register 1 Description */ +/*! @{ */ + +#define GPMI_CTRL1_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_GPMI_MODE_SHIFT (0U) +/*! GPMI_MODE + * 0b0..NAND mode. + * 0b1..ATA mode. + */ +#define GPMI_CTRL1_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK) + +#define GPMI_CTRL1_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK) + +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT (2U) +/*! ATA_IRQRDY_POLARITY + * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + */ +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK) + +#define GPMI_CTRL1_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_DEV_RESET_SHIFT (3U) +/*! DEV_RESET + * 0b0..NANDF_WP_B pin is held low (asserted). + * 0b1..NANDF_WP_B pin is held high (de-asserted). + */ +#define GPMI_CTRL1_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK) + +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK) + +#define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK) + +#define GPMI_CTRL1_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK) + +#define GPMI_CTRL1_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK) + +#define GPMI_CTRL1_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK) + +#define GPMI_CTRL1_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK) + +#define GPMI_CTRL1_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK) + +#define GPMI_CTRL1_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK) + +#define GPMI_CTRL1_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK) + +#define GPMI_CTRL1_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK) + +#define GPMI_CTRL1_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK) + +#define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK) + +#define GPMI_CTRL1_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_TEST_TRIGGER_SHIFT (21U) +/*! TEST_TRIGGER + * 0b0..Disable + * 0b1..Enable + */ +#define GPMI_CTRL1_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TEST_TRIGGER_MASK) + +#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK) + +#define GPMI_CTRL1_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK) + +#define GPMI_CTRL1_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK) + +#define GPMI_CTRL1_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK) + +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT (27U) +/*! GPMI_CLK_DIV2_EN + * 0b0..internal factor-2 clock divider is disabled + * 0b1..internal factor-2 clock divider is enabled. + */ +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK) + +#define GPMI_CTRL1_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK) + +#define GPMI_CTRL1_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK) + +#define GPMI_CTRL1_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK) + +#define GPMI_CTRL1_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK) +/*! @} */ + +/*! @name CTRL1_SET - GPMI Control Register 1 Description */ +/*! @{ */ + +#define GPMI_CTRL1_SET_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_SET_GPMI_MODE_SHIFT (0U) +/*! GPMI_MODE + * 0b0..NAND mode. + * 0b1..ATA mode. + */ +#define GPMI_CTRL1_SET_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_MODE_SHIFT)) & GPMI_CTRL1_SET_GPMI_MODE_MASK) + +#define GPMI_CTRL1_SET_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_SET_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_SET_CAMERA_MODE_MASK) + +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT (2U) +/*! ATA_IRQRDY_POLARITY + * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + */ +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK) + +#define GPMI_CTRL1_SET_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_SET_DEV_RESET_SHIFT (3U) +/*! DEV_RESET + * 0b0..NANDF_WP_B pin is held low (asserted). + * 0b1..NANDF_WP_B pin is held high (de-asserted). + */ +#define GPMI_CTRL1_SET_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_RESET_SHIFT)) & GPMI_CTRL1_SET_DEV_RESET_MASK) + +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK) + +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK) + +#define GPMI_CTRL1_SET_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_SET_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_SET_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BURST_EN_SHIFT)) & GPMI_CTRL1_SET_BURST_EN_MASK) + +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK) + +#define GPMI_CTRL1_SET_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_SET_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_SET_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_IRQ_SHIFT)) & GPMI_CTRL1_SET_DEV_IRQ_MASK) + +#define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_SET_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_SET_DMA2ECC_MODE_MASK) + +#define GPMI_CTRL1_SET_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_SET_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_SET_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_RDN_DELAY_SHIFT)) & GPMI_CTRL1_SET_RDN_DELAY_MASK) + +#define GPMI_CTRL1_SET_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_SET_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_SET_HALF_PERIOD_MASK) + +#define GPMI_CTRL1_SET_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_SET_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_SET_DLL_ENABLE_MASK) + +#define GPMI_CTRL1_SET_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_SET_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_SET_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BCH_MODE_SHIFT)) & GPMI_CTRL1_SET_BCH_MODE_MASK) + +#define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK) + +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK) + +#define GPMI_CTRL1_SET_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT (21U) +/*! TEST_TRIGGER + * 0b0..Disable + * 0b1..Enable + */ +#define GPMI_CTRL1_SET_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_SET_TEST_TRIGGER_MASK) + +#define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_SET_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_SET_WRN_DLY_SEL_MASK) + +#define GPMI_CTRL1_SET_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_SET_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_SET_DECOUPLE_CS_MASK) + +#define GPMI_CTRL1_SET_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_SET_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_SET_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SET_SSYNCMODE_MASK) + +#define GPMI_CTRL1_SET_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_SET_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_SET_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_UPDATE_CS_SHIFT)) & GPMI_CTRL1_SET_UPDATE_CS_MASK) + +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT (27U) +/*! GPMI_CLK_DIV2_EN + * 0b0..internal factor-2 clock divider is disabled + * 0b1..internal factor-2 clock divider is enabled. + */ +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK) + +#define GPMI_CTRL1_SET_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_SET_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_SET_TOGGLE_MODE_MASK) + +#define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK) + +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK) + +#define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_SET_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_DEV_CLK_STOP_MASK) +/*! @} */ + +/*! @name CTRL1_CLR - GPMI Control Register 1 Description */ +/*! @{ */ + +#define GPMI_CTRL1_CLR_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT (0U) +/*! GPMI_MODE + * 0b0..NAND mode. + * 0b1..ATA mode. + */ +#define GPMI_CTRL1_CLR_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_MODE_SHIFT)) & GPMI_CTRL1_CLR_GPMI_MODE_MASK) + +#define GPMI_CTRL1_CLR_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_CLR_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CLR_CAMERA_MODE_MASK) + +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT (2U) +/*! ATA_IRQRDY_POLARITY + * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + */ +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK) + +#define GPMI_CTRL1_CLR_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_CLR_DEV_RESET_SHIFT (3U) +/*! DEV_RESET + * 0b0..NANDF_WP_B pin is held low (asserted). + * 0b1..NANDF_WP_B pin is held high (de-asserted). + */ +#define GPMI_CTRL1_CLR_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_RESET_SHIFT)) & GPMI_CTRL1_CLR_DEV_RESET_MASK) + +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK) + +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK) + +#define GPMI_CTRL1_CLR_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_CLR_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_CLR_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BURST_EN_SHIFT)) & GPMI_CTRL1_CLR_BURST_EN_MASK) + +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK) + +#define GPMI_CTRL1_CLR_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_CLR_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_IRQ_SHIFT)) & GPMI_CTRL1_CLR_DEV_IRQ_MASK) + +#define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK) + +#define GPMI_CTRL1_CLR_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_CLR_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_RDN_DELAY_SHIFT)) & GPMI_CTRL1_CLR_RDN_DELAY_MASK) + +#define GPMI_CTRL1_CLR_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_CLR_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_CLR_HALF_PERIOD_MASK) + +#define GPMI_CTRL1_CLR_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_CLR_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_CLR_DLL_ENABLE_MASK) + +#define GPMI_CTRL1_CLR_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_CLR_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_CLR_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BCH_MODE_SHIFT)) & GPMI_CTRL1_CLR_BCH_MODE_MASK) + +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK) + +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK) + +#define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT (21U) +/*! TEST_TRIGGER + * 0b0..Disable + * 0b1..Enable + */ +#define GPMI_CTRL1_CLR_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_CLR_TEST_TRIGGER_MASK) + +#define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK) + +#define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_CLR_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_CLR_DECOUPLE_CS_MASK) + +#define GPMI_CTRL1_CLR_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_CLR_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNCMODE_SHIFT)) & GPMI_CTRL1_CLR_SSYNCMODE_MASK) + +#define GPMI_CTRL1_CLR_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_CLR_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_UPDATE_CS_SHIFT)) & GPMI_CTRL1_CLR_UPDATE_CS_MASK) + +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT (27U) +/*! GPMI_CLK_DIV2_EN + * 0b0..internal factor-2 clock divider is disabled + * 0b1..internal factor-2 clock divider is enabled. + */ +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK) + +#define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_CLR_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_CLR_TOGGLE_MODE_MASK) + +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK) + +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK) + +#define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK) +/*! @} */ + +/*! @name CTRL1_TOG - GPMI Control Register 1 Description */ +/*! @{ */ + +#define GPMI_CTRL1_TOG_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT (0U) +/*! GPMI_MODE + * 0b0..NAND mode. + * 0b1..ATA mode. + */ +#define GPMI_CTRL1_TOG_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_MODE_SHIFT)) & GPMI_CTRL1_TOG_GPMI_MODE_MASK) + +#define GPMI_CTRL1_TOG_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_TOG_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_TOG_CAMERA_MODE_MASK) + +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT (2U) +/*! ATA_IRQRDY_POLARITY + * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + */ +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK) + +#define GPMI_CTRL1_TOG_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_TOG_DEV_RESET_SHIFT (3U) +/*! DEV_RESET + * 0b0..NANDF_WP_B pin is held low (asserted). + * 0b1..NANDF_WP_B pin is held high (de-asserted). + */ +#define GPMI_CTRL1_TOG_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_RESET_SHIFT)) & GPMI_CTRL1_TOG_DEV_RESET_MASK) + +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK) + +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK) + +#define GPMI_CTRL1_TOG_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_TOG_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_TOG_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BURST_EN_SHIFT)) & GPMI_CTRL1_TOG_BURST_EN_MASK) + +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK) + +#define GPMI_CTRL1_TOG_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_TOG_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_IRQ_SHIFT)) & GPMI_CTRL1_TOG_DEV_IRQ_MASK) + +#define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK) + +#define GPMI_CTRL1_TOG_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_TOG_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_RDN_DELAY_SHIFT)) & GPMI_CTRL1_TOG_RDN_DELAY_MASK) + +#define GPMI_CTRL1_TOG_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_TOG_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_TOG_HALF_PERIOD_MASK) + +#define GPMI_CTRL1_TOG_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_TOG_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_TOG_DLL_ENABLE_MASK) + +#define GPMI_CTRL1_TOG_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_TOG_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_TOG_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BCH_MODE_SHIFT)) & GPMI_CTRL1_TOG_BCH_MODE_MASK) + +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK) + +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK) + +#define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT (21U) +/*! TEST_TRIGGER + * 0b0..Disable + * 0b1..Enable + */ +#define GPMI_CTRL1_TOG_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TOG_TEST_TRIGGER_MASK) + +#define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK) + +#define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_TOG_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_TOG_DECOUPLE_CS_MASK) + +#define GPMI_CTRL1_TOG_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_TOG_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNCMODE_SHIFT)) & GPMI_CTRL1_TOG_SSYNCMODE_MASK) + +#define GPMI_CTRL1_TOG_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_TOG_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_UPDATE_CS_SHIFT)) & GPMI_CTRL1_TOG_UPDATE_CS_MASK) + +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT (27U) +/*! GPMI_CLK_DIV2_EN + * 0b0..internal factor-2 clock divider is disabled + * 0b1..internal factor-2 clock divider is enabled. + */ +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK) + +#define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_TOG_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOG_TOGGLE_MODE_MASK) + +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK) + +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK) + +#define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK) +/*! @} */ + +/*! @name TIMING0 - GPMI Timing Register 0 Description */ +/*! @{ */ + +#define GPMI_TIMING0_DATA_SETUP_MASK (0xFFU) +#define GPMI_TIMING0_DATA_SETUP_SHIFT (0U) +#define GPMI_TIMING0_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK) + +#define GPMI_TIMING0_DATA_HOLD_MASK (0xFF00U) +#define GPMI_TIMING0_DATA_HOLD_SHIFT (8U) +#define GPMI_TIMING0_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK) + +#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xFF0000U) +#define GPMI_TIMING0_ADDRESS_SETUP_SHIFT (16U) +#define GPMI_TIMING0_ADDRESS_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK) + +#define GPMI_TIMING0_RSVD1_MASK (0xFF000000U) +#define GPMI_TIMING0_RSVD1_SHIFT (24U) +#define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK) +/*! @} */ + +/*! @name TIMING1 - GPMI Timing Register 1 Description */ +/*! @{ */ + +#define GPMI_TIMING1_RSVD1_MASK (0xFFFFU) +#define GPMI_TIMING1_RSVD1_SHIFT (0U) +#define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK) + +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xFFFF0000U) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT (16U) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK) +/*! @} */ + +/*! @name TIMING2 - GPMI Timing Register 2 Description */ +/*! @{ */ + +#define GPMI_TIMING2_DATA_PAUSE_MASK (0xFU) +#define GPMI_TIMING2_DATA_PAUSE_SHIFT (0U) +#define GPMI_TIMING2_DATA_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK) + +#define GPMI_TIMING2_CMDADD_PAUSE_MASK (0xF0U) +#define GPMI_TIMING2_CMDADD_PAUSE_SHIFT (4U) +#define GPMI_TIMING2_CMDADD_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK) + +#define GPMI_TIMING2_POSTAMBLE_DELAY_MASK (0xF00U) +#define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT (8U) +#define GPMI_TIMING2_POSTAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK) + +#define GPMI_TIMING2_PREAMBLE_DELAY_MASK (0xF000U) +#define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT (12U) +#define GPMI_TIMING2_PREAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK) + +#define GPMI_TIMING2_CE_DELAY_MASK (0x1F0000U) +#define GPMI_TIMING2_CE_DELAY_SHIFT (16U) +#define GPMI_TIMING2_CE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK) + +#define GPMI_TIMING2_RSVD0_MASK (0xE00000U) +#define GPMI_TIMING2_RSVD0_SHIFT (21U) +#define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK) + +#define GPMI_TIMING2_READ_LATENCY_MASK (0x7000000U) +#define GPMI_TIMING2_READ_LATENCY_SHIFT (24U) +/*! READ_LATENCY + * 0b000..READ LATENCY is 0 + * 0b001..READ LATENCY is 1 + * 0b010..READ LATENCY is 2 + * 0b011..READ LATENCY is 3 + * 0b100..READ LATENCY is 4 + * 0b101..READ LATENCY is 5 + */ +#define GPMI_TIMING2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK) + +#define GPMI_TIMING2_TCR_MASK (0x18000000U) +#define GPMI_TIMING2_TCR_SHIFT (27U) +#define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK) + +#define GPMI_TIMING2_TRPSTH_MASK (0xE0000000U) +#define GPMI_TIMING2_TRPSTH_SHIFT (29U) +#define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK) +/*! @} */ + +/*! @name DATA - GPMI DMA Data Transfer Register Description */ +/*! @{ */ + +#define GPMI_DATA_DATA_MASK (0xFFFFFFFFU) +#define GPMI_DATA_DATA_SHIFT (0U) +#define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK) +/*! @} */ + +/*! @name STAT - GPMI Status Register Description */ +/*! @{ */ + +#define GPMI_STAT_PRESENT_MASK (0x1U) +#define GPMI_STAT_PRESENT_SHIFT (0U) +/*! PRESENT + * 0b0..GPMI is not present in this product. + * 0b1..GPMI is present is in this product. + */ +#define GPMI_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK) + +#define GPMI_STAT_FIFO_FULL_MASK (0x2U) +#define GPMI_STAT_FIFO_FULL_SHIFT (1U) +/*! FIFO_FULL + * 0b0..FIFO is not full. + * 0b1..FIFO is full. + */ +#define GPMI_STAT_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK) + +#define GPMI_STAT_FIFO_EMPTY_MASK (0x4U) +#define GPMI_STAT_FIFO_EMPTY_SHIFT (2U) +/*! FIFO_EMPTY + * 0b0..FIFO is not empty. + * 0b1..FIFO is empty. + */ +#define GPMI_STAT_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK) + +#define GPMI_STAT_INVALID_BUFFER_MASK_MASK (0x8U) +#define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT (3U) +/*! INVALID_BUFFER_MASK + * 0b0..ECC Buffer Mask is not invalid. + * 0b1..ECC Buffer Mask is invalid. + */ +#define GPMI_STAT_INVALID_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK) + +#define GPMI_STAT_ATA_IRQ_MASK (0x10U) +#define GPMI_STAT_ATA_IRQ_SHIFT (4U) +#define GPMI_STAT_ATA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK) + +#define GPMI_STAT_RSVD1_MASK (0xE0U) +#define GPMI_STAT_RSVD1_SHIFT (5U) +#define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK) + +#define GPMI_STAT_DEV0_ERROR_MASK (0x100U) +#define GPMI_STAT_DEV0_ERROR_SHIFT (8U) +/*! DEV0_ERROR + * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 0. + * 0b1..An Error has occurred on ATA/NAND Device accessed by + */ +#define GPMI_STAT_DEV0_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK) + +#define GPMI_STAT_DEV1_ERROR_MASK (0x200U) +#define GPMI_STAT_DEV1_ERROR_SHIFT (9U) +/*! DEV1_ERROR + * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 1. + * 0b1..An Error has occurred on ATA/NAND Device accessed by + */ +#define GPMI_STAT_DEV1_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK) + +#define GPMI_STAT_DEV2_ERROR_MASK (0x400U) +#define GPMI_STAT_DEV2_ERROR_SHIFT (10U) +/*! DEV2_ERROR + * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 2. + * 0b1..An Error has occurred on ATA/NAND Device accessed by + */ +#define GPMI_STAT_DEV2_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK) + +#define GPMI_STAT_DEV3_ERROR_MASK (0x800U) +#define GPMI_STAT_DEV3_ERROR_SHIFT (11U) +/*! DEV3_ERROR + * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 3. + * 0b1..An Error has occurred on ATA/NAND Device accessed by + */ +#define GPMI_STAT_DEV3_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK) + +#define GPMI_STAT_DEV4_ERROR_MASK (0x1000U) +#define GPMI_STAT_DEV4_ERROR_SHIFT (12U) +/*! DEV4_ERROR + * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 4. + * 0b1..An Error has occurred on ATA/NAND Device accessed by + */ +#define GPMI_STAT_DEV4_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK) + +#define GPMI_STAT_DEV5_ERROR_MASK (0x2000U) +#define GPMI_STAT_DEV5_ERROR_SHIFT (13U) +/*! DEV5_ERROR + * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 5. + * 0b1..An Error has occurred on ATA/NAND Device accessed by + */ +#define GPMI_STAT_DEV5_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK) + +#define GPMI_STAT_DEV6_ERROR_MASK (0x4000U) +#define GPMI_STAT_DEV6_ERROR_SHIFT (14U) +/*! DEV6_ERROR + * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 6. + * 0b1..An Error has occurred on ATA/NAND Device accessed by + */ +#define GPMI_STAT_DEV6_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK) + +#define GPMI_STAT_DEV7_ERROR_MASK (0x8000U) +#define GPMI_STAT_DEV7_ERROR_SHIFT (15U) +/*! DEV7_ERROR + * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 7. + * 0b1..An Error has occurred on ATA/NAND Device accessed by + */ +#define GPMI_STAT_DEV7_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK) + +#define GPMI_STAT_RDY_TIMEOUT_MASK (0xFF0000U) +#define GPMI_STAT_RDY_TIMEOUT_SHIFT (16U) +#define GPMI_STAT_RDY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK) + +#define GPMI_STAT_READY_BUSY_MASK (0xFF000000U) +#define GPMI_STAT_READY_BUSY_SHIFT (24U) +#define GPMI_STAT_READY_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK) +/*! @} */ + +/*! @name DEBUG - GPMI Debug Information Register Description */ +/*! @{ */ + +#define GPMI_DEBUG_CMD_END_MASK (0xFFU) +#define GPMI_DEBUG_CMD_END_SHIFT (0U) +#define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK) + +#define GPMI_DEBUG_DMAREQ_MASK (0xFF00U) +#define GPMI_DEBUG_DMAREQ_SHIFT (8U) +#define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK) + +#define GPMI_DEBUG_DMA_SENSE_MASK (0xFF0000U) +#define GPMI_DEBUG_DMA_SENSE_SHIFT (16U) +#define GPMI_DEBUG_DMA_SENSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK) + +#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xFF000000U) +#define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT (24U) +#define GPMI_DEBUG_WAIT_FOR_READY_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK) +/*! @} */ + +/*! @name VERSION - GPMI Version Register Description */ +/*! @{ */ + +#define GPMI_VERSION_STEP_MASK (0xFFFFU) +#define GPMI_VERSION_STEP_SHIFT (0U) +#define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK) + +#define GPMI_VERSION_MINOR_MASK (0xFF0000U) +#define GPMI_VERSION_MINOR_SHIFT (16U) +#define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK) + +#define GPMI_VERSION_MAJOR_MASK (0xFF000000U) +#define GPMI_VERSION_MAJOR_SHIFT (24U) +#define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name DEBUG2 - GPMI Debug2 Information Register Description */ +/*! @{ */ + +#define GPMI_DEBUG2_RDN_TAP_MASK (0x3FU) +#define GPMI_DEBUG2_RDN_TAP_SHIFT (0U) +#define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK) + +#define GPMI_DEBUG2_UPDATE_WINDOW_MASK (0x40U) +#define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT (6U) +#define GPMI_DEBUG2_UPDATE_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK) + +#define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK (0x80U) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT (7U) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK) + +#define GPMI_DEBUG2_SYND2GPMI_READY_MASK (0x100U) +#define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT (8U) +#define GPMI_DEBUG2_SYND2GPMI_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK) + +#define GPMI_DEBUG2_SYND2GPMI_VALID_MASK (0x200U) +#define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT (9U) +#define GPMI_DEBUG2_SYND2GPMI_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK) + +#define GPMI_DEBUG2_GPMI2SYND_READY_MASK (0x400U) +#define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT (10U) +#define GPMI_DEBUG2_GPMI2SYND_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK) + +#define GPMI_DEBUG2_GPMI2SYND_VALID_MASK (0x800U) +#define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT (11U) +#define GPMI_DEBUG2_GPMI2SYND_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK) + +#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xF000U) +#define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT (12U) +#define GPMI_DEBUG2_SYND2GPMI_BE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK) + +#define GPMI_DEBUG2_MAIN_STATE_MASK (0xF0000U) +#define GPMI_DEBUG2_MAIN_STATE_SHIFT (16U) +#define GPMI_DEBUG2_MAIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK) + +#define GPMI_DEBUG2_PIN_STATE_MASK (0x700000U) +#define GPMI_DEBUG2_PIN_STATE_SHIFT (20U) +#define GPMI_DEBUG2_PIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK) + +#define GPMI_DEBUG2_BUSY_MASK (0x800000U) +#define GPMI_DEBUG2_BUSY_SHIFT (23U) +#define GPMI_DEBUG2_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK) + +#define GPMI_DEBUG2_UDMA_STATE_MASK (0xF000000U) +#define GPMI_DEBUG2_UDMA_STATE_SHIFT (24U) +#define GPMI_DEBUG2_UDMA_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK) + +#define GPMI_DEBUG2_RSVD1_MASK (0xF0000000U) +#define GPMI_DEBUG2_RSVD1_SHIFT (28U) +#define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG3 - GPMI Debug3 Information Register Description */ +/*! @{ */ + +#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK (0xFFFFU) +#define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT (0U) +#define GPMI_DEBUG3_DEV_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK) + +#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xFFFF0000U) +#define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT (16U) +#define GPMI_DEBUG3_APB_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK) +/*! @} */ + +/*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */ +/*! @{ */ + +#define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK (0x1U) +#define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT (0U) +#define GPMI_READ_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK) + +#define GPMI_READ_DDR_DLL_CTRL_RESET_MASK (0x2U) +#define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT (1U) +#define GPMI_READ_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK) + +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) + +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) + +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK) + +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK) + +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) + +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) + +#define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT (18U) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK) + +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) + +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ + +/*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */ +/*! @{ */ + +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK (0x1U) +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT (0U) +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK) + +#define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK (0x2U) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT (1U) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK) + +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) + +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) + +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK) + +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK) + +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) + +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) + +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT (18U) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK) + +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) + +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ + +/*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */ +/*! @{ */ + +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK) + +#define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT (1U) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK) + +#define GPMI_READ_DDR_DLL_STS_RSVD0_MASK (0xFE00U) +#define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT (9U) +#define GPMI_READ_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK) + +#define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT (16U) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK) + +#define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) +#define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT (17U) +#define GPMI_READ_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK) + +#define GPMI_READ_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) +#define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT (25U) +#define GPMI_READ_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK) +/*! @} */ + +/*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */ +/*! @{ */ + +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK) + +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT (1U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK) + +#define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK (0xFE00U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT (9U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK) + +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT (16U) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK) + +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT (17U) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK) + +#define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT (25U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPMI_Register_Masks */ + + +/* GPMI - Peripheral instance base addresses */ +/** Peripheral GPMI base address */ +#define GPMI_BASE (0x33002000u) +/** Peripheral GPMI base pointer */ +#define GPMI ((GPMI_Type *)GPMI_BASE) +/** Array initializer of GPMI peripheral base addresses */ +#define GPMI_BASE_ADDRS { GPMI_BASE } +/** Array initializer of GPMI peripheral base pointers */ +#define GPMI_BASE_PTRS { GPMI } +/** Interrupt vectors for the GPMI peripheral type */ +#define GPMI_IRQS { GPMI_IRQn } + +/*! + * @} + */ /* end of group GPMI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer + * @{ + */ + +/** GPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ + __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ + __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ + __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ + __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ + __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ + __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ +} GPT_Type; + +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/*! @name CR - GPT Control Register */ +/*! @{ */ + +#define GPT_CR_EN_MASK (0x1U) +#define GPT_CR_EN_SHIFT (0U) +/*! EN + * 0b0..GPT is disabled. + * 0b1..GPT is enabled. + */ +#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) + +#define GPT_CR_ENMOD_MASK (0x2U) +#define GPT_CR_ENMOD_SHIFT (1U) +/*! ENMOD + * 0b0..GPT counter will retain its value when it is disabled. + * 0b1..GPT counter value is reset to 0 when it is disabled. + */ +#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) + +#define GPT_CR_DBGEN_MASK (0x4U) +#define GPT_CR_DBGEN_SHIFT (2U) +/*! DBGEN + * 0b0..GPT is disabled in debug mode. + * 0b1..GPT is enabled in debug mode. + */ +#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) + +#define GPT_CR_WAITEN_MASK (0x8U) +#define GPT_CR_WAITEN_SHIFT (3U) +/*! WAITEN + * 0b0..GPT is disabled in wait mode. + * 0b1..GPT is enabled in wait mode. + */ +#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) + +#define GPT_CR_DOZEEN_MASK (0x10U) +#define GPT_CR_DOZEEN_SHIFT (4U) +/*! DOZEEN + * 0b0..GPT is disabled in doze mode. + * 0b1..GPT is enabled in doze mode. + */ +#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) + +#define GPT_CR_STOPEN_MASK (0x20U) +#define GPT_CR_STOPEN_SHIFT (5U) +/*! STOPEN + * 0b0..GPT is disabled in Stop mode. + * 0b1..GPT is enabled in Stop mode. + */ +#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) + +#define GPT_CR_CLKSRC_MASK (0x1C0U) +#define GPT_CR_CLKSRC_SHIFT (6U) +/*! CLKSRC + * 0b000..No clock + * 0b001..Peripheral Clock (ipg_clk) + * 0b010..High Frequency Reference Clock (ipg_clk_highfreq) + * 0b011..External Clock + * 0b100..Low Frequency Reference Clock (ipg_clk_32k) + * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M) + */ +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) + +#define GPT_CR_FRR_MASK (0x200U) +#define GPT_CR_FRR_SHIFT (9U) +/*! FRR + * 0b0..Restart mode + * 0b1..Free-Run mode + */ +#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) + +#define GPT_CR_EN_24M_MASK (0x400U) +#define GPT_CR_EN_24M_SHIFT (10U) +/*! EN_24M + * 0b0..24M clock disabled + * 0b1..24M clock enabled + */ +#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) + +#define GPT_CR_SWR_MASK (0x8000U) +#define GPT_CR_SWR_SHIFT (15U) +/*! SWR + * 0b0..GPT is not in reset state + * 0b1..GPT is in reset state + */ +#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) + +#define GPT_CR_IM1_MASK (0x30000U) +#define GPT_CR_IM1_SHIFT (16U) +#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) + +#define GPT_CR_IM2_MASK (0xC0000U) +#define GPT_CR_IM2_SHIFT (18U) +/*! IM2 + * 0b00..capture disabled + * 0b01..capture on rising edge only + * 0b10..capture on falling edge only + * 0b11..capture on both edges + */ +#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) + +#define GPT_CR_OM1_MASK (0x700000U) +#define GPT_CR_OM1_SHIFT (20U) +#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) + +#define GPT_CR_OM2_MASK (0x3800000U) +#define GPT_CR_OM2_SHIFT (23U) +#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) + +#define GPT_CR_OM3_MASK (0x1C000000U) +#define GPT_CR_OM3_SHIFT (26U) +/*! OM3 + * 0b000..Output disconnected. No response on pin. + * 0b001..Toggle output pin + * 0b010..Clear output pin + * 0b011..Set output pin + * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin. + */ +#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) + +#define GPT_CR_FO1_MASK (0x20000000U) +#define GPT_CR_FO1_SHIFT (29U) +#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) + +#define GPT_CR_FO2_MASK (0x40000000U) +#define GPT_CR_FO2_SHIFT (30U) +#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) + +#define GPT_CR_FO3_MASK (0x80000000U) +#define GPT_CR_FO3_SHIFT (31U) +/*! FO3 + * 0b0..Writing a 0 has no effect. + * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + */ +#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) +/*! @} */ + +/*! @name PR - GPT Prescaler Register */ +/*! @{ */ + +#define GPT_PR_PRESCALER_MASK (0xFFFU) +#define GPT_PR_PRESCALER_SHIFT (0U) +/*! PRESCALER + * 0b000000000000..Divide by 1 + * 0b000000000001..Divide by 2 + * 0b111111111111..Divide by 4096 + */ +#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) + +#define GPT_PR_PRESCALER24M_MASK (0xF000U) +#define GPT_PR_PRESCALER24M_SHIFT (12U) +/*! PRESCALER24M + * 0b0000..Divide by 1 + * 0b0001..Divide by 2 + * 0b1111..Divide by 16 + */ +#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) +/*! @} */ + +/*! @name SR - GPT Status Register */ +/*! @{ */ + +#define GPT_SR_OF1_MASK (0x1U) +#define GPT_SR_OF1_SHIFT (0U) +#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) + +#define GPT_SR_OF2_MASK (0x2U) +#define GPT_SR_OF2_SHIFT (1U) +#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) + +#define GPT_SR_OF3_MASK (0x4U) +#define GPT_SR_OF3_SHIFT (2U) +/*! OF3 + * 0b0..Compare event has not occurred. + * 0b1..Compare event has occurred. + */ +#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) + +#define GPT_SR_IF1_MASK (0x8U) +#define GPT_SR_IF1_SHIFT (3U) +#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) + +#define GPT_SR_IF2_MASK (0x10U) +#define GPT_SR_IF2_SHIFT (4U) +/*! IF2 + * 0b0..Capture event has not occurred. + * 0b1..Capture event has occurred. + */ +#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) + +#define GPT_SR_ROV_MASK (0x20U) +#define GPT_SR_ROV_SHIFT (5U) +/*! ROV + * 0b0..Rollover has not occurred. + * 0b1..Rollover has occurred. + */ +#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) +/*! @} */ + +/*! @name IR - GPT Interrupt Register */ +/*! @{ */ + +#define GPT_IR_OF1IE_MASK (0x1U) +#define GPT_IR_OF1IE_SHIFT (0U) +#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) + +#define GPT_IR_OF2IE_MASK (0x2U) +#define GPT_IR_OF2IE_SHIFT (1U) +#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) + +#define GPT_IR_OF3IE_MASK (0x4U) +#define GPT_IR_OF3IE_SHIFT (2U) +/*! OF3IE + * 0b0..Output Compare Channel n interrupt is disabled. + * 0b1..Output Compare Channel n interrupt is enabled. + */ +#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) + +#define GPT_IR_IF1IE_MASK (0x8U) +#define GPT_IR_IF1IE_SHIFT (3U) +#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) + +#define GPT_IR_IF2IE_MASK (0x10U) +#define GPT_IR_IF2IE_SHIFT (4U) +/*! IF2IE + * 0b0..IF2IE Input Capture n Interrupt Enable is disabled. + * 0b1..IF2IE Input Capture n Interrupt Enable is enabled. + */ +#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) + +#define GPT_IR_ROVIE_MASK (0x20U) +#define GPT_IR_ROVIE_SHIFT (5U) +/*! ROVIE + * 0b0..Rollover interrupt is disabled. + * 0b1..Rollover interrupt enabled. + */ +#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) +/*! @} */ + +/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +/*! @{ */ + +#define GPT_OCR_COMP_MASK (0xFFFFFFFFU) +#define GPT_OCR_COMP_SHIFT (0U) +#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) +/*! @} */ + +/* The count of GPT_OCR */ +#define GPT_OCR_COUNT (3U) + +/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +/*! @{ */ + +#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) +#define GPT_ICR_CAPT_SHIFT (0U) +#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) +/*! @} */ + +/* The count of GPT_ICR */ +#define GPT_ICR_COUNT (2U) + +/*! @name CNT - GPT Counter Register */ +/*! @{ */ + +#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) +#define GPT_CNT_COUNT_SHIFT (0U) +#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPT_Register_Masks */ + + +/* GPT - Peripheral instance base addresses */ +/** Peripheral GPT1 base address */ +#define GPT1_BASE (0x302D0000u) +/** Peripheral GPT1 base pointer */ +#define GPT1 ((GPT_Type *)GPT1_BASE) +/** Peripheral GPT2 base address */ +#define GPT2_BASE (0x302E0000u) +/** Peripheral GPT2 base pointer */ +#define GPT2 ((GPT_Type *)GPT2_BASE) +/** Peripheral GPT3 base address */ +#define GPT3_BASE (0x302F0000u) +/** Peripheral GPT3 base pointer */ +#define GPT3 ((GPT_Type *)GPT3_BASE) +/** Peripheral GPT4 base address */ +#define GPT4_BASE (0x30700000u) +/** Peripheral GPT4 base pointer */ +#define GPT4 ((GPT_Type *)GPT4_BASE) +/** Peripheral GPT5 base address */ +#define GPT5_BASE (0x306F0000u) +/** Peripheral GPT5 base pointer */ +#define GPT5 ((GPT_Type *)GPT5_BASE) +/** Peripheral GPT6 base address */ +#define GPT6_BASE (0x306E0000u) +/** Peripheral GPT6 base pointer */ +#define GPT6 ((GPT_Type *)GPT6_BASE) +/** Array initializer of GPT peripheral base addresses */ +#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE } +/** Array initializer of GPT peripheral base pointers */ +#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 } +/** Interrupt vectors for the GPT peripheral type */ +#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn } + +/*! + * @} + */ /* end of group GPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- HDMI_TX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HDMI_TX_Peripheral_Access_Layer HDMI_TX Peripheral Access Layer + * @{ + */ + +/** HDMI_TX - Register Layout Typedef */ +typedef struct { + __IO uint32_t APB_CTRL; /**< , offset: 0x0 */ + __IO uint32_t XT_INT_CTRL; /**< , offset: 0x4 */ + __I uint32_t MAILBOX_FULL_ADDR; /**< , offset: 0x8 */ + __I uint32_t MAILBOX_EMPTY_ADDR; /**< , offset: 0xC */ + __IO uint32_t MAILBOX0_WR_DATA; /**< , offset: 0x10 */ + __I uint32_t MAILBOX0_RD_DATA; /**< , offset: 0x14 */ + __I uint32_t KEEP_ALIVE; /**< , offset: 0x18 */ + __I uint32_t VER_L; /**< , offset: 0x1C */ + __I uint32_t VER_H; /**< , offset: 0x20 */ + __I uint32_t VER_LIB_L_ADDR; /**< , offset: 0x24 */ + __I uint32_t VER_LIB_H_ADDR; /**< , offset: 0x28 */ + __I uint32_t SW_DEBUG_L; /**< , offset: 0x2C */ + __I uint32_t SW_DEBUG_H; /**< , offset: 0x30 */ + __IO uint32_t MAILBOX_INT_MASK; /**< , offset: 0x34 */ + __I uint32_t MAILBOX_INT_STATUS; /**< , offset: 0x38 */ + __IO uint32_t SW_CLK_L; /**< , offset: 0x3C */ + __IO uint32_t SW_CLK_H; /**< , offset: 0x40 */ + __I uint32_t SW_EVENTS0; /**< , offset: 0x44 */ + __I uint32_t SW_EVENTS1; /**< , offset: 0x48 */ + __I uint32_t SW_EVENTS2; /**< , offset: 0x4C */ + __I uint32_t SW_EVENTS3; /**< , offset: 0x50 */ + uint8_t RESERVED_0[12]; + __IO uint32_t XT_OCD_CTRL; /**< , offset: 0x60 */ + __I uint32_t XT_OCD_CTRL_RO; /**< , offset: 0x64 */ + uint8_t RESERVED_1[4]; + __IO uint32_t APB_INT_MASK; /**< , offset: 0x6C */ + __I uint32_t APB_STATUS_MASK; /**< , offset: 0x70 */ + uint8_t RESERVED_2[196492]; + __IO uint32_t AUDIO_SRC_CNTL; /**< , offset: 0x30000 */ + __IO uint32_t AUDIO_SRC_CNFG; /**< , offset: 0x30004 */ + __IO uint32_t COM_CH_STTS_BITS; /**< , offset: 0x30008 */ + __IO uint32_t STTS_BIT_CH01; /**< , offset: 0x3000C */ + __IO uint32_t STTS_BIT_CH23; /**< , offset: 0x30010 */ + __IO uint32_t STTS_BIT_CH45; /**< , offset: 0x30014 */ + __IO uint32_t STTS_BIT_CH67; /**< , offset: 0x30018 */ + __IO uint32_t STTS_BIT_CH89; /**< , offset: 0x3001C */ + __IO uint32_t STTS_BIT_CH1011; /**< , offset: 0x30020 */ + __IO uint32_t STTS_BIT_CH1213; /**< , offset: 0x30024 */ + __IO uint32_t STTS_BIT_CH1415; /**< , offset: 0x30028 */ + __IO uint32_t STTS_BIT_CH1617; /**< , offset: 0x3002C */ + __IO uint32_t STTS_BIT_CH1819; /**< , offset: 0x30030 */ + __IO uint32_t STTS_BIT_CH2021; /**< , offset: 0x30034 */ + __IO uint32_t STTS_BIT_CH2223; /**< , offset: 0x30038 */ + __IO uint32_t STTS_BIT_CH2425; /**< , offset: 0x3003C */ + __IO uint32_t STTS_BIT_CH2627; /**< , offset: 0x30040 */ + __IO uint32_t STTS_BIT_CH2829; /**< , offset: 0x30044 */ + __IO uint32_t STTS_BIT_CH3031; /**< , offset: 0x30048 */ + __IO uint32_t SPDIF_CTRL_ADDR; /**< , offset: 0x3004C */ + __I uint32_t SPDIF_CH1_CS_3100_ADDR; /**< , offset: 0x30050 */ + __I uint32_t SPDIF_CH1_CS_6332_ADDR; /**< , offset: 0x30054 */ + __I uint32_t SPDIF_CH1_CS_9564_ADDR; /**< , offset: 0x30058 */ + __I uint32_t SPDIF_CH1_CS_12796_ADDR; /**< , offset: 0x3005C */ + __I uint32_t SPDIF_CH1_CS_159128_ADDR; /**< , offset: 0x30060 */ + __I uint32_t SPDIF_CH1_CS_191160_ADDR; /**< , offset: 0x30064 */ + __I uint32_t SPDIF_CH2_CS_3100_ADDR; /**< , offset: 0x30068 */ + __I uint32_t SPDIF_CH2_CS_6332_ADDR; /**< , offset: 0x3006C */ + __I uint32_t SPDIF_CH2_CS_9564_ADDR; /**< , offset: 0x30070 */ + __I uint32_t SPDIF_CH2_CS_12796_ADDR; /**< , offset: 0x30074 */ + __I uint32_t SPDIF_CH2_CS_159128_ADDR; /**< , offset: 0x30078 */ + __I uint32_t SPDIF_CH2_CS_191160_ADDR; /**< , offset: 0x3007C */ + __IO uint32_t SMPL2PKT_CNTL; /**< , offset: 0x30080 */ + __IO uint32_t SMPL2PKT_CNFG; /**< , offset: 0x30084 */ + __IO uint32_t FIFO_CNTL; /**< , offset: 0x30088 */ + __I uint32_t FIFO_STTS; /**< , offset: 0x3008C */ + __IO uint32_t SUB_PCKT_THRSH; /**< , offset: 0x30090 */ + uint8_t RESERVED_3[1900]; + __IO uint32_t SOURCE_PIF_WR_ADDR; /**< , offset: 0x30800 */ + __IO uint32_t SOURCE_PIF_WR_REQ; /**< , offset: 0x30804 */ + __IO uint32_t SOURCE_PIF_RD_ADDR; /**< , offset: 0x30808 */ + __IO uint32_t SOURCE_PIF_RD_REQ; /**< , offset: 0x3080C */ + __IO uint32_t SOURCE_PIF_DATA_WR; /**< , offset: 0x30810 */ + __I uint32_t SOURCE_PIF_DATA_RD; /**< , offset: 0x30814 */ + __IO uint32_t SOURCE_PIF_FIFO1_FLUSH; /**< , offset: 0x30818 */ + __IO uint32_t SOURCE_PIF_FIFO2_FLUSH; /**< , offset: 0x3081C */ + __I uint32_t SOURCE_PIF_STATUS; /**< , offset: 0x30820 */ + __I uint32_t SOURCE_PIF_INTERRUPT_SOURCE; /**< , offset: 0x30824 */ + __IO uint32_t SOURCE_PIF_INTERRUPT_MASK; /**< , offset: 0x30828 */ + __IO uint32_t SOURCE_PIF_PKT_ALLOC_REG; /**< , offset: 0x3082C */ + __IO uint32_t SOURCE_PIF_PKT_ALLOC_WR_EN; /**< , offset: 0x30830 */ + __IO uint32_t SOURCE_PIF_SW_RESET; /**< , offset: 0x30834 */ +} HDMI_TX_Type; + +/* ---------------------------------------------------------------------------- + -- HDMI_TX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HDMI_TX_Register_Masks HDMI_TX Register Masks + * @{ + */ + +/*! @name APB_CTRL - */ +/*! @{ */ + +#define HDMI_TX_APB_CTRL_apb_xt_reset_MASK (0x1U) +#define HDMI_TX_APB_CTRL_apb_xt_reset_SHIFT (0U) +/*! apb_xt_reset - APB Control on the CPU reset active High + */ +#define HDMI_TX_APB_CTRL_apb_xt_reset(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_CTRL_apb_xt_reset_SHIFT)) & HDMI_TX_APB_CTRL_apb_xt_reset_MASK) + +#define HDMI_TX_APB_CTRL_apb_dram_path_MASK (0x2U) +#define HDMI_TX_APB_CTRL_apb_dram_path_SHIFT (1U) +/*! apb_dram_path - When 1 enable APB to R/W the DRAM + */ +#define HDMI_TX_APB_CTRL_apb_dram_path(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_CTRL_apb_dram_path_SHIFT)) & HDMI_TX_APB_CTRL_apb_dram_path_MASK) + +#define HDMI_TX_APB_CTRL_apb_iram_path_MASK (0x4U) +#define HDMI_TX_APB_CTRL_apb_iram_path_SHIFT (2U) +/*! apb_iram_path - When 1 enable APB to R/W the IRAM + */ +#define HDMI_TX_APB_CTRL_apb_iram_path(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_CTRL_apb_iram_path_SHIFT)) & HDMI_TX_APB_CTRL_apb_iram_path_MASK) + +#define HDMI_TX_APB_CTRL_reserved_0_MASK (0xFFFFFFF8U) +#define HDMI_TX_APB_CTRL_reserved_0_SHIFT (3U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_APB_CTRL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_CTRL_reserved_0_SHIFT)) & HDMI_TX_APB_CTRL_reserved_0_MASK) +/*! @} */ + +/*! @name XT_INT_CTRL - */ +/*! @{ */ + +#define HDMI_TX_XT_INT_CTRL_xt_int_polarity_MASK (0x3U) +#define HDMI_TX_XT_INT_CTRL_xt_int_polarity_SHIFT (0U) +/*! xt_int_polarity - xt_int_polarity + */ +#define HDMI_TX_XT_INT_CTRL_xt_int_polarity(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_INT_CTRL_xt_int_polarity_SHIFT)) & HDMI_TX_XT_INT_CTRL_xt_int_polarity_MASK) + +#define HDMI_TX_XT_INT_CTRL_reserved_0_MASK (0xFFFFFFFCU) +#define HDMI_TX_XT_INT_CTRL_reserved_0_SHIFT (2U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_XT_INT_CTRL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_INT_CTRL_reserved_0_SHIFT)) & HDMI_TX_XT_INT_CTRL_reserved_0_MASK) +/*! @} */ + +/*! @name MAILBOX_FULL_ADDR - */ +/*! @{ */ + +#define HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full_MASK (0x1U) +#define HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full_SHIFT (0U) +/*! mailbox_full - Mailboxes full indication + */ +#define HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full_SHIFT)) & HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full_MASK) + +#define HDMI_TX_MAILBOX_FULL_ADDR_reserved_0_MASK (0xFFFFFFFEU) +#define HDMI_TX_MAILBOX_FULL_ADDR_reserved_0_SHIFT (1U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_MAILBOX_FULL_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_FULL_ADDR_reserved_0_SHIFT)) & HDMI_TX_MAILBOX_FULL_ADDR_reserved_0_MASK) +/*! @} */ + +/*! @name MAILBOX_EMPTY_ADDR - */ +/*! @{ */ + +#define HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty_MASK (0x1U) +#define HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty_SHIFT (0U) +/*! mailbox_empty - Mailboxes Empty indication + */ +#define HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty_SHIFT)) & HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty_MASK) + +#define HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0_MASK (0xFFFFFFFEU) +#define HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0_SHIFT (1U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0_SHIFT)) & HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0_MASK) +/*! @} */ + +/*! @name MAILBOX0_WR_DATA - */ +/*! @{ */ + +#define HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data_MASK (0xFFU) +#define HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data_SHIFT (0U) +/*! mailbox0_wr_data - Write Data to Mailbox + */ +#define HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data_SHIFT)) & HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data_MASK) + +#define HDMI_TX_MAILBOX0_WR_DATA_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_MAILBOX0_WR_DATA_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_MAILBOX0_WR_DATA_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX0_WR_DATA_reserved_0_SHIFT)) & HDMI_TX_MAILBOX0_WR_DATA_reserved_0_MASK) +/*! @} */ + +/*! @name MAILBOX0_RD_DATA - */ +/*! @{ */ + +#define HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data_MASK (0xFFU) +#define HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data_SHIFT (0U) +/*! mailbox0_rd_data - Mailbox Read data + */ +#define HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data_SHIFT)) & HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data_MASK) + +#define HDMI_TX_MAILBOX0_RD_DATA_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_MAILBOX0_RD_DATA_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_MAILBOX0_RD_DATA_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX0_RD_DATA_reserved_0_SHIFT)) & HDMI_TX_MAILBOX0_RD_DATA_reserved_0_MASK) +/*! @} */ + +/*! @name KEEP_ALIVE - */ +/*! @{ */ + +#define HDMI_TX_KEEP_ALIVE_keep_alive_cnt_MASK (0xFFU) +#define HDMI_TX_KEEP_ALIVE_keep_alive_cnt_SHIFT (0U) +/*! keep_alive_cnt - Software keep alive counter + */ +#define HDMI_TX_KEEP_ALIVE_keep_alive_cnt(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_KEEP_ALIVE_keep_alive_cnt_SHIFT)) & HDMI_TX_KEEP_ALIVE_keep_alive_cnt_MASK) + +#define HDMI_TX_KEEP_ALIVE_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_KEEP_ALIVE_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_KEEP_ALIVE_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_KEEP_ALIVE_reserved_0_SHIFT)) & HDMI_TX_KEEP_ALIVE_reserved_0_MASK) +/*! @} */ + +/*! @name VER_L - */ +/*! @{ */ + +#define HDMI_TX_VER_L_ver_lsb_MASK (0xFFU) +#define HDMI_TX_VER_L_ver_lsb_SHIFT (0U) +/*! ver_lsb - Software Version LSB + */ +#define HDMI_TX_VER_L_ver_lsb(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_L_ver_lsb_SHIFT)) & HDMI_TX_VER_L_ver_lsb_MASK) + +#define HDMI_TX_VER_L_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_VER_L_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_VER_L_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_L_reserved_0_SHIFT)) & HDMI_TX_VER_L_reserved_0_MASK) +/*! @} */ + +/*! @name VER_H - */ +/*! @{ */ + +#define HDMI_TX_VER_H_ver_msb_MASK (0xFFU) +#define HDMI_TX_VER_H_ver_msb_SHIFT (0U) +/*! ver_msb - Software Version MSB + */ +#define HDMI_TX_VER_H_ver_msb(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_H_ver_msb_SHIFT)) & HDMI_TX_VER_H_ver_msb_MASK) + +#define HDMI_TX_VER_H_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_VER_H_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_VER_H_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_H_reserved_0_SHIFT)) & HDMI_TX_VER_H_reserved_0_MASK) +/*! @} */ + +/*! @name VER_LIB_L_ADDR - */ +/*! @{ */ + +#define HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l_MASK (0xFFU) +#define HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l_SHIFT (0U) +/*! sw_lib_ver_l - Software Lib version written by CPU + */ +#define HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l_SHIFT)) & HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l_MASK) + +#define HDMI_TX_VER_LIB_L_ADDR_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_VER_LIB_L_ADDR_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_VER_LIB_L_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_LIB_L_ADDR_reserved_0_SHIFT)) & HDMI_TX_VER_LIB_L_ADDR_reserved_0_MASK) +/*! @} */ + +/*! @name VER_LIB_H_ADDR - */ +/*! @{ */ + +#define HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h_MASK (0xFFU) +#define HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h_SHIFT (0U) +/*! sw_lib_ver_h - Software Lib version written by CPU + */ +#define HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h_SHIFT)) & HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h_MASK) + +#define HDMI_TX_VER_LIB_H_ADDR_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_VER_LIB_H_ADDR_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_VER_LIB_H_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_LIB_H_ADDR_reserved_0_SHIFT)) & HDMI_TX_VER_LIB_H_ADDR_reserved_0_MASK) +/*! @} */ + +/*! @name SW_DEBUG_L - */ +/*! @{ */ + +#define HDMI_TX_SW_DEBUG_L_sw_debug_7_0_MASK (0xFFU) +#define HDMI_TX_SW_DEBUG_L_sw_debug_7_0_SHIFT (0U) +/*! sw_debug_7_0 - sw_debug_7_0 + */ +#define HDMI_TX_SW_DEBUG_L_sw_debug_7_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_DEBUG_L_sw_debug_7_0_SHIFT)) & HDMI_TX_SW_DEBUG_L_sw_debug_7_0_MASK) + +#define HDMI_TX_SW_DEBUG_L_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_SW_DEBUG_L_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SW_DEBUG_L_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_DEBUG_L_reserved_0_SHIFT)) & HDMI_TX_SW_DEBUG_L_reserved_0_MASK) +/*! @} */ + +/*! @name SW_DEBUG_H - */ +/*! @{ */ + +#define HDMI_TX_SW_DEBUG_H_sw_debug_15_8_MASK (0xFFU) +#define HDMI_TX_SW_DEBUG_H_sw_debug_15_8_SHIFT (0U) +/*! sw_debug_15_8 - sw_debug_15_8 + */ +#define HDMI_TX_SW_DEBUG_H_sw_debug_15_8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_DEBUG_H_sw_debug_15_8_SHIFT)) & HDMI_TX_SW_DEBUG_H_sw_debug_15_8_MASK) + +#define HDMI_TX_SW_DEBUG_H_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_SW_DEBUG_H_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SW_DEBUG_H_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_DEBUG_H_reserved_0_SHIFT)) & HDMI_TX_SW_DEBUG_H_reserved_0_MASK) +/*! @} */ + +/*! @name MAILBOX_INT_MASK - */ +/*! @{ */ + +#define HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask_MASK (0x3U) +#define HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask_SHIFT (0U) +/*! mailbox_int_mask - Mailbox Interupt mask Bit[0] - Empty Bit[1] - Full + */ +#define HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask_SHIFT)) & HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask_MASK) + +#define HDMI_TX_MAILBOX_INT_MASK_reserved_0_MASK (0xFFFFFFFCU) +#define HDMI_TX_MAILBOX_INT_MASK_reserved_0_SHIFT (2U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_MAILBOX_INT_MASK_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_INT_MASK_reserved_0_SHIFT)) & HDMI_TX_MAILBOX_INT_MASK_reserved_0_MASK) +/*! @} */ + +/*! @name MAILBOX_INT_STATUS - */ +/*! @{ */ + +#define HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status_MASK (0x3U) +#define HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status_SHIFT (0U) +/*! mailbox_int_status - Mailbox Interupt Status Bit[0] - Empty Bit[1] - Full + */ +#define HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status_SHIFT)) & HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status_MASK) + +#define HDMI_TX_MAILBOX_INT_STATUS_reserved_0_MASK (0xFFFFFFFCU) +#define HDMI_TX_MAILBOX_INT_STATUS_reserved_0_SHIFT (2U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_MAILBOX_INT_STATUS_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_INT_STATUS_reserved_0_SHIFT)) & HDMI_TX_MAILBOX_INT_STATUS_reserved_0_MASK) +/*! @} */ + +/*! @name SW_CLK_L - */ +/*! @{ */ + +#define HDMI_TX_SW_CLK_L_sw_clock_val_l_MASK (0xFFU) +#define HDMI_TX_SW_CLK_L_sw_clock_val_l_SHIFT (0U) +/*! sw_clock_val_l - Fractial of the clock decimal value + */ +#define HDMI_TX_SW_CLK_L_sw_clock_val_l(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_CLK_L_sw_clock_val_l_SHIFT)) & HDMI_TX_SW_CLK_L_sw_clock_val_l_MASK) + +#define HDMI_TX_SW_CLK_L_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_SW_CLK_L_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SW_CLK_L_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_CLK_L_reserved_0_SHIFT)) & HDMI_TX_SW_CLK_L_reserved_0_MASK) +/*! @} */ + +/*! @name SW_CLK_H - */ +/*! @{ */ + +#define HDMI_TX_SW_CLK_H_sw_clock_val_h_MASK (0xFFU) +#define HDMI_TX_SW_CLK_H_sw_clock_val_h_SHIFT (0U) +/*! sw_clock_val_h - Clock frequency in decimal values + */ +#define HDMI_TX_SW_CLK_H_sw_clock_val_h(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_CLK_H_sw_clock_val_h_SHIFT)) & HDMI_TX_SW_CLK_H_sw_clock_val_h_MASK) + +#define HDMI_TX_SW_CLK_H_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_SW_CLK_H_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SW_CLK_H_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_CLK_H_reserved_0_SHIFT)) & HDMI_TX_SW_CLK_H_reserved_0_MASK) +/*! @} */ + +/*! @name SW_EVENTS0 - */ +/*! @{ */ + +#define HDMI_TX_SW_EVENTS0_sw_events7_0_MASK (0xFFU) +#define HDMI_TX_SW_EVENTS0_sw_events7_0_SHIFT (0U) +/*! sw_events7_0 - When SW writes it updted just the extra event bits When Host read it is cleared + */ +#define HDMI_TX_SW_EVENTS0_sw_events7_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS0_sw_events7_0_SHIFT)) & HDMI_TX_SW_EVENTS0_sw_events7_0_MASK) + +#define HDMI_TX_SW_EVENTS0_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_SW_EVENTS0_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SW_EVENTS0_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS0_reserved_0_SHIFT)) & HDMI_TX_SW_EVENTS0_reserved_0_MASK) +/*! @} */ + +/*! @name SW_EVENTS1 - */ +/*! @{ */ + +#define HDMI_TX_SW_EVENTS1_sw_events15_8_MASK (0xFFU) +#define HDMI_TX_SW_EVENTS1_sw_events15_8_SHIFT (0U) +/*! sw_events15_8 - When SW writes it updted just the extra event bits When Host read it is cleared + */ +#define HDMI_TX_SW_EVENTS1_sw_events15_8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS1_sw_events15_8_SHIFT)) & HDMI_TX_SW_EVENTS1_sw_events15_8_MASK) + +#define HDMI_TX_SW_EVENTS1_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_SW_EVENTS1_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SW_EVENTS1_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS1_reserved_0_SHIFT)) & HDMI_TX_SW_EVENTS1_reserved_0_MASK) +/*! @} */ + +/*! @name SW_EVENTS2 - */ +/*! @{ */ + +#define HDMI_TX_SW_EVENTS2_sw_events23_16_MASK (0xFFU) +#define HDMI_TX_SW_EVENTS2_sw_events23_16_SHIFT (0U) +/*! sw_events23_16 - When SW writes it updted just the extra event bits When Host read it is cleared + */ +#define HDMI_TX_SW_EVENTS2_sw_events23_16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS2_sw_events23_16_SHIFT)) & HDMI_TX_SW_EVENTS2_sw_events23_16_MASK) + +#define HDMI_TX_SW_EVENTS2_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_SW_EVENTS2_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SW_EVENTS2_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS2_reserved_0_SHIFT)) & HDMI_TX_SW_EVENTS2_reserved_0_MASK) +/*! @} */ + +/*! @name SW_EVENTS3 - */ +/*! @{ */ + +#define HDMI_TX_SW_EVENTS3_sw_events31_24_MASK (0xFFU) +#define HDMI_TX_SW_EVENTS3_sw_events31_24_SHIFT (0U) +/*! sw_events31_24 - When SW writes it updted just the extra event bits When Host read it is cleared + */ +#define HDMI_TX_SW_EVENTS3_sw_events31_24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS3_sw_events31_24_SHIFT)) & HDMI_TX_SW_EVENTS3_sw_events31_24_MASK) + +#define HDMI_TX_SW_EVENTS3_reserved_0_MASK (0xFFFFFF00U) +#define HDMI_TX_SW_EVENTS3_reserved_0_SHIFT (8U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SW_EVENTS3_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS3_reserved_0_SHIFT)) & HDMI_TX_SW_EVENTS3_reserved_0_MASK) +/*! @} */ + +/*! @name XT_OCD_CTRL - */ +/*! @{ */ + +#define HDMI_TX_XT_OCD_CTRL_xt_dreset_MASK (0x1U) +#define HDMI_TX_XT_OCD_CTRL_xt_dreset_SHIFT (0U) +/*! xt_dreset - Xtensa Dreset control register + */ +#define HDMI_TX_XT_OCD_CTRL_xt_dreset(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_xt_dreset_SHIFT)) & HDMI_TX_XT_OCD_CTRL_xt_dreset_MASK) + +#define HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset_MASK (0x2U) +#define HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset_SHIFT (1U) +/*! xt_ocdhaltonreset - Xtensa Halt On Reget configuration register + */ +#define HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset_SHIFT)) & HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset_MASK) + +#define HDMI_TX_XT_OCD_CTRL_reserved_0_MASK (0xFFFFFFFCU) +#define HDMI_TX_XT_OCD_CTRL_reserved_0_SHIFT (2U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_XT_OCD_CTRL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_reserved_0_SHIFT)) & HDMI_TX_XT_OCD_CTRL_reserved_0_MASK) +/*! @} */ + +/*! @name XT_OCD_CTRL_RO - */ +/*! @{ */ + +#define HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode_MASK (0x1U) +#define HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode_SHIFT (0U) +/*! xt_xocdmode - Xtensa OCD mode configuration + */ +#define HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode_SHIFT)) & HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode_MASK) + +#define HDMI_TX_XT_OCD_CTRL_RO_reserved_0_MASK (0xFFFFFFFEU) +#define HDMI_TX_XT_OCD_CTRL_RO_reserved_0_SHIFT (1U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_XT_OCD_CTRL_RO_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_RO_reserved_0_SHIFT)) & HDMI_TX_XT_OCD_CTRL_RO_reserved_0_MASK) +/*! @} */ + +/*! @name APB_INT_MASK - */ +/*! @{ */ + +#define HDMI_TX_APB_INT_MASK_apb_intr_mask_MASK (0x7U) +#define HDMI_TX_APB_INT_MASK_apb_intr_mask_SHIFT (0U) +/*! apb_intr_mask - Mask the APB interupt Bit0 - Mailbox Interupt Bit1 - PIF Interupt Bit2 - CEC Interupt + */ +#define HDMI_TX_APB_INT_MASK_apb_intr_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_INT_MASK_apb_intr_mask_SHIFT)) & HDMI_TX_APB_INT_MASK_apb_intr_mask_MASK) + +#define HDMI_TX_APB_INT_MASK_reserved_0_MASK (0xFFFFFFF8U) +#define HDMI_TX_APB_INT_MASK_reserved_0_SHIFT (3U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_APB_INT_MASK_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_INT_MASK_reserved_0_SHIFT)) & HDMI_TX_APB_INT_MASK_reserved_0_MASK) +/*! @} */ + +/*! @name APB_STATUS_MASK - */ +/*! @{ */ + +#define HDMI_TX_APB_STATUS_MASK_apb_intr_status_MASK (0x7U) +#define HDMI_TX_APB_STATUS_MASK_apb_intr_status_SHIFT (0U) +/*! apb_intr_status - APB interupt STATUS Bit0 - Mailbox Interupt Bit1 - PIF Interupt Bit2 - CEC Interupt + */ +#define HDMI_TX_APB_STATUS_MASK_apb_intr_status(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_STATUS_MASK_apb_intr_status_SHIFT)) & HDMI_TX_APB_STATUS_MASK_apb_intr_status_MASK) + +#define HDMI_TX_APB_STATUS_MASK_reserved_0_MASK (0xFFFFFFF8U) +#define HDMI_TX_APB_STATUS_MASK_reserved_0_SHIFT (3U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_APB_STATUS_MASK_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_STATUS_MASK_reserved_0_SHIFT)) & HDMI_TX_APB_STATUS_MASK_reserved_0_MASK) +/*! @} */ + +/*! @name AUDIO_SRC_CNTL - */ +/*! @{ */ + +#define HDMI_TX_AUDIO_SRC_CNTL_sw_rst_MASK (0x1U) +#define HDMI_TX_AUDIO_SRC_CNTL_sw_rst_SHIFT (0U) +/*! sw_rst - Software reset. Active high. + */ +#define HDMI_TX_AUDIO_SRC_CNTL_sw_rst(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_sw_rst_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_sw_rst_MASK) + +#define HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start_MASK (0x2U) +#define HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start_SHIFT (1U) +/*! i2s_dec_start - When high Source Decoder starts. + */ +#define HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start_MASK) + +#define HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force_MASK (0x4U) +#define HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force_SHIFT (2U) +/*! i2s_block_start_force - Force a "Block Start" in the audio stream. + */ +#define HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force_MASK) + +#define HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en_MASK (0x8U) +#define HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en_SHIFT (3U) +/*! spdif_ts_en - Enble SPDIF Time Stamp when decoders are disabled + */ +#define HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en_MASK) + +#define HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en_MASK (0x10U) +#define HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en_SHIFT (4U) +/*! i2s_ts_en - Enble I2S Time Stamp when decoders are disabled + */ +#define HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en_MASK) + +#define HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force_MASK (0x20U) +#define HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force_SHIFT (5U) +/*! valid_bits_force - Force valid bits of the channels + */ +#define HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force_MASK) + +#define HDMI_TX_AUDIO_SRC_CNTL_valid_all_MASK (0x40U) +#define HDMI_TX_AUDIO_SRC_CNTL_valid_all_SHIFT (6U) +/*! valid_all - valid bit for all samples + */ +#define HDMI_TX_AUDIO_SRC_CNTL_valid_all(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_valid_all_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_valid_all_MASK) + +#define HDMI_TX_AUDIO_SRC_CNTL_reserved_0_MASK (0xFFFFFF80U) +#define HDMI_TX_AUDIO_SRC_CNTL_reserved_0_SHIFT (7U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_AUDIO_SRC_CNTL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_reserved_0_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_reserved_0_MASK) +/*! @} */ + +/*! @name AUDIO_SRC_CNFG - */ +/*! @{ */ + +#define HDMI_TX_AUDIO_SRC_CNFG_low_index_msb_MASK (0x1U) +#define HDMI_TX_AUDIO_SRC_CNFG_low_index_msb_SHIFT (0U) +/*! low_index_msb - When low MSB is transmitted first. When high LSB is transmitted first. + */ +#define HDMI_TX_AUDIO_SRC_CNFG_low_index_msb(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_low_index_msb_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_low_index_msb_MASK) + +#define HDMI_TX_AUDIO_SRC_CNFG_ws_polarity_MASK (0x2U) +#define HDMI_TX_AUDIO_SRC_CNFG_ws_polarity_SHIFT (1U) +/*! ws_polarity - Word Select Polarity. 0: No change, 1: Inverted. + */ +#define HDMI_TX_AUDIO_SRC_CNFG_ws_polarity(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_ws_polarity_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_ws_polarity_MASK) + +#define HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num_MASK (0x7CU) +#define HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num_SHIFT (2U) +/*! audio_ch_num - Number of channels to decode + */ +#define HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num_MASK) + +#define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just_MASK (0x180U) +#define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just_SHIFT (7U) +/*! audio_sample_just - Data justification setting:00 left-justified, 01 right-justified + */ +#define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just_MASK) + +#define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width_MASK (0x600U) +#define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width_SHIFT (9U) +/*! audio_sample_width - Decoder sample width:00-16 bit, 01-24 bit, 10-32 bit + */ +#define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width_MASK) + +#define HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width_MASK (0x1800U) +#define HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width_SHIFT (11U) +/*! trans_smpl_width - Decoder Word Select width: 00-16 bit, 01-24 bit, 10-32 bit + */ +#define HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width_MASK) + +#define HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type_MASK (0x1E000U) +#define HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type_SHIFT (13U) +/*! audio_channel_type - Set the transmission type. + */ +#define HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type_MASK) + +#define HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en_MASK (0x1E0000U) +#define HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en_SHIFT (17U) +/*! i2s_dec_port_en - Enables the I2S Decoder ports. Allowed values are:0001 - I2S port 0 is + * enabled.0011 - I2S ports 0,1 are enabled.1111 - I2S ports 0,1,2,3 are enabled. No other values are + * allowed. + */ +#define HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en_MASK) + +#define HDMI_TX_AUDIO_SRC_CNFG_reserved_0_MASK (0xFFE00000U) +#define HDMI_TX_AUDIO_SRC_CNFG_reserved_0_SHIFT (21U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_AUDIO_SRC_CNFG_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_reserved_0_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_reserved_0_MASK) +/*! @} */ + +/*! @name COM_CH_STTS_BITS - */ +/*! @{ */ + +#define HDMI_TX_COM_CH_STTS_BITS_Byte0_MASK (0xFFU) +#define HDMI_TX_COM_CH_STTS_BITS_Byte0_SHIFT (0U) +/*! Byte0 - Byte 0 of transmitted channel. Same for all channels. + */ +#define HDMI_TX_COM_CH_STTS_BITS_Byte0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Byte0_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Byte0_MASK) + +#define HDMI_TX_COM_CH_STTS_BITS_Category_Code_MASK (0xFF00U) +#define HDMI_TX_COM_CH_STTS_BITS_Category_Code_SHIFT (8U) +/*! Category_Code - Category Code of transmitted channel. Same for all channels. + */ +#define HDMI_TX_COM_CH_STTS_BITS_Category_Code(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Category_Code_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Category_Code_MASK) + +#define HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq_MASK (0xF0000U) +#define HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq_SHIFT (16U) +/*! Sampling_Freq - Sampling Frequency of transmitted channel. Same for all channels. + */ +#define HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq_MASK) + +#define HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy_MASK (0xF00000U) +#define HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy_SHIFT (20U) +/*! Clock_accuracy - Clock Accuracy of transmitted channel. Same for all channels. + */ +#define HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy_MASK) + +#define HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq_MASK (0xF000000U) +#define HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq_SHIFT (24U) +/*! Original_samp_freq - Original Sampling Freq. of transmitted channel. Same for all channels. + */ +#define HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq_MASK) + +#define HDMI_TX_COM_CH_STTS_BITS_reserved_0_MASK (0xF0000000U) +#define HDMI_TX_COM_CH_STTS_BITS_reserved_0_SHIFT (28U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_COM_CH_STTS_BITS_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_reserved_0_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH01 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH01_source_num_ch0_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH01_source_num_ch0_SHIFT (0U) +/*! source_num_ch0 - Channel 0 Source number. + */ +#define HDMI_TX_STTS_BIT_CH01_source_num_ch0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_source_num_ch0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_source_num_ch0_MASK) + +#define HDMI_TX_STTS_BIT_CH01_channel_num_ch0_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH01_channel_num_ch0_SHIFT (4U) +/*! channel_num_ch0 - Channel 0 channel number. + */ +#define HDMI_TX_STTS_BIT_CH01_channel_num_ch0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_channel_num_ch0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_channel_num_ch0_MASK) + +#define HDMI_TX_STTS_BIT_CH01_word_length_ch0_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH01_word_length_ch0_SHIFT (8U) +/*! word_length_ch0 - Channel 0 word length. + */ +#define HDMI_TX_STTS_BIT_CH01_word_length_ch0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_word_length_ch0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_word_length_ch0_MASK) + +#define HDMI_TX_STTS_BIT_CH01_source_num_ch1_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH01_source_num_ch1_SHIFT (12U) +/*! source_num_ch1 - Channel 1 Source number. + */ +#define HDMI_TX_STTS_BIT_CH01_source_num_ch1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_source_num_ch1_SHIFT)) & HDMI_TX_STTS_BIT_CH01_source_num_ch1_MASK) + +#define HDMI_TX_STTS_BIT_CH01_channel_num_ch1_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH01_channel_num_ch1_SHIFT (16U) +/*! channel_num_ch1 - Channel 1 channel number. + */ +#define HDMI_TX_STTS_BIT_CH01_channel_num_ch1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_channel_num_ch1_SHIFT)) & HDMI_TX_STTS_BIT_CH01_channel_num_ch1_MASK) + +#define HDMI_TX_STTS_BIT_CH01_word_length_ch1_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH01_word_length_ch1_SHIFT (20U) +/*! word_length_ch1 - Channel 1 word length. + */ +#define HDMI_TX_STTS_BIT_CH01_word_length_ch1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_word_length_ch1_SHIFT)) & HDMI_TX_STTS_BIT_CH01_word_length_ch1_MASK) + +#define HDMI_TX_STTS_BIT_CH01_valid_bits1_0_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH01_valid_bits1_0_SHIFT (24U) +/*! valid_bits1_0 - Valid Bits for channel 1 and 0 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH01_valid_bits1_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_valid_bits1_0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_valid_bits1_0_MASK) + +#define HDMI_TX_STTS_BIT_CH01_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH01_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH01_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH23 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH23_source_num_ch2_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH23_source_num_ch2_SHIFT (0U) +/*! source_num_ch2 - Channel 2 Source number. + */ +#define HDMI_TX_STTS_BIT_CH23_source_num_ch2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_source_num_ch2_SHIFT)) & HDMI_TX_STTS_BIT_CH23_source_num_ch2_MASK) + +#define HDMI_TX_STTS_BIT_CH23_channel_num_ch2_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH23_channel_num_ch2_SHIFT (4U) +/*! channel_num_ch2 - Channel 2 channel number. + */ +#define HDMI_TX_STTS_BIT_CH23_channel_num_ch2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_channel_num_ch2_SHIFT)) & HDMI_TX_STTS_BIT_CH23_channel_num_ch2_MASK) + +#define HDMI_TX_STTS_BIT_CH23_word_length_ch2_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH23_word_length_ch2_SHIFT (8U) +/*! word_length_ch2 - Channel 2 word length. + */ +#define HDMI_TX_STTS_BIT_CH23_word_length_ch2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_word_length_ch2_SHIFT)) & HDMI_TX_STTS_BIT_CH23_word_length_ch2_MASK) + +#define HDMI_TX_STTS_BIT_CH23_source_num_ch3_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH23_source_num_ch3_SHIFT (12U) +/*! source_num_ch3 - Channel 3 Source number. + */ +#define HDMI_TX_STTS_BIT_CH23_source_num_ch3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_source_num_ch3_SHIFT)) & HDMI_TX_STTS_BIT_CH23_source_num_ch3_MASK) + +#define HDMI_TX_STTS_BIT_CH23_channel_num_ch3_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH23_channel_num_ch3_SHIFT (16U) +/*! channel_num_ch3 - Channel 3 channel number. + */ +#define HDMI_TX_STTS_BIT_CH23_channel_num_ch3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_channel_num_ch3_SHIFT)) & HDMI_TX_STTS_BIT_CH23_channel_num_ch3_MASK) + +#define HDMI_TX_STTS_BIT_CH23_word_length_ch3_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH23_word_length_ch3_SHIFT (20U) +/*! word_length_ch3 - Channel 3 word length. + */ +#define HDMI_TX_STTS_BIT_CH23_word_length_ch3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_word_length_ch3_SHIFT)) & HDMI_TX_STTS_BIT_CH23_word_length_ch3_MASK) + +#define HDMI_TX_STTS_BIT_CH23_valid_bits3_2_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH23_valid_bits3_2_SHIFT (24U) +/*! valid_bits3_2 - Valid Bits for channel 3 and 2 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH23_valid_bits3_2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_valid_bits3_2_SHIFT)) & HDMI_TX_STTS_BIT_CH23_valid_bits3_2_MASK) + +#define HDMI_TX_STTS_BIT_CH23_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH23_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH23_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH23_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH45 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH45_source_num_ch4_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH45_source_num_ch4_SHIFT (0U) +/*! source_num_ch4 - Channel 4 Source number. + */ +#define HDMI_TX_STTS_BIT_CH45_source_num_ch4(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_source_num_ch4_SHIFT)) & HDMI_TX_STTS_BIT_CH45_source_num_ch4_MASK) + +#define HDMI_TX_STTS_BIT_CH45_channel_num_ch4_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH45_channel_num_ch4_SHIFT (4U) +/*! channel_num_ch4 - Channel 4 channel number. + */ +#define HDMI_TX_STTS_BIT_CH45_channel_num_ch4(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_channel_num_ch4_SHIFT)) & HDMI_TX_STTS_BIT_CH45_channel_num_ch4_MASK) + +#define HDMI_TX_STTS_BIT_CH45_word_length_ch4_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH45_word_length_ch4_SHIFT (8U) +/*! word_length_ch4 - Channel 4 word length. + */ +#define HDMI_TX_STTS_BIT_CH45_word_length_ch4(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_word_length_ch4_SHIFT)) & HDMI_TX_STTS_BIT_CH45_word_length_ch4_MASK) + +#define HDMI_TX_STTS_BIT_CH45_source_num_ch5_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH45_source_num_ch5_SHIFT (12U) +/*! source_num_ch5 - Channel 5 Source number. + */ +#define HDMI_TX_STTS_BIT_CH45_source_num_ch5(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_source_num_ch5_SHIFT)) & HDMI_TX_STTS_BIT_CH45_source_num_ch5_MASK) + +#define HDMI_TX_STTS_BIT_CH45_channel_num_ch5_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH45_channel_num_ch5_SHIFT (16U) +/*! channel_num_ch5 - Channel 5 channel number. + */ +#define HDMI_TX_STTS_BIT_CH45_channel_num_ch5(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_channel_num_ch5_SHIFT)) & HDMI_TX_STTS_BIT_CH45_channel_num_ch5_MASK) + +#define HDMI_TX_STTS_BIT_CH45_word_length_ch5_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH45_word_length_ch5_SHIFT (20U) +/*! word_length_ch5 - Channel 5 word length. + */ +#define HDMI_TX_STTS_BIT_CH45_word_length_ch5(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_word_length_ch5_SHIFT)) & HDMI_TX_STTS_BIT_CH45_word_length_ch5_MASK) + +#define HDMI_TX_STTS_BIT_CH45_valid_bits5_4_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH45_valid_bits5_4_SHIFT (24U) +/*! valid_bits5_4 - Valid Bits for channel 5 and 4 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH45_valid_bits5_4(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_valid_bits5_4_SHIFT)) & HDMI_TX_STTS_BIT_CH45_valid_bits5_4_MASK) + +#define HDMI_TX_STTS_BIT_CH45_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH45_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH45_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH45_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH67 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH67_source_num_ch6_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH67_source_num_ch6_SHIFT (0U) +/*! source_num_ch6 - Channel 6 Source number. + */ +#define HDMI_TX_STTS_BIT_CH67_source_num_ch6(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_source_num_ch6_SHIFT)) & HDMI_TX_STTS_BIT_CH67_source_num_ch6_MASK) + +#define HDMI_TX_STTS_BIT_CH67_channel_num_ch6_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH67_channel_num_ch6_SHIFT (4U) +/*! channel_num_ch6 - Channel 6 channel number. + */ +#define HDMI_TX_STTS_BIT_CH67_channel_num_ch6(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_channel_num_ch6_SHIFT)) & HDMI_TX_STTS_BIT_CH67_channel_num_ch6_MASK) + +#define HDMI_TX_STTS_BIT_CH67_word_length_ch6_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH67_word_length_ch6_SHIFT (8U) +/*! word_length_ch6 - Channel 6 word length. + */ +#define HDMI_TX_STTS_BIT_CH67_word_length_ch6(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_word_length_ch6_SHIFT)) & HDMI_TX_STTS_BIT_CH67_word_length_ch6_MASK) + +#define HDMI_TX_STTS_BIT_CH67_source_num_ch7_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH67_source_num_ch7_SHIFT (12U) +/*! source_num_ch7 - Channel 7 Source number. + */ +#define HDMI_TX_STTS_BIT_CH67_source_num_ch7(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_source_num_ch7_SHIFT)) & HDMI_TX_STTS_BIT_CH67_source_num_ch7_MASK) + +#define HDMI_TX_STTS_BIT_CH67_channel_num_ch7_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH67_channel_num_ch7_SHIFT (16U) +/*! channel_num_ch7 - Channel 7 channel number. + */ +#define HDMI_TX_STTS_BIT_CH67_channel_num_ch7(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_channel_num_ch7_SHIFT)) & HDMI_TX_STTS_BIT_CH67_channel_num_ch7_MASK) + +#define HDMI_TX_STTS_BIT_CH67_word_length_ch7_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH67_word_length_ch7_SHIFT (20U) +/*! word_length_ch7 - Channel 7 word length. + */ +#define HDMI_TX_STTS_BIT_CH67_word_length_ch7(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_word_length_ch7_SHIFT)) & HDMI_TX_STTS_BIT_CH67_word_length_ch7_MASK) + +#define HDMI_TX_STTS_BIT_CH67_valid_bits7_6_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH67_valid_bits7_6_SHIFT (24U) +/*! valid_bits7_6 - Valid Bits for channel 7 and 6 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH67_valid_bits7_6(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_valid_bits7_6_SHIFT)) & HDMI_TX_STTS_BIT_CH67_valid_bits7_6_MASK) + +#define HDMI_TX_STTS_BIT_CH67_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH67_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH67_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH67_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH89 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH89_source_num_ch8_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH89_source_num_ch8_SHIFT (0U) +/*! source_num_ch8 - Channel 8 Source number. + */ +#define HDMI_TX_STTS_BIT_CH89_source_num_ch8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_source_num_ch8_SHIFT)) & HDMI_TX_STTS_BIT_CH89_source_num_ch8_MASK) + +#define HDMI_TX_STTS_BIT_CH89_channel_num_ch8_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH89_channel_num_ch8_SHIFT (4U) +/*! channel_num_ch8 - Channel 8 channel number. + */ +#define HDMI_TX_STTS_BIT_CH89_channel_num_ch8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_channel_num_ch8_SHIFT)) & HDMI_TX_STTS_BIT_CH89_channel_num_ch8_MASK) + +#define HDMI_TX_STTS_BIT_CH89_word_length_ch8_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH89_word_length_ch8_SHIFT (8U) +/*! word_length_ch8 - Channel 8 word length. + */ +#define HDMI_TX_STTS_BIT_CH89_word_length_ch8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_word_length_ch8_SHIFT)) & HDMI_TX_STTS_BIT_CH89_word_length_ch8_MASK) + +#define HDMI_TX_STTS_BIT_CH89_source_num_ch9_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH89_source_num_ch9_SHIFT (12U) +/*! source_num_ch9 - Channel 9 Source number. + */ +#define HDMI_TX_STTS_BIT_CH89_source_num_ch9(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_source_num_ch9_SHIFT)) & HDMI_TX_STTS_BIT_CH89_source_num_ch9_MASK) + +#define HDMI_TX_STTS_BIT_CH89_channel_num_ch9_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH89_channel_num_ch9_SHIFT (16U) +/*! channel_num_ch9 - Channel 9 channel number. + */ +#define HDMI_TX_STTS_BIT_CH89_channel_num_ch9(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_channel_num_ch9_SHIFT)) & HDMI_TX_STTS_BIT_CH89_channel_num_ch9_MASK) + +#define HDMI_TX_STTS_BIT_CH89_word_length_ch9_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH89_word_length_ch9_SHIFT (20U) +/*! word_length_ch9 - Channel 9 word length. + */ +#define HDMI_TX_STTS_BIT_CH89_word_length_ch9(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_word_length_ch9_SHIFT)) & HDMI_TX_STTS_BIT_CH89_word_length_ch9_MASK) + +#define HDMI_TX_STTS_BIT_CH89_valid_bits9_8_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH89_valid_bits9_8_SHIFT (24U) +/*! valid_bits9_8 - Valid Bits for channel 9 and 8 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH89_valid_bits9_8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_valid_bits9_8_SHIFT)) & HDMI_TX_STTS_BIT_CH89_valid_bits9_8_MASK) + +#define HDMI_TX_STTS_BIT_CH89_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH89_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH89_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH89_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH1011 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH1011_source_num_ch10_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH1011_source_num_ch10_SHIFT (0U) +/*! source_num_ch10 - Channel 10 Source number. + */ +#define HDMI_TX_STTS_BIT_CH1011_source_num_ch10(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_source_num_ch10_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_source_num_ch10_MASK) + +#define HDMI_TX_STTS_BIT_CH1011_channel_num_ch10_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH1011_channel_num_ch10_SHIFT (4U) +/*! channel_num_ch10 - Channel 10 channel number. + */ +#define HDMI_TX_STTS_BIT_CH1011_channel_num_ch10(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_channel_num_ch10_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_channel_num_ch10_MASK) + +#define HDMI_TX_STTS_BIT_CH1011_word_length_ch10_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH1011_word_length_ch10_SHIFT (8U) +/*! word_length_ch10 - Channel 10 word length. + */ +#define HDMI_TX_STTS_BIT_CH1011_word_length_ch10(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_word_length_ch10_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_word_length_ch10_MASK) + +#define HDMI_TX_STTS_BIT_CH1011_source_num_ch11_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH1011_source_num_ch11_SHIFT (12U) +/*! source_num_ch11 - Channel 11 Source number. + */ +#define HDMI_TX_STTS_BIT_CH1011_source_num_ch11(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_source_num_ch11_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_source_num_ch11_MASK) + +#define HDMI_TX_STTS_BIT_CH1011_channel_num_ch11_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH1011_channel_num_ch11_SHIFT (16U) +/*! channel_num_ch11 - Channel 11 channel number. + */ +#define HDMI_TX_STTS_BIT_CH1011_channel_num_ch11(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_channel_num_ch11_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_channel_num_ch11_MASK) + +#define HDMI_TX_STTS_BIT_CH1011_word_length_ch11_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH1011_word_length_ch11_SHIFT (20U) +/*! word_length_ch11 - Channel 11 word length. + */ +#define HDMI_TX_STTS_BIT_CH1011_word_length_ch11(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_word_length_ch11_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_word_length_ch11_MASK) + +#define HDMI_TX_STTS_BIT_CH1011_valid_bits11_10_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH1011_valid_bits11_10_SHIFT (24U) +/*! valid_bits11_10 - Valid Bits for channel 11 and 10 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH1011_valid_bits11_10(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_valid_bits11_10_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_valid_bits11_10_MASK) + +#define HDMI_TX_STTS_BIT_CH1011_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH1011_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH1011_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH1213 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH1213_source_num_ch12_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH1213_source_num_ch12_SHIFT (0U) +/*! source_num_ch12 - Channel 12 Source number. + */ +#define HDMI_TX_STTS_BIT_CH1213_source_num_ch12(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_source_num_ch12_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_source_num_ch12_MASK) + +#define HDMI_TX_STTS_BIT_CH1213_channel_num_ch12_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH1213_channel_num_ch12_SHIFT (4U) +/*! channel_num_ch12 - Channel 12 channel number. + */ +#define HDMI_TX_STTS_BIT_CH1213_channel_num_ch12(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_channel_num_ch12_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_channel_num_ch12_MASK) + +#define HDMI_TX_STTS_BIT_CH1213_word_length_ch12_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH1213_word_length_ch12_SHIFT (8U) +/*! word_length_ch12 - Channel 12 word length. + */ +#define HDMI_TX_STTS_BIT_CH1213_word_length_ch12(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_word_length_ch12_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_word_length_ch12_MASK) + +#define HDMI_TX_STTS_BIT_CH1213_source_num_ch13_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH1213_source_num_ch13_SHIFT (12U) +/*! source_num_ch13 - Channel 13 Source number. + */ +#define HDMI_TX_STTS_BIT_CH1213_source_num_ch13(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_source_num_ch13_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_source_num_ch13_MASK) + +#define HDMI_TX_STTS_BIT_CH1213_channel_num_ch13_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH1213_channel_num_ch13_SHIFT (16U) +/*! channel_num_ch13 - Channel 13 channel number. + */ +#define HDMI_TX_STTS_BIT_CH1213_channel_num_ch13(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_channel_num_ch13_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_channel_num_ch13_MASK) + +#define HDMI_TX_STTS_BIT_CH1213_word_length_ch13_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH1213_word_length_ch13_SHIFT (20U) +/*! word_length_ch13 - Channel 13 word length. + */ +#define HDMI_TX_STTS_BIT_CH1213_word_length_ch13(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_word_length_ch13_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_word_length_ch13_MASK) + +#define HDMI_TX_STTS_BIT_CH1213_valid_bits13_12_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH1213_valid_bits13_12_SHIFT (24U) +/*! valid_bits13_12 - Valid Bits for channel 13 and 12 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH1213_valid_bits13_12(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_valid_bits13_12_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_valid_bits13_12_MASK) + +#define HDMI_TX_STTS_BIT_CH1213_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH1213_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH1213_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH1415 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH1415_source_num_ch14_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH1415_source_num_ch14_SHIFT (0U) +/*! source_num_ch14 - Channel 14 Source number. + */ +#define HDMI_TX_STTS_BIT_CH1415_source_num_ch14(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_source_num_ch14_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_source_num_ch14_MASK) + +#define HDMI_TX_STTS_BIT_CH1415_channel_num_ch14_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH1415_channel_num_ch14_SHIFT (4U) +/*! channel_num_ch14 - Channel 14 channel number. + */ +#define HDMI_TX_STTS_BIT_CH1415_channel_num_ch14(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_channel_num_ch14_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_channel_num_ch14_MASK) + +#define HDMI_TX_STTS_BIT_CH1415_word_length_ch14_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH1415_word_length_ch14_SHIFT (8U) +/*! word_length_ch14 - Channel 14 word length. + */ +#define HDMI_TX_STTS_BIT_CH1415_word_length_ch14(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_word_length_ch14_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_word_length_ch14_MASK) + +#define HDMI_TX_STTS_BIT_CH1415_source_num_ch15_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH1415_source_num_ch15_SHIFT (12U) +/*! source_num_ch15 - Channel 15 Source number. + */ +#define HDMI_TX_STTS_BIT_CH1415_source_num_ch15(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_source_num_ch15_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_source_num_ch15_MASK) + +#define HDMI_TX_STTS_BIT_CH1415_channel_num_ch15_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH1415_channel_num_ch15_SHIFT (16U) +/*! channel_num_ch15 - Channel 15 channel number. + */ +#define HDMI_TX_STTS_BIT_CH1415_channel_num_ch15(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_channel_num_ch15_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_channel_num_ch15_MASK) + +#define HDMI_TX_STTS_BIT_CH1415_word_length_ch15_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH1415_word_length_ch15_SHIFT (20U) +/*! word_length_ch15 - Channel 15 word length. + */ +#define HDMI_TX_STTS_BIT_CH1415_word_length_ch15(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_word_length_ch15_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_word_length_ch15_MASK) + +#define HDMI_TX_STTS_BIT_CH1415_valid_bits15_14_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH1415_valid_bits15_14_SHIFT (24U) +/*! valid_bits15_14 - Valid Bits for channel 15 and 14 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH1415_valid_bits15_14(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_valid_bits15_14_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_valid_bits15_14_MASK) + +#define HDMI_TX_STTS_BIT_CH1415_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH1415_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH1415_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH1617 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH1617_source_num_ch16_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH1617_source_num_ch16_SHIFT (0U) +/*! source_num_ch16 - Channel 16 Source number. + */ +#define HDMI_TX_STTS_BIT_CH1617_source_num_ch16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_source_num_ch16_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_source_num_ch16_MASK) + +#define HDMI_TX_STTS_BIT_CH1617_channel_num_ch16_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH1617_channel_num_ch16_SHIFT (4U) +/*! channel_num_ch16 - Channel 16 channel number. + */ +#define HDMI_TX_STTS_BIT_CH1617_channel_num_ch16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_channel_num_ch16_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_channel_num_ch16_MASK) + +#define HDMI_TX_STTS_BIT_CH1617_word_length_ch16_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH1617_word_length_ch16_SHIFT (8U) +/*! word_length_ch16 - Channel 16 word length. + */ +#define HDMI_TX_STTS_BIT_CH1617_word_length_ch16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_word_length_ch16_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_word_length_ch16_MASK) + +#define HDMI_TX_STTS_BIT_CH1617_source_num_ch17_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH1617_source_num_ch17_SHIFT (12U) +/*! source_num_ch17 - Channel 17 Source number. + */ +#define HDMI_TX_STTS_BIT_CH1617_source_num_ch17(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_source_num_ch17_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_source_num_ch17_MASK) + +#define HDMI_TX_STTS_BIT_CH1617_channel_num_ch17_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH1617_channel_num_ch17_SHIFT (16U) +/*! channel_num_ch17 - Channel 17 channel number. + */ +#define HDMI_TX_STTS_BIT_CH1617_channel_num_ch17(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_channel_num_ch17_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_channel_num_ch17_MASK) + +#define HDMI_TX_STTS_BIT_CH1617_word_length_ch17_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH1617_word_length_ch17_SHIFT (20U) +/*! word_length_ch17 - Channel 17 word length. + */ +#define HDMI_TX_STTS_BIT_CH1617_word_length_ch17(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_word_length_ch17_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_word_length_ch17_MASK) + +#define HDMI_TX_STTS_BIT_CH1617_valid_bits17_16_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH1617_valid_bits17_16_SHIFT (24U) +/*! valid_bits17_16 - Valid Bits for channel 17 and 16 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH1617_valid_bits17_16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_valid_bits17_16_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_valid_bits17_16_MASK) + +#define HDMI_TX_STTS_BIT_CH1617_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH1617_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH1617_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH1819 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH1819_source_num_ch18_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH1819_source_num_ch18_SHIFT (0U) +/*! source_num_ch18 - Channel 18 Source number. + */ +#define HDMI_TX_STTS_BIT_CH1819_source_num_ch18(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_source_num_ch18_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_source_num_ch18_MASK) + +#define HDMI_TX_STTS_BIT_CH1819_channel_num_ch18_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH1819_channel_num_ch18_SHIFT (4U) +/*! channel_num_ch18 - Channel 18 channel number. + */ +#define HDMI_TX_STTS_BIT_CH1819_channel_num_ch18(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_channel_num_ch18_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_channel_num_ch18_MASK) + +#define HDMI_TX_STTS_BIT_CH1819_word_length_ch18_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH1819_word_length_ch18_SHIFT (8U) +/*! word_length_ch18 - Channel 18 word length. + */ +#define HDMI_TX_STTS_BIT_CH1819_word_length_ch18(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_word_length_ch18_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_word_length_ch18_MASK) + +#define HDMI_TX_STTS_BIT_CH1819_source_num_ch19_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH1819_source_num_ch19_SHIFT (12U) +/*! source_num_ch19 - Channel 19 Source number. + */ +#define HDMI_TX_STTS_BIT_CH1819_source_num_ch19(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_source_num_ch19_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_source_num_ch19_MASK) + +#define HDMI_TX_STTS_BIT_CH1819_channel_num_ch19_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH1819_channel_num_ch19_SHIFT (16U) +/*! channel_num_ch19 - Channel 19 channel number. + */ +#define HDMI_TX_STTS_BIT_CH1819_channel_num_ch19(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_channel_num_ch19_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_channel_num_ch19_MASK) + +#define HDMI_TX_STTS_BIT_CH1819_word_length_ch19_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH1819_word_length_ch19_SHIFT (20U) +/*! word_length_ch19 - Channel 19 word length. + */ +#define HDMI_TX_STTS_BIT_CH1819_word_length_ch19(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_word_length_ch19_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_word_length_ch19_MASK) + +#define HDMI_TX_STTS_BIT_CH1819_valid_bits19_18_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH1819_valid_bits19_18_SHIFT (24U) +/*! valid_bits19_18 - Valid Bits for channel 19 and 18 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH1819_valid_bits19_18(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_valid_bits19_18_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_valid_bits19_18_MASK) + +#define HDMI_TX_STTS_BIT_CH1819_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH1819_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH1819_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH2021 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH2021_source_num_ch20_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH2021_source_num_ch20_SHIFT (0U) +/*! source_num_ch20 - Channel 20 Source number. + */ +#define HDMI_TX_STTS_BIT_CH2021_source_num_ch20(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_source_num_ch20_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_source_num_ch20_MASK) + +#define HDMI_TX_STTS_BIT_CH2021_channel_num_ch20_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH2021_channel_num_ch20_SHIFT (4U) +/*! channel_num_ch20 - Channel 20 channel number. + */ +#define HDMI_TX_STTS_BIT_CH2021_channel_num_ch20(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_channel_num_ch20_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_channel_num_ch20_MASK) + +#define HDMI_TX_STTS_BIT_CH2021_word_length_ch20_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH2021_word_length_ch20_SHIFT (8U) +/*! word_length_ch20 - Channel 20 word length. + */ +#define HDMI_TX_STTS_BIT_CH2021_word_length_ch20(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_word_length_ch20_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_word_length_ch20_MASK) + +#define HDMI_TX_STTS_BIT_CH2021_source_num_ch21_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH2021_source_num_ch21_SHIFT (12U) +/*! source_num_ch21 - Channel 21 Source number. + */ +#define HDMI_TX_STTS_BIT_CH2021_source_num_ch21(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_source_num_ch21_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_source_num_ch21_MASK) + +#define HDMI_TX_STTS_BIT_CH2021_channel_num_ch21_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH2021_channel_num_ch21_SHIFT (16U) +/*! channel_num_ch21 - Channel 21 channel number. + */ +#define HDMI_TX_STTS_BIT_CH2021_channel_num_ch21(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_channel_num_ch21_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_channel_num_ch21_MASK) + +#define HDMI_TX_STTS_BIT_CH2021_word_length_ch21_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH2021_word_length_ch21_SHIFT (20U) +/*! word_length_ch21 - Channel 21 word length. + */ +#define HDMI_TX_STTS_BIT_CH2021_word_length_ch21(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_word_length_ch21_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_word_length_ch21_MASK) + +#define HDMI_TX_STTS_BIT_CH2021_valid_bits21_20_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH2021_valid_bits21_20_SHIFT (24U) +/*! valid_bits21_20 - Valid Bits for channel 21 and 20 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH2021_valid_bits21_20(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_valid_bits21_20_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_valid_bits21_20_MASK) + +#define HDMI_TX_STTS_BIT_CH2021_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH2021_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH2021_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH2223 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH2223_source_num_ch22_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH2223_source_num_ch22_SHIFT (0U) +/*! source_num_ch22 - Channel 22 Source number. + */ +#define HDMI_TX_STTS_BIT_CH2223_source_num_ch22(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_source_num_ch22_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_source_num_ch22_MASK) + +#define HDMI_TX_STTS_BIT_CH2223_channel_num_ch22_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH2223_channel_num_ch22_SHIFT (4U) +/*! channel_num_ch22 - Channel 22 channel number. + */ +#define HDMI_TX_STTS_BIT_CH2223_channel_num_ch22(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_channel_num_ch22_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_channel_num_ch22_MASK) + +#define HDMI_TX_STTS_BIT_CH2223_word_length_ch22_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH2223_word_length_ch22_SHIFT (8U) +/*! word_length_ch22 - Channel 22 word length. + */ +#define HDMI_TX_STTS_BIT_CH2223_word_length_ch22(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_word_length_ch22_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_word_length_ch22_MASK) + +#define HDMI_TX_STTS_BIT_CH2223_source_num_ch23_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH2223_source_num_ch23_SHIFT (12U) +/*! source_num_ch23 - Channel 23 Source number. + */ +#define HDMI_TX_STTS_BIT_CH2223_source_num_ch23(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_source_num_ch23_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_source_num_ch23_MASK) + +#define HDMI_TX_STTS_BIT_CH2223_channel_num_ch23_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH2223_channel_num_ch23_SHIFT (16U) +/*! channel_num_ch23 - Channel 23 channel number. + */ +#define HDMI_TX_STTS_BIT_CH2223_channel_num_ch23(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_channel_num_ch23_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_channel_num_ch23_MASK) + +#define HDMI_TX_STTS_BIT_CH2223_word_length_ch23_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH2223_word_length_ch23_SHIFT (20U) +/*! word_length_ch23 - Channel 23 word length. + */ +#define HDMI_TX_STTS_BIT_CH2223_word_length_ch23(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_word_length_ch23_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_word_length_ch23_MASK) + +#define HDMI_TX_STTS_BIT_CH2223_valid_bits23_22_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH2223_valid_bits23_22_SHIFT (24U) +/*! valid_bits23_22 - Valid Bits for channel 23 and 22 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH2223_valid_bits23_22(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_valid_bits23_22_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_valid_bits23_22_MASK) + +#define HDMI_TX_STTS_BIT_CH2223_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH2223_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH2223_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH2425 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH2425_source_num_ch24_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH2425_source_num_ch24_SHIFT (0U) +/*! source_num_ch24 - Channel 24 Source number. + */ +#define HDMI_TX_STTS_BIT_CH2425_source_num_ch24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_source_num_ch24_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_source_num_ch24_MASK) + +#define HDMI_TX_STTS_BIT_CH2425_channel_num_ch24_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH2425_channel_num_ch24_SHIFT (4U) +/*! channel_num_ch24 - Channel 24 channel number. + */ +#define HDMI_TX_STTS_BIT_CH2425_channel_num_ch24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_channel_num_ch24_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_channel_num_ch24_MASK) + +#define HDMI_TX_STTS_BIT_CH2425_word_length_ch24_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH2425_word_length_ch24_SHIFT (8U) +/*! word_length_ch24 - Channel 24 word length. + */ +#define HDMI_TX_STTS_BIT_CH2425_word_length_ch24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_word_length_ch24_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_word_length_ch24_MASK) + +#define HDMI_TX_STTS_BIT_CH2425_source_num_ch25_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH2425_source_num_ch25_SHIFT (12U) +/*! source_num_ch25 - Channel 25 Source number. + */ +#define HDMI_TX_STTS_BIT_CH2425_source_num_ch25(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_source_num_ch25_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_source_num_ch25_MASK) + +#define HDMI_TX_STTS_BIT_CH2425_channel_num_ch25_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH2425_channel_num_ch25_SHIFT (16U) +/*! channel_num_ch25 - Channel 25 channel number. + */ +#define HDMI_TX_STTS_BIT_CH2425_channel_num_ch25(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_channel_num_ch25_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_channel_num_ch25_MASK) + +#define HDMI_TX_STTS_BIT_CH2425_word_length_ch25_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH2425_word_length_ch25_SHIFT (20U) +/*! word_length_ch25 - Channel 25 word length. + */ +#define HDMI_TX_STTS_BIT_CH2425_word_length_ch25(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_word_length_ch25_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_word_length_ch25_MASK) + +#define HDMI_TX_STTS_BIT_CH2425_valid_bits25_24_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH2425_valid_bits25_24_SHIFT (24U) +/*! valid_bits25_24 - Valid Bits for channel 25 and 24 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH2425_valid_bits25_24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_valid_bits25_24_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_valid_bits25_24_MASK) + +#define HDMI_TX_STTS_BIT_CH2425_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH2425_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH2425_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH2627 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH2627_source_num_ch26_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH2627_source_num_ch26_SHIFT (0U) +/*! source_num_ch26 - Channel 26 Source number. + */ +#define HDMI_TX_STTS_BIT_CH2627_source_num_ch26(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_source_num_ch26_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_source_num_ch26_MASK) + +#define HDMI_TX_STTS_BIT_CH2627_channel_num_ch26_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH2627_channel_num_ch26_SHIFT (4U) +/*! channel_num_ch26 - Channel 26 channel number. + */ +#define HDMI_TX_STTS_BIT_CH2627_channel_num_ch26(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_channel_num_ch26_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_channel_num_ch26_MASK) + +#define HDMI_TX_STTS_BIT_CH2627_word_length_ch26_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH2627_word_length_ch26_SHIFT (8U) +/*! word_length_ch26 - Channel 26 word length. + */ +#define HDMI_TX_STTS_BIT_CH2627_word_length_ch26(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_word_length_ch26_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_word_length_ch26_MASK) + +#define HDMI_TX_STTS_BIT_CH2627_source_num_ch27_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH2627_source_num_ch27_SHIFT (12U) +/*! source_num_ch27 - Channel 27 Source number. + */ +#define HDMI_TX_STTS_BIT_CH2627_source_num_ch27(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_source_num_ch27_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_source_num_ch27_MASK) + +#define HDMI_TX_STTS_BIT_CH2627_channel_num_ch27_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH2627_channel_num_ch27_SHIFT (16U) +/*! channel_num_ch27 - Channel 27 channel number. + */ +#define HDMI_TX_STTS_BIT_CH2627_channel_num_ch27(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_channel_num_ch27_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_channel_num_ch27_MASK) + +#define HDMI_TX_STTS_BIT_CH2627_word_length_ch27_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH2627_word_length_ch27_SHIFT (20U) +/*! word_length_ch27 - Channel 27 word length. + */ +#define HDMI_TX_STTS_BIT_CH2627_word_length_ch27(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_word_length_ch27_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_word_length_ch27_MASK) + +#define HDMI_TX_STTS_BIT_CH2627_valid_bits27_26_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH2627_valid_bits27_26_SHIFT (24U) +/*! valid_bits27_26 - Valid Bits for channel 27 and 26 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH2627_valid_bits27_26(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_valid_bits27_26_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_valid_bits27_26_MASK) + +#define HDMI_TX_STTS_BIT_CH2627_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH2627_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH2627_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH2829 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH2829_source_num_ch28_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH2829_source_num_ch28_SHIFT (0U) +/*! source_num_ch28 - Channel 28 Source number. + */ +#define HDMI_TX_STTS_BIT_CH2829_source_num_ch28(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_source_num_ch28_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_source_num_ch28_MASK) + +#define HDMI_TX_STTS_BIT_CH2829_channel_num_ch28_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH2829_channel_num_ch28_SHIFT (4U) +/*! channel_num_ch28 - Channel 28 channel number. + */ +#define HDMI_TX_STTS_BIT_CH2829_channel_num_ch28(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_channel_num_ch28_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_channel_num_ch28_MASK) + +#define HDMI_TX_STTS_BIT_CH2829_word_length_ch28_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH2829_word_length_ch28_SHIFT (8U) +/*! word_length_ch28 - Channel 28 word length. + */ +#define HDMI_TX_STTS_BIT_CH2829_word_length_ch28(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_word_length_ch28_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_word_length_ch28_MASK) + +#define HDMI_TX_STTS_BIT_CH2829_source_num_ch29_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH2829_source_num_ch29_SHIFT (12U) +/*! source_num_ch29 - Channel 29 Source number. + */ +#define HDMI_TX_STTS_BIT_CH2829_source_num_ch29(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_source_num_ch29_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_source_num_ch29_MASK) + +#define HDMI_TX_STTS_BIT_CH2829_channel_num_ch29_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH2829_channel_num_ch29_SHIFT (16U) +/*! channel_num_ch29 - Channel 29 channel number. + */ +#define HDMI_TX_STTS_BIT_CH2829_channel_num_ch29(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_channel_num_ch29_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_channel_num_ch29_MASK) + +#define HDMI_TX_STTS_BIT_CH2829_word_length_ch29_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH2829_word_length_ch29_SHIFT (20U) +/*! word_length_ch29 - Channel 29 word length. + */ +#define HDMI_TX_STTS_BIT_CH2829_word_length_ch29(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_word_length_ch29_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_word_length_ch29_MASK) + +#define HDMI_TX_STTS_BIT_CH2829_valid_bits29_28_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH2829_valid_bits29_28_SHIFT (24U) +/*! valid_bits29_28 - Valid Bits for channel 29 and 28 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH2829_valid_bits29_28(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_valid_bits29_28_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_valid_bits29_28_MASK) + +#define HDMI_TX_STTS_BIT_CH2829_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH2829_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH2829_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_reserved_0_MASK) +/*! @} */ + +/*! @name STTS_BIT_CH3031 - */ +/*! @{ */ + +#define HDMI_TX_STTS_BIT_CH3031_source_num_ch30_MASK (0xFU) +#define HDMI_TX_STTS_BIT_CH3031_source_num_ch30_SHIFT (0U) +/*! source_num_ch30 - Channel 30 Source number. + */ +#define HDMI_TX_STTS_BIT_CH3031_source_num_ch30(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_source_num_ch30_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_source_num_ch30_MASK) + +#define HDMI_TX_STTS_BIT_CH3031_channel_num_ch30_MASK (0xF0U) +#define HDMI_TX_STTS_BIT_CH3031_channel_num_ch30_SHIFT (4U) +/*! channel_num_ch30 - Channel 30 channel number. + */ +#define HDMI_TX_STTS_BIT_CH3031_channel_num_ch30(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_channel_num_ch30_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_channel_num_ch30_MASK) + +#define HDMI_TX_STTS_BIT_CH3031_word_length_ch30_MASK (0xF00U) +#define HDMI_TX_STTS_BIT_CH3031_word_length_ch30_SHIFT (8U) +/*! word_length_ch30 - Channel 30 word length. + */ +#define HDMI_TX_STTS_BIT_CH3031_word_length_ch30(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_word_length_ch30_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_word_length_ch30_MASK) + +#define HDMI_TX_STTS_BIT_CH3031_source_num_ch31_MASK (0xF000U) +#define HDMI_TX_STTS_BIT_CH3031_source_num_ch31_SHIFT (12U) +/*! source_num_ch31 - Channel 31 Source number. + */ +#define HDMI_TX_STTS_BIT_CH3031_source_num_ch31(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_source_num_ch31_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_source_num_ch31_MASK) + +#define HDMI_TX_STTS_BIT_CH3031_channel_num_ch31_MASK (0xF0000U) +#define HDMI_TX_STTS_BIT_CH3031_channel_num_ch31_SHIFT (16U) +/*! channel_num_ch31 - Channel 31 channel number. + */ +#define HDMI_TX_STTS_BIT_CH3031_channel_num_ch31(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_channel_num_ch31_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_channel_num_ch31_MASK) + +#define HDMI_TX_STTS_BIT_CH3031_word_length_ch31_MASK (0xF00000U) +#define HDMI_TX_STTS_BIT_CH3031_word_length_ch31_SHIFT (20U) +/*! word_length_ch31 - Channel 31 word length. + */ +#define HDMI_TX_STTS_BIT_CH3031_word_length_ch31(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_word_length_ch31_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_word_length_ch31_MASK) + +#define HDMI_TX_STTS_BIT_CH3031_valid_bits31_30_MASK (0x3000000U) +#define HDMI_TX_STTS_BIT_CH3031_valid_bits31_30_SHIFT (24U) +/*! valid_bits31_30 - Valid Bits for channel 31 and 30 if force is enabled + */ +#define HDMI_TX_STTS_BIT_CH3031_valid_bits31_30(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_valid_bits31_30_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_valid_bits31_30_MASK) + +#define HDMI_TX_STTS_BIT_CH3031_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_STTS_BIT_CH3031_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_STTS_BIT_CH3031_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_reserved_0_MASK) +/*! @} */ + +/*! @name SPDIF_CTRL_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win_MASK (0x7U) +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win_SHIFT (0U) +/*! spdif_jitter_avg_win - Spdif Jitter AVG Window + */ +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win_MASK) + +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh_MASK (0x7F8U) +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh_SHIFT (3U) +/*! spdif_jitter_thrsh - SPDIF Jitter threshold + */ +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh_MASK) + +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range_MASK (0x7F800U) +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range_SHIFT (11U) +/*! spdif_fifo_mid_range - SPDIF fifo mid range + */ +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range_MASK) + +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass_MASK (0x80000U) +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass_SHIFT (19U) +/*! spdif_jitter_bypass - SPDIF Jitter Bypass + */ +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass_MASK) + +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel_MASK (0x100000U) +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel_SHIFT (20U) +/*! spdif_avg_sel - SPDIF average Select + */ +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel_MASK) + +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable_MASK (0x200000U) +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable_SHIFT (21U) +/*! spdif_enable - SPDIF Enable + */ +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable_MASK) + +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status_MASK (0x3C00000U) +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status_SHIFT (22U) +/*! spdif_jitter_status - SPDIF Jitter Status + */ +#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status_MASK) + +#define HDMI_TX_SPDIF_CTRL_ADDR_reserved_0_MASK (0xFC000000U) +#define HDMI_TX_SPDIF_CTRL_ADDR_reserved_0_SHIFT (26U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SPDIF_CTRL_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_reserved_0_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_reserved_0_MASK) +/*! @} */ + +/*! @name SPDIF_CH1_CS_3100_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100_MASK (0xFFFFFFFFU) +#define HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100_SHIFT (0U) +/*! spdif_ch1_st_stts_bits3100 - SPDIF Channel 1 Status bits[31:0] + */ +#define HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100_MASK) +/*! @} */ + +/*! @name SPDIF_CH1_CS_6332_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332_MASK (0xFFFFFFFFU) +#define HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332_SHIFT (0U) +/*! spdif_ch1_st_stts_bits6332 - SPDIF Channel 1 Status bits[63:32] + */ +#define HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332_MASK) +/*! @} */ + +/*! @name SPDIF_CH1_CS_9564_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564_MASK (0xFFFFFFFFU) +#define HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564_SHIFT (0U) +/*! spdif_ch1_st_stts_bits9564 - SPDIF Channel 1 Status bits[95:64] + */ +#define HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564_MASK) +/*! @} */ + +/*! @name SPDIF_CH1_CS_12796_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796_MASK (0xFFFFFFFFU) +#define HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796_SHIFT (0U) +/*! spdif_ch1_st_stts_bits12796 - SPDIF Channel 1 Status bits[127:96] + */ +#define HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796_MASK) +/*! @} */ + +/*! @name SPDIF_CH1_CS_159128_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128_MASK (0xFFFFFFFFU) +#define HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128_SHIFT (0U) +/*! spdif_ch1_st_stts_bits159128 - SPDIF Channel 1 Status bits[159:128] + */ +#define HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128_MASK) +/*! @} */ + +/*! @name SPDIF_CH1_CS_191160_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160_MASK (0xFFFFFFFFU) +#define HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160_SHIFT (0U) +/*! spdif_ch1_st_stts_bits191160 - SPDIF Channel 1 Status bits[191160] + */ +#define HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160_MASK) +/*! @} */ + +/*! @name SPDIF_CH2_CS_3100_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100_MASK (0xFFFFFFFFU) +#define HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100_SHIFT (0U) +/*! spdif_ch2_st_stts_bits3100 - SPDIF Channel 2 Status bits[31:0] + */ +#define HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100_MASK) +/*! @} */ + +/*! @name SPDIF_CH2_CS_6332_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332_MASK (0xFFFFFFFFU) +#define HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332_SHIFT (0U) +/*! spdif_ch2_st_stts_bits6332 - SPDIF Channel 2 Status bits[63:32] + */ +#define HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332_MASK) +/*! @} */ + +/*! @name SPDIF_CH2_CS_9564_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564_MASK (0xFFFFFFFFU) +#define HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564_SHIFT (0U) +/*! spdif_ch2_st_stts_bits9564 - SPDIF Channel 2 Status bits[95:64] + */ +#define HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564_MASK) +/*! @} */ + +/*! @name SPDIF_CH2_CS_12796_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796_MASK (0xFFFFFFFFU) +#define HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796_SHIFT (0U) +/*! spdif_ch2_st_stts_bits12796 - SPDIF Channel 2 Status bits[127:96] + */ +#define HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796_MASK) +/*! @} */ + +/*! @name SPDIF_CH2_CS_159128_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128_MASK (0xFFFFFFFFU) +#define HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128_SHIFT (0U) +/*! spdif_ch2_st_stts_bits159128 - SPDIF Channel 2 Status bits[159:128] + */ +#define HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128_MASK) +/*! @} */ + +/*! @name SPDIF_CH2_CS_191160_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160_MASK (0xFFFFFFFFU) +#define HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160_SHIFT (0U) +/*! spdif_ch2_st_stts_bits191160 - SPDIF Channel 2 Status bits[191160] + */ +#define HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160_MASK) +/*! @} */ + +/*! @name SMPL2PKT_CNTL - */ +/*! @{ */ + +#define HDMI_TX_SMPL2PKT_CNTL_sw_rst_MASK (0x1U) +#define HDMI_TX_SMPL2PKT_CNTL_sw_rst_SHIFT (0U) +/*! sw_rst - Software reset. Active high. + */ +#define HDMI_TX_SMPL2PKT_CNTL_sw_rst(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNTL_sw_rst_SHIFT)) & HDMI_TX_SMPL2PKT_CNTL_sw_rst_MASK) + +#define HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en_MASK (0x2U) +#define HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en_SHIFT (1U) +/*! smpl2pkt_en - When high Sample to Packets Block starts. + */ +#define HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en_SHIFT)) & HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en_MASK) + +#define HDMI_TX_SMPL2PKT_CNTL_reserved_0_MASK (0xFFFFFFFCU) +#define HDMI_TX_SMPL2PKT_CNTL_reserved_0_SHIFT (2U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SMPL2PKT_CNTL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNTL_reserved_0_SHIFT)) & HDMI_TX_SMPL2PKT_CNTL_reserved_0_MASK) +/*! @} */ + +/*! @name SMPL2PKT_CNFG - */ +/*! @{ */ + +#define HDMI_TX_SMPL2PKT_CNFG_max_num_ch_MASK (0x1FU) +#define HDMI_TX_SMPL2PKT_CNFG_max_num_ch_SHIFT (0U) +/*! max_num_ch - Number of channels to decode. 0: 1 channel, 31: 32 channels + */ +#define HDMI_TX_SMPL2PKT_CNFG_max_num_ch(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_max_num_ch_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_max_num_ch_MASK) + +#define HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports_MASK (0x60U) +#define HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports_SHIFT (5U) +/*! num_of_i2s_ports - Number ofactive I2S ports. 00- 1 port, 01-2 ports, 11- 4 ports, 11 -NA. + */ +#define HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports_MASK) + +#define HDMI_TX_SMPL2PKT_CNFG_audio_type_MASK (0x780U) +#define HDMI_TX_SMPL2PKT_CNFG_audio_type_SHIFT (7U) +/*! audio_type - Audio Type setting. Packet is structured according to audio type. + */ +#define HDMI_TX_SMPL2PKT_CNFG_audio_type(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_audio_type_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_audio_type_MASK) + +#define HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num_MASK (0x3800U) +#define HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num_SHIFT (11U) +/*! cfg_sub_pckt_num - Number of sub-packets in HDMI audio 2-ch packet. 00: 1-SP, 01: 2-SP, 10: 3-SP, 11: 4-SP.100-111: NA. + */ +#define HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num_MASK) + +#define HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt_MASK (0x4000U) +#define HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt_SHIFT (14U) +/*! cfg_block_lpcm_first_pkt - 0 - All packets behave the same. 1- First lpcm audio packet is sent with 1 - SP. + */ +#define HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt_MASK) + +#define HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num_MASK (0x8000U) +#define HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num_SHIFT (15U) +/*! cfg_en_auto_sub_pckt_num - Enable automatics sub packet number. When enabled number of + * sub-packts will be set according to MEM FIFO number of samples. + */ +#define HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num_MASK) + +#define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_MASK (0xF0000U) +#define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_SHIFT (16U) +/*! cfg_sample_present - Sample present bits if force them is active + */ +#define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_MASK) + +#define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force_MASK (0x100000U) +#define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force_SHIFT (20U) +/*! cfg_sample_present_force - Force sample present bits + */ +#define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force_MASK) + +#define HDMI_TX_SMPL2PKT_CNFG_reserved_0_MASK (0xFFE00000U) +#define HDMI_TX_SMPL2PKT_CNFG_reserved_0_SHIFT (21U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SMPL2PKT_CNFG_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_reserved_0_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_reserved_0_MASK) +/*! @} */ + +/*! @name FIFO_CNTL - */ +/*! @{ */ + +#define HDMI_TX_FIFO_CNTL_fifo_sw_rst_MASK (0x1U) +#define HDMI_TX_FIFO_CNTL_fifo_sw_rst_SHIFT (0U) +/*! fifo_sw_rst - Resets Fifo's write and read pointers. When FIFO configuration bits change this + * signal should be high (due to synchronization issues). + */ +#define HDMI_TX_FIFO_CNTL_fifo_sw_rst(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_fifo_sw_rst_SHIFT)) & HDMI_TX_FIFO_CNTL_fifo_sw_rst_MASK) + +#define HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero_MASK (0x2U) +#define HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero_SHIFT (1U) +/*! sync_wr_to_ch_zero - When high the last channel index synchronizes the write addresses (to the next channel group) + */ +#define HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero_SHIFT)) & HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero_MASK) + +#define HDMI_TX_FIFO_CNTL_fifo_dir_MASK (0x4U) +#define HDMI_TX_FIFO_CNTL_fifo_dir_SHIFT (2U) +/*! fifo_dir - 0 - smpl2pkt (inc_step=number of I2S ports), 1 - pkt2smpl (inc_step=num_ch_per_port) + */ +#define HDMI_TX_FIFO_CNTL_fifo_dir(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_fifo_dir_SHIFT)) & HDMI_TX_FIFO_CNTL_fifo_dir_MASK) + +#define HDMI_TX_FIFO_CNTL_fifo_empty_calc_MASK (0x8U) +#define HDMI_TX_FIFO_CNTL_fifo_empty_calc_SHIFT (3U) +/*! fifo_empty_calc - 0- Empty is a function of read address. 1 - Empty is a function of BASE read address. + */ +#define HDMI_TX_FIFO_CNTL_fifo_empty_calc(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_fifo_empty_calc_SHIFT)) & HDMI_TX_FIFO_CNTL_fifo_empty_calc_MASK) + +#define HDMI_TX_FIFO_CNTL_cfg_dis_port3_MASK (0x10U) +#define HDMI_TX_FIFO_CNTL_cfg_dis_port3_SHIFT (4U) +/*! cfg_dis_port3 - 0 - Normal Operation. 1 - I2S port 3 is disabled (user should ignore its + * outputs). This allows for 24-ch, 12-ch, 6-ch transfer. + */ +#define HDMI_TX_FIFO_CNTL_cfg_dis_port3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_cfg_dis_port3_SHIFT)) & HDMI_TX_FIFO_CNTL_cfg_dis_port3_MASK) + +#define HDMI_TX_FIFO_CNTL_reserved_0_MASK (0xFFFFFFE0U) +#define HDMI_TX_FIFO_CNTL_reserved_0_SHIFT (5U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_FIFO_CNTL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_reserved_0_SHIFT)) & HDMI_TX_FIFO_CNTL_reserved_0_MASK) +/*! @} */ + +/*! @name FIFO_STTS - */ +/*! @{ */ + +#define HDMI_TX_FIFO_STTS_wfull_MASK (0x1U) +#define HDMI_TX_FIFO_STTS_wfull_SHIFT (0U) +/*! wfull - Indicates FIFO Full - indication comes with delay caused by Synchronization. + */ +#define HDMI_TX_FIFO_STTS_wfull(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_wfull_SHIFT)) & HDMI_TX_FIFO_STTS_wfull_MASK) + +#define HDMI_TX_FIFO_STTS_rempty_MASK (0x2U) +#define HDMI_TX_FIFO_STTS_rempty_SHIFT (1U) +/*! rempty - Indicates FIFO Empty - indication comes with delay caused by Synchronization. + */ +#define HDMI_TX_FIFO_STTS_rempty(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_rempty_SHIFT)) & HDMI_TX_FIFO_STTS_rempty_MASK) + +#define HDMI_TX_FIFO_STTS_overrun_MASK (0x4U) +#define HDMI_TX_FIFO_STTS_overrun_SHIFT (2U) +/*! overrun - Indicates a FIFO overrun error has occured - FIFO written to when it was full. + */ +#define HDMI_TX_FIFO_STTS_overrun(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_overrun_SHIFT)) & HDMI_TX_FIFO_STTS_overrun_MASK) + +#define HDMI_TX_FIFO_STTS_underrun_MASK (0x8U) +#define HDMI_TX_FIFO_STTS_underrun_SHIFT (3U) +/*! underrun - Indicates a FIFO underrun error has occured - FIFO read when it was empty. + */ +#define HDMI_TX_FIFO_STTS_underrun(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_underrun_SHIFT)) & HDMI_TX_FIFO_STTS_underrun_MASK) + +#define HDMI_TX_FIFO_STTS_reserved_0_MASK (0xFFFFFFF0U) +#define HDMI_TX_FIFO_STTS_reserved_0_SHIFT (4U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_FIFO_STTS_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_reserved_0_SHIFT)) & HDMI_TX_FIFO_STTS_reserved_0_MASK) +/*! @} */ + +/*! @name SUB_PCKT_THRSH - */ +/*! @{ */ + +#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1_MASK (0xFFU) +#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1_SHIFT (0U) +/*! cfg_mem_fifo_thrsh1 - If number of samples in MEM FIFO is below Threshold 1: Each Packet will contain only 1 subpacket. + */ +#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1_SHIFT)) & HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1_MASK) + +#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2_MASK (0xFF00U) +#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2_SHIFT (8U) +/*! cfg_mem_fifo_thrsh2 - If number of samples in MEM FIFO is below Threshold2: Each Packet will contain only 2 subpacket. + */ +#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2_SHIFT)) & HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2_MASK) + +#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3_MASK (0xFF0000U) +#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3_SHIFT (16U) +/*! cfg_mem_fifo_thrsh3 - If number of samples in MEM FIFO is below Threshold 3: Each Packet will contain only 3 subpacket. + */ +#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3_SHIFT)) & HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3_MASK) + +#define HDMI_TX_SUB_PCKT_THRSH_reserved_0_MASK (0xFF000000U) +#define HDMI_TX_SUB_PCKT_THRSH_reserved_0_SHIFT (24U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SUB_PCKT_THRSH_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SUB_PCKT_THRSH_reserved_0_SHIFT)) & HDMI_TX_SUB_PCKT_THRSH_reserved_0_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_WR_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr_MASK (0xFU) +#define HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr_SHIFT (0U) +/*! wr_addr - 4 MSB of the packet memory address in which the data is written. + */ +#define HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr_SHIFT)) & HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr_MASK) + +#define HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0_MASK (0xFFFFFFF0U) +#define HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0_SHIFT (4U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_WR_REQ - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_WR_REQ_host_wr_MASK (0x1U) +#define HDMI_TX_SOURCE_PIF_WR_REQ_host_wr_SHIFT (0U) +/*! host_wr - Write request bit for the host write transaction. + */ +#define HDMI_TX_SOURCE_PIF_WR_REQ_host_wr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_WR_REQ_host_wr_SHIFT)) & HDMI_TX_SOURCE_PIF_WR_REQ_host_wr_MASK) + +#define HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0_MASK (0xFFFFFFFEU) +#define HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0_SHIFT (1U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_RD_ADDR - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr_MASK (0xFU) +#define HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr_SHIFT (0U) +/*! rd_addr - 4 MSB of the packet memory address from which the data is read. + */ +#define HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr_SHIFT)) & HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr_MASK) + +#define HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0_MASK (0xFFFFFFF0U) +#define HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0_SHIFT (4U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_RD_REQ - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_RD_REQ_host_rd_MASK (0x1U) +#define HDMI_TX_SOURCE_PIF_RD_REQ_host_rd_SHIFT (0U) +/*! host_rd - Read request bit for the host read transaction + */ +#define HDMI_TX_SOURCE_PIF_RD_REQ_host_rd(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_RD_REQ_host_rd_SHIFT)) & HDMI_TX_SOURCE_PIF_RD_REQ_host_rd_MASK) + +#define HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0_MASK (0xFFFFFFFEU) +#define HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0_SHIFT (1U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_DATA_WR - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_DATA_WR_data_wr_MASK (0xFFFFFFFFU) +#define HDMI_TX_SOURCE_PIF_DATA_WR_data_wr_SHIFT (0U) +/*! data_wr - The 32 bits of the data to be written to the packet memory. When written to this + * register fifo1_wr_enable will be asserted. + */ +#define HDMI_TX_SOURCE_PIF_DATA_WR_data_wr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_DATA_WR_data_wr_SHIFT)) & HDMI_TX_SOURCE_PIF_DATA_WR_data_wr_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_DATA_RD - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out_MASK (0xFFFFFFFFU) +#define HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out_SHIFT (0U) +/*! fifo2_data_out - The 32 bits of the data to be read from the packet memory. When read from this + * register fifo2_rd_enable will be asserted. + */ +#define HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out_SHIFT)) & HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_FIFO1_FLUSH - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush_MASK (0x1U) +#define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush_SHIFT (0U) +/*! fifo1_flush - Fifo1 flush bit + */ +#define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush_SHIFT)) & HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush_MASK) + +#define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0_MASK (0xFFFFFFFEU) +#define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0_SHIFT (1U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_FIFO2_FLUSH - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush_MASK (0x1U) +#define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush_SHIFT (0U) +/*! fifo2_flush - Fifo2 flush bit + */ +#define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush_SHIFT)) & HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush_MASK) + +#define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0_MASK (0xFFFFFFFEU) +#define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0_SHIFT (1U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_STATUS - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state_MASK (0x3U) +#define HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state_SHIFT (0U) +/*! source_pkt_mem_ctrl_fsm_state - State of the FSM that controls packet memory transactions. + */ +#define HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state_SHIFT)) & HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state_MASK) + +#define HDMI_TX_SOURCE_PIF_STATUS_fifo1_full_MASK (0x4U) +#define HDMI_TX_SOURCE_PIF_STATUS_fifo1_full_SHIFT (2U) +/*! fifo1_full - Fifo1 full indication + */ +#define HDMI_TX_SOURCE_PIF_STATUS_fifo1_full(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_STATUS_fifo1_full_SHIFT)) & HDMI_TX_SOURCE_PIF_STATUS_fifo1_full_MASK) + +#define HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty_MASK (0x8U) +#define HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty_SHIFT (3U) +/*! fifo2_empty - Fifo2 empty indication + */ +#define HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty_SHIFT)) & HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty_MASK) + +#define HDMI_TX_SOURCE_PIF_STATUS_reserved_0_MASK (0xFFFFFFF0U) +#define HDMI_TX_SOURCE_PIF_STATUS_reserved_0_SHIFT (4U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SOURCE_PIF_STATUS_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_STATUS_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_STATUS_reserved_0_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_INTERRUPT_SOURCE - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int_MASK (0x1U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int_SHIFT (0U) +/*! host_wr_done_int - Indication that the host write transaction finished. + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int_MASK (0x2U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int_SHIFT (1U) +/*! host_rd_done_int - Indication that the host read transaction finished. + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int_MASK (0x4U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int_SHIFT (2U) +/*! nonvalid_type_requested_int - Indication that nonvalid type of packet is requested by the packet interface. + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr_MASK (0x8U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr_SHIFT (3U) +/*! pslverr - APB slave error interrupt + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done_MASK (0x10U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done_SHIFT (4U) +/*! alloc_wr_done - Successful write to the allocation table. + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error_MASK (0x20U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error_SHIFT (5U) +/*! alloc_wr_error - Error happened, invalid write to the allocation table. + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow_MASK (0x40U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow_SHIFT (6U) +/*! fifo1_overflow - Fifo1 overflow indication + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow_MASK (0x80U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow_SHIFT (7U) +/*! fifo1_underflow - Fifo1 underflow indication + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow_MASK (0x100U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow_SHIFT (8U) +/*! fifo2_overflow - Fifo2 overflow indication + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow_MASK (0x200U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow_SHIFT (9U) +/*! fifo2_underflow - Fifo2 underflow indication + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0_MASK (0xFFFFFC00U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0_SHIFT (10U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_INTERRUPT_MASK - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask_MASK (0x1U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask_SHIFT (0U) +/*! host_wr_done_int_mask - Masks the host_wr_done_int interrupt + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask_MASK (0x2U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask_SHIFT (1U) +/*! host_rd_done_int_mask - Masks the host_rd_done_int interrupt + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask_MASK (0x4U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask_SHIFT (2U) +/*! nonvalid_type_requested_int_mask - Masks the nonvalid_type_requested_int interrupt + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask_MASK (0x8U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask_SHIFT (3U) +/*! pslverr_mask - Masks the pslverr interrupt + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask_MASK (0x10U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask_SHIFT (4U) +/*! alloc_wr_done_mask - Masks the alloc_wr_done interrupt + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask_MASK (0x20U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask_SHIFT (5U) +/*! alloc_wr_error_mask - Masks the alloc_wr_error interrupt + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask_MASK (0x40U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask_SHIFT (6U) +/*! fifo1_overflow_mask - Masks the fifo1_overflow interrupt + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask_MASK (0x80U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask_SHIFT (7U) +/*! fifo1_underflow_mask - Masks the fifo1_underflow interrupt + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask_MASK (0x100U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask_SHIFT (8U) +/*! fifo2_overflow_mask - Masks the fifo2_overflow interrupt + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask_MASK (0x200U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask_SHIFT (9U) +/*! fifo2_underflow_mask - Masks the fifo2_underflow interrupt + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask_MASK) + +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0_MASK (0xFFFFFC00U) +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0_SHIFT (10U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_PKT_ALLOC_REG - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address_MASK (0xFU) +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address_SHIFT (0U) +/*! pkt_alloc_address - Address of the register in the source allocation table + */ +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address_MASK) + +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0_MASK (0xF0U) +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0_SHIFT (4U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0_MASK) + +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type_MASK (0xFF00U) +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type_SHIFT (8U) +/*! packet_type - Type of packet + */ +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type_MASK) + +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid_MASK (0x10000U) +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid_SHIFT (16U) +/*! type_valid - 1 for valid, 0 for nonvalid + */ +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid_MASK) + +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type_MASK (0x20000U) +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type_SHIFT (17U) +/*! active_idle_type - active_idle_type + */ +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type_MASK) + +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1_MASK (0xFFFC0000U) +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1_SHIFT (18U) +/*! reserved_1 - reserved_1 + */ +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_PKT_ALLOC_WR_EN - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en_MASK (0x1U) +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en_SHIFT (0U) +/*! pkt_alloc_wr_en - Enable bit for writing to the allocation table + */ +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en_MASK) + +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0_MASK (0xFFFFFFFEU) +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0_SHIFT (1U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0_MASK) +/*! @} */ + +/*! @name SOURCE_PIF_SW_RESET - */ +/*! @{ */ + +#define HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst_MASK (0x1U) +#define HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst_SHIFT (0U) +/*! sw_rst - Software reset + */ +#define HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst_SHIFT)) & HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst_MASK) + +#define HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0_MASK (0xFFFFFFFEU) +#define HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0_SHIFT (1U) +/*! reserved_0 - reserved_0 + */ +#define HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group HDMI_TX_Register_Masks */ + + +/* HDMI_TX - Peripheral instance base addresses */ +/** Peripheral HDMI_TX base address */ +#define HDMI_TX_BASE (0x32C00000u) +/** Peripheral HDMI_TX base pointer */ +#define HDMI_TX ((HDMI_TX_Type *)HDMI_TX_BASE) +/** Array initializer of HDMI_TX peripheral base addresses */ +#define HDMI_TX_BASE_ADDRS { HDMI_TX_BASE } +/** Array initializer of HDMI_TX peripheral base pointers */ +#define HDMI_TX_BASE_PTRS { HDMI_TX } + +/*! + * @} + */ /* end of group HDMI_TX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */ + uint8_t RESERVED_0[2]; + __IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */ + uint8_t RESERVED_1[2]; + __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */ + uint8_t RESERVED_2[2]; + __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */ + uint8_t RESERVED_3[2]; + __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name IADR - I2C Address Register */ +/*! @{ */ + +#define I2C_IADR_ADR_MASK (0xFEU) +#define I2C_IADR_ADR_SHIFT (1U) +#define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x)) << I2C_IADR_ADR_SHIFT)) & I2C_IADR_ADR_MASK) +/*! @} */ + +/*! @name IFDR - I2C Frequency Divider Register */ +/*! @{ */ + +#define I2C_IFDR_IC_MASK (0x3FU) +#define I2C_IFDR_IC_SHIFT (0U) +#define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x)) << I2C_IFDR_IC_SHIFT)) & I2C_IFDR_IC_MASK) +/*! @} */ + +/*! @name I2CR - I2C Control Register */ +/*! @{ */ + +#define I2C_I2CR_RSTA_MASK (0x4U) +#define I2C_I2CR_RSTA_SHIFT (2U) +/*! RSTA + * 0b0..No repeat start + * 0b1..Generates a Repeated Start condition + */ +#define I2C_I2CR_RSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_RSTA_SHIFT)) & I2C_I2CR_RSTA_MASK) + +#define I2C_I2CR_TXAK_MASK (0x8U) +#define I2C_I2CR_TXAK_SHIFT (3U) +/*! TXAK + * 0b0..An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. + * 0b1..No acknowledge signal response is sent (that is, the acknowledge bit = 1). + */ +#define I2C_I2CR_TXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_TXAK_SHIFT)) & I2C_I2CR_TXAK_MASK) + +#define I2C_I2CR_MTX_MASK (0x10U) +#define I2C_I2CR_MTX_SHIFT (4U) +/*! MTX + * 0b0..Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in + * the I2C status register (I2C_I2SR[SRW]). + * 0b1..Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1. + */ +#define I2C_I2CR_MTX(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MTX_SHIFT)) & I2C_I2CR_MTX_MASK) + +#define I2C_I2CR_MSTA_MASK (0x20U) +#define I2C_I2CR_MSTA_SHIFT (5U) +/*! MSTA + * 0b0..Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode. + * 0b1..Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode. + */ +#define I2C_I2CR_MSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MSTA_SHIFT)) & I2C_I2CR_MSTA_MASK) + +#define I2C_I2CR_IIEN_MASK (0x40U) +#define I2C_I2CR_IIEN_SHIFT (6U) +/*! IIEN + * 0b0..I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition occurs. + * 0b1..I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set. + */ +#define I2C_I2CR_IIEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IIEN_SHIFT)) & I2C_I2CR_IIEN_MASK) + +#define I2C_I2CR_IEN_MASK (0x80U) +#define I2C_I2CR_IEN_SHIFT (7U) +/*! IEN + * 0b0..The block is disabled, but registers can still be accessed. + * 0b1..The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect. + */ +#define I2C_I2CR_IEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IEN_SHIFT)) & I2C_I2CR_IEN_MASK) +/*! @} */ + +/*! @name I2SR - I2C Status Register */ +/*! @{ */ + +#define I2C_I2SR_RXAK_MASK (0x1U) +#define I2C_I2SR_RXAK_SHIFT (0U) +/*! RXAK + * 0b0..An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus. + * 0b1..A "No acknowledge" signal was detected at the ninth clock. + */ +#define I2C_I2SR_RXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_RXAK_SHIFT)) & I2C_I2SR_RXAK_MASK) + +#define I2C_I2SR_IIF_MASK (0x2U) +#define I2C_I2SR_IIF_SHIFT (1U) +/*! IIF + * 0b0..No I2C interrupt pending. + * 0b1..An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted + * [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the + * interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific + * address in Slave Receive mode. Arbitration is lost. + */ +#define I2C_I2SR_IIF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IIF_SHIFT)) & I2C_I2SR_IIF_MASK) + +#define I2C_I2SR_SRW_MASK (0x4U) +#define I2C_I2SR_SRW_SHIFT (2U) +/*! SRW + * 0b0..Slave receive, master writing to slave + * 0b1..Slave transmit, master reading from slave + */ +#define I2C_I2SR_SRW(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_SRW_SHIFT)) & I2C_I2SR_SRW_MASK) + +#define I2C_I2SR_IAL_MASK (0x10U) +#define I2C_I2SR_IAL_SHIFT (4U) +/*! IAL + * 0b0..No arbitration lost. + * 0b1..Arbitration is lost. + */ +#define I2C_I2SR_IAL(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAL_SHIFT)) & I2C_I2SR_IAL_MASK) + +#define I2C_I2SR_IBB_MASK (0x20U) +#define I2C_I2SR_IBB_SHIFT (5U) +/*! IBB + * 0b0..Bus is idle. If a Stop signal is detected, IBB is cleared. + * 0b1..Bus is busy. When Start is detected, IBB is set. + */ +#define I2C_I2SR_IBB(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IBB_SHIFT)) & I2C_I2SR_IBB_MASK) + +#define I2C_I2SR_IAAS_MASK (0x40U) +#define I2C_I2SR_IAAS_SHIFT (6U) +/*! IAAS + * 0b0..Not addressed + * 0b1..Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address. + */ +#define I2C_I2SR_IAAS(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAAS_SHIFT)) & I2C_I2SR_IAAS_MASK) + +#define I2C_I2SR_ICF_MASK (0x80U) +#define I2C_I2SR_ICF_SHIFT (7U) +/*! ICF + * 0b0..Transfer is in progress. + * 0b1..Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer. + */ +#define I2C_I2SR_ICF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_ICF_SHIFT)) & I2C_I2SR_ICF_MASK) +/*! @} */ + +/*! @name I2DR - I2C Data I/O Register */ +/*! @{ */ + +#define I2C_I2DR_DATA_MASK (0xFFU) +#define I2C_I2DR_DATA_SHIFT (0U) +#define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2DR_DATA_SHIFT)) & I2C_I2DR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x30A20000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** Peripheral I2C2 base address */ +#define I2C2_BASE (0x30A30000u) +/** Peripheral I2C2 base pointer */ +#define I2C2 ((I2C_Type *)I2C2_BASE) +/** Peripheral I2C3 base address */ +#define I2C3_BASE (0x30A40000u) +/** Peripheral I2C3 base pointer */ +#define I2C3 ((I2C_Type *)I2C3_BASE) +/** Peripheral I2C4 base address */ +#define I2C4_BASE (0x30A50000u) +/** Peripheral I2C4 base pointer */ +#define I2C4 ((I2C_Type *)I2C4_BASE) +/** Array initializer of I2C peripheral base addresses */ +#define I2C_BASE_ADDRS { 0u, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { (I2C_Type *)0u, I2C1, I2C2, I2C3, I2C4 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { NotAvail_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ + __O uint32_t TDR[8]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + __I uint32_t TFR[8]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_0[36]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ + __I uint32_t RDR[8]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + __I uint32_t RFR[8]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define I2S_VERID_FEATURE_MASK (0xFFFFU) +#define I2S_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set. + */ +#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) + +#define I2S_VERID_MINOR_MASK (0xFF0000U) +#define I2S_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ +#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) + +#define I2S_VERID_MAJOR_MASK (0xFF000000U) +#define I2S_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ +#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define I2S_PARAM_DATALINE_MASK (0xFU) +#define I2S_PARAM_DATALINE_SHIFT (0U) +/*! DATALINE - Number of Datalines + */ +#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) + +#define I2S_PARAM_FIFO_MASK (0xF00U) +#define I2S_PARAM_FIFO_SHIFT (8U) +/*! FIFO - FIFO Size + */ +#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) + +#define I2S_PARAM_FRAME_MASK (0xF0000U) +#define I2S_PARAM_FRAME_SHIFT (16U) +/*! FRAME - Frame Size + */ +#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ + +/*! @name TCSR - SAI Transmit Control Register */ +/*! @{ */ + +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) + +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) + +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) + +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) + +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) + +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) + +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) + +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Transmit FIFO watermark has not been reached. + * 0b1..Transmit FIFO watermark has been reached. + */ +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) + +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled transmit FIFO is empty. + * 0b1..Enabled transmit FIFO is empty. + */ +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) + +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Transmit underrun not detected. + * 0b1..Transmit underrun detected. + */ +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) + +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) + +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) + +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) + +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) + +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Transmit bit clock is disabled. + * 0b1..Transmit bit clock is enabled. + */ +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) + +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. + * 0b1..Transmitter is enabled in Debug mode. + */ +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) + +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +/*! TE - Transmitter Enable + * 0b0..Transmitter is disabled. + * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + */ +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ + +/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +/*! @{ */ + +#define I2S_TCR1_TFW_MASK (0x7FU) +#define I2S_TCR1_TFW_SHIFT (0U) +/*! TFW - Transmit FIFO Watermark + */ +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) +/*! @} */ + +/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +/*! @{ */ + +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide + */ +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) + +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) + +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) + +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) + +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) + +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) + +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with receiver. + * 0b10..Reserved. + * 0b11..Reserved. + */ +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ + +/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +/*! @{ */ + +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration + */ +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) + +#define I2S_TCR3_TCE_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (1, 8), largest definition used */ +#define I2S_TCR3_TCE_SHIFT (16U) +/*! TCE - Transmit Channel Enable + */ +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 8), largest definition used */ + +#define I2S_TCR3_CFR_MASK (0xFF000000U) +#define I2S_TCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset + */ +#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ + +/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +/*! @{ */ + +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame sync is generated externally in Slave mode. + * 0b1..Frame sync is generated internally in Master mode. + */ +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) + +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) + +#define I2S_TCR4_ONDEM_MASK (0x4U) +#define I2S_TCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ +#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) + +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) + +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is transmitted first. + * 0b1..MSB is transmitted first. + */ +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) + +#define I2S_TCR4_CHMOD_MASK (0x20U) +#define I2S_TCR4_CHMOD_SHIFT (5U) +/*! CHMOD - Channel Mode + * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. + * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. + */ +#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) + +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width + */ +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) + +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame size + */ +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) + +#define I2S_TCR4_FPACK_MASK (0x3000000U) +#define I2S_TCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ +#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) + +#define I2S_TCR4_FCOMB_MASK (0xC000000U) +#define I2S_TCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). + * 0b10..FIFO combine mode enabled on FIFO writes (by software). + * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + */ +#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) + +#define I2S_TCR4_FCONT_MASK (0x10000000U) +#define I2S_TCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ +#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ + +/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +/*! @{ */ + +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + */ +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) + +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + */ +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) + +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + */ +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ + +/*! @name TDR - SAI Transmit Data Register */ +/*! @{ */ + +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +/*! TDR - Transmit Data Register + */ +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (8U) + +/*! @name TFR - SAI Transmit FIFO Register */ +/*! @{ */ + +#define I2S_TFR_RFP_MASK (0xFFU) +#define I2S_TFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer + */ +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) + +#define I2S_TFR_WFP_MASK (0xFF0000U) +#define I2S_TFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer + */ +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) + +#define I2S_TFR_WCP_MASK (0x80000000U) +#define I2S_TFR_WCP_SHIFT (31U) +/*! WCP - Write Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + */ +#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (8U) + +/*! @name TMR - SAI Transmit Mask Register */ +/*! @{ */ + +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +/*! TWM - Transmit Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked. + */ +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ + +/*! @name RCSR - SAI Receive Control Register */ +/*! @{ */ + +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) + +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) + +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) + +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) + +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) + +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) + +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) + +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Receive FIFO watermark not reached. + * 0b1..Receive FIFO watermark has been reached. + */ +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) + +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled receive FIFO is full. + * 0b1..Enabled receive FIFO is full. + */ +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) + +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Receive overflow not detected. + * 0b1..Receive overflow detected. + */ +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) + +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) + +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) + +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) + +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) + +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Receive bit clock is disabled. + * 0b1..Receive bit clock is enabled. + */ +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) + +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Receiver is disabled in Debug mode, after completing the current frame. + * 0b1..Receiver is enabled in Debug mode. + */ +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) + +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +/*! RE - Receiver Enable + * 0b0..Receiver is disabled. + * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + */ +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ + +/*! @name RCR1 - SAI Receive Configuration 1 Register */ +/*! @{ */ + +#define I2S_RCR1_RFW_MASK (0x7FU) +#define I2S_RCR1_RFW_SHIFT (0U) +/*! RFW - Receive FIFO Watermark + */ +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) +/*! @} */ + +/*! @name RCR2 - SAI Receive Configuration 2 Register */ +/*! @{ */ + +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide + */ +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) + +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) + +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) + +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) + +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) + +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) + +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with transmitter. + * 0b10..Reserved. + * 0b11..Reserved. + */ +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ + +/*! @name RCR3 - SAI Receive Configuration 3 Register */ +/*! @{ */ + +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration + */ +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) + +#define I2S_RCR3_RCE_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (1, 8), largest definition used */ +#define I2S_RCR3_RCE_SHIFT (16U) +/*! RCE - Receive Channel Enable + */ +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 8), largest definition used */ + +#define I2S_RCR3_CFR_MASK (0xFF000000U) +#define I2S_RCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset + */ +#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ + +/*! @name RCR4 - SAI Receive Configuration 4 Register */ +/*! @{ */ + +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame Sync is generated externally in Slave mode. + * 0b1..Frame Sync is generated internally in Master mode. + */ +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) + +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) + +#define I2S_RCR4_ONDEM_MASK (0x4U) +#define I2S_RCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ +#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) + +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) + +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is received first. + * 0b1..MSB is received first. + */ +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) + +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width + */ +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) + +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame Size + */ +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) + +#define I2S_RCR4_FPACK_MASK (0x3000000U) +#define I2S_RCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved. + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ +#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) + +#define I2S_RCR4_FCOMB_MASK (0xC000000U) +#define I2S_RCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). + * 0b10..FIFO combine mode enabled on FIFO reads (by software). + * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + */ +#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) + +#define I2S_RCR4_FCONT_MASK (0x10000000U) +#define I2S_RCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ +#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ + +/*! @name RCR5 - SAI Receive Configuration 5 Register */ +/*! @{ */ + +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + */ +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) + +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + */ +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) + +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + */ +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ + +/*! @name RDR - SAI Receive Data Register */ +/*! @{ */ + +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +/*! RDR - Receive Data Register + */ +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (8U) + +/*! @name RFR - SAI Receive FIFO Register */ +/*! @{ */ + +#define I2S_RFR_RFP_MASK (0xFFU) +#define I2S_RFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer + */ +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) + +#define I2S_RFR_RCP_MASK (0x8000U) +#define I2S_RFR_RCP_SHIFT (15U) +/*! RCP - Receive Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. + */ +#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) + +#define I2S_RFR_WFP_MASK (0xFF0000U) +#define I2S_RFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer + */ +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) +/*! @} */ + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (8U) + +/*! @name RMR - SAI Receive Mask Register */ +/*! @{ */ + +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +/*! RWM - Receive Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. + */ +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S1 base address */ +#define I2S1_BASE (0x30010000u) +/** Peripheral I2S1 base pointer */ +#define I2S1 ((I2S_Type *)I2S1_BASE) +/** Peripheral I2S2 base address */ +#define I2S2_BASE (0x308B0000u) +/** Peripheral I2S2 base pointer */ +#define I2S2 ((I2S_Type *)I2S2_BASE) +/** Peripheral I2S3 base address */ +#define I2S3_BASE (0x308C0000u) +/** Peripheral I2S3 base pointer */ +#define I2S3 ((I2S_Type *)I2S3_BASE) +/** Peripheral I2S4 base address */ +#define I2S4_BASE (0x30050000u) +/** Peripheral I2S4 base pointer */ +#define I2S4 ((I2S_Type *)I2S4_BASE) +/** Peripheral I2S5 base address */ +#define I2S5_BASE (0x30040000u) +/** Peripheral I2S5 base pointer */ +#define I2S5 ((I2S_Type *)I2S5_BASE) +/** Peripheral I2S6 base address */ +#define I2S6_BASE (0x30030000u) +/** Peripheral I2S6 base pointer */ +#define I2S6 ((I2S_Type *)I2S6_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { 0u, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { (I2S_Type *)0u, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { NotAvail_IRQn, I2S1_IRQn, I2S2_IRQn, I2S3_IRQn, I2S4_IRQn, I2S56_IRQn, I2S56_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, I2S1_IRQn, I2S2_IRQn, I2S3_IRQn, I2S4_IRQn, I2S56_IRQn, I2S56_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer + * @{ + */ + +/** IOMUXC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[20]; + __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ; /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x14 */ + __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ; /**< SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x18 */ + __IO uint32_t SW_MUX_CTL_PAD_ONOFF; /**< SW_MUX_CTL_PAD_ONOFF SW MUX Control Register, offset: 0x1C */ + __IO uint32_t SW_MUX_CTL_PAD_POR_B; /**< SW_MUX_CTL_PAD_POR_B SW MUX Control Register, offset: 0x20 */ + __IO uint32_t SW_MUX_CTL_PAD_RTC_RESET_B; /**< SW_MUX_CTL_PAD_RTC_RESET_B SW MUX Control Register, offset: 0x24 */ + __IO uint32_t SW_MUX_CTL_PAD[139]; /**< SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register..SW_MUX_CTL_PAD_UART4_TXD SW MUX Control Register, array offset: 0x28, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD[154]; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_UART4_TXD SW PAD Control Register, array offset: 0x254, array step: 0x4 */ + __IO uint32_t SELECT_INPUT[30]; /**< CCM_PMIC_READY_SELECT_INPUT DAISY Register..SAI6_MCLK_SELECT_INPUT DAISY Register, array offset: 0x4BC, array step: 0x4 */ +} IOMUXC_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ +/*! @{ */ + +#define IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x40U) +#define IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (6U) +/*! SION - Software Input On Field + * 0b0..Input Path of pad PMIC_STBY_REQ is determined by functionality + * 0b1..Force Input Path of pad PMIC_STBY_REQ + */ +#define IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK) +/*! @} */ + +/*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ +/*! @{ */ + +#define IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x40U) +#define IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (6U) +/*! SION - Software Input On Field + * 0b0..Input Path of pad PMIC_ON_REQ is determined by functionality + * 0b1..Force Input Path of pad PMIC_ON_REQ + */ +#define IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK) +/*! @} */ + +/*! @name SW_MUX_CTL_PAD_ONOFF - SW_MUX_CTL_PAD_ONOFF SW MUX Control Register */ +/*! @{ */ + +#define IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION_MASK (0x40U) +#define IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION_SHIFT (6U) +/*! SION - Software Input On Field + * 0b0..Input Path of pad ONOFF is determined by functionality + * 0b1..Force Input Path of pad ONOFF + */ +#define IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION_MASK) +/*! @} */ + +/*! @name SW_MUX_CTL_PAD_POR_B - SW_MUX_CTL_PAD_POR_B SW MUX Control Register */ +/*! @{ */ + +#define IOMUXC_SW_MUX_CTL_PAD_POR_B_SION_MASK (0x40U) +#define IOMUXC_SW_MUX_CTL_PAD_POR_B_SION_SHIFT (6U) +/*! SION - Software Input On Field + * 0b0..Input Path of pad POR_B is determined by functionality + * 0b1..Force Input Path of pad POR_B + */ +#define IOMUXC_SW_MUX_CTL_PAD_POR_B_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_POR_B_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_POR_B_SION_MASK) +/*! @} */ + +/*! @name SW_MUX_CTL_PAD_RTC_RESET_B - SW_MUX_CTL_PAD_RTC_RESET_B SW MUX Control Register */ +/*! @{ */ + +#define IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION_MASK (0x40U) +#define IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION_SHIFT (6U) +/*! SION - Software Input On Field + * 0b0..Input Path of pad RTC_RESET_B is determined by functionality + * 0b1..Force Input Path of pad RTC_RESET_B + */ +#define IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION_MASK) +/*! @} */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register..SW_MUX_CTL_PAD_UART4_TXD SW MUX Control Register */ +/*! @{ */ + +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field + * 0b000..Select mux mode: ALT0 mux port: IO00 of instance: GPIO1 + * 0b001..Select mux mode: ALT1 mux port: ENET_PHY_REF_CLK_ROOT of instance: CCM + * 0b101..Select mux mode: ALT5 mux port: REF_CLK_32K of instance: ANAMIX + * 0b110..Select mux mode: ALT6 mux port: EXT_CLK1 of instance: CCM + */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) + +#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) +/*! SION - Software Input On Field + * 0b0..Input Path of pad GPIO1_IO00 is determined by functionality + * 0b1..Force Input Path of pad GPIO1_IO00 + */ +#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_MUX_CTL_PAD */ +#define IOMUXC_SW_MUX_CTL_PAD_COUNT (139U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_UART4_TXD SW PAD Control Register */ +/*! @{ */ + +#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x7U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (0U) +/*! DSE - Drive Strength Field + * 0b000..HI-Z + * 0b001..255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + * 0b010..105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + * 0b011..75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + * 0b100..85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + * 0b101..65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + * 0b110..45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + * 0b111..40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + */ +#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) + +#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x18U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (3U) +/*! SRE - Slew Rate Field + * 0b00..Slow Frequency Slew Rate (50Mhz) + * 0b01..Medium Frequency Slew Rate (100Mhz) + * 0b10..Fast Frequency Slew Rate (150Mhz) + * 0b11..Max Frequency Slew Rate (200Mhz) + */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) + +#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x20U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (5U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) + +#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x40U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (6U) +/*! PUE - Pull Up Enable Field + * 0b0..Pull Up Resistor Disabled + * 0b1..Pull Up Resistor Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) + +#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x80U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (7U) +/*! HYS - Schmitt trigger Enable Field + * 0b0..Schmitt Trigger Disabled + * 0b1..Schmitt Trigger Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) + +#define IOMUXC_SW_PAD_CTL_PAD_LVTTL_MASK (0x100U) +#define IOMUXC_SW_PAD_CTL_PAD_LVTTL_SHIFT (8U) +/*! LVTTL - Lvttl Enable Field + * 0b0..LVTTL Disabled + * 0b1..LVTTL Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_LVTTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_LVTTL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_LVTTL_MASK) + +#define IOMUXC_SW_PAD_CTL_PAD_VSEL_MASK (0x3800U) +#define IOMUXC_SW_PAD_CTL_PAD_VSEL_SHIFT (11U) +/*! VSEL - Voltage Select Field + * 0b000..Auto Detect 3.3/2.5/1.2/1.8 V mode + * 0b001..Auto Detect 3.3/2.5/1.2/1.8 V mode + * 0b010..Auto Detect 3.3/2.5/1.2/1.8 V mode + * 0b011..Auto Detect 3.3/2.5/1.2/1.8 V mode + * 0b100..Manually Set 3.3V mode + * 0b101..Manually Set 2.5V mode + * 0b110..Manually Set 2.5V mode + * 0b111..Manually Set 1.2V/1.8V mode + */ +#define IOMUXC_SW_PAD_CTL_PAD_VSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_VSEL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_VSEL_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_PAD_CTL_PAD */ +#define IOMUXC_SW_PAD_CTL_PAD_COUNT (154U) + +/*! @name SELECT_INPUT - CCM_PMIC_READY_SELECT_INPUT DAISY Register..SAI6_MCLK_SELECT_INPUT DAISY Register */ +/*! @{ */ + +#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) +/*! DAISY - Input Select (DAISY) Field + */ +#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +/*! @} */ + +/* The count of IOMUXC_SELECT_INPUT */ +#define IOMUXC_SELECT_INPUT_COUNT (30U) + + +/*! + * @} + */ /* end of group IOMUXC_Register_Masks */ + + +/* IOMUXC - Peripheral instance base addresses */ +/** Peripheral IOMUXC base address */ +#define IOMUXC_BASE (0x30330000u) +/** Peripheral IOMUXC base pointer */ +#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) +/** Array initializer of IOMUXC peripheral base addresses */ +#define IOMUXC_BASE_ADDRS { IOMUXC_BASE } +/** Array initializer of IOMUXC peripheral base pointers */ +#define IOMUXC_BASE_PTRS { IOMUXC } + +/*! + * @} + */ /* end of group IOMUXC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_GPR - Register Layout Typedef */ +typedef struct { + __IO uint32_t GPR[48]; /**< GPR0 General Purpose Register..GPR47 General Purpose Register, array offset: 0x0, array step: 0x4 */ +} IOMUXC_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/*! @name GPR - GPR0 General Purpose Register..GPR47 General Purpose Register */ +/*! @{ */ + +#define IOMUXC_GPR_GPR_ARCACHE_USDHC_MASK (0x1U) +#define IOMUXC_GPR_GPR_ARCACHE_USDHC_SHIFT (0U) +/*! ARCACHE_USDHC + * 0b0..Drive USDHC AXI Master ARCACHE[1] to 0 + * 0b1..Drive USDHC AXI Master ARCACHE[1] to 1 + */ +#define IOMUXC_GPR_GPR_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_USDHC_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT_MASK (0x3FFU) +#define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT_MASK (0x3FFU) +#define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT_MASK (0x3FFU) +#define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT_MASK (0x3FFU) +#define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR_MASK (0x1U) +#define IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_RX_RCAL_MASK (0x3U) +#define IOMUXC_GPR_GPR_CSI2_1_RX_RCAL_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_1_RX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_RX_RCAL_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT_MASK (0x3FFU) +#define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT_MASK (0x3FFU) +#define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT_MASK (0x3FFU) +#define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT_MASK (0x3FFU) +#define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR_MASK (0x1U) +#define IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_RX_RCAL_MASK (0x3U) +#define IOMUXC_GPR_GPR_CSI2_2_RX_RCAL_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_2_RX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_RX_RCAL_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN_SHIFT (0U) +#define IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN_MASK) + +#define IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT_MASK (0x3FFU) +#define IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT_SHIFT (0U) +#define IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT_MASK) + +#define IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT_MASK (0x3FFU) +#define IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT_SHIFT (0U) +#define IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT_MASK) + +#define IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT_MASK (0x3FFU) +#define IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT_SHIFT (0U) +#define IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT_MASK) + +#define IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT_MASK (0x3FFU) +#define IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT_SHIFT (0U) +#define IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT_MASK) + +#define IOMUXC_GPR_GPR_DSI_RX_RCAL_MASK (0x3U) +#define IOMUXC_GPR_GPR_DSI_RX_RCAL_SHIFT (0U) +#define IOMUXC_GPR_GPR_DSI_RX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR_DSI_RX_RCAL_MASK) + +#define IOMUXC_GPR_GPR_DSI_TEST_PATTERN_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR_DSI_TEST_PATTERN_SHIFT (0U) +#define IOMUXC_GPR_GPR_DSI_TEST_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TEST_PATTERN_SHIFT)) & IOMUXC_GPR_GPR_DSI_TEST_PATTERN_MASK) + +#define IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR_MASK (0x1U) +#define IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR_SHIFT (0U) +#define IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR_MASK) + +#define IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO_SHIFT (0U) +#define IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO_SHIFT)) & IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO_MASK) + +#define IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO_SHIFT (0U) +#define IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO_SHIFT)) & IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO_MASK) + +#define IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO_SHIFT (0U) +#define IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO_SHIFT)) & IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO_MASK) + +#define IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO_MASK (0x3FFFFFFFU) +#define IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO_SHIFT (0U) +#define IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO_SHIFT)) & IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO_MASK) + +#define IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN_SHIFT (0U) +#define IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN_MASK) + +#define IOMUXC_GPR_GPR_HDMI_HPD_PD_MASK (0x1U) +#define IOMUXC_GPR_GPR_HDMI_HPD_PD_SHIFT (0U) +#define IOMUXC_GPR_GPR_HDMI_HPD_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_HDMI_HPD_PD_SHIFT)) & IOMUXC_GPR_GPR_HDMI_HPD_PD_MASK) + +#define IOMUXC_GPR_GPR_OCRAM_TZ_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR_OCRAM_TZ_EN_SHIFT (0U) +/*! OCRAM_TZ_EN + * 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows + * the execution mode access policy described in CSU chapter. + */ +#define IOMUXC_GPR_GPR_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_TZ_EN_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW_MASK (0x7FU) +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW_SHIFT (0U) +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW_MASK (0x7FU) +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW_SHIFT (0U) +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW_MASK) + +#define IOMUXC_GPR_GPR_PCIE_DIAG_STATUS_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR_PCIE_DIAG_STATUS_SHIFT (0U) +#define IOMUXC_GPR_GPR_PCIE_DIAG_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE_DIAG_STATUS_SHIFT)) & IOMUXC_GPR_GPR_PCIE_DIAG_STATUS_MASK) + +#define IOMUXC_GPR_GPR_RDATA_WAIT_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR_RDATA_WAIT_EN_SHIFT (0U) +/*! RDATA_WAIT_EN + * 0b0..read data wait state disabled + * 0b1..read data wait state enabled + */ +#define IOMUXC_GPR_GPR_RDATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_RDATA_WAIT_EN_SHIFT)) & IOMUXC_GPR_GPR_RDATA_WAIT_EN_MASK) + +#define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_MASK (0x1U) +#define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_SHIFT (0U) +/*! SDMA1_IPG_STOP + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR_SDMA1_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SDMA1_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR_SDMA1_IPG_STOP_MASK) + +#define IOMUXC_GPR_GPR_TZASC_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR_TZASC_EN_SHIFT (0U) +#define IOMUXC_GPR_GPR_TZASC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC_EN_SHIFT)) & IOMUXC_GPR_GPR_TZASC_EN_MASK) + +#define IOMUXC_GPR_GPR_AWCACHE_USDHC_MASK (0x2U) +#define IOMUXC_GPR_GPR_AWCACHE_USDHC_SHIFT (1U) +/*! AWCACHE_USDHC + * 0b0..Drive USDHC AXI Master AWCACHE[1] to 0 + * 0b1..Drive USDHC AXI Master AWCACHE[1] to 1 + */ +#define IOMUXC_GPR_GPR_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_USDHC_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS_MASK (0x3EU) +#define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS_SHIFT (1U) +#define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS_MASK (0x3EU) +#define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS_SHIFT (1U) +#define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS_MASK) + +#define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS_MASK (0x3EU) +#define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS_SHIFT (1U) +#define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS_MASK) + +#define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0_MASK (0x2U) +#define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0_SHIFT (1U) +/*! ENET1_IPD_REQ_TIMER_SEL0 + * 0b0..Select ipd_req_mac0_timer2 to SDMA IRQ 45 + * 0b1..Select ipd_req_mac0_timer0 to SDMA IRQ 45 + */ +#define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0_SHIFT)) & IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0_MASK) + +#define IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN_SHIFT (1U) +#define IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN_MASK) + +#define IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD_MASK (0x2U) +#define IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD_SHIFT (1U) +#define IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD_SHIFT)) & IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD_MASK) + +#define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_MASK (0x3EU) +#define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_SHIFT (1U) +#define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_MASK) + +#define IOMUXC_GPR_GPR_RADDR_PIPE_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR_RADDR_PIPE_EN_SHIFT (1U) +/*! RADDR_PIPE_EN + * 0b0..read address pipeline is disabled + * 0b1..read address pipeline is enabled + */ +#define IOMUXC_GPR_GPR_RADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_RADDR_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_RADDR_PIPE_EN_MASK) + +#define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_MASK (0x2U) +#define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_SHIFT (1U) +#define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_SHIFT)) & IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE_MASK (0xFCU) +#define IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE_SHIFT (2U) +#define IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE_MASK (0xFCU) +#define IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE_SHIFT (2U) +#define IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE_MASK) + +#define IOMUXC_GPR_GPR_DSI_RTERM_SEL_MASK (0x4U) +#define IOMUXC_GPR_GPR_DSI_RTERM_SEL_SHIFT (2U) +#define IOMUXC_GPR_GPR_DSI_RTERM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_RTERM_SEL_SHIFT)) & IOMUXC_GPR_GPR_DSI_RTERM_SEL_MASK) + +#define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1_MASK (0x4U) +#define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1_SHIFT (2U) +/*! ENET1_IPD_REQ_TIMER_SEL1 + * 0b0..Select ipd_req_mac0_timer3 to SDMA IRQ 47 + * 0b1..Select ipd_req_mac0_timer1 to SDMA IRQ 47 + */ +#define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1_SHIFT)) & IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1_MASK) + +#define IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN_MASK (0x4U) +#define IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN_SHIFT (2U) +#define IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN_MASK) + +#define IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD_MASK (0x4U) +#define IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD_SHIFT (2U) +#define IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD_SHIFT)) & IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD_MASK) + +#define IOMUXC_GPR_GPR_MIPI_MUX_SEL_MASK (0x4U) +#define IOMUXC_GPR_GPR_MIPI_MUX_SEL_SHIFT (2U) +#define IOMUXC_GPR_GPR_MIPI_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_MIPI_MUX_SEL_SHIFT)) & IOMUXC_GPR_GPR_MIPI_MUX_SEL_MASK) + +#define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_MASK (0x4U) +#define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_SHIFT (2U) +/*! SEC_ERR_RESP_EN + * 0b0..OKAY response + * 0b1..SLVERR response + */ +#define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_MASK) + +#define IOMUXC_GPR_GPR_WDATA_PIPE_EN_MASK (0x4U) +#define IOMUXC_GPR_GPR_WDATA_PIPE_EN_SHIFT (2U) +/*! WDATA_PIPE_EN + * 0b0..write data pipeline is disabled + * 0b1..write data pipeline is enabled + */ +#define IOMUXC_GPR_GPR_WDATA_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDATA_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_WDATA_PIPE_EN_MASK) + +#define IOMUXC_GPR_GPR_DSI_RCALT_MASK (0x18U) +#define IOMUXC_GPR_GPR_DSI_RCALT_SHIFT (3U) +#define IOMUXC_GPR_GPR_DSI_RCALT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_RCALT_SHIFT)) & IOMUXC_GPR_GPR_DSI_RCALT_MASK) + +#define IOMUXC_GPR_GPR_ENET1_IPG_STOP_MASK (0x8U) +#define IOMUXC_GPR_GPR_ENET1_IPG_STOP_SHIFT (3U) +/*! ENET1_IPG_STOP + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR_ENET1_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR_ENET1_IPG_STOP_MASK) + +#define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_MASK (0x8U) +#define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_SHIFT (3U) +/*! EXC_ERR_RESP_EN + * 0b0..OK response on the AXI for an exclusive access error + * 0b1..ERR response on the AXI for an exclusive access error + */ +#define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_MASK) + +#define IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN_MASK (0x8U) +#define IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN_SHIFT (3U) +#define IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN_MASK) + +#define IOMUXC_GPR_GPR_HDMI_CEC_PD_MASK (0x8U) +#define IOMUXC_GPR_GPR_HDMI_CEC_PD_SHIFT (3U) +#define IOMUXC_GPR_GPR_HDMI_CEC_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_HDMI_CEC_PD_SHIFT)) & IOMUXC_GPR_GPR_HDMI_CEC_PD_MASK) + +#define IOMUXC_GPR_GPR_MIPI_MUX_INV_MASK (0x8U) +#define IOMUXC_GPR_GPR_MIPI_MUX_INV_SHIFT (3U) +#define IOMUXC_GPR_GPR_MIPI_MUX_INV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_MIPI_MUX_INV_SHIFT)) & IOMUXC_GPR_GPR_MIPI_MUX_INV_MASK) + +#define IOMUXC_GPR_GPR_WADDR_PIPE_EN_MASK (0x8U) +#define IOMUXC_GPR_GPR_WADDR_PIPE_EN_SHIFT (3U) +/*! WADDR_PIPE_EN + * 0b0..write address pipeline is disabled + * 0b1..write address pipeline is enabled + */ +#define IOMUXC_GPR_GPR_WADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WADDR_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_WADDR_PIPE_EN_MASK) + +#define IOMUXC_GPR_GPR_ARCACHE_PCIE1_MASK (0x10U) +#define IOMUXC_GPR_GPR_ARCACHE_PCIE1_SHIFT (4U) +/*! ARCACHE_PCIE1 + * 0b0..Drive PCIe AXI Master Port ARCACHE[1] to 0 + * 0b1..Drive PCIe AXI Master Port ARCACHE[1] to 1 + */ +#define IOMUXC_GPR_GPR_ARCACHE_PCIE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_PCIE1_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_PCIE1_MASK) + +#define IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN_MASK (0x10U) +#define IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN_SHIFT (4U) +#define IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN_MASK) + +#define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_MASK (0x10U) +#define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_SHIFT (4U) +/*! SDMA2_IPG_STOP + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR_SDMA2_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SDMA2_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR_SDMA2_IPG_STOP_MASK) + +#define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_MASK (0x10U) +#define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_SHIFT (4U) +#define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_SHIFT)) & IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_MASK) + +#define IOMUXC_GPR_GPR_AWCACHE_PCIE1_MASK (0x20U) +#define IOMUXC_GPR_GPR_AWCACHE_PCIE1_SHIFT (5U) +/*! AWCACHE_PCIE1 + * 0b0..Drive PCIe AXI Master Port AWCACHE[1] to 0 + * 0b1..Drive PCIe AXI Master Port AWCACHE[1] to 1 + */ +#define IOMUXC_GPR_GPR_AWCACHE_PCIE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_PCIE1_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_PCIE1_MASK) + +#define IOMUXC_GPR_GPR_DSI_NOCAL_MASK (0x20U) +#define IOMUXC_GPR_GPR_DSI_NOCAL_SHIFT (5U) +#define IOMUXC_GPR_GPR_DSI_NOCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_NOCAL_SHIFT)) & IOMUXC_GPR_GPR_DSI_NOCAL_MASK) + +#define IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN_MASK (0x20U) +#define IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN_SHIFT (5U) +#define IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN_MASK) + +#define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_MASK (0x20U) +#define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_SHIFT (5U) +#define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_MASK) + +#define IOMUXC_GPR_GPR_ARCACHE_LCDIF_MASK (0x40U) +#define IOMUXC_GPR_GPR_ARCACHE_LCDIF_SHIFT (6U) +/*! ARCACHE_LCDIF + * 0b0..Drive LCDIF AXI Master Port ARCACHE[1] to 0 + * 0b1..Drive LCDIF AXI Master Port ARCACHE[1] to 1 + */ +#define IOMUXC_GPR_GPR_ARCACHE_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_LCDIF_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_LCDIF_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR_MASK (0x40U) +#define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR_SHIFT (6U) +#define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR_MASK (0x40U) +#define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR_SHIFT (6U) +#define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR_MASK) + +#define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_MASK (0x40U) +#define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_SHIFT (6U) +#define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_MASK) + +#define IOMUXC_GPR_GPR_DSI_HSEL_MASK (0x40U) +#define IOMUXC_GPR_GPR_DSI_HSEL_SHIFT (6U) +#define IOMUXC_GPR_GPR_DSI_HSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_HSEL_SHIFT)) & IOMUXC_GPR_GPR_DSI_HSEL_MASK) + +#define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_MASK (0x40U) +#define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_SHIFT (6U) +#define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_MASK) + +#define IOMUXC_GPR_GPR_WDOG1_MASK_MASK (0x40U) +#define IOMUXC_GPR_GPR_WDOG1_MASK_SHIFT (6U) +/*! WDOG1_MASK + * 0b0..WDOG1 Timeout behaves normally + * 0b1..WDOG1 Timeout is masked + */ +#define IOMUXC_GPR_GPR_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR_WDOG1_MASK_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS_MASK (0x380U) +#define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS_SHIFT (7U) +#define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS_MASK (0x380U) +#define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS_SHIFT (7U) +#define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS_MASK) + +#define IOMUXC_GPR_GPR_DSI_ECC_ERR_POS_MASK (0x380U) +#define IOMUXC_GPR_GPR_DSI_ECC_ERR_POS_SHIFT (7U) +#define IOMUXC_GPR_GPR_DSI_ECC_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ECC_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_DSI_ECC_ERR_POS_MASK) + +#define IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE_MASK (0xF80U) +#define IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE_SHIFT (7U) +#define IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL_MASK (0x3F80U) +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL_SHIFT (7U) +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL_MASK (0x3F80U) +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL_SHIFT (7U) +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL_MASK) + +#define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_MASK (0x80U) +#define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_SHIFT (7U) +#define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_MASK) + +#define IOMUXC_GPR_GPR_WDOG2_MASK_MASK (0x80U) +#define IOMUXC_GPR_GPR_WDOG2_MASK_SHIFT (7U) +/*! WDOG2_MASK + * 0b0..WDOG2 Timeout behaves normally + * 0b1..WDOG2 Timeout is masked + */ +#define IOMUXC_GPR_GPR_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR_WDOG2_MASK_MASK) + +#define IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN_SHIFT (8U) +/*! ARCACHE_PCIE2_EN + * 0b0..PCIE Primary AXI Master Port ARCACHE[1] driven by PCIE + * 0b1..PCIE Primary AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_PCIE2 bit + */ +#define IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE_MASK (0x100U) +#define IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE_SHIFT (8U) +#define IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE_MASK (0x100U) +#define IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE_SHIFT (8U) +#define IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN_SHIFT (8U) +#define IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN_SHIFT (8U) +#define IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE_MASK (0xF00U) +#define IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE_SHIFT (8U) +/*! PCIE2_CTRL_DEVICE_TYPE + * 0b0000..PCI Express endpoint + * 0b0001..Legacy PCI Express endpoint + * 0b0100..Root port of PCI Express root complex + */ +#define IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE_MASK) + +#define IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN_MASK (0x200U) +#define IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN_SHIFT (9U) +/*! AWCACHE_PCIE2_EN + * 0b0..PCIE Primary AXI Master Port AWCACHE[1] driven by PCIE + * 0b1..PXP Primary AXI Master Port AWCACHE[1] driven to constant value specified by the AWCACHE_PCIE2 bit + */ +#define IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN_MASK (0x200U) +#define IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN_SHIFT (9U) +#define IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN_MASK (0x200U) +#define IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN_SHIFT (9U) +#define IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD_MASK (0x200U) +#define IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD_SHIFT (9U) +#define IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD_MASK (0x200U) +#define IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD_SHIFT (9U) +#define IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD_MASK) + +#define IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN_MASK (0x400U) +#define IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN_SHIFT (10U) +/*! ARCACHE_PCIE1_EN + * 0b0..PCIe AXI Master Port ARCACHE[1] driven by PCIe + * 0b1..PCIe AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_PXP1 bit + */ +#define IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT_MASK (0xFFC00U) +#define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT_SHIFT (10U) +#define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT_MASK (0xFFC00U) +#define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT_SHIFT (10U) +#define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT_MASK (0xFFC00U) +#define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT_SHIFT (10U) +#define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT_MASK (0xFFC00U) +#define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT_SHIFT (10U) +#define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_MASK (0x400U) +#define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_SHIFT (10U) +#define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_HSEL_MASK (0x400U) +#define IOMUXC_GPR_GPR_CSI2_1_HSEL_SHIFT (10U) +#define IOMUXC_GPR_GPR_CSI2_1_HSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_HSEL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_HSEL_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT_MASK (0xFFC00U) +#define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT_SHIFT (10U) +#define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT_MASK (0xFFC00U) +#define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT_SHIFT (10U) +#define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT_MASK (0xFFC00U) +#define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT_SHIFT (10U) +#define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT_MASK (0xFFC00U) +#define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT_SHIFT (10U) +#define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_MASK (0x400U) +#define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_SHIFT (10U) +#define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_HSEL_MASK (0x400U) +#define IOMUXC_GPR_GPR_CSI2_2_HSEL_SHIFT (10U) +#define IOMUXC_GPR_GPR_CSI2_2_HSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_HSEL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_HSEL_MASK) + +#define IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT_MASK (0xFFC00U) +#define IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT_SHIFT (10U) +#define IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT_MASK) + +#define IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT_MASK (0xFFC00U) +#define IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT_SHIFT (10U) +#define IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT_MASK) + +#define IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT_MASK (0xFFC00U) +#define IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT_SHIFT (10U) +#define IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT_MASK) + +#define IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT_MASK (0xFFC00U) +#define IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT_SHIFT (10U) +#define IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT_MASK) + +#define IOMUXC_GPR_GPR_DSI_ECC_ERR_MASK (0x400U) +#define IOMUXC_GPR_GPR_DSI_ECC_ERR_SHIFT (10U) +#define IOMUXC_GPR_GPR_DSI_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ECC_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_ECC_ERR_MASK) + +#define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_MASK (0x400U) +#define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_SHIFT (10U) +/*! OCRAM_S_TZ_EN + * 0b0..The TrustZone feature is disabled. Entire State Retention OCRAM space is available for all access types (secure/non-secure/user/supervisor). + * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows + * the execution mode access policy described in CSU chapter. + */ +#define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN_MASK (0x400U) +#define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN_SHIFT (10U) +#define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN_MASK (0x400U) +#define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN_SHIFT (10U) +#define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN_MASK) + +#define IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN_MASK (0x800U) +#define IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN_SHIFT (11U) +/*! AWCACHE_PCIE1_EN + * 0b0..PCIe AXI Master Port AWCACHE[1] driven by PCIe + * 0b1..PCIe AXI Master Port AWCACHE[1] driven to constant value specified by the AWCACHE_PCIE1 bit + */ +#define IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_PD_RX_MASK (0x800U) +#define IOMUXC_GPR_GPR_CSI2_1_PD_RX_SHIFT (11U) +#define IOMUXC_GPR_GPR_CSI2_1_PD_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_PD_RX_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_PD_RX_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE_MASK (0xF800U) +#define IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE_SHIFT (11U) +#define IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_PD_RX_MASK (0x800U) +#define IOMUXC_GPR_GPR_CSI2_2_PD_RX_SHIFT (11U) +#define IOMUXC_GPR_GPR_CSI2_2_PD_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_PD_RX_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_PD_RX_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE_MASK (0xF800U) +#define IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE_SHIFT (11U) +#define IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR_MASK (0x800U) +#define IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR_SHIFT (11U) +#define IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR_MASK) + +#define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_MASK (0x3800U) +#define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_SHIFT (11U) +#define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_MASK (0x800U) +#define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_SHIFT (11U) +#define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_MASK (0x800U) +#define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_SHIFT (11U) +#define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_MASK) + +#define IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN_MASK (0x1000U) +#define IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN_SHIFT (12U) +/*! ARCACHE_LCDIF_EN + * 0b0..LCDIF AXI Master Port ARCACHE[1] driven by LCDIF + * 0b1..LCDIF AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_LCDIF bit + */ +#define IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB_MASK (0x1000U) +#define IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB_SHIFT (12U) +#define IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB_MASK (0x1000U) +#define IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB_SHIFT (12U) +#define IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB_MASK) + +#define IOMUXC_GPR_GPR_DSI_TRIGGER_ACK_MASK (0x1000U) +#define IOMUXC_GPR_GPR_DSI_TRIGGER_ACK_SHIFT (12U) +#define IOMUXC_GPR_GPR_DSI_TRIGGER_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TRIGGER_ACK_SHIFT)) & IOMUXC_GPR_GPR_DSI_TRIGGER_ACK_MASK) + +#define IOMUXC_GPR_GPR_DSI_TRIGGER_SEND_MASK (0x3000U) +#define IOMUXC_GPR_GPR_DSI_TRIGGER_SEND_SHIFT (12U) +#define IOMUXC_GPR_GPR_DSI_TRIGGER_SEND(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TRIGGER_SEND_SHIFT)) & IOMUXC_GPR_GPR_DSI_TRIGGER_SEND_MASK) + +#define IOMUXC_GPR_GPR_IRQ_MASK (0x1000U) +#define IOMUXC_GPR_GPR_IRQ_SHIFT (12U) +#define IOMUXC_GPR_GPR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_IRQ_SHIFT)) & IOMUXC_GPR_GPR_IRQ_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE_MASK (0xF000U) +#define IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE_SHIFT (12U) +/*! PCIE1_CTRL_DEVICE_TYPE + * 0b0000..PCI Express endpoint + * 0b0001..Legacy PCI Express endpoint + * 0b0100..Root port of PCI Express root complex + */ +#define IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS_MASK (0x1000U) +#define IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS_SHIFT (12U) +#define IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS_MASK (0x1000U) +#define IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS_SHIFT (12U) +#define IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS_MASK) + +#define IOMUXC_GPR_GPR_ARCACHE_PCIE2_MASK (0x2000U) +#define IOMUXC_GPR_GPR_ARCACHE_PCIE2_SHIFT (13U) +/*! ARCACHE_PCIE2 + * 0b0..Drive PCIe AXI Master Port ARCACHE[1] to 0 + * 0b1..Drive PCIe AXI Master Port ARCACHE[1] to 1 + */ +#define IOMUXC_GPR_GPR_ARCACHE_PCIE2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_PCIE2_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_PCIE2_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE_MASK (0x2000U) +#define IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE_SHIFT (13U) +#define IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE_MASK (0x2000U) +#define IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE_SHIFT (13U) +#define IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE_MASK) + +#define IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT_MASK (0x2000U) +#define IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT_SHIFT (13U) +#define IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT_SHIFT)) & IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT_MASK) + +#define IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL_MASK (0x2000U) +#define IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL_SHIFT (13U) +/*! ENET1_TX_CLK_SEL + * 0b0..Gets ENET1 TX reference clk. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. + * 0b1..Gets ENET1 TX reference clk from the ENET1_TX_CLK pin. In this use case, an external OSC provides the + * clock for both the external PHY and the internal controller + */ +#define IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL_MASK (0xE000U) +#define IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL_SHIFT (13U) +#define IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL_MASK (0xE000U) +#define IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL_SHIFT (13U) +#define IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL_MASK) + +#define IOMUXC_GPR_GPR_AWCACHE_PCIE2_MASK (0x4000U) +#define IOMUXC_GPR_GPR_AWCACHE_PCIE2_SHIFT (14U) +/*! AWCACHE_PCIE2 + * 0b0..Drive PCIe AXI Master Port AWCACHE[1] to 0 + * 0b1..Drive PCIe AXI Master Port AWCACHE[1] to 1 + */ +#define IOMUXC_GPR_GPR_AWCACHE_PCIE2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_PCIE2_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_PCIE2_MASK) + +#define IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT_MASK (0x4000U) +#define IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT_SHIFT (14U) +#define IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT_SHIFT)) & IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT_MASK) + +#define IOMUXC_GPR_GPR_DSI_TRIGGER_REQ_MASK (0x4000U) +#define IOMUXC_GPR_GPR_DSI_TRIGGER_REQ_SHIFT (14U) +#define IOMUXC_GPR_GPR_DSI_TRIGGER_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TRIGGER_REQ_SHIFT)) & IOMUXC_GPR_GPR_DSI_TRIGGER_REQ_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB_MASK (0xFC000U) +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB_SHIFT (14U) +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB_MASK (0xFC000U) +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB_SHIFT (14U) +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB_MASK) + +#define IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND_MASK (0x8000U) +#define IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND_SHIFT (15U) +#define IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND_SHIFT)) & IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND_MASK) + +#define IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT_MASK (0x8000U) +#define IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT_SHIFT (15U) +#define IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT_SHIFT)) & IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT_MASK) + +#define IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE_MASK (0x8000U) +#define IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE_SHIFT (15U) +#define IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE_SHIFT)) & IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE_MASK) + +#define IOMUXC_GPR_GPR_CPU_STANDBYWFI_MASK (0xF0000U) +#define IOMUXC_GPR_GPR_CPU_STANDBYWFI_SHIFT (16U) +#define IOMUXC_GPR_GPR_CPU_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CPU_STANDBYWFI_SHIFT)) & IOMUXC_GPR_GPR_CPU_STANDBYWFI_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY_MASK (0x10000U) +#define IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY_SHIFT (16U) +#define IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY_MASK (0x10000U) +#define IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY_SHIFT (16U) +#define IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY_MASK) + +#define IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION_MASK (0x10000U) +#define IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION_SHIFT (16U) +#define IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION_SHIFT)) & IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION_MASK) + +#define IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK_MASK (0x10000U) +#define IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK_SHIFT (16U) +#define IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET_MASK (0x1F0000U) +#define IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET_SHIFT (16U) +#define IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET_MASK (0x1F0000U) +#define IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET_SHIFT (16U) +#define IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET_MASK) + +#define IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG_MASK (0x10000U) +#define IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG_SHIFT (16U) +/*! RDATA_WAIT_EN_PDG + * 0b0..read data wait state control configuration valid + * 0b1..read data wait state control bit changed + */ +#define IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG_SHIFT)) & IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG_MASK) + +#define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK_SHIFT (16U) +/*! SDMA1_IPG_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted, peripheral is in STOP mode + */ +#define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK_MASK) + +#define IOMUXC_GPR_GPR_TZASC_EN_LOCK_MASK (0x10000U) +#define IOMUXC_GPR_GPR_TZASC_EN_LOCK_SHIFT (16U) +#define IOMUXC_GPR_GPR_TZASC_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_TZASC_EN_LOCK_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_CRC_ERR_MASK (0x20000U) +#define IOMUXC_GPR_GPR_CSI2_1_CRC_ERR_SHIFT (17U) +#define IOMUXC_GPR_GPR_CSI2_1_CRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_CRC_ERR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_CRC_ERR_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_CRC_ERR_MASK (0x20000U) +#define IOMUXC_GPR_GPR_CSI2_2_CRC_ERR_SHIFT (17U) +#define IOMUXC_GPR_GPR_CSI2_2_CRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_CRC_ERR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_CRC_ERR_MASK) + +#define IOMUXC_GPR_GPR_DSI_CRC_ERR_MASK (0x20000U) +#define IOMUXC_GPR_GPR_DSI_CRC_ERR_SHIFT (17U) +#define IOMUXC_GPR_GPR_DSI_CRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_CRC_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_CRC_ERR_MASK) + +#define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK_MASK (0x3E0000U) +#define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK_SHIFT (17U) +#define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_MASK (0x1E0000U) +#define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT (17U) +#define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_MASK) + +#define IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG_MASK (0x20000U) +#define IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG_SHIFT (17U) +/*! RADDR_PIPE_EN_PDG + * 0b0..read address pipeline enable configuration valid + * 0b1..read address pipeline enable bit changed + */ +#define IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG_SHIFT)) & IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG_MASK) + +#define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK_MASK (0x20000U) +#define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK_SHIFT (17U) +#define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK_SHIFT)) & IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE_MASK (0x7C0000U) +#define IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE_SHIFT (18U) +#define IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE_MASK (0x7C0000U) +#define IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE_SHIFT (18U) +#define IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_DSI_CALOUT_MASK (0xC0000U) +#define IOMUXC_GPR_GPR_DSI_CALOUT_SHIFT (18U) +#define IOMUXC_GPR_GPR_DSI_CALOUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_CALOUT_SHIFT)) & IOMUXC_GPR_GPR_DSI_CALOUT_MASK) + +#define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK_MASK (0x40000U) +#define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK_SHIFT (18U) +#define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK_MASK) + +#define IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG_MASK (0x40000U) +#define IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG_SHIFT (18U) +/*! WDATA_PIPE_EN_PDG + * 0b0..write data pipeline enable configuration valid + * 0b1..write data pipeline enable bit changed + */ +#define IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG_SHIFT)) & IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG_MASK) + +#define IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK_SHIFT (19U) +/*! ENET1_IPG_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted, peripheral is in STOP mode + */ +#define IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK_MASK) + +#define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK_MASK (0x80000U) +#define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK_SHIFT (19U) +#define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK_MASK) + +#define IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG_MASK (0x80000U) +#define IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG_SHIFT (19U) +/*! WADDR_PIPE_EN_PNDG + * 0b0..write address pipeline enable configuration valid + * 0b1..write address pipeline enable bit changed + */ +#define IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG_MASK) + +#define IOMUXC_GPR_GPR_CPU_STANDBYWFE_MASK (0xF00000U) +#define IOMUXC_GPR_GPR_CPU_STANDBYWFE_SHIFT (20U) +#define IOMUXC_GPR_GPR_CPU_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CPU_STANDBYWFE_SHIFT)) & IOMUXC_GPR_GPR_CPU_STANDBYWFE_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE_MASK (0x100000U) +#define IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE_SHIFT (20U) +#define IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE_MASK (0x100000U) +#define IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE_SHIFT (20U) +#define IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE_MASK (0x100000U) +#define IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE_SHIFT (20U) +#define IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE_MASK (0x100000U) +#define IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE_SHIFT (20U) +#define IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE_MASK (0x100000U) +#define IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE_SHIFT (20U) +#define IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE_MASK (0x100000U) +#define IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE_SHIFT (20U) +#define IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE_MASK (0x100000U) +#define IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE_SHIFT (20U) +#define IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE_MASK (0x100000U) +#define IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE_SHIFT (20U) +#define IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_DSI_CALCOMPL_MASK (0x100000U) +#define IOMUXC_GPR_GPR_DSI_CALCOMPL_SHIFT (20U) +#define IOMUXC_GPR_GPR_DSI_CALCOMPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_CALCOMPL_SHIFT)) & IOMUXC_GPR_GPR_DSI_CALCOMPL_MASK) + +#define IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE_MASK (0x100000U) +#define IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE_SHIFT (20U) +#define IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE_MASK (0x100000U) +#define IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE_SHIFT (20U) +#define IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE_MASK (0x100000U) +#define IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE_SHIFT (20U) +#define IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE_MASK (0x100000U) +#define IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE_SHIFT (20U) +#define IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3F00000U) +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT (20U) +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3F00000U) +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT (20U) +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB_MASK) + +#define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK_SHIFT (20U) +/*! SDMA2_IPG_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted, peripheral is in STOP mode + */ +#define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK_MASK) + +#define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG_MASK (0x100000U) +#define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG_SHIFT (20U) +/*! S_RDATA_WAIT_EN_PNDG + * 0b0..read data wait state control configuration valid + * 0b1..read data wait state control bit changed + */ +#define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG_MASK) + +#define IOMUXC_GPR_GPR_WDOG3_MASK_MASK (0x100000U) +#define IOMUXC_GPR_GPR_WDOG3_MASK_SHIFT (20U) +/*! WDOG3_MASK + * 0b0..WDOG3 Timeout behaves normally + * 0b1..WDOG3 Timeout is masked + */ +#define IOMUXC_GPR_GPR_WDOG3_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDOG3_MASK_SHIFT)) & IOMUXC_GPR_GPR_WDOG3_MASK_MASK) + +#define IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE_MASK (0x3E00000U) +#define IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE_SHIFT (21U) +#define IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_MASK (0x600000U) +#define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_SHIFT (21U) +#define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ_MASK (0xE00000U) +#define IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ_SHIFT (21U) +#define IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ_MASK (0xE00000U) +#define IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ_SHIFT (21U) +#define IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ_MASK) + +#define IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK_SHIFT (21U) +/*! SAI1_IPG_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted, peripheral is in STOP mode + */ +#define IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK_MASK) + +#define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG_MASK (0x200000U) +#define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG_SHIFT (21U) +/*! S_RADDR_PIPE_EN_PNDG + * 0b0..read address pipeline enable configuration valid + * 0b1..read address pipeline enable bit changed + */ +#define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG_MASK) + +#define IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK_SHIFT (22U) +/*! SAI2_IPG_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted, peripheral is in STOP mode + */ +#define IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK_MASK) + +#define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG_MASK (0x400000U) +#define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG_SHIFT (22U) +/*! S_WDATA_PIPE_EN_PNDG + * 0b0..write data pipeline enable configuration valid + * 0b1..write data pipeline enable bit changed + */ +#define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL_MASK (0x800000U) +#define IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL_SHIFT (23U) +#define IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL_MASK (0x800000U) +#define IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL_SHIFT (23U) +#define IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL_MASK) + +#define IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK_SHIFT (23U) +/*! SAI3_IPG_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted, peripheral is in STOP mode + */ +#define IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK_MASK) + +#define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG_MASK (0x800000U) +#define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG_SHIFT (23U) +/*! S_WADDR_PIPE_EN_PNDG + * 0b0..write address pipeline enable configuration valid + * 0b1..write address pipeline enable bit changed + */ +#define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG_MASK) + +#define IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK_MASK (0x800000U) +#define IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT (23U) +/*! TZASC1_SECURE_BOOT_LOCK + * 0b0..Secure boot lock is disabled + * 0b1..Secure boot lock is enabled + */ +#define IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT)) & IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK_MASK) + +#define IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL_MASK (0x1000000U) +#define IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL_SHIFT (24U) +#define IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL_MASK) + +#define IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL_MASK (0x1000000U) +#define IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL_SHIFT (24U) +#define IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL_MASK (0x1F000000U) +#define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL_SHIFT (24U) +#define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL_MASK (0x1F000000U) +#define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL_SHIFT (24U) +#define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL_MASK) + +#define IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK_MASK (0x1000000U) +#define IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK_SHIFT (24U) +/*! SAI4_IPG_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted, peripheral is in STOP mode + */ +#define IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT_MASK (0x1E000000U) +#define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT (25U) +#define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT_MASK) + +#define IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK_MASK (0x2000000U) +#define IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK_SHIFT (25U) +/*! SAI5_IPG_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted, peripheral is in STOP mode + */ +#define IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK_MASK) + +#define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK_MASK (0x4000000U) +#define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK_SHIFT (26U) +#define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1_MASK (0xFC000000U) +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1_SHIFT (26U) +#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1_MASK (0xFC000000U) +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1_SHIFT (26U) +#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1_MASK) + +#define IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK_MASK (0x4000000U) +#define IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK_SHIFT (26U) +/*! SAI6_IPG_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted, peripheral is in STOP mode + */ +#define IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK_MASK) + +#define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK_MASK (0x38000000U) +#define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK_SHIFT (27U) +#define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK_MASK) + +#define IOMUXC_GPR_GPR_DBG_ACK_MASK (0xF0000000U) +#define IOMUXC_GPR_GPR_DBG_ACK_SHIFT (28U) +#define IOMUXC_GPR_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DBG_ACK_SHIFT)) & IOMUXC_GPR_GPR_DBG_ACK_MASK) + +#define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS_MASK (0xE0000000U) +#define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS_SHIFT (29U) +#define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS_MASK (0x60000000U) +#define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS_SHIFT (29U) +#define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS_MASK) + +#define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS_MASK (0xE0000000U) +#define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS_SHIFT (29U) +#define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS_MASK) + +#define IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL_MASK (0x80000000U) +#define IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL_SHIFT (31U) +#define IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL_SHIFT)) & IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL_MASK) +/*! @} */ + +/* The count of IOMUXC_GPR_GPR */ +#define IOMUXC_GPR_GPR_COUNT (48U) + + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Masks */ + + +/* IOMUXC_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_GPR base address */ +#define IOMUXC_GPR_BASE (0x30340000u) +/** Peripheral IOMUXC_GPR base pointer */ +#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) +/** Array initializer of IOMUXC_GPR peripheral base addresses */ +#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } +/** Array initializer of IOMUXC_GPR peripheral base pointers */ +#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } + +/*! + * @} + */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IRQ_STEER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IRQ_STEER_Peripheral_Access_Layer IRQ_STEER Peripheral Access Layer + * @{ + */ + +/** IRQ_STEER - Register Layout Typedef */ +typedef struct { + __IO uint32_t CHANNCTL; /**< Channel n Control Register, offset: 0x0 */ + __IO uint32_t CHN_MASK[16]; /**< Channel n Interrupt Mask Register, array offset: 0x4, array step: 0x4 */ + __IO uint32_t CHN_SET[16]; /**< Channel n Interrupt Set Register, array offset: 0x44, array step: 0x4 */ + __I uint32_t CHN_STATUS[16]; /**< Channel n Interrupt Status Register, array offset: 0x84, array step: 0x4 */ + __IO uint32_t CHN_MINTDIS; /**< Channel n Master Interrupt Disable Register, offset: 0xC4 */ + __I uint32_t CHN_MSTRSTAT; /**< Channel n Master Status Register, offset: 0xC8 */ +} IRQ_STEER_Type; + +/* ---------------------------------------------------------------------------- + -- IRQ_STEER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IRQ_STEER_Register_Masks IRQ_STEER Register Masks + * @{ + */ + +/*! @name CHANNCTL - Channel n Control Register */ +/*! @{ */ + +#define IRQ_STEER_CHANNCTL_CH0_MASK (0x1U) +#define IRQ_STEER_CHANNCTL_CH0_SHIFT (0U) +/*! CH0 - Channel 0 control + * 0b0..Disable channel 0 + * 0b1..Enable channel 0 + */ +#define IRQ_STEER_CHANNCTL_CH0(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH0_SHIFT)) & IRQ_STEER_CHANNCTL_CH0_MASK) + +#define IRQ_STEER_CHANNCTL_CH1_MASK (0x2U) +#define IRQ_STEER_CHANNCTL_CH1_SHIFT (1U) +/*! CH1 - Channel 1 control + * 0b0..Disable channel 1 + * 0b1..Enable channel 1 + */ +#define IRQ_STEER_CHANNCTL_CH1(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH1_SHIFT)) & IRQ_STEER_CHANNCTL_CH1_MASK) + +#define IRQ_STEER_CHANNCTL_CH2_MASK (0x4U) +#define IRQ_STEER_CHANNCTL_CH2_SHIFT (2U) +/*! CH2 - Channel 2 control + * 0b0..Disable channel 2 + * 0b1..Enable channel 2 + */ +#define IRQ_STEER_CHANNCTL_CH2(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH2_SHIFT)) & IRQ_STEER_CHANNCTL_CH2_MASK) + +#define IRQ_STEER_CHANNCTL_CH3_MASK (0x8U) +#define IRQ_STEER_CHANNCTL_CH3_SHIFT (3U) +/*! CH3 - Channel 3 control + * 0b0..Disable channel 3 + * 0b1..Enable channel 3 + */ +#define IRQ_STEER_CHANNCTL_CH3(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH3_SHIFT)) & IRQ_STEER_CHANNCTL_CH3_MASK) + +#define IRQ_STEER_CHANNCTL_CH4_MASK (0x10U) +#define IRQ_STEER_CHANNCTL_CH4_SHIFT (4U) +/*! CH4 - Channel 4 control + * 0b0..Disable channel 4 + * 0b1..Enable channel 4 + */ +#define IRQ_STEER_CHANNCTL_CH4(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH4_SHIFT)) & IRQ_STEER_CHANNCTL_CH4_MASK) +/*! @} */ + +/*! @name CHN_MASK - Channel n Interrupt Mask Register */ +/*! @{ */ + +#define IRQ_STEER_CHN_MASK_MASKFLD_MASK (0xFFFFFFFFU) +#define IRQ_STEER_CHN_MASK_MASKFLD_SHIFT (0U) +/*! MASKFLD - Mask bits + * 0b00000000000000000000000000000000..Mask interrupt + * 0b00000000000000000000000000000001..Do not mask interrupt + */ +#define IRQ_STEER_CHN_MASK_MASKFLD(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_MASK_MASKFLD_SHIFT)) & IRQ_STEER_CHN_MASK_MASKFLD_MASK) +/*! @} */ + +/* The count of IRQ_STEER_CHN_MASK */ +#define IRQ_STEER_CHN_MASK_COUNT (16U) + +/*! @name CHN_SET - Channel n Interrupt Set Register */ +/*! @{ */ + +#define IRQ_STEER_CHN_SET_FORCEFLD_MASK (0xFFFFFFFFU) +#define IRQ_STEER_CHN_SET_FORCEFLD_SHIFT (0U) +/*! FORCEFLD - Brief bitfield description. + * 0b00000000000000000000000000000000..Normal operation + * 0b00000000000000000000000000000001..Force interrupt + */ +#define IRQ_STEER_CHN_SET_FORCEFLD(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_SET_FORCEFLD_SHIFT)) & IRQ_STEER_CHN_SET_FORCEFLD_MASK) +/*! @} */ + +/* The count of IRQ_STEER_CHN_SET */ +#define IRQ_STEER_CHN_SET_COUNT (16U) + +/*! @name CHN_STATUS - Channel n Interrupt Status Register */ +/*! @{ */ + +#define IRQ_STEER_CHN_STATUS_STATUS_MASK (0xFFFFFFFFU) +#define IRQ_STEER_CHN_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Status of an interrupt + * 0b00000000000000000000000000000000..Interrupt is not set. + * 0b00000000000000000000000000000001..Interrupt is set. + */ +#define IRQ_STEER_CHN_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_STATUS_STATUS_SHIFT)) & IRQ_STEER_CHN_STATUS_STATUS_MASK) +/*! @} */ + +/* The count of IRQ_STEER_CHN_STATUS */ +#define IRQ_STEER_CHN_STATUS_COUNT (16U) + +/*! @name CHN_MINTDIS - Channel n Master Interrupt Disable Register */ +/*! @{ */ + +#define IRQ_STEER_CHN_MINTDIS_DISABLE_MASK (0xFFU) +#define IRQ_STEER_CHN_MINTDIS_DISABLE_SHIFT (0U) +/*! DISABLE - Each bit of this field disables the corresponding interrupts in table above. + * 0b00000000..Enable interrupts + * 0b00000001..Disable interrupts + */ +#define IRQ_STEER_CHN_MINTDIS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_MINTDIS_DISABLE_SHIFT)) & IRQ_STEER_CHN_MINTDIS_DISABLE_MASK) +/*! @} */ + +/*! @name CHN_MSTRSTAT - Channel n Master Status Register */ +/*! @{ */ + +#define IRQ_STEER_CHN_MSTRSTAT_STATUS_MASK (0x1U) +#define IRQ_STEER_CHN_MSTRSTAT_STATUS_SHIFT (0U) +/*! STATUS - Status of all interrupts + * 0b0..No interrupts are asserted. + * 0b1..At least one interrupt is asserted. + */ +#define IRQ_STEER_CHN_MSTRSTAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_MSTRSTAT_STATUS_SHIFT)) & IRQ_STEER_CHN_MSTRSTAT_STATUS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IRQ_STEER_Register_Masks */ + + +/* IRQ_STEER - Peripheral instance base addresses */ +/** Peripheral IRQ_STEER base address */ +#define IRQ_STEER_BASE (0x32E2D000u) +/** Peripheral IRQ_STEER base pointer */ +#define IRQ_STEER ((IRQ_STEER_Type *)IRQ_STEER_BASE) +/** Array initializer of IRQ_STEER peripheral base addresses */ +#define IRQ_STEER_BASE_ADDRS { IRQ_STEER_BASE } +/** Array initializer of IRQ_STEER peripheral base pointers */ +#define IRQ_STEER_BASE_PTRS { IRQ_STEER } + +/*! + * @} + */ /* end of group IRQ_STEER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LCDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer + * @{ + */ + +/** LCDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */ + __IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */ + __IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */ + __IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t TIMING; /**< LCD Interface Timing Register, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ + __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ + __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ + __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ + __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ + uint8_t RESERVED_4[12]; + __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ + uint8_t RESERVED_5[12]; + __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ + uint8_t RESERVED_6[12]; + __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DVICTRL0; /**< Digital Video Interface Control0 Register, offset: 0xC0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t DVICTRL1; /**< Digital Video Interface Control1 Register, offset: 0xD0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t DVICTRL2; /**< Digital Video Interface Control2 Register, offset: 0xE0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t DVICTRL3; /**< Digital Video Interface Control3 Register, offset: 0xF0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t DVICTRL4; /**< Digital Video Interface Control4 Register, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CSC_COEFF0; /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CSC_COEFF1; /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CSC_COEFF2; /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CSC_COEFF3; /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CSC_COEFF4; /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CSC_OFFSET; /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CSC_LIMIT; /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */ + uint8_t RESERVED_19[12]; + __IO uint32_t DATA; /**< LCD Interface Data Register, offset: 0x180 */ + uint8_t RESERVED_20[12]; + __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ + uint8_t RESERVED_22[12]; + __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ + uint8_t RESERVED_23[76]; + __IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */ + uint8_t RESERVED_24[12]; + __IO uint32_t AS_CTRL; /**< LCDIF AS Buffer Control Register, offset: 0x210 */ + uint8_t RESERVED_25[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x220 */ + uint8_t RESERVED_26[12]; + __IO uint32_t AS_NEXT_BUF; /**< , offset: 0x230 */ + uint8_t RESERVED_27[12]; + __IO uint32_t AS_CLRKEYLOW; /**< LCDIF Overlay Color Key Low, offset: 0x240 */ + uint8_t RESERVED_28[12]; + __IO uint32_t AS_CLRKEYHIGH; /**< LCDIF Overlay Color Key High, offset: 0x250 */ + uint8_t RESERVED_29[12]; + __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */ +} LCDIF_Type; + +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/*! @name CTRL - LCDIF General Control Register */ +/*! @{ */ + +#define LCDIF_CTRL_RUN_MASK (0x1U) +#define LCDIF_CTRL_RUN_SHIFT (0U) +#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) + +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in + * each byte do not contain any useful data, and should be dropped. + */ +#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) + +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ +#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) + +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) + +#define LCDIF_CTRL_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) + +#define LCDIF_CTRL_MASTER_MASK (0x20U) +#define LCDIF_CTRL_MASTER_SHIFT (5U) +#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) + +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) + +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK) + +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ +#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) + +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ +#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) + +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) + +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) + +#define LCDIF_CTRL_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_DATA_SELECT_SHIFT (16U) +/*! DATA_SELECT + * 0b0..Command Mode. LCD_RS signal is Low. + * 0b1..Data Mode. LCD_RS signal is High. + */ +#define LCDIF_CTRL_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SELECT_SHIFT)) & LCDIF_CTRL_DATA_SELECT_MASK) + +#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) + +#define LCDIF_CTRL_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_VSYNC_MODE_MASK) + +#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) + +#define LCDIF_CTRL_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DVI_MODE_SHIFT)) & LCDIF_CTRL_DVI_MODE_MASK) + +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) + +#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ +#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) + +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK) + +#define LCDIF_CTRL_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_READ_WRITEB_SHIFT)) & LCDIF_CTRL_READ_WRITEB_MASK) + +#define LCDIF_CTRL_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_YCBCR422_INPUT_MASK) + +#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) + +#define LCDIF_CTRL_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - LCDIF General Control Register */ +/*! @{ */ + +#define LCDIF_CTRL_SET_RUN_MASK (0x1U) +#define LCDIF_CTRL_SET_RUN_SHIFT (0U) +#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) + +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in + * each byte do not contain any useful data, and should be dropped. + */ +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) + +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) + +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) + +#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) + +#define LCDIF_CTRL_SET_MASTER_MASK (0x20U) +#define LCDIF_CTRL_SET_MASTER_SHIFT (5U) +#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) + +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) + +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK) + +#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ +#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) + +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) + +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) + +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) + +#define LCDIF_CTRL_SET_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_SET_DATA_SELECT_SHIFT (16U) +/*! DATA_SELECT + * 0b0..Command Mode. LCD_RS signal is Low. + * 0b1..Data Mode. LCD_RS signal is High. + */ +#define LCDIF_CTRL_SET_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SELECT_SHIFT)) & LCDIF_CTRL_SET_DATA_SELECT_MASK) + +#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) + +#define LCDIF_CTRL_SET_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_SET_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_SET_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_SET_VSYNC_MODE_MASK) + +#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) + +#define LCDIF_CTRL_SET_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_SET_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_SET_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DVI_MODE_SHIFT)) & LCDIF_CTRL_SET_DVI_MODE_MASK) + +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) + +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) + +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK) + +#define LCDIF_CTRL_SET_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_SET_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_SET_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_READ_WRITEB_SHIFT)) & LCDIF_CTRL_SET_READ_WRITEB_MASK) + +#define LCDIF_CTRL_SET_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_SET_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_SET_YCBCR422_INPUT_MASK) + +#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) + +#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - LCDIF General Control Register */ +/*! @{ */ + +#define LCDIF_CTRL_CLR_RUN_MASK (0x1U) +#define LCDIF_CTRL_CLR_RUN_SHIFT (0U) +#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) + +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in + * each byte do not contain any useful data, and should be dropped. + */ +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) + +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) + +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) + +#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) + +#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) +#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) +#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) + +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) + +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK) + +#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ +#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) + +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) + +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) + +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) + +#define LCDIF_CTRL_CLR_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_CLR_DATA_SELECT_SHIFT (16U) +/*! DATA_SELECT + * 0b0..Command Mode. LCD_RS signal is Low. + * 0b1..Data Mode. LCD_RS signal is High. + */ +#define LCDIF_CTRL_CLR_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SELECT_SHIFT)) & LCDIF_CTRL_CLR_DATA_SELECT_MASK) + +#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) + +#define LCDIF_CTRL_CLR_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_CLR_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_CLR_VSYNC_MODE_MASK) + +#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) + +#define LCDIF_CTRL_CLR_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_CLR_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_CLR_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DVI_MODE_SHIFT)) & LCDIF_CTRL_CLR_DVI_MODE_MASK) + +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) + +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) + +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK) + +#define LCDIF_CTRL_CLR_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_CLR_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_CLR_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_READ_WRITEB_SHIFT)) & LCDIF_CTRL_CLR_READ_WRITEB_MASK) + +#define LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK) + +#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) + +#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - LCDIF General Control Register */ +/*! @{ */ + +#define LCDIF_CTRL_TOG_RUN_MASK (0x1U) +#define LCDIF_CTRL_TOG_RUN_SHIFT (0U) +#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) + +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in + * each byte do not contain any useful data, and should be dropped. + */ +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) + +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) + +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) + +#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) + +#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) +#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) +#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) + +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) + +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK) + +#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ +#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) + +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) + +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) + +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) + +#define LCDIF_CTRL_TOG_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_TOG_DATA_SELECT_SHIFT (16U) +/*! DATA_SELECT + * 0b0..Command Mode. LCD_RS signal is Low. + * 0b1..Data Mode. LCD_RS signal is High. + */ +#define LCDIF_CTRL_TOG_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SELECT_SHIFT)) & LCDIF_CTRL_TOG_DATA_SELECT_MASK) + +#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) + +#define LCDIF_CTRL_TOG_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_TOG_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_TOG_VSYNC_MODE_MASK) + +#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) + +#define LCDIF_CTRL_TOG_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_TOG_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_TOG_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DVI_MODE_SHIFT)) & LCDIF_CTRL_TOG_DVI_MODE_MASK) + +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) + +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) + +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK) + +#define LCDIF_CTRL_TOG_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_TOG_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_TOG_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_READ_WRITEB_SHIFT)) & LCDIF_CTRL_TOG_READ_WRITEB_MASK) + +#define LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK) + +#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) + +#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL1 - LCDIF General Control1 Register */ +/*! @{ */ + +#define LCDIF_CTRL1_RESET_MASK (0x1U) +#define LCDIF_CTRL1_RESET_SHIFT (0U) +/*! RESET + * 0b0..LCD_RESET output signal is low. + * 0b1..LCD_RESET output signal is high. + */ +#define LCDIF_CTRL1_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RESET_SHIFT)) & LCDIF_CTRL1_RESET_MASK) + +#define LCDIF_CTRL1_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_MODE86_SHIFT (1U) +/*! MODE86 + * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + */ +#define LCDIF_CTRL1_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_MODE86_SHIFT)) & LCDIF_CTRL1_MODE86_MASK) + +#define LCDIF_CTRL1_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_BUSY_ENABLE_SHIFT (2U) +/*! BUSY_ENABLE + * 0b0..The busy signal from the LCD controller will be ignored. + * 0b1..Enable the use of the busy signal from the LCD controller. + */ +#define LCDIF_CTRL1_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_BUSY_ENABLE_MASK) + +#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) + +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) + +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) + +#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) + +#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) + +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) + +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) + +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) + +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) + +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) + +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) + +#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) + +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) + +#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) + +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) + +#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) + +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) + +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK) +/*! @} */ + +/*! @name CTRL1_SET - LCDIF General Control1 Register */ +/*! @{ */ + +#define LCDIF_CTRL1_SET_RESET_MASK (0x1U) +#define LCDIF_CTRL1_SET_RESET_SHIFT (0U) +/*! RESET + * 0b0..LCD_RESET output signal is low. + * 0b1..LCD_RESET output signal is high. + */ +#define LCDIF_CTRL1_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RESET_SHIFT)) & LCDIF_CTRL1_SET_RESET_MASK) + +#define LCDIF_CTRL1_SET_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_SET_MODE86_SHIFT (1U) +/*! MODE86 + * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + */ +#define LCDIF_CTRL1_SET_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_MODE86_SHIFT)) & LCDIF_CTRL1_SET_MODE86_MASK) + +#define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT (2U) +/*! BUSY_ENABLE + * 0b0..The busy signal from the LCD controller will be ignored. + * 0b1..Enable the use of the busy signal from the LCD controller. + */ +#define LCDIF_CTRL1_SET_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_SET_BUSY_ENABLE_MASK) + +#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) + +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) + +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) + +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) + +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) + +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) + +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) + +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) + +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) + +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) + +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) + +#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) + +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) + +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) + +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) + +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) + +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) + +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK) +/*! @} */ + +/*! @name CTRL1_CLR - LCDIF General Control1 Register */ +/*! @{ */ + +#define LCDIF_CTRL1_CLR_RESET_MASK (0x1U) +#define LCDIF_CTRL1_CLR_RESET_SHIFT (0U) +/*! RESET + * 0b0..LCD_RESET output signal is low. + * 0b1..LCD_RESET output signal is high. + */ +#define LCDIF_CTRL1_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RESET_SHIFT)) & LCDIF_CTRL1_CLR_RESET_MASK) + +#define LCDIF_CTRL1_CLR_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_CLR_MODE86_SHIFT (1U) +/*! MODE86 + * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + */ +#define LCDIF_CTRL1_CLR_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_MODE86_SHIFT)) & LCDIF_CTRL1_CLR_MODE86_MASK) + +#define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT (2U) +/*! BUSY_ENABLE + * 0b0..The busy signal from the LCD controller will be ignored. + * 0b1..Enable the use of the busy signal from the LCD controller. + */ +#define LCDIF_CTRL1_CLR_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK) + +#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) + +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) + +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) + +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) + +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) + +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) + +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) + +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) + +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) + +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) + +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) + +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) + +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) + +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) + +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) + +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) + +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) + +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK) +/*! @} */ + +/*! @name CTRL1_TOG - LCDIF General Control1 Register */ +/*! @{ */ + +#define LCDIF_CTRL1_TOG_RESET_MASK (0x1U) +#define LCDIF_CTRL1_TOG_RESET_SHIFT (0U) +/*! RESET + * 0b0..LCD_RESET output signal is low. + * 0b1..LCD_RESET output signal is high. + */ +#define LCDIF_CTRL1_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RESET_SHIFT)) & LCDIF_CTRL1_TOG_RESET_MASK) + +#define LCDIF_CTRL1_TOG_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_TOG_MODE86_SHIFT (1U) +/*! MODE86 + * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + */ +#define LCDIF_CTRL1_TOG_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_MODE86_SHIFT)) & LCDIF_CTRL1_TOG_MODE86_MASK) + +#define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT (2U) +/*! BUSY_ENABLE + * 0b0..The busy signal from the LCD controller will be ignored. + * 0b1..Enable the use of the busy signal from the LCD controller. + */ +#define LCDIF_CTRL1_TOG_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK) + +#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) + +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) + +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) + +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) + +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) + +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) + +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) + +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) + +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) + +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) + +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) + +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) + +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) + +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) + +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) + +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) + +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) + +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK) +/*! @} */ + +/*! @name CTRL2 - LCDIF General Control2 Register */ +/*! @{ */ + +#define LCDIF_CTRL2_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) + +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK) + +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK) + +#define LCDIF_CTRL2_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD1_SHIFT)) & LCDIF_CTRL2_RSRVD1_MASK) + +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK) + +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) + +#define LCDIF_CTRL2_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_READ_PACK_DIR_MASK) + +#define LCDIF_CTRL2_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD2_SHIFT)) & LCDIF_CTRL2_RSRVD2_MASK) + +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) + +#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) + +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) + +#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) + +#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) + +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ +#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) + +#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) +/*! @} */ + +/*! @name CTRL2_SET - LCDIF General Control2 Register */ +/*! @{ */ + +#define LCDIF_CTRL2_SET_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) + +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK) + +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK) + +#define LCDIF_CTRL2_SET_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_SET_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD1_SHIFT)) & LCDIF_CTRL2_SET_RSRVD1_MASK) + +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK) + +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) + +#define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_SET_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_SET_READ_PACK_DIR_MASK) + +#define LCDIF_CTRL2_SET_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_SET_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD2_SHIFT)) & LCDIF_CTRL2_SET_RSRVD2_MASK) + +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) + +#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) + +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) + +#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) + +#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) + +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) + +#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) +/*! @} */ + +/*! @name CTRL2_CLR - LCDIF General Control2 Register */ +/*! @{ */ + +#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) + +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK) + +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK) + +#define LCDIF_CTRL2_CLR_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_CLR_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD1_MASK) + +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK) + +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) + +#define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK) + +#define LCDIF_CTRL2_CLR_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_CLR_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD2_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD2_MASK) + +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) + +#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) + +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) + +#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) + +#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) + +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) + +#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) +/*! @} */ + +/*! @name CTRL2_TOG - LCDIF General Control2 Register */ +/*! @{ */ + +#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) + +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK) + +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK) + +#define LCDIF_CTRL2_TOG_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_TOG_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD1_MASK) + +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK) + +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) + +#define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK) + +#define LCDIF_CTRL2_TOG_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_TOG_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD2_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD2_MASK) + +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) + +#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) + +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) + +#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) + +#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) + +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) + +#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) +/*! @} */ + +/*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ +/*! @{ */ + +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) +#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) +#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) + +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) +#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) +#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) +/*! @} */ + +/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ +/*! @{ */ + +#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_CUR_BUF_ADDR_SHIFT (0U) +#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) +/*! @} */ + +/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ +/*! @{ */ + +#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) +/*! @} */ + +/*! @name TIMING - LCD Interface Timing Register */ +/*! @{ */ + +#define LCDIF_TIMING_DATA_SETUP_MASK (0xFFU) +#define LCDIF_TIMING_DATA_SETUP_SHIFT (0U) +#define LCDIF_TIMING_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_SETUP_SHIFT)) & LCDIF_TIMING_DATA_SETUP_MASK) + +#define LCDIF_TIMING_DATA_HOLD_MASK (0xFF00U) +#define LCDIF_TIMING_DATA_HOLD_SHIFT (8U) +#define LCDIF_TIMING_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_HOLD_SHIFT)) & LCDIF_TIMING_DATA_HOLD_MASK) + +#define LCDIF_TIMING_CMD_SETUP_MASK (0xFF0000U) +#define LCDIF_TIMING_CMD_SETUP_SHIFT (16U) +#define LCDIF_TIMING_CMD_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_SETUP_SHIFT)) & LCDIF_TIMING_CMD_SETUP_MASK) + +#define LCDIF_TIMING_CMD_HOLD_MASK (0xFF000000U) +#define LCDIF_TIMING_CMD_HOLD_SHIFT (24U) +#define LCDIF_TIMING_CMD_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_HOLD_SHIFT)) & LCDIF_TIMING_CMD_HOLD_MASK) +/*! @} */ + +/*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ + +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) + +#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) + +#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) + +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) + +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) + +#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) + +#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) + +#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) + +#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) + +#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) + +#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) + +#define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U) +/*! VSYNC_OEB + * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. + * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + */ +#define LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK) + +#define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ + +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) + +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) + +#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) + +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) + +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) + +#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) + +#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) + +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) + +#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) + +#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) + +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) + +#define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U) +/*! VSYNC_OEB + * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. + * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + */ +#define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK) + +#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ + +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) + +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) + +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) + +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) + +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) + +#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) + +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) + +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) + +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) + +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) + +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) + +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U) +/*! VSYNC_OEB + * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. + * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + */ +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK) + +#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ + +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) + +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) + +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) + +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) + +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) + +#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) + +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) + +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) + +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) + +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) + +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) + +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U) +/*! VSYNC_OEB + * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. + * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + */ +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK) + +#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ +/*! @{ */ + +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) +#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) +/*! @} */ + +/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ +/*! @{ */ + +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) +#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) + +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) +/*! @} */ + +/*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ +/*! @{ */ + +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) + +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) + +#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) +#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) +#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) + +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) + +#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) +#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) +/*! @} */ + +/*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ +/*! @{ */ + +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) + +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) + +#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) +#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) +#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) + +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) +/*! @} */ + +/*! @name DVICTRL0 - Digital Video Interface Control0 Register */ +/*! @{ */ + +#define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK (0xFFFU) +#define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT (0U) +#define LCDIF_DVICTRL0_H_BLANKING_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT)) & LCDIF_DVICTRL0_H_BLANKING_CNT_MASK) + +#define LCDIF_DVICTRL0_RSRVD0_MASK (0xF000U) +#define LCDIF_DVICTRL0_RSRVD0_SHIFT (12U) +#define LCDIF_DVICTRL0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD0_SHIFT)) & LCDIF_DVICTRL0_RSRVD0_MASK) + +#define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK (0xFFF0000U) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT (16U) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT)) & LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK) + +#define LCDIF_DVICTRL0_RSRVD1_MASK (0xF0000000U) +#define LCDIF_DVICTRL0_RSRVD1_SHIFT (28U) +#define LCDIF_DVICTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD1_SHIFT)) & LCDIF_DVICTRL0_RSRVD1_MASK) +/*! @} */ + +/*! @name DVICTRL1 - Digital Video Interface Control1 Register */ +/*! @{ */ + +#define LCDIF_DVICTRL1_F2_START_LINE_MASK (0x3FFU) +#define LCDIF_DVICTRL1_F2_START_LINE_SHIFT (0U) +#define LCDIF_DVICTRL1_F2_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F2_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F2_START_LINE_MASK) + +#define LCDIF_DVICTRL1_F1_END_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL1_F1_END_LINE_SHIFT (10U) +#define LCDIF_DVICTRL1_F1_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_END_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_END_LINE_MASK) + +#define LCDIF_DVICTRL1_F1_START_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL1_F1_START_LINE_SHIFT (20U) +#define LCDIF_DVICTRL1_F1_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_START_LINE_MASK) + +#define LCDIF_DVICTRL1_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL1_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_RSRVD0_SHIFT)) & LCDIF_DVICTRL1_RSRVD0_MASK) +/*! @} */ + +/*! @name DVICTRL2 - Digital Video Interface Control2 Register */ +/*! @{ */ + +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK (0x3FFU) +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT (0U) +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK) + +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT (10U) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK) + +#define LCDIF_DVICTRL2_F2_END_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL2_F2_END_LINE_SHIFT (20U) +#define LCDIF_DVICTRL2_F2_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_F2_END_LINE_SHIFT)) & LCDIF_DVICTRL2_F2_END_LINE_MASK) + +#define LCDIF_DVICTRL2_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL2_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_RSRVD0_SHIFT)) & LCDIF_DVICTRL2_RSRVD0_MASK) +/*! @} */ + +/*! @name DVICTRL3 - Digital Video Interface Control3 Register */ +/*! @{ */ + +#define LCDIF_DVICTRL3_V_LINES_CNT_MASK (0x3FFU) +#define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT (0U) +#define LCDIF_DVICTRL3_V_LINES_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V_LINES_CNT_SHIFT)) & LCDIF_DVICTRL3_V_LINES_CNT_MASK) + +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT (10U) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK) + +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT (20U) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK) + +#define LCDIF_DVICTRL3_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_RSRVD0_SHIFT)) & LCDIF_DVICTRL3_RSRVD0_MASK) +/*! @} */ + +/*! @name DVICTRL4 - Digital Video Interface Control4 Register */ +/*! @{ */ + +#define LCDIF_DVICTRL4_H_FILL_CNT_MASK (0xFFU) +#define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT (0U) +#define LCDIF_DVICTRL4_H_FILL_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_H_FILL_CNT_SHIFT)) & LCDIF_DVICTRL4_H_FILL_CNT_MASK) + +#define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK (0xFF00U) +#define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT (8U) +#define LCDIF_DVICTRL4_CR_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CR_FILL_VALUE_MASK) + +#define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK (0xFF0000U) +#define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT (16U) +#define LCDIF_DVICTRL4_CB_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CB_FILL_VALUE_MASK) + +#define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK (0xFF000000U) +#define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT (24U) +#define LCDIF_DVICTRL4_Y_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_Y_FILL_VALUE_MASK) +/*! @} */ + +/*! @name CSC_COEFF0 - RGB to YCbCr 4:2:2 CSC Coefficient0 Register */ +/*! @{ */ + +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK (0x3U) +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT (0U) +/*! CSC_SUBSAMPLE_FILTER + * 0b00..No filtering, simply keep every chroma value for samples numbered 2n and discard chroma values associated with all samples numbered 2n+1. + * 0b01..Reserved + * 0b10..Chroma samples numbered 2n and 2n+1 are averaged (weights 1/2, 1/2) and that chroma value replaces the + * two chroma values at 2n and 2n+1. This chroma now exists horizontally halfway between the two luma samples. + * 0b11..Chroma samples numbered 2n-1, 2n, and 2n+1 are averaged (weights 1/4, 1/2, 1/4) and that chroma value + * exists at the same site as the luma sample numbered 2n and the chroma samples at 2n+1 are discarded. + */ +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT)) & LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK) + +#define LCDIF_CSC_COEFF0_RSRVD0_MASK (0xFFFCU) +#define LCDIF_CSC_COEFF0_RSRVD0_SHIFT (2U) +#define LCDIF_CSC_COEFF0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD0_MASK) + +#define LCDIF_CSC_COEFF0_C0_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF0_C0_SHIFT (16U) +#define LCDIF_CSC_COEFF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_C0_SHIFT)) & LCDIF_CSC_COEFF0_C0_MASK) + +#define LCDIF_CSC_COEFF0_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF0_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD1_MASK) +/*! @} */ + +/*! @name CSC_COEFF1 - RGB to YCbCr 4:2:2 CSC Coefficient1 Register */ +/*! @{ */ + +#define LCDIF_CSC_COEFF1_C1_MASK (0x3FFU) +#define LCDIF_CSC_COEFF1_C1_SHIFT (0U) +#define LCDIF_CSC_COEFF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C1_SHIFT)) & LCDIF_CSC_COEFF1_C1_MASK) + +#define LCDIF_CSC_COEFF1_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF1_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD0_MASK) + +#define LCDIF_CSC_COEFF1_C2_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF1_C2_SHIFT (16U) +#define LCDIF_CSC_COEFF1_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C2_SHIFT)) & LCDIF_CSC_COEFF1_C2_MASK) + +#define LCDIF_CSC_COEFF1_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF1_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF1_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD1_MASK) +/*! @} */ + +/*! @name CSC_COEFF2 - RGB to YCbCr 4:2:2 CSC Coefficent2 Register */ +/*! @{ */ + +#define LCDIF_CSC_COEFF2_C3_MASK (0x3FFU) +#define LCDIF_CSC_COEFF2_C3_SHIFT (0U) +#define LCDIF_CSC_COEFF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C3_SHIFT)) & LCDIF_CSC_COEFF2_C3_MASK) + +#define LCDIF_CSC_COEFF2_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF2_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD0_MASK) + +#define LCDIF_CSC_COEFF2_C4_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF2_C4_SHIFT (16U) +#define LCDIF_CSC_COEFF2_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C4_SHIFT)) & LCDIF_CSC_COEFF2_C4_MASK) + +#define LCDIF_CSC_COEFF2_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF2_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD1_MASK) +/*! @} */ + +/*! @name CSC_COEFF3 - RGB to YCbCr 4:2:2 CSC Coefficient3 Register */ +/*! @{ */ + +#define LCDIF_CSC_COEFF3_C5_MASK (0x3FFU) +#define LCDIF_CSC_COEFF3_C5_SHIFT (0U) +#define LCDIF_CSC_COEFF3_C5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C5_SHIFT)) & LCDIF_CSC_COEFF3_C5_MASK) + +#define LCDIF_CSC_COEFF3_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF3_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD0_MASK) + +#define LCDIF_CSC_COEFF3_C6_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF3_C6_SHIFT (16U) +#define LCDIF_CSC_COEFF3_C6(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C6_SHIFT)) & LCDIF_CSC_COEFF3_C6_MASK) + +#define LCDIF_CSC_COEFF3_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF3_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF3_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD1_MASK) +/*! @} */ + +/*! @name CSC_COEFF4 - RGB to YCbCr 4:2:2 CSC Coefficient4 Register */ +/*! @{ */ + +#define LCDIF_CSC_COEFF4_C7_MASK (0x3FFU) +#define LCDIF_CSC_COEFF4_C7_SHIFT (0U) +#define LCDIF_CSC_COEFF4_C7(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C7_SHIFT)) & LCDIF_CSC_COEFF4_C7_MASK) + +#define LCDIF_CSC_COEFF4_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF4_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD0_MASK) + +#define LCDIF_CSC_COEFF4_C8_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF4_C8_SHIFT (16U) +#define LCDIF_CSC_COEFF4_C8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C8_SHIFT)) & LCDIF_CSC_COEFF4_C8_MASK) + +#define LCDIF_CSC_COEFF4_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF4_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF4_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD1_MASK) +/*! @} */ + +/*! @name CSC_OFFSET - RGB to YCbCr 4:2:2 CSC Offset Register */ +/*! @{ */ + +#define LCDIF_CSC_OFFSET_Y_OFFSET_MASK (0x1FFU) +#define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT (0U) +#define LCDIF_CSC_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_Y_OFFSET_MASK) + +#define LCDIF_CSC_OFFSET_RSRVD0_MASK (0xFE00U) +#define LCDIF_CSC_OFFSET_RSRVD0_SHIFT (9U) +#define LCDIF_CSC_OFFSET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD0_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD0_MASK) + +#define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK (0x1FF0000U) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT (16U) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK) + +#define LCDIF_CSC_OFFSET_RSRVD1_MASK (0xFE000000U) +#define LCDIF_CSC_OFFSET_RSRVD1_SHIFT (25U) +#define LCDIF_CSC_OFFSET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD1_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD1_MASK) +/*! @} */ + +/*! @name CSC_LIMIT - RGB to YCbCr 4:2:2 CSC Limit Register */ +/*! @{ */ + +#define LCDIF_CSC_LIMIT_Y_MAX_MASK (0xFFU) +#define LCDIF_CSC_LIMIT_Y_MAX_SHIFT (0U) +#define LCDIF_CSC_LIMIT_Y_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MAX_SHIFT)) & LCDIF_CSC_LIMIT_Y_MAX_MASK) + +#define LCDIF_CSC_LIMIT_Y_MIN_MASK (0xFF00U) +#define LCDIF_CSC_LIMIT_Y_MIN_SHIFT (8U) +#define LCDIF_CSC_LIMIT_Y_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MIN_SHIFT)) & LCDIF_CSC_LIMIT_Y_MIN_MASK) + +#define LCDIF_CSC_LIMIT_CBCR_MAX_MASK (0xFF0000U) +#define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT (16U) +#define LCDIF_CSC_LIMIT_CBCR_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MAX_MASK) + +#define LCDIF_CSC_LIMIT_CBCR_MIN_MASK (0xFF000000U) +#define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT (24U) +#define LCDIF_CSC_LIMIT_CBCR_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MIN_MASK) +/*! @} */ + +/*! @name DATA - LCD Interface Data Register */ +/*! @{ */ + +#define LCDIF_DATA_DATA_ZERO_MASK (0xFFU) +#define LCDIF_DATA_DATA_ZERO_SHIFT (0U) +#define LCDIF_DATA_DATA_ZERO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ZERO_SHIFT)) & LCDIF_DATA_DATA_ZERO_MASK) + +#define LCDIF_DATA_DATA_ONE_MASK (0xFF00U) +#define LCDIF_DATA_DATA_ONE_SHIFT (8U) +#define LCDIF_DATA_DATA_ONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ONE_SHIFT)) & LCDIF_DATA_DATA_ONE_MASK) + +#define LCDIF_DATA_DATA_TWO_MASK (0xFF0000U) +#define LCDIF_DATA_DATA_TWO_SHIFT (16U) +#define LCDIF_DATA_DATA_TWO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_TWO_SHIFT)) & LCDIF_DATA_DATA_TWO_MASK) + +#define LCDIF_DATA_DATA_THREE_MASK (0xFF000000U) +#define LCDIF_DATA_DATA_THREE_SHIFT (24U) +#define LCDIF_DATA_DATA_THREE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_THREE_SHIFT)) & LCDIF_DATA_DATA_THREE_MASK) +/*! @} */ + +/*! @name BM_ERROR_STAT - Bus Master Error Status Register */ +/*! @{ */ + +#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) +#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) +/*! @} */ + +/*! @name CRC_STAT - CRC Status Register */ +/*! @{ */ + +#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) +#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) +#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) +/*! @} */ + +/*! @name STAT - LCD Interface Status Register */ +/*! @{ */ + +#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) +#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) +#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) + +#define LCDIF_STAT_RSRVD0_MASK (0xFFFE00U) +#define LCDIF_STAT_RSRVD0_SHIFT (9U) +#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) + +#define LCDIF_STAT_DVI_CURRENT_FIELD_MASK (0x1000000U) +#define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT (24U) +#define LCDIF_STAT_DVI_CURRENT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT)) & LCDIF_STAT_DVI_CURRENT_FIELD_MASK) + +#define LCDIF_STAT_BUSY_MASK (0x2000000U) +#define LCDIF_STAT_BUSY_SHIFT (25U) +#define LCDIF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_BUSY_SHIFT)) & LCDIF_STAT_BUSY_MASK) + +#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) +#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) +#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) + +#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) +#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) +#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) + +#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) +#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) +#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) + +#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) +#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) +#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) + +#define LCDIF_STAT_PRESENT_MASK (0x80000000U) +#define LCDIF_STAT_PRESENT_SHIFT (31U) +#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) +/*! @} */ + +/*! @name THRES - LCDIF Threshold Register */ +/*! @{ */ + +#define LCDIF_THRES_PANIC_MASK (0x1FFU) +#define LCDIF_THRES_PANIC_SHIFT (0U) +#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) + +#define LCDIF_THRES_RSRVD1_MASK (0xFE00U) +#define LCDIF_THRES_RSRVD1_SHIFT (9U) +#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) + +#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) +#define LCDIF_THRES_FASTCLOCK_SHIFT (16U) +#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) + +#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) +#define LCDIF_THRES_RSRVD2_SHIFT (25U) +#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) +/*! @} */ + +/*! @name AS_CTRL - LCDIF AS Buffer Control Register */ +/*! @{ */ + +#define LCDIF_AS_CTRL_AS_ENABLE_MASK (0x1U) +#define LCDIF_AS_CTRL_AS_ENABLE_SHIFT (0U) +#define LCDIF_AS_CTRL_AS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_AS_ENABLE_SHIFT)) & LCDIF_AS_CTRL_AS_ENABLE_MASK) + +#define LCDIF_AS_CTRL_ALPHA_CTRL_MASK (0x6U) +#define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT (1U) +#define LCDIF_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT)) & LCDIF_AS_CTRL_ALPHA_CTRL_MASK) + +#define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK) + +#define LCDIF_AS_CTRL_FORMAT_MASK (0xF0U) +#define LCDIF_AS_CTRL_FORMAT_SHIFT (4U) +#define LCDIF_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_FORMAT_SHIFT)) & LCDIF_AS_CTRL_FORMAT_MASK) + +#define LCDIF_AS_CTRL_ALPHA_MASK (0xFF00U) +#define LCDIF_AS_CTRL_ALPHA_SHIFT (8U) +#define LCDIF_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_SHIFT)) & LCDIF_AS_CTRL_ALPHA_MASK) + +#define LCDIF_AS_CTRL_ROP_MASK (0xF0000U) +#define LCDIF_AS_CTRL_ROP_SHIFT (16U) +#define LCDIF_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ROP_SHIFT)) & LCDIF_AS_CTRL_ROP_MASK) + +#define LCDIF_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) +#define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT (20U) +#define LCDIF_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT)) & LCDIF_AS_CTRL_ALPHA_INVERT_MASK) + +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK (0x600000U) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT (21U) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK) + +#define LCDIF_AS_CTRL_PS_DISABLE_MASK (0x800000U) +#define LCDIF_AS_CTRL_PS_DISABLE_SHIFT (23U) +#define LCDIF_AS_CTRL_PS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_PS_DISABLE_SHIFT)) & LCDIF_AS_CTRL_PS_DISABLE_MASK) + +#define LCDIF_AS_CTRL_RVDS1_MASK (0x7000000U) +#define LCDIF_AS_CTRL_RVDS1_SHIFT (24U) +#define LCDIF_AS_CTRL_RVDS1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_RVDS1_SHIFT)) & LCDIF_AS_CTRL_RVDS1_MASK) + +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK (0x8000000U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT (27U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) + +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK (0x10000000U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT (28U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) + +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK (0x20000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT (29U) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK) + +#define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK (0x40000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT (30U) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK) + +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK (0x80000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT (31U) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK) +/*! @} */ + +/*! @name AS_BUF - Alpha Surface Buffer Pointer */ +/*! @{ */ + +#define LCDIF_AS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_AS_BUF_ADDR_SHIFT (0U) +#define LCDIF_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_BUF_ADDR_SHIFT)) & LCDIF_AS_BUF_ADDR_MASK) +/*! @} */ + +/*! @name AS_NEXT_BUF - */ +/*! @{ */ + +#define LCDIF_AS_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_AS_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_AS_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_NEXT_BUF_ADDR_SHIFT)) & LCDIF_AS_NEXT_BUF_ADDR_MASK) +/*! @} */ + +/*! @name AS_CLRKEYLOW - LCDIF Overlay Color Key Low */ +/*! @{ */ + +#define LCDIF_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) +#define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT (0U) +#define LCDIF_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYLOW_PIXEL_MASK) + +#define LCDIF_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) +#define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT (24U) +#define LCDIF_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYLOW_RSVD1_MASK) +/*! @} */ + +/*! @name AS_CLRKEYHIGH - LCDIF Overlay Color Key High */ +/*! @{ */ + +#define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) +#define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) +#define LCDIF_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYHIGH_PIXEL_MASK) + +#define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) +#define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) +#define LCDIF_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYHIGH_RSVD1_MASK) +/*! @} */ + +/*! @name SYNC_DELAY - LCD working insync mode with CSI for VSYNC delay */ +/*! @{ */ + +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK (0xFFFFU) +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT (0U) +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK) + +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK (0xFFFF0000U) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT (16U) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LCDIF_Register_Masks */ + + +/* LCDIF - Peripheral instance base addresses */ +/** Peripheral LCDIF base address */ +#define LCDIF_BASE (0x30320000u) +/** Peripheral LCDIF base pointer */ +#define LCDIF ((LCDIF_Type *)LCDIF_BASE) +/** Array initializer of LCDIF peripheral base addresses */ +#define LCDIF_BASE_ADDRS { LCDIF_BASE } +/** Array initializer of LCDIF peripheral base pointers */ +#define LCDIF_BASE_PTRS { LCDIF } + +/*! + * @} + */ /* end of group LCDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LMEM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer + * @{ + */ + +/** LMEM - Register Layout Typedef */ +typedef struct { + __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */ + __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */ + __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */ + __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */ + uint8_t RESERVED_0[2032]; + __IO uint32_t PSCCR; /**< Cache control register, offset: 0x800 */ + __IO uint32_t PSCLCR; /**< Cache line control register, offset: 0x804 */ + __IO uint32_t PSCSAR; /**< Cache search address register, offset: 0x808 */ + __IO uint32_t PSCCVR; /**< Cache read/write value register, offset: 0x80C */ +} LMEM_Type; + +/* ---------------------------------------------------------------------------- + -- LMEM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LMEM_Register_Masks LMEM Register Masks + * @{ + */ + +/*! @name PCCCR - Cache control register */ +/*! @{ */ + +#define LMEM_PCCCR_ENCACHE_MASK (0x1U) +#define LMEM_PCCCR_ENCACHE_SHIFT (0U) +/*! ENCACHE - Cache enable + * 0b0..Cache disabled + * 0b1..Cache enabled + */ +#define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK) + +#define LMEM_PCCCR_ENWRBUF_MASK (0x2U) +#define LMEM_PCCCR_ENWRBUF_SHIFT (1U) +/*! ENWRBUF - Enable Write Buffer + * 0b0..Write buffer disabled + * 0b1..Write buffer enabled + */ +#define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK) + +#define LMEM_PCCCR_PCCR2_MASK (0x4U) +#define LMEM_PCCCR_PCCR2_SHIFT (2U) +/*! PCCR2 - Forces all cacheable spaces to write through + */ +#define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK) + +#define LMEM_PCCCR_PCCR3_MASK (0x8U) +#define LMEM_PCCCR_PCCR3_SHIFT (3U) +/*! PCCR3 - Forces no allocation on cache misses (must also have ACCR2 asserted) + */ +#define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK) + +#define LMEM_PCCCR_INVW0_MASK (0x1000000U) +#define LMEM_PCCCR_INVW0_SHIFT (24U) +/*! INVW0 - Invalidate Way 0 + * 0b0..No operation + * 0b1..When setting the GO bit, invalidate all lines in way 0. + */ +#define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK) + +#define LMEM_PCCCR_PUSHW0_MASK (0x2000000U) +#define LMEM_PCCCR_PUSHW0_SHIFT (25U) +/*! PUSHW0 - Push Way 0 + * 0b0..No operation + * 0b1..When setting the GO bit, push all modified lines in way 0 + */ +#define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK) + +#define LMEM_PCCCR_INVW1_MASK (0x4000000U) +#define LMEM_PCCCR_INVW1_SHIFT (26U) +/*! INVW1 - Invalidate Way 1 + * 0b0..No operation + * 0b1..When setting the GO bit, invalidate all lines in way 1 + */ +#define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK) + +#define LMEM_PCCCR_PUSHW1_MASK (0x8000000U) +#define LMEM_PCCCR_PUSHW1_SHIFT (27U) +/*! PUSHW1 - Push Way 1 + * 0b0..No operation + * 0b1..When setting the GO bit, push all modified lines in way 1 + */ +#define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK) + +#define LMEM_PCCCR_GO_MASK (0x80000000U) +#define LMEM_PCCCR_GO_SHIFT (31U) +/*! GO - Initiate Cache Command + * 0b0..Write: no effect. Read: no cache command active. + * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active. + */ +#define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK) +/*! @} */ + +/*! @name PCCLCR - Cache line control register */ +/*! @{ */ + +#define LMEM_PCCLCR_LGO_MASK (0x1U) +#define LMEM_PCCLCR_LGO_SHIFT (0U) +/*! LGO - Initiate Cache Line Command + * 0b0..Write: no effect. Read: no line command active. + * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active. + */ +#define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK) + +#define LMEM_PCCLCR_CACHEADDR_MASK (0x1FFCU) +#define LMEM_PCCLCR_CACHEADDR_SHIFT (2U) +/*! CACHEADDR - Cache address + */ +#define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK) + +#define LMEM_PCCLCR_WSEL_MASK (0x4000U) +#define LMEM_PCCLCR_WSEL_SHIFT (14U) +/*! WSEL - Way select + * 0b0..Way 0 + * 0b1..Way 1 + */ +#define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK) + +#define LMEM_PCCLCR_TDSEL_MASK (0x10000U) +#define LMEM_PCCLCR_TDSEL_SHIFT (16U) +/*! TDSEL - Tag/Data Select + * 0b0..Data + * 0b1..Tag + */ +#define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK) + +#define LMEM_PCCLCR_LCIVB_MASK (0x100000U) +#define LMEM_PCCLCR_LCIVB_SHIFT (20U) +/*! LCIVB - Line Command Initial Valid Bit + */ +#define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK) + +#define LMEM_PCCLCR_LCIMB_MASK (0x200000U) +#define LMEM_PCCLCR_LCIMB_SHIFT (21U) +/*! LCIMB - Line Command Initial Modified Bit + */ +#define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK) + +#define LMEM_PCCLCR_LCWAY_MASK (0x400000U) +#define LMEM_PCCLCR_LCWAY_SHIFT (22U) +/*! LCWAY - Line Command Way + */ +#define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK) + +#define LMEM_PCCLCR_LCMD_MASK (0x3000000U) +#define LMEM_PCCLCR_LCMD_SHIFT (24U) +/*! LCMD - Line Command + * 0b00..Search and read or write + * 0b01..Invalidate + * 0b10..Push + * 0b11..Clear + */ +#define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK) + +#define LMEM_PCCLCR_LADSEL_MASK (0x4000000U) +#define LMEM_PCCLCR_LADSEL_SHIFT (26U) +/*! LADSEL - Line Address Select + * 0b0..Cache address + * 0b1..Physical address + */ +#define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK) + +#define LMEM_PCCLCR_LACC_MASK (0x8000000U) +#define LMEM_PCCLCR_LACC_SHIFT (27U) +/*! LACC - Line access type + * 0b0..Read + * 0b1..Write + */ +#define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK) +/*! @} */ + +/*! @name PCCSAR - Cache search address register */ +/*! @{ */ + +#define LMEM_PCCSAR_LGO_MASK (0x1U) +#define LMEM_PCCSAR_LGO_SHIFT (0U) +/*! LGO - Initiate Cache Line Command + * 0b0..Write: no effect. Read: no line command active. + * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. + */ +#define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK) + +#define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) +#define LMEM_PCCSAR_PHYADDR_SHIFT (2U) +/*! PHYADDR - Physical Address + */ +#define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK) +/*! @} */ + +/*! @name PCCCVR - Cache read/write value register */ +/*! @{ */ + +#define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU) +#define LMEM_PCCCVR_DATA_SHIFT (0U) +/*! DATA - Cache read/write Data + */ +#define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK) +/*! @} */ + +/*! @name PSCCR - Cache control register */ +/*! @{ */ + +#define LMEM_PSCCR_ENCACHE_MASK (0x1U) +#define LMEM_PSCCR_ENCACHE_SHIFT (0U) +/*! ENCACHE - Cache enable + * 0b0..Cache disabled + * 0b1..Cache enabled + */ +#define LMEM_PSCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENCACHE_SHIFT)) & LMEM_PSCCR_ENCACHE_MASK) + +#define LMEM_PSCCR_ENWRBUF_MASK (0x2U) +#define LMEM_PSCCR_ENWRBUF_SHIFT (1U) +/*! ENWRBUF - Enable Write Buffer + * 0b0..Write buffer disabled + * 0b1..Write buffer enabled + */ +#define LMEM_PSCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENWRBUF_SHIFT)) & LMEM_PSCCR_ENWRBUF_MASK) + +#define LMEM_PSCCR_INVW0_MASK (0x1000000U) +#define LMEM_PSCCR_INVW0_SHIFT (24U) +/*! INVW0 - Invalidate Way 0 + * 0b0..No operation + * 0b1..When setting the GO bit, invalidate all lines in way 0. + */ +#define LMEM_PSCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW0_SHIFT)) & LMEM_PSCCR_INVW0_MASK) + +#define LMEM_PSCCR_PUSHW0_MASK (0x2000000U) +#define LMEM_PSCCR_PUSHW0_SHIFT (25U) +/*! PUSHW0 - Push Way 0 + * 0b0..No operation + * 0b1..When setting the GO bit, push all modified lines in way 0 + */ +#define LMEM_PSCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW0_SHIFT)) & LMEM_PSCCR_PUSHW0_MASK) + +#define LMEM_PSCCR_INVW1_MASK (0x4000000U) +#define LMEM_PSCCR_INVW1_SHIFT (26U) +/*! INVW1 - Invalidate Way 1 + * 0b0..No operation + * 0b1..When setting the GO bit, invalidate all lines in way 1 + */ +#define LMEM_PSCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW1_SHIFT)) & LMEM_PSCCR_INVW1_MASK) + +#define LMEM_PSCCR_PUSHW1_MASK (0x8000000U) +#define LMEM_PSCCR_PUSHW1_SHIFT (27U) +/*! PUSHW1 - Push Way 1 + * 0b0..No operation + * 0b1..When setting the GO bit, push all modified lines in way 1 + */ +#define LMEM_PSCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW1_SHIFT)) & LMEM_PSCCR_PUSHW1_MASK) + +#define LMEM_PSCCR_GO_MASK (0x80000000U) +#define LMEM_PSCCR_GO_SHIFT (31U) +/*! GO - Initiate Cache Command + * 0b0..Write: no effect. Read: no cache command active. + * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active. + */ +#define LMEM_PSCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_GO_SHIFT)) & LMEM_PSCCR_GO_MASK) +/*! @} */ + +/*! @name PSCLCR - Cache line control register */ +/*! @{ */ + +#define LMEM_PSCLCR_LGO_MASK (0x1U) +#define LMEM_PSCLCR_LGO_SHIFT (0U) +/*! LGO - Initiate Cache Line Command + * 0b0..Write: no effect. Read: no line command active. + * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active. + */ +#define LMEM_PSCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LGO_SHIFT)) & LMEM_PSCLCR_LGO_MASK) + +#define LMEM_PSCLCR_CACHEADDR_MASK (0x1FFCU) +#define LMEM_PSCLCR_CACHEADDR_SHIFT (2U) +/*! CACHEADDR - Cache address + */ +#define LMEM_PSCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_CACHEADDR_SHIFT)) & LMEM_PSCLCR_CACHEADDR_MASK) + +#define LMEM_PSCLCR_WSEL_MASK (0x4000U) +#define LMEM_PSCLCR_WSEL_SHIFT (14U) +/*! WSEL - Way select + * 0b0..Way 0 + * 0b1..Way 1 + */ +#define LMEM_PSCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_WSEL_SHIFT)) & LMEM_PSCLCR_WSEL_MASK) + +#define LMEM_PSCLCR_TDSEL_MASK (0x10000U) +#define LMEM_PSCLCR_TDSEL_SHIFT (16U) +/*! TDSEL - Tag/Data Select + * 0b0..Data + * 0b1..Tag + */ +#define LMEM_PSCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_TDSEL_SHIFT)) & LMEM_PSCLCR_TDSEL_MASK) + +#define LMEM_PSCLCR_LCIVB_MASK (0x100000U) +#define LMEM_PSCLCR_LCIVB_SHIFT (20U) +/*! LCIVB - Line Command Initial Valid Bit + */ +#define LMEM_PSCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIVB_SHIFT)) & LMEM_PSCLCR_LCIVB_MASK) + +#define LMEM_PSCLCR_LCIMB_MASK (0x200000U) +#define LMEM_PSCLCR_LCIMB_SHIFT (21U) +/*! LCIMB - Line Command Initial Modified Bit + */ +#define LMEM_PSCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIMB_SHIFT)) & LMEM_PSCLCR_LCIMB_MASK) + +#define LMEM_PSCLCR_LCWAY_MASK (0x400000U) +#define LMEM_PSCLCR_LCWAY_SHIFT (22U) +/*! LCWAY - Line Command Way + */ +#define LMEM_PSCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCWAY_SHIFT)) & LMEM_PSCLCR_LCWAY_MASK) + +#define LMEM_PSCLCR_LCMD_MASK (0x3000000U) +#define LMEM_PSCLCR_LCMD_SHIFT (24U) +/*! LCMD - Line Command + * 0b00..Search and read or write + * 0b01..Invalidate + * 0b10..Push + * 0b11..Clear + */ +#define LMEM_PSCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCMD_SHIFT)) & LMEM_PSCLCR_LCMD_MASK) + +#define LMEM_PSCLCR_LADSEL_MASK (0x4000000U) +#define LMEM_PSCLCR_LADSEL_SHIFT (26U) +/*! LADSEL - Line Address Select + * 0b0..Cache address + * 0b1..Physical address + */ +#define LMEM_PSCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LADSEL_SHIFT)) & LMEM_PSCLCR_LADSEL_MASK) + +#define LMEM_PSCLCR_LACC_MASK (0x8000000U) +#define LMEM_PSCLCR_LACC_SHIFT (27U) +/*! LACC - Line access type + * 0b0..Read + * 0b1..Write + */ +#define LMEM_PSCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LACC_SHIFT)) & LMEM_PSCLCR_LACC_MASK) +/*! @} */ + +/*! @name PSCSAR - Cache search address register */ +/*! @{ */ + +#define LMEM_PSCSAR_LGO_MASK (0x1U) +#define LMEM_PSCSAR_LGO_SHIFT (0U) +/*! LGO - Initiate Cache Line Command + * 0b0..Write: no effect. Read: no line command active. + * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. + */ +#define LMEM_PSCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_LGO_SHIFT)) & LMEM_PSCSAR_LGO_MASK) + +#define LMEM_PSCSAR_PHYADDR_MASK (0xFFFFFFFCU) +#define LMEM_PSCSAR_PHYADDR_SHIFT (2U) +/*! PHYADDR - Physical Address + */ +#define LMEM_PSCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_PHYADDR_SHIFT)) & LMEM_PSCSAR_PHYADDR_MASK) +/*! @} */ + +/*! @name PSCCVR - Cache read/write value register */ +/*! @{ */ + +#define LMEM_PSCCVR_DATA_MASK (0xFFFFFFFFU) +#define LMEM_PSCCVR_DATA_SHIFT (0U) +/*! DATA - Cache read/write Data + */ +#define LMEM_PSCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCVR_DATA_SHIFT)) & LMEM_PSCCVR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LMEM_Register_Masks */ + + +/* LMEM - Peripheral instance base addresses */ +/** Peripheral LMEM base address */ +#define LMEM_BASE (0xE0082000u) +/** Peripheral LMEM base pointer */ +#define LMEM ((LMEM_Type *)LMEM_BASE) +/** Array initializer of LMEM peripheral base addresses */ +#define LMEM_BASE_ADDRS { LMEM_BASE } +/** Array initializer of LMEM peripheral base pointers */ +#define LMEM_BASE_PTRS { LMEM } + +/*! + * @} + */ /* end of group LMEM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LUT_LD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LUT_LD_Peripheral_Access_Layer LUT_LD Peripheral Access Layer + * @{ + */ + +/** LUT_LD - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< Control/Status register for LUT Loader., offset: 0x0 */ + __IO uint32_t SET; /**< Control/Status register for LUT Loader., offset: 0x4 */ + __IO uint32_t CLR; /**< Control/Status register for LUT Loader., offset: 0x8 */ + __IO uint32_t TOG; /**< Control/Status register for LUT Loader., offset: 0xC */ + } CTRL_STATUS; + __IO uint32_t BASE_ADDR; /**< Address for data fetch., offset: 0x10 */ +} LUT_LD_Type; + +/* ---------------------------------------------------------------------------- + -- LUT_LD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LUT_LD_Register_Masks LUT_LD Register Masks + * @{ + */ + +/*! @name CTRL_STATUS - Control/Status register for LUT Loader. */ +/*! @{ */ + +#define LUT_LD_CTRL_STATUS_ENABLE_MASK (0x1U) +#define LUT_LD_CTRL_STATUS_ENABLE_SHIFT (0U) +/*! ENABLE - Enable LUT_LD + */ +#define LUT_LD_CTRL_STATUS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_CTRL_STATUS_ENABLE_SHIFT)) & LUT_LD_CTRL_STATUS_ENABLE_MASK) + +#define LUT_LD_CTRL_STATUS_BYTES_PER_REQ_MASK (0x2U) +#define LUT_LD_CTRL_STATUS_BYTES_PER_REQ_SHIFT (1U) +/*! BYTES_PER_REQ - bytes per request control + */ +#define LUT_LD_CTRL_STATUS_BYTES_PER_REQ(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_CTRL_STATUS_BYTES_PER_REQ_SHIFT)) & LUT_LD_CTRL_STATUS_BYTES_PER_REQ_MASK) + +#define LUT_LD_CTRL_STATUS_RD_ERR_EN_MASK (0x100U) +#define LUT_LD_CTRL_STATUS_RD_ERR_EN_SHIFT (8U) +/*! RD_ERR_EN - AXI Read Error IRQ enable. + */ +#define LUT_LD_CTRL_STATUS_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_CTRL_STATUS_RD_ERR_EN_SHIFT)) & LUT_LD_CTRL_STATUS_RD_ERR_EN_MASK) + +#define LUT_LD_CTRL_STATUS_RD_ERR_MASK (0x10000U) +#define LUT_LD_CTRL_STATUS_RD_ERR_SHIFT (16U) +/*! RD_ERR - AXI Read Error. + */ +#define LUT_LD_CTRL_STATUS_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_CTRL_STATUS_RD_ERR_SHIFT)) & LUT_LD_CTRL_STATUS_RD_ERR_MASK) +/*! @} */ + +/*! @name BASE_ADDR - Address for data fetch. */ +/*! @{ */ + +#define LUT_LD_BASE_ADDR_BASE_ADDR_MASK (0xFFFFFFFFU) +#define LUT_LD_BASE_ADDR_BASE_ADDR_SHIFT (0U) +/*! BASE_ADDR - Base Address + */ +#define LUT_LD_BASE_ADDR_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_BASE_ADDR_BASE_ADDR_SHIFT)) & LUT_LD_BASE_ADDR_BASE_ADDR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LUT_LD_Register_Masks */ + + +/* LUT_LD - Peripheral instance base addresses */ +/** Peripheral DCSS__LUT_LD base address */ +#define DCSS__LUT_LD_BASE (0x32E24000u) +/** Peripheral DCSS__LUT_LD base pointer */ +#define DCSS__LUT_LD ((LUT_LD_Type *)DCSS__LUT_LD_BASE) +/** Array initializer of LUT_LD peripheral base addresses */ +#define LUT_LD_BASE_ADDRS { DCSS__LUT_LD_BASE } +/** Array initializer of LUT_LD peripheral base pointers */ +#define LUT_LD_BASE_PTRS { DCSS__LUT_LD } + +/*! + * @} + */ /* end of group LUT_LD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer + * @{ + */ + +/** MCM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[8]; + __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ + __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ + uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */ + uint8_t RESERVED_1[16]; + __I uint32_t FADR; /**< Fault address register, offset: 0x20 */ + __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */ + __I uint32_t FDR; /**< Fault data register, offset: 0x28 */ +} MCM_Type; + +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ +/*! @{ */ + +#define MCM_PLASC_ASC_MASK (0xFFU) +#define MCM_PLASC_ASC_SHIFT (0U) +/*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the + * crossbar switch's slave input port. + * 0b00000000..A bus slave connection to AXBS input port n is absent + * 0b00000001..A bus slave connection to AXBS input port n is present + */ +#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) +/*! @} */ + +/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ +/*! @{ */ + +#define MCM_PLAMC_AMC_MASK (0xFFU) +#define MCM_PLAMC_AMC_SHIFT (0U) +/*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. + * 0b00000000..A bus master connection to AXBS input port n is absent + * 0b00000001..A bus master connection to AXBS input port n is present + */ +#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) +/*! @} */ + +/*! @name FADR - Fault address register */ +/*! @{ */ + +#define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU) +#define MCM_FADR_ADDRESS_SHIFT (0U) +/*! ADDRESS - Fault address + */ +#define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK) +/*! @} */ + +/*! @name FATR - Fault attributes register */ +/*! @{ */ + +#define MCM_FATR_BEDA_MASK (0x1U) +#define MCM_FATR_BEDA_SHIFT (0U) +/*! BEDA - Bus error access type + * 0b0..Instruction + * 0b1..Data + */ +#define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK) + +#define MCM_FATR_BEMD_MASK (0x2U) +#define MCM_FATR_BEMD_SHIFT (1U) +/*! BEMD - Bus error privilege level + * 0b0..User mode + * 0b1..Supervisor/privileged mode + */ +#define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK) + +#define MCM_FATR_BESZ_MASK (0x30U) +#define MCM_FATR_BESZ_SHIFT (4U) +/*! BESZ - Bus error size + * 0b00..8-bit access + * 0b01..16-bit access + * 0b10..32-bit access + * 0b11..Reserved + */ +#define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK) + +#define MCM_FATR_BEWT_MASK (0x80U) +#define MCM_FATR_BEWT_SHIFT (7U) +/*! BEWT - Bus error write + * 0b0..Read access + * 0b1..Write access + */ +#define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK) + +#define MCM_FATR_BEMN_MASK (0xF00U) +#define MCM_FATR_BEMN_SHIFT (8U) +/*! BEMN - Bus error master number + */ +#define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK) + +#define MCM_FATR_BEOVR_MASK (0x80000000U) +#define MCM_FATR_BEOVR_SHIFT (31U) +/*! BEOVR - Bus error overrun + * 0b0..No bus error overrun + * 0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error. + */ +#define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK) +/*! @} */ + +/*! @name FDR - Fault data register */ +/*! @{ */ + +#define MCM_FDR_DATA_MASK (0xFFFFFFFFU) +#define MCM_FDR_DATA_SHIFT (0U) +/*! DATA - Fault data + */ +#define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MCM_Register_Masks */ + + +/* MCM - Peripheral instance base addresses */ +/** Peripheral MCM base address */ +#define MCM_BASE (0xE0080000u) +/** Peripheral MCM base pointer */ +#define MCM ((MCM_Type *)MCM_BASE) +/** Array initializer of MCM peripheral base addresses */ +#define MCM_BASE_ADDRS { MCM_BASE } +/** Array initializer of MCM peripheral base pointers */ +#define MCM_BASE_PTRS { MCM } + +/*! + * @} + */ /* end of group MCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MED_DC_SCALER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MED_DC_SCALER_Peripheral_Access_Layer MED_DC_SCALER Peripheral Access Layer + * @{ + */ + +/** MED_DC_SCALER - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCALE_CTRL; /**< Scale Control Register, offset: 0x0 */ + __IO uint32_t SCALE_OFIFO_CTRL; /**< Scale Output FIFO Control Register, offset: 0x4 */ + __IO uint32_t SCALE_SRC_DATA_CTRL; /**< Scale Source Data Control Register, offset: 0x8 */ + __IO uint32_t SCALE_BIT_DEPTH; /**< Scale Bit Depth Control Register, offset: 0xC */ + __IO uint32_t SCALE_SRC_FORMAT; /**< Scale Source Format Control Register, offset: 0x10 */ + __IO uint32_t SCALE_DST_FORMAT; /**< Scale Destination Format Control Register, offset: 0x14 */ + __IO uint32_t SCALE_SRC_LUMA_RES; /**< Scale Source Luma Resolution Register, offset: 0x18 */ + __IO uint32_t SCALE_SRC_CHROMA_RES; /**< Scale Source Chroma Resolution Register, offset: 0x1C */ + __IO uint32_t SCALE_DST_LUMA_RES; /**< Scale Destination Luma Resolution Register, offset: 0x20 */ + __IO uint32_t SCALE_DST_CHROMA_RES; /**< Scale Destination Chroma Resolution Register, offset: 0x24 */ + uint8_t RESERVED_0[32]; + __IO uint32_t SCALE_V_LUMA_START; /**< Scale Vertical Luma Start Register, offset: 0x48 */ + __IO uint32_t SCALE_V_LUMA_INC; /**< Scale Vertical Luma Increment Register, offset: 0x4C */ + __IO uint32_t SCALE_H_LUMA_START; /**< Scale Horizontal Luma Start Register, offset: 0x50 */ + __IO uint32_t SCALE_H_LUMA_INC; /**< Scale Horizontal Luma Increment Register, offset: 0x54 */ + __IO uint32_t SCALE_V_CHROMA_START; /**< Scale Vertical Chroma Start Register, offset: 0x58 */ + __IO uint32_t SCALE_V_CHROMA_INC; /**< Scale Vertical Chroma Increment Register, offset: 0x5C */ + __IO uint32_t SCALE_H_CHROMA_START; /**< Scale Horizontal Chroma Start Register, offset: 0x60 */ + __IO uint32_t SCALE_H_CHROMA_INC; /**< Scale Horizontal Chroma Increment Register, offset: 0x64 */ + uint8_t RESERVED_1[24]; + __IO uint32_t SCALE_COEF_ARRAY; /**< Scale Coefficient Memory Array, offset: 0x80 */ +} MED_DC_SCALER_Type; + +/* ---------------------------------------------------------------------------- + -- MED_DC_SCALER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MED_DC_SCALER_Register_Masks MED_DC_SCALER Register Masks + * @{ + */ + +/*! @name SCALE_CTRL - Scale Control Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER_MASK (0x1U) +#define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER_SHIFT (0U) +#define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER_SHIFT)) & MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER_MASK) + +#define MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT_MASK (0x10U) +#define MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT_SHIFT (4U) +#define MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT_SHIFT)) & MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT_MASK) + +#define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM_MASK (0x100U) +#define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM_SHIFT (8U) +#define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM_SHIFT)) & MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM_MASK) + +#define MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO_MASK (0x1000U) +#define MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO_SHIFT (12U) +#define MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO_SHIFT)) & MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO_MASK) +/*! @} */ + +/*! @name SCALE_OFIFO_CTRL - Scale Output FIFO Control Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH_MASK (0x3FFU) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH_SHIFT (0U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH_MASK) + +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH_MASK (0x3FF0000U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH_SHIFT (16U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH_MASK) + +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT_MASK (0x4000000U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT_SHIFT (26U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT_MASK) + +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT_MASK (0x8000000U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT_SHIFT (27U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT_MASK) + +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT_MASK (0x10000000U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT_SHIFT (28U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT_MASK) + +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT_MASK (0x20000000U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT_SHIFT (29U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT_MASK) + +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT_MASK (0x40000000U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT_SHIFT (30U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT_MASK) + +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT_MASK (0x80000000U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT_SHIFT (31U) +#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT_MASK) +/*! @} */ + +/*! @name SCALE_SRC_DATA_CTRL - Scale Source Data Control Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT_MASK (0x1U) +#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT_SHIFT (0U) +#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT_MASK) + +#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK_MASK (0x2U) +#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK_SHIFT (1U) +#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK_SHIFT)) & MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK_MASK) + +#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP_MASK (0x10U) +#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP_SHIFT (4U) +#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP_SHIFT)) & MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP_MASK) + +#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT_MASK (0xF00U) +#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT_SHIFT (8U) +#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT_MASK) +/*! @} */ + +/*! @name SCALE_BIT_DEPTH - Scale Bit Depth Control Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH_MASK (0x3U) +#define MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH_SHIFT (0U) +#define MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH_SHIFT)) & MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH_MASK) + +#define MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH_MASK (0x30U) +#define MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH_SHIFT (4U) +#define MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH_SHIFT)) & MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH_MASK) +/*! @} */ + +/*! @name SCALE_SRC_FORMAT - Scale Source Format Control Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT_MASK (0x3U) +#define MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT_SHIFT (0U) +#define MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT_MASK) +/*! @} */ + +/*! @name SCALE_DST_FORMAT - Scale Destination Format Control Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT_MASK (0x3U) +#define MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT_SHIFT (0U) +#define MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT_SHIFT)) & MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT_MASK) +/*! @} */ + +/*! @name SCALE_SRC_LUMA_RES - Scale Source Luma Resolution Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH_MASK (0xFFFU) +#define MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH_SHIFT (0U) +#define MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH_SHIFT)) & MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH_MASK) + +#define MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT_MASK (0xFFF0000U) +#define MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT_SHIFT (16U) +#define MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT_MASK) +/*! @} */ + +/*! @name SCALE_SRC_CHROMA_RES - Scale Source Chroma Resolution Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH_MASK (0xFFFU) +#define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH_SHIFT (0U) +#define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH_SHIFT)) & MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH_MASK) + +#define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT_MASK (0xFFF0000U) +#define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT_SHIFT (16U) +#define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT_MASK) +/*! @} */ + +/*! @name SCALE_DST_LUMA_RES - Scale Destination Luma Resolution Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH_MASK (0xFFFU) +#define MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH_SHIFT (0U) +#define MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH_SHIFT)) & MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH_MASK) + +#define MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT_MASK (0xFFF0000U) +#define MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT_SHIFT (16U) +#define MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT_SHIFT)) & MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT_MASK) +/*! @} */ + +/*! @name SCALE_DST_CHROMA_RES - Scale Destination Chroma Resolution Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH_MASK (0xFFFU) +#define MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH_SHIFT (0U) +#define MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH_SHIFT)) & MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH_MASK) +/*! @} */ + +/*! @name SCALE_V_LUMA_START - Scale Vertical Luma Start Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_V_LUMA_START_V_START_MASK (0x3FFFFFFU) +#define MED_DC_SCALER_SCALE_V_LUMA_START_V_START_SHIFT (0U) +#define MED_DC_SCALER_SCALE_V_LUMA_START_V_START(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_V_LUMA_START_V_START_SHIFT)) & MED_DC_SCALER_SCALE_V_LUMA_START_V_START_MASK) +/*! @} */ + +/*! @name SCALE_V_LUMA_INC - Scale Vertical Luma Increment Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC_MASK (0xFFFFFU) +#define MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC_SHIFT (0U) +#define MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC_SHIFT)) & MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC_MASK) +/*! @} */ + +/*! @name SCALE_H_LUMA_START - Scale Horizontal Luma Start Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_H_LUMA_START_H_START_MASK (0x3FFFFFFU) +#define MED_DC_SCALER_SCALE_H_LUMA_START_H_START_SHIFT (0U) +#define MED_DC_SCALER_SCALE_H_LUMA_START_H_START(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_H_LUMA_START_H_START_SHIFT)) & MED_DC_SCALER_SCALE_H_LUMA_START_H_START_MASK) +/*! @} */ + +/*! @name SCALE_H_LUMA_INC - Scale Horizontal Luma Increment Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC_MASK (0xFFFFFU) +#define MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC_SHIFT (0U) +#define MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC_SHIFT)) & MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC_MASK) +/*! @} */ + +/*! @name SCALE_V_CHROMA_START - Scale Vertical Chroma Start Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_V_CHROMA_START_V_START_MASK (0x3FFFFFFU) +#define MED_DC_SCALER_SCALE_V_CHROMA_START_V_START_SHIFT (0U) +#define MED_DC_SCALER_SCALE_V_CHROMA_START_V_START(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_V_CHROMA_START_V_START_SHIFT)) & MED_DC_SCALER_SCALE_V_CHROMA_START_V_START_MASK) +/*! @} */ + +/*! @name SCALE_V_CHROMA_INC - Scale Vertical Chroma Increment Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC_MASK (0xFFFFFU) +#define MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC_SHIFT (0U) +#define MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC_SHIFT)) & MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC_MASK) +/*! @} */ + +/*! @name SCALE_H_CHROMA_START - Scale Horizontal Chroma Start Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_H_CHROMA_START_H_START_MASK (0x3FFFFFFU) +#define MED_DC_SCALER_SCALE_H_CHROMA_START_H_START_SHIFT (0U) +#define MED_DC_SCALER_SCALE_H_CHROMA_START_H_START(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_H_CHROMA_START_H_START_SHIFT)) & MED_DC_SCALER_SCALE_H_CHROMA_START_H_START_MASK) +/*! @} */ + +/*! @name SCALE_H_CHROMA_INC - Scale Horizontal Chroma Increment Register */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC_MASK (0xFFFFFU) +#define MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC_SHIFT (0U) +#define MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC_SHIFT)) & MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC_MASK) +/*! @} */ + +/*! @name SCALE_COEF_ARRAY - Scale Coefficient Memory Array */ +/*! @{ */ + +#define MED_DC_SCALER_SCALE_COEF_ARRAY_COEF_MASK (0xFFFU) +#define MED_DC_SCALER_SCALE_COEF_ARRAY_COEF_SHIFT (0U) +#define MED_DC_SCALER_SCALE_COEF_ARRAY_COEF(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_COEF_ARRAY_COEF_SHIFT)) & MED_DC_SCALER_SCALE_COEF_ARRAY_COEF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MED_DC_SCALER_Register_Masks */ + + +/* MED_DC_SCALER - Peripheral instance base addresses */ +/** Peripheral DCSS__MED_DC_SCALER base address */ +#define DCSS__MED_DC_SCALER_BASE (0x32E1C000u) +/** Peripheral DCSS__MED_DC_SCALER base pointer */ +#define DCSS__MED_DC_SCALER ((MED_DC_SCALER_Type *)DCSS__MED_DC_SCALER_BASE) +/** Array initializer of MED_DC_SCALER peripheral base addresses */ +#define MED_DC_SCALER_BASE_ADDRS { DCSS__MED_DC_SCALER_BASE } +/** Array initializer of MED_DC_SCALER peripheral base pointers */ +#define MED_DC_SCALER_BASE_PTRS { DCSS__MED_DC_SCALER } + +/*! + * @} + */ /* end of group MED_DC_SCALER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MED_HDR10 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MED_HDR10_Peripheral_Access_Layer MED_HDR10 Peripheral Access Layer + * @{ + */ + +/** MED_HDR10 - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIPE1_A0_LUT; /**< A0 component Look-Up-Table. (LUT), offset: 0x0 */ + uint8_t RESERVED_0[4092]; + __IO uint32_t PIPE1_A1_LUT; /**< A1 component Look-Up-Table. (LUT), offset: 0x1000 */ + uint8_t RESERVED_1[4092]; + __IO uint32_t PIPE1_A2_LUT; /**< A2 component Look-Up-Table. (LUT), offset: 0x2000 */ + uint8_t RESERVED_2[4092]; + __IO uint32_t HDR_PIPE1_CSCA_CONTROL_REG; /**< Pipe1 Colorspace Converter A control., offset: 0x3000 */ + __IO uint32_t HDR_PIPE1_CSCA_H00; /**< Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient, offset: 0x3004 */ + __IO uint32_t HDR_PIPE1_CSCA_H10; /**< Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient, offset: 0x3008 */ + __IO uint32_t HDR_PIPE1_CSCA_H20; /**< Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient, offset: 0x300C */ + __IO uint32_t HDR_PIPE1_CSCA_H01; /**< Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient, offset: 0x3010 */ + __IO uint32_t HDR_PIPE1_CSCA_H11; /**< Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient, offset: 0x3014 */ + __IO uint32_t HDR_PIPE1_CSCA_H21; /**< Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient, offset: 0x3018 */ + __IO uint32_t HDR_PIPE1_CSCA_H02; /**< Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient, offset: 0x301C */ + __IO uint32_t HDR_PIPE1_CSCA_H12; /**< Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient, offset: 0x3020 */ + __IO uint32_t HDR_PIPE1_CSCA_H22; /**< Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient, offset: 0x3024 */ + __IO uint32_t HDR_PIPE1_CSCA_IO_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset, offset: 0x3028 */ + __IO uint32_t HDR_PIPE1_CSCA_IO_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset, offset: 0x302C */ + __IO uint32_t HDR_PIPE1_CSCA_IO_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset, offset: 0x3030 */ + __IO uint32_t HDR_PIPE1_CSCA_IO_MIN_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip min., offset: 0x3034 */ + __IO uint32_t HDR_PIPE1_CSCA_IO_MIN_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip min., offset: 0x3038 */ + __IO uint32_t HDR_PIPE1_CSCA_IO_MIN_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip min., offset: 0x303C */ + __IO uint32_t HDR_PIPE1_CSCA_IO_MAX_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip max value., offset: 0x3040 */ + __IO uint32_t HDR_PIPE1_CSCA_IO_MAX_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip max value., offset: 0x3044 */ + __IO uint32_t HDR_PIPE1_CSCA_IO_MAX_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip max value., offset: 0x3048 */ + __IO uint32_t HDR_PIPE1_CSCA_NORM; /**< Pipe1 Colorspace Converter A (CSCA) normalization factor, offset: 0x304C */ + __IO uint32_t HDR_PIPE1_CSCA_OO_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 0, offset: 0x3050 */ + __IO uint32_t HDR_PIPE1_CSCA_OO_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 1, offset: 0x3054 */ + __IO uint32_t HDR_PIPE1_CSCA_OO_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 2, offset: 0x3058 */ + __IO uint32_t HDR_PIPE1_CSCA_OMIN_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0, offset: 0x305C */ + __IO uint32_t HDR_PIPE1_CSCA_OMIN_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1, offset: 0x3060 */ + __IO uint32_t HDR_PIPE1_CSCA_OMIN_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2, offset: 0x3064 */ + __IO uint32_t HDR_PIPE1_CSCA_OMAX_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0, offset: 0x3068 */ + __IO uint32_t HDR_PIPE1_CSCA_OMAX_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1, offset: 0x306C */ + __IO uint32_t HDR_PIPE1_CSCA_OMAX_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2, offset: 0x3070 */ + uint32_t HDR_PIPE1_ENTRY_29; /**< PIPE1: NOT USED, offset: 0x3074 */ + uint8_t RESERVED_3[8]; + __IO uint32_t HDR_PIPE1_LUT_CONTROL_REG; /**< Pipe1 LUT control register, offset: 0x3080 */ + uint8_t RESERVED_4[1916]; + __IO uint32_t HDR_PIPE1_CSCB_CONTROL_REG; /**< Pipe1 Colorspace Converter B control., offset: 0x3800 */ + __IO uint32_t HDR_PIPE1_CSCB_H00; /**< Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient, offset: 0x3804 */ + __IO uint32_t HDR_PIPE1_CSCB_H10; /**< Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient, offset: 0x3808 */ + __IO uint32_t HDR_PIPE1_CSCB_H20; /**< Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient, offset: 0x380C */ + __IO uint32_t HDR_PIPE1_CSCB_H01; /**< Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient, offset: 0x3810 */ + __IO uint32_t HDR_PIPE1_CSCB_H11; /**< Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient, offset: 0x3814 */ + __IO uint32_t HDR_PIPE1_CSCB_H21; /**< Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient, offset: 0x3818 */ + __IO uint32_t HDR_PIPE1_CSCB_H02; /**< Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient, offset: 0x381C */ + __IO uint32_t HDR_PIPE1_CSCB_H12; /**< Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient, offset: 0x3820 */ + __IO uint32_t HDR_PIPE1_CSCB_H22; /**< Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient, offset: 0x3824 */ + __IO uint32_t HDR_PIPE1_CSCB_IO_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset, offset: 0x3828 */ + __IO uint32_t HDR_PIPE1_CSCB_IO_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset, offset: 0x382C */ + __IO uint32_t HDR_PIPE1_CSCB_IO_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset, offset: 0x3830 */ + __IO uint32_t HDR_PIPE1_CSCB_IO_MIN_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip min., offset: 0x3834 */ + __IO uint32_t HDR_PIPE1_CSCB_IO_MIN_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip min., offset: 0x3838 */ + __IO uint32_t HDR_PIPE1_CSCB_IO_MIN_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip min., offset: 0x383C */ + __IO uint32_t HDR_PIPE1_CSCB_IO_MAX_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip max value., offset: 0x3840 */ + __IO uint32_t HDR_PIPE1_CSCB_IO_MAX_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip max value., offset: 0x3844 */ + __IO uint32_t HDR_PIPE1_CSCB_IO_MAX_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip max value., offset: 0x3848 */ + __IO uint32_t HDR_PIPE1_CSCB_NORM; /**< Pipe1 Colorspace Converter B (CSCB) normalization factor, offset: 0x384C */ + __IO uint32_t HDR_PIPE1_CSCB_OO_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 0, offset: 0x3850 */ + __IO uint32_t HDR_PIPE1_CSCB_OO_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 1, offset: 0x3854 */ + __IO uint32_t HDR_PIPE1_CSCB_OO_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 2, offset: 0x3858 */ + __IO uint32_t HDR_PIPE1_CSCB_OMIN_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0, offset: 0x385C */ + __IO uint32_t HDR_PIPE1_CSCB_OMIN_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1, offset: 0x3860 */ + __IO uint32_t HDR_PIPE1_CSCB_OMIN_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2, offset: 0x3864 */ + __IO uint32_t HDR_PIPE1_CSCB_OMAX_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0, offset: 0x3868 */ + __IO uint32_t HDR_PIPE1_CSCB_OMAX_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1, offset: 0x386C */ + __IO uint32_t HDR_PIPE1_CSCB_OMAX_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2, offset: 0x3870 */ + __IO uint32_t HDR_PIPE1_FL2FX; /**< Pipe1 floating point to fixed point control, offset: 0x3874 */ + uint32_t HDR_PIPE1_ENTRY_30; /**< PIPE1: NOT USED, offset: 0x3878 */ + uint8_t RESERVED_5[1924]; + __IO uint32_t PIPE2_A0_LUT; /**< A0 component Look-Up-Table. (LUT), offset: 0x4000 */ + uint8_t RESERVED_6[4092]; + __IO uint32_t PIPE2_A1_LUT; /**< A1 component Look-Up-Table. (LUT), offset: 0x5000 */ + uint8_t RESERVED_7[4092]; + __IO uint32_t PIPE2_A2_LUT; /**< A2 component Look-Up-Table. (LUT), offset: 0x6000 */ + uint8_t RESERVED_8[4092]; + __IO uint32_t HDR_PIPE2_CSCA_CONTROL_REG; /**< Pipe1 Colorspace Converter A control., offset: 0x7000 */ + __IO uint32_t HDR_PIPE2_CSCA_H00; /**< Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient, offset: 0x7004 */ + __IO uint32_t HDR_PIPE2_CSCA_H10; /**< Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient, offset: 0x7008 */ + __IO uint32_t HDR_PIPE2_CSCA_H20; /**< Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient, offset: 0x700C */ + __IO uint32_t HDR_PIPE2_CSCA_H01; /**< Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient, offset: 0x7010 */ + __IO uint32_t HDR_PIPE2_CSCA_H11; /**< Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient, offset: 0x7014 */ + __IO uint32_t HDR_PIPE2_CSCA_H21; /**< Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient, offset: 0x7018 */ + __IO uint32_t HDR_PIPE2_CSCA_H02; /**< Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient, offset: 0x701C */ + __IO uint32_t HDR_PIPE2_CSCA_H12; /**< Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient, offset: 0x7020 */ + __IO uint32_t HDR_PIPE2_CSCA_H22; /**< Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient, offset: 0x7024 */ + __IO uint32_t HDR_PIPE2_CSCA_IO_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset, offset: 0x7028 */ + __IO uint32_t HDR_PIPE2_CSCA_IO_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset, offset: 0x702C */ + __IO uint32_t HDR_PIPE2_CSCA_IO_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset, offset: 0x7030 */ + __IO uint32_t HDR_PIPE2_CSCA_IO_MIN_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip min., offset: 0x7034 */ + __IO uint32_t HDR_PIPE2_CSCA_IO_MIN_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip min., offset: 0x7038 */ + __IO uint32_t HDR_PIPE2_CSCA_IO_MIN_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip min., offset: 0x703C */ + __IO uint32_t HDR_PIPE2_CSCA_IO_MAX_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip max value., offset: 0x7040 */ + __IO uint32_t HDR_PIPE2_CSCA_IO_MAX_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip max value., offset: 0x7044 */ + __IO uint32_t HDR_PIPE2_CSCA_IO_MAX_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip max value., offset: 0x7048 */ + __IO uint32_t HDR_PIPE2_CSCA_NORM; /**< Pipe1 Colorspace Converter A (CSCA) normalization factor, offset: 0x704C */ + __IO uint32_t HDR_PIPE2_CSCA_OO_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 0, offset: 0x7050 */ + __IO uint32_t HDR_PIPE2_CSCA_OO_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 1, offset: 0x7054 */ + __IO uint32_t HDR_PIPE2_CSCA_OO_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 2, offset: 0x7058 */ + __IO uint32_t HDR_PIPE2_CSCA_OMIN_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0, offset: 0x705C */ + __IO uint32_t HDR_PIPE2_CSCA_OMIN_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1, offset: 0x7060 */ + __IO uint32_t HDR_PIPE2_CSCA_OMIN_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2, offset: 0x7064 */ + __IO uint32_t HDR_PIPE2_CSCA_OMAX_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0, offset: 0x7068 */ + __IO uint32_t HDR_PIPE2_CSCA_OMAX_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1, offset: 0x706C */ + __IO uint32_t HDR_PIPE2_CSCA_OMAX_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2, offset: 0x7070 */ + uint32_t HDR_PIPE2_ENTRY_29; /**< PIPE2: NOT USED, offset: 0x7074 */ + uint8_t RESERVED_9[8]; + __IO uint32_t HDR_PIPE2_LUT_CONTROL_REG; /**< Pipe1 LUT control register, offset: 0x7080 */ + uint8_t RESERVED_10[1916]; + __IO uint32_t HDR_PIPE2_CSCB_CONTROL_REG; /**< Pipe1 Colorspace Converter B control., offset: 0x7800 */ + __IO uint32_t HDR_PIPE2_CSCB_H00; /**< Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient, offset: 0x7804 */ + __IO uint32_t HDR_PIPE2_CSCB_H10; /**< Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient, offset: 0x7808 */ + __IO uint32_t HDR_PIPE2_CSCB_H20; /**< Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient, offset: 0x780C */ + __IO uint32_t HDR_PIPE2_CSCB_H01; /**< Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient, offset: 0x7810 */ + __IO uint32_t HDR_PIPE2_CSCB_H11; /**< Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient, offset: 0x7814 */ + __IO uint32_t HDR_PIPE2_CSCB_H21; /**< Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient, offset: 0x7818 */ + __IO uint32_t HDR_PIPE2_CSCB_H02; /**< Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient, offset: 0x781C */ + __IO uint32_t HDR_PIPE2_CSCB_H12; /**< Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient, offset: 0x7820 */ + __IO uint32_t HDR_PIPE2_CSCB_H22; /**< Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient, offset: 0x7824 */ + __IO uint32_t HDR_PIPE2_CSCB_IO_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset, offset: 0x7828 */ + __IO uint32_t HDR_PIPE2_CSCB_IO_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset, offset: 0x782C */ + __IO uint32_t HDR_PIPE2_CSCB_IO_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset, offset: 0x7830 */ + __IO uint32_t HDR_PIPE2_CSCB_IO_MIN_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip min., offset: 0x7834 */ + __IO uint32_t HDR_PIPE2_CSCB_IO_MIN_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip min., offset: 0x7838 */ + __IO uint32_t HDR_PIPE2_CSCB_IO_MIN_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip min., offset: 0x783C */ + __IO uint32_t HDR_PIPE2_CSCB_IO_MAX_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip max value., offset: 0x7840 */ + __IO uint32_t HDR_PIPE2_CSCB_IO_MAX_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip max value., offset: 0x7844 */ + __IO uint32_t HDR_PIPE2_CSCB_IO_MAX_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip max value., offset: 0x7848 */ + __IO uint32_t HDR_PIPE2_CSCB_NORM; /**< Pipe1 Colorspace Converter B (CSCB) normalization factor, offset: 0x784C */ + __IO uint32_t HDR_PIPE2_CSCB_OO_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 0, offset: 0x7850 */ + __IO uint32_t HDR_PIPE2_CSCB_OO_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 1, offset: 0x7854 */ + __IO uint32_t HDR_PIPE2_CSCB_OO_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 2, offset: 0x7858 */ + __IO uint32_t HDR_PIPE2_CSCB_OMIN_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0, offset: 0x785C */ + __IO uint32_t HDR_PIPE2_CSCB_OMIN_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1, offset: 0x7860 */ + __IO uint32_t HDR_PIPE2_CSCB_OMIN_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2, offset: 0x7864 */ + __IO uint32_t HDR_PIPE2_CSCB_OMAX_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0, offset: 0x7868 */ + __IO uint32_t HDR_PIPE2_CSCB_OMAX_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1, offset: 0x786C */ + __IO uint32_t HDR_PIPE2_CSCB_OMAX_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2, offset: 0x7870 */ + __IO uint32_t HDR_PIPE2_FL2FX; /**< Pipe1 floating point to fixed point control, offset: 0x7874 */ + uint32_t HDR_PIPE2_ENTRY_30; /**< PIPE2: NOT USED, offset: 0x7878 */ + uint8_t RESERVED_11[1924]; + __IO uint32_t PIPE3_A0_LUT; /**< A0 component Look-Up-Table. (LUT), offset: 0x8000 */ + uint8_t RESERVED_12[4092]; + __IO uint32_t PIPE3_A1_LUT; /**< A1 component Look-Up-Table. (LUT), offset: 0x9000 */ + uint8_t RESERVED_13[4092]; + __IO uint32_t PIPE3_A2_LUT; /**< A2 component Look-Up-Table. (LUT), offset: 0xA000 */ + uint8_t RESERVED_14[4092]; + __IO uint32_t HDR_PIPE3_CSCA_CONTROL_REG; /**< Pipe1 Colorspace Converter A control., offset: 0xB000 */ + __IO uint32_t HDR_PIPE3_CSCA_H00; /**< Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient, offset: 0xB004 */ + __IO uint32_t HDR_PIPE3_CSCA_H10; /**< Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient, offset: 0xB008 */ + __IO uint32_t HDR_PIPE3_CSCA_H20; /**< Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient, offset: 0xB00C */ + __IO uint32_t HDR_PIPE3_CSCA_H01; /**< Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient, offset: 0xB010 */ + __IO uint32_t HDR_PIPE3_CSCA_H11; /**< Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient, offset: 0xB014 */ + __IO uint32_t HDR_PIPE3_CSCA_H21; /**< Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient, offset: 0xB018 */ + __IO uint32_t HDR_PIPE3_CSCA_H02; /**< Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient, offset: 0xB01C */ + __IO uint32_t HDR_PIPE3_CSCA_H12; /**< Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient, offset: 0xB020 */ + __IO uint32_t HDR_PIPE3_CSCA_H22; /**< Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient, offset: 0xB024 */ + __IO uint32_t HDR_PIPE3_CSCA_IO_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset, offset: 0xB028 */ + __IO uint32_t HDR_PIPE3_CSCA_IO_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset, offset: 0xB02C */ + __IO uint32_t HDR_PIPE3_CSCA_IO_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset, offset: 0xB030 */ + __IO uint32_t HDR_PIPE3_CSCA_IO_MIN_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip min., offset: 0xB034 */ + __IO uint32_t HDR_PIPE3_CSCA_IO_MIN_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip min., offset: 0xB038 */ + __IO uint32_t HDR_PIPE3_CSCA_IO_MIN_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip min., offset: 0xB03C */ + __IO uint32_t HDR_PIPE3_CSCA_IO_MAX_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip max value., offset: 0xB040 */ + __IO uint32_t HDR_PIPE3_CSCA_IO_MAX_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip max value., offset: 0xB044 */ + __IO uint32_t HDR_PIPE3_CSCA_IO_MAX_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip max value., offset: 0xB048 */ + __IO uint32_t HDR_PIPE3_CSCA_NORM; /**< Pipe1 Colorspace Converter A (CSCA) normalization factor, offset: 0xB04C */ + __IO uint32_t HDR_PIPE3_CSCA_OO_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 0, offset: 0xB050 */ + __IO uint32_t HDR_PIPE3_CSCA_OO_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 1, offset: 0xB054 */ + __IO uint32_t HDR_PIPE3_CSCA_OO_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 2, offset: 0xB058 */ + __IO uint32_t HDR_PIPE3_CSCA_OMIN_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0, offset: 0xB05C */ + __IO uint32_t HDR_PIPE3_CSCA_OMIN_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1, offset: 0xB060 */ + __IO uint32_t HDR_PIPE3_CSCA_OMIN_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2, offset: 0xB064 */ + __IO uint32_t HDR_PIPE3_CSCA_OMAX_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0, offset: 0xB068 */ + __IO uint32_t HDR_PIPE3_CSCA_OMAX_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1, offset: 0xB06C */ + __IO uint32_t HDR_PIPE3_CSCA_OMAX_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2, offset: 0xB070 */ + uint32_t HDR_PIPE3_ENTRY_29; /**< PIPE3: NOT USED, offset: 0xB074 */ + uint8_t RESERVED_15[8]; + __IO uint32_t HDR_PIPE3_LUT_CONTROL_REG; /**< Pipe1 LUT control register, offset: 0xB080 */ + uint8_t RESERVED_16[1916]; + __IO uint32_t HDR_PIPE3_CSCB_CONTROL_REG; /**< Pipe1 Colorspace Converter B control., offset: 0xB800 */ + __IO uint32_t HDR_PIPE3_CSCB_H00; /**< Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient, offset: 0xB804 */ + __IO uint32_t HDR_PIPE3_CSCB_H10; /**< Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient, offset: 0xB808 */ + __IO uint32_t HDR_PIPE3_CSCB_H20; /**< Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient, offset: 0xB80C */ + __IO uint32_t HDR_PIPE3_CSCB_H01; /**< Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient, offset: 0xB810 */ + __IO uint32_t HDR_PIPE3_CSCB_H11; /**< Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient, offset: 0xB814 */ + __IO uint32_t HDR_PIPE3_CSCB_H21; /**< Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient, offset: 0xB818 */ + __IO uint32_t HDR_PIPE3_CSCB_H02; /**< Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient, offset: 0xB81C */ + __IO uint32_t HDR_PIPE3_CSCB_H12; /**< Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient, offset: 0xB820 */ + __IO uint32_t HDR_PIPE3_CSCB_H22; /**< Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient, offset: 0xB824 */ + __IO uint32_t HDR_PIPE3_CSCB_IO_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset, offset: 0xB828 */ + __IO uint32_t HDR_PIPE3_CSCB_IO_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset, offset: 0xB82C */ + __IO uint32_t HDR_PIPE3_CSCB_IO_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset, offset: 0xB830 */ + __IO uint32_t HDR_PIPE3_CSCB_IO_MIN_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip min., offset: 0xB834 */ + __IO uint32_t HDR_PIPE3_CSCB_IO_MIN_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip min., offset: 0xB838 */ + __IO uint32_t HDR_PIPE3_CSCB_IO_MIN_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip min., offset: 0xB83C */ + __IO uint32_t HDR_PIPE3_CSCB_IO_MAX_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip max value., offset: 0xB840 */ + __IO uint32_t HDR_PIPE3_CSCB_IO_MAX_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip max value., offset: 0xB844 */ + __IO uint32_t HDR_PIPE3_CSCB_IO_MAX_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip max value., offset: 0xB848 */ + __IO uint32_t HDR_PIPE3_CSCB_NORM; /**< Pipe1 Colorspace Converter B (CSCB) normalization factor, offset: 0xB84C */ + __IO uint32_t HDR_PIPE3_CSCB_OO_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 0, offset: 0xB850 */ + __IO uint32_t HDR_PIPE3_CSCB_OO_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 1, offset: 0xB854 */ + __IO uint32_t HDR_PIPE3_CSCB_OO_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 2, offset: 0xB858 */ + __IO uint32_t HDR_PIPE3_CSCB_OMIN_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0, offset: 0xB85C */ + __IO uint32_t HDR_PIPE3_CSCB_OMIN_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1, offset: 0xB860 */ + __IO uint32_t HDR_PIPE3_CSCB_OMIN_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2, offset: 0xB864 */ + __IO uint32_t HDR_PIPE3_CSCB_OMAX_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0, offset: 0xB868 */ + __IO uint32_t HDR_PIPE3_CSCB_OMAX_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1, offset: 0xB86C */ + __IO uint32_t HDR_PIPE3_CSCB_OMAX_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2, offset: 0xB870 */ + __IO uint32_t HDR_PIPE3_FL2FX; /**< Pipe1 floating point to fixed point control, offset: 0xB874 */ + uint32_t HDR_PIPE3_ENTRY_30; /**< PIPE3: NOT USED, offset: 0xB878 */ + uint8_t RESERVED_17[1924]; + __IO uint32_t OPIPE_A0_TABLE; /**< A0 component Linear-to-Non-linear conversion table, offset: 0xC000 */ + uint8_t RESERVED_18[4092]; + __IO uint32_t OPIPE_A1_TABLE; /**< A1 component Linear-to-Non-linear conversion table, offset: 0xD000 */ + uint8_t RESERVED_19[4092]; + __IO uint32_t OPIPE_A2_TABLE; /**< A2 component Linear-to-Non-linear conversion table, offset: 0xE000 */ + uint8_t RESERVED_20[4092]; + __IO uint32_t HDR_OPIPE_CSC_CONTROL_REG; /**< HDR output stage Colorspace Converter (CSCO) control., offset: 0xF000 */ + __IO uint32_t HDR_OPIPE_CSC_H00; /**< Pipe1 Colorspace Converter (CSC) h(0,0) matrix coefficient, offset: 0xF004 */ + __IO uint32_t HDR_OPIPE_CSC_H10; /**< Pipe1 Colorspace Converter (CSC) h(1,0) matrix coefficient, offset: 0xF008 */ + __IO uint32_t HDR_OPIPE_CSC_H20; /**< HDR OUTPUT Colorspace Converter (CSCO) h(2,0) matrix coefficient, offset: 0xF00C */ + __IO uint32_t HDR_OPIPE_CSC_H01; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,1) matrix coefficient, offset: 0xF010 */ + __IO uint32_t HDR_OPIPE_CSC_H11; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) h(1,1) matrix coefficient, offset: 0xF014 */ + __IO uint32_t HDR_OPIPE_CSC_H21; /**< HDR_output pipe Colorspace Converter (CSCO) h(2,1) matrix coefficient, offset: 0xF018 */ + __IO uint32_t HDR_OPIPE_CSC_H02; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,2) matrix coefficient, offset: 0xF01C */ + __IO uint32_t HDR_OPIPE_CSC_H12; /**< HDR OUPUT pipe Colorspace Converter (CSCO) h(1,2) matrix coefficient, offset: 0xF020 */ + __IO uint32_t HDR_; /**< HDR OUPUT pipe Colorspace Converter (CSCO) h(2,2) matrix coefficient, offset: 0xF024 */ + __IO uint32_t HDR_OPIPE_CSC_IO_0; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) component 0 pre-offset, offset: 0xF028 */ + __IO uint32_t HDR_OPIPE_CSC_IO_1; /**< HDR OUPTUT pipe Colorspace Converter (CSCO) component 1 pre-offset, offset: 0xF02C */ + __IO uint32_t HDR_OPIPE_CSC_IO_2; /**< HDR OUPUT pipe: Colorspace Converter (CSCO) component 2 pre-offset, offset: 0xF030 */ + __IO uint32_t HDR_OPIPE_CSC_MIN_0; /**< HDR OUPTU pipe Colorspace Converter (CSCO) component 0 clip min., offset: 0xF034 */ + __IO uint32_t HDR_OPIPE_CSC_MIN_1; /**< HDR OUPUT pipe Colorspace Converter (CSCO) component 1 clip min., offset: 0xF038 */ + __IO uint32_t HDR_OPIPE_CSC_MIN_2; /**< HDR OUPTU pipe Colorspace Converter (CSCO) component 2 clip min., offset: 0xF03C */ + __IO uint32_t HDR_OPIPE_CSC_MAX_0; /**< HDR OUPTUT pipe Colorspace Converter O (CSC) component 0 clip max value., offset: 0xF040 */ + __IO uint32_t HDR_OPIPE_CSC_MAX_1; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) component 1 clip max value., offset: 0xF044 */ + __IO uint32_t HDR_OPIPE_CSC_MAX_2; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) component 2 clip max value., offset: 0xF048 */ + __IO uint32_t HDR_OPIPE_CSC_NORM; /**< HDR OUPUT pipe Colorspace Converter (CSCO) normalization factor, offset: 0xF04C */ + __IO uint32_t HDR_OPIPE_CSC_OO_0; /**< HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 0, offset: 0xF050 */ + __IO uint32_t HDR_OPIPE_CSC_OO_1; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset component 1, offset: 0xF054 */ + __IO uint32_t HDR_OPIPE_CSC_OO_2; /**< HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 2, offset: 0xF058 */ + __IO uint32_t HDR_OPIPE_CSC_OMIN_0; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 0, offset: 0xF05C */ + __IO uint32_t HDR_OPIPE_CSC_OMIN_1; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 1, offset: 0xF060 */ + __IO uint32_t HDR_OPIPE_CSC_OMIN_2; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 2, offset: 0xF064 */ + __IO uint32_t HDR_OPIPE_CSC_OMAX_0; /**< HDR OUPTUT pipe Colorspace Converter (CSC): Post offset max clip value for component 0, offset: 0xF068 */ + __IO uint32_t HDR_OPIPE_CSC_OMAX_1; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 1, offset: 0xF06C */ + __IO uint32_t HDR_OPIPE_CSC_OMAX_2; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 2, offset: 0xF070 */ + uint8_t RESERVED_21[2048]; + __IO uint32_t HDR_OPIPE_2NL_CONTROL_REG; /**< HDR OUTPUT -TO NON LINEAR pipeline control, offset: 0xF874 */ +} MED_HDR10_Type; + +/* ---------------------------------------------------------------------------- + -- MED_HDR10 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MED_HDR10_Register_Masks MED_HDR10 Register Masks + * @{ + */ + +/*! @name PIPE1_A0_LUT - A0 component Look-Up-Table. (LUT) */ +/*! @{ */ + +#define MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT_MASK (0x3FFFU) +#define MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT_SHIFT (0U) +#define MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT_SHIFT)) & MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT_MASK) +/*! @} */ + +/*! @name PIPE1_A1_LUT - A1 component Look-Up-Table. (LUT) */ +/*! @{ */ + +#define MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT_MASK (0x3FFFU) +#define MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT_SHIFT (0U) +#define MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT_SHIFT)) & MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT_MASK) +/*! @} */ + +/*! @name PIPE1_A2_LUT - A2 component Look-Up-Table. (LUT) */ +/*! @{ */ + +#define MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT_MASK (0x3FFFU) +#define MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT_SHIFT (0U) +#define MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT_SHIFT)) & MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_CONTROL_REG - Pipe1 Colorspace Converter A control. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_MASK (0x1U) +#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_MASK) + +#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) +#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) +#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) + +#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS_MASK (0x8000U) +#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS_SHIFT (15U) +#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_H00 - Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_H00_H00_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCA_H00_H00_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H00_H00_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_H10 - Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_H10_H10_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCA_H10_H10_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H10_H10_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_H20 - Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_H20_H20_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCA_H20_H20_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H20_H20_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_H01 - Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_H01_H01_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCA_H01_H01_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H01_H01_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_H11 - Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_H11_H11_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCA_H11_H11_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H11_H11_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_H21 - Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_H21_H21_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCA_H21_H21_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H21_H21_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_H02 - Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_H02_H02_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCA_H02_H02_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H02_H02_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_H12 - Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_H12_H12_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCA_H12_H12_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H12_H12_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_H22 - Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_H22_H22_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCA_H22_H22_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H22_H22_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_IO_0 - Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_IO_1 - Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_IO_2 - Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_IO_MIN_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_IO_MIN_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_IO_MIN_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_IO_MAX_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_IO_MAX_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_IO_MAX_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_NORM - Pipe1 Colorspace Converter A (CSCA) normalization factor */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM_MASK (0x1FU) +#define MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_OO_0 - Pipe1 Colorspace Converter A (CSCA): Post offset component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_OO_1 - Pipe1 Colorspace Converter A (CSCA): Post offset component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_OO_2 - Pipe1 Colorspace Converter A (CSCA): Post offset component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_OMIN_0 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_OMIN_1 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_OMIN_2 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_OMAX_0 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_OMAX_1 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCA_OMAX_2 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_LUT_CONTROL_REG - Pipe1 LUT control register */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_MASK (0x1U) +#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_MASK) + +#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) +#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) +#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) + +#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS_MASK (0x8000U) +#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS_SHIFT (15U) +#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_CONTROL_REG - Pipe1 Colorspace Converter B control. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_MASK (0x1U) +#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_MASK) + +#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) +#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) +#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) + +#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS_MASK (0x8000U) +#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS_SHIFT (15U) +#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_H00 - Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_H00_H00_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_H00_H00_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H00_H00_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_H10 - Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_H10_H10_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_H10_H10_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H10_H10_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_H20 - Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_H20_H20_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_H20_H20_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H20_H20_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_H01 - Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_H01_H01_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_H01_H01_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H01_H01_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_H11 - Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_H11_H11_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_H11_H11_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H11_H11_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_H21 - Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_H21_H21_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_H21_H21_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H21_H21_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_H02 - Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_H02_H02_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_H02_H02_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H02_H02_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_H12 - Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_H12_H12_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_H12_H12_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H12_H12_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_H22 - Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_H22_H22_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_H22_H22_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H22_H22_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_IO_0 - Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_IO_1 - Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_IO_2 - Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_IO_MIN_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_IO_MIN_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_IO_MIN_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_IO_MAX_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_IO_MAX_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_IO_MAX_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_NORM - Pipe1 Colorspace Converter B (CSCB) normalization factor */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM_MASK (0x1FU) +#define MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_OO_0 - Pipe1 Colorspace Converter B (CSCB): Post offset component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0_MASK (0x1FFFFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_OO_1 - Pipe1 Colorspace Converter B (CSCB): Post offset component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1_MASK (0x1FFFFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_OO_2 - Pipe1 Colorspace Converter B (CSCB): Post offset component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2_MASK (0x1FFFFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_OMIN_0 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_OMIN_1 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_OMIN_2 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_OMAX_0 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_OMAX_1 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_CSCB_OMAX_2 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE1_FL2FX - Pipe1 floating point to fixed point control */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_MASK (0x1U) +#define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_SHIFT (0U) +#define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_MASK) + +#define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS_MASK (0x2U) +#define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT (1U) +#define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS_MASK) +/*! @} */ + +/*! @name PIPE2_A0_LUT - A0 component Look-Up-Table. (LUT) */ +/*! @{ */ + +#define MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT_MASK (0x3FFFU) +#define MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT_SHIFT (0U) +#define MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT_SHIFT)) & MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT_MASK) +/*! @} */ + +/*! @name PIPE2_A1_LUT - A1 component Look-Up-Table. (LUT) */ +/*! @{ */ + +#define MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT_MASK (0x3FFFU) +#define MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT_SHIFT (0U) +#define MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT_SHIFT)) & MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT_MASK) +/*! @} */ + +/*! @name PIPE2_A2_LUT - A2 component Look-Up-Table. (LUT) */ +/*! @{ */ + +#define MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT_MASK (0x3FFFU) +#define MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT_SHIFT (0U) +#define MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT_SHIFT)) & MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_CONTROL_REG - Pipe1 Colorspace Converter A control. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_MASK (0x1U) +#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_MASK) + +#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) +#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) +#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) + +#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS_MASK (0x8000U) +#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS_SHIFT (15U) +#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_H00 - Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_H00_H00_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCA_H00_H00_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H00_H00_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_H10 - Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_H10_H10_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCA_H10_H10_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H10_H10_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_H20 - Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_H20_H20_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCA_H20_H20_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H20_H20_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_H01 - Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_H01_H01_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCA_H01_H01_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H01_H01_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_H11 - Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_H11_H11_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCA_H11_H11_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H11_H11_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_H21 - Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_H21_H21_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCA_H21_H21_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H21_H21_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_H02 - Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_H02_H02_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCA_H02_H02_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H02_H02_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_H12 - Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_H12_H12_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCA_H12_H12_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H12_H12_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_H22 - Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_H22_H22_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCA_H22_H22_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H22_H22_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_IO_0 - Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_IO_1 - Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_IO_2 - Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_IO_MIN_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_IO_MIN_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_IO_MIN_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_IO_MAX_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_IO_MAX_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_IO_MAX_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_NORM - Pipe1 Colorspace Converter A (CSCA) normalization factor */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM_MASK (0x1FU) +#define MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_OO_0 - Pipe1 Colorspace Converter A (CSCA): Post offset component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_OO_1 - Pipe1 Colorspace Converter A (CSCA): Post offset component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_OO_2 - Pipe1 Colorspace Converter A (CSCA): Post offset component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_OMIN_0 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_OMIN_1 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_OMIN_2 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_OMAX_0 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_OMAX_1 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCA_OMAX_2 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_LUT_CONTROL_REG - Pipe1 LUT control register */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_MASK (0x1U) +#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_MASK) + +#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) +#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) +#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) + +#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS_MASK (0x8000U) +#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS_SHIFT (15U) +#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_CONTROL_REG - Pipe1 Colorspace Converter B control. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_MASK (0x1U) +#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_MASK) + +#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) +#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) +#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) + +#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS_MASK (0x8000U) +#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS_SHIFT (15U) +#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_H00 - Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_H00_H00_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_H00_H00_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H00_H00_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_H10 - Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_H10_H10_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_H10_H10_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H10_H10_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_H20 - Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_H20_H20_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_H20_H20_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H20_H20_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_H01 - Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_H01_H01_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_H01_H01_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H01_H01_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_H11 - Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_H11_H11_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_H11_H11_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H11_H11_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_H21 - Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_H21_H21_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_H21_H21_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H21_H21_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_H02 - Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_H02_H02_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_H02_H02_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H02_H02_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_H12 - Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_H12_H12_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_H12_H12_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H12_H12_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_H22 - Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_H22_H22_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_H22_H22_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H22_H22_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_IO_0 - Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_IO_1 - Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_IO_2 - Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_IO_MIN_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_IO_MIN_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_IO_MIN_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_IO_MAX_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_IO_MAX_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_IO_MAX_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_NORM - Pipe1 Colorspace Converter B (CSCB) normalization factor */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM_MASK (0x1FU) +#define MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_OO_0 - Pipe1 Colorspace Converter B (CSCB): Post offset component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0_MASK (0x1FFFFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_OO_1 - Pipe1 Colorspace Converter B (CSCB): Post offset component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1_MASK (0x1FFFFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_OO_2 - Pipe1 Colorspace Converter B (CSCB): Post offset component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2_MASK (0x1FFFFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_OMIN_0 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_OMIN_1 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_OMIN_2 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_OMAX_0 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_OMAX_1 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_CSCB_OMAX_2 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE2_FL2FX - Pipe1 floating point to fixed point control */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_MASK (0x1U) +#define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_SHIFT (0U) +#define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_MASK) + +#define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS_MASK (0x2U) +#define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT (1U) +#define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS_MASK) +/*! @} */ + +/*! @name PIPE3_A0_LUT - A0 component Look-Up-Table. (LUT) */ +/*! @{ */ + +#define MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT_MASK (0x3FFFU) +#define MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT_SHIFT (0U) +#define MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT_SHIFT)) & MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT_MASK) +/*! @} */ + +/*! @name PIPE3_A1_LUT - A1 component Look-Up-Table. (LUT) */ +/*! @{ */ + +#define MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT_MASK (0x3FFFU) +#define MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT_SHIFT (0U) +#define MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT_SHIFT)) & MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT_MASK) +/*! @} */ + +/*! @name PIPE3_A2_LUT - A2 component Look-Up-Table. (LUT) */ +/*! @{ */ + +#define MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT_MASK (0x3FFFU) +#define MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT_SHIFT (0U) +#define MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT_SHIFT)) & MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_CONTROL_REG - Pipe1 Colorspace Converter A control. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_MASK (0x1U) +#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_MASK) + +#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) +#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) +#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) + +#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS_MASK (0x8000U) +#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS_SHIFT (15U) +#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_H00 - Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_H00_H00_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCA_H00_H00_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H00_H00_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_H10 - Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_H10_H10_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCA_H10_H10_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H10_H10_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_H20 - Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_H20_H20_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCA_H20_H20_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H20_H20_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_H01 - Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_H01_H01_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCA_H01_H01_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H01_H01_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_H11 - Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_H11_H11_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCA_H11_H11_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H11_H11_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_H21 - Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_H21_H21_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCA_H21_H21_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H21_H21_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_H02 - Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_H02_H02_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCA_H02_H02_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H02_H02_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_H12 - Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_H12_H12_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCA_H12_H12_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H12_H12_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_H22 - Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_H22_H22_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCA_H22_H22_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H22_H22_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_IO_0 - Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_IO_1 - Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_IO_2 - Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_IO_MIN_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_IO_MIN_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_IO_MIN_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_IO_MAX_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_IO_MAX_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_IO_MAX_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_NORM - Pipe1 Colorspace Converter A (CSCA) normalization factor */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM_MASK (0x1FU) +#define MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_OO_0 - Pipe1 Colorspace Converter A (CSCA): Post offset component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_OO_1 - Pipe1 Colorspace Converter A (CSCA): Post offset component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_OO_2 - Pipe1 Colorspace Converter A (CSCA): Post offset component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_OMIN_0 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_OMIN_1 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_OMIN_2 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_OMAX_0 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_OMAX_1 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCA_OMAX_2 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_LUT_CONTROL_REG - Pipe1 LUT control register */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_MASK (0x1U) +#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_MASK) + +#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) +#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) +#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) + +#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS_MASK (0x8000U) +#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS_SHIFT (15U) +#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_CONTROL_REG - Pipe1 Colorspace Converter B control. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_MASK (0x1U) +#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_MASK) + +#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) +#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) +#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) + +#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS_MASK (0x8000U) +#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS_SHIFT (15U) +#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_H00 - Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_H00_H00_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_H00_H00_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H00_H00_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_H10 - Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_H10_H10_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_H10_H10_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H10_H10_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_H20 - Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_H20_H20_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_H20_H20_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H20_H20_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_H01 - Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_H01_H01_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_H01_H01_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H01_H01_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_H11 - Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_H11_H11_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_H11_H11_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H11_H11_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_H21 - Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_H21_H21_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_H21_H21_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H21_H21_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_H02 - Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_H02_H02_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_H02_H02_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H02_H02_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_H12 - Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_H12_H12_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_H12_H12_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H12_H12_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_H22 - Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_H22_H22_MASK (0xFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_H22_H22_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H22_H22_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_IO_0 - Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_IO_1 - Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_IO_2 - Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_IO_MIN_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_IO_MIN_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_IO_MIN_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_IO_MAX_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_IO_MAX_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_IO_MAX_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_NORM - Pipe1 Colorspace Converter B (CSCB) normalization factor */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM_MASK (0x1FU) +#define MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_OO_0 - Pipe1 Colorspace Converter B (CSCB): Post offset component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0_MASK (0x1FFFFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_OO_1 - Pipe1 Colorspace Converter B (CSCB): Post offset component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1_MASK (0x1FFFFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_OO_2 - Pipe1 Colorspace Converter B (CSCB): Post offset component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2_MASK (0x1FFFFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_OMIN_0 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_OMIN_1 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_OMIN_2 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_OMAX_0 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_OMAX_1 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_CSCB_OMAX_2 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_PIPE3_FL2FX - Pipe1 floating point to fixed point control */ +/*! @{ */ + +#define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_MASK (0x1U) +#define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_SHIFT (0U) +#define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_MASK) + +#define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS_MASK (0x2U) +#define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT (1U) +#define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS_MASK) +/*! @} */ + +/*! @name OPIPE_A0_TABLE - A0 component Linear-to-Non-linear conversion table */ +/*! @{ */ + +#define MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE_MASK (0x3FFFU) +#define MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE_SHIFT (0U) +#define MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE_SHIFT)) & MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE_MASK) +/*! @} */ + +/*! @name OPIPE_A1_TABLE - A1 component Linear-to-Non-linear conversion table */ +/*! @{ */ + +#define MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE_MASK (0x3FFFU) +#define MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE_SHIFT (0U) +#define MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE_SHIFT)) & MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE_MASK) +/*! @} */ + +/*! @name OPIPE_A2_TABLE - A2 component Linear-to-Non-linear conversion table */ +/*! @{ */ + +#define MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE_MASK (0x3FFFU) +#define MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE_SHIFT (0U) +#define MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE_SHIFT)) & MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_CONTROL_REG - HDR output stage Colorspace Converter (CSCO) control. */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_MASK (0x1U) +#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_MASK) + +#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) +#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) +#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) + +#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS_MASK (0x8000U) +#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS_SHIFT (15U) +#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_H00 - Pipe1 Colorspace Converter (CSC) h(0,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_H00_H00_MASK (0xFFFFU) +#define MED_HDR10_HDR_OPIPE_CSC_H00_H00_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H00_H00_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H00_H00_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_H10 - Pipe1 Colorspace Converter (CSC) h(1,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_H10_H10_MASK (0xFFFFU) +#define MED_HDR10_HDR_OPIPE_CSC_H10_H10_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H10_H10_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H10_H10_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_H20 - HDR OUTPUT Colorspace Converter (CSCO) h(2,0) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_H20_H20_MASK (0xFFFFU) +#define MED_HDR10_HDR_OPIPE_CSC_H20_H20_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H20_H20_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H20_H20_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_H01 - HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_H01_H01_MASK (0xFFFFU) +#define MED_HDR10_HDR_OPIPE_CSC_H01_H01_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H01_H01_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H01_H01_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_H11 - HDR OUTPUT pipe Colorspace Converter (CSCO) h(1,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_H11_H11_MASK (0xFFFFU) +#define MED_HDR10_HDR_OPIPE_CSC_H11_H11_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H11_H11_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H11_H11_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_H21 - HDR_output pipe Colorspace Converter (CSCO) h(2,1) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_H21_H21_MASK (0xFFFFU) +#define MED_HDR10_HDR_OPIPE_CSC_H21_H21_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H21_H21_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H21_H21_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_H02 - HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_H02_H02_MASK (0xFFFFU) +#define MED_HDR10_HDR_OPIPE_CSC_H02_H02_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H02_H02_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H02_H02_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_H12 - HDR OUPUT pipe Colorspace Converter (CSCO) h(1,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_H12_H12_MASK (0xFFFFU) +#define MED_HDR10_HDR_OPIPE_CSC_H12_H12_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H12_H12_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H12_H12_MASK) +/*! @} */ + +/*! @name HDR_ - HDR OUPUT pipe Colorspace Converter (CSCO) h(2,2) matrix coefficient */ +/*! @{ */ + +#define MED_HDR10_HDR__H22_MASK (0xFFFFU) +#define MED_HDR10_HDR__H22_SHIFT (0U) +#define MED_HDR10_HDR__H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR__H22_SHIFT)) & MED_HDR10_HDR__H22_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_IO_0 - HDR OUTPUT pipe Colorspace Converter (CSCO) component 0 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_IO_1 - HDR OUPTUT pipe Colorspace Converter (CSCO) component 1 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_IO_2 - HDR OUPUT pipe: Colorspace Converter (CSCO) component 2 pre-offset */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_MIN_0 - HDR OUPTU pipe Colorspace Converter (CSCO) component 0 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_MIN_1 - HDR OUPUT pipe Colorspace Converter (CSCO) component 1 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_MIN_2 - HDR OUPTU pipe Colorspace Converter (CSCO) component 2 clip min. */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_MAX_0 - HDR OUPTUT pipe Colorspace Converter O (CSC) component 0 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_MAX_1 - HDR OUTPUT pipe Colorspace Converter (CSCO) component 1 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_MAX_2 - HDR OUTPUT pipe Colorspace Converter (CSCO) component 2 clip max value. */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_NORM - HDR OUPUT pipe Colorspace Converter (CSCO) normalization factor */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM_MASK (0x1FU) +#define MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_OO_0 - HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_OO_1 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_OO_2 - HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2_MASK (0xFFFFFFFU) +#define MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_OMIN_0 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_OMIN_1 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_OMIN_2 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_OMAX_0 - HDR OUPTUT pipe Colorspace Converter (CSC): Post offset max clip value for component 0 */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_OMAX_1 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 1 */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_CSC_OMAX_2 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 2 */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX_MASK (0x3FFU) +#define MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX_MASK) +/*! @} */ + +/*! @name HDR_OPIPE_2NL_CONTROL_REG - HDR OUTPUT -TO NON LINEAR pipeline control */ +/*! @{ */ + +#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU_MASK (0x1U) +#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU_SHIFT (0U) +#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU_SHIFT)) & MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU_MASK) + +#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT_MASK (0x2U) +#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT_SHIFT (1U) +#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT_SHIFT)) & MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT_MASK) + +#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS_MASK (0x4U) +#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS_SHIFT (2U) +#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS_MASK) + +#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS_MASK (0x8U) +#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS_SHIFT (3U) +#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MED_HDR10_Register_Masks */ + + +/* MED_HDR10 - Peripheral instance base addresses */ +/** Peripheral DCSS__MED_HDR10 base address */ +#define DCSS__MED_HDR10_BASE (0x32E0C000u) +/** Peripheral DCSS__MED_HDR10 base pointer */ +#define DCSS__MED_HDR10 ((MED_HDR10_Type *)DCSS__MED_HDR10_BASE) +/** Array initializer of MED_HDR10 peripheral base addresses */ +#define MED_HDR10_BASE_ADDRS { DCSS__MED_HDR10_BASE } +/** Array initializer of MED_HDR10 peripheral base pointers */ +#define MED_HDR10_BASE_PTRS { DCSS__MED_HDR10 } + +/*! + * @} + */ /* end of group MED_HDR10_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MIPI_CSI2RX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_CSI2RX_Peripheral_Access_Layer MIPI_CSI2RX Peripheral Access Layer + * @{ + */ + +/** MIPI_CSI2RX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSI2RX_CFG_NUM_LANES; /**< , offset: 0x0 */ + __IO uint32_t CSI2RX_CFG_DISABLE_DATA_LANES; /**< , offset: 0x4 */ + __I uint32_t CSI2RX_BIT_ERR; /**< , offset: 0x8 */ + __I uint32_t CSI2RX_IRQ_STATUS; /**< , offset: 0xC */ + __IO uint32_t CSI2RX_IRQ_MASK; /**< , offset: 0x10 */ + __I uint32_t CSI2RX_ULPS_STATUS; /**< , offset: 0x14 */ + __I uint32_t CSI2RX_PPI_ERRSOT_HS; /**< , offset: 0x18 */ + __I uint32_t CSI2RX_PPI_ERRSOTSYNC_HS; /**< , offset: 0x1C */ + __I uint32_t CSI2RX_PPI_ERRESC; /**< , offset: 0x20 */ + __I uint32_t CSI2RX_PPI_ERRSYNCESC; /**< , offset: 0x24 */ + __I uint32_t CSI2RX_PPI_ERRCONTROL; /**< , offset: 0x28 */ + __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_0; /**< , offset: 0x2C */ + __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_1; /**< , offset: 0x30 */ +} MIPI_CSI2RX_Type; + +/* ---------------------------------------------------------------------------- + -- MIPI_CSI2RX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_CSI2RX_Register_Masks MIPI_CSI2RX Register Masks + * @{ + */ + +/*! @name CSI2RX_CFG_NUM_LANES - */ +/*! @{ */ + +#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK (0x3U) +#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_SHIFT (0U) +/*! csi2rx_cfg_num_lanes - Sets the number of active lanes that are to be used for receiving data. + * 0b00..1 Lane + * 0b01..2 Lane + * 0b10..3 Lane + * 0b11..4 Lane + */ +#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK) +/*! @} */ + +/*! @name CSI2RX_CFG_DISABLE_DATA_LANES - */ +/*! @{ */ + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_MASK (0xFU) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_SHIFT (0U) +/*! csi2rx_cfg_disable_data_lanes - Setting bits to a '1' value causes the DPHY Enable signal to deassert. + * 0b0001..Data Lane 0 + * 0b0010..Data Lane 1 + * 0b0100..Data Lane 2 + * 0b1000..Data Lane 3 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_MASK) +/*! @} */ + +/*! @name CSI2RX_BIT_ERR - */ +/*! @{ */ + +#define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_MASK (0x3FFU) +#define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_SHIFT (0U) +/*! csi2rx_bit_err - BIT_ERR: CSI-2 RX Controller ECC and CRC error status. + */ +#define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_SHIFT)) & MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_MASK) +/*! @} */ + +/*! @name CSI2RX_IRQ_STATUS - */ +/*! @{ */ + +#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_MASK (0x1FFU) +#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_SHIFT (0U) +/*! csi2rx_irq_status - CSI2 RX IRQ status + */ +#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_MASK) +/*! @} */ + +/*! @name CSI2RX_IRQ_MASK - */ +/*! @{ */ + +#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK (0x1FFU) +#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_SHIFT (0U) +/*! csi2rx_irq_mask - CSI2 RX IRQ Mask setting + */ +#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK) +/*! @} */ + +/*! @name CSI2RX_ULPS_STATUS - */ +/*! @{ */ + +#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_MASK (0x3FFU) +#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_SHIFT (0U) +/*! csi2rx_ulps_status - Status of RX DPHY ULPS state + */ +#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_SHIFT)) & MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_MASK) +/*! @} */ + +/*! @name CSI2RX_PPI_ERRSOT_HS - */ +/*! @{ */ + +#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_MASK (0xFU) +#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_SHIFT (0U) +/*! csi2rx_ppi_errsot_hs - CSI2 RX DPHY PPI ErrSotHS captured status from the DPHY. + */ +#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_MASK) +/*! @} */ + +/*! @name CSI2RX_PPI_ERRSOTSYNC_HS - */ +/*! @{ */ + +#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_MASK (0xFU) +#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_SHIFT (0U) +/*! csi2rx_ppi_errsotsync_hs - CSI2 RX DPHY PPI ErrSotSync_HS captured status from the DPHY. + */ +#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_MASK) +/*! @} */ + +/*! @name CSI2RX_PPI_ERRESC - */ +/*! @{ */ + +#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_MASK (0xFU) +#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_SHIFT (0U) +/*! csi2rx_ppi_erresc - CSI2 RX DPHY PPI ErrEsc captured status from the DPHY. + */ +#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_MASK) +/*! @} */ + +/*! @name CSI2RX_PPI_ERRSYNCESC - */ +/*! @{ */ + +#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_MASK (0xFU) +#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_SHIFT (0U) +/*! csi2rx_ppi_errsyncesc - CSI2 RX DPHY PPI ErrSyncEsc captured status from the DPHY. + */ +#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_MASK) +/*! @} */ + +/*! @name CSI2RX_PPI_ERRCONTROL - */ +/*! @{ */ + +#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_MASK (0xFU) +#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_SHIFT (0U) +/*! csi2rx_ppi_errcontrol - CSI2 RX DPHY PPI ErrControl captured status from the DPHY. + */ +#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_MASK) +/*! @} */ + +/*! @name CSI2RX_CFG_DISABLE_PAYLOAD_0 - */ +/*! @{ */ + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null_MASK (0x1U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null_SHIFT (0U) +/*! csi2rx_cfg_disable_payload_null - Null + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank_MASK (0x2U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank_SHIFT (1U) +/*! csi2rx_cfg_disable_payload_blank - Blank + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded_MASK (0x4U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded_SHIFT (2U) +/*! csi2rx_cfg_disable_payload_embedded - Embedded + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8_MASK (0x400U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8_SHIFT (10U) +/*! csi2rx_cfg_disable_payload_legacy_yuv_8 - Legacy YUV 420 8 bit + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8_MASK (0x4000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8_SHIFT (14U) +/*! csi2rx_cfg_disable_payload_yuv_8 - YUV422 8 bit + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10_MASK (0x8000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10_SHIFT (15U) +/*! csi2rx_cfg_disable_payload_yuv_10 - YUV422 10 bit + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444_MASK (0x10000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444_SHIFT (16U) +/*! csi2rx_cfg_disable_payload_rgb444 - RGB444 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555_MASK (0x20000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555_SHIFT (17U) +/*! csi2rx_cfg_disable_payload_rgb555 - RGB555 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565_MASK (0x40000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565_SHIFT (18U) +/*! csi2rx_cfg_disable_payload_rgb565 - RGB565 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666_MASK (0x80000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666_SHIFT (19U) +/*! csi2rx_cfg_disable_payload_rgb666 - RGB666 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888_MASK (0x100000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888_SHIFT (20U) +/*! csi2rx_cfg_disable_payload_rgb888 - RGB888 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6_MASK (0x1000000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6_SHIFT (24U) +/*! csi2rx_cfg_disable_payload_raw6 - RAW6 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7_MASK (0x2000000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7_SHIFT (25U) +/*! csi2rx_cfg_disable_payload_raw7 - RAW7 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8_MASK (0x4000000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8_SHIFT (26U) +/*! csi2rx_cfg_disable_payload_raw8 - RAW8 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10_MASK (0x8000000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10_SHIFT (27U) +/*! csi2rx_cfg_disable_payload_raw10 - RAW10 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12_MASK (0x10000000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12_SHIFT (28U) +/*! csi2rx_cfg_disable_payload_raw12 - RAW12 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14_MASK (0x20000000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14_SHIFT (29U) +/*! csi2rx_cfg_disable_payload_raw14 - RAW14 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14_MASK) +/*! @} */ + +/*! @name CSI2RX_CFG_DISABLE_PAYLOAD_1 - */ +/*! @{ */ + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30_MASK (0x1U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30_SHIFT (0U) +/*! csi2rx_cfg_disable_payload_udef_30 - User defined type 0x31 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31_MASK (0x2U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31_SHIFT (1U) +/*! csi2rx_cfg_disable_payload_udef_31 - User defined type 0x32 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32_MASK (0x4U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32_SHIFT (2U) +/*! csi2rx_cfg_disable_payload_udef_32 - User defined type 0x33 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33_MASK (0x8U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33_SHIFT (3U) +/*! csi2rx_cfg_disable_payload_udef_33 - User defined type 0x34 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34_MASK (0x10U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34_SHIFT (4U) +/*! csi2rx_cfg_disable_payload_udef_34 - User defined type 0x35 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35_MASK (0x20U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35_SHIFT (5U) +/*! csi2rx_cfg_disable_payload_udef_35 - User defined type 0x35 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36_MASK (0x40U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36_SHIFT (6U) +/*! csi2rx_cfg_disable_payload_udef_36 - User defined type 0x36 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37_MASK (0x80U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37_SHIFT (7U) +/*! csi2rx_cfg_disable_payload_udef_37 - User defined type 0x37 + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37_MASK) + +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported_MASK (0x10000U) +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported_SHIFT (16U) +/*! csi2rx_cfg_disable_payload_unsupported - Unsupported Data Types + */ +#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MIPI_CSI2RX_Register_Masks */ + + +/* MIPI_CSI2RX - Peripheral instance base addresses */ +/** Peripheral MIPI_CSI2RX1 base address */ +#define MIPI_CSI2RX1_BASE (0x30A70000u) +/** Peripheral MIPI_CSI2RX1 base pointer */ +#define MIPI_CSI2RX1 ((MIPI_CSI2RX_Type *)MIPI_CSI2RX1_BASE) +/** Peripheral MIPI_CSI2RX2 base address */ +#define MIPI_CSI2RX2_BASE (0x30B60000u) +/** Peripheral MIPI_CSI2RX2 base pointer */ +#define MIPI_CSI2RX2 ((MIPI_CSI2RX_Type *)MIPI_CSI2RX2_BASE) +/** Array initializer of MIPI_CSI2RX peripheral base addresses */ +#define MIPI_CSI2RX_BASE_ADDRS { 0u, MIPI_CSI2RX1_BASE, MIPI_CSI2RX2_BASE } +/** Array initializer of MIPI_CSI2RX peripheral base pointers */ +#define MIPI_CSI2RX_BASE_PTRS { (MIPI_CSI2RX_Type *)0u, MIPI_CSI2RX1, MIPI_CSI2RX2 } + +/*! + * @} + */ /* end of group MIPI_CSI2RX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MIPI_DSI_HOST Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_HOST_Peripheral_Access_Layer MIPI_DSI_HOST Peripheral Access Layer + * @{ + */ + +/** MIPI_DSI_HOST - Register Layout Typedef */ +typedef struct { + __IO uint32_t DSI_HOST_CFG_NUM_LANES; /**< , offset: 0x0 */ + __IO uint32_t DSI_HOST_CFG_NONCONTINUOUS_CLK; /**< , offset: 0x4 */ + __IO uint32_t DSI_HOST_CFG_T_PRE; /**< , offset: 0x8 */ + __IO uint32_t DSI_HOST_CFG_T_POST; /**< , offset: 0xC */ + __IO uint32_t DSI_HOST_CFG_TX_GAP; /**< , offset: 0x10 */ + __IO uint32_t DSI_HOST_CFG_AUTOINSERT_EOTP; /**< , offset: 0x14 */ + __IO uint32_t DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP; /**< , offset: 0x18 */ + __IO uint32_t DSI_HOST_CFG_HTX_TO_COUNT; /**< , offset: 0x1C */ + __IO uint32_t DSI_HOST_CFG_LRX_H_TO_COUNT; /**< , offset: 0x20 */ + __IO uint32_t DSI_HOST_CFG_BTA_H_TO_COUNT; /**< , offset: 0x24 */ + __IO uint32_t DSI_HOST_CFG_TWAKEUP; /**< , offset: 0x28 */ + __I uint32_t DSI_HOST_CFG_STATUS_OUT; /**< , offset: 0x2C */ + __I uint32_t DSI_HOST_RX_ERROR_STATUS; /**< , offset: 0x30 */ +} MIPI_DSI_HOST_Type; + +/* ---------------------------------------------------------------------------- + -- MIPI_DSI_HOST Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_HOST_Register_Masks MIPI_DSI_HOST Register Masks + * @{ + */ + +/*! @name DSI_HOST_CFG_NUM_LANES - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK (0x3U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT (0U) +/*! dsi_host_cfg_num_lanes - Sets the number of active lanes that are to be used for transmitting + * data. 2'b00 - 1 Lane 2'b01 - 2 Lanes 2'b10 - 3 Lanes 2'b11 - 4 Lanes + */ +#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_NONCONTINUOUS_CLK - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK (0x1U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT (0U) +/*! dsi_host_cfg_noncontinuous_clk - Sets the Host Controller into non-continuous MIPI clock mode. + * When in non-continuous clock mode, the high speed clock will transistion into low power mode + * between transmissions. 1'b0 - Continuous high speed clock 1'b1 - Non-Continuous high speed clock + */ +#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_T_PRE - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK (0x7FU) +#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT (0U) +/*! dsi_host_cfg_t_pre - Sets the number of byte clock periods ('clk_byte' input) that the + * controller will wait after enabling the clock lane for HS operation before enabling the data lanes for + * HS operation. This setting represents the TCLK-PRE parameter. The minimum value for this port + * is 1. + */ +#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_T_POST - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK (0x7FU) +#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT (0U) +/*! dsi_host_cfg_t_post - Sets the number of byte clock periods ('clk_byte' input) to wait before + * putting the clock lane into LP mode after the data lanes have been detected to be in Stop State. + * This setting represents the DPHY timing parameters TLPX (TxClkEsc) + TCLK-PREPARE + TCLK-ZERO + * + TCLK-PRE requirement for the clock lane before the data lane is allowed to change from LP11 + * to start a high speed transmission. The minimum value for this port is 1. + */ +#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_TX_GAP - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK (0x7FU) +#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT (0U) +/*! dsi_host_cfg_tx_gap - Sets the number of byte clock periods ('clk_byte' input) that the + * controller will wait after the clock lane has been put into LP mode before enabling the clock lane for + * HS mode again. This setting represents the THS-EXIT parameter. The minimum value for this + * port is 1. + */ +#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_AUTOINSERT_EOTP - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK (0x1U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT (0U) +/*! dsi_host_cfg_autoinsert_eotp - Enables the Host Controller to automatically insert an EoTp short + * packet when switching from HS to LP mode. 1'b0 - EoTp is not automatically inserted 1'b1 - + * EoTp is automatically inserted + */ +#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK (0xFFU) +#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT (0U) +/*! dsi_host_cfg_extra_cmds_after_eotp - Configures the DSI Host Controller to send extra End Of + * Transmission Packets after the end of a packet. The value is the number of extra EOTP packets + * sent. + */ +#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_HTX_TO_COUNT - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK (0xFFFFFFU) +#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT (0U) +/*! dsi_host_cfg_htx_to_count - Sets the value of the DSI Host High Speed TX timeout count in + * clk_byte clock periods that once reached will initiate a timeout error and follow the recovery + * procedure documented in the DSI specification. This timeout parameter should be configured to + * represent the time taken to transmit the biggest HS data payload. If this timeout is reached the + * DSI byte count is cleared and the HS transmission is aborted. This timer can be also disabled, + * when set to 0. + */ +#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_LRX_H_TO_COUNT - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK (0xFFFFFFU) +#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT (0U) +/*! dsi_host_cfg_lrx_h_to_count - Sets the value of the DSI Host low power RX timeout count in + * clk_byte clock periods that once reached will initiate a timeout error and follow the recovery + * procedure documented in the DSI specification. This timeout parameter should be configured to + * represent the time taken to receive the biggest LP (Escape mode) data payload. If this timeout is + * reached, the DSI byte count is cleared and the LP reception is aborted. This timer can be also + * disabled, when set to 0 + */ +#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_BTA_H_TO_COUNT - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK (0xFFFFFFU) +#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT (0U) +/*! dsi_host_cfg_bta_h_to_count - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in + * clk_byte clock periods that once reached will initiate a timeout error. + */ +#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_TWAKEUP - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK (0x7FFFFU) +#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT (0U) +/*! dsi_host_cfg_twakeup - DPHY Twakeup timing parameter. Sets the number of clk_esc clock periods + * to keep a clock or data lane in Mark-1 state after exiting ULPS. The MIPI DPHY spec requires a + * minimum of 1ms in Mark-1 state after leaving ULPS. + */ +#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_STATUS_OUT - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_MASK (0x1U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_SHIFT (0U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_MASK) + +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_MASK (0x2U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_SHIFT (1U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_MASK) + +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_MASK (0x4U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_SHIFT (2U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_MASK) + +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_MASK (0x8U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_SHIFT (3U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_MASK) + +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_MASK (0x10U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_SHIFT (4U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_MASK) + +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_MASK (0x20U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_SHIFT (5U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_MASK) + +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_MASK (0x40U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_SHIFT (6U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_MASK) + +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_MASK (0x80U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_SHIFT (7U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_MASK) + +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_MASK (0x100U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_SHIFT (8U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_MASK) + +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_MASK (0x200U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_SHIFT (9U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_MASK) + +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_MASK (0x400U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_SHIFT (10U) +#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_MASK) +/*! @} */ + +/*! @name DSI_HOST_RX_ERROR_STATUS - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK (0x7FFU) +#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT (0U) +/*! dsi_host_rx_error_status - Status Register for Host receive error detection, ECC errors, CRC + * errors and for timeout indicators [0] ECC single bit error detected [1] ECC multi bit error + * detected [6:2] Errored bit position for single bit ECC error [7] CRC error detected [8] High Speed + * forward TX timeout detected [9] Reverse Low power data receive timeout detected [10] BTA + * timeout detected + */ +#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MIPI_DSI_HOST_Register_Masks */ + + +/* MIPI_DSI_HOST - Peripheral instance base addresses */ +/** Peripheral MIPI_DSI_HOST base address */ +#define MIPI_DSI_HOST_BASE (0x30A10000u) +/** Peripheral MIPI_DSI_HOST base pointer */ +#define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE) +/** Array initializer of MIPI_DSI_HOST peripheral base addresses */ +#define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST_BASE } +/** Array initializer of MIPI_DSI_HOST peripheral base pointers */ +#define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST } + +/*! + * @} + */ /* end of group MIPI_DSI_HOST_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MIPI_DSI_HOST_APB_PKT_IF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer MIPI_DSI_HOST_APB_PKT_IF Peripheral Access Layer + * @{ + */ + +/** MIPI_DSI_HOST_APB_PKT_IF - Register Layout Typedef */ +typedef struct { + __IO uint32_t DSI_HOST_TX_PAYLOAD; /**< , offset: 0x0 */ + __IO uint32_t DSI_HOST_PKT_CONTROL; /**< , offset: 0x4 */ + __IO uint32_t DSI_HOST_SEND_PACKET; /**< , offset: 0x8 */ + __I uint32_t DSI_HOST_PKT_STATUS; /**< , offset: 0xC */ + __I uint32_t DSI_HOST_PKT_FIFO_WR_LEVEL; /**< , offset: 0x10 */ + __I uint32_t DSI_HOST_PKT_FIFO_RD_LEVEL; /**< , offset: 0x14 */ + __I uint32_t DSI_HOST_PKT_RX_PAYLOAD; /**< , offset: 0x18 */ + __I uint32_t DSI_HOST_PKT_RX_PKT_HEADER; /**< , offset: 0x1C */ + __I uint32_t DSI_HOST_IRQ_STATUS; /**< , offset: 0x20 */ + __I uint32_t DSI_HOST_IRQ_STATUS2; /**< , offset: 0x24 */ + __IO uint32_t DSI_HOST_IRQ_MASK; /**< , offset: 0x28 */ + __IO uint32_t DSI_HOST_IRQ_MASK2; /**< , offset: 0x2C */ +} MIPI_DSI_HOST_APB_PKT_IF_Type; + +/* ---------------------------------------------------------------------------- + -- MIPI_DSI_HOST_APB_PKT_IF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_HOST_APB_PKT_IF_Register_Masks MIPI_DSI_HOST_APB_PKT_IF Register Masks + * @{ + */ + +/*! @name DSI_HOST_TX_PAYLOAD - */ +/*! @{ */ + +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK (0xFFFFFFFFU) +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT (0U) +/*! dsi_host_tx_payload - Tx Payload data write register. Writes to this registers load the payload fifo with 32 bit values. + */ +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK) +/*! @} */ + +/*! @name DSI_HOST_PKT_CONTROL - */ +/*! @{ */ + +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK (0x7FFFFFFU) +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT (0U) +/*! dsi_host_pkt_control - Tx packet control register. [15:0] - Packet word count [17:16] - Packet + * Virtual Channel [23:18] - Packet Header DSI Data Type [24] - Lp or HS select. 0 - LP mode, 1 - + * HS mode [25] - perform BTA after packet is sent [26] - perform BTA only, no packet tx + */ +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK) +/*! @} */ + +/*! @name DSI_HOST_SEND_PACKET - */ +/*! @{ */ + +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK (0x1U) +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT (0U) +/*! dsi_host_send_packet - Tx send packet. Writing to this register causes the packet described in dsi_host_pkt_control to be sent. + */ +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK) +/*! @} */ + +/*! @name DSI_HOST_PKT_STATUS - */ +/*! @{ */ + +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK (0x1FFU) +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT (0U) +/*! dsi_host_pkt_status - Status of APB to packet interface [0] - state machine not idle [1] - Tx + * packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow + * [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header + * has been received [8] - all rx packet payload data has been receive d + */ +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK) +/*! @} */ + +/*! @name DSI_HOST_PKT_FIFO_WR_LEVEL - */ +/*! @{ */ + +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK (0xFFFFU) +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT (0U) +/*! dsi_host_pkt_fifo_wr_level - Write level of APB to pkt interface fifo + */ +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK) +/*! @} */ + +/*! @name DSI_HOST_PKT_FIFO_RD_LEVEL - */ +/*! @{ */ + +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK (0xFFFFU) +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT (0U) +/*! dsi_host_pkt_fifo_rd_level - Read level of APB to pkt interface fifo + */ +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK) +/*! @} */ + +/*! @name DSI_HOST_PKT_RX_PAYLOAD - */ +/*! @{ */ + +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK (0xFFFFFFFFU) +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT (0U) +/*! dsi_host_pkt_rx_payload - APB to pkt interface rx payload read + */ +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK) +/*! @} */ + +/*! @name DSI_HOST_PKT_RX_PKT_HEADER - */ +/*! @{ */ + +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK (0xFFFFFFU) +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT (0U) +/*! dsi_host_pkt_rx_pkt_header - APB to pkt interface rx packet header [15:0] word count [21:16] data type [23:22] Virtual Channel + */ +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK) +/*! @} */ + +/*! @name DSI_HOST_IRQ_STATUS - */ +/*! @{ */ + +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK (0xFFFFFFFFU) +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT (0U) +/*! dsi_host_irq_status - Status of APB to packet interface [0] - state machine not idle [1] - Tx + * packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow + * [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header + * has been received [8] - all rx packet payload data has been received [28:9] - map directory to + * dsi host controller status_out port bit descriptions [29] - host bta timeout, host controller + * host_bta_timeout port [30] - low power rx timeout, host controller lp_rx_timeout port [31] - + * high speed tx timeout, host controller hs_tx_timeout port + */ +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK) +/*! @} */ + +/*! @name DSI_HOST_IRQ_STATUS2 - */ +/*! @{ */ + +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK (0x7U) +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT (0U) +/*! dsi_host_irq_status2 - Status of APB to packet interface part 2. Read part 2 first then + * dsi_host_irq_status. Reading dsi_host_irq_status will clear both status and status 2. [0] - single bit + * ecc error [1] - multi bit ecc error [2] - crc error + */ +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK) +/*! @} */ + +/*! @name DSI_HOST_IRQ_MASK - */ +/*! @{ */ + +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK (0xFFFFFFFFU) +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT (0U) +/*! dsi_host_irq_mask - irq mask [0] - state machine not idle [1] - Tx packet done [2] - dphy + * direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow [4] - tx fifo underflow [5] + * - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header has been received [8] - all + * rx packet payload data has been received [28:9] - map directory to dsi host controller + * status_out port bit descriptions [29] - host bta timeout, host controller host_bta_timeout port [30] + * - low power rx timeout, host controller lp_rx_timeout port [31] - high speed tx timeout, host + * controller hs_tx_timeout port + */ +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK) +/*! @} */ + +/*! @name DSI_HOST_IRQ_MASK2 - */ +/*! @{ */ + +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK (0x7U) +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT (0U) +/*! dsi_host_irq_mask2 - irq mask 2 [0] - single bit ecc error [1] - multi bit ecc error [2] - crc error + */ +#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MIPI_DSI_HOST_APB_PKT_IF_Register_Masks */ + + +/* MIPI_DSI_HOST_APB_PKT_IF - Peripheral instance base addresses */ +/** Peripheral MIPI_DSI_HOST_APB_PKT_IF base address */ +#define MIPI_DSI_HOST_APB_PKT_IF_BASE (0x30A10280u) +/** Peripheral MIPI_DSI_HOST_APB_PKT_IF base pointer */ +#define MIPI_DSI_HOST_APB_PKT_IF ((MIPI_DSI_HOST_APB_PKT_IF_Type *)MIPI_DSI_HOST_APB_PKT_IF_BASE) +/** Array initializer of MIPI_DSI_HOST_APB_PKT_IF peripheral base addresses */ +#define MIPI_DSI_HOST_APB_PKT_IF_BASE_ADDRS { MIPI_DSI_HOST_APB_PKT_IF_BASE } +/** Array initializer of MIPI_DSI_HOST_APB_PKT_IF peripheral base pointers */ +#define MIPI_DSI_HOST_APB_PKT_IF_BASE_PTRS { MIPI_DSI_HOST_APB_PKT_IF } + +/*! + * @} + */ /* end of group MIPI_DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MIPI_DSI_HOST_DPI_INTFC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_HOST_DPI_INTFC_Peripheral_Access_Layer MIPI_DSI_HOST_DPI_INTFC Peripheral Access Layer + * @{ + */ + +/** MIPI_DSI_HOST_DPI_INTFC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE; /**< , offset: 0x0 */ + __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL; /**< , offset: 0x4 */ + __IO uint32_t DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING; /**< , offset: 0x8 */ + __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FORMAT; /**< , offset: 0xC */ + __IO uint32_t DSI_HOST_CFG_DPI_VSYNC_POLARITY; /**< , offset: 0x10 */ + __IO uint32_t DSI_HOST_CFG_DPI_HSYNC_POLARITY; /**< , offset: 0x14 */ + __IO uint32_t DSI_HOST_CFG_DPI_VIDEO_MODE; /**< , offset: 0x18 */ + __IO uint32_t DSI_HOST_CFG_DPI_HFP; /**< , offset: 0x1C */ + __IO uint32_t DSI_HOST_CFG_DPI_HBP; /**< , offset: 0x20 */ + __IO uint32_t DSI_HOST_CFG_DPI_HSA; /**< , offset: 0x24 */ + __IO uint32_t DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS; /**< , offset: 0x28 */ + __IO uint32_t DSI_HOST_CFG_DPI_VBP; /**< , offset: 0x2C */ + __IO uint32_t DSI_HOST_CFG_DPI_VFP; /**< , offset: 0x30 */ + __IO uint32_t DSI_HOST_CFG_DPI_BLLP_MODE; /**< , offset: 0x34 */ + __IO uint32_t DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP; /**< , offset: 0x38 */ + __IO uint32_t DSI_HOST_CFG_DPI_VACTIVE; /**< , offset: 0x3C */ + __IO uint32_t DSI_HOST_CFG_DPI_VC; /**< , offset: 0x40 */ +} MIPI_DSI_HOST_DPI_INTFC_Type; + +/* ---------------------------------------------------------------------------- + -- MIPI_DSI_HOST_DPI_INTFC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_HOST_DPI_INTFC_Register_Masks MIPI_DSI_HOST_DPI_INTFC Register Masks + * @{ + */ + +/*! @name DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK (0xFFFFU) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT (0U) +/*! dsi_host_cfg_dpi_pixel_payload_size - Maximum number of pixels that should be sent as one DSI + * packet. Recommended that the line size (in pixels) is evenly divisible by this parameter (packet + * payload size in pixels). + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK (0xFFFFU) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT (0U) +/*! dsi_host_cfg_dpi_pixel_fifo_send_level - In order to optimize DSI utility, the DPI bridge + * buffers a cerntain number of DPI pixels before initiating a DSI packet. This configuration port + * controls the level at which the DPI Host bridge begins sending pixels. + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK (0x7U) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT (0U) +/*! dsi_host_cfg_dpi_interface_color_coding - Sets the distribution of RGB bits within the 24-bit d + * bus, as specified by the DPI specification. 0= 16-bit Configuration 1 1= 16-bit Configuration + * 2 2= 16-bit Configuration 3 3= 18-bit Configuration 1 4= 18-bit Configuration 2 5= 24-bit + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_PIXEL_FORMAT - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK (0x3U) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT (0U) +/*! dsi_host_cfg_dpi_pixel_format - Sets the DSI packet type of the pixels. 0 - 16 bit 1 - 18 bit 2 - 18 bit loosely packed 3 - 24 bit + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_VSYNC_POLARITY - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK (0x1U) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT (0U) +/*! dsi_host_cfg_dpi_vsync_polarity - Sets polarity of dpi_vsync_input 0 - active low 1 - active high + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_HSYNC_POLARITY - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK (0x1U) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT (0U) +/*! dsi_host_cfg_dpi_hsync_polarity - Sets polarity of dpi_hsync_input 0 - active low 1 - active high + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_VIDEO_MODE - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK (0x3U) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT (0U) +/*! dsi_host_cfg_dpi_video_mode - Select DSI video mode that the host DPI module should generate + * packets for. 2'b00 - Non-Burst mode with Sync Pulses 2'b01 - Non-Burst mode with Sync Events + * 2'b10 - Burst mode 2'b11 - Reserved, not valid + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_HFP - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK (0xFFFFU) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT (0U) +/*! dsi_host_cfg_dpi_hfp - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet. + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_HBP - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK (0xFFFFU) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT (0U) +/*! dsi_host_cfg_dpi_hbp - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet. + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_HSA - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK (0xFFFFU) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT (0U) +/*! dsi_host_cfg_dpi_hsa - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet. + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK (0x1U) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT (0U) +/*! dsi_host_cfg_dpi_enable_mult_pkts - Enable Multiple packets per video line. When enabled, + * cfg_dpi_pixel_payload_size must be set to exactly half the size of the video line. 0 - Video Line is + * sent in a single packet 1 - Video Line is sent in two packets + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_VBP - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK (0xFFU) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT (0U) +/*! dsi_host_cfg_dpi_vbp - Sets the number of lines in the vertical back porch. + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_VFP - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK (0xFFU) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT (0U) +/*! dsi_host_cfg_dpi_vfp - Sets the number of lines in the vertical front porch. + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_BLLP_MODE - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK (0x1U) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT (0U) +/*! dsi_host_cfg_dpi_bllp_mode - Optimize bllp periods to Low Power mode when possible 0 - blanking + * packets are sent during BLLP periods 1 - LP mode is used for BLLP periods + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK (0x1U) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT (0U) +/*! dsi_host_cfg_dpi_use_null_pkt_bllp - Selects type of blanking packet to be sent during bllp + * region 0 - Blanking packet used in bllp region 1 - Null packet used in bllp region + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_VACTIVE - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK (0x3FFFU) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT (0U) +/*! dsi_host_cfg_dpi_vactive - Sets the number of lines in the vertical active area. This field is + * equivalent to (real vertical size) - 1. For example, for an image of size 640x480, the bit + * field should be set as 479. + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK) +/*! @} */ + +/*! @name DSI_HOST_CFG_DPI_VC - */ +/*! @{ */ + +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK (0x3U) +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT (0U) +/*! dsi_host_cfg_dpi_vc - Sets the Virtual Channel (VC) of packets that will be sent to the receive + * packet interface. Packets with VC not equal to this value are discarded and the "DSI VC ID + * Invalid" bit (bit 12) in the DSI error report is set. + */ +#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MIPI_DSI_HOST_DPI_INTFC_Register_Masks */ + + +/* MIPI_DSI_HOST_DPI_INTFC - Peripheral instance base addresses */ +/** Peripheral MIPI_DSI_HOST_DPI_INTFC base address */ +#define MIPI_DSI_HOST_DPI_INTFC_BASE (0x30A10200u) +/** Peripheral MIPI_DSI_HOST_DPI_INTFC base pointer */ +#define MIPI_DSI_HOST_DPI_INTFC ((MIPI_DSI_HOST_DPI_INTFC_Type *)MIPI_DSI_HOST_DPI_INTFC_BASE) +/** Array initializer of MIPI_DSI_HOST_DPI_INTFC peripheral base addresses */ +#define MIPI_DSI_HOST_DPI_INTFC_BASE_ADDRS { MIPI_DSI_HOST_DPI_INTFC_BASE } +/** Array initializer of MIPI_DSI_HOST_DPI_INTFC peripheral base pointers */ +#define MIPI_DSI_HOST_DPI_INTFC_BASE_PTRS { MIPI_DSI_HOST_DPI_INTFC } + +/*! + * @} + */ /* end of group MIPI_DSI_HOST_DPI_INTFC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Peripheral_Access_Layer MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Peripheral Access Layer + * @{ + */ + +/** MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DPHY_PD_DPHY; /**< , offset: 0x0 */ + __IO uint32_t DPHY_M_PRG_HS_PREPARE; /**< , offset: 0x4 */ + __IO uint32_t DPHY_MC_PRG_HS_PREPARE; /**< , offset: 0x8 */ + __IO uint32_t DPHY_M_PRG_HS_ZERO; /**< , offset: 0xC */ + __IO uint32_t DPHY_MC_PRG_HS_ZERO; /**< , offset: 0x10 */ + __IO uint32_t DPHY_M_PRG_HS_TRAIL; /**< , offset: 0x14 */ + __IO uint32_t DPHY_MC_PRG_HS_TRAIL; /**< , offset: 0x18 */ + __IO uint32_t DPHY_PD_PLL; /**< , offset: 0x1C */ + __IO uint32_t DPHY_TST; /**< , offset: 0x20 */ + __IO uint32_t DPHY_CN; /**< , offset: 0x24 */ + __IO uint32_t DPHY_CM; /**< , offset: 0x28 */ + __IO uint32_t DPHY_CO; /**< , offset: 0x2C */ + __I uint32_t DPHY_LOCK; /**< , offset: 0x30 */ + __IO uint32_t DPHY_LOCK_BYP; /**< , offset: 0x34 */ + __IO uint32_t DPHY_RTERM_SEL; /**< , offset: 0x38 */ + __IO uint32_t DPHY_AUTO_PD_EN; /**< , offset: 0x3C */ + __IO uint32_t DPHY_RXLPRP; /**< , offset: 0x40 */ + __IO uint32_t DPHY_RXCDRP; /**< , offset: 0x44 */ +} MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Type; + +/* ---------------------------------------------------------------------------- + -- MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Register_Masks MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Register Masks + * @{ + */ + +/*! @name DPHY_PD_DPHY - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_MASK (0x1U) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_SHIFT (0U) +/*! dphy_pd_dphy - DPHY PD_DPHY input control. Detailed information about this parameter programming + * is available in the MIPI-DSI DPHY section. + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_MASK) +/*! @} */ + +/*! @name DPHY_M_PRG_HS_PREPARE - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK (0x3U) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT (0U) +/*! dphy_m_prg_hs_prepare - DPHY m_PRG_HS_PREPARE input. Detailed information about this parameter + * programming is available in the MIPI-DSI DPHY section. + * 0b00..1 + * 0b01..1.5 + * 0b10..2 + * 0b11..2.5 + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK) +/*! @} */ + +/*! @name DPHY_MC_PRG_HS_PREPARE - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK (0x1U) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT (0U) +/*! dphy_mc_prg_hs_prepare - DPHY mc_PRG_HS_PREPARE input. Detailed information about this parameter + * programming is available in the MIPI-DSI DPHY section. + * 0b0..1 + * 0b1..1.5 + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK) +/*! @} */ + +/*! @name DPHY_M_PRG_HS_ZERO - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK (0x1FU) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT (0U) +/*! dphy_m_prg_hs_zero - DPHY m_PRG_HS_ZERO input. Detailed information about this parameter + * programming is available in the MIPI-DSI DPHY section. + * 0b00000..0 + * 0b00001..1 + * 0b00010..2 + * 0b00011..3 + * 0b00100..4 + * 0b00101..5 + * 0b00110..6 + * 0b00111..7 + * 0b01000..8 + * 0b01001..9 + * 0b01010..10 + * 0b01011..11 + * 0b01100..12 + * 0b01101..13 + * 0b01110..14 + * 0b01111..15 + * 0b10000..16 + * 0b10001..17 + * 0b10010..18 + * 0b10011..19 + * 0b10100..20 + * 0b10101..21 + * 0b10110..22 + * 0b10111..23 + * 0b11000..24 + * 0b11001..25 + * 0b11010..26 + * 0b11011..27 + * 0b11100..28 + * 0b11101..29 + * 0b11110..30 + * 0b11111..31 + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK) +/*! @} */ + +/*! @name DPHY_MC_PRG_HS_ZERO - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK (0x3FU) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT (0U) +/*! dphy_mc_prg_hs_zero - DPHY mc_PRG_HS_ZERO input. Detailed information about this parameter + * programming is available in the MIPI-DSI DPHY section. + * 0b100000..32 + * 0b100001..33 + * 0b100010..34 + * 0b100011..35 + * 0b100100..36 + * 0b100101..37 + * 0b100110..38 + * 0b100111..39 + * 0b101000..40 + * 0b101001..41 + * 0b101010..42 + * 0b101011..43 + * 0b101100..44 + * 0b101101..45 + * 0b101110..46 + * 0b101111..47 + * 0b110000..48 + * 0b110001..49 + * 0b110010..50 + * 0b110011..51 + * 0b110100..52 + * 0b110101..53 + * 0b110110..54 + * 0b110111..55 + * 0b111000..56 + * 0b111001..57 + * 0b111010..58 + * 0b111011..59 + * 0b111100..60 + * 0b111101..61 + * 0b111110..62 + * 0b111111..63 + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK) +/*! @} */ + +/*! @name DPHY_M_PRG_HS_TRAIL - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK (0xFU) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT (0U) +/*! dphy_m_prg_hs_trail - DPHY m_PRG_HS_TRAIL input. Detailed information about this parameter + * programming is available in the MIPI-DSI DPHY section. + * 0b0000..0 + * 0b0001..1 + * 0b0010..2 + * 0b0011..3 + * 0b0100..4 + * 0b0101..5 + * 0b0110..6 + * 0b0111..7 + * 0b1000..8 + * 0b1001..9 + * 0b1010..10 + * 0b1011..11 + * 0b1100..12 + * 0b1101..13 + * 0b1110..14 + * 0b1111..15 + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK) +/*! @} */ + +/*! @name DPHY_MC_PRG_HS_TRAIL - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK (0xFU) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT (0U) +/*! dphy_mc_prg_hs_trail - DPHY mc_PRG_HS_TRAIL input. Detailed information about this parameter + * programming is available in the MIPI-DSI DPHY section. + * 0b0000..0 + * 0b0001..1 + * 0b0010..2 + * 0b0011..3 + * 0b0100..4 + * 0b0101..5 + * 0b0110..6 + * 0b0111..7 + * 0b1000..8 + * 0b1001..9 + * 0b1010..10 + * 0b1011..11 + * 0b1100..12 + * 0b1101..13 + * 0b1110..14 + * 0b1111..15 + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK) +/*! @} */ + +/*! @name DPHY_PD_PLL - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_MASK (0x1U) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_SHIFT (0U) +/*! PD - DPHY PD_PLL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_MASK) +/*! @} */ + +/*! @name DPHY_TST - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_MASK (0x3FU) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_SHIFT (0U) +/*! TST - DPHY TST input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_MASK) +/*! @} */ + +/*! @name DPHY_CN - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_MASK (0x1FU) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_SHIFT (0U) +/*! CN + * 0b11111..Divide by 1 + * 0b00000..Divide by 2 + * 0b10000..Divide by 3 + * 0b11000..Divide by 4 + * 0b11100..Divide by 5 + * 0b01110..Divide by 6 + * 0b00111..Divide by 7 + * 0b10011..Divide by 8 + * 0b01001..Divide by 9 + * 0b00100..Divide by 10 + * 0b00010..Divide by 11 + * 0b10001..Divide by 12 + * 0b01000..Divide by 13 + * 0b10100..Divide by 14 + * 0b01010..Divide by 15 + * 0b10101..Divide by 16 + * 0b11010..Divide by 17 + * 0b11101..Divide by 18 + * 0b11110..Divide by 19 + * 0b01111..Divide by 20 + * 0b10111..Divide by 21 + * 0b11011..Divide by 22 + * 0b01101..Divide by 23 + * 0b10110..Divide by 24 + * 0b01011..Divide by 25 + * 0b00101..Divide by 26 + * 0b10010..Divide by 27 + * 0b11001..Divide by 28 + * 0b01100..Divide by 29 + * 0b00110..Divide by 30 + * 0b00011..Divide by 31 + * 0b00001..Divide by 32 + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_MASK) +/*! @} */ + +/*! @name DPHY_CM - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_MASK (0xFFU) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_SHIFT (0U) +/*! CM + * 0b111x0000..Divide by 16 + * 0b111x1111..Divide by 31 + * 0b11000000..Divide by 32 + * 0b11011111..Divide by 63 + * 0b10000000..Divide by 64 + * 0b10111111..Divide by 127 + * 0b00000000..Divide by 128 + * 0b01111111..Divide by 255 + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_MASK) +/*! @} */ + +/*! @name DPHY_CO - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_MASK (0x3U) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_SHIFT (0U) +/*! CO + * 0b00..Divide by 1 + * 0b01..Divide by 2 + * 0b10..Divide by 4 + * 0b11..Divide by 8 + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_MASK) +/*! @} */ + +/*! @name DPHY_LOCK - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_MASK (0x1U) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_SHIFT (0U) +/*! LOCK - DPHY PLL LOCK output. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_MASK) +/*! @} */ + +/*! @name DPHY_LOCK_BYP - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_MASK (0x1U) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT (0U) +/*! dphy_lock_byp - DPHY LOCK_BYP input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_MASK) +/*! @} */ + +/*! @name DPHY_RTERM_SEL - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_MASK (0x1U) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_SHIFT (0U) +/*! dphy_rterm_sel - DPHY RTERM_SEL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_MASK) +/*! @} */ + +/*! @name DPHY_AUTO_PD_EN - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK (0x1U) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT (0U) +/*! dphy_auto_pd_en - DPHY AUTO_PD_EN input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK) +/*! @} */ + +/*! @name DPHY_RXLPRP - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_MASK (0x3U) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_SHIFT (0U) +/*! dphy_rxlprp - DPHY RXLPRP input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_MASK) +/*! @} */ + +/*! @name DPHY_RXCDRP - */ +/*! @{ */ + +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_MASK (0x3U) +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_SHIFT (0U) +/*! dphy_rxcdrp - DPHY RXCDRP input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Register_Masks */ + + +/* MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC - Peripheral instance base addresses */ +/** Peripheral MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC base address */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE (0x30A10300u) +/** Peripheral MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC base pointer */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC ((MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Type *)MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE) +/** Array initializer of MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC peripheral base + * addresses */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE_ADDRS { MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE } +/** Array initializer of MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC peripheral base + * pointers */ +#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE_PTRS { MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC } + +/*! + * @} + */ /* end of group MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Peripheral_Access_Layer */ + +/*! + * @brief Power mode on the other side definition. + */ +typedef enum _mu_power_mode +{ + kMU_PowerModeRun = 0x00U, /*!< Run mode. */ + kMU_PowerModeWait = 0x01U, /*!< WAIT mode. */ + kMU_PowerModeStop = 0x03U, /*!< STOP mode. */ +} mu_power_mode_t; + + +/* ---------------------------------------------------------------------------- + -- MU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer + * @{ + */ + +/** MU - Register Layout Typedef */ +typedef struct { + __IO uint32_t TR[4]; /**< Processor B Transmit Register 0..Processor B Transmit Register 3, array offset: 0x0, array step: 0x4 */ + __I uint32_t RR[4]; /**< Processor B Receive Register 0..Processor B Receive Register 3, array offset: 0x10, array step: 0x4 */ + __IO uint32_t SR; /**< Processor B Status Register, offset: 0x20 */ + __IO uint32_t CR; /**< Processor B Control Register, offset: 0x24 */ +} MU_Type; + +/* ---------------------------------------------------------------------------- + -- MU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Register_Masks MU Register Masks + * @{ + */ + +/*! @name TR - Processor B Transmit Register 0..Processor B Transmit Register 3 */ +/*! @{ */ + +#define MU_TR_BTR0_MASK (0xFFFFFFFFU) +#define MU_TR_BTR0_SHIFT (0U) +#define MU_TR_BTR0(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR0_SHIFT)) & MU_TR_BTR0_MASK) + +#define MU_TR_BTR1_MASK (0xFFFFFFFFU) +#define MU_TR_BTR1_SHIFT (0U) +#define MU_TR_BTR1(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR1_SHIFT)) & MU_TR_BTR1_MASK) + +#define MU_TR_BTR2_MASK (0xFFFFFFFFU) +#define MU_TR_BTR2_SHIFT (0U) +#define MU_TR_BTR2(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK) + +#define MU_TR_BTR3_MASK (0xFFFFFFFFU) +#define MU_TR_BTR3_SHIFT (0U) +#define MU_TR_BTR3(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR3_SHIFT)) & MU_TR_BTR3_MASK) +/*! @} */ + +/* The count of MU_TR */ +#define MU_TR_COUNT (4U) + +/*! @name RR - Processor B Receive Register 0..Processor B Receive Register 3 */ +/*! @{ */ + +#define MU_RR_BRR0_MASK (0xFFFFFFFFU) +#define MU_RR_BRR0_SHIFT (0U) +#define MU_RR_BRR0(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR0_SHIFT)) & MU_RR_BRR0_MASK) + +#define MU_RR_BRR1_MASK (0xFFFFFFFFU) +#define MU_RR_BRR1_SHIFT (0U) +#define MU_RR_BRR1(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR1_SHIFT)) & MU_RR_BRR1_MASK) + +#define MU_RR_BRR2_MASK (0xFFFFFFFFU) +#define MU_RR_BRR2_SHIFT (0U) +#define MU_RR_BRR2(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR2_SHIFT)) & MU_RR_BRR2_MASK) + +#define MU_RR_BRR3_MASK (0xFFFFFFFFU) +#define MU_RR_BRR3_SHIFT (0U) +#define MU_RR_BRR3(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR3_SHIFT)) & MU_RR_BRR3_MASK) +/*! @} */ + +/* The count of MU_RR */ +#define MU_RR_COUNT (4U) + +/*! @name SR - Processor B Status Register */ +/*! @{ */ + +#define MU_SR_Fn_MASK (0x7U) +#define MU_SR_Fn_SHIFT (0U) +/*! Fn + * 0b000..ABFn bit in ACR register is written 0 (default). + * 0b001..ABFn bit in ACR register is written 1. + */ +#define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK) + +#define MU_SR_EP_MASK (0x10U) +#define MU_SR_EP_SHIFT (4U) +/*! EP + * 0b0..The Processor B-side event is not pending (default). + * 0b1..The Processor B-side event is pending. + */ +#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) + +#define MU_SR_APM_MASK (0x60U) +#define MU_SR_APM_SHIFT (5U) +/*! APM + * 0b00..The System is in Run Mode. + * 0b01..The System is in WAIT Mode. + * 0b10..Reserved. + * 0b11..The System is in STOP Mode. + */ +#define MU_SR_APM(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_APM_SHIFT)) & MU_SR_APM_MASK) + +#define MU_SR_ARS_MASK (0x80U) +#define MU_SR_ARS_SHIFT (7U) +/*! ARS + * 0b0..The Processor A or the Processor A-side of the MU is not in reset. + * 0b1..The Processor A or the Processor A-side of the MU is in reset. + */ +#define MU_SR_ARS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_ARS_SHIFT)) & MU_SR_ARS_MASK) + +#define MU_SR_FUP_MASK (0x100U) +#define MU_SR_FUP_SHIFT (8U) +/*! FUP + * 0b0..No flags updated, initiated by the Processor B, in progress (default) + * 0b1..Processor B initiated flags update, processing + */ +#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) + +#define MU_SR_TEn_MASK (0xF00000U) +#define MU_SR_TEn_SHIFT (20U) +/*! TEn + * 0b0000..BTRn register is not empty. + * 0b0001..BTRn register is empty (default). + */ +#define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK) + +#define MU_SR_RFn_MASK (0xF000000U) +#define MU_SR_RFn_SHIFT (24U) +/*! RFn + * 0b0000..BRRn register is not full (default). + * 0b0001..BRRn register has received data from ATRn register and is ready to be read by the Processor B. + */ +#define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK) + +#define MU_SR_GIPn_MASK (0xF0000000U) +#define MU_SR_GIPn_SHIFT (28U) +/*! GIPn + * 0b0000..Processor B general purpose interrupt n is not pending. (default) + * 0b0001..Processor B general purpose interrupt n is pending. + */ +#define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK) +/*! @} */ + +/*! @name CR - Processor B Control Register */ +/*! @{ */ + +#define MU_CR_BAFn_MASK (0x7U) +#define MU_CR_BAFn_SHIFT (0U) +/*! BAFn + * 0b000..Clears the Fn bit in the ASR register. + * 0b001..Sets the Fn bit in the ASR register. + */ +#define MU_CR_BAFn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BAFn_SHIFT)) & MU_CR_BAFn_MASK) + +#define MU_CR_HRM_MASK (0x10U) +#define MU_CR_HRM_SHIFT (4U) +/*! HRM + * 0b0..BHR bit in ACR is not masked, enables the hardware reset to the Processor B (default after hardware reset). + * 0b1..BHR bit in ACR is masked, disables the hardware reset request to the Processor B. + */ +#define MU_CR_HRM(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_HRM_SHIFT)) & MU_CR_HRM_MASK) + +#define MU_CR_GIRn_MASK (0xF0000U) +#define MU_CR_GIRn_SHIFT (16U) +/*! GIRn + * 0b0000..Processor B General Interrupt n is not requested to the Processor A (default). + * 0b0001..Processor B General Interrupt n is requested to the Processor A. + */ +#define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK) + +#define MU_CR_TIEn_MASK (0xF00000U) +#define MU_CR_TIEn_SHIFT (20U) +/*! TIEn + * 0b0000..Disables Processor B Transmit Interrupt n. (default) + * 0b0001..Enables Processor B Transmit Interrupt n. + */ +#define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK) + +#define MU_CR_RIEn_MASK (0xF000000U) +#define MU_CR_RIEn_SHIFT (24U) +/*! RIEn + * 0b0000..Disables Processor B Receive Interrupt n. (default) + * 0b0001..Enables Processor B Receive Interrupt n. + */ +#define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK) + +#define MU_CR_GIEn_MASK (0xF0000000U) +#define MU_CR_GIEn_SHIFT (28U) +/*! GIEn + * 0b0000..Disables Processor B General Interrupt n. (default) + * 0b0001..Enables Processor B General Interrupt n. + */ +#define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MU_Register_Masks */ + + +/* MU - Peripheral instance base addresses */ +/** Peripheral MUB base address */ +#define MUB_BASE (0x30AB0000u) +/** Peripheral MUB base pointer */ +#define MUB ((MU_Type *)MUB_BASE) +/** Array initializer of MU peripheral base addresses */ +#define MU_BASE_ADDRS { MUB_BASE } +/** Array initializer of MU peripheral base pointers */ +#define MU_BASE_PTRS { MUB } +/** Interrupt vectors for the MU peripheral type */ +#define MU_IRQS { MU_M4_IRQn } +/* Backward compatibility */ +#define MU_SR_PM_MASK MU_SR_APM_MASK +#define MU_SR_PM_SHIFT MU_SR_APM_SHIFT +#define MU_SR_PM(x) MU_SR_APM(x) +#define MU_SR_RS_MASK MU_SR_ARS_MASK +#define MU_SR_RS_SHIFT MU_SR_ARS_SHIFT +#define MU_SR_RS(x) MU_SR_ARS(x) +#define MU_CR_Fn_MASK MU_CR_BAFn_MASK +#define MU_CR_Fn_SHIFT MU_CR_BAFn_SHIFT +#define MU_CR_Fn(x) MU_CR_BAFn(x) + + +/*! + * @} + */ /* end of group MU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OCOTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer + * @{ + */ + +/** OCOTP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ + __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */ + uint8_t RESERVED_3[12]; + __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ + __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ + __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ + __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ + uint8_t RESERVED_5[32]; + __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */ + uint8_t RESERVED_6[876]; + __I uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ + uint8_t RESERVED_7[12]; + __IO uint32_t TESTER0; /**< Value of OTP Bank0 Word1 (Tester Info.), offset: 0x410 */ + uint8_t RESERVED_8[12]; + __IO uint32_t TESTER1; /**< Value of OTP Bank0 Word2 (tester Info.), offset: 0x420 */ + uint8_t RESERVED_9[12]; + __IO uint32_t TESTER2; /**< Value of OTP Bank0 Word3 (Tester Info.), offset: 0x430 */ + uint8_t RESERVED_10[12]; + __IO uint32_t TESTER3; /**< Value of OTP Bank1 Word0 (Tester Info.), offset: 0x440 */ + uint8_t RESERVED_11[12]; + __IO uint32_t TESTER4; /**< Value of OTP Bank1 Word1 (Tester Info.), offset: 0x450 */ + uint8_t RESERVED_12[12]; + __IO uint32_t TESTER5; /**< Value of OTP Bank1 Word2 (Tester Info.), offset: 0x460 */ + uint8_t RESERVED_13[12]; + __IO uint32_t BOOT_CFG0; /**< Value of OTP Bank1 Word3 (Boot Configuration Info.), offset: 0x470 */ + uint8_t RESERVED_14[12]; + __IO uint32_t BOOT_CFG1; /**< Value of OTP Bank2 Word0 (Boot Configuration Info.), offset: 0x480 */ + uint8_t RESERVED_15[12]; + __IO uint32_t BOOT_CFG2; /**< Value of OTP Bank2 Word1 (Boot Configuration Info.), offset: 0x490 */ + uint8_t RESERVED_16[12]; + __IO uint32_t BOOT_CFG3; /**< Value of OTP Bank2 Word2 (Boot Configuration Info.), offset: 0x4A0 */ + uint8_t RESERVED_17[12]; + __IO uint32_t BOOT_CFG4; /**< Value of OTP Bank2 Word3 (BOOT Configuration Info.), offset: 0x4B0 */ + uint8_t RESERVED_18[12]; + __IO uint32_t MEM_TRIM0; /**< Value of OTP Bank3 Word0 (Memory Related Info.), offset: 0x4C0 */ + uint8_t RESERVED_19[12]; + __IO uint32_t MEM_TRIM1; /**< Value of OTP Bank3 Word1 (Memory Related Info.), offset: 0x4D0 */ + uint8_t RESERVED_20[12]; + __IO uint32_t ANA0; /**< Value of OTP Bank3 Word2 (Analog Info.), offset: 0x4E0 */ + uint8_t RESERVED_21[12]; + __IO uint32_t ANA1; /**< Value of OTP Bank3 Word3 (Analog Info.), offset: 0x4F0 */ + uint8_t RESERVED_22[140]; + __IO uint32_t SRK0; /**< Shadow Register for OTP Bank6 Word0 (SRK Hash), offset: 0x580 */ + uint8_t RESERVED_23[12]; + __IO uint32_t SRK1; /**< Shadow Register for OTP Bank6 Word1 (SRK Hash), offset: 0x590 */ + uint8_t RESERVED_24[12]; + __IO uint32_t SRK2; /**< Shadow Register for OTP Bank6 Word2 (SRK Hash), offset: 0x5A0 */ + uint8_t RESERVED_25[12]; + __IO uint32_t SRK3; /**< Shadow Register for OTP Bank6 Word3 (SRK Hash), offset: 0x5B0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t SRK4; /**< Shadow Register for OTP Bank7 Word0 (SRK Hash), offset: 0x5C0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t SRK5; /**< Shadow Register for OTP Bank7 Word1 (SRK Hash), offset: 0x5D0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t SRK6; /**< Shadow Register for OTP Bank7 Word2 (SRK Hash), offset: 0x5E0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t SRK7; /**< Shadow Register for OTP Bank7 Word3 (SRK Hash), offset: 0x5F0 */ + uint8_t RESERVED_30[12]; + __IO uint32_t SJC_RESP0; /**< Value of OTP Bank8 Word0 (Secure JTAG Response Field), offset: 0x600 */ + uint8_t RESERVED_31[12]; + __IO uint32_t SJC_RESP1; /**< Value of OTP Bank8 Word1 (Secure JTAG Response Field), offset: 0x610 */ + uint8_t RESERVED_32[12]; + __IO uint32_t USB_ID; /**< Value of OTP Bank8 Word2 (USB ID info), offset: 0x620 */ + uint8_t RESERVED_33[12]; + __IO uint32_t FIELD_RETURN; /**< Value of OTP Bank5 Word6 (Field Return), offset: 0x630 */ + uint8_t RESERVED_34[12]; + __IO uint32_t MAC_ADDR0; /**< Value of OTP Bank9 Word0 (MAC Address), offset: 0x640 */ + uint8_t RESERVED_35[12]; + __IO uint32_t MAC_ADDR1; /**< Value of OTP Bank9 Word1 (MAC Address), offset: 0x650 */ + uint8_t RESERVED_36[12]; + __IO uint32_t MAC_ADDR2; /**< Value of OTP Bank9 Word2 (MAC Address), offset: 0x660 */ + uint8_t RESERVED_37[12]; + __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank9 Word3 (SRK Revoke), offset: 0x670 */ + uint8_t RESERVED_38[12]; + __IO uint32_t MAU_KEY0; /**< Shadow Register for OTP Bank10 Word0 (MAU Key), offset: 0x680 */ + uint8_t RESERVED_39[12]; + __IO uint32_t MAU_KEY1; /**< Shadow Register for OTP Bank10 Word1 (MAU Key), offset: 0x690 */ + uint8_t RESERVED_40[12]; + __IO uint32_t MAU_KEY2; /**< Shadow Register for OTP Bank10 Word2 (MAU Key), offset: 0x6A0 */ + uint8_t RESERVED_41[12]; + __IO uint32_t MAU_KEY3; /**< Shadow Register for OTP Bank10 Word3 (MAU Key), offset: 0x6B0 */ + uint8_t RESERVED_42[12]; + __IO uint32_t MAU_KEY4; /**< Shadow Register for OTP Bank11 Word0 (MAU Key), offset: 0x6C0 */ + uint8_t RESERVED_43[12]; + __IO uint32_t MAU_KEY5; /**< Shadow Register for OTP Bank11 Word1 (MAU Key), offset: 0x6D0 */ + uint8_t RESERVED_44[12]; + __IO uint32_t MAU_KEY6; /**< Shadow Register for OTP Bank11 Word2 (MAU Key), offset: 0x6E0 */ + uint8_t RESERVED_45[12]; + __IO uint32_t MAU_KEY7; /**< Shadow Register for OTP Bank11 Word3 (MAU Key), offset: 0x6F0 */ + uint8_t RESERVED_46[140]; + __IO uint32_t GP10; /**< Value of OTP Bank14 Word0 (), offset: 0x780 */ + uint8_t RESERVED_47[12]; + __IO uint32_t GP11; /**< Value of OTP Bank14 Word1 (), offset: 0x790 */ + uint8_t RESERVED_48[12]; + __IO uint32_t GP20; /**< Value of OTP Bank14 Word2 (), offset: 0x7A0 */ + uint8_t RESERVED_49[12]; + __IO uint32_t GP21; /**< Value of OTP Bank14 Word3 (), offset: 0x7B0 */ + uint8_t RESERVED_50[12]; + __IO uint32_t GP_CRC0; /**< Value of OTP Bank15 Word0 (CRC Key), offset: 0x7C0 */ + uint8_t RESERVED_51[12]; + __IO uint32_t GP_CRC1; /**< Value of OTP Bank15 Word1 (CRC Key), offset: 0x7D0 */ + uint8_t RESERVED_52[12]; + __IO uint32_t GP_CRC2; /**< Value of OTP Bank15 Word2 (CRC Key), offset: 0x7E0 */ + uint8_t RESERVED_53[12]; + __IO uint32_t GROUP_MASK; /**< Value of OTP Bank15 Word3 (CRC Key), offset: 0x7F0 */ + uint8_t RESERVED_54[12]; + __IO uint32_t HDMI_FW_SRK0; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x800 */ + uint8_t RESERVED_55[12]; + __IO uint32_t HDMI_FW_SRK1; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x810 */ + uint8_t RESERVED_56[12]; + __IO uint32_t HDMI_FW_SRK2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x820 */ + uint8_t RESERVED_57[12]; + __IO uint32_t HDMI_FW_SRK3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x830 */ + uint8_t RESERVED_58[12]; + __IO uint32_t HDMI_FW_SRK4; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x840 */ + uint8_t RESERVED_59[12]; + __IO uint32_t HDMI_FW_SRK5; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x850 */ + uint8_t RESERVED_60[12]; + __IO uint32_t HDMI_FW_SRK6; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x860 */ + uint8_t RESERVED_61[12]; + __IO uint32_t HDMI_FW_SRK7; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x870 */ + uint8_t RESERVED_62[12]; + __IO uint32_t HDMI_KMEK0; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x880 */ + uint8_t RESERVED_63[12]; + __IO uint32_t HDMI_KMEK1; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x890 */ + uint8_t RESERVED_64[12]; + __IO uint32_t HDMI_KMEK2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x8A0 */ + uint8_t RESERVED_65[12]; + __IO uint32_t HDMI_KMEK3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x8B0 */ + uint8_t RESERVED_66[76]; + __IO uint32_t HDCP_TX_CONS0; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x900 */ + uint8_t RESERVED_67[12]; + __IO uint32_t HDCP_TX_CONS1; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x910 */ + uint8_t RESERVED_68[12]; + __IO uint32_t HDCP_TX_CONS2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x920 */ + uint8_t RESERVED_69[12]; + __IO uint32_t HDCP_TX_CONS3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x930 */ + uint8_t RESERVED_70[12]; + __IO uint32_t HDCP_TX_CERT0; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x940 */ + uint8_t RESERVED_71[12]; + __IO uint32_t HDCP_TX_CERT1; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x950 */ + uint8_t RESERVED_72[12]; + __IO uint32_t HDCP_TX_CERT2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x960 */ + uint8_t RESERVED_73[12]; + __IO uint32_t HDCP_TX_CERT3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x970 */ + uint8_t RESERVED_74[12]; + __IO uint32_t HDCP_TX_CERT4; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x980 */ + uint8_t RESERVED_75[12]; + __IO uint32_t HDCP_TX_CERT5; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x990 */ + uint8_t RESERVED_76[12]; + __IO uint32_t HDCP_TX_CERT6; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x9A0 */ + uint8_t RESERVED_77[12]; + __IO uint32_t HDCP_TX_CERT7; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x9B0 */ + uint8_t RESERVED_78[12]; + __IO uint32_t HDCP_TX_CERT8; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x9C0 */ + uint8_t RESERVED_79[12]; + __IO uint32_t HDCP_TX_CERT9; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x9D0 */ + uint8_t RESERVED_80[12]; + __IO uint32_t HDCP_TX_CERT10; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x9E0 */ + uint8_t RESERVED_81[12]; + __IO uint32_t HDCP_TX_CERT11; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x9F0 */ + uint8_t RESERVED_82[12]; + __IO uint32_t HDCP_TX_CERT12; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA00 */ + uint8_t RESERVED_83[12]; + __IO uint32_t HDCP_TX_CERT13; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xA10 */ + uint8_t RESERVED_84[12]; + __IO uint32_t HDCP_TX_CERT14; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA20 */ + uint8_t RESERVED_85[12]; + __IO uint32_t HDCP_TX_CERT15; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA30 */ + uint8_t RESERVED_86[12]; + __IO uint32_t HDCP_TX_CERT16; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xA40 */ + uint8_t RESERVED_87[12]; + __IO uint32_t HDCP_TX_CERT17; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xA50 */ + uint8_t RESERVED_88[12]; + __IO uint32_t HDCP_TX_CERT18; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA60 */ + uint8_t RESERVED_89[12]; + __IO uint32_t HDCP_TX_CERT19; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA70 */ + uint8_t RESERVED_90[12]; + __IO uint32_t HDCP_TX_CERT20; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA80 */ + uint8_t RESERVED_91[12]; + __IO uint32_t HDCP_TX_CERT21; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA90 */ + uint8_t RESERVED_92[12]; + __IO uint32_t HDCP_TX_CERT22; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xAA0 */ + uint8_t RESERVED_93[12]; + __IO uint32_t HDCP_TX_CERT23; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xAB0 */ + uint8_t RESERVED_94[12]; + __IO uint32_t HDCP_TX_CERT24; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xAC0 */ + uint8_t RESERVED_95[12]; + __IO uint32_t HDCP_TX_CERT25; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xAD0 */ + uint8_t RESERVED_96[12]; + __IO uint32_t HDCP_TX_CERT26; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xAE0 */ + uint8_t RESERVED_97[12]; + __IO uint32_t HDCP_TX_CERT27; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xAF0 */ + uint8_t RESERVED_98[12]; + __IO uint32_t HDCP_TX_CERT28; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB00 */ + uint8_t RESERVED_99[12]; + __IO uint32_t HDCP_TX_CERT29; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xB10 */ + uint8_t RESERVED_100[12]; + __IO uint32_t HDCP_TX_CERT30; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB20 */ + uint8_t RESERVED_101[12]; + __IO uint32_t HDCP_TX_CERT31; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB30 */ + uint8_t RESERVED_102[12]; + __IO uint32_t HDCP_TX_CERT32; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xB40 */ + uint8_t RESERVED_103[12]; + __IO uint32_t HDCP_TX_CERT33; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xB50 */ + uint8_t RESERVED_104[12]; + __IO uint32_t HDCP_TX_CERT34; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB60 */ + uint8_t RESERVED_105[12]; + __IO uint32_t HDCP_TX_CERT35; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB70 */ + uint8_t RESERVED_106[12]; + __IO uint32_t HDCP_TX_CERT36; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB80 */ + uint8_t RESERVED_107[12]; + __IO uint32_t HDCP_TX_CERT37; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB90 */ + uint8_t RESERVED_108[12]; + __IO uint32_t HDCP_TX_CERT38; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xBA0 */ + uint8_t RESERVED_109[12]; + __IO uint32_t HDCP_TX_CERT39; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xBB0 */ + uint8_t RESERVED_110[12]; + __IO uint32_t HDCP_TX_CERT40; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xBC0 */ + uint8_t RESERVED_111[12]; + __IO uint32_t HDCP_TX_CERT41; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xBD0 */ + uint8_t RESERVED_112[12]; + __IO uint32_t HDCP_TX_CERT42; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xBE0 */ + uint8_t RESERVED_113[12]; + __IO uint32_t HDCP_TX_CERT43; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xBF0 */ + uint8_t RESERVED_114[12]; + __IO uint32_t HDCP_TX_CERT44; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC00 */ + uint8_t RESERVED_115[12]; + __IO uint32_t HDCP_TX_CERT45; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xC10 */ + uint8_t RESERVED_116[12]; + __IO uint32_t HDCP_TX_CERT46; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC20 */ + uint8_t RESERVED_117[12]; + __IO uint32_t HDCP_TX_CERT47; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC30 */ + uint8_t RESERVED_118[12]; + __IO uint32_t HDCP_TX_CERT48; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xC40 */ + uint8_t RESERVED_119[12]; + __IO uint32_t HDCP_TX_CERT49; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xC50 */ + uint8_t RESERVED_120[12]; + __IO uint32_t HDCP_TX_CERT50; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC60 */ + uint8_t RESERVED_121[12]; + __IO uint32_t HDCP_TX_CERT51; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC70 */ + uint8_t RESERVED_122[12]; + __IO uint32_t HDCP_TX_CERT52; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC80 */ + uint8_t RESERVED_123[12]; + __IO uint32_t HDCP_TX_CERT53; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC90 */ + uint8_t RESERVED_124[12]; + __IO uint32_t HDCP_TX_CERT54; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xCA0 */ + uint8_t RESERVED_125[12]; + __IO uint32_t HDCP_TX_CERT55; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xCB0 */ + uint8_t RESERVED_126[12]; + __IO uint32_t HDCP_TX_CERT56; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xCC0 */ + uint8_t RESERVED_127[12]; + __IO uint32_t HDCP_TX_CERT57; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xCD0 */ + uint8_t RESERVED_128[12]; + __IO uint32_t HDCP_TX_CERT58; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xCE0 */ + uint8_t RESERVED_129[12]; + __IO uint32_t HDCP_TX_CERT59; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xCF0 */ + uint8_t RESERVED_130[12]; + __IO uint32_t HDCP_TX_CERT60; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD00 */ + uint8_t RESERVED_131[12]; + __IO uint32_t HDCP_TX_CERT61; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xD10 */ + uint8_t RESERVED_132[12]; + __IO uint32_t HDCP_TX_CERT62; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD20 */ + uint8_t RESERVED_133[12]; + __IO uint32_t HDCP_TX_CERT63; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD30 */ + uint8_t RESERVED_134[12]; + __IO uint32_t HDCP_TX_CERT64; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xD40 */ + uint8_t RESERVED_135[12]; + __IO uint32_t HDCP_TX_CERT65; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xD50 */ + uint8_t RESERVED_136[12]; + __IO uint32_t HDCP_TX_CERT66; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD60 */ + uint8_t RESERVED_137[12]; + __IO uint32_t HDCP_TX_CERT67; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD70 */ + uint8_t RESERVED_138[12]; + __IO uint32_t HDCP_TX_CERT68; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD80 */ + uint8_t RESERVED_139[12]; + __IO uint32_t HDCP_TX_CERT69; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD90 */ + uint8_t RESERVED_140[12]; + __IO uint32_t HDCP_TX_CERT70; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xDA0 */ + uint8_t RESERVED_141[12]; + __IO uint32_t HDCP_TX_CERT71; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xDB0 */ + uint8_t RESERVED_142[12]; + __IO uint32_t HDCP_TX_CERT72; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xDC0 */ + uint8_t RESERVED_143[12]; + __IO uint32_t HDCP_TX_CERT73; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xDD0 */ + uint8_t RESERVED_144[12]; + __IO uint32_t HDCP_TX_CERT74; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xDE0 */ + uint8_t RESERVED_145[12]; + __IO uint32_t HDCP_TX_CERT75; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xDF0 */ + uint8_t RESERVED_146[12]; + __IO uint32_t HDCP_TX_CERT76; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE00 */ + uint8_t RESERVED_147[12]; + __IO uint32_t HDCP_TX_CERT77; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xE10 */ + uint8_t RESERVED_148[12]; + __IO uint32_t HDCP_TX_CERT78; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE20 */ + uint8_t RESERVED_149[12]; + __IO uint32_t HDCP_TX_CERT79; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE30 */ + uint8_t RESERVED_150[12]; + __IO uint32_t HDCP_TX_CERT80; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xE40 */ + uint8_t RESERVED_151[12]; + __IO uint32_t HDCP_TX_CERT81; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xE50 */ + uint8_t RESERVED_152[12]; + __IO uint32_t HDCP_TX_CERT82; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE60 */ + uint8_t RESERVED_153[12]; + __IO uint32_t HDCP_TX_CERT83; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE70 */ + uint8_t RESERVED_154[12]; + __IO uint32_t HDCP_TX_CERT84; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE80 */ + uint8_t RESERVED_155[12]; + __IO uint32_t HDCP_TX_CERT85; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE90 */ + uint8_t RESERVED_156[12]; + __IO uint32_t HDCP_TX_CERT86; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xEA0 */ + uint8_t RESERVED_157[12]; + __IO uint32_t HDCP_TX_CERT87; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xEB0 */ + uint8_t RESERVED_158[12]; + __IO uint32_t HDCP_TX_CERT88; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xEC0 */ + uint8_t RESERVED_159[12]; + __IO uint32_t HDCP_TX_CERT89; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xED0 */ + uint8_t RESERVED_160[12]; + __IO uint32_t HDCP_TX_CERT90; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xEE0 */ + uint8_t RESERVED_161[12]; + __IO uint32_t HDCP_TX_CERT91; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xEF0 */ + uint8_t RESERVED_162[12]; + __IO uint32_t HDCP_TX_CERT92; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF00 */ + uint8_t RESERVED_163[12]; + __IO uint32_t HDCP_TX_CERT93; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xF10 */ + uint8_t RESERVED_164[12]; + __IO uint32_t HDCP_TX_CERT94; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF20 */ + uint8_t RESERVED_165[12]; + __IO uint32_t HDCP_TX_CERT95; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF30 */ + uint8_t RESERVED_166[12]; + __IO uint32_t HDCP_KEY0; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xF40 */ + uint8_t RESERVED_167[12]; + __IO uint32_t HDCP_KEY1; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xF50 */ + uint8_t RESERVED_168[12]; + __IO uint32_t HDCP_KEY2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF60 */ + uint8_t RESERVED_169[12]; + __IO uint32_t HDCP_KEY3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF70 */ + uint8_t RESERVED_170[12]; + __IO uint32_t HDCP_KEY4; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF80 */ + uint8_t RESERVED_171[12]; + __IO uint32_t HDCP_KEY5; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF90 */ + uint8_t RESERVED_172[12]; + __IO uint32_t HDCP_KEY6; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xFA0 */ + uint8_t RESERVED_173[12]; + __IO uint32_t HDCP_KEY7; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xFB0 */ + uint8_t RESERVED_174[12]; + __IO uint32_t HDCP_KEY8; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xFC0 */ + uint8_t RESERVED_175[12]; + __IO uint32_t HDCP_KEY9; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xFD0 */ + uint8_t RESERVED_176[12]; + __IO uint32_t HDCP_KEY10; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xFE0 */ + uint8_t RESERVED_177[12]; + __IO uint32_t HDCP_KEY11; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xFF0 */ + uint8_t RESERVED_178[12]; + __IO uint32_t HDCP_KEY12; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1000 */ + uint8_t RESERVED_179[12]; + __IO uint32_t HDCP_KEY13; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x1010 */ + uint8_t RESERVED_180[12]; + __IO uint32_t HDCP_KEY14; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1020 */ + uint8_t RESERVED_181[12]; + __IO uint32_t HDCP_KEY15; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1030 */ + uint8_t RESERVED_182[12]; + __IO uint32_t HDCP_KEY16; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x1040 */ + uint8_t RESERVED_183[12]; + __IO uint32_t HDCP_KEY17; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x1050 */ + uint8_t RESERVED_184[12]; + __IO uint32_t HDCP_KEY18; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1060 */ + uint8_t RESERVED_185[12]; + __IO uint32_t HDCP_KEY19; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1070 */ + uint8_t RESERVED_186[12]; + __IO uint32_t HDCP_KEY20; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1080 */ + uint8_t RESERVED_187[12]; + __IO uint32_t HDCP_KEY21; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1090 */ + uint8_t RESERVED_188[12]; + __IO uint32_t HDCP_KEY22; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x10A0 */ + uint8_t RESERVED_189[12]; + __IO uint32_t HDCP_KEY23; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x10B0 */ + uint8_t RESERVED_190[12]; + __IO uint32_t HDCP_KEY24; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x10C0 */ + uint8_t RESERVED_191[12]; + __IO uint32_t HDCP_KEY25; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x10D0 */ + uint8_t RESERVED_192[12]; + __IO uint32_t HDCP_KEY26; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x10E0 */ + uint8_t RESERVED_193[12]; + __IO uint32_t HDCP_KEY27; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x10F0 */ + uint8_t RESERVED_194[12]; + __IO uint32_t HDCP_KEY28; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1100 */ + uint8_t RESERVED_195[12]; + __IO uint32_t HDCP_KEY29; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x1110 */ + uint8_t RESERVED_196[12]; + __IO uint32_t HDCP_KEY30; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1120 */ + uint8_t RESERVED_197[12]; + __IO uint32_t HDCP_KEY31; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1130 */ + uint8_t RESERVED_198[12]; + __IO uint32_t HDCP_KEY32; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x1140 */ + uint8_t RESERVED_199[12]; + __IO uint32_t HDCP_KEY33; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x1150 */ + uint8_t RESERVED_200[12]; + __IO uint32_t HDCP_KEY34; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1160 */ + uint8_t RESERVED_201[12]; + __IO uint32_t HDCP_KEY35; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1170 */ + uint8_t RESERVED_202[12]; + __IO uint32_t HDCP_KEY36; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1180 */ + uint8_t RESERVED_203[12]; + __IO uint32_t HDCP_KEY37; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1190 */ + uint8_t RESERVED_204[12]; + __IO uint32_t HDCP_KEY38; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x11A0 */ + uint8_t RESERVED_205[12]; + __IO uint32_t HDCP_KEY39; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x11B0 */ + uint8_t RESERVED_206[12]; + __IO uint32_t HDCP_KEY40; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x11C0 */ + uint8_t RESERVED_207[12]; + __IO uint32_t HDCP_KEY41; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x11D0 */ + uint8_t RESERVED_208[12]; + __IO uint32_t HDCP_KEY42; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x11E0 */ + uint8_t RESERVED_209[12]; + __IO uint32_t HDCP_KEY43; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x11F0 */ + uint8_t RESERVED_210[12]; + __IO uint32_t HDCP_KEY44; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1200 */ + uint8_t RESERVED_211[12]; + __IO uint32_t HDCP_KEY45; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x1210 */ + uint8_t RESERVED_212[12]; + __IO uint32_t HDCP_KEY46; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1220 */ + uint8_t RESERVED_213[12]; + __IO uint32_t HDCP_KEY47; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1230 */ + uint8_t RESERVED_214[12]; + __IO uint32_t HDCP_KEY48; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x1240 */ + uint8_t RESERVED_215[12]; + __IO uint32_t HDCP_KEY49; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x1250 */ + uint8_t RESERVED_216[12]; + __IO uint32_t HDCP_KEY50; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1260 */ + uint8_t RESERVED_217[12]; + __IO uint32_t HDCP_KEY51; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1270 */ + uint8_t RESERVED_218[12]; + __IO uint32_t HDCP_KEY52; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1280 */ + uint8_t RESERVED_219[12]; + __IO uint32_t HDCP_KEY53; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1290 */ + uint8_t RESERVED_220[12]; + __IO uint32_t HDCP_KEY54; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x12A0 */ + uint8_t RESERVED_221[12]; + __IO uint32_t HDCP_KEY55; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x12B0 */ + uint8_t RESERVED_222[12]; + __IO uint32_t HDCP_KEY56; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x12C0 */ + uint8_t RESERVED_223[12]; + __IO uint32_t HDCP_KEY57; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x12D0 */ + uint8_t RESERVED_224[12]; + __IO uint32_t HDCP_KEY58; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x12E0 */ + uint8_t RESERVED_225[12]; + __IO uint32_t HDCP_KEY59; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x12F0 */ + uint8_t RESERVED_226[12]; + __IO uint32_t HDCP_KEY60; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1300 */ + uint8_t RESERVED_227[12]; + __IO uint32_t HDCP_KEY61; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x1310 */ + uint8_t RESERVED_228[12]; + __IO uint32_t HDCP_KEY62; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1320 */ + uint8_t RESERVED_229[12]; + __IO uint32_t HDCP_KEY63; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1330 */ + uint8_t RESERVED_230[12]; + __IO uint32_t HDCP_KEY64; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x1340 */ + uint8_t RESERVED_231[12]; + __IO uint32_t HDCP_KEY65; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x1350 */ + uint8_t RESERVED_232[12]; + __IO uint32_t HDCP_KEY66; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1360 */ + uint8_t RESERVED_233[12]; + __IO uint32_t HDCP_KEY67; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1370 */ + uint8_t RESERVED_234[12]; + __IO uint32_t HDCP_KEY68; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1380 */ + uint8_t RESERVED_235[12]; + __IO uint32_t HDCP_KEY69; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1390 */ + uint8_t RESERVED_236[12]; + __IO uint32_t HDCP_KEY70; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x13A0 */ + uint8_t RESERVED_237[12]; + __IO uint32_t HDCP_KEY71; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x13B0 */ +} OCOTP_Type; + +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/*! @name CTRL - OTP Controller Control Register */ +/*! @{ */ + +#define OCOTP_CTRL_ADDR_MASK (0xFFU) +#define OCOTP_CTRL_ADDR_SHIFT (0U) +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) + +#define OCOTP_CTRL_BUSY_MASK (0x100U) +#define OCOTP_CTRL_BUSY_SHIFT (8U) +#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) + +#define OCOTP_CTRL_ERROR_MASK (0x200U) +#define OCOTP_CTRL_ERROR_SHIFT (9U) +#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) + +#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) + +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_SET - OTP Controller Control Register */ +/*! @{ */ + +#define OCOTP_CTRL_SET_ADDR_MASK (0xFFU) +#define OCOTP_CTRL_SET_ADDR_SHIFT (0U) +#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) + +#define OCOTP_CTRL_SET_BUSY_MASK (0x100U) +#define OCOTP_CTRL_SET_BUSY_SHIFT (8U) +#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) + +#define OCOTP_CTRL_SET_ERROR_MASK (0x200U) +#define OCOTP_CTRL_SET_ERROR_SHIFT (9U) +#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) + +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) + +#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_CLR - OTP Controller Control Register */ +/*! @{ */ + +#define OCOTP_CTRL_CLR_ADDR_MASK (0xFFU) +#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) +#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) + +#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U) +#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U) +#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) + +#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U) +#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U) +#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) + +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) + +#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_TOG - OTP Controller Control Register */ +/*! @{ */ + +#define OCOTP_CTRL_TOG_ADDR_MASK (0xFFU) +#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) +#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) + +#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U) +#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U) +#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) + +#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U) +#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U) +#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) + +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) + +#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name TIMING - OTP Controller Timing Register */ +/*! @{ */ + +#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) +#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) +#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) + +#define OCOTP_TIMING_RELAX_MASK (0xF000U) +#define OCOTP_TIMING_RELAX_SHIFT (12U) +#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK) + +#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U) +#define OCOTP_TIMING_STROBE_READ_SHIFT (16U) +#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK) + +#define OCOTP_TIMING_WAIT_MASK (0xFC00000U) +#define OCOTP_TIMING_WAIT_SHIFT (22U) +#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) + +#define OCOTP_TIMING_RSRVD0_MASK (0xF0000000U) +#define OCOTP_TIMING_RSRVD0_SHIFT (28U) +#define OCOTP_TIMING_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RSRVD0_SHIFT)) & OCOTP_TIMING_RSRVD0_MASK) +/*! @} */ + +/*! @name DATA - OTP Controller Write Data Register */ +/*! @{ */ + +#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_DATA_DATA_SHIFT (0U) +#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) +/*! @} */ + +/*! @name READ_CTRL - OTP Controller Write Data Register */ +/*! @{ */ + +#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) +#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) +#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) + +#define OCOTP_READ_CTRL_RSVD0_MASK (0xFFFFFFFEU) +#define OCOTP_READ_CTRL_RSVD0_SHIFT (1U) +#define OCOTP_READ_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_RSVD0_SHIFT)) & OCOTP_READ_CTRL_RSVD0_MASK) +/*! @} */ + +/*! @name READ_FUSE_DATA - OTP Controller Read Data Register */ +/*! @{ */ + +#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) +#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) +/*! @} */ + +/*! @name SW_STICKY - Sticky bit Register */ +/*! @{ */ + +#define OCOTP_SW_STICKY_RSVD0_MASK (0x1U) +#define OCOTP_SW_STICKY_RSVD0_SHIFT (0U) +#define OCOTP_SW_STICKY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD0_SHIFT)) & OCOTP_SW_STICKY_RSVD0_MASK) + +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK) + +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) + +#define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK) + +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK) + +#define OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_MASK (0x20U) +#define OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_SHIFT (5U) +#define OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_MASK) + +#define OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_MASK (0x40U) +#define OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_SHIFT (6U) +#define OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_MASK) + +#define OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_MASK (0x80U) +#define OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_SHIFT (7U) +#define OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_MASK) + +#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_MASK (0x100U) +#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_SHIFT (8U) +#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_MASK) + +#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_MASK (0x200U) +#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_SHIFT (9U) +#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_MASK) + +#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_MASK (0x400U) +#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_SHIFT (10U) +#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_MASK) + +#define OCOTP_SW_STICKY_RSVD1_MASK (0xFFFFF800U) +#define OCOTP_SW_STICKY_RSVD1_SHIFT (11U) +#define OCOTP_SW_STICKY_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD1_SHIFT)) & OCOTP_SW_STICKY_RSVD1_MASK) +/*! @} */ + +/*! @name SCS - Software Controllable Signals Register */ +/*! @{ */ + +#define OCOTP_SCS_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) + +#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SPARE_SHIFT (1U) +#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK) + +#define OCOTP_SCS_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_LOCK_SHIFT (31U) +#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) +/*! @} */ + +/*! @name SCS_SET - Software Controllable Signals Register */ +/*! @{ */ + +#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) + +#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SET_SPARE_SHIFT (1U) +#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK) + +#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_SET_LOCK_SHIFT (31U) +#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) +/*! @} */ + +/*! @name SCS_CLR - Software Controllable Signals Register */ +/*! @{ */ + +#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) + +#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_CLR_SPARE_SHIFT (1U) +#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK) + +#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_CLR_LOCK_SHIFT (31U) +#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) +/*! @} */ + +/*! @name SCS_TOG - Software Controllable Signals Register */ +/*! @{ */ + +#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) + +#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_TOG_SPARE_SHIFT (1U) +#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK) + +#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_TOG_LOCK_SHIFT (31U) +#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) +/*! @} */ + +/*! @name VERSION - OTP Controller Version Register */ +/*! @{ */ + +#define OCOTP_VERSION_STEP_MASK (0xFFFFU) +#define OCOTP_VERSION_STEP_SHIFT (0U) +#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) + +#define OCOTP_VERSION_MINOR_MASK (0xFF0000U) +#define OCOTP_VERSION_MINOR_SHIFT (16U) +#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) + +#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) +#define OCOTP_VERSION_MAJOR_SHIFT (24U) +#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ +/*! @{ */ + +#define OCOTP_LOCK_TESTER_MASK (0x3U) +#define OCOTP_LOCK_TESTER_SHIFT (0U) +#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) + +#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU) +#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U) +#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK) + +#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U) +#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U) +#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK) + +#define OCOTP_LOCK_ANALOG_MASK (0xC0U) +#define OCOTP_LOCK_ANALOG_SHIFT (6U) +#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK) + +#define OCOTP_LOCK_OTPMK_MASK (0x100U) +#define OCOTP_LOCK_OTPMK_SHIFT (8U) +#define OCOTP_LOCK_OTPMK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_SHIFT)) & OCOTP_LOCK_OTPMK_MASK) + +#define OCOTP_LOCK_SRK_MASK (0x200U) +#define OCOTP_LOCK_SRK_SHIFT (9U) +#define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK) + +#define OCOTP_LOCK_SJC_RESP_MASK (0x400U) +#define OCOTP_LOCK_SJC_RESP_SHIFT (10U) +#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK) + +#define OCOTP_LOCK_GROUP_MASK_MASK (0x800U) +#define OCOTP_LOCK_GROUP_MASK_SHIFT (11U) +#define OCOTP_LOCK_GROUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GROUP_MASK_SHIFT)) & OCOTP_LOCK_GROUP_MASK_MASK) + +#define OCOTP_LOCK_USB_ID_MASK (0x3000U) +#define OCOTP_LOCK_USB_ID_SHIFT (12U) +#define OCOTP_LOCK_USB_ID(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_USB_ID_SHIFT)) & OCOTP_LOCK_USB_ID_MASK) + +#define OCOTP_LOCK_MAC_ADDR_MASK (0xC000U) +#define OCOTP_LOCK_MAC_ADDR_SHIFT (14U) +#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK) + +#define OCOTP_LOCK_MAU_KEY_MASK (0x10000U) +#define OCOTP_LOCK_MAU_KEY_SHIFT (16U) +#define OCOTP_LOCK_MAU_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAU_KEY_SHIFT)) & OCOTP_LOCK_MAU_KEY_MASK) + +#define OCOTP_LOCK_ROM_PATCH_MASK (0x20000U) +#define OCOTP_LOCK_ROM_PATCH_SHIFT (17U) +#define OCOTP_LOCK_ROM_PATCH(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ROM_PATCH_SHIFT)) & OCOTP_LOCK_ROM_PATCH_MASK) + +#define OCOTP_LOCK_GP_CRC_MASK (0xC0000U) +#define OCOTP_LOCK_GP_CRC_SHIFT (18U) +#define OCOTP_LOCK_GP_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP_CRC_SHIFT)) & OCOTP_LOCK_GP_CRC_MASK) + +#define OCOTP_LOCK_GP1_MASK (0x300000U) +#define OCOTP_LOCK_GP1_SHIFT (20U) +#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK) + +#define OCOTP_LOCK_GP2_MASK (0xC00000U) +#define OCOTP_LOCK_GP2_SHIFT (22U) +#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) + +#define OCOTP_LOCK_HDMI_KEY_MASK (0x3000000U) +#define OCOTP_LOCK_HDMI_KEY_SHIFT (24U) +#define OCOTP_LOCK_HDMI_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_HDMI_KEY_SHIFT)) & OCOTP_LOCK_HDMI_KEY_MASK) + +#define OCOTP_LOCK_HDMI_CRC_MASK (0xC000000U) +#define OCOTP_LOCK_HDMI_CRC_SHIFT (26U) +#define OCOTP_LOCK_HDMI_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_HDMI_CRC_SHIFT)) & OCOTP_LOCK_HDMI_CRC_MASK) + +#define OCOTP_LOCK_HDCP_KEY_MASK (0x30000000U) +#define OCOTP_LOCK_HDCP_KEY_SHIFT (28U) +#define OCOTP_LOCK_HDCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_HDCP_KEY_SHIFT)) & OCOTP_LOCK_HDCP_KEY_MASK) + +#define OCOTP_LOCK_HDCP_CRC_MASK (0xC0000000U) +#define OCOTP_LOCK_HDCP_CRC_SHIFT (30U) +#define OCOTP_LOCK_HDCP_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_HDCP_CRC_SHIFT)) & OCOTP_LOCK_HDCP_CRC_MASK) +/*! @} */ + +/*! @name TESTER0 - Value of OTP Bank0 Word1 (Tester Info.) */ +/*! @{ */ + +#define OCOTP_TESTER0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_TESTER0_BITS_SHIFT (0U) +#define OCOTP_TESTER0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER0_BITS_SHIFT)) & OCOTP_TESTER0_BITS_MASK) +/*! @} */ + +/*! @name TESTER1 - Value of OTP Bank0 Word2 (tester Info.) */ +/*! @{ */ + +#define OCOTP_TESTER1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_TESTER1_BITS_SHIFT (0U) +#define OCOTP_TESTER1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER1_BITS_SHIFT)) & OCOTP_TESTER1_BITS_MASK) +/*! @} */ + +/*! @name TESTER2 - Value of OTP Bank0 Word3 (Tester Info.) */ +/*! @{ */ + +#define OCOTP_TESTER2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_TESTER2_BITS_SHIFT (0U) +#define OCOTP_TESTER2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER2_BITS_SHIFT)) & OCOTP_TESTER2_BITS_MASK) +/*! @} */ + +/*! @name TESTER3 - Value of OTP Bank1 Word0 (Tester Info.) */ +/*! @{ */ + +#define OCOTP_TESTER3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_TESTER3_BITS_SHIFT (0U) +#define OCOTP_TESTER3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER3_BITS_SHIFT)) & OCOTP_TESTER3_BITS_MASK) +/*! @} */ + +/*! @name TESTER4 - Value of OTP Bank1 Word1 (Tester Info.) */ +/*! @{ */ + +#define OCOTP_TESTER4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_TESTER4_BITS_SHIFT (0U) +#define OCOTP_TESTER4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER4_BITS_SHIFT)) & OCOTP_TESTER4_BITS_MASK) +/*! @} */ + +/*! @name TESTER5 - Value of OTP Bank1 Word2 (Tester Info.) */ +/*! @{ */ + +#define OCOTP_TESTER5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_TESTER5_BITS_SHIFT (0U) +#define OCOTP_TESTER5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER5_BITS_SHIFT)) & OCOTP_TESTER5_BITS_MASK) +/*! @} */ + +/*! @name BOOT_CFG0 - Value of OTP Bank1 Word3 (Boot Configuration Info.) */ +/*! @{ */ + +#define OCOTP_BOOT_CFG0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_BOOT_CFG0_BITS_SHIFT (0U) +#define OCOTP_BOOT_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG0_BITS_SHIFT)) & OCOTP_BOOT_CFG0_BITS_MASK) +/*! @} */ + +/*! @name BOOT_CFG1 - Value of OTP Bank2 Word0 (Boot Configuration Info.) */ +/*! @{ */ + +#define OCOTP_BOOT_CFG1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_BOOT_CFG1_BITS_SHIFT (0U) +#define OCOTP_BOOT_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG1_BITS_SHIFT)) & OCOTP_BOOT_CFG1_BITS_MASK) +/*! @} */ + +/*! @name BOOT_CFG2 - Value of OTP Bank2 Word1 (Boot Configuration Info.) */ +/*! @{ */ + +#define OCOTP_BOOT_CFG2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_BOOT_CFG2_BITS_SHIFT (0U) +#define OCOTP_BOOT_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG2_BITS_SHIFT)) & OCOTP_BOOT_CFG2_BITS_MASK) +/*! @} */ + +/*! @name BOOT_CFG3 - Value of OTP Bank2 Word2 (Boot Configuration Info.) */ +/*! @{ */ + +#define OCOTP_BOOT_CFG3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_BOOT_CFG3_BITS_SHIFT (0U) +#define OCOTP_BOOT_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG3_BITS_SHIFT)) & OCOTP_BOOT_CFG3_BITS_MASK) +/*! @} */ + +/*! @name BOOT_CFG4 - Value of OTP Bank2 Word3 (BOOT Configuration Info.) */ +/*! @{ */ + +#define OCOTP_BOOT_CFG4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_BOOT_CFG4_BITS_SHIFT (0U) +#define OCOTP_BOOT_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG4_BITS_SHIFT)) & OCOTP_BOOT_CFG4_BITS_MASK) +/*! @} */ + +/*! @name MEM_TRIM0 - Value of OTP Bank3 Word0 (Memory Related Info.) */ +/*! @{ */ + +#define OCOTP_MEM_TRIM0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM_TRIM0_BITS_SHIFT (0U) +#define OCOTP_MEM_TRIM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM_TRIM0_BITS_SHIFT)) & OCOTP_MEM_TRIM0_BITS_MASK) +/*! @} */ + +/*! @name MEM_TRIM1 - Value of OTP Bank3 Word1 (Memory Related Info.) */ +/*! @{ */ + +#define OCOTP_MEM_TRIM1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM_TRIM1_BITS_SHIFT (0U) +#define OCOTP_MEM_TRIM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM_TRIM1_BITS_SHIFT)) & OCOTP_MEM_TRIM1_BITS_MASK) +/*! @} */ + +/*! @name ANA0 - Value of OTP Bank3 Word2 (Analog Info.) */ +/*! @{ */ + +#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA0_BITS_SHIFT (0U) +#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) +/*! @} */ + +/*! @name ANA1 - Value of OTP Bank3 Word3 (Analog Info.) */ +/*! @{ */ + +#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA1_BITS_SHIFT (0U) +#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) +/*! @} */ + +/*! @name SRK0 - Shadow Register for OTP Bank6 Word0 (SRK Hash) */ +/*! @{ */ + +#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK0_BITS_SHIFT (0U) +#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) +/*! @} */ + +/*! @name SRK1 - Shadow Register for OTP Bank6 Word1 (SRK Hash) */ +/*! @{ */ + +#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK1_BITS_SHIFT (0U) +#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) +/*! @} */ + +/*! @name SRK2 - Shadow Register for OTP Bank6 Word2 (SRK Hash) */ +/*! @{ */ + +#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK2_BITS_SHIFT (0U) +#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) +/*! @} */ + +/*! @name SRK3 - Shadow Register for OTP Bank6 Word3 (SRK Hash) */ +/*! @{ */ + +#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK3_BITS_SHIFT (0U) +#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) +/*! @} */ + +/*! @name SRK4 - Shadow Register for OTP Bank7 Word0 (SRK Hash) */ +/*! @{ */ + +#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK4_BITS_SHIFT (0U) +#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) +/*! @} */ + +/*! @name SRK5 - Shadow Register for OTP Bank7 Word1 (SRK Hash) */ +/*! @{ */ + +#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK5_BITS_SHIFT (0U) +#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) +/*! @} */ + +/*! @name SRK6 - Shadow Register for OTP Bank7 Word2 (SRK Hash) */ +/*! @{ */ + +#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK6_BITS_SHIFT (0U) +#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) +/*! @} */ + +/*! @name SRK7 - Shadow Register for OTP Bank7 Word3 (SRK Hash) */ +/*! @{ */ + +#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK7_BITS_SHIFT (0U) +#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) +/*! @} */ + +/*! @name SJC_RESP0 - Value of OTP Bank8 Word0 (Secure JTAG Response Field) */ +/*! @{ */ + +#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP0_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) +/*! @} */ + +/*! @name SJC_RESP1 - Value of OTP Bank8 Word1 (Secure JTAG Response Field) */ +/*! @{ */ + +#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP1_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) +/*! @} */ + +/*! @name USB_ID - Value of OTP Bank8 Word2 (USB ID info) */ +/*! @{ */ + +#define OCOTP_USB_ID_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_USB_ID_BITS_SHIFT (0U) +#define OCOTP_USB_ID_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_USB_ID_BITS_SHIFT)) & OCOTP_USB_ID_BITS_MASK) +/*! @} */ + +/*! @name FIELD_RETURN - Value of OTP Bank5 Word6 (Field Return) */ +/*! @{ */ + +#define OCOTP_FIELD_RETURN_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_FIELD_RETURN_BITS_SHIFT (0U) +#define OCOTP_FIELD_RETURN_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FIELD_RETURN_BITS_SHIFT)) & OCOTP_FIELD_RETURN_BITS_MASK) +/*! @} */ + +/*! @name MAC_ADDR0 - Value of OTP Bank9 Word0 (MAC Address) */ +/*! @{ */ + +#define OCOTP_MAC_ADDR0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC_ADDR0_BITS_SHIFT (0U) +#define OCOTP_MAC_ADDR0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC_ADDR0_BITS_SHIFT)) & OCOTP_MAC_ADDR0_BITS_MASK) +/*! @} */ + +/*! @name MAC_ADDR1 - Value of OTP Bank9 Word1 (MAC Address) */ +/*! @{ */ + +#define OCOTP_MAC_ADDR1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC_ADDR1_BITS_SHIFT (0U) +#define OCOTP_MAC_ADDR1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC_ADDR1_BITS_SHIFT)) & OCOTP_MAC_ADDR1_BITS_MASK) +/*! @} */ + +/*! @name MAC_ADDR2 - Value of OTP Bank9 Word2 (MAC Address) */ +/*! @{ */ + +#define OCOTP_MAC_ADDR2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC_ADDR2_BITS_SHIFT (0U) +#define OCOTP_MAC_ADDR2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC_ADDR2_BITS_SHIFT)) & OCOTP_MAC_ADDR2_BITS_MASK) +/*! @} */ + +/*! @name SRK_REVOKE - Value of OTP Bank9 Word3 (SRK Revoke) */ +/*! @{ */ + +#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) +#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) +/*! @} */ + +/*! @name MAU_KEY0 - Shadow Register for OTP Bank10 Word0 (MAU Key) */ +/*! @{ */ + +#define OCOTP_MAU_KEY0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAU_KEY0_BITS_SHIFT (0U) +#define OCOTP_MAU_KEY0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY0_BITS_SHIFT)) & OCOTP_MAU_KEY0_BITS_MASK) +/*! @} */ + +/*! @name MAU_KEY1 - Shadow Register for OTP Bank10 Word1 (MAU Key) */ +/*! @{ */ + +#define OCOTP_MAU_KEY1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAU_KEY1_BITS_SHIFT (0U) +#define OCOTP_MAU_KEY1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY1_BITS_SHIFT)) & OCOTP_MAU_KEY1_BITS_MASK) +/*! @} */ + +/*! @name MAU_KEY2 - Shadow Register for OTP Bank10 Word2 (MAU Key) */ +/*! @{ */ + +#define OCOTP_MAU_KEY2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAU_KEY2_BITS_SHIFT (0U) +#define OCOTP_MAU_KEY2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY2_BITS_SHIFT)) & OCOTP_MAU_KEY2_BITS_MASK) +/*! @} */ + +/*! @name MAU_KEY3 - Shadow Register for OTP Bank10 Word3 (MAU Key) */ +/*! @{ */ + +#define OCOTP_MAU_KEY3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAU_KEY3_BITS_SHIFT (0U) +#define OCOTP_MAU_KEY3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY3_BITS_SHIFT)) & OCOTP_MAU_KEY3_BITS_MASK) +/*! @} */ + +/*! @name MAU_KEY4 - Shadow Register for OTP Bank11 Word0 (MAU Key) */ +/*! @{ */ + +#define OCOTP_MAU_KEY4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAU_KEY4_BITS_SHIFT (0U) +#define OCOTP_MAU_KEY4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY4_BITS_SHIFT)) & OCOTP_MAU_KEY4_BITS_MASK) +/*! @} */ + +/*! @name MAU_KEY5 - Shadow Register for OTP Bank11 Word1 (MAU Key) */ +/*! @{ */ + +#define OCOTP_MAU_KEY5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAU_KEY5_BITS_SHIFT (0U) +#define OCOTP_MAU_KEY5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY5_BITS_SHIFT)) & OCOTP_MAU_KEY5_BITS_MASK) +/*! @} */ + +/*! @name MAU_KEY6 - Shadow Register for OTP Bank11 Word2 (MAU Key) */ +/*! @{ */ + +#define OCOTP_MAU_KEY6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAU_KEY6_BITS_SHIFT (0U) +#define OCOTP_MAU_KEY6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY6_BITS_SHIFT)) & OCOTP_MAU_KEY6_BITS_MASK) +/*! @} */ + +/*! @name MAU_KEY7 - Shadow Register for OTP Bank11 Word3 (MAU Key) */ +/*! @{ */ + +#define OCOTP_MAU_KEY7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAU_KEY7_BITS_SHIFT (0U) +#define OCOTP_MAU_KEY7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY7_BITS_SHIFT)) & OCOTP_MAU_KEY7_BITS_MASK) +/*! @} */ + +/*! @name GP10 - Value of OTP Bank14 Word0 () */ +/*! @{ */ + +#define OCOTP_GP10_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP10_BITS_SHIFT (0U) +#define OCOTP_GP10_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP10_BITS_SHIFT)) & OCOTP_GP10_BITS_MASK) +/*! @} */ + +/*! @name GP11 - Value of OTP Bank14 Word1 () */ +/*! @{ */ + +#define OCOTP_GP11_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP11_BITS_SHIFT (0U) +#define OCOTP_GP11_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP11_BITS_SHIFT)) & OCOTP_GP11_BITS_MASK) +/*! @} */ + +/*! @name GP20 - Value of OTP Bank14 Word2 () */ +/*! @{ */ + +#define OCOTP_GP20_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP20_BITS_SHIFT (0U) +#define OCOTP_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP20_BITS_SHIFT)) & OCOTP_GP20_BITS_MASK) +/*! @} */ + +/*! @name GP21 - Value of OTP Bank14 Word3 () */ +/*! @{ */ + +#define OCOTP_GP21_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP21_BITS_SHIFT (0U) +#define OCOTP_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP21_BITS_SHIFT)) & OCOTP_GP21_BITS_MASK) +/*! @} */ + +/*! @name GP_CRC0 - Value of OTP Bank15 Word0 (CRC Key) */ +/*! @{ */ + +#define OCOTP_GP_CRC0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP_CRC0_BITS_SHIFT (0U) +#define OCOTP_GP_CRC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP_CRC0_BITS_SHIFT)) & OCOTP_GP_CRC0_BITS_MASK) +/*! @} */ + +/*! @name GP_CRC1 - Value of OTP Bank15 Word1 (CRC Key) */ +/*! @{ */ + +#define OCOTP_GP_CRC1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP_CRC1_BITS_SHIFT (0U) +#define OCOTP_GP_CRC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP_CRC1_BITS_SHIFT)) & OCOTP_GP_CRC1_BITS_MASK) +/*! @} */ + +/*! @name GP_CRC2 - Value of OTP Bank15 Word2 (CRC Key) */ +/*! @{ */ + +#define OCOTP_GP_CRC2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP_CRC2_BITS_SHIFT (0U) +#define OCOTP_GP_CRC2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP_CRC2_BITS_SHIFT)) & OCOTP_GP_CRC2_BITS_MASK) +/*! @} */ + +/*! @name GROUP_MASK - Value of OTP Bank15 Word3 (CRC Key) */ +/*! @{ */ + +#define OCOTP_GROUP_MASK_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GROUP_MASK_BITS_SHIFT (0U) +#define OCOTP_GROUP_MASK_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GROUP_MASK_BITS_SHIFT)) & OCOTP_GROUP_MASK_BITS_MASK) +/*! @} */ + +/*! @name HDMI_FW_SRK0 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDMI_FW_SRK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDMI_FW_SRK0_BITS_SHIFT (0U) +#define OCOTP_HDMI_FW_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK0_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK0_BITS_MASK) +/*! @} */ + +/*! @name HDMI_FW_SRK1 - Value of OTP Bank16 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDMI_FW_SRK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDMI_FW_SRK1_BITS_SHIFT (0U) +#define OCOTP_HDMI_FW_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK1_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK1_BITS_MASK) +/*! @} */ + +/*! @name HDMI_FW_SRK2 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDMI_FW_SRK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDMI_FW_SRK2_BITS_SHIFT (0U) +#define OCOTP_HDMI_FW_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK2_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK2_BITS_MASK) +/*! @} */ + +/*! @name HDMI_FW_SRK3 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDMI_FW_SRK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDMI_FW_SRK3_BITS_SHIFT (0U) +#define OCOTP_HDMI_FW_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK3_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK3_BITS_MASK) +/*! @} */ + +/*! @name HDMI_FW_SRK4 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDMI_FW_SRK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDMI_FW_SRK4_BITS_SHIFT (0U) +#define OCOTP_HDMI_FW_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK4_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK4_BITS_MASK) +/*! @} */ + +/*! @name HDMI_FW_SRK5 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDMI_FW_SRK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDMI_FW_SRK5_BITS_SHIFT (0U) +#define OCOTP_HDMI_FW_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK5_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK5_BITS_MASK) +/*! @} */ + +/*! @name HDMI_FW_SRK6 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDMI_FW_SRK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDMI_FW_SRK6_BITS_SHIFT (0U) +#define OCOTP_HDMI_FW_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK6_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK6_BITS_MASK) +/*! @} */ + +/*! @name HDMI_FW_SRK7 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDMI_FW_SRK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDMI_FW_SRK7_BITS_SHIFT (0U) +#define OCOTP_HDMI_FW_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK7_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK7_BITS_MASK) +/*! @} */ + +/*! @name HDMI_KMEK0 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDMI_KMEK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDMI_KMEK0_BITS_SHIFT (0U) +#define OCOTP_HDMI_KMEK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_KMEK0_BITS_SHIFT)) & OCOTP_HDMI_KMEK0_BITS_MASK) +/*! @} */ + +/*! @name HDMI_KMEK1 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDMI_KMEK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDMI_KMEK1_BITS_SHIFT (0U) +#define OCOTP_HDMI_KMEK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_KMEK1_BITS_SHIFT)) & OCOTP_HDMI_KMEK1_BITS_MASK) +/*! @} */ + +/*! @name HDMI_KMEK2 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDMI_KMEK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDMI_KMEK2_BITS_SHIFT (0U) +#define OCOTP_HDMI_KMEK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_KMEK2_BITS_SHIFT)) & OCOTP_HDMI_KMEK2_BITS_MASK) +/*! @} */ + +/*! @name HDMI_KMEK3 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDMI_KMEK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDMI_KMEK3_BITS_SHIFT (0U) +#define OCOTP_HDMI_KMEK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_KMEK3_BITS_SHIFT)) & OCOTP_HDMI_KMEK3_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CONS0 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CONS0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CONS0_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CONS0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CONS0_BITS_SHIFT)) & OCOTP_HDCP_TX_CONS0_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CONS1 - Value of OTP Bank16 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CONS1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CONS1_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CONS1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CONS1_BITS_SHIFT)) & OCOTP_HDCP_TX_CONS1_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CONS2 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CONS2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CONS2_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CONS2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CONS2_BITS_SHIFT)) & OCOTP_HDCP_TX_CONS2_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CONS3 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CONS3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CONS3_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CONS3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CONS3_BITS_SHIFT)) & OCOTP_HDCP_TX_CONS3_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT0 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT0_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT0_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT0_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT1 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT1_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT1_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT1_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT2 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT2_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT2_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT2_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT3 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT3_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT3_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT3_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT4 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT4_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT4_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT4_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT5 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT5_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT5_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT5_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT6 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT6_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT6_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT6_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT7 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT7_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT7_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT7_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT8 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT8_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT8_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT8_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT8_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT8_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT9 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT9_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT9_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT9_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT9_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT9_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT10 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT10_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT10_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT10_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT10_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT10_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT11 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT11_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT11_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT11_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT11_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT11_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT12 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT12_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT12_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT12_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT12_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT12_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT13 - Value of OTP Bank16 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT13_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT13_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT13_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT13_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT13_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT14 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT14_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT14_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT14_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT14_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT14_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT15 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT15_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT15_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT15_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT15_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT15_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT16 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT16_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT16_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT16_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT16_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT16_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT17 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT17_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT17_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT17_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT17_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT17_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT18 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT18_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT18_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT18_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT18_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT18_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT19 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT19_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT19_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT19_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT19_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT19_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT20 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT20_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT20_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT20_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT20_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT21 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT21_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT21_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT21_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT21_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT22 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT22_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT22_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT22_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT22_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT23 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT23_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT23_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT23_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT23_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT24 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT24_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT24_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT24_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT24_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT24_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT25 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT25_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT25_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT25_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT25_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT25_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT26 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT26_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT26_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT26_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT26_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT26_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT27 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT27_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT27_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT27_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT27_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT27_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT28 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT28_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT28_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT28_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT28_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT28_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT29 - Value of OTP Bank16 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT29_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT29_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT29_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT29_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT29_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT30 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT30_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT30_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT30_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT30_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT30_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT31 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT31_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT31_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT31_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT31_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT31_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT32 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT32_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT32_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT32_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT32_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT33 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT33_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT33_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT33_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT33_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT33_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT34 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT34_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT34_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT34_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT34_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT34_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT35 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT35_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT35_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT35_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT35_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT35_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT36 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT36_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT36_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT36_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT36_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT36_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT37 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT37_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT37_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT37_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT37_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT37_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT38 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT38_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT38_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT38_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT38_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT38_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT39 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT39_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT39_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT39_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT39_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT39_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT40 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT40_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT40_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT40_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT40_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT40_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT41 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT41_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT41_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT41_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT41_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT41_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT42 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT42_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT42_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT42_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT42_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT42_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT43 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT43_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT43_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT43_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT43_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT43_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT44 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT44_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT44_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT44_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT44_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT44_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT45 - Value of OTP Bank16 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT45_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT45_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT45_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT45_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT45_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT46 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT46_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT46_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT46_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT46_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT46_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT47 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT47_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT47_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT47_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT47_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT47_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT48 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT48_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT48_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT48_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT48_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT48_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT49 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT49_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT49_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT49_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT49_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT49_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT50 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT50_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT50_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT50_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT50_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT50_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT51 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT51_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT51_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT51_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT51_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT51_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT52 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT52_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT52_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT52_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT52_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT52_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT53 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT53_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT53_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT53_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT53_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT53_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT54 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT54_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT54_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT54_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT54_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT54_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT55 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT55_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT55_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT55_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT55_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT55_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT56 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT56_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT56_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT56_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT56_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT56_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT57 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT57_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT57_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT57_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT57_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT57_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT58 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT58_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT58_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT58_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT58_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT58_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT59 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT59_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT59_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT59_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT59_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT59_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT60 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT60_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT60_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT60_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT60_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT60_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT61 - Value of OTP Bank16 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT61_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT61_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT61_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT61_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT61_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT62 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT62_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT62_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT62_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT62_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT62_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT63 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT63_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT63_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT63_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT63_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT63_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT64 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT64_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT64_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT64_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT64_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT64_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT65 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT65_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT65_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT65_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT65_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT65_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT66 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT66_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT66_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT66_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT66_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT66_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT67 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT67_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT67_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT67_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT67_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT67_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT68 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT68_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT68_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT68_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT68_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT68_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT69 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT69_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT69_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT69_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT69_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT69_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT70 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT70_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT70_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT70_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT70_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT70_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT71 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT71_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT71_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT71_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT71_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT71_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT72 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT72_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT72_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT72_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT72_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT72_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT73 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT73_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT73_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT73_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT73_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT73_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT74 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT74_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT74_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT74_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT74_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT74_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT75 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT75_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT75_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT75_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT75_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT75_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT76 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT76_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT76_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT76_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT76_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT76_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT77 - Value of OTP Bank16 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT77_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT77_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT77_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT77_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT77_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT78 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT78_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT78_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT78_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT78_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT78_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT79 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT79_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT79_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT79_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT79_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT79_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT80 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT80_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT80_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT80_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT80_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT80_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT81 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT81_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT81_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT81_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT81_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT81_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT82 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT82_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT82_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT82_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT82_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT82_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT83 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT83_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT83_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT83_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT83_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT83_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT84 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT84_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT84_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT84_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT84_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT84_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT85 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT85_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT85_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT85_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT85_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT85_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT86 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT86_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT86_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT86_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT86_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT86_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT87 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT87_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT87_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT87_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT87_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT87_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT88 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT88_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT88_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT88_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT88_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT88_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT89 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT89_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT89_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT89_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT89_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT89_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT90 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT90_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT90_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT90_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT90_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT90_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT91 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT91_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT91_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT91_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT91_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT91_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT92 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT92_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT92_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT92_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT92_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT92_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT93 - Value of OTP Bank16 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT93_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT93_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT93_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT93_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT93_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT94 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT94_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT94_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT94_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT94_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT94_BITS_MASK) +/*! @} */ + +/*! @name HDCP_TX_CERT95 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_TX_CERT95_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_TX_CERT95_BITS_SHIFT (0U) +#define OCOTP_HDCP_TX_CERT95_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT95_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT95_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY0 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY0_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY0_BITS_SHIFT)) & OCOTP_HDCP_KEY0_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY1 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY1_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY1_BITS_SHIFT)) & OCOTP_HDCP_KEY1_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY2 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY2_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY2_BITS_SHIFT)) & OCOTP_HDCP_KEY2_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY3 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY3_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY3_BITS_SHIFT)) & OCOTP_HDCP_KEY3_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY4 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY4_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY4_BITS_SHIFT)) & OCOTP_HDCP_KEY4_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY5 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY5_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY5_BITS_SHIFT)) & OCOTP_HDCP_KEY5_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY6 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY6_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY6_BITS_SHIFT)) & OCOTP_HDCP_KEY6_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY7 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY7_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY7_BITS_SHIFT)) & OCOTP_HDCP_KEY7_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY8 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY8_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY8_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY8_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY8_BITS_SHIFT)) & OCOTP_HDCP_KEY8_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY9 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY9_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY9_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY9_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY9_BITS_SHIFT)) & OCOTP_HDCP_KEY9_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY10 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY10_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY10_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY10_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY10_BITS_SHIFT)) & OCOTP_HDCP_KEY10_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY11 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY11_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY11_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY11_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY11_BITS_SHIFT)) & OCOTP_HDCP_KEY11_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY12 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY12_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY12_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY12_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY12_BITS_SHIFT)) & OCOTP_HDCP_KEY12_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY13 - Value of OTP Bank16 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY13_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY13_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY13_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY13_BITS_SHIFT)) & OCOTP_HDCP_KEY13_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY14 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY14_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY14_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY14_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY14_BITS_SHIFT)) & OCOTP_HDCP_KEY14_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY15 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY15_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY15_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY15_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY15_BITS_SHIFT)) & OCOTP_HDCP_KEY15_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY16 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY16_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY16_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY16_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY16_BITS_SHIFT)) & OCOTP_HDCP_KEY16_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY17 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY17_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY17_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY17_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY17_BITS_SHIFT)) & OCOTP_HDCP_KEY17_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY18 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY18_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY18_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY18_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY18_BITS_SHIFT)) & OCOTP_HDCP_KEY18_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY19 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY19_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY19_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY19_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY19_BITS_SHIFT)) & OCOTP_HDCP_KEY19_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY20 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY20_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY20_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY20_BITS_SHIFT)) & OCOTP_HDCP_KEY20_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY21 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY21_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY21_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY21_BITS_SHIFT)) & OCOTP_HDCP_KEY21_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY22 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY22_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY22_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY22_BITS_SHIFT)) & OCOTP_HDCP_KEY22_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY23 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY23_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY23_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY23_BITS_SHIFT)) & OCOTP_HDCP_KEY23_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY24 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY24_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY24_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY24_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY24_BITS_SHIFT)) & OCOTP_HDCP_KEY24_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY25 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY25_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY25_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY25_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY25_BITS_SHIFT)) & OCOTP_HDCP_KEY25_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY26 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY26_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY26_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY26_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY26_BITS_SHIFT)) & OCOTP_HDCP_KEY26_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY27 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY27_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY27_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY27_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY27_BITS_SHIFT)) & OCOTP_HDCP_KEY27_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY28 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY28_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY28_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY28_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY28_BITS_SHIFT)) & OCOTP_HDCP_KEY28_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY29 - Value of OTP Bank16 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY29_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY29_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY29_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY29_BITS_SHIFT)) & OCOTP_HDCP_KEY29_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY30 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY30_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY30_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY30_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY30_BITS_SHIFT)) & OCOTP_HDCP_KEY30_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY31 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY31_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY31_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY31_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY31_BITS_SHIFT)) & OCOTP_HDCP_KEY31_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY32 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY32_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY32_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY32_BITS_SHIFT)) & OCOTP_HDCP_KEY32_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY33 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY33_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY33_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY33_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY33_BITS_SHIFT)) & OCOTP_HDCP_KEY33_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY34 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY34_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY34_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY34_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY34_BITS_SHIFT)) & OCOTP_HDCP_KEY34_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY35 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY35_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY35_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY35_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY35_BITS_SHIFT)) & OCOTP_HDCP_KEY35_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY36 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY36_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY36_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY36_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY36_BITS_SHIFT)) & OCOTP_HDCP_KEY36_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY37 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY37_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY37_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY37_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY37_BITS_SHIFT)) & OCOTP_HDCP_KEY37_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY38 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY38_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY38_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY38_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY38_BITS_SHIFT)) & OCOTP_HDCP_KEY38_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY39 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY39_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY39_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY39_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY39_BITS_SHIFT)) & OCOTP_HDCP_KEY39_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY40 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY40_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY40_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY40_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY40_BITS_SHIFT)) & OCOTP_HDCP_KEY40_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY41 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY41_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY41_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY41_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY41_BITS_SHIFT)) & OCOTP_HDCP_KEY41_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY42 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY42_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY42_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY42_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY42_BITS_SHIFT)) & OCOTP_HDCP_KEY42_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY43 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY43_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY43_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY43_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY43_BITS_SHIFT)) & OCOTP_HDCP_KEY43_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY44 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY44_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY44_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY44_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY44_BITS_SHIFT)) & OCOTP_HDCP_KEY44_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY45 - Value of OTP Bank16 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY45_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY45_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY45_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY45_BITS_SHIFT)) & OCOTP_HDCP_KEY45_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY46 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY46_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY46_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY46_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY46_BITS_SHIFT)) & OCOTP_HDCP_KEY46_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY47 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY47_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY47_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY47_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY47_BITS_SHIFT)) & OCOTP_HDCP_KEY47_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY48 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY48_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY48_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY48_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY48_BITS_SHIFT)) & OCOTP_HDCP_KEY48_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY49 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY49_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY49_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY49_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY49_BITS_SHIFT)) & OCOTP_HDCP_KEY49_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY50 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY50_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY50_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY50_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY50_BITS_SHIFT)) & OCOTP_HDCP_KEY50_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY51 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY51_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY51_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY51_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY51_BITS_SHIFT)) & OCOTP_HDCP_KEY51_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY52 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY52_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY52_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY52_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY52_BITS_SHIFT)) & OCOTP_HDCP_KEY52_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY53 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY53_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY53_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY53_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY53_BITS_SHIFT)) & OCOTP_HDCP_KEY53_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY54 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY54_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY54_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY54_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY54_BITS_SHIFT)) & OCOTP_HDCP_KEY54_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY55 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY55_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY55_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY55_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY55_BITS_SHIFT)) & OCOTP_HDCP_KEY55_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY56 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY56_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY56_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY56_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY56_BITS_SHIFT)) & OCOTP_HDCP_KEY56_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY57 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY57_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY57_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY57_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY57_BITS_SHIFT)) & OCOTP_HDCP_KEY57_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY58 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY58_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY58_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY58_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY58_BITS_SHIFT)) & OCOTP_HDCP_KEY58_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY59 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY59_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY59_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY59_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY59_BITS_SHIFT)) & OCOTP_HDCP_KEY59_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY60 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY60_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY60_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY60_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY60_BITS_SHIFT)) & OCOTP_HDCP_KEY60_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY61 - Value of OTP Bank16 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY61_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY61_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY61_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY61_BITS_SHIFT)) & OCOTP_HDCP_KEY61_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY62 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY62_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY62_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY62_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY62_BITS_SHIFT)) & OCOTP_HDCP_KEY62_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY63 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY63_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY63_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY63_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY63_BITS_SHIFT)) & OCOTP_HDCP_KEY63_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY64 - Value of OTP Bank17 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY64_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY64_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY64_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY64_BITS_SHIFT)) & OCOTP_HDCP_KEY64_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY65 - Value of OTP Bank17 Word1 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY65_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY65_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY65_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY65_BITS_SHIFT)) & OCOTP_HDCP_KEY65_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY66 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY66_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY66_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY66_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY66_BITS_SHIFT)) & OCOTP_HDCP_KEY66_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY67 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY67_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY67_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY67_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY67_BITS_SHIFT)) & OCOTP_HDCP_KEY67_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY68 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY68_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY68_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY68_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY68_BITS_SHIFT)) & OCOTP_HDCP_KEY68_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY69 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY69_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY69_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY69_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY69_BITS_SHIFT)) & OCOTP_HDCP_KEY69_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY70 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY70_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY70_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY70_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY70_BITS_SHIFT)) & OCOTP_HDCP_KEY70_BITS_MASK) +/*! @} */ + +/*! @name HDCP_KEY71 - Value of OTP Bank16 Word0 (HDCP Key) */ +/*! @{ */ + +#define OCOTP_HDCP_KEY71_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_HDCP_KEY71_BITS_SHIFT (0U) +#define OCOTP_HDCP_KEY71_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY71_BITS_SHIFT)) & OCOTP_HDCP_KEY71_BITS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OCOTP_Register_Masks */ + + +/* OCOTP - Peripheral instance base addresses */ +/** Peripheral OCOTP base address */ +#define OCOTP_BASE (0x30350000u) +/** Peripheral OCOTP base pointer */ +#define OCOTP ((OCOTP_Type *)OCOTP_BASE) +/** Array initializer of OCOTP peripheral base addresses */ +#define OCOTP_BASE_ADDRS { OCOTP_BASE } +/** Array initializer of OCOTP peripheral base pointers */ +#define OCOTP_BASE_PTRS { OCOTP } + +/*! + * @} + */ /* end of group OCOTP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWMCR; /**< PWM Control Register, offset: 0x0 */ + __IO uint32_t PWMSR; /**< PWM Status Register, offset: 0x4 */ + __IO uint32_t PWMIR; /**< PWM Interrupt Register, offset: 0x8 */ + __IO uint32_t PWMSAR; /**< PWM Sample Register, offset: 0xC */ + __IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */ + __I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name PWMCR - PWM Control Register */ +/*! @{ */ + +#define PWM_PWMCR_EN_MASK (0x1U) +#define PWM_PWMCR_EN_SHIFT (0U) +/*! EN + * 0b0..PWM disabled + * 0b1..PWM enabled + */ +#define PWM_PWMCR_EN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK) + +#define PWM_PWMCR_REPEAT_MASK (0x6U) +#define PWM_PWMCR_REPEAT_SHIFT (1U) +/*! REPEAT + * 0b00..Use each sample once + * 0b01..Use each sample twice + * 0b10..Use each sample four times + * 0b11..Use each sample eight times + */ +#define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK) + +#define PWM_PWMCR_SWR_MASK (0x8U) +#define PWM_PWMCR_SWR_SHIFT (3U) +/*! SWR + * 0b0..PWM is out of reset + * 0b1..PWM is undergoing reset + */ +#define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK) + +#define PWM_PWMCR_PRESCALER_MASK (0xFFF0U) +#define PWM_PWMCR_PRESCALER_SHIFT (4U) +/*! PRESCALER + * 0b000000000000..Divide by 1 + * 0b000000000001..Divide by 2 + * 0b111111111111..Divide by 4096 + */ +#define PWM_PWMCR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK) + +#define PWM_PWMCR_CLKSRC_MASK (0x30000U) +#define PWM_PWMCR_CLKSRC_SHIFT (16U) +/*! CLKSRC + * 0b00..Clock is off + * 0b01..ipg_clk + * 0b10..ipg_clk_highfreq + * 0b11..ipg_clk_32k + */ +#define PWM_PWMCR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK) + +#define PWM_PWMCR_POUTC_MASK (0xC0000U) +#define PWM_PWMCR_POUTC_SHIFT (18U) +/*! POUTC + * 0b00..Output pin is set at rollover and cleared at comparison + * 0b01..Output pin is cleared at rollover and set at comparison + * 0b10..PWM output is disconnected + * 0b11..PWM output is disconnected + */ +#define PWM_PWMCR_POUTC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK) + +#define PWM_PWMCR_HCTR_MASK (0x100000U) +#define PWM_PWMCR_HCTR_SHIFT (20U) +/*! HCTR + * 0b0..Half word swapping does not take place + * 0b1..Half words from write data bus are swapped + */ +#define PWM_PWMCR_HCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK) + +#define PWM_PWMCR_BCTR_MASK (0x200000U) +#define PWM_PWMCR_BCTR_SHIFT (21U) +/*! BCTR + * 0b0..byte ordering remains the same + * 0b1..byte ordering is reversed + */ +#define PWM_PWMCR_BCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK) + +#define PWM_PWMCR_DBGEN_MASK (0x400000U) +#define PWM_PWMCR_DBGEN_SHIFT (22U) +/*! DBGEN + * 0b0..Inactive in debug mode + * 0b1..Active in debug mode + */ +#define PWM_PWMCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DBGEN_SHIFT)) & PWM_PWMCR_DBGEN_MASK) + +#define PWM_PWMCR_WAITEN_MASK (0x800000U) +#define PWM_PWMCR_WAITEN_SHIFT (23U) +/*! WAITEN + * 0b0..Inactive in wait mode + * 0b1..Active in wait mode + */ +#define PWM_PWMCR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK) + +#define PWM_PWMCR_DOZEN_MASK (0x1000000U) +#define PWM_PWMCR_DOZEN_SHIFT (24U) +/*! DOZEN + * 0b0..Inactive in doze mode + * 0b1..Active in doze mode + */ +#define PWM_PWMCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK) + +#define PWM_PWMCR_STOPEN_MASK (0x2000000U) +#define PWM_PWMCR_STOPEN_SHIFT (25U) +/*! STOPEN + * 0b0..Inactive in stop mode + * 0b1..Active in stop mode + */ +#define PWM_PWMCR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK) + +#define PWM_PWMCR_FWM_MASK (0xC000000U) +#define PWM_PWMCR_FWM_SHIFT (26U) +/*! FWM + * 0b00..FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO + * 0b01..FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO + * 0b10..FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO + * 0b11..FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO + */ +#define PWM_PWMCR_FWM(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK) +/*! @} */ + +/*! @name PWMSR - PWM Status Register */ +/*! @{ */ + +#define PWM_PWMSR_FIFOAV_MASK (0x7U) +#define PWM_PWMSR_FIFOAV_SHIFT (0U) +/*! FIFOAV + * 0b000..No data available + * 0b001..1 word of data in FIFO + * 0b010..2 words of data in FIFO + * 0b011..3 words of data in FIFO + * 0b100..4 words of data in FIFO + * 0b101..unused + * 0b110..unused + * 0b111..unused + */ +#define PWM_PWMSR_FIFOAV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK) + +#define PWM_PWMSR_FE_MASK (0x8U) +#define PWM_PWMSR_FE_SHIFT (3U) +/*! FE + * 0b0..Data level is above water mark + * 0b1..When the data level falls below the mark set by FWM field + */ +#define PWM_PWMSR_FE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK) + +#define PWM_PWMSR_ROV_MASK (0x10U) +#define PWM_PWMSR_ROV_SHIFT (4U) +/*! ROV + * 0b0..Roll-over event not occurred + * 0b1..Roll-over event occurred + */ +#define PWM_PWMSR_ROV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK) + +#define PWM_PWMSR_CMP_MASK (0x20U) +#define PWM_PWMSR_CMP_SHIFT (5U) +/*! CMP + * 0b0..Compare event not occurred + * 0b1..Compare event occurred + */ +#define PWM_PWMSR_CMP(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK) + +#define PWM_PWMSR_FWE_MASK (0x40U) +#define PWM_PWMSR_FWE_SHIFT (6U) +/*! FWE + * 0b0..FIFO write error not occurred + * 0b1..FIFO write error occurred + */ +#define PWM_PWMSR_FWE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK) +/*! @} */ + +/*! @name PWMIR - PWM Interrupt Register */ +/*! @{ */ + +#define PWM_PWMIR_FIE_MASK (0x1U) +#define PWM_PWMIR_FIE_SHIFT (0U) +/*! FIE + * 0b0..FIFO Empty interrupt disabled + * 0b1..FIFO Empty interrupt enabled + */ +#define PWM_PWMIR_FIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK) + +#define PWM_PWMIR_RIE_MASK (0x2U) +#define PWM_PWMIR_RIE_SHIFT (1U) +/*! RIE + * 0b0..Roll-over interrupt not enabled + * 0b1..Roll-over Interrupt enabled + */ +#define PWM_PWMIR_RIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK) + +#define PWM_PWMIR_CIE_MASK (0x4U) +#define PWM_PWMIR_CIE_SHIFT (2U) +/*! CIE + * 0b0..Compare Interrupt not enabled + * 0b1..Compare Interrupt enabled + */ +#define PWM_PWMIR_CIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK) +/*! @} */ + +/*! @name PWMSAR - PWM Sample Register */ +/*! @{ */ + +#define PWM_PWMSAR_SAMPLE_MASK (0xFFFFU) +#define PWM_PWMSAR_SAMPLE_SHIFT (0U) +#define PWM_PWMSAR_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK) +/*! @} */ + +/*! @name PWMPR - PWM Period Register */ +/*! @{ */ + +#define PWM_PWMPR_PERIOD_MASK (0xFFFFU) +#define PWM_PWMPR_PERIOD_SHIFT (0U) +#define PWM_PWMPR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK) +/*! @} */ + +/*! @name PWMCNR - PWM Counter Register */ +/*! @{ */ + +#define PWM_PWMCNR_COUNT_MASK (0xFFFFU) +#define PWM_PWMCNR_COUNT_SHIFT (0U) +#define PWM_PWMCNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +/** Peripheral PWM1 base address */ +#define PWM1_BASE (0x30660000u) +/** Peripheral PWM1 base pointer */ +#define PWM1 ((PWM_Type *)PWM1_BASE) +/** Peripheral PWM2 base address */ +#define PWM2_BASE (0x30670000u) +/** Peripheral PWM2 base pointer */ +#define PWM2 ((PWM_Type *)PWM2_BASE) +/** Peripheral PWM3 base address */ +#define PWM3_BASE (0x30680000u) +/** Peripheral PWM3 base pointer */ +#define PWM3 ((PWM_Type *)PWM3_BASE) +/** Peripheral PWM4 base address */ +#define PWM4_BASE (0x30690000u) +/** Peripheral PWM4 base pointer */ +#define PWM4 ((PWM_Type *)PWM4_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_IRQS { NotAvail_IRQn, PWM1_IRQn, PWM2_IRQn, PWM3_IRQn, PWM4_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- QuadSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer + * @{ + */ + +/** QuadSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ + __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */ + __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */ + __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */ + __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */ + __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */ + __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ + __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */ + __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */ + uint8_t RESERVED_2[196]; + __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */ + __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */ + __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */ + uint8_t RESERVED_4[60]; + __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ + __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ + uint8_t RESERVED_5[4]; + __I uint32_t SR; /**< Status Register, offset: 0x15C */ + __IO uint32_t FR; /**< Flag Register, offset: 0x160 */ + __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */ + __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */ + __IO uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */ + uint8_t RESERVED_6[16]; + __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */ + __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */ + __IO uint32_t SFB1AD; /**< Serial Flash B1Top Address, offset: 0x188 */ + __IO uint32_t SFB2AD; /**< Serial Flash B2Top Address, offset: 0x18C */ + uint8_t RESERVED_7[112]; + __IO uint32_t RBDR[32]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[128]; + __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */ + __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */ + uint8_t RESERVED_9[8]; + __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */ +} QuadSPI_Type; + +/* ---------------------------------------------------------------------------- + -- QuadSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +/*! @{ */ + +#define QuadSPI_MCR_SWRSTSD_MASK (0x1U) +#define QuadSPI_MCR_SWRSTSD_SHIFT (0U) +/*! SWRSTSD + * 0b0..No action + * 0b1..Serial Flash domain flops are reset. Does not reset configuration registers. It is advisable to reset + * both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side + * effects. + */ +#define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK) + +#define QuadSPI_MCR_SWRSTHD_MASK (0x2U) +#define QuadSPI_MCR_SWRSTHD_SHIFT (1U) +/*! SWRSTHD + * 0b0..No action + * 0b1..AHB domain flops are reset. Does not reset configuration registers. It is advisable to reset both the + * serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. + */ +#define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK) + +#define QuadSPI_MCR_END_CFG_MASK (0xCU) +#define QuadSPI_MCR_END_CFG_SHIFT (2U) +#define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK) + +#define QuadSPI_MCR_DQS_EN_MASK (0x40U) +#define QuadSPI_MCR_DQS_EN_SHIFT (6U) +/*! DQS_EN + * 0b0..DQS disabled. + * 0b1..DQS enabled- When enabled, the incoming data is sampled on both the edges of DQS input when + * QSPI_MCR[DDR_EN] is set, else, on only one edge when QSPI_MCR[DDR_EN] is 0. The QSPI_SMPR[DDR_SMP] values are ignored. + */ +#define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK) + +#define QuadSPI_MCR_DDR_EN_MASK (0x80U) +#define QuadSPI_MCR_DDR_EN_SHIFT (7U) +/*! DDR_EN + * 0b0..2x and 4x clocks are disabled for SDR instructions only + * 0b1..2x and 4x clocks are enabled supports both SDR and DDR instruction. + */ +#define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK) + +#define QuadSPI_MCR_CLR_RXF_MASK (0x400U) +#define QuadSPI_MCR_CLR_RXF_SHIFT (10U) +/*! CLR_RXF + * 0b0..No action. + * 0b1..Read and write pointers of the RX Buffer are reset to 0. QSPI_RBSR[RDBFL] is reset to 0. + */ +#define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK) + +#define QuadSPI_MCR_CLR_TXF_MASK (0x800U) +#define QuadSPI_MCR_CLR_TXF_SHIFT (11U) +/*! CLR_TXF + * 0b0..No action. + * 0b1..Read and write pointers of the TX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0. + */ +#define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK) + +#define QuadSPI_MCR_MDIS_MASK (0x4000U) +#define QuadSPI_MCR_MDIS_SHIFT (14U) +/*! MDIS + * 0b0..Enable QuadSPI clocks. + * 0b1..Allow external logic to disable QuadSPI clocks. + */ +#define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK) + +#define QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_MASK (0x1000000U) +#define QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_SHIFT (24U) +#define QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_SHIFT)) & QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_MASK) + +#define QuadSPI_MCR_DQS_LOOPBACK_EN_MASK (0x2000000U) +#define QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT (25U) +#define QuadSPI_MCR_DQS_LOOPBACK_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT)) & QuadSPI_MCR_DQS_LOOPBACK_EN_MASK) + +#define QuadSPI_MCR_DQS_PHASE_EN_MASK (0x4000000U) +#define QuadSPI_MCR_DQS_PHASE_EN_SHIFT (26U) +#define QuadSPI_MCR_DQS_PHASE_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_PHASE_EN_SHIFT)) & QuadSPI_MCR_DQS_PHASE_EN_MASK) +/*! @} */ + +/*! @name IPCR - IP Configuration Register */ +/*! @{ */ + +#define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU) +#define QuadSPI_IPCR_IDATSZ_SHIFT (0U) +#define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK) + +#define QuadSPI_IPCR_PAR_EN_MASK (0x10000U) +#define QuadSPI_IPCR_PAR_EN_SHIFT (16U) +#define QuadSPI_IPCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_PAR_EN_SHIFT)) & QuadSPI_IPCR_PAR_EN_MASK) + +#define QuadSPI_IPCR_SEQID_MASK (0xF000000U) +#define QuadSPI_IPCR_SEQID_SHIFT (24U) +#define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK) +/*! @} */ + +/*! @name FLSHCR - Flash Configuration Register */ +/*! @{ */ + +#define QuadSPI_FLSHCR_TCSS_MASK (0xFU) +#define QuadSPI_FLSHCR_TCSS_SHIFT (0U) +#define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK) + +#define QuadSPI_FLSHCR_TCSH_MASK (0xF00U) +#define QuadSPI_FLSHCR_TCSH_SHIFT (8U) +#define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK) + +#define QuadSPI_FLSHCR_TDH_MASK (0x30000U) +#define QuadSPI_FLSHCR_TDH_SHIFT (16U) +/*! TDH + * 0b00..Data aligned with the posedge of Internal reference clock of QuadSPI + * 0b01..Data aligned with 2x serial flash half clock + * 0b10..Reserved + * 0b11..Reserved + */ +#define QuadSPI_FLSHCR_TDH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK) +/*! @} */ + +/*! @name BUF0CR - Buffer0 Configuration Register */ +/*! @{ */ + +#define QuadSPI_BUF0CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF0CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK) + +#define QuadSPI_BUF0CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK) + +#define QuadSPI_BUF0CR_HP_EN_MASK (0x80000000U) +#define QuadSPI_BUF0CR_HP_EN_SHIFT (31U) +#define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK) +/*! @} */ + +/*! @name BUF1CR - Buffer1 Configuration Register */ +/*! @{ */ + +#define QuadSPI_BUF1CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF1CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK) + +#define QuadSPI_BUF1CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK) +/*! @} */ + +/*! @name BUF2CR - Buffer2 Configuration Register */ +/*! @{ */ + +#define QuadSPI_BUF2CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF2CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK) + +#define QuadSPI_BUF2CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK) +/*! @} */ + +/*! @name BUF3CR - Buffer3 Configuration Register */ +/*! @{ */ + +#define QuadSPI_BUF3CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF3CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK) + +#define QuadSPI_BUF3CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK) + +#define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U) +#define QuadSPI_BUF3CR_ALLMST_SHIFT (31U) +#define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK) +/*! @} */ + +/*! @name BFGENCR - Buffer Generic Configuration Register */ +/*! @{ */ + +#define QuadSPI_BFGENCR_SEQID_MASK (0xF000U) +#define QuadSPI_BFGENCR_SEQID_SHIFT (12U) +#define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK) + +#define QuadSPI_BFGENCR_PAR_EN_MASK (0x10000U) +#define QuadSPI_BFGENCR_PAR_EN_SHIFT (16U) +#define QuadSPI_BFGENCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_PAR_EN_SHIFT)) & QuadSPI_BFGENCR_PAR_EN_MASK) +/*! @} */ + +/*! @name BUF0IND - Buffer0 Top Index Register */ +/*! @{ */ + +#define QuadSPI_BUF0IND_TPINDX0_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U) +#define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK) +/*! @} */ + +/*! @name BUF1IND - Buffer1 Top Index Register */ +/*! @{ */ + +#define QuadSPI_BUF1IND_TPINDX1_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U) +#define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK) +/*! @} */ + +/*! @name BUF2IND - Buffer2 Top Index Register */ +/*! @{ */ + +#define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U) +#define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK) +/*! @} */ + +/*! @name SFAR - Serial Flash Address Register */ +/*! @{ */ + +#define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU) +#define QuadSPI_SFAR_SFADR_SHIFT (0U) +#define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK) +/*! @} */ + +/*! @name SMPR - Sampling Register */ +/*! @{ */ + +#define QuadSPI_SMPR_SDRSMP_MASK (0x60U) +#define QuadSPI_SMPR_SDRSMP_SHIFT (5U) +#define QuadSPI_SMPR_SDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_SDRSMP_SHIFT)) & QuadSPI_SMPR_SDRSMP_MASK) + +#define QuadSPI_SMPR_DDRSMP_MASK (0x70000U) +#define QuadSPI_SMPR_DDRSMP_SHIFT (16U) +#define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DDRSMP_SHIFT)) & QuadSPI_SMPR_DDRSMP_MASK) +/*! @} */ + +/*! @name RBSR - RX Buffer Status Register */ +/*! @{ */ + +#define QuadSPI_RBSR_RDBFL_MASK (0x3F00U) +#define QuadSPI_RBSR_RDBFL_SHIFT (8U) +#define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK) + +#define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U) +#define QuadSPI_RBSR_RDCTR_SHIFT (16U) +#define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK) +/*! @} */ + +/*! @name RBCT - RX Buffer Control Register */ +/*! @{ */ + +#define QuadSPI_RBCT_WMRK_MASK (0x1FU) +#define QuadSPI_RBCT_WMRK_SHIFT (0U) +#define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK) + +#define QuadSPI_RBCT_RXBRD_MASK (0x100U) +#define QuadSPI_RBCT_RXBRD_SHIFT (8U) +/*! RXBRD + * 0b0..RX Buffer content is read using the AHB Bus registers QSPI_ARDB0 to QSPI_ARDB31. For details, refer to + * Exclusive Access to Serial Flash for AHB Commands. + * 0b1..RX Buffer content is read using the IP Bus registers QSPI_RBDR0 to QSPI_RBDR31. + */ +#define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK) +/*! @} */ + +/*! @name TBSR - TX Buffer Status Register */ +/*! @{ */ + +#define QuadSPI_TBSR_TRBFL_MASK (0x1F00U) +#define QuadSPI_TBSR_TRBFL_SHIFT (8U) +#define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK) + +#define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U) +#define QuadSPI_TBSR_TRCTR_SHIFT (16U) +#define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK) +/*! @} */ + +/*! @name TBDR - TX Buffer Data Register */ +/*! @{ */ + +#define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU) +#define QuadSPI_TBDR_TXDATA_SHIFT (0U) +#define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK) +/*! @} */ + +/*! @name SR - Status Register */ +/*! @{ */ + +#define QuadSPI_SR_BUSY_MASK (0x1U) +#define QuadSPI_SR_BUSY_SHIFT (0U) +#define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK) + +#define QuadSPI_SR_IP_ACC_MASK (0x2U) +#define QuadSPI_SR_IP_ACC_SHIFT (1U) +#define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK) + +#define QuadSPI_SR_AHB_ACC_MASK (0x4U) +#define QuadSPI_SR_AHB_ACC_SHIFT (2U) +#define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK) + +#define QuadSPI_SR_AHBGNT_MASK (0x20U) +#define QuadSPI_SR_AHBGNT_SHIFT (5U) +#define QuadSPI_SR_AHBGNT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBGNT_SHIFT)) & QuadSPI_SR_AHBGNT_MASK) + +#define QuadSPI_SR_AHBTRN_MASK (0x40U) +#define QuadSPI_SR_AHBTRN_SHIFT (6U) +#define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK) + +#define QuadSPI_SR_AHB0NE_MASK (0x80U) +#define QuadSPI_SR_AHB0NE_SHIFT (7U) +#define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK) + +#define QuadSPI_SR_AHB1NE_MASK (0x100U) +#define QuadSPI_SR_AHB1NE_SHIFT (8U) +#define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK) + +#define QuadSPI_SR_AHB2NE_MASK (0x200U) +#define QuadSPI_SR_AHB2NE_SHIFT (9U) +#define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK) + +#define QuadSPI_SR_AHB3NE_MASK (0x400U) +#define QuadSPI_SR_AHB3NE_SHIFT (10U) +#define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK) + +#define QuadSPI_SR_AHB0FUL_MASK (0x800U) +#define QuadSPI_SR_AHB0FUL_SHIFT (11U) +#define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK) + +#define QuadSPI_SR_AHB1FUL_MASK (0x1000U) +#define QuadSPI_SR_AHB1FUL_SHIFT (12U) +#define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK) + +#define QuadSPI_SR_AHB2FUL_MASK (0x2000U) +#define QuadSPI_SR_AHB2FUL_SHIFT (13U) +#define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK) + +#define QuadSPI_SR_AHB3FUL_MASK (0x4000U) +#define QuadSPI_SR_AHB3FUL_SHIFT (14U) +#define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK) + +#define QuadSPI_SR_RXWE_MASK (0x10000U) +#define QuadSPI_SR_RXWE_SHIFT (16U) +#define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK) + +#define QuadSPI_SR_RXFULL_MASK (0x80000U) +#define QuadSPI_SR_RXFULL_SHIFT (19U) +#define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK) + +#define QuadSPI_SR_RXDMA_MASK (0x800000U) +#define QuadSPI_SR_RXDMA_SHIFT (23U) +#define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK) + +#define QuadSPI_SR_TXEDA_MASK (0x1000000U) +#define QuadSPI_SR_TXEDA_SHIFT (24U) +/*! TXEDA - Tx Buffer Enough Data Available + */ +#define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK) + +#define QuadSPI_SR_TXFULL_MASK (0x8000000U) +#define QuadSPI_SR_TXFULL_SHIFT (27U) +#define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK) + +#define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) +#define QuadSPI_SR_DLPSMP_SHIFT (29U) +#define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK) +/*! @} */ + +/*! @name FR - Flag Register */ +/*! @{ */ + +#define QuadSPI_FR_TFF_MASK (0x1U) +#define QuadSPI_FR_TFF_SHIFT (0U) +#define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK) + +#define QuadSPI_FR_IPGEF_MASK (0x10U) +#define QuadSPI_FR_IPGEF_SHIFT (4U) +#define QuadSPI_FR_IPGEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPGEF_SHIFT)) & QuadSPI_FR_IPGEF_MASK) + +#define QuadSPI_FR_IPIEF_MASK (0x40U) +#define QuadSPI_FR_IPIEF_SHIFT (6U) +#define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK) + +#define QuadSPI_FR_IPAEF_MASK (0x80U) +#define QuadSPI_FR_IPAEF_SHIFT (7U) +#define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK) + +#define QuadSPI_FR_IUEF_MASK (0x800U) +#define QuadSPI_FR_IUEF_SHIFT (11U) +#define QuadSPI_FR_IUEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IUEF_SHIFT)) & QuadSPI_FR_IUEF_MASK) + +#define QuadSPI_FR_ABOF_MASK (0x1000U) +#define QuadSPI_FR_ABOF_SHIFT (12U) +#define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK) + +#define QuadSPI_FR_ABSEF_MASK (0x8000U) +#define QuadSPI_FR_ABSEF_SHIFT (15U) +#define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK) + +#define QuadSPI_FR_RBDF_MASK (0x10000U) +#define QuadSPI_FR_RBDF_SHIFT (16U) +#define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK) + +#define QuadSPI_FR_RBOF_MASK (0x20000U) +#define QuadSPI_FR_RBOF_SHIFT (17U) +#define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK) + +#define QuadSPI_FR_ILLINE_MASK (0x800000U) +#define QuadSPI_FR_ILLINE_SHIFT (23U) +#define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK) + +#define QuadSPI_FR_TBUF_MASK (0x4000000U) +#define QuadSPI_FR_TBUF_SHIFT (26U) +#define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK) + +#define QuadSPI_FR_TBFF_MASK (0x8000000U) +#define QuadSPI_FR_TBFF_SHIFT (27U) +#define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK) + +#define QuadSPI_FR_DLPFF_MASK (0x80000000U) +#define QuadSPI_FR_DLPFF_SHIFT (31U) +#define QuadSPI_FR_DLPFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK) +/*! @} */ + +/*! @name RSER - Interrupt and DMA Request Select and Enable Register */ +/*! @{ */ + +#define QuadSPI_RSER_TFIE_MASK (0x1U) +#define QuadSPI_RSER_TFIE_SHIFT (0U) +/*! TFIE + * 0b0..No TFF interrupt will be generated + * 0b1..TFF interrupt will be generated + */ +#define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK) + +#define QuadSPI_RSER_IPGEIE_MASK (0x10U) +#define QuadSPI_RSER_IPGEIE_SHIFT (4U) +/*! IPGEIE + * 0b0..No IPGEF interrupt will be generated + * 0b1..IPGEF interrupt will be generated + */ +#define QuadSPI_RSER_IPGEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPGEIE_SHIFT)) & QuadSPI_RSER_IPGEIE_MASK) + +#define QuadSPI_RSER_IPIEIE_MASK (0x40U) +#define QuadSPI_RSER_IPIEIE_SHIFT (6U) +/*! IPIEIE + * 0b0..No IPIEF interrupt will be generated + * 0b0..IPIEF interrupt will be generated + */ +#define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK) + +#define QuadSPI_RSER_IPAEIE_MASK (0x80U) +#define QuadSPI_RSER_IPAEIE_SHIFT (7U) +/*! IPAEIE + * 0b0..No IPAEF interrupt will be generated + * 0b1..IPAEF interrupt will be generated + */ +#define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK) + +#define QuadSPI_RSER_IUEIE_MASK (0x800U) +#define QuadSPI_RSER_IUEIE_SHIFT (11U) +/*! IUEIE + * 0b0..No IUEF interrupt will be generated + * 0b1..IUEF interrupt will be generated + */ +#define QuadSPI_RSER_IUEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IUEIE_SHIFT)) & QuadSPI_RSER_IUEIE_MASK) + +#define QuadSPI_RSER_ABOIE_MASK (0x1000U) +#define QuadSPI_RSER_ABOIE_SHIFT (12U) +/*! ABOIE + * 0b0..No ABOF interrupt will be generated + * 0b1..ABOF interrupt will be generated + */ +#define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK) + +#define QuadSPI_RSER_ABSEIE_MASK (0x8000U) +#define QuadSPI_RSER_ABSEIE_SHIFT (15U) +/*! ABSEIE + * 0b0..No ABSEF interrupt will be generated + * 0b1..ABSEF interrupt will be generated + */ +#define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK) + +#define QuadSPI_RSER_RBDIE_MASK (0x10000U) +#define QuadSPI_RSER_RBDIE_SHIFT (16U) +/*! RBDIE + * 0b0..No RBDF interrupt will be generated + * 0b1..RBDF Interrupt will be generated + */ +#define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK) + +#define QuadSPI_RSER_RBOIE_MASK (0x20000U) +#define QuadSPI_RSER_RBOIE_SHIFT (17U) +/*! RBOIE + * 0b0..No RBOF interrupt will be generated + * 0b1..RBOF interrupt will be generated + */ +#define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK) + +#define QuadSPI_RSER_RBDDE_MASK (0x200000U) +#define QuadSPI_RSER_RBDDE_SHIFT (21U) +/*! RBDDE + * 0b0..No DMA request will be generated + * 0b1..DMA request will be generated + */ +#define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK) + +#define QuadSPI_RSER_ILLINIE_MASK (0x800000U) +#define QuadSPI_RSER_ILLINIE_SHIFT (23U) +/*! ILLINIE + * 0b0..No ILLINE interrupt will be generated + * 0b1..ILLINE interrupt will be generated + */ +#define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK) + +#define QuadSPI_RSER_TBUIE_MASK (0x4000000U) +#define QuadSPI_RSER_TBUIE_SHIFT (26U) +/*! TBUIE + * 0b0..No TBUF interrupt will be generated + * 0b1..TBUF interrupt will be generated + */ +#define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK) + +#define QuadSPI_RSER_TBFIE_MASK (0x8000000U) +#define QuadSPI_RSER_TBFIE_SHIFT (27U) +/*! TBFIE + * 0b0..No TBFF interrupt will be generated + * 0b1..TBFF interrupt will be generated + */ +#define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK) + +#define QuadSPI_RSER_DLPFIE_MASK (0x80000000U) +#define QuadSPI_RSER_DLPFIE_SHIFT (31U) +/*! DLPFIE + * 0b0..No DLPFF interrupt will be generated + * 0b1..DLPFF interrupt will be generated + */ +#define QuadSPI_RSER_DLPFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK) +/*! @} */ + +/*! @name SPNDST - Sequence Suspend Status Register */ +/*! @{ */ + +#define QuadSPI_SPNDST_SUSPND_MASK (0x1U) +#define QuadSPI_SPNDST_SUSPND_SHIFT (0U) +#define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK) + +#define QuadSPI_SPNDST_SPDBUF_MASK (0xC0U) +#define QuadSPI_SPNDST_SPDBUF_SHIFT (6U) +#define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK) + +#define QuadSPI_SPNDST_DATLFT_MASK (0xFE00U) +#define QuadSPI_SPNDST_DATLFT_SHIFT (9U) +#define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK) +/*! @} */ + +/*! @name SPTRCLR - Sequence Pointer Clear Register */ +/*! @{ */ + +#define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U) +#define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U) +#define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK) + +#define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U) +#define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U) +#define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK) +/*! @} */ + +/*! @name SFA1AD - Serial Flash A1 Top Address */ +/*! @{ */ + +#define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U) +#define QuadSPI_SFA1AD_TPADA1_SHIFT (10U) +#define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK) +/*! @} */ + +/*! @name SFA2AD - Serial Flash A2 Top Address */ +/*! @{ */ + +#define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U) +#define QuadSPI_SFA2AD_TPADA2_SHIFT (10U) +#define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK) +/*! @} */ + +/*! @name SFB1AD - Serial Flash B1Top Address */ +/*! @{ */ + +#define QuadSPI_SFB1AD_TPADB1_MASK (0xFFFFFC00U) +#define QuadSPI_SFB1AD_TPADB1_SHIFT (10U) +#define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK) +/*! @} */ + +/*! @name SFB2AD - Serial Flash B2Top Address */ +/*! @{ */ + +#define QuadSPI_SFB2AD_TPADB2_MASK (0xFFFFFC00U) +#define QuadSPI_SFB2AD_TPADB2_SHIFT (10U) +#define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK) +/*! @} */ + +/*! @name RBDR - RX Buffer Data Register */ +/*! @{ */ + +#define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU) +#define QuadSPI_RBDR_RXDATA_SHIFT (0U) +#define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK) +/*! @} */ + +/* The count of QuadSPI_RBDR */ +#define QuadSPI_RBDR_COUNT (32U) + +/*! @name LUTKEY - LUT Key Register */ +/*! @{ */ + +#define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define QuadSPI_LUTKEY_KEY_SHIFT (0U) +#define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK) +/*! @} */ + +/*! @name LCKCR - LUT Lock Configuration Register */ +/*! @{ */ + +#define QuadSPI_LCKCR_LOCK_MASK (0x1U) +#define QuadSPI_LCKCR_LOCK_SHIFT (0U) +#define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK) + +#define QuadSPI_LCKCR_UNLOCK_MASK (0x2U) +#define QuadSPI_LCKCR_UNLOCK_SHIFT (1U) +#define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK) +/*! @} */ + +/*! @name LUT - Look-up Table register */ +/*! @{ */ + +#define QuadSPI_LUT_OPRND0_MASK (0xFFU) +#define QuadSPI_LUT_OPRND0_SHIFT (0U) +/*! OPRND0 - Operand for INSTR0. + */ +#define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK) + +#define QuadSPI_LUT_PAD0_MASK (0x300U) +#define QuadSPI_LUT_PAD0_SHIFT (8U) +/*! PAD0 - Pad information for INSTR0. + * 0b00..1 Pad + * 0b01..2 Pads + * 0b10..4 Pads + * 0b11..NA + */ +#define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK) + +#define QuadSPI_LUT_INSTR0_MASK (0xFC00U) +#define QuadSPI_LUT_INSTR0_SHIFT (10U) +/*! INSTR0 - Instruction 0 + */ +#define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK) + +#define QuadSPI_LUT_OPRND1_MASK (0xFF0000U) +#define QuadSPI_LUT_OPRND1_SHIFT (16U) +/*! OPRND1 - Operand for INSTR1. + */ +#define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK) + +#define QuadSPI_LUT_PAD1_MASK (0x3000000U) +#define QuadSPI_LUT_PAD1_SHIFT (24U) +/*! PAD1 - Pad information for INSTR1. + * 0b00..1 Pad + * 0b01..2 Pads + * 0b10..4 Pads + * 0b11..NA + */ +#define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK) + +#define QuadSPI_LUT_INSTR1_MASK (0xFC000000U) +#define QuadSPI_LUT_INSTR1_SHIFT (26U) +/*! INSTR1 - Instruction 1 + */ +#define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK) +/*! @} */ + +/* The count of QuadSPI_LUT */ +#define QuadSPI_LUT_COUNT (64U) + + +/*! + * @} + */ /* end of group QuadSPI_Register_Masks */ + + +/* QuadSPI - Peripheral instance base addresses */ +/** Peripheral QuadSPI base address */ +#define QuadSPI_BASE (0x30BB0000u) +/** Peripheral QuadSPI base pointer */ +#define QuadSPI ((QuadSPI_Type *)QuadSPI_BASE) +/** Array initializer of QuadSPI peripheral base addresses */ +#define QuadSPI_BASE_ADDRS { QuadSPI_BASE } +/** Array initializer of QuadSPI peripheral base pointers */ +#define QuadSPI_BASE_PTRS { QuadSPI } +/** Interrupt vectors for the QuadSPI peripheral type */ +#define QuadSPI_IRQS { QSPI_IRQn } + +/*! + * @} + */ /* end of group QuadSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer + * @{ + */ + +/** RDC - Register Layout Typedef */ +typedef struct { + __I uint32_t VIR; /**< Version Information, offset: 0x0 */ + uint8_t RESERVED_0[32]; + __IO uint32_t STAT; /**< Status, offset: 0x24 */ + __IO uint32_t INTCTRL; /**< Interrupt and Control, offset: 0x28 */ + __IO uint32_t INTSTAT; /**< Interrupt Status, offset: 0x2C */ + uint8_t RESERVED_1[464]; + __IO uint32_t MDA[27]; /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_2[404]; + __IO uint32_t PDAP[118]; /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_3[552]; + struct { /* offset: 0x800, array step: 0x10 */ + __IO uint32_t MRSA; /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */ + __IO uint32_t MREA; /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */ + __IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, array step: 0x10 */ + __IO uint32_t MRVS; /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */ + } MR[52]; +} RDC_Type; + +/* ---------------------------------------------------------------------------- + -- RDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_Register_Masks RDC Register Masks + * @{ + */ + +/*! @name VIR - Version Information */ +/*! @{ */ + +#define RDC_VIR_NDID_MASK (0xFU) +#define RDC_VIR_NDID_SHIFT (0U) +/*! NDID - Number of Domains + */ +#define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK) + +#define RDC_VIR_NMSTR_MASK (0xFF0U) +#define RDC_VIR_NMSTR_SHIFT (4U) +/*! NMSTR - Number of Masters + */ +#define RDC_VIR_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK) + +#define RDC_VIR_NPER_MASK (0xFF000U) +#define RDC_VIR_NPER_SHIFT (12U) +/*! NPER - Number of Peripherals + */ +#define RDC_VIR_NPER(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK) + +#define RDC_VIR_NRGN_MASK (0xFF00000U) +#define RDC_VIR_NRGN_SHIFT (20U) +/*! NRGN - Number of Memory Regions + */ +#define RDC_VIR_NRGN(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define RDC_STAT_DID_MASK (0xFU) +#define RDC_STAT_DID_SHIFT (0U) +/*! DID - Domain ID + */ +#define RDC_STAT_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK) + +#define RDC_STAT_PDS_MASK (0x100U) +#define RDC_STAT_PDS_SHIFT (8U) +/*! PDS - Power Domain Status + * 0b0..Power Down Domain is OFF + * 0b1..Power Down Domain is ON + */ +#define RDC_STAT_PDS(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK) +/*! @} */ + +/*! @name INTCTRL - Interrupt and Control */ +/*! @{ */ + +#define RDC_INTCTRL_RCI_EN_MASK (0x1U) +#define RDC_INTCTRL_RCI_EN_SHIFT (0U) +/*! RCI_EN - Restoration Complete Interrupt + * 0b0..Interrupt Disabled + * 0b1..Interrupt Enabled + */ +#define RDC_INTCTRL_RCI_EN(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status */ +/*! @{ */ + +#define RDC_INTSTAT_INT_MASK (0x1U) +#define RDC_INTSTAT_INT_SHIFT (0U) +/*! INT - Interrupt Status + * 0b0..No Interrupt Pending + * 0b1..Interrupt Pending + */ +#define RDC_INTSTAT_INT(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK) +/*! @} */ + +/*! @name MDA - Master Domain Assignment */ +/*! @{ */ + +#define RDC_MDA_DID_MASK (0x3U) +#define RDC_MDA_DID_SHIFT (0U) +/*! DID - Domain ID + * 0b00..Master assigned to Processing Domain 0 + * 0b01..Master assigned to Processing Domain 1 + * 0b10..Master assigned to Processing Domain 2 + * 0b11..Master assigned to Processing Domain 3 + */ +#define RDC_MDA_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK) + +#define RDC_MDA_LCK_MASK (0x80000000U) +#define RDC_MDA_LCK_SHIFT (31U) +/*! LCK + * 0b0..Not Locked + * 0b1..Locked + */ +#define RDC_MDA_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK) +/*! @} */ + +/* The count of RDC_MDA */ +#define RDC_MDA_COUNT (27U) + +/*! @name PDAP - Peripheral Domain Access Permissions */ +/*! @{ */ + +#define RDC_PDAP_D0W_MASK (0x1U) +#define RDC_PDAP_D0W_SHIFT (0U) +/*! D0W - Domain 0 Write Access + * 0b0..No Write Access + * 0b1..Write Access Allowed + */ +#define RDC_PDAP_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK) + +#define RDC_PDAP_D0R_MASK (0x2U) +#define RDC_PDAP_D0R_SHIFT (1U) +/*! D0R - Domain 0 Read Access + * 0b0..No Read Access + * 0b1..Read Access Allowed + */ +#define RDC_PDAP_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK) + +#define RDC_PDAP_D1W_MASK (0x4U) +#define RDC_PDAP_D1W_SHIFT (2U) +/*! D1W - Domain 1 Write Access + * 0b0..No Write Access + * 0b1..Write Access Allowed + */ +#define RDC_PDAP_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK) + +#define RDC_PDAP_D1R_MASK (0x8U) +#define RDC_PDAP_D1R_SHIFT (3U) +/*! D1R - Domain 1 Read Access + * 0b0..No Read Access + * 0b1..Read Access Allowed + */ +#define RDC_PDAP_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK) + +#define RDC_PDAP_D2W_MASK (0x10U) +#define RDC_PDAP_D2W_SHIFT (4U) +/*! D2W - Domain 2 Write Access + * 0b0..No Write Access + * 0b1..Write Access Allowed + */ +#define RDC_PDAP_D2W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2W_SHIFT)) & RDC_PDAP_D2W_MASK) + +#define RDC_PDAP_D2R_MASK (0x20U) +#define RDC_PDAP_D2R_SHIFT (5U) +/*! D2R - Domain 2 Read Access + * 0b0..No Read Access + * 0b1..Read Access Allowed + */ +#define RDC_PDAP_D2R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2R_SHIFT)) & RDC_PDAP_D2R_MASK) + +#define RDC_PDAP_D3W_MASK (0x40U) +#define RDC_PDAP_D3W_SHIFT (6U) +/*! D3W - Domain 3 Write Access + * 0b0..No Write Access + * 0b1..Write Access Allowed + */ +#define RDC_PDAP_D3W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3W_SHIFT)) & RDC_PDAP_D3W_MASK) + +#define RDC_PDAP_D3R_MASK (0x80U) +#define RDC_PDAP_D3R_SHIFT (7U) +/*! D3R - Domain 3 Read Access + * 0b0..No Read Access + * 0b1..Read Access Allowed + */ +#define RDC_PDAP_D3R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3R_SHIFT)) & RDC_PDAP_D3R_MASK) + +#define RDC_PDAP_SREQ_MASK (0x40000000U) +#define RDC_PDAP_SREQ_SHIFT (30U) +/*! SREQ - Semaphore Required + * 0b0..Semaphores have no effect + * 0b1..Semaphores are enforced + */ +#define RDC_PDAP_SREQ(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK) + +#define RDC_PDAP_LCK_MASK (0x80000000U) +#define RDC_PDAP_LCK_SHIFT (31U) +/*! LCK - Peripheral Permissions Lock + * 0b0..Not Locked + * 0b1..Locked + */ +#define RDC_PDAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK) +/*! @} */ + +/* The count of RDC_PDAP */ +#define RDC_PDAP_COUNT (118U) + +/*! @name MRSA - Memory Region Start Address */ +/*! @{ */ + +#define RDC_MRSA_SADR_MASK (0xFFFFFF80U) +#define RDC_MRSA_SADR_SHIFT (7U) +/*! SADR - Start address for memory region + */ +#define RDC_MRSA_SADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK) +/*! @} */ + +/* The count of RDC_MRSA */ +#define RDC_MRSA_COUNT (52U) + +/*! @name MREA - Memory Region End Address */ +/*! @{ */ + +#define RDC_MREA_EADR_MASK (0xFFFFFF80U) +#define RDC_MREA_EADR_SHIFT (7U) +/*! EADR - Upper bound for memory region + */ +#define RDC_MREA_EADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK) +/*! @} */ + +/* The count of RDC_MREA */ +#define RDC_MREA_COUNT (52U) + +/*! @name MRC - Memory Region Control */ +/*! @{ */ + +#define RDC_MRC_D0W_MASK (0x1U) +#define RDC_MRC_D0W_SHIFT (0U) +/*! D0W - Domain 0 Write Access to Region + * 0b0..Processing Domain 0 does not have Write access to the memory region + * 0b1..Processing Domain 0 has Write access to the memory region + */ +#define RDC_MRC_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK) + +#define RDC_MRC_D0R_MASK (0x2U) +#define RDC_MRC_D0R_SHIFT (1U) +/*! D0R - Domain 0 Read Access to Region + * 0b0..Processing Domain 0 does not have Read access to the memory region + * 0b1..Processing Domain 0 has Read access to the memory region + */ +#define RDC_MRC_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK) + +#define RDC_MRC_D1W_MASK (0x4U) +#define RDC_MRC_D1W_SHIFT (2U) +/*! D1W - Domain 1 Write Access to Region + * 0b0..Processing Domain 1 does not have Write access to the memory region + * 0b1..Processing Domain 1 has Write access to the memory region + */ +#define RDC_MRC_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK) + +#define RDC_MRC_D1R_MASK (0x8U) +#define RDC_MRC_D1R_SHIFT (3U) +/*! D1R - Domain 1 Read Access to Region + * 0b0..Processing Domain 1 does not have Read access to the memory region + * 0b1..Processing Domain 1 has Read access to the memory region + */ +#define RDC_MRC_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK) + +#define RDC_MRC_D2W_MASK (0x10U) +#define RDC_MRC_D2W_SHIFT (4U) +/*! D2W - Domain 2 Write Access to Region + * 0b0..Processing Domain 2 does not have Write access to the memory region + * 0b1..Processing Domain 2 has Write access to the memory region + */ +#define RDC_MRC_D2W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2W_SHIFT)) & RDC_MRC_D2W_MASK) + +#define RDC_MRC_D2R_MASK (0x20U) +#define RDC_MRC_D2R_SHIFT (5U) +/*! D2R - Domain 2 Read Access to Region + * 0b0..Processing Domain 2 does not have Read access to the memory region + * 0b1..Processing Domain 2 has Read access to the memory region + */ +#define RDC_MRC_D2R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2R_SHIFT)) & RDC_MRC_D2R_MASK) + +#define RDC_MRC_D3W_MASK (0x40U) +#define RDC_MRC_D3W_SHIFT (6U) +/*! D3W - Domain 3 Write Access to Region + * 0b0..Processing Domain 3 does not have Write access to the memory region + * 0b1..Processing Domain 3 has Read access to the memory region + */ +#define RDC_MRC_D3W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3W_SHIFT)) & RDC_MRC_D3W_MASK) + +#define RDC_MRC_D3R_MASK (0x80U) +#define RDC_MRC_D3R_SHIFT (7U) +/*! D3R - Domain 3 Read Access to Region + * 0b0..Processing Domain 3 does not have Read access to the memory region + * 0b1..Processing Domain 3 has Read access to the memory region + */ +#define RDC_MRC_D3R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3R_SHIFT)) & RDC_MRC_D3R_MASK) + +#define RDC_MRC_ENA_MASK (0x40000000U) +#define RDC_MRC_ENA_SHIFT (30U) +/*! ENA - Region Enable + * 0b0..Memory region is not defined or restricted. + * 0b1..Memory boundaries, domain permissions and controls are in effect. + */ +#define RDC_MRC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK) + +#define RDC_MRC_LCK_MASK (0x80000000U) +#define RDC_MRC_LCK_SHIFT (31U) +/*! LCK - Region Lock + * 0b0..No Lock. All fields in this register may be modified. + * 0b1..Locked. No fields in this register may be modified except ENA, which may be set but not cleared. + */ +#define RDC_MRC_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK) +/*! @} */ + +/* The count of RDC_MRC */ +#define RDC_MRC_COUNT (52U) + +/*! @name MRVS - Memory Region Violation Status */ +/*! @{ */ + +#define RDC_MRVS_VDID_MASK (0x3U) +#define RDC_MRVS_VDID_SHIFT (0U) +/*! VDID - Violating Domain ID + * 0b00..Processing Domain 0 + * 0b01..Processing Domain 1 + * 0b10..Processing Domain 2 + * 0b11..Processing Domain 3 + */ +#define RDC_MRVS_VDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK) + +#define RDC_MRVS_AD_MASK (0x10U) +#define RDC_MRVS_AD_SHIFT (4U) +/*! AD - Access Denied + */ +#define RDC_MRVS_AD(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK) + +#define RDC_MRVS_VADR_MASK (0xFFFFFFE0U) +#define RDC_MRVS_VADR_SHIFT (5U) +/*! VADR - Violating Address + */ +#define RDC_MRVS_VADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK) +/*! @} */ + +/* The count of RDC_MRVS */ +#define RDC_MRVS_COUNT (52U) + + +/*! + * @} + */ /* end of group RDC_Register_Masks */ + + +/* RDC - Peripheral instance base addresses */ +/** Peripheral RDC base address */ +#define RDC_BASE (0x303D0000u) +/** Peripheral RDC base pointer */ +#define RDC ((RDC_Type *)RDC_BASE) +/** Array initializer of RDC peripheral base addresses */ +#define RDC_BASE_ADDRS { RDC_BASE } +/** Array initializer of RDC peripheral base pointers */ +#define RDC_BASE_PTRS { RDC } +/** Interrupt vectors for the RDC peripheral type */ +#define RDC_IRQS { RDC_IRQn } + +/*! + * @} + */ /* end of group RDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RDC_SEMAPHORE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer + * @{ + */ + +/** RDC_SEMAPHORE - Register Layout Typedef */ +typedef struct { + __IO uint8_t GATE0; /**< Gate Register, offset: 0x0 */ + __IO uint8_t GATE1; /**< Gate Register, offset: 0x1 */ + __IO uint8_t GATE2; /**< Gate Register, offset: 0x2 */ + __IO uint8_t GATE3; /**< Gate Register, offset: 0x3 */ + __IO uint8_t GATE4; /**< Gate Register, offset: 0x4 */ + __IO uint8_t GATE5; /**< Gate Register, offset: 0x5 */ + __IO uint8_t GATE6; /**< Gate Register, offset: 0x6 */ + __IO uint8_t GATE7; /**< Gate Register, offset: 0x7 */ + __IO uint8_t GATE8; /**< Gate Register, offset: 0x8 */ + __IO uint8_t GATE9; /**< Gate Register, offset: 0x9 */ + __IO uint8_t GATE10; /**< Gate Register, offset: 0xA */ + __IO uint8_t GATE11; /**< Gate Register, offset: 0xB */ + __IO uint8_t GATE12; /**< Gate Register, offset: 0xC */ + __IO uint8_t GATE13; /**< Gate Register, offset: 0xD */ + __IO uint8_t GATE14; /**< Gate Register, offset: 0xE */ + __IO uint8_t GATE15; /**< Gate Register, offset: 0xF */ + __IO uint8_t GATE16; /**< Gate Register, offset: 0x10 */ + __IO uint8_t GATE17; /**< Gate Register, offset: 0x11 */ + __IO uint8_t GATE18; /**< Gate Register, offset: 0x12 */ + __IO uint8_t GATE19; /**< Gate Register, offset: 0x13 */ + __IO uint8_t GATE20; /**< Gate Register, offset: 0x14 */ + __IO uint8_t GATE21; /**< Gate Register, offset: 0x15 */ + __IO uint8_t GATE22; /**< Gate Register, offset: 0x16 */ + __IO uint8_t GATE23; /**< Gate Register, offset: 0x17 */ + __IO uint8_t GATE24; /**< Gate Register, offset: 0x18 */ + __IO uint8_t GATE25; /**< Gate Register, offset: 0x19 */ + __IO uint8_t GATE26; /**< Gate Register, offset: 0x1A */ + __IO uint8_t GATE27; /**< Gate Register, offset: 0x1B */ + __IO uint8_t GATE28; /**< Gate Register, offset: 0x1C */ + __IO uint8_t GATE29; /**< Gate Register, offset: 0x1D */ + __IO uint8_t GATE30; /**< Gate Register, offset: 0x1E */ + __IO uint8_t GATE31; /**< Gate Register, offset: 0x1F */ + __IO uint8_t GATE32; /**< Gate Register, offset: 0x20 */ + __IO uint8_t GATE33; /**< Gate Register, offset: 0x21 */ + __IO uint8_t GATE34; /**< Gate Register, offset: 0x22 */ + __IO uint8_t GATE35; /**< Gate Register, offset: 0x23 */ + __IO uint8_t GATE36; /**< Gate Register, offset: 0x24 */ + __IO uint8_t GATE37; /**< Gate Register, offset: 0x25 */ + __IO uint8_t GATE38; /**< Gate Register, offset: 0x26 */ + __IO uint8_t GATE39; /**< Gate Register, offset: 0x27 */ + __IO uint8_t GATE40; /**< Gate Register, offset: 0x28 */ + __IO uint8_t GATE41; /**< Gate Register, offset: 0x29 */ + __IO uint8_t GATE42; /**< Gate Register, offset: 0x2A */ + __IO uint8_t GATE43; /**< Gate Register, offset: 0x2B */ + __IO uint8_t GATE44; /**< Gate Register, offset: 0x2C */ + __IO uint8_t GATE45; /**< Gate Register, offset: 0x2D */ + __IO uint8_t GATE46; /**< Gate Register, offset: 0x2E */ + __IO uint8_t GATE47; /**< Gate Register, offset: 0x2F */ + __IO uint8_t GATE48; /**< Gate Register, offset: 0x30 */ + __IO uint8_t GATE49; /**< Gate Register, offset: 0x31 */ + __IO uint8_t GATE50; /**< Gate Register, offset: 0x32 */ + __IO uint8_t GATE51; /**< Gate Register, offset: 0x33 */ + __IO uint8_t GATE52; /**< Gate Register, offset: 0x34 */ + __IO uint8_t GATE53; /**< Gate Register, offset: 0x35 */ + __IO uint8_t GATE54; /**< Gate Register, offset: 0x36 */ + __IO uint8_t GATE55; /**< Gate Register, offset: 0x37 */ + __IO uint8_t GATE56; /**< Gate Register, offset: 0x38 */ + __IO uint8_t GATE57; /**< Gate Register, offset: 0x39 */ + __IO uint8_t GATE58; /**< Gate Register, offset: 0x3A */ + __IO uint8_t GATE59; /**< Gate Register, offset: 0x3B */ + __IO uint8_t GATE60; /**< Gate Register, offset: 0x3C */ + __IO uint8_t GATE61; /**< Gate Register, offset: 0x3D */ + __IO uint8_t GATE62; /**< Gate Register, offset: 0x3E */ + __IO uint8_t GATE63; /**< Gate Register, offset: 0x3F */ + union { /* offset: 0x40 */ + __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */ + __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ + }; +} RDC_SEMAPHORE_Type; + +/* ---------------------------------------------------------------------------- + -- RDC_SEMAPHORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks + * @{ + */ + +/*! @name GATE0 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE0_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE0_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE0_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE0_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE0_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE0_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE0_LDOM_MASK) +/*! @} */ + +/*! @name GATE1 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE1_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE1_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE1_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE1_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE1_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE1_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE1_LDOM_MASK) +/*! @} */ + +/*! @name GATE2 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE2_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE2_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE2_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE2_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE2_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE2_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE2_LDOM_MASK) +/*! @} */ + +/*! @name GATE3 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE3_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE3_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE3_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE3_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE3_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE3_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE3_LDOM_MASK) +/*! @} */ + +/*! @name GATE4 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE4_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE4_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE4_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE4_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE4_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE4_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE4_LDOM_MASK) +/*! @} */ + +/*! @name GATE5 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE5_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE5_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE5_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE5_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE5_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE5_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE5_LDOM_MASK) +/*! @} */ + +/*! @name GATE6 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE6_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE6_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE6_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE6_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE6_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE6_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE6_LDOM_MASK) +/*! @} */ + +/*! @name GATE7 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE7_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE7_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE7_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE7_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE7_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE7_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE7_LDOM_MASK) +/*! @} */ + +/*! @name GATE8 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE8_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE8_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE8_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE8_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE8_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE8_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE8_LDOM_MASK) +/*! @} */ + +/*! @name GATE9 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE9_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE9_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE9_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE9_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE9_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE9_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE9_LDOM_MASK) +/*! @} */ + +/*! @name GATE10 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE10_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE10_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE10_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE10_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE10_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE10_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE10_LDOM_MASK) +/*! @} */ + +/*! @name GATE11 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE11_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE11_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE11_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE11_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE11_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE11_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE11_LDOM_MASK) +/*! @} */ + +/*! @name GATE12 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE12_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE12_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE12_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE12_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE12_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE12_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE12_LDOM_MASK) +/*! @} */ + +/*! @name GATE13 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE13_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE13_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE13_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE13_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE13_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE13_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE13_LDOM_MASK) +/*! @} */ + +/*! @name GATE14 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE14_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE14_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE14_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE14_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE14_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE14_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE14_LDOM_MASK) +/*! @} */ + +/*! @name GATE15 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE15_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE15_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE15_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE15_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE15_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE15_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE15_LDOM_MASK) +/*! @} */ + +/*! @name GATE16 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE16_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE16_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE16_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE16_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE16_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE16_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE16_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE16_LDOM_MASK) +/*! @} */ + +/*! @name GATE17 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE17_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE17_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE17_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE17_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE17_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE17_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE17_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE17_LDOM_MASK) +/*! @} */ + +/*! @name GATE18 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE18_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE18_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE18_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE18_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE18_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE18_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE18_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE18_LDOM_MASK) +/*! @} */ + +/*! @name GATE19 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE19_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE19_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE19_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE19_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE19_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE19_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE19_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE19_LDOM_MASK) +/*! @} */ + +/*! @name GATE20 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE20_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE20_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE20_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE20_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE20_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE20_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE20_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE20_LDOM_MASK) +/*! @} */ + +/*! @name GATE21 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE21_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE21_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE21_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE21_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE21_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE21_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE21_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE21_LDOM_MASK) +/*! @} */ + +/*! @name GATE22 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE22_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE22_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE22_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE22_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE22_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE22_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE22_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE22_LDOM_MASK) +/*! @} */ + +/*! @name GATE23 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE23_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE23_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE23_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE23_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE23_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE23_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE23_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE23_LDOM_MASK) +/*! @} */ + +/*! @name GATE24 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE24_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE24_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE24_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE24_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE24_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE24_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE24_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE24_LDOM_MASK) +/*! @} */ + +/*! @name GATE25 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE25_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE25_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE25_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE25_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE25_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE25_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE25_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE25_LDOM_MASK) +/*! @} */ + +/*! @name GATE26 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE26_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE26_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE26_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE26_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE26_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE26_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE26_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE26_LDOM_MASK) +/*! @} */ + +/*! @name GATE27 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE27_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE27_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE27_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE27_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE27_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE27_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE27_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE27_LDOM_MASK) +/*! @} */ + +/*! @name GATE28 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE28_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE28_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE28_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE28_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE28_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE28_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE28_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE28_LDOM_MASK) +/*! @} */ + +/*! @name GATE29 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE29_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE29_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE29_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE29_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE29_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE29_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE29_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE29_LDOM_MASK) +/*! @} */ + +/*! @name GATE30 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE30_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE30_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE30_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE30_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE30_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE30_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE30_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE30_LDOM_MASK) +/*! @} */ + +/*! @name GATE31 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE31_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE31_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE31_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE31_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE31_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE31_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE31_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE31_LDOM_MASK) +/*! @} */ + +/*! @name GATE32 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE32_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE32_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE32_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE32_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE32_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE32_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE32_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE32_LDOM_MASK) +/*! @} */ + +/*! @name GATE33 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE33_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE33_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE33_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE33_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE33_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE33_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE33_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE33_LDOM_MASK) +/*! @} */ + +/*! @name GATE34 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE34_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE34_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE34_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE34_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE34_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE34_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE34_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE34_LDOM_MASK) +/*! @} */ + +/*! @name GATE35 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE35_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE35_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE35_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE35_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE35_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE35_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE35_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE35_LDOM_MASK) +/*! @} */ + +/*! @name GATE36 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE36_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE36_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE36_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE36_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE36_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE36_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE36_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE36_LDOM_MASK) +/*! @} */ + +/*! @name GATE37 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE37_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE37_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE37_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE37_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE37_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE37_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE37_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE37_LDOM_MASK) +/*! @} */ + +/*! @name GATE38 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE38_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE38_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE38_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE38_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE38_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE38_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE38_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE38_LDOM_MASK) +/*! @} */ + +/*! @name GATE39 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE39_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE39_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE39_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE39_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE39_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE39_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE39_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE39_LDOM_MASK) +/*! @} */ + +/*! @name GATE40 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE40_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE40_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE40_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE40_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE40_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE40_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE40_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE40_LDOM_MASK) +/*! @} */ + +/*! @name GATE41 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE41_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE41_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE41_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE41_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE41_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE41_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE41_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE41_LDOM_MASK) +/*! @} */ + +/*! @name GATE42 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE42_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE42_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE42_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE42_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE42_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE42_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE42_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE42_LDOM_MASK) +/*! @} */ + +/*! @name GATE43 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE43_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE43_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE43_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE43_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE43_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE43_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE43_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE43_LDOM_MASK) +/*! @} */ + +/*! @name GATE44 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE44_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE44_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE44_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE44_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE44_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE44_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE44_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE44_LDOM_MASK) +/*! @} */ + +/*! @name GATE45 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE45_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE45_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE45_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE45_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE45_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE45_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE45_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE45_LDOM_MASK) +/*! @} */ + +/*! @name GATE46 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE46_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE46_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE46_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE46_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE46_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE46_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE46_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE46_LDOM_MASK) +/*! @} */ + +/*! @name GATE47 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE47_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE47_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE47_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE47_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE47_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE47_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE47_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE47_LDOM_MASK) +/*! @} */ + +/*! @name GATE48 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE48_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE48_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE48_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE48_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE48_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE48_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE48_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE48_LDOM_MASK) +/*! @} */ + +/*! @name GATE49 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE49_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE49_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE49_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE49_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE49_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE49_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE49_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE49_LDOM_MASK) +/*! @} */ + +/*! @name GATE50 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE50_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE50_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE50_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE50_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE50_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE50_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE50_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE50_LDOM_MASK) +/*! @} */ + +/*! @name GATE51 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE51_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE51_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE51_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE51_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE51_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE51_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE51_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE51_LDOM_MASK) +/*! @} */ + +/*! @name GATE52 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE52_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE52_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE52_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE52_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE52_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE52_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE52_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE52_LDOM_MASK) +/*! @} */ + +/*! @name GATE53 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE53_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE53_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE53_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE53_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE53_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE53_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE53_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE53_LDOM_MASK) +/*! @} */ + +/*! @name GATE54 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE54_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE54_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE54_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE54_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE54_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE54_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE54_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE54_LDOM_MASK) +/*! @} */ + +/*! @name GATE55 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE55_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE55_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE55_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE55_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE55_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE55_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE55_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE55_LDOM_MASK) +/*! @} */ + +/*! @name GATE56 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE56_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE56_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE56_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE56_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE56_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE56_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE56_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE56_LDOM_MASK) +/*! @} */ + +/*! @name GATE57 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE57_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE57_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE57_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE57_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE57_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE57_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE57_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE57_LDOM_MASK) +/*! @} */ + +/*! @name GATE58 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE58_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE58_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE58_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE58_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE58_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE58_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE58_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE58_LDOM_MASK) +/*! @} */ + +/*! @name GATE59 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE59_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE59_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE59_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE59_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE59_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE59_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE59_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE59_LDOM_MASK) +/*! @} */ + +/*! @name GATE60 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE60_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE60_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE60_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE60_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE60_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE60_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE60_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE60_LDOM_MASK) +/*! @} */ + +/*! @name GATE61 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE61_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE61_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE61_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE61_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE61_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE61_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE61_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE61_LDOM_MASK) +/*! @} */ + +/*! @name GATE62 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE62_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE62_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE62_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE62_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE62_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE62_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE62_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE62_LDOM_MASK) +/*! @} */ + +/*! @name GATE63 - Gate Register */ +/*! @{ */ + +#define RDC_SEMAPHORE_GATE63_GTFSM_MASK (0xFU) +#define RDC_SEMAPHORE_GATE63_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b0000..The gate is unlocked (free). + * 0b0001..The gate has been locked by processor with master_index = 0. + * 0b0010..The gate has been locked by processor with master_index = 1. + * 0b0011..The gate has been locked by processor with master_index = 2. + * 0b0100..The gate has been locked by processor with master_index = 3. + * 0b0101..The gate has been locked by processor with master_index = 4. + * 0b0110..The gate has been locked by processor with master_index = 5. + * 0b0111..The gate has been locked by processor with master_index = 6. + * 0b1000..The gate has been locked by processor with master_index = 7. + * 0b1001..The gate has been locked by processor with master_index = 8. + * 0b1010..The gate has been locked by processor with master_index = 9. + * 0b1011..The gate has been locked by processor with master_index = 10. + * 0b1100..The gate has been locked by processor with master_index = 11. + * 0b1101..The gate has been locked by processor with master_index = 12. + * 0b1110..The gate has been locked by processor with master_index = 13. + * 0b1111..The gate has been locked by processor with master_index = 14. + */ +#define RDC_SEMAPHORE_GATE63_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE63_GTFSM_MASK) + +#define RDC_SEMAPHORE_GATE63_LDOM_MASK (0x30U) +#define RDC_SEMAPHORE_GATE63_LDOM_SHIFT (4U) +/*! LDOM + * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b01..The gate has been locked by domain 1. + * 0b10..The gate has been locked by domain 2. + * 0b11..The gate has been locked by domain 3. + */ +#define RDC_SEMAPHORE_GATE63_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE63_LDOM_MASK) +/*! @} */ + +/*! @name RSTGT_R - Reset Gate Read */ +/*! @{ */ + +#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK (0xFU) +#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT (0U) +#define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK) + +#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK (0x30U) +#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT (4U) +/*! RSTGSM + * 0b00..Idle, waiting for the first data pattern write. + * 0b01..Waiting for the second data pattern write. + * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, + * this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists + * for only one clock cycle. Software will never be able to observe this state. + * 0b11..This state encoding is never used and therefore reserved. + */ +#define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK) + +#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK (0xFF00U) +#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT (8U) +#define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK) +/*! @} */ + +/*! @name RSTGT_W - Reset Gate Write */ +/*! @{ */ + +#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK (0xFFU) +#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT (0U) +#define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK) + +#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK (0xFF00U) +#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT (8U) +#define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RDC_SEMAPHORE_Register_Masks */ + + +/* RDC_SEMAPHORE - Peripheral instance base addresses */ +/** Peripheral RDC_SEMAPHORE1 base address */ +#define RDC_SEMAPHORE1_BASE (0x303B0000u) +/** Peripheral RDC_SEMAPHORE1 base pointer */ +#define RDC_SEMAPHORE1 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE) +/** Peripheral RDC_SEMAPHORE2 base address */ +#define RDC_SEMAPHORE2_BASE (0x303C0000u) +/** Peripheral RDC_SEMAPHORE2 base pointer */ +#define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE) +/** Array initializer of RDC_SEMAPHORE peripheral base addresses */ +#define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE } +/** Array initializer of RDC_SEMAPHORE peripheral base pointers */ +#define RDC_SEMAPHORE_BASE_PTRS { (RDC_SEMAPHORE_Type *)0u, RDC_SEMAPHORE1, RDC_SEMAPHORE2 } + +/*! + * @} + */ /* end of group RDC_SEMAPHORE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RD_SRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RD_SRC_Peripheral_Access_Layer RD_SRC Peripheral Access Layer + * @{ + */ + +/** RD_SRC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< Control register for Read surface., offset: 0x0 */ + __IO uint32_t SET; /**< Control register for Read surface., offset: 0x4 */ + __IO uint32_t CLR; /**< Control register for Read surface., offset: 0x8 */ + __IO uint32_t TOG; /**< Control register for Read surface., offset: 0xC */ + } CTRL_STATUS; + __IO uint32_t BASE_ADDR; /**< Read Surface Base address, offset: 0x10 */ + __IO uint32_t PITCH; /**< Read surface vertical pitch, offset: 0x14 */ + __IO uint32_t WIDTH; /**< Source frame buffer width, offset: 0x18 */ + __IO uint32_t HEIGHT; /**< Height of frame to be read, offset: 0x1C */ +} RD_SRC_Type; + +/* ---------------------------------------------------------------------------- + -- RD_SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RD_SRC_Register_Masks RD_SRC Register Masks + * @{ + */ + +/*! @name CTRL_STATUS - Control register for Read surface. */ +/*! @{ */ + +#define RD_SRC_CTRL_STATUS_ENABLE_MASK (0x1U) +#define RD_SRC_CTRL_STATUS_ENABLE_SHIFT (0U) +/*! ENABLE - Read surface enable. + */ +#define RD_SRC_CTRL_STATUS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_ENABLE_SHIFT)) & RD_SRC_CTRL_STATUS_ENABLE_MASK) + +#define RD_SRC_CTRL_STATUS_BPP_MASK (0x1CU) +#define RD_SRC_CTRL_STATUS_BPP_SHIFT (2U) +/*! BPP - Bits per pixel + */ +#define RD_SRC_CTRL_STATUS_BPP(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_BPP_SHIFT)) & RD_SRC_CTRL_STATUS_BPP_MASK) + +#define RD_SRC_CTRL_STATUS_T_SIZE_MASK (0x60U) +#define RD_SRC_CTRL_STATUS_T_SIZE_SHIFT (5U) +/*! T_SIZE - Transaction Size (T_SIZE) + */ +#define RD_SRC_CTRL_STATUS_T_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_T_SIZE_SHIFT)) & RD_SRC_CTRL_STATUS_T_SIZE_MASK) + +#define RD_SRC_CTRL_STATUS_P_SIZE_MASK (0x380U) +#define RD_SRC_CTRL_STATUS_P_SIZE_SHIFT (7U) +/*! P_SIZE - Payload size (P_SIZE) + */ +#define RD_SRC_CTRL_STATUS_P_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_P_SIZE_SHIFT)) & RD_SRC_CTRL_STATUS_P_SIZE_MASK) + +#define RD_SRC_CTRL_STATUS_FRAME_COMP_EN_MASK (0x4000U) +#define RD_SRC_CTRL_STATUS_FRAME_COMP_EN_SHIFT (14U) +/*! FRAME_COMP_EN - Frame complete IRQ enable + */ +#define RD_SRC_CTRL_STATUS_FRAME_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_FRAME_COMP_EN_SHIFT)) & RD_SRC_CTRL_STATUS_FRAME_COMP_EN_MASK) + +#define RD_SRC_CTRL_STATUS_RD_ERR_EN_MASK (0x8000U) +#define RD_SRC_CTRL_STATUS_RD_ERR_EN_SHIFT (15U) +/*! RD_ERR_EN - AXI Read Error IRQ enable + */ +#define RD_SRC_CTRL_STATUS_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_RD_ERR_EN_SHIFT)) & RD_SRC_CTRL_STATUS_RD_ERR_EN_MASK) + +#define RD_SRC_CTRL_STATUS_FIFO_SIZE_MASK (0x7F0000U) +#define RD_SRC_CTRL_STATUS_FIFO_SIZE_SHIFT (16U) +/*! FIFO_SIZE - FIFO size + */ +#define RD_SRC_CTRL_STATUS_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_FIFO_SIZE_SHIFT)) & RD_SRC_CTRL_STATUS_FIFO_SIZE_MASK) + +#define RD_SRC_CTRL_STATUS_FRAME_COMP_MASK (0x40000000U) +#define RD_SRC_CTRL_STATUS_FRAME_COMP_SHIFT (30U) +/*! FRAME_COMP - Frame processing complete + */ +#define RD_SRC_CTRL_STATUS_FRAME_COMP(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_FRAME_COMP_SHIFT)) & RD_SRC_CTRL_STATUS_FRAME_COMP_MASK) + +#define RD_SRC_CTRL_STATUS_RD_ERR_MASK (0x80000000U) +#define RD_SRC_CTRL_STATUS_RD_ERR_SHIFT (31U) +/*! RD_ERR - AXI Read Error + */ +#define RD_SRC_CTRL_STATUS_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_RD_ERR_SHIFT)) & RD_SRC_CTRL_STATUS_RD_ERR_MASK) +/*! @} */ + +/*! @name BASE_ADDR - Read Surface Base address */ +/*! @{ */ + +#define RD_SRC_BASE_ADDR_BASE_ADDR_MASK (0xFFFFFFFFU) +#define RD_SRC_BASE_ADDR_BASE_ADDR_SHIFT (0U) +/*! BASE_ADDR - Base address + */ +#define RD_SRC_BASE_ADDR_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_BASE_ADDR_BASE_ADDR_SHIFT)) & RD_SRC_BASE_ADDR_BASE_ADDR_MASK) +/*! @} */ + +/*! @name PITCH - Read surface vertical pitch */ +/*! @{ */ + +#define RD_SRC_PITCH_PITCH_MASK (0xFFFFU) +#define RD_SRC_PITCH_PITCH_SHIFT (0U) +/*! PITCH - Pitch + */ +#define RD_SRC_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_PITCH_PITCH_SHIFT)) & RD_SRC_PITCH_PITCH_MASK) +/*! @} */ + +/*! @name WIDTH - Source frame buffer width */ +/*! @{ */ + +#define RD_SRC_WIDTH_WIDTH_MASK (0xFFFFU) +#define RD_SRC_WIDTH_WIDTH_SHIFT (0U) +/*! WIDTH - Width + */ +#define RD_SRC_WIDTH_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_WIDTH_WIDTH_SHIFT)) & RD_SRC_WIDTH_WIDTH_MASK) +/*! @} */ + +/*! @name HEIGHT - Height of frame to be read */ +/*! @{ */ + +#define RD_SRC_HEIGHT_HEIGHT_MASK (0xFFFFU) +#define RD_SRC_HEIGHT_HEIGHT_SHIFT (0U) +/*! HEIGHT - Height + */ +#define RD_SRC_HEIGHT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_HEIGHT_HEIGHT_SHIFT)) & RD_SRC_HEIGHT_HEIGHT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RD_SRC_Register_Masks */ + + +/* RD_SRC - Peripheral instance base addresses */ +/** Peripheral DCSS__RD_SRC base address */ +#define DCSS__RD_SRC_BASE (0x32E22000u) +/** Peripheral DCSS__RD_SRC base pointer */ +#define DCSS__RD_SRC ((RD_SRC_Type *)DCSS__RD_SRC_BASE) +/** Array initializer of RD_SRC peripheral base addresses */ +#define RD_SRC_BASE_ADDRS { DCSS__RD_SRC_BASE } +/** Array initializer of RD_SRC peripheral base pointers */ +#define RD_SRC_BASE_PTRS { DCSS__RD_SRC } + +/*! + * @} + */ /* end of group RD_SRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ROMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer + * @{ + */ + +/** ROMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[212]; + __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ + __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ + uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ + __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ + __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[200]; + __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ +} ROMC_Type; + +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/*! @name ROMPATCHD - ROMC Data Registers */ +/*! @{ */ + +#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) +#define ROMC_ROMPATCHD_DATAX_SHIFT (0U) +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) +/*! @} */ + +/* The count of ROMC_ROMPATCHD */ +#define ROMC_ROMPATCHD_COUNT (8U) + +/*! @name ROMPATCHCNTL - ROMC Control Register */ +/*! @{ */ + +#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) +#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) +/*! DATAFIX + * 0b00000000..Address comparator triggers a opcode patch + * 0b00000001..Address comparator triggers a data fix + */ +#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) + +#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) +#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) +/*! DIS + * 0b0..Does not affect any ROMC functions (default) + * 0b1..Disable all ROMC functions: data fixing, and opcode patching + */ +#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) +/*! @} */ + +/*! @name ROMPATCHENL - ROMC Enable Register Low */ +/*! @{ */ + +#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) +#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) +/*! ENABLE + * 0b0000000000000000..Address comparator disabled + * 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + */ +#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) +/*! @} */ + +/*! @name ROMPATCHA - ROMC Address Registers */ +/*! @{ */ + +#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) +#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) +/*! THUMBX + * 0b0..Arm patch + * 0b1..THUMB patch (ignore if data fix) + */ +#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) + +#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) +#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) +#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) +/*! @} */ + +/* The count of ROMC_ROMPATCHA */ +#define ROMC_ROMPATCHA_COUNT (16U) + +/*! @name ROMPATCHSR - ROMC Status Register */ +/*! @{ */ + +#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) +#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) +/*! SOURCE + * 0b000000..Address Comparator 0 matched + * 0b000001..Address Comparator 1 matched + * 0b001111..Address Comparator 15 matched + */ +#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) + +#define ROMC_ROMPATCHSR_SW_MASK (0x20000U) +#define ROMC_ROMPATCHSR_SW_SHIFT (17U) +/*! SW + * 0b0..no event or comparator collisions + * 0b1..a collision has occurred + */ +#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ROMC_Register_Masks */ + + +/* ROMC - Peripheral instance base addresses */ +/** Peripheral ROMC base address */ +#define ROMC_BASE (0x30310000u) +/** Peripheral ROMC base pointer */ +#define ROMC ((ROMC_Type *)ROMC_BASE) +/** Array initializer of ROMC peripheral base addresses */ +#define ROMC_BASE_ADDRS { ROMC_BASE } +/** Array initializer of ROMC peripheral base pointers */ +#define ROMC_BASE_PTRS { ROMC } + +/*! + * @} + */ /* end of group ROMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SDMAARM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer + * @{ + */ + +/** SDMAARM - Register Layout Typedef */ +typedef struct { + __IO uint32_t MC0PTR; /**< Arm platform Channel 0 Pointer, offset: 0x0 */ + __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ + __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */ + __IO uint32_t HSTART; /**< Channel Start, offset: 0xC */ + __IO uint32_t EVTOVR; /**< Channel Event Override, offset: 0x10 */ + __IO uint32_t DSPOVR; /**< Channel BP Override, offset: 0x14 */ + __IO uint32_t HOSTOVR; /**< Channel Arm platform Override, offset: 0x18 */ + __IO uint32_t EVTPEND; /**< Channel Event Pending, offset: 0x1C */ + uint8_t RESERVED_0[4]; + __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ + __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */ + __IO uint32_t INTRMASK; /**< Channel Arm platform Interrupt Mask, offset: 0x2C */ + __I uint32_t PSW; /**< Schedule Status, offset: 0x30 */ + __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */ + __IO uint32_t CONFIG; /**< Configuration Register, offset: 0x38 */ + __IO uint32_t SDMA_LOCK; /**< SDMA LOCK, offset: 0x3C */ + __IO uint32_t ONCE_ENB; /**< OnCE Enable, offset: 0x40 */ + __IO uint32_t ONCE_DATA; /**< OnCE Data Register, offset: 0x44 */ + __IO uint32_t ONCE_INSTR; /**< OnCE Instruction Register, offset: 0x48 */ + __I uint32_t ONCE_STAT; /**< OnCE Status Register, offset: 0x4C */ + __IO uint32_t ONCE_CMD; /**< OnCE Command Register, offset: 0x50 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ILLINSTADDR; /**< Illegal Instruction Trap Address, offset: 0x58 */ + __IO uint32_t CHN0ADDR; /**< Channel 0 Boot Address, offset: 0x5C */ + __I uint32_t EVT_MIRROR; /**< DMA Requests, offset: 0x60 */ + __I uint32_t EVT_MIRROR2; /**< DMA Requests 2, offset: 0x64 */ + uint8_t RESERVED_2[8]; + __IO uint32_t XTRIG_CONF1; /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */ + __IO uint32_t XTRIG_CONF2; /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */ + uint8_t RESERVED_3[136]; + __IO uint32_t SDMA_CHNPRI[32]; /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_4[128]; + __IO uint32_t CHNENBL[48]; /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */ +} SDMAARM_Type; + +/* ---------------------------------------------------------------------------- + -- SDMAARM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks + * @{ + */ + +/*! @name MC0PTR - Arm platform Channel 0 Pointer */ +/*! @{ */ + +#define SDMAARM_MC0PTR_MC0PTR_MASK (0xFFFFFFFFU) +#define SDMAARM_MC0PTR_MC0PTR_SHIFT (0U) +#define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_MC0PTR_MC0PTR_SHIFT)) & SDMAARM_MC0PTR_MC0PTR_MASK) +/*! @} */ + +/*! @name INTR - Channel Interrupts */ +/*! @{ */ + +#define SDMAARM_INTR_HI_MASK (0xFFFFFFFFU) +#define SDMAARM_INTR_HI_SHIFT (0U) +#define SDMAARM_INTR_HI(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTR_HI_SHIFT)) & SDMAARM_INTR_HI_MASK) +/*! @} */ + +/*! @name STOP_STAT - Channel Stop/Channel Status */ +/*! @{ */ + +#define SDMAARM_STOP_STAT_HE_MASK (0xFFFFFFFFU) +#define SDMAARM_STOP_STAT_HE_SHIFT (0U) +#define SDMAARM_STOP_STAT_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_STOP_STAT_HE_SHIFT)) & SDMAARM_STOP_STAT_HE_MASK) +/*! @} */ + +/*! @name HSTART - Channel Start */ +/*! @{ */ + +#define SDMAARM_HSTART_HSTART_HE_MASK (0xFFFFFFFFU) +#define SDMAARM_HSTART_HSTART_HE_SHIFT (0U) +#define SDMAARM_HSTART_HSTART_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HSTART_HSTART_HE_SHIFT)) & SDMAARM_HSTART_HSTART_HE_MASK) +/*! @} */ + +/*! @name EVTOVR - Channel Event Override */ +/*! @{ */ + +#define SDMAARM_EVTOVR_EO_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTOVR_EO_SHIFT (0U) +#define SDMAARM_EVTOVR_EO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTOVR_EO_SHIFT)) & SDMAARM_EVTOVR_EO_MASK) +/*! @} */ + +/*! @name DSPOVR - Channel BP Override */ +/*! @{ */ + +#define SDMAARM_DSPOVR_DO_MASK (0xFFFFFFFFU) +#define SDMAARM_DSPOVR_DO_SHIFT (0U) +/*! DO + * 0b00000000000000000000000000000000..- Reserved + * 0b00000000000000000000000000000001..- Reset value. + */ +#define SDMAARM_DSPOVR_DO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DSPOVR_DO_SHIFT)) & SDMAARM_DSPOVR_DO_MASK) +/*! @} */ + +/*! @name HOSTOVR - Channel Arm platform Override */ +/*! @{ */ + +#define SDMAARM_HOSTOVR_HO_MASK (0xFFFFFFFFU) +#define SDMAARM_HOSTOVR_HO_SHIFT (0U) +#define SDMAARM_HOSTOVR_HO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HOSTOVR_HO_SHIFT)) & SDMAARM_HOSTOVR_HO_MASK) +/*! @} */ + +/*! @name EVTPEND - Channel Event Pending */ +/*! @{ */ + +#define SDMAARM_EVTPEND_EP_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTPEND_EP_SHIFT (0U) +#define SDMAARM_EVTPEND_EP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTPEND_EP_SHIFT)) & SDMAARM_EVTPEND_EP_MASK) +/*! @} */ + +/*! @name RESET - Reset Register */ +/*! @{ */ + +#define SDMAARM_RESET_RESET_MASK (0x1U) +#define SDMAARM_RESET_RESET_SHIFT (0U) +#define SDMAARM_RESET_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESET_SHIFT)) & SDMAARM_RESET_RESET_MASK) + +#define SDMAARM_RESET_RESCHED_MASK (0x2U) +#define SDMAARM_RESET_RESCHED_SHIFT (1U) +#define SDMAARM_RESET_RESCHED(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESCHED_SHIFT)) & SDMAARM_RESET_RESCHED_MASK) +/*! @} */ + +/*! @name EVTERR - DMA Request Error Register */ +/*! @{ */ + +#define SDMAARM_EVTERR_CHNERR_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTERR_CHNERR_SHIFT (0U) +#define SDMAARM_EVTERR_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERR_CHNERR_SHIFT)) & SDMAARM_EVTERR_CHNERR_MASK) +/*! @} */ + +/*! @name INTRMASK - Channel Arm platform Interrupt Mask */ +/*! @{ */ + +#define SDMAARM_INTRMASK_HIMASK_MASK (0xFFFFFFFFU) +#define SDMAARM_INTRMASK_HIMASK_SHIFT (0U) +#define SDMAARM_INTRMASK_HIMASK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTRMASK_HIMASK_SHIFT)) & SDMAARM_INTRMASK_HIMASK_MASK) +/*! @} */ + +/*! @name PSW - Schedule Status */ +/*! @{ */ + +#define SDMAARM_PSW_CCR_MASK (0xFU) +#define SDMAARM_PSW_CCR_SHIFT (0U) +#define SDMAARM_PSW_CCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCR_SHIFT)) & SDMAARM_PSW_CCR_MASK) + +#define SDMAARM_PSW_CCP_MASK (0xF0U) +#define SDMAARM_PSW_CCP_SHIFT (4U) +/*! CCP + * 0b0000..No running channel + * 0b0001..Active channel priority + */ +#define SDMAARM_PSW_CCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCP_SHIFT)) & SDMAARM_PSW_CCP_MASK) + +#define SDMAARM_PSW_NCR_MASK (0x1F00U) +#define SDMAARM_PSW_NCR_SHIFT (8U) +#define SDMAARM_PSW_NCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCR_SHIFT)) & SDMAARM_PSW_NCR_MASK) + +#define SDMAARM_PSW_NCP_MASK (0xE000U) +#define SDMAARM_PSW_NCP_SHIFT (13U) +/*! NCP + * 0b000..No running channel + * 0b001..Active channel priority + */ +#define SDMAARM_PSW_NCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCP_SHIFT)) & SDMAARM_PSW_NCP_MASK) +/*! @} */ + +/*! @name EVTERRDBG - DMA Request Error Register */ +/*! @{ */ + +#define SDMAARM_EVTERRDBG_CHNERR_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTERRDBG_CHNERR_SHIFT (0U) +#define SDMAARM_EVTERRDBG_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERRDBG_CHNERR_SHIFT)) & SDMAARM_EVTERRDBG_CHNERR_MASK) +/*! @} */ + +/*! @name CONFIG - Configuration Register */ +/*! @{ */ + +#define SDMAARM_CONFIG_CSM_MASK (0x3U) +#define SDMAARM_CONFIG_CSM_SHIFT (0U) +/*! CSM + * 0b00..static + * 0b01..dynamic low power + * 0b10..dynamic with no loop + * 0b11..dynamic + */ +#define SDMAARM_CONFIG_CSM(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_CSM_SHIFT)) & SDMAARM_CONFIG_CSM_MASK) + +#define SDMAARM_CONFIG_ACR_MASK (0x10U) +#define SDMAARM_CONFIG_ACR_SHIFT (4U) +/*! ACR + * 0b0..Arm platform DMA interface frequency equals twice core frequency + * 0b1..Arm platform DMA interface frequency equals core frequency + */ +#define SDMAARM_CONFIG_ACR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_ACR_SHIFT)) & SDMAARM_CONFIG_ACR_MASK) + +#define SDMAARM_CONFIG_RTDOBS_MASK (0x800U) +#define SDMAARM_CONFIG_RTDOBS_SHIFT (11U) +/*! RTDOBS + * 0b0..RTD pins disabled + * 0b1..RTD pins enabled + */ +#define SDMAARM_CONFIG_RTDOBS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_RTDOBS_SHIFT)) & SDMAARM_CONFIG_RTDOBS_MASK) + +#define SDMAARM_CONFIG_DSPDMA_MASK (0x1000U) +#define SDMAARM_CONFIG_DSPDMA_SHIFT (12U) +/*! DSPDMA + * 0b0..- Reset Value + * 0b1..- Reserved + */ +#define SDMAARM_CONFIG_DSPDMA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_DSPDMA_SHIFT)) & SDMAARM_CONFIG_DSPDMA_MASK) +/*! @} */ + +/*! @name SDMA_LOCK - SDMA LOCK */ +/*! @{ */ + +#define SDMAARM_SDMA_LOCK_LOCK_MASK (0x1U) +#define SDMAARM_SDMA_LOCK_LOCK_SHIFT (0U) +/*! LOCK + * 0b0..LOCK disengaged. + * 0b1..LOCK enabled. + */ +#define SDMAARM_SDMA_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_LOCK_SHIFT)) & SDMAARM_SDMA_LOCK_LOCK_MASK) + +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK (0x2U) +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT (1U) +/*! SRESET_LOCK_CLR + * 0b0..Software Reset does not clear the LOCK bit. + * 0b1..Software Reset clears the LOCK bit. + */ +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT)) & SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK) +/*! @} */ + +/*! @name ONCE_ENB - OnCE Enable */ +/*! @{ */ + +#define SDMAARM_ONCE_ENB_ENB_MASK (0x1U) +#define SDMAARM_ONCE_ENB_ENB_SHIFT (0U) +#define SDMAARM_ONCE_ENB_ENB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_ENB_ENB_SHIFT)) & SDMAARM_ONCE_ENB_ENB_MASK) +/*! @} */ + +/*! @name ONCE_DATA - OnCE Data Register */ +/*! @{ */ + +#define SDMAARM_ONCE_DATA_DATA_MASK (0xFFFFFFFFU) +#define SDMAARM_ONCE_DATA_DATA_SHIFT (0U) +#define SDMAARM_ONCE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_DATA_DATA_SHIFT)) & SDMAARM_ONCE_DATA_DATA_MASK) +/*! @} */ + +/*! @name ONCE_INSTR - OnCE Instruction Register */ +/*! @{ */ + +#define SDMAARM_ONCE_INSTR_INSTR_MASK (0xFFFFU) +#define SDMAARM_ONCE_INSTR_INSTR_SHIFT (0U) +#define SDMAARM_ONCE_INSTR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_INSTR_INSTR_SHIFT)) & SDMAARM_ONCE_INSTR_INSTR_MASK) +/*! @} */ + +/*! @name ONCE_STAT - OnCE Status Register */ +/*! @{ */ + +#define SDMAARM_ONCE_STAT_ECDR_MASK (0x7U) +#define SDMAARM_ONCE_STAT_ECDR_SHIFT (0U) +/*! ECDR + * 0b000..1 matched addra_cond + * 0b001..1 matched addrb_cond + * 0b010..1 matched data_cond + */ +#define SDMAARM_ONCE_STAT_ECDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ECDR_SHIFT)) & SDMAARM_ONCE_STAT_ECDR_MASK) + +#define SDMAARM_ONCE_STAT_MST_MASK (0x80U) +#define SDMAARM_ONCE_STAT_MST_SHIFT (7U) +/*! MST + * 0b0..The JTAG interface controls the OnCE. + * 0b1..The Arm platform peripheral interface controls the OnCE. + */ +#define SDMAARM_ONCE_STAT_MST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_MST_SHIFT)) & SDMAARM_ONCE_STAT_MST_MASK) + +#define SDMAARM_ONCE_STAT_SWB_MASK (0x100U) +#define SDMAARM_ONCE_STAT_SWB_SHIFT (8U) +#define SDMAARM_ONCE_STAT_SWB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_SWB_SHIFT)) & SDMAARM_ONCE_STAT_SWB_MASK) + +#define SDMAARM_ONCE_STAT_ODR_MASK (0x200U) +#define SDMAARM_ONCE_STAT_ODR_SHIFT (9U) +#define SDMAARM_ONCE_STAT_ODR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ODR_SHIFT)) & SDMAARM_ONCE_STAT_ODR_MASK) + +#define SDMAARM_ONCE_STAT_EDR_MASK (0x400U) +#define SDMAARM_ONCE_STAT_EDR_SHIFT (10U) +#define SDMAARM_ONCE_STAT_EDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_EDR_SHIFT)) & SDMAARM_ONCE_STAT_EDR_MASK) + +#define SDMAARM_ONCE_STAT_RCV_MASK (0x800U) +#define SDMAARM_ONCE_STAT_RCV_SHIFT (11U) +#define SDMAARM_ONCE_STAT_RCV(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_RCV_SHIFT)) & SDMAARM_ONCE_STAT_RCV_MASK) + +#define SDMAARM_ONCE_STAT_PST_MASK (0xF000U) +#define SDMAARM_ONCE_STAT_PST_SHIFT (12U) +/*! PST + * 0b0000..Program + * 0b0001..Data + * 0b0010..Change of Flow + * 0b0011..Change of Flow in Loop + * 0b0100..Debug + * 0b0101..Functional Unit + * 0b0110..Sleep + * 0b0111..Save + * 0b1000..Program in Sleep + * 0b1001..Data in Sleep + * 0b0010..Change of Flow in Sleep + * 0b0011..Change Flow in Loop in Sleep + * 0b1100..Debug in Sleep + * 0b1101..Functional Unit in Sleep + * 0b1110..Sleep after Reset + * 0b1111..Restore + */ +#define SDMAARM_ONCE_STAT_PST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_PST_SHIFT)) & SDMAARM_ONCE_STAT_PST_MASK) +/*! @} */ + +/*! @name ONCE_CMD - OnCE Command Register */ +/*! @{ */ + +#define SDMAARM_ONCE_CMD_CMD_MASK (0xFU) +#define SDMAARM_ONCE_CMD_CMD_SHIFT (0U) +/*! CMD + * 0b0000..rstatus + * 0b0001..dmov + * 0b0010..exec_once + * 0b0011..run_core + * 0b0100..exec_core + * 0b0101..debug_rqst + * 0b0110..rbuffer + */ +#define SDMAARM_ONCE_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_CMD_CMD_SHIFT)) & SDMAARM_ONCE_CMD_CMD_MASK) +/*! @} */ + +/*! @name ILLINSTADDR - Illegal Instruction Trap Address */ +/*! @{ */ + +#define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK (0x3FFFU) +#define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT (0U) +#define SDMAARM_ILLINSTADDR_ILLINSTADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT)) & SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK) +/*! @} */ + +/*! @name CHN0ADDR - Channel 0 Boot Address */ +/*! @{ */ + +#define SDMAARM_CHN0ADDR_CHN0ADDR_MASK (0x3FFFU) +#define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT (0U) +#define SDMAARM_CHN0ADDR_CHN0ADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT)) & SDMAARM_CHN0ADDR_CHN0ADDR_MASK) + +#define SDMAARM_CHN0ADDR_SMSZ_MASK (0x4000U) +#define SDMAARM_CHN0ADDR_SMSZ_SHIFT (14U) +/*! SMSZ + * 0b0..24 words per context + * 0b1..32 words per context + */ +#define SDMAARM_CHN0ADDR_SMSZ(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_SMSZ_SHIFT)) & SDMAARM_CHN0ADDR_SMSZ_MASK) +/*! @} */ + +/*! @name EVT_MIRROR - DMA Requests */ +/*! @{ */ + +#define SDMAARM_EVT_MIRROR_EVENTS_MASK (0xFFFFFFFFU) +#define SDMAARM_EVT_MIRROR_EVENTS_SHIFT (0U) +/*! EVENTS + * 0b00000000000000000000000000000000..DMA request event not pending + * 0b00000000000000000000000000000001..DMA request event pending + */ +#define SDMAARM_EVT_MIRROR_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR_EVENTS_MASK) +/*! @} */ + +/*! @name EVT_MIRROR2 - DMA Requests 2 */ +/*! @{ */ + +#define SDMAARM_EVT_MIRROR2_EVENTS_MASK (0xFFFFU) +#define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT (0U) +/*! EVENTS + * 0b0000000000000000..- DMA request event not pending + */ +#define SDMAARM_EVT_MIRROR2_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR2_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR2_EVENTS_MASK) +/*! @} */ + +/*! @name XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 */ +/*! @{ */ + +#define SDMAARM_XTRIG_CONF1_NUM0_MASK (0x3FU) +#define SDMAARM_XTRIG_CONF1_NUM0_SHIFT (0U) +#define SDMAARM_XTRIG_CONF1_NUM0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM0_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM0_MASK) + +#define SDMAARM_XTRIG_CONF1_CNF0_MASK (0x40U) +#define SDMAARM_XTRIG_CONF1_CNF0_SHIFT (6U) +/*! CNF0 + * 0b0..channel + * 0b1..DMA request + */ +#define SDMAARM_XTRIG_CONF1_CNF0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF0_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF0_MASK) + +#define SDMAARM_XTRIG_CONF1_NUM1_MASK (0x3F00U) +#define SDMAARM_XTRIG_CONF1_NUM1_SHIFT (8U) +#define SDMAARM_XTRIG_CONF1_NUM1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM1_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM1_MASK) + +#define SDMAARM_XTRIG_CONF1_CNF1_MASK (0x4000U) +#define SDMAARM_XTRIG_CONF1_CNF1_SHIFT (14U) +/*! CNF1 + * 0b0..channel + * 0b1..DMA request + */ +#define SDMAARM_XTRIG_CONF1_CNF1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF1_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF1_MASK) + +#define SDMAARM_XTRIG_CONF1_NUM2_MASK (0x3F0000U) +#define SDMAARM_XTRIG_CONF1_NUM2_SHIFT (16U) +#define SDMAARM_XTRIG_CONF1_NUM2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM2_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM2_MASK) + +#define SDMAARM_XTRIG_CONF1_CNF2_MASK (0x400000U) +#define SDMAARM_XTRIG_CONF1_CNF2_SHIFT (22U) +/*! CNF2 + * 0b0..channel + * 0b1..DMA request + */ +#define SDMAARM_XTRIG_CONF1_CNF2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF2_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF2_MASK) + +#define SDMAARM_XTRIG_CONF1_NUM3_MASK (0x3F000000U) +#define SDMAARM_XTRIG_CONF1_NUM3_SHIFT (24U) +#define SDMAARM_XTRIG_CONF1_NUM3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM3_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM3_MASK) + +#define SDMAARM_XTRIG_CONF1_CNF3_MASK (0x40000000U) +#define SDMAARM_XTRIG_CONF1_CNF3_SHIFT (30U) +/*! CNF3 + * 0b0..channel + * 0b1..DMA request + */ +#define SDMAARM_XTRIG_CONF1_CNF3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF3_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF3_MASK) +/*! @} */ + +/*! @name XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 */ +/*! @{ */ + +#define SDMAARM_XTRIG_CONF2_NUM4_MASK (0x3FU) +#define SDMAARM_XTRIG_CONF2_NUM4_SHIFT (0U) +#define SDMAARM_XTRIG_CONF2_NUM4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM4_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM4_MASK) + +#define SDMAARM_XTRIG_CONF2_CNF4_MASK (0x40U) +#define SDMAARM_XTRIG_CONF2_CNF4_SHIFT (6U) +/*! CNF4 + * 0b0..channel + * 0b1..DMA request + */ +#define SDMAARM_XTRIG_CONF2_CNF4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF4_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF4_MASK) + +#define SDMAARM_XTRIG_CONF2_NUM5_MASK (0x3F00U) +#define SDMAARM_XTRIG_CONF2_NUM5_SHIFT (8U) +#define SDMAARM_XTRIG_CONF2_NUM5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM5_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM5_MASK) + +#define SDMAARM_XTRIG_CONF2_CNF5_MASK (0x4000U) +#define SDMAARM_XTRIG_CONF2_CNF5_SHIFT (14U) +/*! CNF5 + * 0b0..channel + * 0b1..DMA request + */ +#define SDMAARM_XTRIG_CONF2_CNF5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF5_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF5_MASK) + +#define SDMAARM_XTRIG_CONF2_NUM6_MASK (0x3F0000U) +#define SDMAARM_XTRIG_CONF2_NUM6_SHIFT (16U) +#define SDMAARM_XTRIG_CONF2_NUM6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM6_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM6_MASK) + +#define SDMAARM_XTRIG_CONF2_CNF6_MASK (0x400000U) +#define SDMAARM_XTRIG_CONF2_CNF6_SHIFT (22U) +/*! CNF6 + * 0b0..channel + * 0b1..DMA request + */ +#define SDMAARM_XTRIG_CONF2_CNF6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF6_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF6_MASK) + +#define SDMAARM_XTRIG_CONF2_NUM7_MASK (0x3F000000U) +#define SDMAARM_XTRIG_CONF2_NUM7_SHIFT (24U) +#define SDMAARM_XTRIG_CONF2_NUM7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM7_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM7_MASK) + +#define SDMAARM_XTRIG_CONF2_CNF7_MASK (0x40000000U) +#define SDMAARM_XTRIG_CONF2_CNF7_SHIFT (30U) +/*! CNF7 + * 0b0..channel + * 0b1..DMA request + */ +#define SDMAARM_XTRIG_CONF2_CNF7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF7_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF7_MASK) +/*! @} */ + +/*! @name SDMA_CHNPRI - Channel Priority Registers */ +/*! @{ */ + +#define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK (0x7U) +#define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT (0U) +#define SDMAARM_SDMA_CHNPRI_CHNPRIn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT)) & SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK) +/*! @} */ + +/* The count of SDMAARM_SDMA_CHNPRI */ +#define SDMAARM_SDMA_CHNPRI_COUNT (32U) + +/*! @name CHNENBL - Channel Enable RAM */ +/*! @{ */ + +#define SDMAARM_CHNENBL_ENBLn_MASK (0xFFFFFFFFU) +#define SDMAARM_CHNENBL_ENBLn_SHIFT (0U) +#define SDMAARM_CHNENBL_ENBLn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHNENBL_ENBLn_SHIFT)) & SDMAARM_CHNENBL_ENBLn_MASK) +/*! @} */ + +/* The count of SDMAARM_CHNENBL */ +#define SDMAARM_CHNENBL_COUNT (48U) + + +/*! + * @} + */ /* end of group SDMAARM_Register_Masks */ + + +/* SDMAARM - Peripheral instance base addresses */ +/** Peripheral SDMAARM1 base address */ +#define SDMAARM1_BASE (0x30BD0000u) +/** Peripheral SDMAARM1 base pointer */ +#define SDMAARM1 ((SDMAARM_Type *)SDMAARM1_BASE) +/** Peripheral SDMAARM2 base address */ +#define SDMAARM2_BASE (0x302C0000u) +/** Peripheral SDMAARM2 base pointer */ +#define SDMAARM2 ((SDMAARM_Type *)SDMAARM2_BASE) +/** Array initializer of SDMAARM peripheral base addresses */ +#define SDMAARM_BASE_ADDRS { 0u, SDMAARM1_BASE, SDMAARM2_BASE } +/** Array initializer of SDMAARM peripheral base pointers */ +#define SDMAARM_BASE_PTRS { (SDMAARM_Type *)0u, SDMAARM1, SDMAARM2 } +/** Interrupt vectors for the SDMAARM peripheral type */ +#define SDMAARM_IRQS { NotAvail_IRQn, SDMA1_IRQn, SDMA2_IRQn } + +/*! + * @} + */ /* end of group SDMAARM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SEMA4 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer + * @{ + */ + +/** SEMA4 - Register Layout Typedef */ +typedef struct { + __IO uint8_t Gate00; /**< Semaphores Gate 0 Register, offset: 0x0 */ + __IO uint8_t Gate01; /**< Semaphores Gate 1 Register, offset: 0x1 */ + __IO uint8_t Gate02; /**< Semaphores Gate 2 Register, offset: 0x2 */ + __IO uint8_t Gate03; /**< Semaphores Gate 3 Register, offset: 0x3 */ + __IO uint8_t Gate04; /**< Semaphores Gate 4 Register, offset: 0x4 */ + __IO uint8_t Gate05; /**< Semaphores Gate 5 Register, offset: 0x5 */ + __IO uint8_t Gate06; /**< Semaphores Gate 6 Register, offset: 0x6 */ + __IO uint8_t Gate07; /**< Semaphores Gate 7 Register, offset: 0x7 */ + __IO uint8_t Gate08; /**< Semaphores Gate 8 Register, offset: 0x8 */ + __IO uint8_t Gate09; /**< Semaphores Gate 9 Register, offset: 0x9 */ + __IO uint8_t Gate10; /**< Semaphores Gate 10 Register, offset: 0xA */ + __IO uint8_t Gate11; /**< Semaphores Gate 11 Register, offset: 0xB */ + __IO uint8_t Gate12; /**< Semaphores Gate 12 Register, offset: 0xC */ + __IO uint8_t Gate13; /**< Semaphores Gate 13 Register, offset: 0xD */ + __IO uint8_t Gate14; /**< Semaphores Gate 14 Register, offset: 0xE */ + __IO uint8_t Gate15; /**< Semaphores Gate 15 Register, offset: 0xF */ + uint8_t RESERVED_0[48]; + struct { /* offset: 0x40, array step: 0x8 */ + __IO uint16_t CPINE; /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */ + uint8_t RESERVED_0[6]; + } CPINE[2]; + uint8_t RESERVED_1[48]; + struct { /* offset: 0x80, array step: 0x8 */ + __I uint16_t CPNTF; /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */ + uint8_t RESERVED_0[6]; + } CPNTF[2]; + uint8_t RESERVED_2[112]; + __IO uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */ + uint8_t RESERVED_3[2]; + __IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */ +} SEMA4_Type; + +/* ---------------------------------------------------------------------------- + -- SEMA4 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks + * @{ + */ + +/*! @name Gate00 - Semaphores Gate 0 Register */ +/*! @{ */ + +#define SEMA4_Gate00_GTFSM_MASK (0x3U) +#define SEMA4_Gate00_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate00_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate00_GTFSM_SHIFT)) & SEMA4_Gate00_GTFSM_MASK) +/*! @} */ + +/*! @name Gate01 - Semaphores Gate 1 Register */ +/*! @{ */ + +#define SEMA4_Gate01_GTFSM_MASK (0x3U) +#define SEMA4_Gate01_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate01_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate01_GTFSM_SHIFT)) & SEMA4_Gate01_GTFSM_MASK) +/*! @} */ + +/*! @name Gate02 - Semaphores Gate 2 Register */ +/*! @{ */ + +#define SEMA4_Gate02_GTFSM_MASK (0x3U) +#define SEMA4_Gate02_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate02_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate02_GTFSM_SHIFT)) & SEMA4_Gate02_GTFSM_MASK) +/*! @} */ + +/*! @name Gate03 - Semaphores Gate 3 Register */ +/*! @{ */ + +#define SEMA4_Gate03_GTFSM_MASK (0x3U) +#define SEMA4_Gate03_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate03_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate03_GTFSM_SHIFT)) & SEMA4_Gate03_GTFSM_MASK) +/*! @} */ + +/*! @name Gate04 - Semaphores Gate 4 Register */ +/*! @{ */ + +#define SEMA4_Gate04_GTFSM_MASK (0x3U) +#define SEMA4_Gate04_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate04_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate04_GTFSM_SHIFT)) & SEMA4_Gate04_GTFSM_MASK) +/*! @} */ + +/*! @name Gate05 - Semaphores Gate 5 Register */ +/*! @{ */ + +#define SEMA4_Gate05_GTFSM_MASK (0x3U) +#define SEMA4_Gate05_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate05_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate05_GTFSM_SHIFT)) & SEMA4_Gate05_GTFSM_MASK) +/*! @} */ + +/*! @name Gate06 - Semaphores Gate 6 Register */ +/*! @{ */ + +#define SEMA4_Gate06_GTFSM_MASK (0x3U) +#define SEMA4_Gate06_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate06_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate06_GTFSM_SHIFT)) & SEMA4_Gate06_GTFSM_MASK) +/*! @} */ + +/*! @name Gate07 - Semaphores Gate 7 Register */ +/*! @{ */ + +#define SEMA4_Gate07_GTFSM_MASK (0x3U) +#define SEMA4_Gate07_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate07_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate07_GTFSM_SHIFT)) & SEMA4_Gate07_GTFSM_MASK) +/*! @} */ + +/*! @name Gate08 - Semaphores Gate 8 Register */ +/*! @{ */ + +#define SEMA4_Gate08_GTFSM_MASK (0x3U) +#define SEMA4_Gate08_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate08_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate08_GTFSM_SHIFT)) & SEMA4_Gate08_GTFSM_MASK) +/*! @} */ + +/*! @name Gate09 - Semaphores Gate 9 Register */ +/*! @{ */ + +#define SEMA4_Gate09_GTFSM_MASK (0x3U) +#define SEMA4_Gate09_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate09_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate09_GTFSM_SHIFT)) & SEMA4_Gate09_GTFSM_MASK) +/*! @} */ + +/*! @name Gate10 - Semaphores Gate 10 Register */ +/*! @{ */ + +#define SEMA4_Gate10_GTFSM_MASK (0x3U) +#define SEMA4_Gate10_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate10_GTFSM_SHIFT)) & SEMA4_Gate10_GTFSM_MASK) +/*! @} */ + +/*! @name Gate11 - Semaphores Gate 11 Register */ +/*! @{ */ + +#define SEMA4_Gate11_GTFSM_MASK (0x3U) +#define SEMA4_Gate11_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate11_GTFSM_SHIFT)) & SEMA4_Gate11_GTFSM_MASK) +/*! @} */ + +/*! @name Gate12 - Semaphores Gate 12 Register */ +/*! @{ */ + +#define SEMA4_Gate12_GTFSM_MASK (0x3U) +#define SEMA4_Gate12_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate12_GTFSM_SHIFT)) & SEMA4_Gate12_GTFSM_MASK) +/*! @} */ + +/*! @name Gate13 - Semaphores Gate 13 Register */ +/*! @{ */ + +#define SEMA4_Gate13_GTFSM_MASK (0x3U) +#define SEMA4_Gate13_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate13_GTFSM_SHIFT)) & SEMA4_Gate13_GTFSM_MASK) +/*! @} */ + +/*! @name Gate14 - Semaphores Gate 14 Register */ +/*! @{ */ + +#define SEMA4_Gate14_GTFSM_MASK (0x3U) +#define SEMA4_Gate14_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate14_GTFSM_SHIFT)) & SEMA4_Gate14_GTFSM_MASK) +/*! @} */ + +/*! @name Gate15 - Semaphores Gate 15 Register */ +/*! @{ */ + +#define SEMA4_Gate15_GTFSM_MASK (0x3U) +#define SEMA4_Gate15_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine. + * 0b00..The gate is unlocked (free). + * 0b01..The gate has been locked by processor 0. + * 0b10..The gate has been locked by processor 1. + * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no + * operation" and do not affect the gate state machine. + */ +#define SEMA4_Gate15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate15_GTFSM_SHIFT)) & SEMA4_Gate15_GTFSM_MASK) +/*! @} */ + +/*! @name CPINE - Semaphores Processor n IRQ Notification Enable */ +/*! @{ */ + +#define SEMA4_CPINE_INE7_MASK (0x1U) +#define SEMA4_CPINE_INE7_SHIFT (0U) +/*! INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation + * of an interrupt notification from a failed attempt to lock gate 7. + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK) + +#define SEMA4_CPINE_INE6_MASK (0x2U) +#define SEMA4_CPINE_INE6_SHIFT (1U) +/*! INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation + * of an interrupt notification from a failed attempt to lock gate 6. + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK) + +#define SEMA4_CPINE_INE5_MASK (0x4U) +#define SEMA4_CPINE_INE5_SHIFT (2U) +/*! INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation + * of an interrupt notification from a failed attempt to lock gate 5. + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK) + +#define SEMA4_CPINE_INE4_MASK (0x8U) +#define SEMA4_CPINE_INE4_SHIFT (3U) +/*! INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation + * of an interrupt notification from a failed attempt to lock gate 4. + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK) + +#define SEMA4_CPINE_INE3_MASK (0x10U) +#define SEMA4_CPINE_INE3_SHIFT (4U) +/*! INE3 + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK) + +#define SEMA4_CPINE_INE2_MASK (0x20U) +#define SEMA4_CPINE_INE2_SHIFT (5U) +/*! INE2 + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK) + +#define SEMA4_CPINE_INE1_MASK (0x40U) +#define SEMA4_CPINE_INE1_SHIFT (6U) +/*! INE1 + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK) + +#define SEMA4_CPINE_INE0_MASK (0x80U) +#define SEMA4_CPINE_INE0_SHIFT (7U) +/*! INE0 + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK) + +#define SEMA4_CPINE_INE15_MASK (0x100U) +#define SEMA4_CPINE_INE15_SHIFT (8U) +/*! INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the + * generation of an interrupt notification from a failed attempt to lock gate 15. + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK) + +#define SEMA4_CPINE_INE14_MASK (0x200U) +#define SEMA4_CPINE_INE14_SHIFT (9U) +/*! INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the + * generation of an interrupt notification from a failed attempt to lock gate 14. + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK) + +#define SEMA4_CPINE_INE13_MASK (0x400U) +#define SEMA4_CPINE_INE13_SHIFT (10U) +/*! INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the + * generation of an interrupt notification from a failed attempt to lock gate 13. + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK) + +#define SEMA4_CPINE_INE12_MASK (0x800U) +#define SEMA4_CPINE_INE12_SHIFT (11U) +/*! INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the + * generation of an interrupt notification from a failed attempt to lock gate 12. + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK) + +#define SEMA4_CPINE_INE11_MASK (0x1000U) +#define SEMA4_CPINE_INE11_SHIFT (12U) +/*! INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the + * generation of an interrupt notification from a failed attempt to lock gate 11. + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK) + +#define SEMA4_CPINE_INE10_MASK (0x2000U) +#define SEMA4_CPINE_INE10_SHIFT (13U) +/*! INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the + * generation of an interrupt notification from a failed attempt to lock gate 10. + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK) + +#define SEMA4_CPINE_INE9_MASK (0x4000U) +#define SEMA4_CPINE_INE9_SHIFT (14U) +/*! INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation + * of an interrupt notification from a failed attempt to lock gate 9. + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK) + +#define SEMA4_CPINE_INE8_MASK (0x8000U) +#define SEMA4_CPINE_INE8_SHIFT (15U) +/*! INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation + * of an interrupt notification from a failed attempt to lock gate 8. + * 0b0..The generation of the notification interrupt is disabled. + * 0b1..The generation of the notification interrupt is enabled. + */ +#define SEMA4_CPINE_INE8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK) +/*! @} */ + +/* The count of SEMA4_CPINE */ +#define SEMA4_CPINE_COUNT (2U) + +/*! @name CPNTF - Semaphores Processor n IRQ Notification */ +/*! @{ */ + +#define SEMA4_CPNTF_GN7_MASK (0x1U) +#define SEMA4_CPNTF_GN7_SHIFT (0U) +#define SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK) + +#define SEMA4_CPNTF_GN6_MASK (0x2U) +#define SEMA4_CPNTF_GN6_SHIFT (1U) +#define SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK) + +#define SEMA4_CPNTF_GN5_MASK (0x4U) +#define SEMA4_CPNTF_GN5_SHIFT (2U) +#define SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK) + +#define SEMA4_CPNTF_GN4_MASK (0x8U) +#define SEMA4_CPNTF_GN4_SHIFT (3U) +#define SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK) + +#define SEMA4_CPNTF_GN3_MASK (0x10U) +#define SEMA4_CPNTF_GN3_SHIFT (4U) +#define SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK) + +#define SEMA4_CPNTF_GN2_MASK (0x20U) +#define SEMA4_CPNTF_GN2_SHIFT (5U) +#define SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK) + +#define SEMA4_CPNTF_GN1_MASK (0x40U) +#define SEMA4_CPNTF_GN1_SHIFT (6U) +#define SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK) + +#define SEMA4_CPNTF_GN0_MASK (0x80U) +#define SEMA4_CPNTF_GN0_SHIFT (7U) +#define SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK) + +#define SEMA4_CPNTF_GN15_MASK (0x100U) +#define SEMA4_CPNTF_GN15_SHIFT (8U) +#define SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK) + +#define SEMA4_CPNTF_GN14_MASK (0x200U) +#define SEMA4_CPNTF_GN14_SHIFT (9U) +#define SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK) + +#define SEMA4_CPNTF_GN13_MASK (0x400U) +#define SEMA4_CPNTF_GN13_SHIFT (10U) +#define SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK) + +#define SEMA4_CPNTF_GN12_MASK (0x800U) +#define SEMA4_CPNTF_GN12_SHIFT (11U) +#define SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK) + +#define SEMA4_CPNTF_GN11_MASK (0x1000U) +#define SEMA4_CPNTF_GN11_SHIFT (12U) +#define SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK) + +#define SEMA4_CPNTF_GN10_MASK (0x2000U) +#define SEMA4_CPNTF_GN10_SHIFT (13U) +#define SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK) + +#define SEMA4_CPNTF_GN9_MASK (0x4000U) +#define SEMA4_CPNTF_GN9_SHIFT (14U) +#define SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK) + +#define SEMA4_CPNTF_GN8_MASK (0x8000U) +#define SEMA4_CPNTF_GN8_SHIFT (15U) +#define SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK) +/*! @} */ + +/* The count of SEMA4_CPNTF */ +#define SEMA4_CPNTF_COUNT (2U) + +/*! @name RSTGT - Semaphores (Secure) Reset Gate n */ +/*! @{ */ + +#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK (0xFFU) +#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT (0U) +#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK) + +#define SEMA4_RSTGT_RSTGTN_MASK (0xFF00U) +#define SEMA4_RSTGT_RSTGTN_SHIFT (8U) +#define SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK) +/*! @} */ + +/*! @name RSTNTF - Semaphores (Secure) Reset IRQ Notification */ +/*! @{ */ + +#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK (0xFFU) +#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT (0U) +#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK) + +#define SEMA4_RSTNTF_RSTNTN_MASK (0xFF00U) +#define SEMA4_RSTNTF_RSTNTN_SHIFT (8U) +#define SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SEMA4_Register_Masks */ + + +/* SEMA4 - Peripheral instance base addresses */ +/** Peripheral SEMA4 base address */ +#define SEMA4_BASE (0x30AC0000u) +/** Peripheral SEMA4 base pointer */ +#define SEMA4 ((SEMA4_Type *)SEMA4_BASE) +/** Array initializer of SEMA4 peripheral base addresses */ +#define SEMA4_BASE_ADDRS { SEMA4_BASE } +/** Array initializer of SEMA4 peripheral base pointers */ +#define SEMA4_BASE_PTRS { SEMA4 } + +/*! + * @} + */ /* end of group SEMA4_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer + * @{ + */ + +/** SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ + __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */ + __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */ + __IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */ + __IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */ + __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ + __IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */ + __IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */ + __I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */ + __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */ + __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */ + __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ + __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ + __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ + __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ + __IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */ + __IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LPSECR; /**< SNVS_LP Security Events Configuration Register, offset: 0x48 */ + __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ + __IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */ + __IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */ + __IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */ + __I uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ + __I uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ + __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */ + __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */ + __IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ + uint8_t RESERVED_2[96]; + __IO uint32_t LPGPR[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_3[2792]; + __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ + __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ +} SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/*! @name HPLR - SNVS_HP Lock Register */ +/*! @{ */ + +#define SNVS_HPLR_ZMK_WSL_MASK (0x1U) +#define SNVS_HPLR_ZMK_WSL_SHIFT (0U) +/*! ZMK_WSL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) + +#define SNVS_HPLR_ZMK_RSL_MASK (0x2U) +#define SNVS_HPLR_ZMK_RSL_SHIFT (1U) +/*! ZMK_RSL + * 0b0..Read access is allowed (only in software Programming mode) + * 0b1..Read access is not allowed + */ +#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) + +#define SNVS_HPLR_SRTC_SL_MASK (0x4U) +#define SNVS_HPLR_SRTC_SL_SHIFT (2U) +/*! SRTC_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) + +#define SNVS_HPLR_LPCALB_SL_MASK (0x8U) +#define SNVS_HPLR_LPCALB_SL_SHIFT (3U) +/*! LPCALB_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) + +#define SNVS_HPLR_MC_SL_MASK (0x10U) +#define SNVS_HPLR_MC_SL_SHIFT (4U) +/*! MC_SL + * 0b0..Write access (increment) is allowed + * 0b1..Write access (increment) is not allowed + */ +#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) + +#define SNVS_HPLR_GPR_SL_MASK (0x20U) +#define SNVS_HPLR_GPR_SL_SHIFT (5U) +/*! GPR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) + +#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U) +#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U) +/*! LPSVCR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) + +#define SNVS_HPLR_LPSECR_SL_MASK (0x100U) +#define SNVS_HPLR_LPSECR_SL_SHIFT (8U) +/*! LPSECR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPSECR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK) + +#define SNVS_HPLR_MKS_SL_MASK (0x200U) +#define SNVS_HPLR_MKS_SL_SHIFT (9U) +/*! MKS_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) + +#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U) +#define SNVS_HPLR_HPSVCR_L_SHIFT (16U) +/*! HPSVCR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) + +#define SNVS_HPLR_HPSICR_L_MASK (0x20000U) +#define SNVS_HPLR_HPSICR_L_SHIFT (17U) +/*! HPSICR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) + +#define SNVS_HPLR_HAC_L_MASK (0x40000U) +#define SNVS_HPLR_HAC_L_SHIFT (18U) +/*! HAC_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) +/*! @} */ + +/*! @name HPCOMR - SNVS_HP Command Register */ +/*! @{ */ + +#define SNVS_HPCOMR_SSM_ST_MASK (0x1U) +#define SNVS_HPCOMR_SSM_ST_SHIFT (0U) +#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) + +#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) +#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) +/*! SSM_ST_DIS + * 0b0..Secure to Trusted State transition is enabled + * 0b1..Secure to Trusted State transition is disabled + */ +#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) + +#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) +#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) +/*! SSM_SFNS_DIS + * 0b0..Soft Fail to Non-Secure State transition is enabled + * 0b1..Soft Fail to Non-Secure State transition is disabled + */ +#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) + +#define SNVS_HPCOMR_LP_SWR_MASK (0x10U) +#define SNVS_HPCOMR_LP_SWR_SHIFT (4U) +/*! LP_SWR + * 0b0..No Action + * 0b1..Reset LP section + */ +#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) + +#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) +/*! LP_SWR_DIS + * 0b0..LP software reset is enabled + * 0b1..LP software reset is disabled + */ +#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) + +#define SNVS_HPCOMR_SW_SV_MASK (0x100U) +#define SNVS_HPCOMR_SW_SV_SHIFT (8U) +#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK) + +#define SNVS_HPCOMR_SW_FSV_MASK (0x200U) +#define SNVS_HPCOMR_SW_FSV_SHIFT (9U) +#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK) + +#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U) +#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U) +#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) + +#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) +#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) +/*! PROG_ZMK + * 0b0..No Action + * 0b1..Activate hardware key programming mechanism + */ +#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) + +#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) +#define SNVS_HPCOMR_MKS_EN_SHIFT (13U) +/*! MKS_EN + * 0b0..OTP master key is selected as an SNVS master key + * 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR + */ +#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) + +#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) +#define SNVS_HPCOMR_HAC_EN_SHIFT (16U) +/*! HAC_EN + * 0b0..High Assurance Counter is disabled + * 0b1..High Assurance Counter is enabled + */ +#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) + +#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) +#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) +/*! HAC_LOAD + * 0b0..No Action + * 0b1..Load the HAC + */ +#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) + +#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) +#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) +/*! HAC_CLEAR + * 0b0..No Action + * 0b1..Clear the HAC + */ +#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) + +#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) +#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U) +#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK) + +#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) +#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) +#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) +/*! @} */ + +/*! @name HPCR - SNVS_HP Control Register */ +/*! @{ */ + +#define SNVS_HPCR_RTC_EN_MASK (0x1U) +#define SNVS_HPCR_RTC_EN_SHIFT (0U) +/*! RTC_EN + * 0b0..RTC is disabled + * 0b1..RTC is enabled + */ +#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) + +#define SNVS_HPCR_HPTA_EN_MASK (0x2U) +#define SNVS_HPCR_HPTA_EN_SHIFT (1U) +/*! HPTA_EN + * 0b0..HP Time Alarm Interrupt is disabled + * 0b1..HP Time Alarm Interrupt is enabled + */ +#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) + +#define SNVS_HPCR_DIS_PI_MASK (0x4U) +#define SNVS_HPCR_DIS_PI_SHIFT (2U) +/*! DIS_PI + * 0b0..Periodic interrupt will trigger a functional interrupt + * 0b1..Disable periodic interrupt in the function interrupt + */ +#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) + +#define SNVS_HPCR_PI_EN_MASK (0x8U) +#define SNVS_HPCR_PI_EN_SHIFT (3U) +/*! PI_EN + * 0b0..HP Periodic Interrupt is disabled + * 0b1..HP Periodic Interrupt is enabled + */ +#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) + +#define SNVS_HPCR_PI_FREQ_MASK (0xF0U) +#define SNVS_HPCR_PI_FREQ_SHIFT (4U) +/*! PI_FREQ + * 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt + */ +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) + +#define SNVS_HPCR_HPCALB_EN_MASK (0x100U) +#define SNVS_HPCR_HPCALB_EN_SHIFT (8U) +/*! HPCALB_EN + * 0b0..HP Timer calibration disabled + * 0b1..HP Timer calibration enabled + */ +#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) + +#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) +#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) +/*! HPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter + * 0b00001..+1 counts per each 32768 ticks of the counter + * 0b00010..+2 counts per each 32768 ticks of the counter + * 0b01111..+15 counts per each 32768 ticks of the counter + * 0b10000..-16 counts per each 32768 ticks of the counter + * 0b10001..-15 counts per each 32768 ticks of the counter + * 0b11110..-2 counts per each 32768 ticks of the counter + * 0b11111..-1 counts per each 32768 ticks of the counter + */ +#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) + +#define SNVS_HPCR_HP_TS_MASK (0x10000U) +#define SNVS_HPCR_HP_TS_SHIFT (16U) +/*! HP_TS + * 0b0..No Action + * 0b1..Synchronize the HP Time Counter to the LP Time Counter + */ +#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) + +#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) +#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) +#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) + +#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) +#define SNVS_HPCR_BTN_MASK_SHIFT (27U) +#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) +/*! @} */ + +/*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ +/*! @{ */ + +#define SNVS_HPSICR_SV0_EN_MASK (0x1U) +#define SNVS_HPSICR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 Interrupt is Disabled + * 0b1..Security Violation 0 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) + +#define SNVS_HPSICR_SV1_EN_MASK (0x2U) +#define SNVS_HPSICR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 Interrupt is Disabled + * 0b1..Security Violation 1 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK) + +#define SNVS_HPSICR_SV2_EN_MASK (0x4U) +#define SNVS_HPSICR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 Interrupt is Disabled + * 0b1..Security Violation 2 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK) + +#define SNVS_HPSICR_SV3_EN_MASK (0x8U) +#define SNVS_HPSICR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 Interrupt is Disabled + * 0b1..Security Violation 3 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK) + +#define SNVS_HPSICR_SV4_EN_MASK (0x10U) +#define SNVS_HPSICR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 Interrupt is Disabled + * 0b1..Security Violation 4 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK) + +#define SNVS_HPSICR_SV5_EN_MASK (0x20U) +#define SNVS_HPSICR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 Interrupt is Disabled + * 0b1..Security Violation 5 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK) + +#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) +#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) +/*! LPSVI_EN + * 0b0..LP Security Violation Interrupt is Disabled + * 0b1..LP Security Violation Interrupt is Enabled + */ +#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) +/*! @} */ + +/*! @name HPSVCR - SNVS_HP Security Violation Control Register */ +/*! @{ */ + +#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) +#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) +/*! SV0_CFG + * 0b0..Security Violation 0 is a non-fatal violation + * 0b1..Security Violation 0 is a fatal violation + */ +#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) + +#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U) +#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U) +/*! SV1_CFG + * 0b0..Security Violation 1 is a non-fatal violation + * 0b1..Security Violation 1 is a fatal violation + */ +#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK) + +#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U) +#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U) +/*! SV2_CFG + * 0b0..Security Violation 2 is a non-fatal violation + * 0b1..Security Violation 2 is a fatal violation + */ +#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK) + +#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U) +#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U) +/*! SV3_CFG + * 0b0..Security Violation 3 is a non-fatal violation + * 0b1..Security Violation 3 is a fatal violation + */ +#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK) + +#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U) +#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U) +/*! SV4_CFG + * 0b0..Security Violation 4 is a non-fatal violation + * 0b1..Security Violation 4 is a fatal violation + */ +#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK) + +#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U) +#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U) +/*! SV5_CFG + * 0b00..Security Violation 5 is disabled + * 0b01..Security Violation 5 is a non-fatal violation + * 0b1x..Security Violation 5 is a fatal violation + */ +#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK) + +#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) +#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) +/*! LPSV_CFG + * 0b00..LP security violation is disabled + * 0b01..LP security violation is a non-fatal violation + * 0b1x..LP security violation is a fatal violation + */ +#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) +/*! @} */ + +/*! @name HPSR - SNVS_HP Status Register */ +/*! @{ */ + +#define SNVS_HPSR_HPTA_MASK (0x1U) +#define SNVS_HPSR_HPTA_SHIFT (0U) +/*! HPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ +#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) + +#define SNVS_HPSR_PI_MASK (0x2U) +#define SNVS_HPSR_PI_SHIFT (1U) +/*! PI + * 0b0..No periodic interrupt occurred. + * 0b1..A periodic interrupt occurred. + */ +#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) + +#define SNVS_HPSR_LPDIS_MASK (0x10U) +#define SNVS_HPSR_LPDIS_SHIFT (4U) +#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK) + +#define SNVS_HPSR_BTN_MASK (0x40U) +#define SNVS_HPSR_BTN_SHIFT (6U) +#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) + +#define SNVS_HPSR_BI_MASK (0x80U) +#define SNVS_HPSR_BI_SHIFT (7U) +#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) + +#define SNVS_HPSR_SSM_STATE_MASK (0xF00U) +#define SNVS_HPSR_SSM_STATE_SHIFT (8U) +/*! SSM_STATE + * 0b0000..Init + * 0b0001..Hard Fail + * 0b0011..Soft Fail + * 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) + * 0b1001..Check + * 0b1011..Non-Secure + * 0b1101..Trusted + * 0b1111..Secure + */ +#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) + +#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U) +#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U) +/*! SECURITY_CONFIG + * 0b0000, 0b1000..FAB configuration + * 0b0001, 0b0010, 0b0011..OPEN configuration + * 0b1010, 0b1001, 0b1011..CLOSED configuration + * 0bx1xx..FIELD RETURN configuration + */ +#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK) + +#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK) + +#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) +#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) +/*! OTPMK_ZERO + * 0b0..The OTPMK is not zero. + * 0b1..The OTPMK is zero. + */ +#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) + +#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) +#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) +/*! ZMK_ZERO + * 0b0..The ZMK is not zero. + * 0b1..The ZMK is zero. + */ +#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) +/*! @} */ + +/*! @name HPSVSR - SNVS_HP Security Violation Status Register */ +/*! @{ */ + +#define SNVS_HPSVSR_SV0_MASK (0x1U) +#define SNVS_HPSVSR_SV0_SHIFT (0U) +/*! SV0 + * 0b0..No Security Violation 0 security violation was detected. + * 0b1..Security Violation 0 security violation was detected. + */ +#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) + +#define SNVS_HPSVSR_SV1_MASK (0x2U) +#define SNVS_HPSVSR_SV1_SHIFT (1U) +/*! SV1 + * 0b0..No Security Violation 1 security violation was detected. + * 0b1..Security Violation 1 security violation was detected. + */ +#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK) + +#define SNVS_HPSVSR_SV2_MASK (0x4U) +#define SNVS_HPSVSR_SV2_SHIFT (2U) +/*! SV2 + * 0b0..No Security Violation 2 security violation was detected. + * 0b1..Security Violation 2 security violation was detected. + */ +#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK) + +#define SNVS_HPSVSR_SV3_MASK (0x8U) +#define SNVS_HPSVSR_SV3_SHIFT (3U) +/*! SV3 + * 0b0..No Security Violation 3 security violation was detected. + * 0b1..Security Violation 3 security violation was detected. + */ +#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK) + +#define SNVS_HPSVSR_SV4_MASK (0x10U) +#define SNVS_HPSVSR_SV4_SHIFT (4U) +/*! SV4 + * 0b0..No Security Violation 4 security violation was detected. + * 0b1..Security Violation 4 security violation was detected. + */ +#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK) + +#define SNVS_HPSVSR_SV5_MASK (0x20U) +#define SNVS_HPSVSR_SV5_SHIFT (5U) +/*! SV5 + * 0b0..No Security Violation 5 security violation was detected. + * 0b1..Security Violation 5 security violation was detected. + */ +#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK) + +#define SNVS_HPSVSR_SW_SV_MASK (0x2000U) +#define SNVS_HPSVSR_SW_SV_SHIFT (13U) +#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK) + +#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U) +#define SNVS_HPSVSR_SW_FSV_SHIFT (14U) +#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK) + +#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U) +#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U) +#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK) + +#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) + +#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) +#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) +/*! ZMK_ECC_FAIL + * 0b0..ZMK ECC Failure was not detected. + * 0b1..ZMK ECC Failure was detected. + */ +#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) + +#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) +#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) +#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) +/*! @} */ + +/*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ +/*! @{ */ + +#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) +#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) +#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) +/*! @} */ + +/*! @name HPHACR - SNVS_HP High Assurance Counter Register */ +/*! @{ */ + +#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) +#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) +/*! @} */ + +/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ +/*! @{ */ + +#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) +#define SNVS_HPRTCMR_RTC_SHIFT (0U) +#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) +/*! @} */ + +/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ +/*! @{ */ + +#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCLR_RTC_SHIFT (0U) +#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) +/*! @} */ + +/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +/*! @{ */ + +#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) +#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) +#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) +/*! @} */ + +/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +/*! @{ */ + +#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) +#define SNVS_HPTALR_HPTA_LS_SHIFT (0U) +#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) +/*! @} */ + +/*! @name LPLR - SNVS_LP Lock Register */ +/*! @{ */ + +#define SNVS_LPLR_ZMK_WHL_MASK (0x1U) +#define SNVS_LPLR_ZMK_WHL_SHIFT (0U) +/*! ZMK_WHL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) + +#define SNVS_LPLR_ZMK_RHL_MASK (0x2U) +#define SNVS_LPLR_ZMK_RHL_SHIFT (1U) +/*! ZMK_RHL + * 0b0..Read access is allowed (only in software programming mode). + * 0b1..Read access is not allowed. + */ +#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) + +#define SNVS_LPLR_SRTC_HL_MASK (0x4U) +#define SNVS_LPLR_SRTC_HL_SHIFT (2U) +/*! SRTC_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) + +#define SNVS_LPLR_LPCALB_HL_MASK (0x8U) +#define SNVS_LPLR_LPCALB_HL_SHIFT (3U) +/*! LPCALB_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) + +#define SNVS_LPLR_MC_HL_MASK (0x10U) +#define SNVS_LPLR_MC_HL_SHIFT (4U) +/*! MC_HL + * 0b0..Write access (increment) is allowed. + * 0b1..Write access (increment) is not allowed. + */ +#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) + +#define SNVS_LPLR_GPR_HL_MASK (0x20U) +#define SNVS_LPLR_GPR_HL_SHIFT (5U) +/*! GPR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) + +#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U) +#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U) +/*! LPSVCR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) + +#define SNVS_LPLR_LPSECR_HL_MASK (0x100U) +#define SNVS_LPLR_LPSECR_HL_SHIFT (8U) +/*! LPSECR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPSECR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK) + +#define SNVS_LPLR_MKS_HL_MASK (0x200U) +#define SNVS_LPLR_MKS_HL_SHIFT (9U) +/*! MKS_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) +/*! @} */ + +/*! @name LPCR - SNVS_LP Control Register */ +/*! @{ */ + +#define SNVS_LPCR_SRTC_ENV_MASK (0x1U) +#define SNVS_LPCR_SRTC_ENV_SHIFT (0U) +/*! SRTC_ENV + * 0b0..SRTC is disabled or invalid. + * 0b1..SRTC is enabled and valid. + */ +#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) + +#define SNVS_LPCR_LPTA_EN_MASK (0x2U) +#define SNVS_LPCR_LPTA_EN_SHIFT (1U) +/*! LPTA_EN + * 0b0..LP time alarm interrupt is disabled. + * 0b1..LP time alarm interrupt is enabled. + */ +#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) + +#define SNVS_LPCR_MC_ENV_MASK (0x4U) +#define SNVS_LPCR_MC_ENV_SHIFT (2U) +/*! MC_ENV + * 0b0..MC is disabled or invalid. + * 0b1..MC is enabled and valid. + */ +#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) + +#define SNVS_LPCR_LPWUI_EN_MASK (0x8U) +#define SNVS_LPCR_LPWUI_EN_SHIFT (3U) +#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) + +#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) +#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) +/*! SRTC_INV_EN + * 0b0..SRTC stays valid in the case of security violation. + * 0b1..SRTC is invalidated in the case of security violation. + */ +#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) + +#define SNVS_LPCR_DP_EN_MASK (0x20U) +#define SNVS_LPCR_DP_EN_SHIFT (5U) +/*! DP_EN + * 0b0..Smart PMIC enabled. + * 0b1..Dumb PMIC enabled. + */ +#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) + +#define SNVS_LPCR_TOP_MASK (0x40U) +#define SNVS_LPCR_TOP_SHIFT (6U) +/*! TOP + * 0b0..Leave system power on. + * 0b1..Turn off system power. + */ +#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) + +#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) +#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) +#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) + +#define SNVS_LPCR_LPCALB_EN_MASK (0x100U) +#define SNVS_LPCR_LPCALB_EN_SHIFT (8U) +/*! LPCALB_EN + * 0b0..SRTC Time calibration is disabled. + * 0b1..SRTC Time calibration is enabled. + */ +#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) + +#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) +#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U) +/*! LPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter clock + * 0b00001..+1 counts per each 32768 ticks of the counter clock + * 0b00010..+2 counts per each 32768 ticks of the counter clock + * 0b01111..+15 counts per each 32768 ticks of the counter clock + * 0b10000..-16 counts per each 32768 ticks of the counter clock + * 0b10001..-15 counts per each 32768 ticks of the counter clock + * 0b11110..-2 counts per each 32768 ticks of the counter clock + * 0b11111..-1 counts per each 32768 ticks of the counter clock + */ +#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) + +#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) +#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) +#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) + +#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) +#define SNVS_LPCR_DEBOUNCE_SHIFT (18U) +#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) + +#define SNVS_LPCR_ON_TIME_MASK (0x300000U) +#define SNVS_LPCR_ON_TIME_SHIFT (20U) +#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) + +#define SNVS_LPCR_PK_EN_MASK (0x400000U) +#define SNVS_LPCR_PK_EN_SHIFT (22U) +#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) + +#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) +#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) +#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) + +#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) +#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) +#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) +/*! @} */ + +/*! @name LPMKCR - SNVS_LP Master Key Control Register */ +/*! @{ */ + +#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) +#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) +/*! MASTER_KEY_SEL + * 0b0x..Select one time programmable master key. + * 0b10..Select zeroizable master key when MKS_EN bit is set . + * 0b11..Select combined master key when MKS_EN bit is set . + */ +#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) + +#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) +#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) +/*! ZMK_HWP + * 0b0..ZMK is in the software programming mode. + * 0b1..ZMK is in the hardware programming mode. + */ +#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) + +#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) +#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) +/*! ZMK_VAL + * 0b0..ZMK is not valid. + * 0b1..ZMK is valid. + */ +#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) + +#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) +#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) +/*! ZMK_ECC_EN + * 0b0..ZMK ECC check is disabled. + * 0b1..ZMK ECC check is enabled. + */ +#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) + +#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) +/*! @} */ + +/*! @name LPSVCR - SNVS_LP Security Violation Control Register */ +/*! @{ */ + +#define SNVS_LPSVCR_SV0_EN_MASK (0x1U) +#define SNVS_LPSVCR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 is disabled in the LP domain. + * 0b1..Security Violation 0 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) + +#define SNVS_LPSVCR_SV1_EN_MASK (0x2U) +#define SNVS_LPSVCR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 is disabled in the LP domain. + * 0b1..Security Violation 1 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK) + +#define SNVS_LPSVCR_SV2_EN_MASK (0x4U) +#define SNVS_LPSVCR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 is disabled in the LP domain. + * 0b1..Security Violation 2 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK) + +#define SNVS_LPSVCR_SV3_EN_MASK (0x8U) +#define SNVS_LPSVCR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 is disabled in the LP domain. + * 0b1..Security Violation 3 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK) + +#define SNVS_LPSVCR_SV4_EN_MASK (0x10U) +#define SNVS_LPSVCR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 is disabled in the LP domain. + * 0b1..Security Violation 4 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK) + +#define SNVS_LPSVCR_SV5_EN_MASK (0x20U) +#define SNVS_LPSVCR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 is disabled in the LP domain. + * 0b1..Security Violation 5 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) +/*! @} */ + +/*! @name LPSECR - SNVS_LP Security Events Configuration Register */ +/*! @{ */ + +#define SNVS_LPSECR_SRTCR_EN_MASK (0x2U) +#define SNVS_LPSECR_SRTCR_EN_SHIFT (1U) +/*! SRTCR_EN + * 0b0..SRTC rollover is disabled. + * 0b1..SRTC rollover is enabled. + */ +#define SNVS_LPSECR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_SRTCR_EN_SHIFT)) & SNVS_LPSECR_SRTCR_EN_MASK) + +#define SNVS_LPSECR_MCR_EN_MASK (0x4U) +#define SNVS_LPSECR_MCR_EN_SHIFT (2U) +/*! MCR_EN + * 0b0..MC rollover is disabled. + * 0b1..MC rollover is enabled. + */ +#define SNVS_LPSECR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_MCR_EN_SHIFT)) & SNVS_LPSECR_MCR_EN_MASK) + +#define SNVS_LPSECR_PFD_OBSERV_MASK (0x4000U) +#define SNVS_LPSECR_PFD_OBSERV_SHIFT (14U) +#define SNVS_LPSECR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_PFD_OBSERV_SHIFT)) & SNVS_LPSECR_PFD_OBSERV_MASK) + +#define SNVS_LPSECR_POR_OBSERV_MASK (0x8000U) +#define SNVS_LPSECR_POR_OBSERV_SHIFT (15U) +#define SNVS_LPSECR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_POR_OBSERV_SHIFT)) & SNVS_LPSECR_POR_OBSERV_MASK) + +#define SNVS_LPSECR_LTDC_MASK (0x70000U) +#define SNVS_LPSECR_LTDC_SHIFT (16U) +#define SNVS_LPSECR_LTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_LTDC_SHIFT)) & SNVS_LPSECR_LTDC_MASK) + +#define SNVS_LPSECR_HTDC_MASK (0x700000U) +#define SNVS_LPSECR_HTDC_SHIFT (20U) +#define SNVS_LPSECR_HTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_HTDC_SHIFT)) & SNVS_LPSECR_HTDC_MASK) + +#define SNVS_LPSECR_VRC_MASK (0x7000000U) +#define SNVS_LPSECR_VRC_SHIFT (24U) +#define SNVS_LPSECR_VRC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_VRC_SHIFT)) & SNVS_LPSECR_VRC_MASK) + +#define SNVS_LPSECR_OSCB_MASK (0x10000000U) +#define SNVS_LPSECR_OSCB_SHIFT (28U) +/*! OSCB + * 0b0..Normal SRTC clock oscillator not bypassed. + * 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. + */ +#define SNVS_LPSECR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_OSCB_SHIFT)) & SNVS_LPSECR_OSCB_MASK) +/*! @} */ + +/*! @name LPSR - SNVS_LP Status Register */ +/*! @{ */ + +#define SNVS_LPSR_LPTA_MASK (0x1U) +#define SNVS_LPSR_LPTA_SHIFT (0U) +/*! LPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ +#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) + +#define SNVS_LPSR_SRTCR_MASK (0x2U) +#define SNVS_LPSR_SRTCR_SHIFT (1U) +/*! SRTCR + * 0b0..SRTC has not reached its maximum value. + * 0b1..SRTC has reached its maximum value. + */ +#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) + +#define SNVS_LPSR_MCR_MASK (0x4U) +#define SNVS_LPSR_MCR_SHIFT (2U) +/*! MCR + * 0b0..MC has not reached its maximum value. + * 0b1..MC has reached its maximum value. + */ +#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) + +#define SNVS_LPSR_PGD_MASK (0x8U) +#define SNVS_LPSR_PGD_SHIFT (3U) +#define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK) + +#define SNVS_LPSR_ESVD_MASK (0x10000U) +#define SNVS_LPSR_ESVD_SHIFT (16U) +/*! ESVD + * 0b0..No external security violation. + * 0b1..External security violation is detected. + */ +#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) + +#define SNVS_LPSR_EO_MASK (0x20000U) +#define SNVS_LPSR_EO_SHIFT (17U) +/*! EO + * 0b0..Emergency off was not detected. + * 0b1..Emergency off was detected. + */ +#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) + +#define SNVS_LPSR_SPO_MASK (0x40000U) +#define SNVS_LPSR_SPO_SHIFT (18U) +/*! SPO + * 0b0..Set Power Off was not detected. + * 0b1..Set Power Off was detected. + */ +#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) + +#define SNVS_LPSR_LPNS_MASK (0x40000000U) +#define SNVS_LPSR_LPNS_SHIFT (30U) +/*! LPNS + * 0b0..LP section was not programmed in the non-secure state. + * 0b1..LP section was programmed in the non-secure state. + */ +#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) + +#define SNVS_LPSR_LPS_MASK (0x80000000U) +#define SNVS_LPSR_LPS_SHIFT (31U) +/*! LPS + * 0b0..LP section was not programmed in secure or trusted state. + * 0b1..LP section was programmed in secure or trusted state. + */ +#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) +/*! @} */ + +/*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ +/*! @{ */ + +#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) +#define SNVS_LPSRTCMR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) +/*! @} */ + +/*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ +/*! @{ */ + +#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) +#define SNVS_LPSRTCLR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) +/*! @} */ + +/*! @name LPTAR - SNVS_LP Time Alarm Register */ +/*! @{ */ + +#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) +#define SNVS_LPTAR_LPTA_SHIFT (0U) +#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) +/*! @} */ + +/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +/*! @{ */ + +#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) +#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) + +#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) +#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) +#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) +/*! @} */ + +/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +/*! @{ */ + +#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) +/*! @} */ + +/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ +/*! @{ */ + +#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) +#define SNVS_LPPGDR_PGD_SHIFT (0U) +#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) +/*! @} */ + +/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ +/*! @{ */ + +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) +/*! @} */ + +/*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ +/*! @{ */ + +#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) +#define SNVS_LPZMKR_ZMK_SHIFT (0U) +#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) +/*! @} */ + +/* The count of SNVS_LPZMKR */ +#define SNVS_LPZMKR_COUNT (8U) + +/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @{ */ + +#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) +/*! @} */ + +/* The count of SNVS_LPGPR_ALIAS */ +#define SNVS_LPGPR_ALIAS_COUNT (4U) + +/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @{ */ + +#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_GPR_SHIFT (0U) +#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) +/*! @} */ + +/* The count of SNVS_LPGPR */ +#define SNVS_LPGPR_COUNT (4U) + +/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +/*! @{ */ + +#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) +#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) +#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) + +#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) +#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) +#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) + +#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) +#define SNVS_HPVIDR1_IP_ID_SHIFT (16U) +#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) +/*! @} */ + +/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +/*! @{ */ + +#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) +#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) +#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) + +#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) +#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) +#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) + +#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) +#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) +#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) + +#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) +#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) +#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SNVS_Register_Masks */ + + +/* SNVS - Peripheral instance base addresses */ +/** Peripheral SNVS base address */ +#define SNVS_BASE (0x30370000u) +/** Peripheral SNVS base pointer */ +#define SNVS ((SNVS_Type *)SNVS_BASE) +/** Array initializer of SNVS peripheral base addresses */ +#define SNVS_BASE_ADDRS { SNVS_BASE } +/** Array initializer of SNVS peripheral base pointers */ +#define SNVS_BASE_PTRS { SNVS } +/** Interrupt vectors for the SNVS peripheral type */ +#define SNVS_IRQS { SNVS_IRQn } +#define SNVS_CONSOLIDATED_IRQS { SNVS_Consolidated_IRQn } +#define SNVS_SECURITY_IRQS { SNVS_Security_IRQn } + +/*! + * @} + */ /* end of group SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPBA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer + * @{ + */ + +/** SPBA - Register Layout Typedef */ +typedef struct { + __IO uint32_t PRR[32]; /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */ +} SPBA_Type; + +/* ---------------------------------------------------------------------------- + -- SPBA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Register_Masks SPBA Register Masks + * @{ + */ + +/*! @name PRR - Peripheral Rights Register */ +/*! @{ */ + +#define SPBA_PRR_RARA_MASK (0x1U) +#define SPBA_PRR_RARA_SHIFT (0U) +/*! RARA + * 0b0..Access to peripheral is not allowed. + * 0b1..Access to peripheral is granted. + */ +#define SPBA_PRR_RARA(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARA_SHIFT)) & SPBA_PRR_RARA_MASK) + +#define SPBA_PRR_RARB_MASK (0x2U) +#define SPBA_PRR_RARB_SHIFT (1U) +/*! RARB + * 0b0..Access to peripheral is not allowed. + * 0b1..Access to peripheral is granted. + */ +#define SPBA_PRR_RARB(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARB_SHIFT)) & SPBA_PRR_RARB_MASK) + +#define SPBA_PRR_RARC_MASK (0x4U) +#define SPBA_PRR_RARC_SHIFT (2U) +/*! RARC + * 0b0..Access to peripheral is not allowed. + * 0b1..Access to peripheral is granted. + */ +#define SPBA_PRR_RARC(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARC_SHIFT)) & SPBA_PRR_RARC_MASK) + +#define SPBA_PRR_ROI_MASK (0x30000U) +#define SPBA_PRR_ROI_SHIFT (16U) +/*! ROI + * 0b00..Unowned resource. + * 0b01..The resource is owned by master A port. + * 0b10..The resource is owned by master B port. + * 0b11..The resource is owned by master C port. + */ +#define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_ROI_SHIFT)) & SPBA_PRR_ROI_MASK) + +#define SPBA_PRR_RMO_MASK (0xC0000000U) +#define SPBA_PRR_RMO_SHIFT (30U) +/*! RMO + * 0b00..The resource is unowned. + * 0b01..Reserved. + * 0b10..The resource is owned by another master. + * 0b11..The resource is owned by the requesting master. + */ +#define SPBA_PRR_RMO(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RMO_SHIFT)) & SPBA_PRR_RMO_MASK) +/*! @} */ + +/* The count of SPBA_PRR */ +#define SPBA_PRR_COUNT (32U) + + +/*! + * @} + */ /* end of group SPBA_Register_Masks */ + + +/* SPBA - Peripheral instance base addresses */ +/** Peripheral SPBA1 base address */ +#define SPBA1_BASE (0x308F0000u) +/** Peripheral SPBA1 base pointer */ +#define SPBA1 ((SPBA_Type *)SPBA1_BASE) +/** Peripheral SPBA2 base address */ +#define SPBA2_BASE (0x300F0000u) +/** Peripheral SPBA2 base pointer */ +#define SPBA2 ((SPBA_Type *)SPBA2_BASE) +/** Array initializer of SPBA peripheral base addresses */ +#define SPBA_BASE_ADDRS { 0u, SPBA1_BASE, SPBA2_BASE } +/** Array initializer of SPBA peripheral base pointers */ +#define SPBA_BASE_PTRS { (SPBA_Type *)0u, SPBA1, SPBA2 } + +/*! + * @} + */ /* end of group SPBA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer + * @{ + */ + +/** SPDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ + __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ + __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ + __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ + union { /* offset: 0x10 */ + __O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ + __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ + }; + __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ + __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ + __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ + __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ + __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ + __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ + __O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ + __O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ + __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ + __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ + uint8_t RESERVED_0[8]; + __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ + uint8_t RESERVED_1[8]; + __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ +} SPDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/*! @name SCR - SPDIF Configuration Register */ +/*! @{ */ + +#define SPDIF_SCR_USRC_SEL_MASK (0x3U) +#define SPDIF_SCR_USRC_SEL_SHIFT (0U) +/*! USrc_Sel + * 0b00..No embedded U channel + * 0b01..U channel from SPDIF receive block (CD mode) + * 0b10..Reserved + * 0b11..U channel from on chip transmitter + */ +#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) + +#define SPDIF_SCR_TXSEL_MASK (0x1CU) +#define SPDIF_SCR_TXSEL_SHIFT (2U) +/*! TxSel + * 0b000..Off and output 0 + * 0b001..Feed-through SPDIFIN + * 0b101..Tx Normal operation + */ +#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) + +#define SPDIF_SCR_VALCTRL_MASK (0x20U) +#define SPDIF_SCR_VALCTRL_SHIFT (5U) +/*! ValCtrl + * 0b0..Outgoing Validity always set + * 0b1..Outgoing Validity always clear + */ +#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) + +#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) +#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) +#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) + +#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) +#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) +#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) + +#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) +#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) +/*! TxFIFO_Ctrl + * 0b00..Send out digital zero on SPDIF Tx + * 0b01..Tx Normal operation + * 0b10..Reset to 1 sample remaining + * 0b11..Reserved + */ +#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) + +#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) +#define SPDIF_SCR_SOFT_RESET_SHIFT (12U) +#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) + +#define SPDIF_SCR_LOW_POWER_MASK (0x2000U) +#define SPDIF_SCR_LOW_POWER_SHIFT (13U) +#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) + +#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) +/*! TxFIFOEmpty_Sel + * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs + * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs + * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs + * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs + */ +#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) + +#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) +#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) +/*! TxAutoSync + * 0b0..Tx FIFO auto sync off + * 0b1..Tx FIFO auto sync on + */ +#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) + +#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) +#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) +/*! RxAutoSync + * 0b0..Rx FIFO auto sync off + * 0b1..RxFIFO auto sync on + */ +#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) + +#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) +#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) +/*! RxFIFOFull_Sel + * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs + * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs + * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs + * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO + */ +#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) + +#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) +#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) +/*! RxFIFO_Rst + * 0b0..Normal operation + * 0b1..Reset register to 1 sample remaining + */ +#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) + +#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) +#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) +/*! RxFIFO_Off_On + * 0b0..SPDIF Rx FIFO is on + * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface + */ +#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) + +#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) +#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) +/*! RxFIFO_Ctrl + * 0b0..Normal operation + * 0b1..Always read zero from Rx data register + */ +#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) +/*! @} */ + +/*! @name SRCD - CDText Control Register */ +/*! @{ */ + +#define SPDIF_SRCD_USYNCMODE_MASK (0x2U) +#define SPDIF_SRCD_USYNCMODE_SHIFT (1U) +/*! USyncMode + * 0b0..Non-CD data + * 0b1..CD user channel subcode + */ +#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) +/*! @} */ + +/*! @name SRPC - PhaseConfig Register */ +/*! @{ */ + +#define SPDIF_SRPC_GAINSEL_MASK (0x38U) +#define SPDIF_SRPC_GAINSEL_SHIFT (3U) +/*! GainSel + * 0b000..24*(2**10) + * 0b001..16*(2**10) + * 0b010..12*(2**10) + * 0b011..8*(2**10) + * 0b100..6*(2**10) + * 0b101..4*(2**10) + * 0b110..3*(2**10) + */ +#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) + +#define SPDIF_SRPC_LOCK_MASK (0x40U) +#define SPDIF_SRPC_LOCK_SHIFT (6U) +#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) + +#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) +#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) +/*! ClkSrc_Sel + * 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + * 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + * 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + * 0b0101..REF_CLK_32K (XTALOSC) + * 0b0110..tx_clk (SPDIF0_CLK_ROOT) + * 0b1000..SPDIF_EXT_CLK + */ +#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) +/*! @} */ + +/*! @name SIE - InterruptEn Register */ +/*! @{ */ + +#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) + +#define SPDIF_SIE_TXEM_MASK (0x2U) +#define SPDIF_SIE_TXEM_SHIFT (1U) +#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) + +#define SPDIF_SIE_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIE_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) + +#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) + +#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) + +#define SPDIF_SIE_UQERR_MASK (0x20U) +#define SPDIF_SIE_UQERR_SHIFT (5U) +#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) + +#define SPDIF_SIE_UQSYNC_MASK (0x40U) +#define SPDIF_SIE_UQSYNC_SHIFT (6U) +#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) + +#define SPDIF_SIE_QRXOV_MASK (0x80U) +#define SPDIF_SIE_QRXOV_SHIFT (7U) +#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) + +#define SPDIF_SIE_QRXFUL_MASK (0x100U) +#define SPDIF_SIE_QRXFUL_SHIFT (8U) +#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) + +#define SPDIF_SIE_URXOV_MASK (0x200U) +#define SPDIF_SIE_URXOV_SHIFT (9U) +#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) + +#define SPDIF_SIE_URXFUL_MASK (0x400U) +#define SPDIF_SIE_URXFUL_SHIFT (10U) +#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) + +#define SPDIF_SIE_BITERR_MASK (0x4000U) +#define SPDIF_SIE_BITERR_SHIFT (14U) +#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) + +#define SPDIF_SIE_SYMERR_MASK (0x8000U) +#define SPDIF_SIE_SYMERR_SHIFT (15U) +#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) + +#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIE_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) + +#define SPDIF_SIE_CNEW_MASK (0x20000U) +#define SPDIF_SIE_CNEW_SHIFT (17U) +#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) + +#define SPDIF_SIE_TXRESYN_MASK (0x40000U) +#define SPDIF_SIE_TXRESYN_SHIFT (18U) +#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) + +#define SPDIF_SIE_TXUNOV_MASK (0x80000U) +#define SPDIF_SIE_TXUNOV_SHIFT (19U) +#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) + +#define SPDIF_SIE_LOCK_MASK (0x100000U) +#define SPDIF_SIE_LOCK_SHIFT (20U) +#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) +/*! @} */ + +/*! @name SIC - InterruptClear Register */ +/*! @{ */ + +#define SPDIF_SIC_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIC_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) + +#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) + +#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) + +#define SPDIF_SIC_UQERR_MASK (0x20U) +#define SPDIF_SIC_UQERR_SHIFT (5U) +#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) + +#define SPDIF_SIC_UQSYNC_MASK (0x40U) +#define SPDIF_SIC_UQSYNC_SHIFT (6U) +#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) + +#define SPDIF_SIC_QRXOV_MASK (0x80U) +#define SPDIF_SIC_QRXOV_SHIFT (7U) +#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) + +#define SPDIF_SIC_URXOV_MASK (0x200U) +#define SPDIF_SIC_URXOV_SHIFT (9U) +#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) + +#define SPDIF_SIC_BITERR_MASK (0x4000U) +#define SPDIF_SIC_BITERR_SHIFT (14U) +#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) + +#define SPDIF_SIC_SYMERR_MASK (0x8000U) +#define SPDIF_SIC_SYMERR_SHIFT (15U) +#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) + +#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIC_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) + +#define SPDIF_SIC_CNEW_MASK (0x20000U) +#define SPDIF_SIC_CNEW_SHIFT (17U) +#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) + +#define SPDIF_SIC_TXRESYN_MASK (0x40000U) +#define SPDIF_SIC_TXRESYN_SHIFT (18U) +#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) + +#define SPDIF_SIC_TXUNOV_MASK (0x80000U) +#define SPDIF_SIC_TXUNOV_SHIFT (19U) +#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) + +#define SPDIF_SIC_LOCK_MASK (0x100000U) +#define SPDIF_SIC_LOCK_SHIFT (20U) +#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) +/*! @} */ + +/*! @name SIS - InterruptStat Register */ +/*! @{ */ + +#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) + +#define SPDIF_SIS_TXEM_MASK (0x2U) +#define SPDIF_SIS_TXEM_SHIFT (1U) +#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) + +#define SPDIF_SIS_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIS_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) + +#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) + +#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) + +#define SPDIF_SIS_UQERR_MASK (0x20U) +#define SPDIF_SIS_UQERR_SHIFT (5U) +#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) + +#define SPDIF_SIS_UQSYNC_MASK (0x40U) +#define SPDIF_SIS_UQSYNC_SHIFT (6U) +#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) + +#define SPDIF_SIS_QRXOV_MASK (0x80U) +#define SPDIF_SIS_QRXOV_SHIFT (7U) +#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) + +#define SPDIF_SIS_QRXFUL_MASK (0x100U) +#define SPDIF_SIS_QRXFUL_SHIFT (8U) +#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) + +#define SPDIF_SIS_URXOV_MASK (0x200U) +#define SPDIF_SIS_URXOV_SHIFT (9U) +#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) + +#define SPDIF_SIS_URXFUL_MASK (0x400U) +#define SPDIF_SIS_URXFUL_SHIFT (10U) +#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) + +#define SPDIF_SIS_BITERR_MASK (0x4000U) +#define SPDIF_SIS_BITERR_SHIFT (14U) +#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) + +#define SPDIF_SIS_SYMERR_MASK (0x8000U) +#define SPDIF_SIS_SYMERR_SHIFT (15U) +#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) + +#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIS_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) + +#define SPDIF_SIS_CNEW_MASK (0x20000U) +#define SPDIF_SIS_CNEW_SHIFT (17U) +#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) + +#define SPDIF_SIS_TXRESYN_MASK (0x40000U) +#define SPDIF_SIS_TXRESYN_SHIFT (18U) +#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) + +#define SPDIF_SIS_TXUNOV_MASK (0x80000U) +#define SPDIF_SIS_TXUNOV_SHIFT (19U) +#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) + +#define SPDIF_SIS_LOCK_MASK (0x100000U) +#define SPDIF_SIS_LOCK_SHIFT (20U) +#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) +/*! @} */ + +/*! @name SRL - SPDIFRxLeft Register */ +/*! @{ */ + +#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_SRL_RXDATALEFT_SHIFT (0U) +#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) +/*! @} */ + +/*! @name SRR - SPDIFRxRight Register */ +/*! @{ */ + +#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) +#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) +/*! @} */ + +/*! @name SRCSH - SPDIFRxCChannel_h Register */ +/*! @{ */ + +#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) +#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) +#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) +/*! @} */ + +/*! @name SRCSL - SPDIFRxCChannel_l Register */ +/*! @{ */ + +#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) +#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) +#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) +/*! @} */ + +/*! @name SRU - UchannelRx Register */ +/*! @{ */ + +#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) +#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) +/*! @} */ + +/*! @name SRQ - QchannelRx Register */ +/*! @{ */ + +#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) +#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) +/*! @} */ + +/*! @name STL - SPDIFTxLeft Register */ +/*! @{ */ + +#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_STL_TXDATALEFT_SHIFT (0U) +#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) +/*! @} */ + +/*! @name STR - SPDIFTxRight Register */ +/*! @{ */ + +#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_STR_TXDATARIGHT_SHIFT (0U) +#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) +/*! @} */ + +/*! @name STCSCH - SPDIFTxCChannelCons_h Register */ +/*! @{ */ + +#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) +#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) +#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) +/*! @} */ + +/*! @name STCSCL - SPDIFTxCChannelCons_l Register */ +/*! @{ */ + +#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) +#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) +#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) +/*! @} */ + +/*! @name SRFM - FreqMeas Register */ +/*! @{ */ + +#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) +#define SPDIF_SRFM_FREQMEAS_SHIFT (0U) +#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) +/*! @} */ + +/*! @name STC - SPDIFTxClk Register */ +/*! @{ */ + +#define SPDIF_STC_TXCLK_DF_MASK (0x7FU) +#define SPDIF_STC_TXCLK_DF_SHIFT (0U) +/*! TxClk_DF + * 0b0000000..divider factor is 1 + * 0b0000001..divider factor is 2 + * 0b1111111..divider factor is 128 + */ +#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) + +#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) +#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) +/*! tx_all_clk_en + * 0b0..disable transfer clock. + * 0b1..enable transfer clock. + */ +#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) + +#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) +#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) +/*! TxClk_Source + * 0b000..REF_CLK_32K input (XTALOSC 32 kHz clock) + * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + * 0b011..SPDIF_EXT_CLK, from pads + * 0b101..ipg_clk input (frequency divided) + */ +#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) + +#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) +#define SPDIF_STC_SYSCLK_DF_SHIFT (11U) +/*! SYSCLK_DF + * 0b000000000..no clock signal + * 0b000000001..divider factor is 2 + * 0b111111111..divider factor is 512 + */ +#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPDIF_Register_Masks */ + + +/* SPDIF - Peripheral instance base addresses */ +/** Peripheral SPDIF1 base address */ +#define SPDIF1_BASE (0x30810000u) +/** Peripheral SPDIF1 base pointer */ +#define SPDIF1 ((SPDIF_Type *)SPDIF1_BASE) +/** Peripheral SPDIF2 base address */ +#define SPDIF2_BASE (0x308A0000u) +/** Peripheral SPDIF2 base pointer */ +#define SPDIF2 ((SPDIF_Type *)SPDIF2_BASE) +/** Array initializer of SPDIF peripheral base addresses */ +#define SPDIF_BASE_ADDRS { 0u, SPDIF1_BASE, SPDIF2_BASE } +/** Array initializer of SPDIF peripheral base pointers */ +#define SPDIF_BASE_PTRS { (SPDIF_Type *)0u, SPDIF1, SPDIF2 } +/** Interrupt vectors for the SPDIF peripheral type */ +#define SPDIF_IRQS { NotAvail_IRQn, SPDIF1_IRQn, SPDIF2_IRQn } + +/*! + * @} + */ /* end of group SPDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer + * @{ + */ + +/** SRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SRC Reset Control Register, offset: 0x0 */ + __IO uint32_t A53RCR0; /**< A53 Reset Control Register, offset: 0x4 */ + __IO uint32_t A53RCR1; /**< A53 Reset Control Register, offset: 0x8 */ + __IO uint32_t M4RCR; /**< M4 Reset Control Register, offset: 0xC */ + uint8_t RESERVED_0[16]; + __IO uint32_t USBOPHY1_RCR; /**< USB OTG PHY1 Reset Control Register, offset: 0x20 */ + __IO uint32_t USBOPHY2_RCR; /**< USB OTG PHY2 Reset Control Register, offset: 0x24 */ + __IO uint32_t MIPIPHY_RCR; /**< MIPI PHY Reset Control Register, offset: 0x28 */ + __IO uint32_t PCIEPHY_RCR; /**< PCIE PHY Reset Control Register, offset: 0x2C */ + __IO uint32_t HDMI_RCR; /**< HDMI Reset Control Register, offset: 0x30 */ + __IO uint32_t DISP_RCR; /**< DISP Reset Control Register, offset: 0x34 */ + uint8_t RESERVED_1[8]; + __IO uint32_t GPU_RCR; /**< GPU Reset Control Register, offset: 0x40 */ + __IO uint32_t VPU_RCR; /**< VPU Reset Control Register, offset: 0x44 */ + __IO uint32_t PCIE2_RCR; /**< PCIE2 Reset Control Register, offset: 0x48 */ + __IO uint32_t MIPIPHY1_RCR; /**< MIPI CSI1 PHY Reset Control Register, offset: 0x4C */ + __IO uint32_t MIPIPHY2_RCR; /**< MIPI CSI2 PHY Reset Control Register, offset: 0x50 */ + uint8_t RESERVED_2[4]; + __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x58 */ + __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x5C */ + uint8_t RESERVED_3[8]; + __I uint32_t SISR; /**< SRC Interrupt Status Register, offset: 0x68 */ + __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ + __IO uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x70 */ + __IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x74, array step: 0x4 */ + uint8_t RESERVED_4[3940]; + __IO uint32_t DDRC_RCR; /**< SRC DDR Controller Reset Control Register, offset: 0x1000 */ + __IO uint32_t DDRC2_RCR; /**< SRC DDRC2 Controller Reset Control Register, offset: 0x1004 */ +} SRC_Type; + +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/*! @name SCR - SRC Reset Control Register */ +/*! @{ */ + +#define SRC_SCR_MASK_TEMPSENSE_RESET_MASK (0xF0U) +#define SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT (4U) +/*! MASK_TEMPSENSE_RESET + * 0b0101..tempsense_reset is masked + * 0b1010..tempsense_reset is not masked + */ +#define SRC_SCR_MASK_TEMPSENSE_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT)) & SRC_SCR_MASK_TEMPSENSE_RESET_MASK) + +#define SRC_SCR_DOMAIN0_MASK (0x1000000U) +#define SRC_SCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_SCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN0_SHIFT)) & SRC_SCR_DOMAIN0_MASK) + +#define SRC_SCR_DOMAIN1_MASK (0x2000000U) +#define SRC_SCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_SCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN1_SHIFT)) & SRC_SCR_DOMAIN1_MASK) + +#define SRC_SCR_DOMAIN2_MASK (0x4000000U) +#define SRC_SCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_SCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN2_SHIFT)) & SRC_SCR_DOMAIN2_MASK) + +#define SRC_SCR_DOMAIN3_MASK (0x8000000U) +#define SRC_SCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_SCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN3_SHIFT)) & SRC_SCR_DOMAIN3_MASK) + +#define SRC_SCR_LOCK_MASK (0x40000000U) +#define SRC_SCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_SCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCK_SHIFT)) & SRC_SCR_LOCK_MASK) + +#define SRC_SCR_DOM_EN_MASK (0x80000000U) +#define SRC_SCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_SCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOM_EN_SHIFT)) & SRC_SCR_DOM_EN_MASK) +/*! @} */ + +/*! @name A53RCR0 - A53 Reset Control Register */ +/*! @{ */ + +#define SRC_A53RCR0_A53_CORE_POR_RESET0_MASK (0x1U) +#define SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT (0U) +/*! A53_CORE_POR_RESET0 + * 0b0..do not assert core0 reset + * 0b1..assert core0 reset + */ +#define SRC_A53RCR0_A53_CORE_POR_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET0_MASK) + +#define SRC_A53RCR0_A53_CORE_POR_RESET1_MASK (0x2U) +#define SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT (1U) +/*! A53_CORE_POR_RESET1 + * 0b0..do not assert core1 reset + * 0b1..assert core1 reset + */ +#define SRC_A53RCR0_A53_CORE_POR_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET1_MASK) + +#define SRC_A53RCR0_A53_CORE_POR_RESET2_MASK (0x4U) +#define SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT (2U) +/*! A53_CORE_POR_RESET2 + * 0b0..do not assert core2 reset + * 0b1..assert core2 reset + */ +#define SRC_A53RCR0_A53_CORE_POR_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET2_MASK) + +#define SRC_A53RCR0_A53_CORE_POR_RESET3_MASK (0x8U) +#define SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT (3U) +/*! A53_CORE_POR_RESET3 + * 0b0..do not assert core3 reset + * 0b1..assert core3 reset + */ +#define SRC_A53RCR0_A53_CORE_POR_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET3_MASK) + +#define SRC_A53RCR0_A53_CORE_RESET0_MASK (0x10U) +#define SRC_A53RCR0_A53_CORE_RESET0_SHIFT (4U) +/*! A53_CORE_RESET0 + * 0b0..do not assert core0 reset + * 0b1..assert core0 reset + */ +#define SRC_A53RCR0_A53_CORE_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET0_MASK) + +#define SRC_A53RCR0_A53_CORE_RESET1_MASK (0x20U) +#define SRC_A53RCR0_A53_CORE_RESET1_SHIFT (5U) +/*! A53_CORE_RESET1 + * 0b0..do not assert core1 reset + * 0b1..assert core1 reset + */ +#define SRC_A53RCR0_A53_CORE_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET1_MASK) + +#define SRC_A53RCR0_A53_CORE_RESET2_MASK (0x40U) +#define SRC_A53RCR0_A53_CORE_RESET2_SHIFT (6U) +/*! A53_CORE_RESET2 + * 0b0..do not assert core2 reset + * 0b1..assert core2 reset + */ +#define SRC_A53RCR0_A53_CORE_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET2_MASK) + +#define SRC_A53RCR0_A53_CORE_RESET3_MASK (0x80U) +#define SRC_A53RCR0_A53_CORE_RESET3_SHIFT (7U) +/*! A53_CORE_RESET3 + * 0b0..do not assert core3 reset + * 0b1..assert core3 reset + */ +#define SRC_A53RCR0_A53_CORE_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET3_MASK) + +#define SRC_A53RCR0_A53_DBG_RESET0_MASK (0x100U) +#define SRC_A53RCR0_A53_DBG_RESET0_SHIFT (8U) +/*! A53_DBG_RESET0 + * 0b0..do not assert core0 debug reset + * 0b1..assert core0 debug reset + */ +#define SRC_A53RCR0_A53_DBG_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET0_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET0_MASK) + +#define SRC_A53RCR0_A53_DBG_RESET1_MASK (0x200U) +#define SRC_A53RCR0_A53_DBG_RESET1_SHIFT (9U) +/*! A53_DBG_RESET1 + * 0b0..do not assert core1 debug reset + * 0b1..assert core1 debug reset + */ +#define SRC_A53RCR0_A53_DBG_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET1_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET1_MASK) + +#define SRC_A53RCR0_A53_DBG_RESET2_MASK (0x400U) +#define SRC_A53RCR0_A53_DBG_RESET2_SHIFT (10U) +/*! A53_DBG_RESET2 + * 0b0..do not assert core2 debug reset + * 0b1..assert core2 debug reset + */ +#define SRC_A53RCR0_A53_DBG_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET2_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET2_MASK) + +#define SRC_A53RCR0_A53_DBG_RESET3_MASK (0x800U) +#define SRC_A53RCR0_A53_DBG_RESET3_SHIFT (11U) +/*! A53_DBG_RESET3 + * 0b0..do not assert core3 debug reset + * 0b1..assert core3 debug reset + */ +#define SRC_A53RCR0_A53_DBG_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET3_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET3_MASK) + +#define SRC_A53RCR0_A53_ETM_RESET0_MASK (0x1000U) +#define SRC_A53RCR0_A53_ETM_RESET0_SHIFT (12U) +/*! A53_ETM_RESET0 + * 0b0..do not assert core0 ETM reset + * 0b1..assert core0 ETM reset + */ +#define SRC_A53RCR0_A53_ETM_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET0_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET0_MASK) + +#define SRC_A53RCR0_A53_ETM_RESET1_MASK (0x2000U) +#define SRC_A53RCR0_A53_ETM_RESET1_SHIFT (13U) +/*! A53_ETM_RESET1 + * 0b0..do not assert core1 ETM reset + * 0b1..assert core1 ETM reset + */ +#define SRC_A53RCR0_A53_ETM_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET1_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET1_MASK) + +#define SRC_A53RCR0_A53_ETM_RESET2_MASK (0x4000U) +#define SRC_A53RCR0_A53_ETM_RESET2_SHIFT (14U) +/*! A53_ETM_RESET2 + * 0b0..do not assert core2 ETM reset + * 0b1..assert core2 ETM reset + */ +#define SRC_A53RCR0_A53_ETM_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET2_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET2_MASK) + +#define SRC_A53RCR0_A53_ETM_RESET3_MASK (0x8000U) +#define SRC_A53RCR0_A53_ETM_RESET3_SHIFT (15U) +/*! A53_ETM_RESET3 + * 0b0..do not assert core3 ETM reset + * 0b1..assert core3 ETM reset + */ +#define SRC_A53RCR0_A53_ETM_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET3_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET3_MASK) + +#define SRC_A53RCR0_MASK_WDOG1_RST_MASK (0xF0000U) +#define SRC_A53RCR0_MASK_WDOG1_RST_SHIFT (16U) +/*! MASK_WDOG1_RST + * 0b0101..wdog1_rst_b is masked + * 0b1010..wdog1_rst_b is not masked + */ +#define SRC_A53RCR0_MASK_WDOG1_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_MASK_WDOG1_RST_SHIFT)) & SRC_A53RCR0_MASK_WDOG1_RST_MASK) + +#define SRC_A53RCR0_A53_SOC_DBG_RESET_MASK (0x100000U) +#define SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT (20U) +/*! A53_SOC_DBG_RESET + * 0b0..do not assert system level debug reset + * 0b1..assert system level debug reset + */ +#define SRC_A53RCR0_A53_SOC_DBG_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT)) & SRC_A53RCR0_A53_SOC_DBG_RESET_MASK) + +#define SRC_A53RCR0_A53_L2RESET_MASK (0x200000U) +#define SRC_A53RCR0_A53_L2RESET_SHIFT (21U) +/*! A53_L2RESET + * 0b0..do not assert SCU reset + * 0b1..assert SCU reset + */ +#define SRC_A53RCR0_A53_L2RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_L2RESET_SHIFT)) & SRC_A53RCR0_A53_L2RESET_MASK) + +#define SRC_A53RCR0_DOMAIN0_MASK (0x1000000U) +#define SRC_A53RCR0_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_A53RCR0_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN0_SHIFT)) & SRC_A53RCR0_DOMAIN0_MASK) + +#define SRC_A53RCR0_DOMAIN1_MASK (0x2000000U) +#define SRC_A53RCR0_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_A53RCR0_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN1_SHIFT)) & SRC_A53RCR0_DOMAIN1_MASK) + +#define SRC_A53RCR0_DOMAIN2_MASK (0x4000000U) +#define SRC_A53RCR0_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_A53RCR0_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN2_SHIFT)) & SRC_A53RCR0_DOMAIN2_MASK) + +#define SRC_A53RCR0_DOMAIN3_MASK (0x8000000U) +#define SRC_A53RCR0_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_A53RCR0_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN3_SHIFT)) & SRC_A53RCR0_DOMAIN3_MASK) + +#define SRC_A53RCR0_LOCK_MASK (0x40000000U) +#define SRC_A53RCR0_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_A53RCR0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_LOCK_SHIFT)) & SRC_A53RCR0_LOCK_MASK) + +#define SRC_A53RCR0_DOM_EN_MASK (0x80000000U) +#define SRC_A53RCR0_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_A53RCR0_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOM_EN_SHIFT)) & SRC_A53RCR0_DOM_EN_MASK) +/*! @} */ + +/*! @name A53RCR1 - A53 Reset Control Register */ +/*! @{ */ + +#define SRC_A53RCR1_A53_CORE0_ENABLE_MASK (0x1U) +#define SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT (0U) +#define SRC_A53RCR1_A53_CORE0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE0_ENABLE_MASK) + +#define SRC_A53RCR1_A53_CORE1_ENABLE_MASK (0x2U) +#define SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT (1U) +/*! A53_CORE1_ENABLE + * 0b0..core1 is disabled + * 0b1..core1 is enabled + */ +#define SRC_A53RCR1_A53_CORE1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE1_ENABLE_MASK) + +#define SRC_A53RCR1_A53_CORE2_ENABLE_MASK (0x4U) +#define SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT (2U) +/*! A53_CORE2_ENABLE + * 0b0..core2 is disabled + * 0b1..core2 is enabled + */ +#define SRC_A53RCR1_A53_CORE2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE2_ENABLE_MASK) + +#define SRC_A53RCR1_A53_CORE3_ENABLE_MASK (0x8U) +#define SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT (3U) +/*! A53_CORE3_ENABLE + * 0b0..core3 is disabled + * 0b1..core3 is enabled + */ +#define SRC_A53RCR1_A53_CORE3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE3_ENABLE_MASK) + +#define SRC_A53RCR1_A53_RST_SLOW_MASK (0x70U) +#define SRC_A53RCR1_A53_RST_SLOW_SHIFT (4U) +#define SRC_A53RCR1_A53_RST_SLOW(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_RST_SLOW_SHIFT)) & SRC_A53RCR1_A53_RST_SLOW_MASK) + +#define SRC_A53RCR1_DOMAIN0_MASK (0x1000000U) +#define SRC_A53RCR1_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_A53RCR1_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN0_SHIFT)) & SRC_A53RCR1_DOMAIN0_MASK) + +#define SRC_A53RCR1_DOMAIN1_MASK (0x2000000U) +#define SRC_A53RCR1_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_A53RCR1_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN1_SHIFT)) & SRC_A53RCR1_DOMAIN1_MASK) + +#define SRC_A53RCR1_DOMAIN2_MASK (0x4000000U) +#define SRC_A53RCR1_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_A53RCR1_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN2_SHIFT)) & SRC_A53RCR1_DOMAIN2_MASK) + +#define SRC_A53RCR1_DOMAIN3_MASK (0x8000000U) +#define SRC_A53RCR1_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_A53RCR1_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN3_SHIFT)) & SRC_A53RCR1_DOMAIN3_MASK) + +#define SRC_A53RCR1_LOCK_MASK (0x40000000U) +#define SRC_A53RCR1_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_A53RCR1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_LOCK_SHIFT)) & SRC_A53RCR1_LOCK_MASK) + +#define SRC_A53RCR1_DOM_EN_MASK (0x80000000U) +#define SRC_A53RCR1_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_A53RCR1_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOM_EN_SHIFT)) & SRC_A53RCR1_DOM_EN_MASK) +/*! @} */ + +/*! @name M4RCR - M4 Reset Control Register */ +/*! @{ */ + +#define SRC_M4RCR_SW_M4C_NON_SCLR_RST_MASK (0x1U) +#define SRC_M4RCR_SW_M4C_NON_SCLR_RST_SHIFT (0U) +/*! SW_M4C_NON_SCLR_RST + * 0b0..do not assert M4 core reset + * 0b1..assert M4 core reset + */ +#define SRC_M4RCR_SW_M4C_NON_SCLR_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_SW_M4C_NON_SCLR_RST_SHIFT)) & SRC_M4RCR_SW_M4C_NON_SCLR_RST_MASK) + +#define SRC_M4RCR_SW_M4C_RST_MASK (0x2U) +#define SRC_M4RCR_SW_M4C_RST_SHIFT (1U) +/*! SW_M4C_RST + * 0b0..do not assert M4 core reset + * 0b1..assert M4 core reset + */ +#define SRC_M4RCR_SW_M4C_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_SW_M4C_RST_SHIFT)) & SRC_M4RCR_SW_M4C_RST_MASK) + +#define SRC_M4RCR_SW_M4P_RST_MASK (0x4U) +#define SRC_M4RCR_SW_M4P_RST_SHIFT (2U) +/*! SW_M4P_RST + * 0b0..do not assert M4 platform reset + * 0b1..assert M4 platform reset + */ +#define SRC_M4RCR_SW_M4P_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_SW_M4P_RST_SHIFT)) & SRC_M4RCR_SW_M4P_RST_MASK) + +#define SRC_M4RCR_ENABLE_M4_MASK (0x8U) +#define SRC_M4RCR_ENABLE_M4_SHIFT (3U) +/*! ENABLE_M4 + * 0b0..M4 is disabled + * 0b1..M4 is enabled + */ +#define SRC_M4RCR_ENABLE_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_ENABLE_M4_SHIFT)) & SRC_M4RCR_ENABLE_M4_MASK) + +#define SRC_M4RCR_MASK_WDOG3_RST_MASK (0xF0U) +#define SRC_M4RCR_MASK_WDOG3_RST_SHIFT (4U) +/*! MASK_WDOG3_RST + * 0b0101..wdog3_rst_b is masked + * 0b1010..wdog3_rst_b is not masked + */ +#define SRC_M4RCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_MASK_WDOG3_RST_SHIFT)) & SRC_M4RCR_MASK_WDOG3_RST_MASK) + +#define SRC_M4RCR_WDOG3_RST_OPTION_M4_MASK (0x100U) +#define SRC_M4RCR_WDOG3_RST_OPTION_M4_SHIFT (8U) +/*! WDOG3_RST_OPTION_M4 + * 0b0..wdgo3_rst_b Reset M4 core only + * 0b1..Reset both M4 core and platform + */ +#define SRC_M4RCR_WDOG3_RST_OPTION_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_WDOG3_RST_OPTION_M4_SHIFT)) & SRC_M4RCR_WDOG3_RST_OPTION_M4_MASK) + +#define SRC_M4RCR_WDOG3_RST_OPTION_MASK (0x200U) +#define SRC_M4RCR_WDOG3_RST_OPTION_SHIFT (9U) +/*! WDOG3_RST_OPTION + * 0b0..Wdog3_rst_b asserts M4 reset + * 0b1..Wdog3_rst_b asserts global reset + */ +#define SRC_M4RCR_WDOG3_RST_OPTION(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_WDOG3_RST_OPTION_SHIFT)) & SRC_M4RCR_WDOG3_RST_OPTION_MASK) + +#define SRC_M4RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_M4RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_M4RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOMAIN0_SHIFT)) & SRC_M4RCR_DOMAIN0_MASK) + +#define SRC_M4RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_M4RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_M4RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOMAIN1_SHIFT)) & SRC_M4RCR_DOMAIN1_MASK) + +#define SRC_M4RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_M4RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_M4RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOMAIN2_SHIFT)) & SRC_M4RCR_DOMAIN2_MASK) + +#define SRC_M4RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_M4RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_M4RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOMAIN3_SHIFT)) & SRC_M4RCR_DOMAIN3_MASK) + +#define SRC_M4RCR_LOCK_MASK (0x40000000U) +#define SRC_M4RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_M4RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_LOCK_SHIFT)) & SRC_M4RCR_LOCK_MASK) + +#define SRC_M4RCR_DOM_EN_MASK (0x80000000U) +#define SRC_M4RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_M4RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOM_EN_SHIFT)) & SRC_M4RCR_DOM_EN_MASK) +/*! @} */ + +/*! @name USBOPHY1_RCR - USB OTG PHY1 Reset Control Register */ +/*! @{ */ + +#define SRC_USBOPHY1_RCR_OTG1_PHY_RESET_MASK (0x1U) +#define SRC_USBOPHY1_RCR_OTG1_PHY_RESET_SHIFT (0U) +/*! OTG1_PHY_RESET + * 0b0..Don't reset USB OTG1 PHY + * 0b1..Reset USB OTG1 PHY + */ +#define SRC_USBOPHY1_RCR_OTG1_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_OTG1_PHY_RESET_SHIFT)) & SRC_USBOPHY1_RCR_OTG1_PHY_RESET_MASK) + +#define SRC_USBOPHY1_RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_USBOPHY1_RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_USBOPHY1_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN0_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN0_MASK) + +#define SRC_USBOPHY1_RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_USBOPHY1_RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_USBOPHY1_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN1_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN1_MASK) + +#define SRC_USBOPHY1_RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_USBOPHY1_RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_USBOPHY1_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN2_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN2_MASK) + +#define SRC_USBOPHY1_RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_USBOPHY1_RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_USBOPHY1_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN3_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN3_MASK) + +#define SRC_USBOPHY1_RCR_LOCK_MASK (0x40000000U) +#define SRC_USBOPHY1_RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_USBOPHY1_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_LOCK_SHIFT)) & SRC_USBOPHY1_RCR_LOCK_MASK) + +#define SRC_USBOPHY1_RCR_DOM_EN_MASK (0x80000000U) +#define SRC_USBOPHY1_RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_USBOPHY1_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOM_EN_SHIFT)) & SRC_USBOPHY1_RCR_DOM_EN_MASK) +/*! @} */ + +/*! @name USBOPHY2_RCR - USB OTG PHY2 Reset Control Register */ +/*! @{ */ + +#define SRC_USBOPHY2_RCR_OTG2_PHY_RESET_MASK (0x1U) +#define SRC_USBOPHY2_RCR_OTG2_PHY_RESET_SHIFT (0U) +/*! OTG2_PHY_RESET + * 0b0..Don't reset USB OTG2 PHY + * 0b1..Reset USB OTG2 PHY + */ +#define SRC_USBOPHY2_RCR_OTG2_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_OTG2_PHY_RESET_SHIFT)) & SRC_USBOPHY2_RCR_OTG2_PHY_RESET_MASK) + +#define SRC_USBOPHY2_RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_USBOPHY2_RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_USBOPHY2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOMAIN0_SHIFT)) & SRC_USBOPHY2_RCR_DOMAIN0_MASK) + +#define SRC_USBOPHY2_RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_USBOPHY2_RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_USBOPHY2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOMAIN1_SHIFT)) & SRC_USBOPHY2_RCR_DOMAIN1_MASK) + +#define SRC_USBOPHY2_RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_USBOPHY2_RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_USBOPHY2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOMAIN2_SHIFT)) & SRC_USBOPHY2_RCR_DOMAIN2_MASK) + +#define SRC_USBOPHY2_RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_USBOPHY2_RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_USBOPHY2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOMAIN3_SHIFT)) & SRC_USBOPHY2_RCR_DOMAIN3_MASK) + +#define SRC_USBOPHY2_RCR_LOCK_MASK (0x40000000U) +#define SRC_USBOPHY2_RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_USBOPHY2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_LOCK_SHIFT)) & SRC_USBOPHY2_RCR_LOCK_MASK) + +#define SRC_USBOPHY2_RCR_DOM_EN_MASK (0x80000000U) +#define SRC_USBOPHY2_RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_USBOPHY2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOM_EN_SHIFT)) & SRC_USBOPHY2_RCR_DOM_EN_MASK) +/*! @} */ + +/*! @name MIPIPHY_RCR - MIPI PHY Reset Control Register */ +/*! @{ */ + +#define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N_MASK (0x2U) +#define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N_SHIFT (1U) +/*! MIPI_DSI_RESET_BYTE_N + * 0b0..Reset + * 0b1..Don't reset + */ +#define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N_MASK) + +#define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N_MASK (0x4U) +#define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N_SHIFT (2U) +/*! MIPI_DSI_RESET_N + * 0b0..Reset + * 0b1..Don't reset + */ +#define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N_MASK) + +#define SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N_MASK (0x8U) +#define SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N_SHIFT (3U) +/*! MIPI_DIS_DPI_RESET_N + * 0b0..Reset + * 0b1..Don't reset + */ +#define SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N_MASK) + +#define SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N_MASK (0x10U) +#define SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N_SHIFT (4U) +/*! MIPI_DIS_ESC_RESET_N + * 0b0..Reset + * 0b1..Don't reset + */ +#define SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N_MASK) + +#define SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N_MASK (0x20U) +#define SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N_SHIFT (5U) +/*! MIPI_DIS_PCLK_RESET_N + * 0b0..Reset + * 0b1..Don't reset + */ +#define SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N_MASK) + +#define SRC_MIPIPHY_RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_MIPIPHY_RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_MIPIPHY_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN0_MASK) + +#define SRC_MIPIPHY_RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_MIPIPHY_RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_MIPIPHY_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN1_MASK) + +#define SRC_MIPIPHY_RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_MIPIPHY_RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_MIPIPHY_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN2_MASK) + +#define SRC_MIPIPHY_RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_MIPIPHY_RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_MIPIPHY_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN3_MASK) + +#define SRC_MIPIPHY_RCR_LOCK_MASK (0x40000000U) +#define SRC_MIPIPHY_RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_MIPIPHY_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_LOCK_SHIFT)) & SRC_MIPIPHY_RCR_LOCK_MASK) + +#define SRC_MIPIPHY_RCR_DOM_EN_MASK (0x80000000U) +#define SRC_MIPIPHY_RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_MIPIPHY_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY_RCR_DOM_EN_MASK) +/*! @} */ + +/*! @name PCIEPHY_RCR - PCIE PHY Reset Control Register */ +/*! @{ */ + +#define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N_MASK (0x1U) +#define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N_SHIFT (0U) +#define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N_MASK) + +#define SRC_PCIEPHY_RCR_PCIEPHY_G_RST_MASK (0x2U) +#define SRC_PCIEPHY_RCR_PCIEPHY_G_RST_SHIFT (1U) +#define SRC_PCIEPHY_RCR_PCIEPHY_G_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIEPHY_G_RST_SHIFT)) & SRC_PCIEPHY_RCR_PCIEPHY_G_RST_MASK) + +#define SRC_PCIEPHY_RCR_PCIEPHY_BTN_MASK (0x4U) +#define SRC_PCIEPHY_RCR_PCIEPHY_BTN_SHIFT (2U) +#define SRC_PCIEPHY_RCR_PCIEPHY_BTN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIEPHY_BTN_SHIFT)) & SRC_PCIEPHY_RCR_PCIEPHY_BTN_MASK) + +#define SRC_PCIEPHY_RCR_PCIEPHY_PERST_MASK (0x8U) +#define SRC_PCIEPHY_RCR_PCIEPHY_PERST_SHIFT (3U) +#define SRC_PCIEPHY_RCR_PCIEPHY_PERST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIEPHY_PERST_SHIFT)) & SRC_PCIEPHY_RCR_PCIEPHY_PERST_MASK) + +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK (0x10U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT (4U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK) + +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_MASK (0x20U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_SHIFT (5U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_MASK) + +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_MASK (0x40U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_SHIFT (6U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_MASK) + +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_MASK (0x80U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_SHIFT (7U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_MASK) + +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_MASK (0x100U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_SHIFT (8U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_MASK) + +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_MASK (0x200U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_SHIFT (9U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_MASK) + +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_MASK (0x400U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_SHIFT (10U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_MASK) + +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_MASK (0x800U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT (11U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_MASK) + +#define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_MASK (0x1000U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT (12U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_MASK) + +#define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_MASK (0x4000U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_SHIFT (14U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_MASK) + +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK (0x8000U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT (15U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK) + +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK (0x10000U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT (16U) +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK) + +#define SRC_PCIEPHY_RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_PCIEPHY_RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_PCIEPHY_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN0_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN0_MASK) + +#define SRC_PCIEPHY_RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_PCIEPHY_RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_PCIEPHY_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN1_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN1_MASK) + +#define SRC_PCIEPHY_RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_PCIEPHY_RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_PCIEPHY_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN2_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN2_MASK) + +#define SRC_PCIEPHY_RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_PCIEPHY_RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_PCIEPHY_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN3_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN3_MASK) + +#define SRC_PCIEPHY_RCR_LOCK_MASK (0x40000000U) +#define SRC_PCIEPHY_RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_PCIEPHY_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_LOCK_SHIFT)) & SRC_PCIEPHY_RCR_LOCK_MASK) + +#define SRC_PCIEPHY_RCR_DOM_EN_MASK (0x80000000U) +#define SRC_PCIEPHY_RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_PCIEPHY_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOM_EN_SHIFT)) & SRC_PCIEPHY_RCR_DOM_EN_MASK) +/*! @} */ + +/*! @name HDMI_RCR - HDMI Reset Control Register */ +/*! @{ */ + +#define SRC_HDMI_RCR_HDMI_PHY_APB_RESET_MASK (0x1U) +#define SRC_HDMI_RCR_HDMI_PHY_APB_RESET_SHIFT (0U) +#define SRC_HDMI_RCR_HDMI_PHY_APB_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_HDMI_PHY_APB_RESET_SHIFT)) & SRC_HDMI_RCR_HDMI_PHY_APB_RESET_MASK) + +#define SRC_HDMI_RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_HDMI_RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_HDMI_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN0_SHIFT)) & SRC_HDMI_RCR_DOMAIN0_MASK) + +#define SRC_HDMI_RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_HDMI_RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_HDMI_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN1_SHIFT)) & SRC_HDMI_RCR_DOMAIN1_MASK) + +#define SRC_HDMI_RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_HDMI_RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_HDMI_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN2_SHIFT)) & SRC_HDMI_RCR_DOMAIN2_MASK) + +#define SRC_HDMI_RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_HDMI_RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_HDMI_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN3_SHIFT)) & SRC_HDMI_RCR_DOMAIN3_MASK) + +#define SRC_HDMI_RCR_LOCK_MASK (0x40000000U) +#define SRC_HDMI_RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_HDMI_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_LOCK_SHIFT)) & SRC_HDMI_RCR_LOCK_MASK) + +#define SRC_HDMI_RCR_DOM_EN_MASK (0x80000000U) +#define SRC_HDMI_RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_HDMI_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOM_EN_SHIFT)) & SRC_HDMI_RCR_DOM_EN_MASK) +/*! @} */ + +/*! @name DISP_RCR - DISP Reset Control Register */ +/*! @{ */ + +#define SRC_DISP_RCR_DISP_RESET_MASK (0x1U) +#define SRC_DISP_RCR_DISP_RESET_SHIFT (0U) +/*! DISP_RESET + * 0b0..Don't reset dispmix + * 0b1..Reset dispmix + */ +#define SRC_DISP_RCR_DISP_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DISP_RESET_SHIFT)) & SRC_DISP_RCR_DISP_RESET_MASK) + +#define SRC_DISP_RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_DISP_RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_DISP_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN0_SHIFT)) & SRC_DISP_RCR_DOMAIN0_MASK) + +#define SRC_DISP_RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_DISP_RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_DISP_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN1_SHIFT)) & SRC_DISP_RCR_DOMAIN1_MASK) + +#define SRC_DISP_RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_DISP_RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_DISP_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN2_SHIFT)) & SRC_DISP_RCR_DOMAIN2_MASK) + +#define SRC_DISP_RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_DISP_RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_DISP_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN3_SHIFT)) & SRC_DISP_RCR_DOMAIN3_MASK) + +#define SRC_DISP_RCR_LOCK_MASK (0x40000000U) +#define SRC_DISP_RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_DISP_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_LOCK_SHIFT)) & SRC_DISP_RCR_LOCK_MASK) + +#define SRC_DISP_RCR_DOM_EN_MASK (0x80000000U) +#define SRC_DISP_RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_DISP_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOM_EN_SHIFT)) & SRC_DISP_RCR_DOM_EN_MASK) +/*! @} */ + +/*! @name GPU_RCR - GPU Reset Control Register */ +/*! @{ */ + +#define SRC_GPU_RCR_GPU_RESET_MASK (0x1U) +#define SRC_GPU_RCR_GPU_RESET_SHIFT (0U) +#define SRC_GPU_RCR_GPU_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_GPU_RESET_SHIFT)) & SRC_GPU_RCR_GPU_RESET_MASK) + +#define SRC_GPU_RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_GPU_RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_GPU_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN0_SHIFT)) & SRC_GPU_RCR_DOMAIN0_MASK) + +#define SRC_GPU_RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_GPU_RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_GPU_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN1_SHIFT)) & SRC_GPU_RCR_DOMAIN1_MASK) + +#define SRC_GPU_RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_GPU_RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_GPU_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN2_SHIFT)) & SRC_GPU_RCR_DOMAIN2_MASK) + +#define SRC_GPU_RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_GPU_RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_GPU_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN3_SHIFT)) & SRC_GPU_RCR_DOMAIN3_MASK) + +#define SRC_GPU_RCR_LOCK_MASK (0x40000000U) +#define SRC_GPU_RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_GPU_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_LOCK_SHIFT)) & SRC_GPU_RCR_LOCK_MASK) + +#define SRC_GPU_RCR_DOM_EN_MASK (0x80000000U) +#define SRC_GPU_RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_GPU_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOM_EN_SHIFT)) & SRC_GPU_RCR_DOM_EN_MASK) +/*! @} */ + +/*! @name VPU_RCR - VPU Reset Control Register */ +/*! @{ */ + +#define SRC_VPU_RCR_VPU_RESET_MASK (0x1U) +#define SRC_VPU_RCR_VPU_RESET_SHIFT (0U) +#define SRC_VPU_RCR_VPU_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_VPU_RESET_SHIFT)) & SRC_VPU_RCR_VPU_RESET_MASK) + +#define SRC_VPU_RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_VPU_RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_VPU_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN0_SHIFT)) & SRC_VPU_RCR_DOMAIN0_MASK) + +#define SRC_VPU_RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_VPU_RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_VPU_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN1_SHIFT)) & SRC_VPU_RCR_DOMAIN1_MASK) + +#define SRC_VPU_RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_VPU_RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_VPU_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN2_SHIFT)) & SRC_VPU_RCR_DOMAIN2_MASK) + +#define SRC_VPU_RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_VPU_RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_VPU_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN3_SHIFT)) & SRC_VPU_RCR_DOMAIN3_MASK) + +#define SRC_VPU_RCR_LOCK_MASK (0x40000000U) +#define SRC_VPU_RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_VPU_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_LOCK_SHIFT)) & SRC_VPU_RCR_LOCK_MASK) + +#define SRC_VPU_RCR_DOM_EN_MASK (0x80000000U) +#define SRC_VPU_RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_VPU_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOM_EN_SHIFT)) & SRC_VPU_RCR_DOM_EN_MASK) +/*! @} */ + +/*! @name PCIE2_RCR - PCIE2 Reset Control Register */ +/*! @{ */ + +#define SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N_MASK (0x1U) +#define SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N_SHIFT (0U) +#define SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N_SHIFT)) & SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N_MASK) + +#define SRC_PCIE2_RCR_PCIE_G_RST_MASK (0x2U) +#define SRC_PCIE2_RCR_PCIE_G_RST_SHIFT (1U) +#define SRC_PCIE2_RCR_PCIE_G_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_G_RST_SHIFT)) & SRC_PCIE2_RCR_PCIE_G_RST_MASK) + +#define SRC_PCIE2_RCR_PCIE_BTN_MASK (0x4U) +#define SRC_PCIE2_RCR_PCIE_BTN_SHIFT (2U) +#define SRC_PCIE2_RCR_PCIE_BTN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_BTN_SHIFT)) & SRC_PCIE2_RCR_PCIE_BTN_MASK) + +#define SRC_PCIE2_RCR_PCIE_PERST_MASK (0x8U) +#define SRC_PCIE2_RCR_PCIE_PERST_SHIFT (3U) +#define SRC_PCIE2_RCR_PCIE_PERST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_PERST_SHIFT)) & SRC_PCIE2_RCR_PCIE_PERST_MASK) + +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK (0x10U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT (4U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK) + +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST_MASK (0x20U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST_SHIFT (5U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST_MASK) + +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN_MASK (0x40U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN_SHIFT (6U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN_MASK) + +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY_MASK (0x80U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY_SHIFT (7U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY_MASK) + +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER_MASK (0x100U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER_SHIFT (8U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER_MASK) + +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT_MASK (0x200U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT_SHIFT (9U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT_MASK) + +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME_MASK (0x400U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME_SHIFT (10U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME_MASK) + +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF_MASK (0x800U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT (11U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF_MASK) + +#define SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX_MASK (0x1000U) +#define SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT (12U) +#define SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX_MASK) + +#define SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT_MASK (0x4000U) +#define SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT_SHIFT (14U) +#define SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT_MASK) + +#define SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK (0x8000U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT (15U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK) + +#define SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK (0x10000U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT (16U) +#define SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK) + +#define SRC_PCIE2_RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_PCIE2_RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_PCIE2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOMAIN0_SHIFT)) & SRC_PCIE2_RCR_DOMAIN0_MASK) + +#define SRC_PCIE2_RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_PCIE2_RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_PCIE2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOMAIN1_SHIFT)) & SRC_PCIE2_RCR_DOMAIN1_MASK) + +#define SRC_PCIE2_RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_PCIE2_RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_PCIE2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOMAIN2_SHIFT)) & SRC_PCIE2_RCR_DOMAIN2_MASK) + +#define SRC_PCIE2_RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_PCIE2_RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_PCIE2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOMAIN3_SHIFT)) & SRC_PCIE2_RCR_DOMAIN3_MASK) + +#define SRC_PCIE2_RCR_LOCK_MASK (0x40000000U) +#define SRC_PCIE2_RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_PCIE2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_LOCK_SHIFT)) & SRC_PCIE2_RCR_LOCK_MASK) + +#define SRC_PCIE2_RCR_DOM_EN_MASK (0x80000000U) +#define SRC_PCIE2_RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_PCIE2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOM_EN_SHIFT)) & SRC_PCIE2_RCR_DOM_EN_MASK) +/*! @} */ + +/*! @name MIPIPHY1_RCR - MIPI CSI1 PHY Reset Control Register */ +/*! @{ */ + +#define SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET_MASK (0x1U) +#define SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET_SHIFT (0U) +#define SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET_SHIFT)) & SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET_MASK) + +#define SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET_MASK (0x2U) +#define SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET_SHIFT (1U) +#define SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET_SHIFT)) & SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET_MASK) + +#define SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET_MASK (0x4U) +#define SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET_SHIFT (2U) +#define SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET_SHIFT)) & SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET_MASK) + +#define SRC_MIPIPHY1_RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_MIPIPHY1_RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_MIPIPHY1_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN0_MASK) + +#define SRC_MIPIPHY1_RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_MIPIPHY1_RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_MIPIPHY1_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN1_MASK) + +#define SRC_MIPIPHY1_RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_MIPIPHY1_RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_MIPIPHY1_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN2_MASK) + +#define SRC_MIPIPHY1_RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_MIPIPHY1_RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_MIPIPHY1_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN3_MASK) + +#define SRC_MIPIPHY1_RCR_LOCK_MASK (0x40000000U) +#define SRC_MIPIPHY1_RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_MIPIPHY1_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_LOCK_SHIFT)) & SRC_MIPIPHY1_RCR_LOCK_MASK) + +#define SRC_MIPIPHY1_RCR_DOM_EN_MASK (0x80000000U) +#define SRC_MIPIPHY1_RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_MIPIPHY1_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY1_RCR_DOM_EN_MASK) +/*! @} */ + +/*! @name MIPIPHY2_RCR - MIPI CSI2 PHY Reset Control Register */ +/*! @{ */ + +#define SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET_MASK (0x1U) +#define SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET_SHIFT (0U) +#define SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET_SHIFT)) & SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET_MASK) + +#define SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET_MASK (0x2U) +#define SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET_SHIFT (1U) +#define SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET_SHIFT)) & SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET_MASK) + +#define SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET_MASK (0x4U) +#define SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET_SHIFT (2U) +#define SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET_SHIFT)) & SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET_MASK) + +#define SRC_MIPIPHY2_RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_MIPIPHY2_RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_MIPIPHY2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN0_MASK) + +#define SRC_MIPIPHY2_RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_MIPIPHY2_RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_MIPIPHY2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN1_MASK) + +#define SRC_MIPIPHY2_RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_MIPIPHY2_RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_MIPIPHY2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN2_MASK) + +#define SRC_MIPIPHY2_RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_MIPIPHY2_RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_MIPIPHY2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN3_MASK) + +#define SRC_MIPIPHY2_RCR_LOCK_MASK (0x40000000U) +#define SRC_MIPIPHY2_RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_MIPIPHY2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_LOCK_SHIFT)) & SRC_MIPIPHY2_RCR_LOCK_MASK) + +#define SRC_MIPIPHY2_RCR_DOM_EN_MASK (0x80000000U) +#define SRC_MIPIPHY2_RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_MIPIPHY2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY2_RCR_DOM_EN_MASK) +/*! @} */ + +/*! @name SBMR1 - SRC Boot Mode Register 1 */ +/*! @{ */ + +#define SRC_SBMR1_BOOT_CFG_MASK (0xFFFFFFFFU) +#define SRC_SBMR1_BOOT_CFG_SHIFT (0U) +#define SRC_SBMR1_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG_SHIFT)) & SRC_SBMR1_BOOT_CFG_MASK) +/*! @} */ + +/*! @name SRSR - SRC Reset Status Register */ +/*! @{ */ + +#define SRC_SRSR_CSU_RESET_B_MASK (0x4U) +#define SRC_SRSR_CSU_RESET_B_SHIFT (2U) +/*! csu_reset_b + * 0b0..Reset is not a result of the csu_reset_b event. + * 0b1..Reset is a result of the csu_reset_b event. + */ +#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) + +#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) +#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) +/*! ipp_user_reset_b + * 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + */ +#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) + +#define SRC_SRSR_WDOG1_RST_B_MASK (0x10U) +#define SRC_SRSR_WDOG1_RST_B_SHIFT (4U) +/*! wdog1_rst_b + * 0b0..Reset is not a result of the watchdog1 time-out event. + * 0b1..Reset is a result of the watchdog1 time-out event. + */ +#define SRC_SRSR_WDOG1_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG1_RST_B_SHIFT)) & SRC_SRSR_WDOG1_RST_B_MASK) + +#define SRC_SRSR_JTAG_RST_B_MASK (0x20U) +#define SRC_SRSR_JTAG_RST_B_SHIFT (5U) +/*! jtag_rst_b + * 0b0..Reset is not a result of HIGH-Z reset from JTAG. + * 0b1..Reset is a result of HIGH-Z reset from JTAG. + */ +#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) + +#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) +#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) +/*! jtag_sw_rst + * 0b0..Reset is not a result of software reset from JTAG. + * 0b1..Reset is a result of software reset from JTAG. + */ +#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) + +#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) +#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) +/*! wdog3_rst_b + * 0b0..Reset is not a result of the watchdog3 time-out event. + * 0b1..Reset is a result of the watchdog3 time-out event. + */ +#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) + +#define SRC_SRSR_WDOG4_RST_B_MASK (0x100U) +#define SRC_SRSR_WDOG4_RST_B_SHIFT (8U) +/*! wdog4_rst_b + * 0b0..Reset is not a result of the watchdog4 time-out event. + * 0b1..Reset is a result of the watchdog4 time-out event. + */ +#define SRC_SRSR_WDOG4_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_SHIFT)) & SRC_SRSR_WDOG4_RST_B_MASK) + +#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x200U) +#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (9U) +/*! tempsense_rst_b + * 0b0..Reset is not a result of software reset from Temperature Sensor. + * 0b1..Reset is a result of software reset from Temperature Sensor. + */ +#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) +/*! @} */ + +/*! @name SISR - SRC Interrupt Status Register */ +/*! @{ */ + +#define SRC_SISR_HSICPHY_PASSED_RESET_MASK (0x2U) +#define SRC_SISR_HSICPHY_PASSED_RESET_SHIFT (1U) +/*! HSICPHY_PASSED_RESET + * 0b0..Interrupt generated not due to HSIC PHY passed reset + * 0b1..Interrupt generated due to HSIC PHY passed reset + */ +#define SRC_SISR_HSICPHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_HSICPHY_PASSED_RESET_SHIFT)) & SRC_SISR_HSICPHY_PASSED_RESET_MASK) + +#define SRC_SISR_OTGPHY1_PASSED_RESET_MASK (0x4U) +#define SRC_SISR_OTGPHY1_PASSED_RESET_SHIFT (2U) +/*! OTGPHY1_PASSED_RESET + * 0b0..Interrupt generated not due to OTG PHY1 passed reset + * 0b1..Interrupt generated due to OTG PHY1 passed reset + */ +#define SRC_SISR_OTGPHY1_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_OTGPHY1_PASSED_RESET_SHIFT)) & SRC_SISR_OTGPHY1_PASSED_RESET_MASK) + +#define SRC_SISR_OTGPHY2_PASSED_RESET_MASK (0x8U) +#define SRC_SISR_OTGPHY2_PASSED_RESET_SHIFT (3U) +/*! OTGPHY2_PASSED_RESET + * 0b0..Interrupt generated not due to OTG PHY2 passed reset + * 0b1..Interrupt generated due to OTG PHY2 passed reset + */ +#define SRC_SISR_OTGPHY2_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_OTGPHY2_PASSED_RESET_SHIFT)) & SRC_SISR_OTGPHY2_PASSED_RESET_MASK) + +#define SRC_SISR_MIPIPHY_PASSED_RESET_MASK (0x10U) +#define SRC_SISR_MIPIPHY_PASSED_RESET_SHIFT (4U) +/*! MIPIPHY_PASSED_RESET + * 0b0..Interrupt generated not due to MIPI PHY passed reset + * 0b1..Interrupt generated due to MIPI PHY passed reset + */ +#define SRC_SISR_MIPIPHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_MIPIPHY_PASSED_RESET_SHIFT)) & SRC_SISR_MIPIPHY_PASSED_RESET_MASK) + +#define SRC_SISR_PCIE1_PHY_PASSED_RESET_MASK (0x20U) +#define SRC_SISR_PCIE1_PHY_PASSED_RESET_SHIFT (5U) +/*! PCIE1_PHY_PASSED_RESET + * 0b0..Interrupt generated not due to PCIE1 PHY passed reset + * 0b1..Interrupt generated due to PCIE1 PHY passed reset + */ +#define SRC_SISR_PCIE1_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_PCIE1_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_PCIE1_PHY_PASSED_RESET_MASK) + +#define SRC_SISR_HDMI_PASSED_RESET_MASK (0x40U) +#define SRC_SISR_HDMI_PASSED_RESET_SHIFT (6U) +/*! HDMI_PASSED_RESET + * 0b0..Interrupt generated not due to HDMI passed reset + * 0b1..Interrupt generated due to HDMI passed reset + */ +#define SRC_SISR_HDMI_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_HDMI_PASSED_RESET_SHIFT)) & SRC_SISR_HDMI_PASSED_RESET_MASK) + +#define SRC_SISR_DISPLAY_PASSED_RESET_MASK (0x80U) +#define SRC_SISR_DISPLAY_PASSED_RESET_SHIFT (7U) +/*! DISPLAY_PASSED_RESET + * 0b0..Interrupt generated not due to DISPLAY passed reset + * 0b1..Interrupt generated due to DISPLAY passed reset + */ +#define SRC_SISR_DISPLAY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_DISPLAY_PASSED_RESET_SHIFT)) & SRC_SISR_DISPLAY_PASSED_RESET_MASK) + +#define SRC_SISR_M4C_PASSED_RESET_MASK (0x100U) +#define SRC_SISR_M4C_PASSED_RESET_SHIFT (8U) +/*! M4C_PASSED_RESET + * 0b0..interrupt generated not due to m4 core reset + * 0b1..interrupt generated due to m4 core reset + */ +#define SRC_SISR_M4C_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_M4C_PASSED_RESET_SHIFT)) & SRC_SISR_M4C_PASSED_RESET_MASK) + +#define SRC_SISR_M4P_PASSED_RESET_MASK (0x200U) +#define SRC_SISR_M4P_PASSED_RESET_SHIFT (9U) +/*! M4P_PASSED_RESET + * 0b0..interrupt generated not due to m4 platform reset + * 0b1..interrupt generated due to m4 platform reset + */ +#define SRC_SISR_M4P_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_M4P_PASSED_RESET_SHIFT)) & SRC_SISR_M4P_PASSED_RESET_MASK) + +#define SRC_SISR_GPU_PASSED_RESET_MASK (0x400U) +#define SRC_SISR_GPU_PASSED_RESET_SHIFT (10U) +/*! GPU_PASSED_RESET + * 0b0..interrupt generated not due to GPU reset + * 0b1..interrupt generated due to GPU reset + */ +#define SRC_SISR_GPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_GPU_PASSED_RESET_SHIFT)) & SRC_SISR_GPU_PASSED_RESET_MASK) + +#define SRC_SISR_VPU_PASSED_RESET_MASK (0x800U) +#define SRC_SISR_VPU_PASSED_RESET_SHIFT (11U) +/*! VPU_PASSED_RESET + * 0b0..interrupt generated not due to VPU reset + * 0b1..interrupt generated due to VPU reset + */ +#define SRC_SISR_VPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_VPU_PASSED_RESET_SHIFT)) & SRC_SISR_VPU_PASSED_RESET_MASK) + +#define SRC_SISR_PCIE2_PHY_PASSED_RESET_MASK (0x1000U) +#define SRC_SISR_PCIE2_PHY_PASSED_RESET_SHIFT (12U) +/*! PCIE2_PHY_PASSED_RESET + * 0b0..interrupt generated not due to PCIE2 PHY reset + * 0b1..interrupt generated due to PCIE2 PHY reset + */ +#define SRC_SISR_PCIE2_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_PCIE2_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_PCIE2_PHY_PASSED_RESET_MASK) + +#define SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET_MASK (0x2000U) +#define SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET_SHIFT (13U) +/*! MIPI_CSI1_PHY_PASSED_RESET + * 0b0..interrupt generated not due to MIPI CSI1 PHY reset + * 0b1..interrupt generated due to MIPI CSI1 PHY reset + */ +#define SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET_MASK) + +#define SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET_MASK (0x4000U) +#define SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET_SHIFT (14U) +/*! MIPI_CSI2_PHY_PASSED_RESET + * 0b0..interrupt generated not due to MIPI CSI2 PHY reset + * 0b1..interrupt generated due to MIPI CSI2 PHY reset + */ +#define SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET_MASK) +/*! @} */ + +/*! @name SIMR - SRC Interrupt Mask Register */ +/*! @{ */ + +#define SRC_SIMR_MASK_HSICPHY_PASSED_RESET_MASK (0x2U) +#define SRC_SIMR_MASK_HSICPHY_PASSED_RESET_SHIFT (1U) +/*! MASK_HSICPHY_PASSED_RESET + * 0b0..do not mask interrupt due to HSIC PHY passed reset - interrupt will be created + * 0b1..mask interrupt due to HSIC PHY passed reset + */ +#define SRC_SIMR_MASK_HSICPHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_HSICPHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_HSICPHY_PASSED_RESET_MASK) + +#define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_MASK (0x4U) +#define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_SHIFT (2U) +/*! MASK_OTGPHY1_PASSED_RESET + * 0b0..do not mask interrupt due to OTG PHY1 passed reset - interrupt will be created + * 0b1..mask interrupt due to OTG PHY1 passed reset + */ +#define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_MASK) + +#define SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_MASK (0x8U) +#define SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_SHIFT (3U) +/*! MASK_OTGPHY2_PASSED_RESET + * 0b0..do not mask interrupt due to OTG PHY2 passed reset - interrupt will be created + * 0b1..mask interrupt due to OTG PHY2 passed reset + */ +#define SRC_SIMR_MASK_OTGPHY2_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_MASK) + +#define SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_MASK (0x10U) +#define SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_SHIFT (4U) +/*! MASK_MIPIPHY_PASSED_RESET + * 0b0..do not mask interrupt due to MIPI PHY passed reset - interrupt will be created + * 0b1..mask interrupt due to MIPI PHY passed reset + */ +#define SRC_SIMR_MASK_MIPIPHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_MASK) + +#define SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET_MASK (0x20U) +#define SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET_SHIFT (5U) +/*! MASK_PCIE1_PHY_PASSED_RESET + * 0b0..do not mask interrupt due to PCIE1 PHY passed reset - interrupt will be created + * 0b1..mask interrupt due to PCIE1 PHY passed reset + */ +#define SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET_MASK) + +#define SRC_SIMR_MASK_HDMI_PASSED_RESET_MASK (0x40U) +#define SRC_SIMR_MASK_HDMI_PASSED_RESET_SHIFT (6U) +/*! MASK_HDMI_PASSED_RESET + * 0b0..do not mask interrupt due to HDMI passed reset - interrupt will be created + * 0b1..mask interrupt due to HDMI passed reset + */ +#define SRC_SIMR_MASK_HDMI_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_HDMI_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_HDMI_PASSED_RESET_MASK) + +#define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK (0x80U) +#define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT (7U) +/*! MASK_DISPLAY_PASSED_RESET + * 0b0..do not mask interrupt due to HDMI passed reset - interrupt will be created + * 0b1..mask interrupt due to HDMI passed reset + */ +#define SRC_SIMR_MASK_DISPLAY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK) + +#define SRC_SIMR_MASK_M4C_PASSED_RESET_MASK (0x100U) +#define SRC_SIMR_MASK_M4C_PASSED_RESET_SHIFT (8U) +/*! MASK_M4C_PASSED_RESET + * 0b0..do not mask interrupt due to m4 core passed reset - interrupt will be created + * 0b1..mask interrupt due to m4 core passed reset + */ +#define SRC_SIMR_MASK_M4C_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_M4C_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_M4C_PASSED_RESET_MASK) + +#define SRC_SIMR_MASK_M4P_PASSED_RESET_MASK (0x200U) +#define SRC_SIMR_MASK_M4P_PASSED_RESET_SHIFT (9U) +/*! MASK_M4P_PASSED_RESET + * 0b0..do not mask interrupt due to m4 platform passed reset - interrupt will be created + * 0b1..mask interrupt due to m4platform passed reset + */ +#define SRC_SIMR_MASK_M4P_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_M4P_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_M4P_PASSED_RESET_MASK) + +#define SRC_SIMR_MASK_GPU_PASSED_RESET_MASK (0x400U) +#define SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT (10U) +/*! MASK_GPU_PASSED_RESET + * 0b0..do not mask interrupt due to GPU passed reset - interrupt will be created + * 0b1..mask interrupt due to GPU passed reset + */ +#define SRC_SIMR_MASK_GPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_GPU_PASSED_RESET_MASK) + +#define SRC_SIMR_MASK_VPU_PASSED_RESET_MASK (0x800U) +#define SRC_SIMR_MASK_VPU_PASSED_RESET_SHIFT (11U) +/*! MASK_VPU_PASSED_RESET + * 0b0..do not mask interrupt due to VPU passed reset - interrupt will be created + * 0b1..mask interrupt due to VPU passed reset + */ +#define SRC_SIMR_MASK_VPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_VPU_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_VPU_PASSED_RESET_MASK) + +#define SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET_MASK (0x1000U) +#define SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET_SHIFT (12U) +/*! MASK_PCIE2_PHY_PASSED_RESET + * 0b0..do not mask interrupt due to PCIE2 PHY passed reset - interrupt will be created + * 0b1..mask interrupt due to PCIE2 PHY passed reset + */ +#define SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET_MASK) + +#define SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET_MASK (0x2000U) +#define SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET_SHIFT (13U) +/*! MASK_MIPI_CSI1_PHY_PASSED_RESET + * 0b0..do not mask interrupt due to MIPI CSI1 PHY passed reset - interrupt will be created + * 0b1..mask interrupt due to MIPI CSI1 PHY passed reset + */ +#define SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET_MASK) + +#define SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET_MASK (0x4000U) +#define SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET_SHIFT (14U) +/*! MASK_MIPI_CSI2_PHY_PASSED_RESET + * 0b0..do not mask interrupt due to MIPI CSI2 PHY passed reset - interrupt will be created + * 0b1..mask interrupt due to MIPI CSI2 PHY passed reset + */ +#define SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET_MASK) +/*! @} */ + +/*! @name SBMR2 - SRC Boot Mode Register 2 */ +/*! @{ */ + +#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) +#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) +#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) + +#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) +#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) +#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) + +#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) +#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) +#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) + +#define SRC_SBMR2_FUSE_FORCE_COLD_BOOT_MASK (0x20U) +#define SRC_SBMR2_FUSE_FORCE_COLD_BOOT_SHIFT (5U) +#define SRC_SBMR2_FUSE_FORCE_COLD_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_FUSE_FORCE_COLD_BOOT_SHIFT)) & SRC_SBMR2_FUSE_FORCE_COLD_BOOT_MASK) + +#define SRC_SBMR2_BMOD_MASK (0x3000000U) +#define SRC_SBMR2_BMOD_SHIFT (24U) +#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) +/*! @} */ + +/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ +/*! @{ */ + +#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) + +#define SRC_GPR_PERSISTENT_ARG1_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ARG1_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ARG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG1_SHIFT)) & SRC_GPR_PERSISTENT_ARG1_MASK) + +#define SRC_GPR_PERSISTENT_ARG2_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ARG2_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ARG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG2_SHIFT)) & SRC_GPR_PERSISTENT_ARG2_MASK) + +#define SRC_GPR_PERSISTENT_ARG3_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ARG3_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ARG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG3_SHIFT)) & SRC_GPR_PERSISTENT_ARG3_MASK) + +#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) + +#define SRC_GPR_PERSISTENT_ENTRY1_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY1_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY1_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY1_MASK) + +#define SRC_GPR_PERSISTENT_ENTRY2_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY2_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY2_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY2_MASK) + +#define SRC_GPR_PERSISTENT_ENTRY3_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY3_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY3_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY3_MASK) +/*! @} */ + +/* The count of SRC_GPR */ +#define SRC_GPR_COUNT (10U) + +/*! @name DDRC_RCR - SRC DDR Controller Reset Control Register */ +/*! @{ */ + +#define SRC_DDRC_RCR_DDRC1_PRST_MASK (0x1U) +#define SRC_DDRC_RCR_DDRC1_PRST_SHIFT (0U) +/*! DDRC1_PRST + * 0b0..De-ssert DDR Controller preset and DDR PHY reset reset + * 0b1..Assert DDR Controller preset and DDR PHY reset + */ +#define SRC_DDRC_RCR_DDRC1_PRST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PRST_SHIFT)) & SRC_DDRC_RCR_DDRC1_PRST_MASK) + +#define SRC_DDRC_RCR_DDRC1_CORE_RST_MASK (0x2U) +#define SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT (1U) +/*! DDRC1_CORE_RST + * 0b0..De-ssert DDR controller aresetn and core_ddrc_rstn + * 0b1..Assert DDR Controller preset and DDR PHY reset + */ +#define SRC_DDRC_RCR_DDRC1_CORE_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT)) & SRC_DDRC_RCR_DDRC1_CORE_RST_MASK) + +#define SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK (0x4U) +#define SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT (2U) +/*! DDRC1_PHY_RESET + * 0b0..De-ssert DDR controller + * 0b1..Assert DDR Controller + */ +#define SRC_DDRC_RCR_DDRC1_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK) + +#define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK (0x8U) +#define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT (3U) +/*! DDRC1_PHY_PWROKIN + * 0b0..De-ssert DDR controller + * 0b1..Assert DDR Controller + */ +#define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK) + +#define SRC_DDRC_RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_DDRC_RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_DDRC_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN0_SHIFT)) & SRC_DDRC_RCR_DOMAIN0_MASK) + +#define SRC_DDRC_RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_DDRC_RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_DDRC_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN1_SHIFT)) & SRC_DDRC_RCR_DOMAIN1_MASK) + +#define SRC_DDRC_RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_DDRC_RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_DDRC_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN2_SHIFT)) & SRC_DDRC_RCR_DOMAIN2_MASK) + +#define SRC_DDRC_RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_DDRC_RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_DDRC_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN3_SHIFT)) & SRC_DDRC_RCR_DOMAIN3_MASK) + +#define SRC_DDRC_RCR_LOCK_MASK (0x40000000U) +#define SRC_DDRC_RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_DDRC_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_LOCK_SHIFT)) & SRC_DDRC_RCR_LOCK_MASK) + +#define SRC_DDRC_RCR_DOM_EN_MASK (0x80000000U) +#define SRC_DDRC_RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_DDRC_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOM_EN_SHIFT)) & SRC_DDRC_RCR_DOM_EN_MASK) +/*! @} */ + +/*! @name DDRC2_RCR - SRC DDRC2 Controller Reset Control Register */ +/*! @{ */ + +#define SRC_DDRC2_RCR_DDRC2_PRST_MASK (0x1U) +#define SRC_DDRC2_RCR_DDRC2_PRST_SHIFT (0U) +/*! DDRC2_PRST + * 0b0..De-ssert DDRC2 Controller preset and DDR PHY reset reset + * 0b1..Assert DDRC2 Controller preset and DDR PHY reset + */ +#define SRC_DDRC2_RCR_DDRC2_PRST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DDRC2_PRST_SHIFT)) & SRC_DDRC2_RCR_DDRC2_PRST_MASK) + +#define SRC_DDRC2_RCR_DDRC2_CORE_RST_MASK (0x2U) +#define SRC_DDRC2_RCR_DDRC2_CORE_RST_SHIFT (1U) +/*! DDRC2_CORE_RST + * 0b0..De-ssert DDR controller aresetn and core_ddrc_rstn + * 0b1..Assert DDR Controller preset and DDR PHY reset + */ +#define SRC_DDRC2_RCR_DDRC2_CORE_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DDRC2_CORE_RST_SHIFT)) & SRC_DDRC2_RCR_DDRC2_CORE_RST_MASK) + +#define SRC_DDRC2_RCR_DDRC1_PHY_RESET_MASK (0x4U) +#define SRC_DDRC2_RCR_DDRC1_PHY_RESET_SHIFT (2U) +/*! DDRC1_PHY_RESET + * 0b0..De-ssert DDR controller + * 0b1..Assert DDR Controller + */ +#define SRC_DDRC2_RCR_DDRC1_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DDRC1_PHY_RESET_SHIFT)) & SRC_DDRC2_RCR_DDRC1_PHY_RESET_MASK) + +#define SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_MASK (0x8U) +#define SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_SHIFT (3U) +/*! DDRC1_PHY_PWROKIN + * 0b0..De-ssert DDR controller + * 0b1..Assert DDR Controller + */ +#define SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_SHIFT)) & SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_MASK) + +#define SRC_DDRC2_RCR_DOMAIN0_MASK (0x1000000U) +#define SRC_DDRC2_RCR_DOMAIN0_SHIFT (24U) +/*! DOMAIN0 + * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain0. The master from domain3 can write to this register + */ +#define SRC_DDRC2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOMAIN0_SHIFT)) & SRC_DDRC2_RCR_DOMAIN0_MASK) + +#define SRC_DDRC2_RCR_DOMAIN1_MASK (0x2000000U) +#define SRC_DDRC2_RCR_DOMAIN1_SHIFT (25U) +/*! DOMAIN1 + * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain1. The master from domain3 can write to this register + */ +#define SRC_DDRC2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOMAIN1_SHIFT)) & SRC_DDRC2_RCR_DOMAIN1_MASK) + +#define SRC_DDRC2_RCR_DOMAIN2_MASK (0x4000000U) +#define SRC_DDRC2_RCR_DOMAIN2_SHIFT (26U) +/*! DOMAIN2 + * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain2. The master from domain3 can write to this register + */ +#define SRC_DDRC2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOMAIN2_SHIFT)) & SRC_DDRC2_RCR_DOMAIN2_MASK) + +#define SRC_DDRC2_RCR_DOMAIN3_MASK (0x8000000U) +#define SRC_DDRC2_RCR_DOMAIN3_SHIFT (27U) +/*! DOMAIN3 + * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. + * 0b1..This register is assigned to domain3. The master from domain3 can write to this register + */ +#define SRC_DDRC2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOMAIN3_SHIFT)) & SRC_DDRC2_RCR_DOMAIN3_MASK) + +#define SRC_DDRC2_RCR_LOCK_MASK (0x40000000U) +#define SRC_DDRC2_RCR_LOCK_SHIFT (30U) +/*! LOCK + * 0b0..[31] and [27:24] bits can be modified + * 0b1..[31] and [27:24] bits cannot be modified + */ +#define SRC_DDRC2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_LOCK_SHIFT)) & SRC_DDRC2_RCR_LOCK_MASK) + +#define SRC_DDRC2_RCR_DOM_EN_MASK (0x80000000U) +#define SRC_DDRC2_RCR_DOM_EN_SHIFT (31U) +/*! DOM_EN + * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by + * the masters from the domains specified in [27:24] area. + */ +#define SRC_DDRC2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOM_EN_SHIFT)) & SRC_DDRC2_RCR_DOM_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SRC_Register_Masks */ + + +/* SRC - Peripheral instance base addresses */ +/** Peripheral SRC base address */ +#define SRC_BASE (0x30390000u) +/** Peripheral SRC base pointer */ +#define SRC ((SRC_Type *)SRC_BASE) +/** Array initializer of SRC peripheral base addresses */ +#define SRC_BASE_ADDRS { SRC_BASE } +/** Array initializer of SRC peripheral base pointers */ +#define SRC_BASE_PTRS { SRC } +/** Interrupt vectors for the SRC peripheral type */ +#define SRC_IRQS { SRC_IRQn } +#define SRC_COMBINED_IRQS { SRC_Combined_IRQn } + +/*! + * @} + */ /* end of group SRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SUBSAM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SUBSAM_Peripheral_Access_Layer SUBSAM Peripheral Access Layer + * @{ + */ + +/** SUBSAM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< , offset: 0x0 */ + __IO uint32_t SET; /**< , offset: 0x4 */ + __IO uint32_t CLR; /**< , offset: 0x8 */ + __IO uint32_t TOG; /**< , offset: 0xC */ + } SS_SYS_CTRL; + struct { /* offset: 0x10 */ + __IO uint32_t RW; /**< , offset: 0x10 */ + __IO uint32_t SET; /**< , offset: 0x14 */ + __IO uint32_t CLR; /**< , offset: 0x18 */ + __IO uint32_t TOG; /**< , offset: 0x1C */ + } SS_DISPLAY; + struct { /* offset: 0x20 */ + __IO uint32_t RW; /**< , offset: 0x20 */ + __IO uint32_t SET; /**< , offset: 0x24 */ + __IO uint32_t CLR; /**< , offset: 0x28 */ + __IO uint32_t TOG; /**< , offset: 0x2C */ + } SS_HSYNC; + struct { /* offset: 0x30 */ + __IO uint32_t RW; /**< , offset: 0x30 */ + __IO uint32_t SET; /**< , offset: 0x34 */ + __IO uint32_t CLR; /**< , offset: 0x38 */ + __IO uint32_t TOG; /**< , offset: 0x3C */ + } SS_VSYNC; + struct { /* offset: 0x40 */ + __IO uint32_t RW; /**< , offset: 0x40 */ + __IO uint32_t SET; /**< , offset: 0x44 */ + __IO uint32_t CLR; /**< , offset: 0x48 */ + __IO uint32_t TOG; /**< , offset: 0x4C */ + } SS_DE_ULC; + struct { /* offset: 0x50 */ + __IO uint32_t RW; /**< , offset: 0x50 */ + __IO uint32_t SET; /**< , offset: 0x54 */ + __IO uint32_t CLR; /**< , offset: 0x58 */ + __IO uint32_t TOG; /**< , offset: 0x5C */ + } SS_DE_LRC; + struct { /* offset: 0x60 */ + __IO uint32_t RW; /**< , offset: 0x60 */ + __IO uint32_t SET; /**< , offset: 0x64 */ + __IO uint32_t CLR; /**< , offset: 0x68 */ + __IO uint32_t TOG; /**< , offset: 0x6C */ + } SS_MODE; + struct { /* offset: 0x70 */ + __IO uint32_t RW; /**< , offset: 0x70 */ + __IO uint32_t SET; /**< , offset: 0x74 */ + __IO uint32_t CLR; /**< , offset: 0x78 */ + __IO uint32_t TOG; /**< , offset: 0x7C */ + } SS_COEFF; + struct { /* offset: 0x80 */ + __IO uint32_t RW; /**< , offset: 0x80 */ + __IO uint32_t SET; /**< , offset: 0x84 */ + __IO uint32_t CLR; /**< , offset: 0x88 */ + __IO uint32_t TOG; /**< , offset: 0x8C */ + } SS_CLIP_CB; + struct { /* offset: 0x90 */ + __IO uint32_t RW; /**< , offset: 0x90 */ + __IO uint32_t SET; /**< , offset: 0x94 */ + __IO uint32_t CLR; /**< , offset: 0x98 */ + __IO uint32_t TOG; /**< , offset: 0x9C */ + } SS_CLIP_CR; + struct { /* offset: 0xA0 */ + __IO uint32_t RW; /**< , offset: 0xA0 */ + __IO uint32_t SET; /**< , offset: 0xA4 */ + __IO uint32_t CLR; /**< , offset: 0xA8 */ + __IO uint32_t TOG; /**< , offset: 0xAC */ + } SS_INTER_MODE; + __IO uint32_t SS_CHKSUM_CTRL; /**< , offset: 0xB0 */ + __IO uint32_t SS_CHKSUM_START; /**< , offset: 0xB4 */ + __IO uint32_t SS_CHKSUM_END; /**< , offset: 0xB8 */ + __I uint32_t SS_CHKSUM_DATA_LOW; /**< , offset: 0xBC */ + __IO uint32_t SS_CHKSUM_DATA_HIGH; /**< , offset: 0xC0 */ +} SUBSAM_Type; + +/* ---------------------------------------------------------------------------- + -- SUBSAM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SUBSAM_Register_Masks SUBSAM Register Masks + * @{ + */ + +/*! @name SS_SYS_CTRL - */ +/*! @{ */ + +#define SUBSAM_SS_SYS_CTRL_RUN_EN_MASK (0x1U) +#define SUBSAM_SS_SYS_CTRL_RUN_EN_SHIFT (0U) +#define SUBSAM_SS_SYS_CTRL_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_SYS_CTRL_RUN_EN_SHIFT)) & SUBSAM_SS_SYS_CTRL_RUN_EN_MASK) +/*! @} */ + +/*! @name SS_DISPLAY - */ +/*! @{ */ + +#define SUBSAM_SS_DISPLAY_LRC_X_MASK (0x1FFFU) +#define SUBSAM_SS_DISPLAY_LRC_X_SHIFT (0U) +#define SUBSAM_SS_DISPLAY_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DISPLAY_LRC_X_SHIFT)) & SUBSAM_SS_DISPLAY_LRC_X_MASK) + +#define SUBSAM_SS_DISPLAY_LRC_Y_MASK (0x1FFF0000U) +#define SUBSAM_SS_DISPLAY_LRC_Y_SHIFT (16U) +#define SUBSAM_SS_DISPLAY_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DISPLAY_LRC_Y_SHIFT)) & SUBSAM_SS_DISPLAY_LRC_Y_MASK) +/*! @} */ + +/*! @name SS_HSYNC - */ +/*! @{ */ + +#define SUBSAM_SS_HSYNC_START_MASK (0x1FFFU) +#define SUBSAM_SS_HSYNC_START_SHIFT (0U) +#define SUBSAM_SS_HSYNC_START(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_HSYNC_START_SHIFT)) & SUBSAM_SS_HSYNC_START_MASK) + +#define SUBSAM_SS_HSYNC_END_MASK (0x1FFF0000U) +#define SUBSAM_SS_HSYNC_END_SHIFT (16U) +#define SUBSAM_SS_HSYNC_END(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_HSYNC_END_SHIFT)) & SUBSAM_SS_HSYNC_END_MASK) + +#define SUBSAM_SS_HSYNC_POL_MASK (0x80000000U) +#define SUBSAM_SS_HSYNC_POL_SHIFT (31U) +#define SUBSAM_SS_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_HSYNC_POL_SHIFT)) & SUBSAM_SS_HSYNC_POL_MASK) +/*! @} */ + +/*! @name SS_VSYNC - */ +/*! @{ */ + +#define SUBSAM_SS_VSYNC_START_MASK (0x1FFFU) +#define SUBSAM_SS_VSYNC_START_SHIFT (0U) +#define SUBSAM_SS_VSYNC_START(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_VSYNC_START_SHIFT)) & SUBSAM_SS_VSYNC_START_MASK) + +#define SUBSAM_SS_VSYNC_END_MASK (0x1FFF0000U) +#define SUBSAM_SS_VSYNC_END_SHIFT (16U) +#define SUBSAM_SS_VSYNC_END(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_VSYNC_END_SHIFT)) & SUBSAM_SS_VSYNC_END_MASK) + +#define SUBSAM_SS_VSYNC_POL_MASK (0x80000000U) +#define SUBSAM_SS_VSYNC_POL_SHIFT (31U) +#define SUBSAM_SS_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_VSYNC_POL_SHIFT)) & SUBSAM_SS_VSYNC_POL_MASK) +/*! @} */ + +/*! @name SS_DE_ULC - */ +/*! @{ */ + +#define SUBSAM_SS_DE_ULC_ULC_X_MASK (0x1FFFU) +#define SUBSAM_SS_DE_ULC_ULC_X_SHIFT (0U) +#define SUBSAM_SS_DE_ULC_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_ULC_ULC_X_SHIFT)) & SUBSAM_SS_DE_ULC_ULC_X_MASK) + +#define SUBSAM_SS_DE_ULC_ULC_Y_MASK (0x1FFF0000U) +#define SUBSAM_SS_DE_ULC_ULC_Y_SHIFT (16U) +#define SUBSAM_SS_DE_ULC_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_ULC_ULC_Y_SHIFT)) & SUBSAM_SS_DE_ULC_ULC_Y_MASK) + +#define SUBSAM_SS_DE_ULC_POL_MASK (0x80000000U) +#define SUBSAM_SS_DE_ULC_POL_SHIFT (31U) +#define SUBSAM_SS_DE_ULC_POL(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_ULC_POL_SHIFT)) & SUBSAM_SS_DE_ULC_POL_MASK) +/*! @} */ + +/*! @name SS_DE_LRC - */ +/*! @{ */ + +#define SUBSAM_SS_DE_LRC_LRC_X_MASK (0x1FFFU) +#define SUBSAM_SS_DE_LRC_LRC_X_SHIFT (0U) +#define SUBSAM_SS_DE_LRC_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_LRC_LRC_X_SHIFT)) & SUBSAM_SS_DE_LRC_LRC_X_MASK) + +#define SUBSAM_SS_DE_LRC_LRC_Y_MASK (0x1FFF0000U) +#define SUBSAM_SS_DE_LRC_LRC_Y_SHIFT (16U) +#define SUBSAM_SS_DE_LRC_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_LRC_LRC_Y_SHIFT)) & SUBSAM_SS_DE_LRC_LRC_Y_MASK) +/*! @} */ + +/*! @name SS_MODE - */ +/*! @{ */ + +#define SUBSAM_SS_MODE_PIPE_MODE_MASK (0x3U) +#define SUBSAM_SS_MODE_PIPE_MODE_SHIFT (0U) +#define SUBSAM_SS_MODE_PIPE_MODE(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_PIPE_MODE_SHIFT)) & SUBSAM_SS_MODE_PIPE_MODE_MASK) + +#define SUBSAM_SS_MODE_COMP_SEL0_OUT_MASK (0x300U) +#define SUBSAM_SS_MODE_COMP_SEL0_OUT_SHIFT (8U) +#define SUBSAM_SS_MODE_COMP_SEL0_OUT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL0_OUT_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL0_OUT_MASK) + +#define SUBSAM_SS_MODE_COMP_SEL1_OUT_MASK (0xC00U) +#define SUBSAM_SS_MODE_COMP_SEL1_OUT_SHIFT (10U) +#define SUBSAM_SS_MODE_COMP_SEL1_OUT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL1_OUT_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL1_OUT_MASK) + +#define SUBSAM_SS_MODE_COMP_SEL2_OUT_MASK (0x3000U) +#define SUBSAM_SS_MODE_COMP_SEL2_OUT_SHIFT (12U) +#define SUBSAM_SS_MODE_COMP_SEL2_OUT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL2_OUT_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL2_OUT_MASK) + +#define SUBSAM_SS_MODE_COMP_SEL0_IN_MASK (0x30000U) +#define SUBSAM_SS_MODE_COMP_SEL0_IN_SHIFT (16U) +#define SUBSAM_SS_MODE_COMP_SEL0_IN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL0_IN_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL0_IN_MASK) + +#define SUBSAM_SS_MODE_COMP_SEL1_IN_MASK (0xC0000U) +#define SUBSAM_SS_MODE_COMP_SEL1_IN_SHIFT (18U) +#define SUBSAM_SS_MODE_COMP_SEL1_IN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL1_IN_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL1_IN_MASK) + +#define SUBSAM_SS_MODE_COMP_SEL2_IN_MASK (0x300000U) +#define SUBSAM_SS_MODE_COMP_SEL2_IN_SHIFT (20U) +#define SUBSAM_SS_MODE_COMP_SEL2_IN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL2_IN_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL2_IN_MASK) +/*! @} */ + +/*! @name SS_COEFF - */ +/*! @{ */ + +#define SUBSAM_SS_COEFF_HORIZ_A_MASK (0xFU) +#define SUBSAM_SS_COEFF_HORIZ_A_SHIFT (0U) +#define SUBSAM_SS_COEFF_HORIZ_A(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_HORIZ_A_SHIFT)) & SUBSAM_SS_COEFF_HORIZ_A_MASK) + +#define SUBSAM_SS_COEFF_HORIZ_B_MASK (0xF0U) +#define SUBSAM_SS_COEFF_HORIZ_B_SHIFT (4U) +#define SUBSAM_SS_COEFF_HORIZ_B(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_HORIZ_B_SHIFT)) & SUBSAM_SS_COEFF_HORIZ_B_MASK) + +#define SUBSAM_SS_COEFF_HORIZ_C_MASK (0xF00U) +#define SUBSAM_SS_COEFF_HORIZ_C_SHIFT (8U) +#define SUBSAM_SS_COEFF_HORIZ_C(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_HORIZ_C_SHIFT)) & SUBSAM_SS_COEFF_HORIZ_C_MASK) + +#define SUBSAM_SS_COEFF_HORIZ_NORM_MASK (0x7000U) +#define SUBSAM_SS_COEFF_HORIZ_NORM_SHIFT (12U) +#define SUBSAM_SS_COEFF_HORIZ_NORM(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_HORIZ_NORM_SHIFT)) & SUBSAM_SS_COEFF_HORIZ_NORM_MASK) + +#define SUBSAM_SS_COEFF_VERT_A_MASK (0xF0000U) +#define SUBSAM_SS_COEFF_VERT_A_SHIFT (16U) +#define SUBSAM_SS_COEFF_VERT_A(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_VERT_A_SHIFT)) & SUBSAM_SS_COEFF_VERT_A_MASK) + +#define SUBSAM_SS_COEFF_VERT_B_MASK (0xF00000U) +#define SUBSAM_SS_COEFF_VERT_B_SHIFT (20U) +#define SUBSAM_SS_COEFF_VERT_B(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_VERT_B_SHIFT)) & SUBSAM_SS_COEFF_VERT_B_MASK) + +#define SUBSAM_SS_COEFF_VERT_C_MASK (0xF000000U) +#define SUBSAM_SS_COEFF_VERT_C_SHIFT (24U) +#define SUBSAM_SS_COEFF_VERT_C(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_VERT_C_SHIFT)) & SUBSAM_SS_COEFF_VERT_C_MASK) + +#define SUBSAM_SS_COEFF_VERT_NORM_MASK (0x70000000U) +#define SUBSAM_SS_COEFF_VERT_NORM_SHIFT (28U) +#define SUBSAM_SS_COEFF_VERT_NORM(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_VERT_NORM_SHIFT)) & SUBSAM_SS_COEFF_VERT_NORM_MASK) +/*! @} */ + +/*! @name SS_CLIP_CB - */ +/*! @{ */ + +#define SUBSAM_SS_CLIP_CB_MIN_MASK (0xFFFU) +#define SUBSAM_SS_CLIP_CB_MIN_SHIFT (0U) +#define SUBSAM_SS_CLIP_CB_MIN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CLIP_CB_MIN_SHIFT)) & SUBSAM_SS_CLIP_CB_MIN_MASK) + +#define SUBSAM_SS_CLIP_CB_MAX_MASK (0xFFF0000U) +#define SUBSAM_SS_CLIP_CB_MAX_SHIFT (16U) +#define SUBSAM_SS_CLIP_CB_MAX(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CLIP_CB_MAX_SHIFT)) & SUBSAM_SS_CLIP_CB_MAX_MASK) +/*! @} */ + +/*! @name SS_CLIP_CR - */ +/*! @{ */ + +#define SUBSAM_SS_CLIP_CR_MIN_MASK (0xFFFU) +#define SUBSAM_SS_CLIP_CR_MIN_SHIFT (0U) +#define SUBSAM_SS_CLIP_CR_MIN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CLIP_CR_MIN_SHIFT)) & SUBSAM_SS_CLIP_CR_MIN_MASK) + +#define SUBSAM_SS_CLIP_CR_MAX_MASK (0xFFF0000U) +#define SUBSAM_SS_CLIP_CR_MAX_SHIFT (16U) +#define SUBSAM_SS_CLIP_CR_MAX(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CLIP_CR_MAX_SHIFT)) & SUBSAM_SS_CLIP_CR_MAX_MASK) +/*! @} */ + +/*! @name SS_INTER_MODE - */ +/*! @{ */ + +#define SUBSAM_SS_INTER_MODE_INT_EN_MASK (0x1U) +#define SUBSAM_SS_INTER_MODE_INT_EN_SHIFT (0U) +#define SUBSAM_SS_INTER_MODE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_INTER_MODE_INT_EN_SHIFT)) & SUBSAM_SS_INTER_MODE_INT_EN_MASK) + +#define SUBSAM_SS_INTER_MODE_VSYNC_SHIFT_MASK (0x2U) +#define SUBSAM_SS_INTER_MODE_VSYNC_SHIFT_SHIFT (1U) +#define SUBSAM_SS_INTER_MODE_VSYNC_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_INTER_MODE_VSYNC_SHIFT_SHIFT)) & SUBSAM_SS_INTER_MODE_VSYNC_SHIFT_MASK) +/*! @} */ + +/*! @name SS_CHKSUM_CTRL - */ +/*! @{ */ + +#define SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN_MASK (0x1U) +#define SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN_SHIFT (0U) +/*! CHKSUM_EN + * 0b0..Checksum is disabled. + * 0b1..Checksum is enabled. + */ +#define SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN_SHIFT)) & SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN_MASK) + +#define SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES_MASK (0xF0U) +#define SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES_SHIFT (4U) +/*! NUM_FRAMES + * 0b0000..Continuous mode. Output a checksum after each start trigger to end trigger process. + * 0b0001..Accumulate the cheksum over one complete frame. + * 0b0010..Accumulate the cheksum over two complete frames. + * 0b0011-0b1111..Accumulate the cheksum over NUM_FRAMES complete frames. + */ +#define SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES_SHIFT)) & SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES_MASK) +/*! @} */ + +/*! @name SS_CHKSUM_START - */ +/*! @{ */ + +#define SUBSAM_SS_CHKSUM_START_VCOUNT_START_MASK (0x1FFFU) +#define SUBSAM_SS_CHKSUM_START_VCOUNT_START_SHIFT (0U) +#define SUBSAM_SS_CHKSUM_START_VCOUNT_START(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_START_VCOUNT_START_SHIFT)) & SUBSAM_SS_CHKSUM_START_VCOUNT_START_MASK) + +#define SUBSAM_SS_CHKSUM_START_HCOUNT_START_MASK (0x1FFF0000U) +#define SUBSAM_SS_CHKSUM_START_HCOUNT_START_SHIFT (16U) +#define SUBSAM_SS_CHKSUM_START_HCOUNT_START(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_START_HCOUNT_START_SHIFT)) & SUBSAM_SS_CHKSUM_START_HCOUNT_START_MASK) +/*! @} */ + +/*! @name SS_CHKSUM_END - */ +/*! @{ */ + +#define SUBSAM_SS_CHKSUM_END_VCOUNT_END_MASK (0x1FFFU) +#define SUBSAM_SS_CHKSUM_END_VCOUNT_END_SHIFT (0U) +#define SUBSAM_SS_CHKSUM_END_VCOUNT_END(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_END_VCOUNT_END_SHIFT)) & SUBSAM_SS_CHKSUM_END_VCOUNT_END_MASK) + +#define SUBSAM_SS_CHKSUM_END_HCOUNT_END_MASK (0x1FFF0000U) +#define SUBSAM_SS_CHKSUM_END_HCOUNT_END_SHIFT (16U) +#define SUBSAM_SS_CHKSUM_END_HCOUNT_END(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_END_HCOUNT_END_SHIFT)) & SUBSAM_SS_CHKSUM_END_HCOUNT_END_MASK) +/*! @} */ + +/*! @name SS_CHKSUM_DATA_LOW - */ +/*! @{ */ + +#define SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT_MASK (0xFFFFFFFFU) +#define SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT_SHIFT (0U) +#define SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT_SHIFT)) & SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT_MASK) +/*! @} */ + +/*! @name SS_CHKSUM_DATA_HIGH - */ +/*! @{ */ + +#define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT_MASK (0x3FFU) +#define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT_SHIFT (0U) +#define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT_SHIFT)) & SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT_MASK) + +#define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD_MASK (0x80000000U) +#define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD_SHIFT (31U) +#define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD_SHIFT)) & SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SUBSAM_Register_Masks */ + + +/* SUBSAM - Peripheral instance base addresses */ +/** Peripheral DCSS__SUBSAM base address */ +#define DCSS__SUBSAM_BASE (0x32E1B000u) +/** Peripheral DCSS__SUBSAM base pointer */ +#define DCSS__SUBSAM ((SUBSAM_Type *)DCSS__SUBSAM_BASE) +/** Array initializer of SUBSAM peripheral base addresses */ +#define SUBSAM_BASE_ADDRS { DCSS__SUBSAM_BASE } +/** Array initializer of SUBSAM peripheral base pointers */ +#define SUBSAM_BASE_PTRS { DCSS__SUBSAM } + +/*! + * @} + */ /* end of group SUBSAM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TMU_Peripheral_Access_Layer TMU Peripheral Access Layer + * @{ + */ + +/** TMU - Register Layout Typedef */ +typedef struct { + __IO uint32_t TMR; /**< TMU Mode register, offset: 0x0 */ + __I uint32_t TSR; /**< TMU Status register, offset: 0x4 */ + __IO uint32_t TMTMIR; /**< TMU Monitor Temperature Measurement Interval register, offset: 0x8 */ + uint8_t RESERVED_0[20]; + __IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x20 */ + __IO uint32_t TIDR; /**< TMU Interrupt Detect register, offset: 0x24 */ + __IO uint32_t TISCR; /**< TMU Interrupt Site Capture register, offset: 0x28 */ + __IO uint32_t TICSCR; /**< TMU Interrupt Critical Site Capture register, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __I uint32_t TMHTCRH; /**< TMU Monitor High Temperature Capture register, offset: 0x40 */ + __I uint32_t TMHTCRL; /**< TMU Monitor Low Temperature Capture register, offset: 0x44 */ + uint8_t RESERVED_2[8]; + __IO uint32_t TMHTITR; /**< TMU Monitor High Temperature Immediate Threshold register, offset: 0x50 */ + __IO uint32_t TMHTATR; /**< TMU Monitor High Temperature Average threshold register, offset: 0x54 */ + __IO uint32_t TMHTACTR; /**< TMU Monitor High Temperature Average Critical Threshold register, offset: 0x58 */ + uint8_t RESERVED_3[36]; + __IO uint32_t TTCFGR; /**< TMU Temperature Configuration register, offset: 0x80 */ + __IO uint32_t TSCFGR; /**< TMU Sensor Configuration register, offset: 0x84 */ + uint8_t RESERVED_4[120]; + struct { /* offset: 0x100, array step: 0x10 */ + __I uint32_t TRITSR; /**< TMU Report Immediate Temperature Site register n, array offset: 0x100, array step: 0x10 */ + __I uint32_t TRATSR; /**< TMU Report Average Temperature Site register n, array offset: 0x104, array step: 0x10 */ + uint8_t RESERVED_0[8]; + } TRTSR[16]; + uint8_t RESERVED_5[2552]; + __I uint32_t IPBRR0; /**< IP Block Revision register 0, offset: 0xBF8 */ + uint8_t RESERVED_6[788]; + __IO uint32_t TTRCR[4]; /**< TMU Temperature Range n Control register, array offset: 0xF10, array step: 0x4 */ +} TMU_Type; + +/* ---------------------------------------------------------------------------- + -- TMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TMU_Register_Masks TMU Register Masks + * @{ + */ + +/*! @name TMR - TMU Mode register */ +/*! @{ */ + +#define TMU_TMR_MSITE_MASK (0xFFFFU) +#define TMU_TMR_MSITE_SHIFT (0U) +#define TMU_TMR_MSITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_MSITE_SHIFT)) & TMU_TMR_MSITE_MASK) + +#define TMU_TMR_ALPF_MASK (0xC000000U) +#define TMU_TMR_ALPF_SHIFT (26U) +/*! ALPF + * 0b00..1.0 + * 0b01..0.5 + * 0b10..0.25 + * 0b11..0.125 + */ +#define TMU_TMR_ALPF(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_ALPF_SHIFT)) & TMU_TMR_ALPF_MASK) + +#define TMU_TMR_ME_MASK (0x80000000U) +#define TMU_TMR_ME_SHIFT (31U) +/*! ME + * 0b0..No monitoring. Power saving mode. + * 0b1..Monitoring of sites as defined by MSITE. + */ +#define TMU_TMR_ME(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_ME_SHIFT)) & TMU_TMR_ME_MASK) +/*! @} */ + +/*! @name TSR - TMU Status register */ +/*! @{ */ + +#define TMU_TSR_ORH_MASK (0x10000000U) +#define TMU_TSR_ORH_SHIFT (28U) +#define TMU_TSR_ORH(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_ORH_SHIFT)) & TMU_TSR_ORH_MASK) + +#define TMU_TSR_ORL_MASK (0x20000000U) +#define TMU_TSR_ORL_SHIFT (29U) +#define TMU_TSR_ORL(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_ORL_SHIFT)) & TMU_TSR_ORL_MASK) + +#define TMU_TSR_MIE_MASK (0x40000000U) +#define TMU_TSR_MIE_SHIFT (30U) +/*! MIE + * 0b0..Monitoring interval not exceeded. + * 0b1..Monitoring interval exceeded. The time required to perform measurement of all monitored sites has + * exceeded the monitoring interval as defined by TMTMIR. + */ +#define TMU_TSR_MIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_MIE_SHIFT)) & TMU_TSR_MIE_MASK) +/*! @} */ + +/*! @name TMTMIR - TMU Monitor Temperature Measurement Interval register */ +/*! @{ */ + +#define TMU_TMTMIR_TMI_MASK (0xFU) +#define TMU_TMTMIR_TMI_SHIFT (0U) +#define TMU_TMTMIR_TMI(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMTMIR_TMI_SHIFT)) & TMU_TMTMIR_TMI_MASK) +/*! @} */ + +/*! @name TIER - TMU Interrupt Enable register */ +/*! @{ */ + +#define TMU_TIER_ATCTEIE_MASK (0x20000000U) +#define TMU_TIER_ATCTEIE_SHIFT (29U) +/*! ATCTEIE + * 0b0..Disabled. + * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATCTE] is set. + */ +#define TMU_TIER_ATCTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATCTEIE_SHIFT)) & TMU_TIER_ATCTEIE_MASK) + +#define TMU_TIER_ATTEIE_MASK (0x40000000U) +#define TMU_TIER_ATTEIE_SHIFT (30U) +/*! ATTEIE + * 0b0..Disabled. + * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATTE] is set. + */ +#define TMU_TIER_ATTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATTEIE_SHIFT)) & TMU_TIER_ATTEIE_MASK) + +#define TMU_TIER_ITTEIE_MASK (0x80000000U) +#define TMU_TIER_ITTEIE_SHIFT (31U) +/*! ITTEIE + * 0b0..Disabled. + * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ITTE] is set. + */ +#define TMU_TIER_ITTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ITTEIE_SHIFT)) & TMU_TIER_ITTEIE_MASK) +/*! @} */ + +/*! @name TIDR - TMU Interrupt Detect register */ +/*! @{ */ + +#define TMU_TIDR_ATCTE_MASK (0x20000000U) +#define TMU_TIDR_ATCTE_SHIFT (29U) +/*! ATCTE + * 0b0..No threshold exceeded. + * 0b1..Average temperature critical threshold, as defined by TMHTACTR, has been exceeded by one or more + * monitored sites. The sites which has exceeded the threshold are captured in TICSCR[CASITE]. + */ +#define TMU_TIDR_ATCTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATCTE_SHIFT)) & TMU_TIDR_ATCTE_MASK) + +#define TMU_TIDR_ATTE_MASK (0x40000000U) +#define TMU_TIDR_ATTE_SHIFT (30U) +/*! ATTE + * 0b0..No threshold exceeded. + * 0b1..Average temperature threshold, as defined by TMHTATR, has been exceeded by one or more monitored sites. + * The sites which has exceeded the threshold are captured in TISCR[ASITE]. + */ +#define TMU_TIDR_ATTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATTE_SHIFT)) & TMU_TIDR_ATTE_MASK) + +#define TMU_TIDR_ITTE_MASK (0x80000000U) +#define TMU_TIDR_ITTE_SHIFT (31U) +/*! ITTE + * 0b0..No threshold exceeded. + * 0b1..Immediate temperature threshold, as defined by TMHTITR, has been exceeded by one or more monitored sites. + * This includes an out-of-range measured temperature above 125degree C. The sites which has exceeded the + * threshold are captured in TISCR[ISITE]. + */ +#define TMU_TIDR_ITTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ITTE_SHIFT)) & TMU_TIDR_ITTE_MASK) +/*! @} */ + +/*! @name TISCR - TMU Interrupt Site Capture register */ +/*! @{ */ + +#define TMU_TISCR_ASITE_MASK (0xFFFFU) +#define TMU_TISCR_ASITE_SHIFT (0U) +#define TMU_TISCR_ASITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TISCR_ASITE_SHIFT)) & TMU_TISCR_ASITE_MASK) + +#define TMU_TISCR_ISITE_MASK (0xFFFF0000U) +#define TMU_TISCR_ISITE_SHIFT (16U) +#define TMU_TISCR_ISITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TISCR_ISITE_SHIFT)) & TMU_TISCR_ISITE_MASK) +/*! @} */ + +/*! @name TICSCR - TMU Interrupt Critical Site Capture register */ +/*! @{ */ + +#define TMU_TICSCR_CASITE_MASK (0xFFFFU) +#define TMU_TICSCR_CASITE_SHIFT (0U) +#define TMU_TICSCR_CASITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TICSCR_CASITE_SHIFT)) & TMU_TICSCR_CASITE_MASK) +/*! @} */ + +/*! @name TMHTCRH - TMU Monitor High Temperature Capture register */ +/*! @{ */ + +#define TMU_TMHTCRH_TEMP_MASK (0xFFU) +#define TMU_TMHTCRH_TEMP_SHIFT (0U) +#define TMU_TMHTCRH_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCRH_TEMP_SHIFT)) & TMU_TMHTCRH_TEMP_MASK) + +#define TMU_TMHTCRH_V_MASK (0x80000000U) +#define TMU_TMHTCRH_V_SHIFT (31U) +/*! V + * 0b0..Temperature reading is not valid due to no measured temperature within the sensor range of 0-125 degree C for an enabled monitored site. + * 0b1..Temperature reading is valid. + */ +#define TMU_TMHTCRH_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCRH_V_SHIFT)) & TMU_TMHTCRH_V_MASK) +/*! @} */ + +/*! @name TMHTCRL - TMU Monitor Low Temperature Capture register */ +/*! @{ */ + +#define TMU_TMHTCRL_TEMP_MASK (0xFFU) +#define TMU_TMHTCRL_TEMP_SHIFT (0U) +#define TMU_TMHTCRL_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCRL_TEMP_SHIFT)) & TMU_TMHTCRL_TEMP_MASK) + +#define TMU_TMHTCRL_V_MASK (0x80000000U) +#define TMU_TMHTCRL_V_SHIFT (31U) +/*! V + * 0b0..Temperature reading is not valid due to no measured temperature within the sensor range of 0-125 degree C for an enabled monitored site. + * 0b1..Temperature reading is valid. + */ +#define TMU_TMHTCRL_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCRL_V_SHIFT)) & TMU_TMHTCRL_V_MASK) +/*! @} */ + +/*! @name TMHTITR - TMU Monitor High Temperature Immediate Threshold register */ +/*! @{ */ + +#define TMU_TMHTITR_TEMP_MASK (0xFFU) +#define TMU_TMHTITR_TEMP_SHIFT (0U) +#define TMU_TMHTITR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_TEMP_SHIFT)) & TMU_TMHTITR_TEMP_MASK) + +#define TMU_TMHTITR_EN_MASK (0x80000000U) +#define TMU_TMHTITR_EN_SHIFT (31U) +/*! EN + * 0b0..Disabled. + * 0b1..Threshold enabled. + */ +#define TMU_TMHTITR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_EN_SHIFT)) & TMU_TMHTITR_EN_MASK) +/*! @} */ + +/*! @name TMHTATR - TMU Monitor High Temperature Average threshold register */ +/*! @{ */ + +#define TMU_TMHTATR_TEMP_MASK (0xFFU) +#define TMU_TMHTATR_TEMP_SHIFT (0U) +#define TMU_TMHTATR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_TEMP_SHIFT)) & TMU_TMHTATR_TEMP_MASK) + +#define TMU_TMHTATR_EN_MASK (0x80000000U) +#define TMU_TMHTATR_EN_SHIFT (31U) +/*! EN + * 0b0..Disabled. + * 0b1..Threshold enabled. + */ +#define TMU_TMHTATR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_EN_SHIFT)) & TMU_TMHTATR_EN_MASK) +/*! @} */ + +/*! @name TMHTACTR - TMU Monitor High Temperature Average Critical Threshold register */ +/*! @{ */ + +#define TMU_TMHTACTR_TEMP_MASK (0xFFU) +#define TMU_TMHTACTR_TEMP_SHIFT (0U) +#define TMU_TMHTACTR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_TEMP_SHIFT)) & TMU_TMHTACTR_TEMP_MASK) + +#define TMU_TMHTACTR_EN_MASK (0x80000000U) +#define TMU_TMHTACTR_EN_SHIFT (31U) +/*! EN + * 0b0..Disabled. + * 0b1..Threshold enabled. + */ +#define TMU_TMHTACTR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_EN_SHIFT)) & TMU_TMHTACTR_EN_MASK) +/*! @} */ + +/*! @name TTCFGR - TMU Temperature Configuration register */ +/*! @{ */ + +#define TMU_TTCFGR_DATA_MASK (0xFFFFFFFFU) +#define TMU_TTCFGR_DATA_SHIFT (0U) +#define TMU_TTCFGR_DATA(x) (((uint32_t)(((uint32_t)(x)) << TMU_TTCFGR_DATA_SHIFT)) & TMU_TTCFGR_DATA_MASK) +/*! @} */ + +/*! @name TSCFGR - TMU Sensor Configuration register */ +/*! @{ */ + +#define TMU_TSCFGR_DATA_MASK (0xFFFFFFFFU) +#define TMU_TSCFGR_DATA_SHIFT (0U) +#define TMU_TSCFGR_DATA(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSCFGR_DATA_SHIFT)) & TMU_TSCFGR_DATA_MASK) +/*! @} */ + +/*! @name TRITSR - TMU Report Immediate Temperature Site register n */ +/*! @{ */ + +#define TMU_TRITSR_TEMP_MASK (0xFFU) +#define TMU_TRITSR_TEMP_SHIFT (0U) +#define TMU_TRITSR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_TEMP_SHIFT)) & TMU_TRITSR_TEMP_MASK) + +#define TMU_TRITSR_V_MASK (0x80000000U) +#define TMU_TRITSR_V_SHIFT (31U) +/*! V + * 0b0..Not valid. Temperature out of sensor range or first measurement still pending. + * 0b1..Valid. + */ +#define TMU_TRITSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_V_SHIFT)) & TMU_TRITSR_V_MASK) +/*! @} */ + +/* The count of TMU_TRITSR */ +#define TMU_TRITSR_COUNT (16U) + +/*! @name TRATSR - TMU Report Average Temperature Site register n */ +/*! @{ */ + +#define TMU_TRATSR_TEMP_MASK (0xFFU) +#define TMU_TRATSR_TEMP_SHIFT (0U) +#define TMU_TRATSR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_TEMP_SHIFT)) & TMU_TRATSR_TEMP_MASK) + +#define TMU_TRATSR_V_MASK (0x80000000U) +#define TMU_TRATSR_V_SHIFT (31U) +/*! V + * 0b0..Not valid. Temperature out of sensor range or first measurement still pending. + * 0b1..Valid. + */ +#define TMU_TRATSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_V_SHIFT)) & TMU_TRATSR_V_MASK) +/*! @} */ + +/* The count of TMU_TRATSR */ +#define TMU_TRATSR_COUNT (16U) + +/*! @name IPBRR0 - IP Block Revision register 0 */ +/*! @{ */ + +#define TMU_IPBRR0_IP_MN_MASK (0xFFU) +#define TMU_IPBRR0_IP_MN_SHIFT (0U) +#define TMU_IPBRR0_IP_MN(x) (((uint32_t)(((uint32_t)(x)) << TMU_IPBRR0_IP_MN_SHIFT)) & TMU_IPBRR0_IP_MN_MASK) + +#define TMU_IPBRR0_IP_MJ_MASK (0xFF00U) +#define TMU_IPBRR0_IP_MJ_SHIFT (8U) +#define TMU_IPBRR0_IP_MJ(x) (((uint32_t)(((uint32_t)(x)) << TMU_IPBRR0_IP_MJ_SHIFT)) & TMU_IPBRR0_IP_MJ_MASK) + +#define TMU_IPBRR0_IP_ID_MASK (0xFFFF0000U) +#define TMU_IPBRR0_IP_ID_SHIFT (16U) +#define TMU_IPBRR0_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TMU_IPBRR0_IP_ID_SHIFT)) & TMU_IPBRR0_IP_ID_MASK) +/*! @} */ + +/*! @name TTRCR - TMU Temperature Range n Control register */ +/*! @{ */ + +#define TMU_TTRCR_TEMP_MASK (0xFFU) +#define TMU_TTRCR_TEMP_SHIFT (0U) +#define TMU_TTRCR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TTRCR_TEMP_SHIFT)) & TMU_TTRCR_TEMP_MASK) + +#define TMU_TTRCR_CAL_PTS_MASK (0xF0000U) +#define TMU_TTRCR_CAL_PTS_SHIFT (16U) +#define TMU_TTRCR_CAL_PTS(x) (((uint32_t)(((uint32_t)(x)) << TMU_TTRCR_CAL_PTS_SHIFT)) & TMU_TTRCR_CAL_PTS_MASK) +/*! @} */ + +/* The count of TMU_TTRCR */ +#define TMU_TTRCR_COUNT (4U) + + +/*! + * @} + */ /* end of group TMU_Register_Masks */ + + +/* TMU - Peripheral instance base addresses */ +/** Peripheral TMU base address */ +#define TMU_BASE (0x30260000u) +/** Peripheral TMU base pointer */ +#define TMU ((TMU_Type *)TMU_BASE) +/** Array initializer of TMU peripheral base addresses */ +#define TMU_BASE_ADDRS { TMU_BASE } +/** Array initializer of TMU peripheral base pointers */ +#define TMU_BASE_PTRS { TMU } + +/*! + * @} + */ /* end of group TMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer + * @{ + */ + +/** UART - Register Layout Typedef */ +typedef struct { + __I uint32_t URXD; /**< UART Receiver Register, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __O uint32_t UTXD; /**< UART Transmitter Register, offset: 0x40 */ + uint8_t RESERVED_1[60]; + __IO uint32_t UCR1; /**< UART Control Register 1, offset: 0x80 */ + __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ + __IO uint32_t UCR3; /**< UART Control Register 3, offset: 0x88 */ + __IO uint32_t UCR4; /**< UART Control Register 4, offset: 0x8C */ + __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ + __IO uint32_t USR1; /**< UART Status Register 1, offset: 0x94 */ + __IO uint32_t USR2; /**< UART Status Register 2, offset: 0x98 */ + __IO uint32_t UESC; /**< UART Escape Character Register, offset: 0x9C */ + __IO uint32_t UTIM; /**< UART Escape Timer Register, offset: 0xA0 */ + __IO uint32_t UBIR; /**< UART BRM Incremental Register, offset: 0xA4 */ + __IO uint32_t UBMR; /**< UART BRM Modulator Register, offset: 0xA8 */ + __I uint32_t UBRC; /**< UART Baud Rate Count Register, offset: 0xAC */ + __IO uint32_t ONEMS; /**< UART One Millisecond Register, offset: 0xB0 */ + __IO uint32_t UTS; /**< UART Test Register, offset: 0xB4 */ + __IO uint32_t UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 */ +} UART_Type; + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/*! @name URXD - UART Receiver Register */ +/*! @{ */ + +#define UART_URXD_RX_DATA_MASK (0xFFU) +#define UART_URXD_RX_DATA_SHIFT (0U) +#define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_RX_DATA_SHIFT)) & UART_URXD_RX_DATA_MASK) + +#define UART_URXD_PRERR_MASK (0x400U) +#define UART_URXD_PRERR_SHIFT (10U) +/*! PRERR + * 0b0..= No parity error was detected for data in the RX_DATA field + * 0b1..= A parity error was detected for data in the RX_DATA field + */ +#define UART_URXD_PRERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_PRERR_SHIFT)) & UART_URXD_PRERR_MASK) + +#define UART_URXD_BRK_MASK (0x800U) +#define UART_URXD_BRK_SHIFT (11U) +/*! BRK + * 0b0..The current character is not a BREAK character + * 0b1..The current character is a BREAK character + */ +#define UART_URXD_BRK(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_BRK_SHIFT)) & UART_URXD_BRK_MASK) + +#define UART_URXD_FRMERR_MASK (0x1000U) +#define UART_URXD_FRMERR_SHIFT (12U) +/*! FRMERR + * 0b0..The current character has no framing error + * 0b1..The current character has a framing error + */ +#define UART_URXD_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_FRMERR_SHIFT)) & UART_URXD_FRMERR_MASK) + +#define UART_URXD_OVRRUN_MASK (0x2000U) +#define UART_URXD_OVRRUN_SHIFT (13U) +/*! OVRRUN + * 0b0..No RxFIFO overrun was detected + * 0b1..A RxFIFO overrun was detected + */ +#define UART_URXD_OVRRUN(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_OVRRUN_SHIFT)) & UART_URXD_OVRRUN_MASK) + +#define UART_URXD_ERR_MASK (0x4000U) +#define UART_URXD_ERR_SHIFT (14U) +/*! ERR + * 0b0..No error status was detected + * 0b1..An error status was detected + */ +#define UART_URXD_ERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_ERR_SHIFT)) & UART_URXD_ERR_MASK) + +#define UART_URXD_CHARRDY_MASK (0x8000U) +#define UART_URXD_CHARRDY_SHIFT (15U) +/*! CHARRDY + * 0b0..Character in RX_DATA field and associated flags are invalid. + * 0b1..Character in RX_DATA field and associated flags valid and ready for reading. + */ +#define UART_URXD_CHARRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_CHARRDY_SHIFT)) & UART_URXD_CHARRDY_MASK) +/*! @} */ + +/*! @name UTXD - UART Transmitter Register */ +/*! @{ */ + +#define UART_UTXD_TX_DATA_MASK (0xFFU) +#define UART_UTXD_TX_DATA_SHIFT (0U) +#define UART_UTXD_TX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_UTXD_TX_DATA_SHIFT)) & UART_UTXD_TX_DATA_MASK) +/*! @} */ + +/*! @name UCR1 - UART Control Register 1 */ +/*! @{ */ + +#define UART_UCR1_UARTEN_MASK (0x1U) +#define UART_UCR1_UARTEN_SHIFT (0U) +/*! UARTEN + * 0b0..Disable the UART + * 0b1..Enable the UART + */ +#define UART_UCR1_UARTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_UARTEN_SHIFT)) & UART_UCR1_UARTEN_MASK) + +#define UART_UCR1_DOZE_MASK (0x2U) +#define UART_UCR1_DOZE_SHIFT (1U) +/*! DOZE + * 0b0..The UART is enabled when in DOZE state + * 0b1..The UART is disabled when in DOZE state + */ +#define UART_UCR1_DOZE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_DOZE_SHIFT)) & UART_UCR1_DOZE_MASK) + +#define UART_UCR1_ATDMAEN_MASK (0x4U) +#define UART_UCR1_ATDMAEN_SHIFT (2U) +/*! ATDMAEN + * 0b0..Disable AGTIM DMA request + * 0b1..Enable AGTIM DMA request + */ +#define UART_UCR1_ATDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ATDMAEN_SHIFT)) & UART_UCR1_ATDMAEN_MASK) + +#define UART_UCR1_TXDMAEN_MASK (0x8U) +#define UART_UCR1_TXDMAEN_SHIFT (3U) +/*! TXDMAEN + * 0b0..Disable transmit DMA request + * 0b1..Enable transmit DMA request + */ +#define UART_UCR1_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXDMAEN_SHIFT)) & UART_UCR1_TXDMAEN_MASK) + +#define UART_UCR1_SNDBRK_MASK (0x10U) +#define UART_UCR1_SNDBRK_SHIFT (4U) +/*! SNDBRK + * 0b0..Do not send a BREAK character + * 0b1..Send a BREAK character (continuous 0s) + */ +#define UART_UCR1_SNDBRK(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_SNDBRK_SHIFT)) & UART_UCR1_SNDBRK_MASK) + +#define UART_UCR1_RTSDEN_MASK (0x20U) +#define UART_UCR1_RTSDEN_SHIFT (5U) +/*! RTSDEN + * 0b0..Disable RTSD interrupt + * 0b1..Enable RTSD interrupt + */ +#define UART_UCR1_RTSDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RTSDEN_SHIFT)) & UART_UCR1_RTSDEN_MASK) + +#define UART_UCR1_TXMPTYEN_MASK (0x40U) +#define UART_UCR1_TXMPTYEN_SHIFT (6U) +/*! TXMPTYEN + * 0b0..Disable the transmitter FIFO empty interrupt + * 0b1..Enable the transmitter FIFO empty interrupt + */ +#define UART_UCR1_TXMPTYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXMPTYEN_SHIFT)) & UART_UCR1_TXMPTYEN_MASK) + +#define UART_UCR1_IREN_MASK (0x80U) +#define UART_UCR1_IREN_SHIFT (7U) +/*! IREN + * 0b0..Disable the IR interface + * 0b1..Enable the IR interface + */ +#define UART_UCR1_IREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IREN_SHIFT)) & UART_UCR1_IREN_MASK) + +#define UART_UCR1_RXDMAEN_MASK (0x100U) +#define UART_UCR1_RXDMAEN_SHIFT (8U) +/*! RXDMAEN + * 0b0..Disable DMA request + * 0b1..Enable DMA request + */ +#define UART_UCR1_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RXDMAEN_SHIFT)) & UART_UCR1_RXDMAEN_MASK) + +#define UART_UCR1_RRDYEN_MASK (0x200U) +#define UART_UCR1_RRDYEN_SHIFT (9U) +/*! RRDYEN + * 0b0..Disables the RRDY interrupt + * 0b1..Enables the RRDY interrupt + */ +#define UART_UCR1_RRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RRDYEN_SHIFT)) & UART_UCR1_RRDYEN_MASK) + +#define UART_UCR1_ICD_MASK (0xC00U) +#define UART_UCR1_ICD_SHIFT (10U) +/*! ICD + * 0b00..Idle for more than 4 frames + * 0b01..Idle for more than 8 frames + * 0b10..Idle for more than 16 frames + * 0b11..Idle for more than 32 frames + */ +#define UART_UCR1_ICD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ICD_SHIFT)) & UART_UCR1_ICD_MASK) + +#define UART_UCR1_IDEN_MASK (0x1000U) +#define UART_UCR1_IDEN_SHIFT (12U) +/*! IDEN + * 0b0..Disable the IDLE interrupt + * 0b1..Enable the IDLE interrupt + */ +#define UART_UCR1_IDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IDEN_SHIFT)) & UART_UCR1_IDEN_MASK) + +#define UART_UCR1_TRDYEN_MASK (0x2000U) +#define UART_UCR1_TRDYEN_SHIFT (13U) +/*! TRDYEN + * 0b0..Disable the transmitter ready interrupt + * 0b1..Enable the transmitter ready interrupt + */ +#define UART_UCR1_TRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TRDYEN_SHIFT)) & UART_UCR1_TRDYEN_MASK) + +#define UART_UCR1_ADBR_MASK (0x4000U) +#define UART_UCR1_ADBR_SHIFT (14U) +/*! ADBR + * 0b0..Disable automatic detection of baud rate + * 0b1..Enable automatic detection of baud rate + */ +#define UART_UCR1_ADBR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADBR_SHIFT)) & UART_UCR1_ADBR_MASK) + +#define UART_UCR1_ADEN_MASK (0x8000U) +#define UART_UCR1_ADEN_SHIFT (15U) +/*! ADEN + * 0b0..Disable the automatic baud rate detection interrupt + * 0b1..Enable the automatic baud rate detection interrupt + */ +#define UART_UCR1_ADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADEN_SHIFT)) & UART_UCR1_ADEN_MASK) +/*! @} */ + +/*! @name UCR2 - UART Control Register 2 */ +/*! @{ */ + +#define UART_UCR2_SRST_MASK (0x1U) +#define UART_UCR2_SRST_SHIFT (0U) +/*! SRST + * 0b0..Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3]. + * 0b1..No reset + */ +#define UART_UCR2_SRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_SRST_SHIFT)) & UART_UCR2_SRST_MASK) + +#define UART_UCR2_RXEN_MASK (0x2U) +#define UART_UCR2_RXEN_SHIFT (1U) +/*! RXEN + * 0b0..Disable the receiver + * 0b1..Enable the receiver + */ +#define UART_UCR2_RXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RXEN_SHIFT)) & UART_UCR2_RXEN_MASK) + +#define UART_UCR2_TXEN_MASK (0x4U) +#define UART_UCR2_TXEN_SHIFT (2U) +/*! TXEN + * 0b0..Disable the transmitter + * 0b1..Enable the transmitter + */ +#define UART_UCR2_TXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_TXEN_SHIFT)) & UART_UCR2_TXEN_MASK) + +#define UART_UCR2_ATEN_MASK (0x8U) +#define UART_UCR2_ATEN_SHIFT (3U) +/*! ATEN + * 0b0..AGTIM interrupt disabled + * 0b1..AGTIM interrupt enabled + */ +#define UART_UCR2_ATEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ATEN_SHIFT)) & UART_UCR2_ATEN_MASK) + +#define UART_UCR2_RTSEN_MASK (0x10U) +#define UART_UCR2_RTSEN_SHIFT (4U) +/*! RTSEN + * 0b0..Disable request to send interrupt + * 0b1..Enable request to send interrupt + */ +#define UART_UCR2_RTSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTSEN_SHIFT)) & UART_UCR2_RTSEN_MASK) + +#define UART_UCR2_WS_MASK (0x20U) +#define UART_UCR2_WS_SHIFT (5U) +/*! WS + * 0b0..7-bit transmit and receive character length (not including START, STOP or PARITY bits) + * 0b1..8-bit transmit and receive character length (not including START, STOP or PARITY bits) + */ +#define UART_UCR2_WS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_WS_SHIFT)) & UART_UCR2_WS_MASK) + +#define UART_UCR2_STPB_MASK (0x40U) +#define UART_UCR2_STPB_SHIFT (6U) +/*! STPB + * 0b0..The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits. + * 0b1..The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits. + */ +#define UART_UCR2_STPB(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_STPB_SHIFT)) & UART_UCR2_STPB_MASK) + +#define UART_UCR2_PROE_MASK (0x80U) +#define UART_UCR2_PROE_SHIFT (7U) +/*! PROE + * 0b0..Even parity + * 0b1..Odd parity + */ +#define UART_UCR2_PROE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PROE_SHIFT)) & UART_UCR2_PROE_MASK) + +#define UART_UCR2_PREN_MASK (0x100U) +#define UART_UCR2_PREN_SHIFT (8U) +/*! PREN + * 0b0..Disable parity generator and checker + * 0b1..Enable parity generator and checker + */ +#define UART_UCR2_PREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PREN_SHIFT)) & UART_UCR2_PREN_MASK) + +#define UART_UCR2_RTEC_MASK (0x600U) +#define UART_UCR2_RTEC_SHIFT (9U) +/*! RTEC + * 0b00..Trigger interrupt on a rising edge + * 0b01..Trigger interrupt on a falling edge + * 0b1x..Trigger interrupt on any edge + */ +#define UART_UCR2_RTEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTEC_SHIFT)) & UART_UCR2_RTEC_MASK) + +#define UART_UCR2_ESCEN_MASK (0x800U) +#define UART_UCR2_ESCEN_SHIFT (11U) +/*! ESCEN + * 0b0..Disable escape sequence detection + * 0b1..Enable escape sequence detection + */ +#define UART_UCR2_ESCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCEN_SHIFT)) & UART_UCR2_ESCEN_MASK) + +#define UART_UCR2_CTS_MASK (0x1000U) +#define UART_UCR2_CTS_SHIFT (12U) +/*! CTS + * 0b0..The CTS_B pin is high (inactive) + * 0b1..The CTS_B pin is low (active) + */ +#define UART_UCR2_CTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTS_SHIFT)) & UART_UCR2_CTS_MASK) + +#define UART_UCR2_CTSC_MASK (0x2000U) +#define UART_UCR2_CTSC_SHIFT (13U) +/*! CTSC + * 0b0..The CTS_B pin is controlled by the CTS bit + * 0b1..The CTS_B pin is controlled by the receiver + */ +#define UART_UCR2_CTSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTSC_SHIFT)) & UART_UCR2_CTSC_MASK) + +#define UART_UCR2_IRTS_MASK (0x4000U) +#define UART_UCR2_IRTS_SHIFT (14U) +/*! IRTS + * 0b0..Transmit only when the RTS pin is asserted + * 0b1..Ignore the RTS pin + */ +#define UART_UCR2_IRTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_IRTS_SHIFT)) & UART_UCR2_IRTS_MASK) + +#define UART_UCR2_ESCI_MASK (0x8000U) +#define UART_UCR2_ESCI_SHIFT (15U) +/*! ESCI + * 0b0..Disable the escape sequence interrupt + * 0b1..Enable the escape sequence interrupt + */ +#define UART_UCR2_ESCI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCI_SHIFT)) & UART_UCR2_ESCI_MASK) +/*! @} */ + +/*! @name UCR3 - UART Control Register 3 */ +/*! @{ */ + +#define UART_UCR3_ACIEN_MASK (0x1U) +#define UART_UCR3_ACIEN_SHIFT (0U) +/*! ACIEN + * 0b0..ACST interrupt disabled + * 0b1..ACST interrupt enabled + */ +#define UART_UCR3_ACIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ACIEN_SHIFT)) & UART_UCR3_ACIEN_MASK) + +#define UART_UCR3_INVT_MASK (0x2U) +#define UART_UCR3_INVT_SHIFT (1U) +/*! INVT + * 0b0..TXD is not inverted + * 0b1..TXD is inverted + * 0b0..TXD Active low transmission + * 0b1..TXD Active high transmission + */ +#define UART_UCR3_INVT(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_INVT_SHIFT)) & UART_UCR3_INVT_MASK) + +#define UART_UCR3_RXDMUXSEL_MASK (0x4U) +#define UART_UCR3_RXDMUXSEL_SHIFT (2U) +#define UART_UCR3_RXDMUXSEL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDMUXSEL_SHIFT)) & UART_UCR3_RXDMUXSEL_MASK) + +#define UART_UCR3_DTRDEN_MASK (0x8U) +#define UART_UCR3_DTRDEN_SHIFT (3U) +#define UART_UCR3_DTRDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTRDEN_SHIFT)) & UART_UCR3_DTRDEN_MASK) + +#define UART_UCR3_AWAKEN_MASK (0x10U) +#define UART_UCR3_AWAKEN_SHIFT (4U) +/*! AWAKEN + * 0b0..Disable the AWAKE interrupt + * 0b1..Enable the AWAKE interrupt + */ +#define UART_UCR3_AWAKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AWAKEN_SHIFT)) & UART_UCR3_AWAKEN_MASK) + +#define UART_UCR3_AIRINTEN_MASK (0x20U) +#define UART_UCR3_AIRINTEN_SHIFT (5U) +/*! AIRINTEN + * 0b0..Disable the AIRINT interrupt + * 0b1..Enable the AIRINT interrupt + */ +#define UART_UCR3_AIRINTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AIRINTEN_SHIFT)) & UART_UCR3_AIRINTEN_MASK) + +#define UART_UCR3_RXDSEN_MASK (0x40U) +#define UART_UCR3_RXDSEN_SHIFT (6U) +/*! RXDSEN + * 0b0..Disable the RXDS interrupt + * 0b1..Enable the RXDS interrupt + */ +#define UART_UCR3_RXDSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDSEN_SHIFT)) & UART_UCR3_RXDSEN_MASK) + +#define UART_UCR3_ADNIMP_MASK (0x80U) +#define UART_UCR3_ADNIMP_SHIFT (7U) +/*! ADNIMP + * 0b0..Autobaud detection new features selected + * 0b1..Keep old autobaud detection mechanism + */ +#define UART_UCR3_ADNIMP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ADNIMP_SHIFT)) & UART_UCR3_ADNIMP_MASK) + +#define UART_UCR3_RI_MASK (0x100U) +#define UART_UCR3_RI_SHIFT (8U) +#define UART_UCR3_RI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RI_SHIFT)) & UART_UCR3_RI_MASK) + +#define UART_UCR3_DCD_MASK (0x200U) +#define UART_UCR3_DCD_SHIFT (9U) +#define UART_UCR3_DCD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DCD_SHIFT)) & UART_UCR3_DCD_MASK) + +#define UART_UCR3_DSR_MASK (0x400U) +#define UART_UCR3_DSR_SHIFT (10U) +#define UART_UCR3_DSR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DSR_SHIFT)) & UART_UCR3_DSR_MASK) + +#define UART_UCR3_FRAERREN_MASK (0x800U) +#define UART_UCR3_FRAERREN_SHIFT (11U) +/*! FRAERREN + * 0b0..Disable the frame error interrupt + * 0b1..Enable the frame error interrupt + */ +#define UART_UCR3_FRAERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_FRAERREN_SHIFT)) & UART_UCR3_FRAERREN_MASK) + +#define UART_UCR3_PARERREN_MASK (0x1000U) +#define UART_UCR3_PARERREN_SHIFT (12U) +/*! PARERREN + * 0b0..Disable the parity error interrupt + * 0b1..Enable the parity error interrupt + */ +#define UART_UCR3_PARERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_PARERREN_SHIFT)) & UART_UCR3_PARERREN_MASK) + +#define UART_UCR3_DTREN_MASK (0x2000U) +#define UART_UCR3_DTREN_SHIFT (13U) +#define UART_UCR3_DTREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTREN_SHIFT)) & UART_UCR3_DTREN_MASK) + +#define UART_UCR3_DPEC_MASK (0xC000U) +#define UART_UCR3_DPEC_SHIFT (14U) +#define UART_UCR3_DPEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DPEC_SHIFT)) & UART_UCR3_DPEC_MASK) +/*! @} */ + +/*! @name UCR4 - UART Control Register 4 */ +/*! @{ */ + +#define UART_UCR4_DREN_MASK (0x1U) +#define UART_UCR4_DREN_SHIFT (0U) +/*! DREN + * 0b0..Disable RDR interrupt + * 0b1..Enable RDR interrupt + */ +#define UART_UCR4_DREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_DREN_SHIFT)) & UART_UCR4_DREN_MASK) + +#define UART_UCR4_OREN_MASK (0x2U) +#define UART_UCR4_OREN_SHIFT (1U) +/*! OREN + * 0b0..Disable ORE interrupt + * 0b1..Enable ORE interrupt + */ +#define UART_UCR4_OREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_OREN_SHIFT)) & UART_UCR4_OREN_MASK) + +#define UART_UCR4_BKEN_MASK (0x4U) +#define UART_UCR4_BKEN_SHIFT (2U) +/*! BKEN + * 0b0..Disable the BRCD interrupt + * 0b1..Enable the BRCD interrupt + */ +#define UART_UCR4_BKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_BKEN_SHIFT)) & UART_UCR4_BKEN_MASK) + +#define UART_UCR4_TCEN_MASK (0x8U) +#define UART_UCR4_TCEN_SHIFT (3U) +/*! TCEN + * 0b0..Disable TXDC interrupt + * 0b1..Enable TXDC interrupt + */ +#define UART_UCR4_TCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_TCEN_SHIFT)) & UART_UCR4_TCEN_MASK) + +#define UART_UCR4_LPBYP_MASK (0x10U) +#define UART_UCR4_LPBYP_SHIFT (4U) +/*! LPBYP + * 0b0..Low power features enabled + * 0b1..Low power features disabled + */ +#define UART_UCR4_LPBYP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_LPBYP_SHIFT)) & UART_UCR4_LPBYP_MASK) + +#define UART_UCR4_IRSC_MASK (0x20U) +#define UART_UCR4_IRSC_SHIFT (5U) +/*! IRSC + * 0b0..The vote logic uses the sampling clock (16x baud rate) for normal operation + * 0b1..The vote logic uses the UART reference clock + */ +#define UART_UCR4_IRSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IRSC_SHIFT)) & UART_UCR4_IRSC_MASK) + +#define UART_UCR4_IDDMAEN_MASK (0x40U) +#define UART_UCR4_IDDMAEN_SHIFT (6U) +/*! IDDMAEN + * 0b0..DMA IDLE interrupt disabled + * 0b1..DMA IDLE interrupt enabled + */ +#define UART_UCR4_IDDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IDDMAEN_SHIFT)) & UART_UCR4_IDDMAEN_MASK) + +#define UART_UCR4_WKEN_MASK (0x80U) +#define UART_UCR4_WKEN_SHIFT (7U) +/*! WKEN + * 0b0..Disable the WAKE interrupt + * 0b1..Enable the WAKE interrupt + */ +#define UART_UCR4_WKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_WKEN_SHIFT)) & UART_UCR4_WKEN_MASK) + +#define UART_UCR4_ENIRI_MASK (0x100U) +#define UART_UCR4_ENIRI_SHIFT (8U) +/*! ENIRI + * 0b0..Serial infrared Interrupt disabled + * 0b1..Serial infrared Interrupt enabled + */ +#define UART_UCR4_ENIRI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_ENIRI_SHIFT)) & UART_UCR4_ENIRI_MASK) + +#define UART_UCR4_INVR_MASK (0x200U) +#define UART_UCR4_INVR_SHIFT (9U) +/*! INVR + * 0b0..RXD input is not inverted + * 0b1..RXD input is inverted + * 0b0..RXD active low detection + * 0b1..RXD active high detection + */ +#define UART_UCR4_INVR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_INVR_SHIFT)) & UART_UCR4_INVR_MASK) + +#define UART_UCR4_CTSTL_MASK (0xFC00U) +#define UART_UCR4_CTSTL_SHIFT (10U) +/*! CTSTL + * 0b000000..0 characters received + * 0b000001..1 characters in the RxFIFO + * 0b100000..32 characters in the RxFIFO (maximum) + */ +#define UART_UCR4_CTSTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_CTSTL_SHIFT)) & UART_UCR4_CTSTL_MASK) +/*! @} */ + +/*! @name UFCR - UART FIFO Control Register */ +/*! @{ */ + +#define UART_UFCR_RXTL_MASK (0x3FU) +#define UART_UFCR_RXTL_SHIFT (0U) +/*! RXTL + * 0b000000..0 characters received + * 0b000001..RxFIFO has 1 character + * 0b011111..RxFIFO has 31 characters + * 0b100000..RxFIFO has 32 characters (maximum) + */ +#define UART_UFCR_RXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RXTL_SHIFT)) & UART_UFCR_RXTL_MASK) + +#define UART_UFCR_DCEDTE_MASK (0x40U) +#define UART_UFCR_DCEDTE_SHIFT (6U) +/*! DCEDTE + * 0b0..DCE mode selected + * 0b1..DTE mode selected + */ +#define UART_UFCR_DCEDTE(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_DCEDTE_SHIFT)) & UART_UFCR_DCEDTE_MASK) + +#define UART_UFCR_RFDIV_MASK (0x380U) +#define UART_UFCR_RFDIV_SHIFT (7U) +/*! RFDIV + * 0b000..Divide input clock by 6 + * 0b001..Divide input clock by 5 + * 0b010..Divide input clock by 4 + * 0b011..Divide input clock by 3 + * 0b100..Divide input clock by 2 + * 0b101..Divide input clock by 1 + * 0b110..Divide input clock by 7 + * 0b111..Reserved + */ +#define UART_UFCR_RFDIV(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RFDIV_SHIFT)) & UART_UFCR_RFDIV_MASK) + +#define UART_UFCR_TXTL_MASK (0xFC00U) +#define UART_UFCR_TXTL_SHIFT (10U) +/*! TXTL + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..TxFIFO has 2 or fewer characters + * 0b011111..TxFIFO has 31 or fewer characters + * 0b100000..TxFIFO has 32 characters (maximum) + */ +#define UART_UFCR_TXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_TXTL_SHIFT)) & UART_UFCR_TXTL_MASK) +/*! @} */ + +/*! @name USR1 - UART Status Register 1 */ +/*! @{ */ + +#define UART_USR1_SAD_MASK (0x8U) +#define UART_USR1_SAD_SHIFT (3U) +/*! SAD + * 0b0..No slave address detected + * 0b1..Slave address detected + */ +#define UART_USR1_SAD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_SAD_SHIFT)) & UART_USR1_SAD_MASK) + +#define UART_USR1_AWAKE_MASK (0x10U) +#define UART_USR1_AWAKE_SHIFT (4U) +/*! AWAKE + * 0b0..No falling edge was detected on the RXD Serial pin + * 0b1..A falling edge was detected on the RXD Serial pin + */ +#define UART_USR1_AWAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AWAKE_SHIFT)) & UART_USR1_AWAKE_MASK) + +#define UART_USR1_AIRINT_MASK (0x20U) +#define UART_USR1_AIRINT_SHIFT (5U) +/*! AIRINT + * 0b0..No pulse was detected on the RXD IrDA pin + * 0b1..A pulse was detected on the RXD IrDA pin + */ +#define UART_USR1_AIRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AIRINT_SHIFT)) & UART_USR1_AIRINT_MASK) + +#define UART_USR1_RXDS_MASK (0x40U) +#define UART_USR1_RXDS_SHIFT (6U) +/*! RXDS + * 0b0..Receive in progress + * 0b1..Receiver is IDLE + */ +#define UART_USR1_RXDS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RXDS_SHIFT)) & UART_USR1_RXDS_MASK) + +#define UART_USR1_DTRD_MASK (0x80U) +#define UART_USR1_DTRD_SHIFT (7U) +#define UART_USR1_DTRD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_DTRD_SHIFT)) & UART_USR1_DTRD_MASK) + +#define UART_USR1_AGTIM_MASK (0x100U) +#define UART_USR1_AGTIM_SHIFT (8U) +/*! AGTIM + * 0b0..AGTIM is not active + * 0b1..AGTIM is active (write 1 to clear) + */ +#define UART_USR1_AGTIM(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AGTIM_SHIFT)) & UART_USR1_AGTIM_MASK) + +#define UART_USR1_RRDY_MASK (0x200U) +#define UART_USR1_RRDY_SHIFT (9U) +/*! RRDY + * 0b0..No character ready + * 0b1..Character(s) ready (interrupt posted) + */ +#define UART_USR1_RRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RRDY_SHIFT)) & UART_USR1_RRDY_MASK) + +#define UART_USR1_FRAMERR_MASK (0x400U) +#define UART_USR1_FRAMERR_SHIFT (10U) +/*! FRAMERR + * 0b0..No frame error detected + * 0b1..Frame error detected (write 1 to clear) + */ +#define UART_USR1_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_FRAMERR_SHIFT)) & UART_USR1_FRAMERR_MASK) + +#define UART_USR1_ESCF_MASK (0x800U) +#define UART_USR1_ESCF_SHIFT (11U) +/*! ESCF + * 0b0..No escape sequence detected + * 0b1..Escape sequence detected (write 1 to clear). + */ +#define UART_USR1_ESCF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_ESCF_SHIFT)) & UART_USR1_ESCF_MASK) + +#define UART_USR1_RTSD_MASK (0x1000U) +#define UART_USR1_RTSD_SHIFT (12U) +/*! RTSD + * 0b0..RTS_B pin did not change state since last cleared + * 0b1..RTS_B pin changed state (write 1 to clear) + */ +#define UART_USR1_RTSD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSD_SHIFT)) & UART_USR1_RTSD_MASK) + +#define UART_USR1_TRDY_MASK (0x2000U) +#define UART_USR1_TRDY_SHIFT (13U) +/*! TRDY + * 0b0..The transmitter does not require data + * 0b1..The transmitter requires data (interrupt posted) + */ +#define UART_USR1_TRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_TRDY_SHIFT)) & UART_USR1_TRDY_MASK) + +#define UART_USR1_RTSS_MASK (0x4000U) +#define UART_USR1_RTSS_SHIFT (14U) +/*! RTSS + * 0b0..The RTS_B module input is high (inactive) + * 0b1..The RTS_B module input is low (active) + */ +#define UART_USR1_RTSS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSS_SHIFT)) & UART_USR1_RTSS_MASK) + +#define UART_USR1_PARITYERR_MASK (0x8000U) +#define UART_USR1_PARITYERR_SHIFT (15U) +/*! PARITYERR + * 0b0..No parity error detected + * 0b1..Parity error detected (write 1 to clear) + */ +#define UART_USR1_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_PARITYERR_SHIFT)) & UART_USR1_PARITYERR_MASK) +/*! @} */ + +/*! @name USR2 - UART Status Register 2 */ +/*! @{ */ + +#define UART_USR2_RDR_MASK (0x1U) +#define UART_USR2_RDR_SHIFT (0U) +/*! RDR + * 0b0..No receive data ready + * 0b1..Receive data ready + */ +#define UART_USR2_RDR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RDR_SHIFT)) & UART_USR2_RDR_MASK) + +#define UART_USR2_ORE_MASK (0x2U) +#define UART_USR2_ORE_SHIFT (1U) +/*! ORE + * 0b0..No overrun error + * 0b1..Overrun error (write 1 to clear) + */ +#define UART_USR2_ORE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ORE_SHIFT)) & UART_USR2_ORE_MASK) + +#define UART_USR2_BRCD_MASK (0x4U) +#define UART_USR2_BRCD_SHIFT (2U) +/*! BRCD + * 0b0..No BREAK condition was detected + * 0b1..A BREAK condition was detected (write 1 to clear) + */ +#define UART_USR2_BRCD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_BRCD_SHIFT)) & UART_USR2_BRCD_MASK) + +#define UART_USR2_TXDC_MASK (0x8U) +#define UART_USR2_TXDC_SHIFT (3U) +/*! TXDC + * 0b0..Transmit is incomplete + * 0b1..Transmit is complete + */ +#define UART_USR2_TXDC(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXDC_SHIFT)) & UART_USR2_TXDC_MASK) + +#define UART_USR2_RTSF_MASK (0x10U) +#define UART_USR2_RTSF_SHIFT (4U) +/*! RTSF + * 0b0..Programmed edge not detected on RTS_B + * 0b1..Programmed edge detected on RTS_B (write 1 to clear) + */ +#define UART_USR2_RTSF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RTSF_SHIFT)) & UART_USR2_RTSF_MASK) + +#define UART_USR2_DCDIN_MASK (0x20U) +#define UART_USR2_DCDIN_SHIFT (5U) +#define UART_USR2_DCDIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDIN_SHIFT)) & UART_USR2_DCDIN_MASK) + +#define UART_USR2_DCDDELT_MASK (0x40U) +#define UART_USR2_DCDDELT_SHIFT (6U) +#define UART_USR2_DCDDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDDELT_SHIFT)) & UART_USR2_DCDDELT_MASK) + +#define UART_USR2_WAKE_MASK (0x80U) +#define UART_USR2_WAKE_SHIFT (7U) +/*! WAKE + * 0b0..start bit not detected + * 0b1..start bit detected (write 1 to clear) + */ +#define UART_USR2_WAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_WAKE_SHIFT)) & UART_USR2_WAKE_MASK) + +#define UART_USR2_IRINT_MASK (0x100U) +#define UART_USR2_IRINT_SHIFT (8U) +/*! IRINT + * 0b0..no edge detected + * 0b1..valid edge detected (write 1 to clear) + */ +#define UART_USR2_IRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IRINT_SHIFT)) & UART_USR2_IRINT_MASK) + +#define UART_USR2_RIIN_MASK (0x200U) +#define UART_USR2_RIIN_SHIFT (9U) +#define UART_USR2_RIIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIIN_SHIFT)) & UART_USR2_RIIN_MASK) + +#define UART_USR2_RIDELT_MASK (0x400U) +#define UART_USR2_RIDELT_SHIFT (10U) +#define UART_USR2_RIDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIDELT_SHIFT)) & UART_USR2_RIDELT_MASK) + +#define UART_USR2_ACST_MASK (0x800U) +#define UART_USR2_ACST_SHIFT (11U) +/*! ACST + * 0b0..Measurement of bit length not finished (in autobaud) + * 0b1..Measurement of bit length finished (in autobaud). (write 1 to clear) + */ +#define UART_USR2_ACST(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ACST_SHIFT)) & UART_USR2_ACST_MASK) + +#define UART_USR2_IDLE_MASK (0x1000U) +#define UART_USR2_IDLE_SHIFT (12U) +/*! IDLE + * 0b0..No idle condition detected + * 0b1..Idle condition detected (write 1 to clear) + */ +#define UART_USR2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IDLE_SHIFT)) & UART_USR2_IDLE_MASK) + +#define UART_USR2_DTRF_MASK (0x2000U) +#define UART_USR2_DTRF_SHIFT (13U) +#define UART_USR2_DTRF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DTRF_SHIFT)) & UART_USR2_DTRF_MASK) + +#define UART_USR2_TXFE_MASK (0x4000U) +#define UART_USR2_TXFE_SHIFT (14U) +/*! TXFE + * 0b0..The transmit buffer (TxFIFO) is not empty + * 0b1..The transmit buffer (TxFIFO) is empty + */ +#define UART_USR2_TXFE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXFE_SHIFT)) & UART_USR2_TXFE_MASK) + +#define UART_USR2_ADET_MASK (0x8000U) +#define UART_USR2_ADET_SHIFT (15U) +/*! ADET + * 0b0..ASCII "A" or "a" was not received + * 0b1..ASCII "A" or "a" was received (write 1 to clear) + */ +#define UART_USR2_ADET(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ADET_SHIFT)) & UART_USR2_ADET_MASK) +/*! @} */ + +/*! @name UESC - UART Escape Character Register */ +/*! @{ */ + +#define UART_UESC_ESC_CHAR_MASK (0xFFU) +#define UART_UESC_ESC_CHAR_SHIFT (0U) +#define UART_UESC_ESC_CHAR(x) (((uint32_t)(((uint32_t)(x)) << UART_UESC_ESC_CHAR_SHIFT)) & UART_UESC_ESC_CHAR_MASK) +/*! @} */ + +/*! @name UTIM - UART Escape Timer Register */ +/*! @{ */ + +#define UART_UTIM_TIM_MASK (0xFFFU) +#define UART_UTIM_TIM_SHIFT (0U) +#define UART_UTIM_TIM(x) (((uint32_t)(((uint32_t)(x)) << UART_UTIM_TIM_SHIFT)) & UART_UTIM_TIM_MASK) +/*! @} */ + +/*! @name UBIR - UART BRM Incremental Register */ +/*! @{ */ + +#define UART_UBIR_INC_MASK (0xFFFFU) +#define UART_UBIR_INC_SHIFT (0U) +#define UART_UBIR_INC(x) (((uint32_t)(((uint32_t)(x)) << UART_UBIR_INC_SHIFT)) & UART_UBIR_INC_MASK) +/*! @} */ + +/*! @name UBMR - UART BRM Modulator Register */ +/*! @{ */ + +#define UART_UBMR_MOD_MASK (0xFFFFU) +#define UART_UBMR_MOD_SHIFT (0U) +#define UART_UBMR_MOD(x) (((uint32_t)(((uint32_t)(x)) << UART_UBMR_MOD_SHIFT)) & UART_UBMR_MOD_MASK) +/*! @} */ + +/*! @name UBRC - UART Baud Rate Count Register */ +/*! @{ */ + +#define UART_UBRC_BCNT_MASK (0xFFFFU) +#define UART_UBRC_BCNT_SHIFT (0U) +#define UART_UBRC_BCNT(x) (((uint32_t)(((uint32_t)(x)) << UART_UBRC_BCNT_SHIFT)) & UART_UBRC_BCNT_MASK) +/*! @} */ + +/*! @name ONEMS - UART One Millisecond Register */ +/*! @{ */ + +#define UART_ONEMS_ONEMS_MASK (0xFFFFFFU) +#define UART_ONEMS_ONEMS_SHIFT (0U) +#define UART_ONEMS_ONEMS(x) (((uint32_t)(((uint32_t)(x)) << UART_ONEMS_ONEMS_SHIFT)) & UART_ONEMS_ONEMS_MASK) +/*! @} */ + +/*! @name UTS - UART Test Register */ +/*! @{ */ + +#define UART_UTS_SOFTRST_MASK (0x1U) +#define UART_UTS_SOFTRST_SHIFT (0U) +/*! SOFTRST + * 0b0..Software reset inactive + * 0b1..Software reset active + */ +#define UART_UTS_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_SOFTRST_SHIFT)) & UART_UTS_SOFTRST_MASK) + +#define UART_UTS_RXFULL_MASK (0x8U) +#define UART_UTS_RXFULL_SHIFT (3U) +/*! RXFULL + * 0b0..The RxFIFO is not full + * 0b1..The RxFIFO is full + */ +#define UART_UTS_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXFULL_SHIFT)) & UART_UTS_RXFULL_MASK) + +#define UART_UTS_TXFULL_MASK (0x10U) +#define UART_UTS_TXFULL_SHIFT (4U) +/*! TXFULL + * 0b0..The TxFIFO is not full + * 0b1..The TxFIFO is full + */ +#define UART_UTS_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXFULL_SHIFT)) & UART_UTS_TXFULL_MASK) + +#define UART_UTS_RXEMPTY_MASK (0x20U) +#define UART_UTS_RXEMPTY_SHIFT (5U) +/*! RXEMPTY + * 0b0..The RxFIFO is not empty + * 0b1..The RxFIFO is empty + */ +#define UART_UTS_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXEMPTY_SHIFT)) & UART_UTS_RXEMPTY_MASK) + +#define UART_UTS_TXEMPTY_MASK (0x40U) +#define UART_UTS_TXEMPTY_SHIFT (6U) +/*! TXEMPTY + * 0b0..The TxFIFO is not empty + * 0b1..The TxFIFO is empty + */ +#define UART_UTS_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXEMPTY_SHIFT)) & UART_UTS_TXEMPTY_MASK) + +#define UART_UTS_RXDBG_MASK (0x200U) +#define UART_UTS_RXDBG_SHIFT (9U) +/*! RXDBG + * 0b0..rx fifo read pointer does not increment + * 0b1..rx_fifo read pointer increments as normal + */ +#define UART_UTS_RXDBG(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXDBG_SHIFT)) & UART_UTS_RXDBG_MASK) + +#define UART_UTS_LOOPIR_MASK (0x400U) +#define UART_UTS_LOOPIR_SHIFT (10U) +/*! LOOPIR + * 0b0..No IR loop + * 0b1..Connect IR transmitter to IR receiver + */ +#define UART_UTS_LOOPIR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOPIR_SHIFT)) & UART_UTS_LOOPIR_MASK) + +#define UART_UTS_DBGEN_MASK (0x800U) +#define UART_UTS_DBGEN_SHIFT (11U) +/*! DBGEN + * 0b0..UART will go into debug mode when debug_req is HIGH + * 0b1..UART will not go into debug mode even if debug_req is HIGH + */ +#define UART_UTS_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_DBGEN_SHIFT)) & UART_UTS_DBGEN_MASK) + +#define UART_UTS_LOOP_MASK (0x1000U) +#define UART_UTS_LOOP_SHIFT (12U) +/*! LOOP + * 0b0..Normal receiver operation + * 0b1..Internally connect the transmitter output to the receiver input + */ +#define UART_UTS_LOOP(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOP_SHIFT)) & UART_UTS_LOOP_MASK) + +#define UART_UTS_FRCPERR_MASK (0x2000U) +#define UART_UTS_FRCPERR_SHIFT (13U) +/*! FRCPERR + * 0b0..Generate normal parity + * 0b1..Generate inverted parity (error) + */ +#define UART_UTS_FRCPERR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_FRCPERR_SHIFT)) & UART_UTS_FRCPERR_MASK) +/*! @} */ + +/*! @name UMCR - UART RS-485 Mode Control Register */ +/*! @{ */ + +#define UART_UMCR_MDEN_MASK (0x1U) +#define UART_UMCR_MDEN_SHIFT (0U) +/*! MDEN + * 0b0..Normal RS-232 or IrDA mode, see for detail. + * 0b1..Enable RS-485 mode, see for detail + */ +#define UART_UMCR_MDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_MDEN_SHIFT)) & UART_UMCR_MDEN_MASK) + +#define UART_UMCR_SLAM_MASK (0x2U) +#define UART_UMCR_SLAM_SHIFT (1U) +/*! SLAM + * 0b0..Select Normal Address Detect mode + * 0b1..Select Automatic Address Detect mode + */ +#define UART_UMCR_SLAM(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLAM_SHIFT)) & UART_UMCR_SLAM_MASK) + +#define UART_UMCR_TXB8_MASK (0x4U) +#define UART_UMCR_TXB8_SHIFT (2U) +/*! TXB8 + * 0b0..0 will be transmitted as the RS485 9th data bit + * 0b1..1 will be transmitted as the RS485 9th data bit + */ +#define UART_UMCR_TXB8(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_TXB8_SHIFT)) & UART_UMCR_TXB8_MASK) + +#define UART_UMCR_SADEN_MASK (0x8U) +#define UART_UMCR_SADEN_SHIFT (3U) +/*! SADEN + * 0b0..Disable RS-485 Slave Address Detected Interrupt + * 0b1..Enable RS-485 Slave Address Detected Interrupt + */ +#define UART_UMCR_SADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SADEN_SHIFT)) & UART_UMCR_SADEN_MASK) + +#define UART_UMCR_SLADDR_MASK (0xFF00U) +#define UART_UMCR_SLADDR_SHIFT (8U) +#define UART_UMCR_SLADDR(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLADDR_SHIFT)) & UART_UMCR_SLADDR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group UART_Register_Masks */ + + +/* UART - Peripheral instance base addresses */ +/** Peripheral UART1 base address */ +#define UART1_BASE (0x30860000u) +/** Peripheral UART1 base pointer */ +#define UART1 ((UART_Type *)UART1_BASE) +/** Peripheral UART2 base address */ +#define UART2_BASE (0x30890000u) +/** Peripheral UART2 base pointer */ +#define UART2 ((UART_Type *)UART2_BASE) +/** Peripheral UART3 base address */ +#define UART3_BASE (0x30880000u) +/** Peripheral UART3 base pointer */ +#define UART3 ((UART_Type *)UART3_BASE) +/** Peripheral UART4 base address */ +#define UART4_BASE (0x30A60000u) +/** Peripheral UART4 base pointer */ +#define UART4 ((UART_Type *)UART4_BASE) +/** Array initializer of UART peripheral base addresses */ +#define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE } +/** Array initializer of UART peripheral base pointers */ +#define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2, UART3, UART4 } +/** Interrupt vectors for the UART peripheral type */ +#define UART_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn } + +/*! + * @} + */ /* end of group UART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer + * @{ + */ + +/** USDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ + __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ + __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ + __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ + __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ + __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ + __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ + __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ + __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ + __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ + __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ + __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ + __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ + __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ + __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ + __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ + __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ + __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ + uint8_t RESERVED_0[4]; + __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ + __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ + __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ + __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ + __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ + uint8_t RESERVED_2[4]; + __IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL Control, offset: 0x70 */ + __I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL Status, offset: 0x74 */ + uint8_t RESERVED_3[72]; + __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ + __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ + __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ + __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ +} USDHC_Type; + +/* ---------------------------------------------------------------------------- + -- USDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Register_Masks USDHC Register Masks + * @{ + */ + +/*! @name DS_ADDR - DMA System Address */ +/*! @{ */ + +#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFCU) +#define USDHC_DS_ADDR_DS_ADDR_SHIFT (2U) +#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) +/*! @} */ + +/*! @name BLK_ATT - Block Attributes */ +/*! @{ */ + +#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) +#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) +/*! BLKSIZE + * 0b0000000001000..4096 Bytes + * 0b0001100100000..2048 Bytes + * 0b0000011001000..512 Bytes + * 0b0000000000100..4 Bytes + * 0b0000000000011..3 Bytes + * 0b0000000000010..2 Bytes + * 0b0000000000001..1 Byte + * 0b0000000000000..No data transfer + */ +#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) + +#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) +#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) +/*! BLKCNT + * 0b0000000000000010..2 blocks + * 0b0000000000000001..1 block + * 0b0000000000000000..Stop Count + */ +#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) +/*! @} */ + +/*! @name CMD_ARG - Command Argument */ +/*! @{ */ + +#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) +#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) +/*! CMDARG - Command Argument + */ +#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) +/*! @} */ + +/*! @name CMD_XFR_TYP - Command Transfer Type */ +/*! @{ */ + +#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) +#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) +/*! RSPTYP - Response Type Select + * 0b00..No Response + * 0b01..Response Length 136 + * 0b10..Response Length 48 + * 0b11..Response Length 48, check Busy after response + */ +#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) + +#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) +#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) +/*! CCCEN - Command CRC Check Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) + +#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) +#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) +/*! CICEN - Command Index Check Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) + +#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) +#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) +/*! DPSEL - Data Present Select + * 0b1..Data Present + * 0b0..No Data Present + */ +#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) + +#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) +#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) +/*! CMDTYP - Command Type + * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR + * 0b10..Resume CMD52 for writing Function Select in CCCR + * 0b01..Suspend CMD52 for writing Bus Suspend in CCCR + * 0b00..Normal Other commands + */ +#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) + +#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) +#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) +/*! CMDINX - Command Index + */ +#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) +/*! @} */ + +/*! @name CMD_RSP0 - Command Response0 */ +/*! @{ */ + +#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) +/*! CMDRSP0 - Command Response 0 + */ +#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) +/*! @} */ + +/*! @name CMD_RSP1 - Command Response1 */ +/*! @{ */ + +#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) +/*! CMDRSP1 - Command Response 1 + */ +#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) +/*! @} */ + +/*! @name CMD_RSP2 - Command Response2 */ +/*! @{ */ + +#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) +/*! CMDRSP2 - Command Response 2 + */ +#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) +/*! @} */ + +/*! @name CMD_RSP3 - Command Response3 */ +/*! @{ */ + +#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) +/*! CMDRSP3 - Command Response 3 + */ +#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) +/*! @} */ + +/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +/*! @{ */ + +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) +/*! DATCONT - Data Content + */ +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) +/*! @} */ + +/*! @name PRES_STATE - Present State */ +/*! @{ */ + +#define USDHC_PRES_STATE_CIHB_MASK (0x1U) +#define USDHC_PRES_STATE_CIHB_SHIFT (0U) +/*! CIHB - Command Inhibit (CMD) + * 0b1..Cannot issue command + * 0b0..Can issue command using only CMD line + */ +#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) + +#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) +#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) +/*! CDIHB - Command Inhibit (DATA) + * 0b1..Cannot issue command which uses the DATA line + * 0b0..Can issue command which uses the DATA line + */ +#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) + +#define USDHC_PRES_STATE_DLA_MASK (0x4U) +#define USDHC_PRES_STATE_DLA_SHIFT (2U) +/*! DLA - Data Line Active + * 0b1..DATA Line Active + * 0b0..DATA Line Inactive + */ +#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) + +#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) +#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) +/*! SDSTB - SD Clock Stable + * 0b1..Clock is stable. + * 0b0..Clock is changing frequency and not stable. + */ +#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) + +#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) +#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) +/*! IPGOFF - IPG_CLK Gated Off Internally + * 0b1..IPG_CLK is gated off. + * 0b0..IPG_CLK is active. + */ +#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) + +#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) +#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) +/*! HCKOFF - HCLK Gated Off Internally + * 0b1..HCLK is gated off. + * 0b0..HCLK is active. + */ +#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) + +#define USDHC_PRES_STATE_PEROFF_MASK (0x40U) +#define USDHC_PRES_STATE_PEROFF_SHIFT (6U) +/*! PEROFF - IPG_PERCLK Gated Off Internally + * 0b1..IPG_PERCLK is gated off. + * 0b0..IPG_PERCLK is active. + */ +#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) + +#define USDHC_PRES_STATE_SDOFF_MASK (0x80U) +#define USDHC_PRES_STATE_SDOFF_SHIFT (7U) +/*! SDOFF - SD Clock Gated Off Internally + * 0b1..SD Clock is gated off. + * 0b0..SD Clock is active. + */ +#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) + +#define USDHC_PRES_STATE_WTA_MASK (0x100U) +#define USDHC_PRES_STATE_WTA_SHIFT (8U) +/*! WTA - Write Transfer Active + * 0b1..Transferring data + * 0b0..No valid data + */ +#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) + +#define USDHC_PRES_STATE_RTA_MASK (0x200U) +#define USDHC_PRES_STATE_RTA_SHIFT (9U) +/*! RTA - Read Transfer Active + * 0b1..Transferring data + * 0b0..No valid data + */ +#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) + +#define USDHC_PRES_STATE_BWEN_MASK (0x400U) +#define USDHC_PRES_STATE_BWEN_SHIFT (10U) +/*! BWEN - Buffer Write Enable + * 0b1..Write enable + * 0b0..Write disable + */ +#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) + +#define USDHC_PRES_STATE_BREN_MASK (0x800U) +#define USDHC_PRES_STATE_BREN_SHIFT (11U) +/*! BREN - Buffer Read Enable + * 0b1..Read enable + * 0b0..Read disable + */ +#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) + +#define USDHC_PRES_STATE_RTR_MASK (0x1000U) +#define USDHC_PRES_STATE_RTR_SHIFT (12U) +/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode) + * 0b1..Sampling clock needs re-tuning + * 0b0..Fixed or well tuned sampling clock + */ +#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) + +#define USDHC_PRES_STATE_TSCD_MASK (0x8000U) +#define USDHC_PRES_STATE_TSCD_SHIFT (15U) +/*! TSCD - Tape Select Change Done + * 0b1..Delay cell select change is finished. + * 0b0..Delay cell select change is not finished. + */ +#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) + +#define USDHC_PRES_STATE_CINST_MASK (0x10000U) +#define USDHC_PRES_STATE_CINST_SHIFT (16U) +/*! CINST - Card Inserted + * 0b1..Card Inserted + * 0b0..Power on Reset or No Card + */ +#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) + +#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) +#define USDHC_PRES_STATE_CDPL_SHIFT (18U) +/*! CDPL - Card Detect Pin Level + * 0b1..Card present (CD_B = 0) + * 0b0..No card present (CD_B = 1) + */ +#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) + +#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) +#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) +/*! WPSPL - Write Protect Switch Pin Level + * 0b1..Write enabled (WP = 0) + * 0b0..Write protected (WP = 1) + */ +#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) + +#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) +#define USDHC_PRES_STATE_CLSL_SHIFT (23U) +/*! CLSL - CMD Line Signal Level + */ +#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) + +#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) +#define USDHC_PRES_STATE_DLSL_SHIFT (24U) +/*! DLSL - DATA[7:0] Line Signal Level + */ +#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) +/*! @} */ + +/*! @name PROT_CTRL - Protocol Control */ +/*! @{ */ + +#define USDHC_PROT_CTRL_LCTL_MASK (0x1U) +#define USDHC_PROT_CTRL_LCTL_SHIFT (0U) +/*! LCTL - LED Control + * 0b1..LED on + * 0b0..LED off + */ +#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) + +#define USDHC_PROT_CTRL_DTW_MASK (0x6U) +#define USDHC_PROT_CTRL_DTW_SHIFT (1U) +/*! DTW - Data Transfer Width + * 0b10..8-bit mode + * 0b01..4-bit mode + * 0b00..1-bit mode + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) + +#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) +#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) +/*! D3CD - DATA3 as Card Detection Pin + * 0b1..DATA3 as Card Detection Pin + * 0b0..DATA3 does not monitor Card Insertion + */ +#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) + +#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) +#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) +/*! EMODE - Endian Mode + * 0b00..Big Endian Mode + * 0b01..Half Word Big Endian Mode + * 0b10..Little Endian Mode + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) + +#define USDHC_PROT_CTRL_CDTL_MASK (0x40U) +#define USDHC_PROT_CTRL_CDTL_SHIFT (6U) +/*! CDTL - Card Detect Test Level + * 0b1..Card Detect Test Level is 1, card inserted + * 0b0..Card Detect Test Level is 0, no card inserted + */ +#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) + +#define USDHC_PROT_CTRL_CDSS_MASK (0x80U) +#define USDHC_PROT_CTRL_CDSS_SHIFT (7U) +/*! CDSS - Card Detect Signal Selection + * 0b1..Card Detection Test Level is selected (for test purpose). + * 0b0..Card Detection Level is selected (for normal purpose). + */ +#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) + +#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) +#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) +/*! DMASEL - DMA Select + * 0b00..No DMA or Simple DMA is selected + * 0b01..ADMA1 is selected + * 0b10..ADMA2 is selected + * 0b11..reserved + */ +#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) + +#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) +#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) +/*! SABGREQ - Stop At Block Gap Request + * 0b1..Stop + * 0b0..Transfer + */ +#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) + +#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) +#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) +/*! CREQ - Continue Request + * 0b1..Restart + * 0b0..No effect + */ +#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) + +#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) +#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) +/*! RWCTL - Read Wait Control + * 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + * 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + */ +#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) + +#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) +#define USDHC_PROT_CTRL_IABG_SHIFT (19U) +/*! IABG - Interrupt At Block Gap + * 0b1..Enabled + * 0b0..Disabled + */ +#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) + +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) + +#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) +#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) +/*! WECINT - Wakeup Event Enable On Card Interrupt + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) + +#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) +#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) +/*! WECINS - Wakeup Event Enable On SD Card Insertion + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) + +#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) +#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) +/*! WECRM - Wakeup Event Enable On SD Card Removal + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) + +#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) +#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) +/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + * 0bxx1..Burst length is enabled for INCR + * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16 + * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + */ +#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) + +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) +/*! NON_EXACT_BLK_RD + * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + * 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + */ +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) +/*! @} */ + +/*! @name SYS_CTRL - System Control */ +/*! @{ */ + +#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) +#define USDHC_SYS_CTRL_DVS_SHIFT (4U) +/*! DVS - Divisor + * 0b0000..Divide-by-1 + * 0b0001..Divide-by-2 + * 0b1110..Divide-by-15 + * 0b1111..Divide-by-16 + */ +#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) + +#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) +#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) +/*! SDCLKFS - SDCLK Frequency Select + */ +#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) + +#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) +#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +/*! DTOCV - Data Timeout Counter Value + * 0b1111..SDCLK x 2 29 + * 0b1110..SDCLK x 2 28 + * 0b0001..SDCLK x 2 15 + * 0b0000..SDCLK x 2 14 + */ +#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) + +#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) +#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) +#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) + +#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) +#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) +/*! RSTA - Software Reset For ALL + * 0b1..Reset + * 0b0..No Reset + */ +#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) + +#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) +#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) +/*! RSTC - Software Reset For CMD Line + * 0b1..Reset + * 0b0..No Reset + */ +#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) + +#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) +#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) +/*! RSTD - Software Reset For DATA Line + * 0b1..Reset + * 0b0..No Reset + */ +#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) + +#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) +#define USDHC_SYS_CTRL_INITA_SHIFT (27U) +/*! INITA - Initialization Active + */ +#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) + +#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) +#define USDHC_SYS_CTRL_RSTT_SHIFT (28U) +/*! RSTT - Reset Tuning + */ +#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status */ +/*! @{ */ + +#define USDHC_INT_STATUS_CC_MASK (0x1U) +#define USDHC_INT_STATUS_CC_SHIFT (0U) +/*! CC - Command Complete + * 0b1..Command complete + * 0b0..Command not complete + */ +#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) + +#define USDHC_INT_STATUS_TC_MASK (0x2U) +#define USDHC_INT_STATUS_TC_SHIFT (1U) +/*! TC - Transfer Complete + * 0b1..Transfer complete + * 0b0..Transfer not complete + */ +#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) + +#define USDHC_INT_STATUS_BGE_MASK (0x4U) +#define USDHC_INT_STATUS_BGE_SHIFT (2U) +/*! BGE - Block Gap Event + * 0b1..Transaction stopped at block gap + * 0b0..No block gap event + */ +#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) + +#define USDHC_INT_STATUS_DINT_MASK (0x8U) +#define USDHC_INT_STATUS_DINT_SHIFT (3U) +/*! DINT - DMA Interrupt + * 0b1..DMA Interrupt is generated + * 0b0..No DMA Interrupt + */ +#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) + +#define USDHC_INT_STATUS_BWR_MASK (0x10U) +#define USDHC_INT_STATUS_BWR_SHIFT (4U) +/*! BWR - Buffer Write Ready + * 0b1..Ready to write buffer: + * 0b0..Not ready to write buffer + */ +#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) + +#define USDHC_INT_STATUS_BRR_MASK (0x20U) +#define USDHC_INT_STATUS_BRR_SHIFT (5U) +/*! BRR - Buffer Read Ready + * 0b1..Ready to read buffer + * 0b0..Not ready to read buffer + */ +#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) + +#define USDHC_INT_STATUS_CINS_MASK (0x40U) +#define USDHC_INT_STATUS_CINS_SHIFT (6U) +/*! CINS - Card Insertion + * 0b1..Card inserted + * 0b0..Card state unstable or removed + */ +#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) + +#define USDHC_INT_STATUS_CRM_MASK (0x80U) +#define USDHC_INT_STATUS_CRM_SHIFT (7U) +/*! CRM - Card Removal + * 0b1..Card removed + * 0b0..Card state unstable or inserted + */ +#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) + +#define USDHC_INT_STATUS_CINT_MASK (0x100U) +#define USDHC_INT_STATUS_CINT_SHIFT (8U) +/*! CINT - Card Interrupt + * 0b1..Generate Card Interrupt + * 0b0..No Card Interrupt + */ +#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) + +#define USDHC_INT_STATUS_RTE_MASK (0x1000U) +#define USDHC_INT_STATUS_RTE_SHIFT (12U) +/*! RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode) + * 0b1..Re-Tuning should be performed + * 0b0..Re-Tuning is not required + */ +#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) + +#define USDHC_INT_STATUS_TP_MASK (0x4000U) +#define USDHC_INT_STATUS_TP_SHIFT (14U) +/*! TP - Tuning Pass:(only for SD3.0 SDR104 mode) + */ +#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) + +#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) +#define USDHC_INT_STATUS_CTOE_SHIFT (16U) +/*! CTOE - Command Timeout Error + * 0b1..Time out + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) + +#define USDHC_INT_STATUS_CCE_MASK (0x20000U) +#define USDHC_INT_STATUS_CCE_SHIFT (17U) +/*! CCE - Command CRC Error + * 0b1..CRC Error Generated. + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) + +#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) +#define USDHC_INT_STATUS_CEBE_SHIFT (18U) +/*! CEBE - Command End Bit Error + * 0b1..End Bit Error Generated + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) + +#define USDHC_INT_STATUS_CIE_MASK (0x80000U) +#define USDHC_INT_STATUS_CIE_SHIFT (19U) +/*! CIE - Command Index Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) + +#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) +#define USDHC_INT_STATUS_DTOE_SHIFT (20U) +/*! DTOE - Data Timeout Error + * 0b1..Time out + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) + +#define USDHC_INT_STATUS_DCE_MASK (0x200000U) +#define USDHC_INT_STATUS_DCE_SHIFT (21U) +/*! DCE - Data CRC Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) + +#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) +#define USDHC_INT_STATUS_DEBE_SHIFT (22U) +/*! DEBE - Data End Bit Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) + +#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) +#define USDHC_INT_STATUS_AC12E_SHIFT (24U) +/*! AC12E - Auto CMD12 Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) + +#define USDHC_INT_STATUS_TNE_MASK (0x4000000U) +#define USDHC_INT_STATUS_TNE_SHIFT (26U) +/*! TNE - Tuning Error: (only for SD3.0 SDR104 mode) + */ +#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) + +#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) +#define USDHC_INT_STATUS_DMAE_SHIFT (28U) +/*! DMAE - DMA Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) +/*! @} */ + +/*! @name INT_STATUS_EN - Interrupt Status Enable */ +/*! @{ */ + +#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) +#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) +/*! CCSEN - Command Complete Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) + +#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) +#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) +/*! TCSEN - Transfer Complete Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) + +#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) +#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) +/*! BGESEN - Block Gap Event Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) + +#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) +#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) +/*! DINTSEN - DMA Interrupt Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) + +#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) +#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) +/*! BWRSEN - Buffer Write Ready Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) + +#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) +#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) +/*! BRRSEN - Buffer Read Ready Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) + +#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) +#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) +/*! CINSSEN - Card Insertion Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) + +#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) +#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) +/*! CRMSEN - Card Removal Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) + +#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) +#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) +/*! CINTSEN - Card Interrupt Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) + +#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) +#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) +/*! RTESEN - Re-Tuning Event Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) + +#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) +#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) +/*! TPSEN - Tuning Pass Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) + +#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) +#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) +/*! CTOESEN - Command Timeout Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) + +#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) +#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) +/*! CCESEN - Command CRC Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) + +#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) +#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) +/*! CEBESEN - Command End Bit Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) + +#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) +#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) +/*! CIESEN - Command Index Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) + +#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) +#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) +/*! DTOESEN - Data Timeout Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) + +#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) +#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) +/*! DCESEN - Data CRC Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) + +#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) +#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) +/*! DEBESEN - Data End Bit Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) + +#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) +#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) +/*! AC12ESEN - Auto CMD12 Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) + +#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) +#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) +/*! TNESEN - Tuning Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) + +#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) +#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) +/*! DMAESEN - DMA Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) +/*! @} */ + +/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +/*! @{ */ + +#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) +#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) +/*! CCIEN - Command Complete Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) +#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) +/*! TCIEN - Transfer Complete Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) +#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) +/*! BGEIEN - Block Gap Event Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) +#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) +/*! DINTIEN - DMA Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) +#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) +/*! BWRIEN - Buffer Write Ready Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) +#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) +/*! BRRIEN - Buffer Read Ready Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) +#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) +/*! CINSIEN - Card Insertion Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) +#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) +/*! CRMIEN - Card Removal Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) +#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) +/*! CINTIEN - Card Interrupt Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) +#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) +/*! RTEIEN - Re-Tuning Event Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) +#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) +/*! TPIEN - Tuning Pass Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) +/*! CTOEIEN - Command Timeout Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) +#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) +/*! CCEIEN - Command CRC Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) +/*! CEBEIEN - Command End Bit Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) +#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) +/*! CIEIEN - Command Index Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) +/*! DTOEIEN - Data Timeout Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) +#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) +/*! DCEIEN - Data CRC Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) +/*! DEBEIEN - Data End Bit Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) +/*! AC12EIEN - Auto CMD12 Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) +#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) +/*! TNEIEN - Tuning Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) +/*! DMAEIEN - DMA Error Interrupt Enable + * 0b1..Enable + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) +/*! @} */ + +/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +/*! @{ */ + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) +/*! AC12NE - Auto CMD12 Not Executed + * 0b1..Not executed + * 0b0..Executed + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) +/*! AC12TOE - Auto CMD12 / 23 Timeout Error + * 0b1..Time out + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) +/*! AC12EBE - Auto CMD12 / 23 End Bit Error + * 0b1..End Bit Error Generated + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) +/*! AC12CE - Auto CMD12 / 23 CRC Error + * 0b1..CRC Error Met in Auto CMD12/23 Response + * 0b0..No CRC error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) +/*! AC12IE - Auto CMD12 / 23 Index Error + * 0b1..Error, the CMD index in response is not CMD12/23 + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) +/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error + * 0b1..Not Issued + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) +/*! EXECUTE_TUNING - Execute Tuning + */ +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - Sample Clock Select + * 0b1..Tuned clock is used to sample data + * 0b0..Fixed clock is used to sample data + */ +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) +/*! @} */ + +/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +/*! @{ */ + +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) +/*! SDR50_SUPPORT - SDR50 support + */ +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) + +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) +/*! SDR104_SUPPORT - SDR104 support + */ +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) + +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) +/*! DDR50_SUPPORT - DDR50 support + */ +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) + +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) +/*! TIME_COUNT_RETUNING - Time Counter for Retuning + */ +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) + +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) +/*! USE_TUNING_SDR50 - Use Tuning for SDR50 + * 0b1..SDR50 requires tuning + * 0b0..SDR does not require tuning + */ +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) + +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) +/*! RETUNING_MODE - Retuning Mode + * 0b00..Mode 1 + * 0b01..Mode 2 + * 0b10..Mode 3 + * 0b11..Reserved + */ +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) + +#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) +#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) +/*! MBL - Max Block Length + * 0b000..512 bytes + * 0b001..1024 bytes + * 0b010..2048 bytes + * 0b011..4096 bytes + */ +#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) + +#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) +#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) +/*! ADMAS - ADMA Support + * 0b1..Advanced DMA Supported + * 0b0..Advanced DMA Not supported + */ +#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) + +#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) +#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) +/*! HSS - High Speed Support + * 0b1..High Speed Supported + * 0b0..High Speed Not Supported + */ +#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) + +#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) +#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) +/*! DMAS - DMA Support + * 0b1..DMA Supported + * 0b0..DMA not supported + */ +#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) + +#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) +#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) +/*! SRS - Suspend / Resume Support + * 0b1..Supported + * 0b0..Not supported + */ +#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) + +#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) +#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) +/*! VS33 - Voltage Support 3.3V + * 0b1..3.3V supported + * 0b0..3.3V not supported + */ +#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) + +#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) +#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) +/*! VS30 - Voltage Support 3.0 V + * 0b1..3.0V supported + * 0b0..3.0V not supported + */ +#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) + +#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) +#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) +/*! VS18 - Voltage Support 1.8 V + * 0b1..1.8V supported + * 0b0..1.8V not supported + */ +#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) +/*! @} */ + +/*! @name WTMK_LVL - Watermark Level */ +/*! @{ */ + +#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) +#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) +/*! RD_WML - Read Watermark Level + */ +#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) + +#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) +#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) +/*! RD_BRST_LEN - Read Burst Length Due to system restriction, the actual burst length may not exceed 16. + */ +#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) + +#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) +#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) +/*! WR_WML - Write Watermark Level + */ +#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) + +#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) +#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) +/*! WR_BRST_LEN - Write Burst Length Due to system restriction, the actual burst length may not exceed 16. + */ +#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) +/*! @} */ + +/*! @name MIX_CTRL - Mixer Control */ +/*! @{ */ + +#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) +#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) +/*! DMAEN - DMA Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) + +#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) +#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) +/*! BCEN - Block Count Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) + +#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) +#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) +/*! AC12EN - Auto CMD12 Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) + +#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) +#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) +/*! DDR_EN - Dual Data Rate mode selection + */ +#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) + +#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) +#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) +/*! DTDSEL - Data Transfer Direction Select + * 0b1..Read (Card to Host) + * 0b0..Write (Host to Card) + */ +#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) + +#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) +#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) +/*! MSBSEL - Multi / Single Block Select + * 0b1..Multiple Blocks + * 0b0..Single Block + */ +#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) + +#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) +#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) +#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) + +#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) +#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) +/*! AC23EN - Auto CMD23 Enable + */ +#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) + +#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) +#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) +/*! EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode) + * 0b1..Execute Tuning + * 0b0..Not Tuned or Tuning Completed + */ +#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) + +#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL + * 0b1..Tuned clock is used to sample data / cmd + * 0b0..Fixed clock is used to sample data / cmd + */ +#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) + +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) +/*! AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode) + * 0b1..Enable auto tuning + * 0b0..Disable auto tuning + */ +#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) + +#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) +#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) +/*! FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode) + * 0b1..Feedback clock comes from the ipp_card_clk_out + * 0b0..Feedback clock comes from the loopback CLK + */ +#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) + +#define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U) +#define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U) +/*! HS400_MODE - Enable HS400 Mode + */ +#define USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK) +/*! @} */ + +/*! @name FORCE_EVENT - Force Event */ +/*! @{ */ + +#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) +#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) +/*! FEVTAC12NE - Force Event Auto Command 12 Not Executed + */ +#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) +/*! FEVTAC12TOE - Force Event Auto Command 12 Time Out Error + */ +#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) +#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) +/*! FEVTAC12CE - Force Event Auto Command 12 CRC Error + */ +#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) +/*! FEVTAC12EBE - Force Event Auto Command 12 End Bit Error + */ +#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) +#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) +/*! FEVTAC12IE - Force Event Auto Command 12 Index Error + */ +#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) +/*! FEVTCNIBAC12E - Force Event Command Not Executed By Auto Command 12 Error + */ +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) + +#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) +#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) +/*! FEVTCTOE - Force Event Command Time Out Error + */ +#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) +#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) +/*! FEVTCCE - Force Event Command CRC Error + */ +#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) +#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) +/*! FEVTCEBE - Force Event Command End Bit Error + */ +#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) +#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) +/*! FEVTCIE - Force Event Command Index Error + */ +#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) + +#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) +#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) +/*! FEVTDTOE - Force Event Data Time Out Error + */ +#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) + +#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) +#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) +/*! FEVTDCE - Force Event Data CRC Error + */ +#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) + +#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) +#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) +/*! FEVTDEBE - Force Event Data End Bit Error + */ +#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) +#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) +/*! FEVTAC12E - Force Event Auto Command 12 Error + */ +#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) + +#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) +#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) +/*! FEVTTNE - Force Tuning Error + */ +#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) + +#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) +#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) +/*! FEVTDMAE - Force Event DMA Error + */ +#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) +#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) +/*! FEVTCINT - Force Event Card Interrupt + */ +#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) +/*! @} */ + +/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ +/*! @{ */ + +#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) +#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) +/*! ADMAES - ADMA Error State (when ADMA Error is occurred) + */ +#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) + +#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) +#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) +/*! ADMALME - ADMA Length Mismatch Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) + +#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) +/*! ADMADCE - ADMA Descritor Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) +/*! @} */ + +/*! @name ADMA_SYS_ADDR - ADMA System Address */ +/*! @{ */ + +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) +/*! ADS_ADDR - ADMA System Address + */ +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) +/*! @} */ + +/*! @name DLL_CTRL - DLL (Delay Line) Control */ +/*! @{ */ + +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ + +/*! @name DLL_STATUS - DLL Status */ +/*! @{ */ + +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) + +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) + +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) + +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) +/*! @} */ + +/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +/*! @{ */ + +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) +/*! @} */ + +/*! @name STROBE_DLL_CTRL - Strobe DLL Control */ +/*! @{ */ + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U) +/*! STROBE_DLL_CTRL_ENABLE - Strobe DLL Control Enable + */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U) +/*! STROBE_DLL_CTRL_RESET - Strobe DLL Control Reset + */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +/*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL Control Slave Force Updated + */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x38U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) +/*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target + */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK (0x40U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT (6U) +/*! STROBE_DLL_CTRL_GATE_UPDATE_0 - Strobe DLL Control Gate Update + */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK (0x80U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT (7U) +/*! STROBE_DLL_CTRL_GATE_UPDATE_1 - Strobe DLL Control Gate Update + */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +/*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL Control Slave Override + */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +/*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL Control Slave Override Value + */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +/*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL Control Slave Update Interval + */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +/*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL Control Reference Update Interval + */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ + +/*! @name STROBE_DLL_STATUS - Strobe DLL Status */ +/*! @{ */ + +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U) +/*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL Status Slave Lock + */ +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK) + +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U) +/*! STROBE_DLL_STS_REF_LOCK - Strobe DLL Status Reference Lock + */ +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK) + +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U) +/*! STROBE_DLL_STS_SLV_SEL - Strobe DLL Status Slave Select + */ +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK) + +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U) +/*! STROBE_DLL_STS_REF_SEL - Strobe DLL Status Reference Select + */ +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK) +/*! @} */ + +/*! @name VEND_SPEC - Vendor Specific Register */ +/*! @{ */ + +#define USDHC_VEND_SPEC_EXT_DMA_EN_MASK (0x1U) +#define USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT (0U) +/*! EXT_DMA_EN - External DMA Request Enable + * 0b0..In any scenario, uSDHC does not send out external DMA request. + * 0b1..When internal DMA is not active, the external DMA request will be sent out. + */ +#define USDHC_VEND_SPEC_EXT_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT)) & USDHC_VEND_SPEC_EXT_DMA_EN_MASK) + +#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) +#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) +/*! VSELECT - Voltage Selection + * 0b1..Change the voltage to low voltage range, around 1.8 V + * 0b0..Change the voltage to high voltage range, around 3.0 V + */ +#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) + +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) +/*! CONFLICT_CHK_EN - Conflict check enable. + * 0b0..Conflict check disable + * 0b1..Conflict check enable + */ +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) + +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) +/*! AC12_WR_CHKBUSY_EN + * 0b0..Do not check busy after auto CMD12 for write data packet + * 0b1..Check busy after auto CMD12 for write data packet + */ +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) + +#define USDHC_VEND_SPEC_DAT3_CD_POL_MASK (0x10U) +#define USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT (4U) +/*! DAT3_CD_POL + * 0b0..Card detected when DATA3 is high. + * 0b1..Card detected when DATA3 is low. + */ +#define USDHC_VEND_SPEC_DAT3_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT)) & USDHC_VEND_SPEC_DAT3_CD_POL_MASK) + +#define USDHC_VEND_SPEC_CD_POL_MASK (0x20U) +#define USDHC_VEND_SPEC_CD_POL_SHIFT (5U) +/*! CD_POL + * 0b0..CD_B pin is low active. + * 0b1..CD_B pin is high active. + */ +#define USDHC_VEND_SPEC_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CD_POL_SHIFT)) & USDHC_VEND_SPEC_CD_POL_MASK) + +#define USDHC_VEND_SPEC_WP_POL_MASK (0x40U) +#define USDHC_VEND_SPEC_WP_POL_SHIFT (6U) +/*! WP_POL + * 0b0..WP pin is high active. + * 0b1..WP pin is low active. + */ +#define USDHC_VEND_SPEC_WP_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_WP_POL_SHIFT)) & USDHC_VEND_SPEC_WP_POL_MASK) + +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK (0x80U) +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT (7U) +/*! CLKONJ_IN_ABORT + * 0b0..The CLK output is active when sending abort command while data is transmitting even if the internal FIFO + * is full (for read) or empty (for write). + * 0b1..The CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is + * full (for read) or empty (for write). + */ +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT)) & USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK) + +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) +/*! FRC_SDCLK_ON + * 0b0..CLK active or inactive is fully controlled by the hardware. + * 0b1..Force CLK active. + */ +#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) + +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK (0x800U) +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT (11U) +/*! IPG_CLK_SOFT_EN - IPG_CLK Software Enable + * 0b0..Gate off the IPG_CLK + * 0b1..Enable the IPG_CLK + */ +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK) + +#define USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK (0x1000U) +#define USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT (12U) +/*! HCLK_SOFT_EN - AHB Clock Software Enable + * 0b0..Gate off the AHB clock. + * 0b1..Enable the AHB clock. + */ +#define USDHC_VEND_SPEC_HCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK) + +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK (0x2000U) +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT (13U) +/*! IPG_PERCLK_SOFT_EN - IPG_PERCLK Software Enable + * 0b0..Gate off the IPG_PERCLK + * 0b1..Enable the IPG_PERCLK + */ +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK) + +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK (0x4000U) +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT (14U) +/*! CARD_CLK_SOFT_EN - Card Clock Software Enable + * 0b0..Gate off the sd_clk + * 0b1..Enable the sd_clk + */ +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK) + +#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) +/*! CRC_CHK_DIS - CRC Check Disable + * 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet + * 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + */ +#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) + +#define USDHC_VEND_SPEC_INT_ST_VAL_MASK (0xFF0000U) +#define USDHC_VEND_SPEC_INT_ST_VAL_SHIFT (16U) +/*! INT_ST_VAL - Internal State Value + */ +#define USDHC_VEND_SPEC_INT_ST_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_INT_ST_VAL_SHIFT)) & USDHC_VEND_SPEC_INT_ST_VAL_MASK) + +#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) +/*! CMD_BYTE_EN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) +/*! @} */ + +/*! @name MMC_BOOT - MMC Boot Register */ +/*! @{ */ + +#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) +#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) +/*! DTOCV_ACK + * 0b0000..SDCLK x 2^13 + * 0b0001..SDCLK x 2^14 + * 0b0010..SDCLK x 2^15 + * 0b0011..SDCLK x 2^16 + * 0b0100..SDCLK x 2^17 + * 0b0101..SDCLK x 2^18 + * 0b0110..SDCLK x 2^19 + * 0b0111..SDCLK x 2^20 + * 0b1110..SDCLK x 2^27 + * 0b1111..SDCLK x 2^28 + */ +#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) + +#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) +#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) +/*! BOOT_ACK + * 0b0..No ack + * 0b1..Ack + */ +#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) + +#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) +#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) +/*! BOOT_MODE + * 0b0..Normal boot + * 0b1..Alternative boot + */ +#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) + +#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) +#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) +/*! BOOT_EN + * 0b0..Fast boot disable + * 0b1..Fast boot enable + */ +#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) + +#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) + +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) +/*! DISABLE_TIME_OUT - Disable Time Out + * 0b0..Enable time out + * 0b1..Disable time out + */ +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) + +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) +/*! @} */ + +/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +/*! @{ */ + +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK (0x1U) +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT (0U) +/*! SDR104_TIMING_DIS + * 0b0..The timeout counter for Ncr changes to 80, Ncrc changes to 21. + * 0b1..The timeout counter for Ncr changes to 72, Ncrc changes to 15. + */ +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK) + +#define USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK (0x2U) +#define USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT (1U) +/*! SDR104_OE_DIS + * 0b0..Drive the CMD_OE / DATA_OE for one more clock cycle after the end bit. + * 0b1..Stop to drive the CMD_OE / DATA_OE at once after driving the end bit. + */ +#define USDHC_VEND_SPEC2_SDR104_OE_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK) + +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK (0x4U) +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT (2U) +/*! SDR104_NSD_DIS + * 0b0..Enable the interrupt window 9 cycles later after the end of the I/O abort command (or CMD12) is sent. + * 0b1..Enable the interrupt window 5 cycles later after the end of the I/O abort command (or CMD12) is sent. + */ +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK) + +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) +/*! CARD_INT_D3_TEST - Card Interrupt Detection Test + * 0b0..Check the card interrupt only when DATA3 is high. + * 0b1..Check the card interrupt by ignoring the status of DATA3. + */ +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) + +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) +/*! TUNING_8bit_EN + * 0b0..Tuning circuit only checks the DATA[3:0]. + * 0b1..Tuning circuit only checks the DATA0. + */ +#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) + +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) + +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) +/*! TUNING_CMD_EN + * 0b0..Auto tuning circuit does not check the CMD line. + * 0b1..Auto tuning circuit checks the CMD line. + */ +#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) + +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK (0x80U) +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT (7U) +/*! CARD_INT_AUTO_CLR_DIS + * 0b0..Card interrupt status bit (CINT) can be cleared when Card Interrupt status enable bit is 0. + * 0b1..Card interrupt status bit (CINT) can only be cleared by writting a 1 to CINT bit. + */ +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK) + +#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U) +#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U) +/*! HS400_WR_CLK_STOP_EN - HS400 Write Clock Stop Enable + */ +#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK) + +#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U) +#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U) +/*! HS400_RD_CLK_STOP_EN - HS400 Read Clock Stop Enable + */ +#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK) +/*! @} */ + +/*! @name TUNING_CTRL - Tuning Control Register */ +/*! @{ */ + +#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) +#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) +#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) + +#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) + +#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) +#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) +#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) + +#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) + +#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USDHC_Register_Masks */ + + +/* USDHC - Peripheral instance base addresses */ +/** Peripheral uSDHC1 base address */ +#define uSDHC1_BASE (0x30B40000u) +/** Peripheral uSDHC1 base pointer */ +#define uSDHC1 ((USDHC_Type *)uSDHC1_BASE) +/** Peripheral uSDHC2 base address */ +#define uSDHC2_BASE (0x30B50000u) +/** Peripheral uSDHC2 base pointer */ +#define uSDHC2 ((USDHC_Type *)uSDHC2_BASE) +/** Array initializer of USDHC peripheral base addresses */ +#define USDHC_BASE_ADDRS { 0u, uSDHC1_BASE, uSDHC2_BASE } +/** Array initializer of USDHC peripheral base pointers */ +#define USDHC_BASE_PTRS { (USDHC_Type *)0u, uSDHC1, uSDHC2 } +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn } + +/*! + * @} + */ /* end of group USDHC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ + __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ + __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ + __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ + __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name WCR - Watchdog Control Register */ +/*! @{ */ + +#define WDOG_WCR_WDZST_MASK (0x1U) +#define WDOG_WCR_WDZST_SHIFT (0U) +/*! WDZST + * 0b0..Continue timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ +#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) + +#define WDOG_WCR_WDBG_MASK (0x2U) +#define WDOG_WCR_WDBG_SHIFT (1U) +/*! WDBG + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ +#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) + +#define WDOG_WCR_WDE_MASK (0x4U) +#define WDOG_WCR_WDE_SHIFT (2U) +/*! WDE + * 0b0..Disable the Watchdog (Default). + * 0b1..Enable the Watchdog. + */ +#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) + +#define WDOG_WCR_WDT_MASK (0x8U) +#define WDOG_WCR_WDT_SHIFT (3U) +/*! WDT + * 0b0..No effect on WDOG_B (Default). + * 0b1..Assert WDOG_B upon a Watchdog Time-out event. + */ +#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) + +#define WDOG_WCR_SRS_MASK (0x10U) +#define WDOG_WCR_SRS_SHIFT (4U) +/*! SRS + * 0b0..Assert system reset signal. + * 0b1..No effect on the system (Default). + */ +#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) + +#define WDOG_WCR_WDA_MASK (0x20U) +#define WDOG_WCR_WDA_SHIFT (5U) +/*! WDA + * 0b0..Assert WDOG_B output. + * 0b1..No effect on system (Default). + */ +#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) + +#define WDOG_WCR_SRE_MASK (0x40U) +#define WDOG_WCR_SRE_SHIFT (6U) +/*! SRE - Software Reset Extension. Required to be set to 1 when used in conjunction with the Software Reset Signal (SRS). + * 0b0..Reserved + * 0b1..This bit must be set to 1. + */ +#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) + +#define WDOG_WCR_WDW_MASK (0x80U) +#define WDOG_WCR_WDW_SHIFT (7U) +/*! WDW + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend WDOG timer operation. + */ +#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) + +#define WDOG_WCR_WT_MASK (0xFF00U) +#define WDOG_WCR_WT_SHIFT (8U) +/*! WT + * 0b00000000..- 0.5 Seconds (Default). + * 0b00000001..- 1.0 Seconds. + * 0b00000010..- 1.5 Seconds. + * 0b00000011..- 2.0 Seconds. + * 0b11111111..- 128 Seconds. + */ +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) +/*! @} */ + +/*! @name WSR - Watchdog Service Register */ +/*! @{ */ + +#define WDOG_WSR_WSR_MASK (0xFFFFU) +#define WDOG_WSR_WSR_SHIFT (0U) +/*! WSR + * 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR). + * 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR). + */ +#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) +/*! @} */ + +/*! @name WRSR - Watchdog Reset Status Register */ +/*! @{ */ + +#define WDOG_WRSR_SFTW_MASK (0x1U) +#define WDOG_WRSR_SFTW_SHIFT (0U) +/*! SFTW + * 0b0..Reset is not the result of a software reset. + * 0b1..Reset is the result of a software reset. + */ +#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) + +#define WDOG_WRSR_TOUT_MASK (0x2U) +#define WDOG_WRSR_TOUT_SHIFT (1U) +/*! TOUT + * 0b0..Reset is not the result of a WDOG timeout. + * 0b1..Reset is the result of a WDOG timeout. + */ +#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) + +#define WDOG_WRSR_POR_MASK (0x10U) +#define WDOG_WRSR_POR_SHIFT (4U) +/*! POR + * 0b0..Reset is not the result of a power on reset. + * 0b1..Reset is the result of a power on reset. + */ +#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) +/*! @} */ + +/*! @name WICR - Watchdog Interrupt Control Register */ +/*! @{ */ + +#define WDOG_WICR_WICT_MASK (0xFFU) +#define WDOG_WICR_WICT_SHIFT (0U) +/*! WICT + * 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + * 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + * 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + * 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + */ +#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) + +#define WDOG_WICR_WTIS_MASK (0x4000U) +#define WDOG_WICR_WTIS_SHIFT (14U) +/*! WTIS + * 0b0..No interrupt has occurred (Default). + * 0b1..Interrupt has occurred + */ +#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) + +#define WDOG_WICR_WIE_MASK (0x8000U) +#define WDOG_WICR_WIE_SHIFT (15U) +/*! WIE + * 0b0..Disable Interrupt (Default). + * 0b1..Enable Interrupt. + */ +#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) +/*! @} */ + +/*! @name WMCR - Watchdog Miscellaneous Control Register */ +/*! @{ */ + +#define WDOG_WMCR_PDE_MASK (0x1U) +#define WDOG_WMCR_PDE_SHIFT (0U) +/*! PDE + * 0b0..Power Down Counter of WDOG is disabled. + * 0b1..Power Down Counter of WDOG is enabled (Default). + */ +#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG1 base address */ +#define WDOG1_BASE (0x30280000u) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +/** Peripheral WDOG2 base address */ +#define WDOG2_BASE (0x30290000u) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +/** Peripheral WDOG3 base address */ +#define WDOG3_BASE (0x302A0000u) +/** Peripheral WDOG3 base pointer */ +#define WDOG3 ((WDOG_Type *)WDOG3_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE, WDOG3_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2, WDOG3 } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn } + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WR_SCL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WR_SCL_Peripheral_Access_Layer WR_SCL Peripheral Access Layer + * @{ + */ + +/** WR_SCL - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< Control register for Context Loader., offset: 0x0 */ + __IO uint32_t SET; /**< Control register for Context Loader., offset: 0x4 */ + __IO uint32_t CLR; /**< Control register for Context Loader., offset: 0x8 */ + __IO uint32_t TOG; /**< Control register for Context Loader., offset: 0xC */ + } CTRL_STATUS; + __IO uint32_t BASE_ADDR; /**< Holds the base address, offset: 0x10 */ + __IO uint32_t PITCH; /**< Pitch, offset: 0x14 */ +} WR_SCL_Type; + +/* ---------------------------------------------------------------------------- + -- WR_SCL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WR_SCL_Register_Masks WR_SCL Register Masks + * @{ + */ + +/*! @name CTRL_STATUS - Control register for Context Loader. */ +/*! @{ */ + +#define WR_SCL_CTRL_STATUS_ENABLE_MASK (0x1U) +#define WR_SCL_CTRL_STATUS_ENABLE_SHIFT (0U) +/*! ENABLE - Enable / Busy + */ +#define WR_SCL_CTRL_STATUS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_ENABLE_SHIFT)) & WR_SCL_CTRL_STATUS_ENABLE_MASK) + +#define WR_SCL_CTRL_STATUS_REPEAT_MASK (0x2U) +#define WR_SCL_CTRL_STATUS_REPEAT_SHIFT (1U) +/*! REPEAT - Repeat feature + */ +#define WR_SCL_CTRL_STATUS_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_REPEAT_SHIFT)) & WR_SCL_CTRL_STATUS_REPEAT_MASK) + +#define WR_SCL_CTRL_STATUS_BPP_MASK (0x1CU) +#define WR_SCL_CTRL_STATUS_BPP_SHIFT (2U) +/*! BPP - Bits per pixel + */ +#define WR_SCL_CTRL_STATUS_BPP(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_BPP_SHIFT)) & WR_SCL_CTRL_STATUS_BPP_MASK) + +#define WR_SCL_CTRL_STATUS_T_SIZE_MASK (0x60U) +#define WR_SCL_CTRL_STATUS_T_SIZE_SHIFT (5U) +/*! T_SIZE - Transaction Size + */ +#define WR_SCL_CTRL_STATUS_T_SIZE(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_T_SIZE_SHIFT)) & WR_SCL_CTRL_STATUS_T_SIZE_MASK) + +#define WR_SCL_CTRL_STATUS_P_SIZE_MASK (0x380U) +#define WR_SCL_CTRL_STATUS_P_SIZE_SHIFT (7U) +/*! P_SIZE - Payload Size + */ +#define WR_SCL_CTRL_STATUS_P_SIZE(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_P_SIZE_SHIFT)) & WR_SCL_CTRL_STATUS_P_SIZE_MASK) + +#define WR_SCL_CTRL_STATUS_P_FREQ_MASK (0x3FC00U) +#define WR_SCL_CTRL_STATUS_P_FREQ_SHIFT (10U) +/*! P_FREQ - Payload frequency + */ +#define WR_SCL_CTRL_STATUS_P_FREQ(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_P_FREQ_SHIFT)) & WR_SCL_CTRL_STATUS_P_FREQ_MASK) + +#define WR_SCL_CTRL_STATUS_FIFO_SIZE_MASK (0x1FC0000U) +#define WR_SCL_CTRL_STATUS_FIFO_SIZE_SHIFT (18U) +/*! FIFO_SIZE - Size of FIFO in design + */ +#define WR_SCL_CTRL_STATUS_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_FIFO_SIZE_SHIFT)) & WR_SCL_CTRL_STATUS_FIFO_SIZE_MASK) + +#define WR_SCL_CTRL_STATUS_FRAME_COMP_EN_MASK (0x10000000U) +#define WR_SCL_CTRL_STATUS_FRAME_COMP_EN_SHIFT (28U) +/*! FRAME_COMP_EN - Write error IRQ enable + */ +#define WR_SCL_CTRL_STATUS_FRAME_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_FRAME_COMP_EN_SHIFT)) & WR_SCL_CTRL_STATUS_FRAME_COMP_EN_MASK) + +#define WR_SCL_CTRL_STATUS_FRAME_COMP_MASK (0x20000000U) +#define WR_SCL_CTRL_STATUS_FRAME_COMP_SHIFT (29U) +/*! FRAME_COMP - Indicates the current frame being processed has finished. + */ +#define WR_SCL_CTRL_STATUS_FRAME_COMP(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_FRAME_COMP_SHIFT)) & WR_SCL_CTRL_STATUS_FRAME_COMP_MASK) + +#define WR_SCL_CTRL_STATUS_WR_ERR_EN_MASK (0x40000000U) +#define WR_SCL_CTRL_STATUS_WR_ERR_EN_SHIFT (30U) +/*! WR_ERR_EN - Write error IRQ enable + */ +#define WR_SCL_CTRL_STATUS_WR_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_WR_ERR_EN_SHIFT)) & WR_SCL_CTRL_STATUS_WR_ERR_EN_MASK) + +#define WR_SCL_CTRL_STATUS_WR_ERR_MASK (0x80000000U) +#define WR_SCL_CTRL_STATUS_WR_ERR_SHIFT (31U) +/*! WR_ERR - Indicates a write error on the axi interface. + */ +#define WR_SCL_CTRL_STATUS_WR_ERR(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_WR_ERR_SHIFT)) & WR_SCL_CTRL_STATUS_WR_ERR_MASK) +/*! @} */ + +/*! @name BASE_ADDR - Holds the base address */ +/*! @{ */ + +#define WR_SCL_BASE_ADDR_BASE_ADDR_MASK (0xFFFFFFFFU) +#define WR_SCL_BASE_ADDR_BASE_ADDR_SHIFT (0U) +/*! BASE_ADDR - Base address + */ +#define WR_SCL_BASE_ADDR_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_BASE_ADDR_BASE_ADDR_SHIFT)) & WR_SCL_BASE_ADDR_BASE_ADDR_MASK) +/*! @} */ + +/*! @name PITCH - Pitch */ +/*! @{ */ + +#define WR_SCL_PITCH_PITCH_MASK (0xFFFFU) +#define WR_SCL_PITCH_PITCH_SHIFT (0U) +/*! PITCH - Vertical pitch for memory address calculation. + */ +#define WR_SCL_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_PITCH_PITCH_SHIFT)) & WR_SCL_PITCH_PITCH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WR_SCL_Register_Masks */ + + +/* WR_SCL - Peripheral instance base addresses */ +/** Peripheral DCSS__WR_SCL base address */ +#define DCSS__WR_SCL_BASE (0x32E21000u) +/** Peripheral DCSS__WR_SCL base pointer */ +#define DCSS__WR_SCL ((WR_SCL_Type *)DCSS__WR_SCL_BASE) +/** Array initializer of WR_SCL peripheral base addresses */ +#define WR_SCL_BASE_ADDRS { DCSS__WR_SCL_BASE } +/** Array initializer of WR_SCL peripheral base pointers */ +#define WR_SCL_BASE_PTRS { DCSS__WR_SCL } + +/*! + * @} + */ /* end of group WR_SCL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XTALOSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC_Peripheral_Access_Layer XTALOSC Peripheral Access Layer + * @{ + */ + +/** XTALOSC - Register Layout Typedef */ +typedef struct { + __IO uint32_t OSC25M_CTL_CFG; /**< 25M Oscillator Control Configuration Register, offset: 0x0 */ + __IO uint32_t OSC25M_TEST_CFG; /**< 25M Oscillator Test Configuration Register, offset: 0x4 */ + uint8_t RESERVED_0[32760]; + __IO uint32_t OSC27M_CTL_CFG; /**< 27M Oscillator Control Configuration Register, offset: 0x8000 */ + __IO uint32_t OSC27M_TEST_CFG; /**< 27M Oscillator Test Configuration Register, offset: 0x8004 */ +} XTALOSC_Type; + +/* ---------------------------------------------------------------------------- + -- XTALOSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC_Register_Masks XTALOSC Register Masks + * @{ + */ + +/*! @name OSC25M_CTL_CFG - 25M Oscillator Control Configuration Register */ +/*! @{ */ + +#define XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL_MASK (0x4U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL_SHIFT (2U) +/*! OSC_ALC_CTL + * 0b0..Enable automatic level controller + * 0b1..Disable automatic level controller + */ +#define XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL_MASK) + +#define XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL_MASK (0x8U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL_SHIFT (3U) +/*! OSC_HYST_CTL + * 0b0..Enable hysteresis control + * 0b1..Disable hysteresis control + */ +#define XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL_MASK) + +#define XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL_MASK (0x70U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL_SHIFT (4U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL_MASK) + +#define XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU_MASK (0x80U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU_SHIFT (7U) +/*! OSC_INT_STU + * 0b0..No oscillator clock interrupt occurred + * 0b1..Oscillator clock interrupt pending + */ +#define XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU_MASK) + +#define XTALOSC_OSC25M_CTL_CFG_OSC_DIV_MASK (0x1F00U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_DIV_SHIFT (8U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_DIV_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_DIV_MASK) + +#define XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS_MASK (0x2000U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS_SHIFT (13U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS_MASK) + +#define XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK_MASK (0x8000U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK_SHIFT (15U) +/*! OSC_INT_MASK + * 0b0..Crystal oscillator clock interrupt is masked + * 0b1..Crystal oscillator clock interrupt is enabled + */ +#define XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK_MASK) + +#define XTALOSC_OSC25M_CTL_CFG_OSC_EOCV_MASK (0xFF0000U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_EOCV_SHIFT (16U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_EOCV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_EOCV_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_EOCV_MASK) + +#define XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL_MASK (0x40000000U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL_SHIFT (30U) +/*! OSC_GM_TST_SEL + * 0b0..Normal run mode + * 0b1..Enable test mode measurement of GM + */ +#define XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL_MASK) + +#define XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_MASK (0x80000000U) +#define XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_SHIFT (31U) +/*! OSC_BYPSS + * 0b0..Oscillator output is used as root clock. + * 0b1..EXTAL is used as root clock + */ +#define XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_MASK) +/*! @} */ + +/*! @name OSC25M_TEST_CFG - 25M Oscillator Test Configuration Register */ +/*! @{ */ + +#define XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN_MASK (0x80000000U) +#define XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN_SHIFT (31U) +#define XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN_SHIFT)) & XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN_MASK) +/*! @} */ + +/*! @name OSC27M_CTL_CFG - 27M Oscillator Control Configuration Register */ +/*! @{ */ + +#define XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL_MASK (0x4U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL_SHIFT (2U) +/*! OSC_ALC_CTL + * 0b0..Enable automatic level controller + * 0b1..Disable automatic level controller + */ +#define XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL_MASK) + +#define XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL_MASK (0x8U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL_SHIFT (3U) +/*! OSC_HYST_CTL + * 0b0..Enable hysteresis control + * 0b1..Disable hysteresis control + */ +#define XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL_MASK) + +#define XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL_MASK (0x70U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL_SHIFT (4U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL_MASK) + +#define XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU_MASK (0x80U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU_SHIFT (7U) +/*! OSC_INT_STU + * 0b0..No oscillator clock interrupt occurred + * 0b1..Oscillator clock interrupt pending + */ +#define XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU_MASK) + +#define XTALOSC_OSC27M_CTL_CFG_OSC_DIV_MASK (0x1F00U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_DIV_SHIFT (8U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_DIV_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_DIV_MASK) + +#define XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS_MASK (0x2000U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS_SHIFT (13U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS_MASK) + +#define XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK_MASK (0x8000U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK_SHIFT (15U) +/*! OSC_INT_MASK + * 0b0..Crystal oscillator clock interrupt is masked + * 0b1..Crystal oscillator clock interrupt is enabled + */ +#define XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK_MASK) + +#define XTALOSC_OSC27M_CTL_CFG_OSC_EOCV_MASK (0xFF0000U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_EOCV_SHIFT (16U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_EOCV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_EOCV_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_EOCV_MASK) + +#define XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL_MASK (0x40000000U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL_SHIFT (30U) +/*! OSC_GM_TST_SEL + * 0b0..Normal run mode + * 0b1..Enable test mode measurement of GM + */ +#define XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL_MASK) + +#define XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_MASK (0x80000000U) +#define XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_SHIFT (31U) +/*! OSC_BYPSS + * 0b0..Oscillator output is used as root clock. + * 0b1..EXTAL is used as root clock + */ +#define XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_MASK) +/*! @} */ + +/*! @name OSC27M_TEST_CFG - 27M Oscillator Test Configuration Register */ +/*! @{ */ + +#define XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN_MASK (0x80000000U) +#define XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN_SHIFT (31U) +#define XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN_SHIFT)) & XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XTALOSC_Register_Masks */ + + +/* XTALOSC - Peripheral instance base addresses */ +/** Peripheral XTALOSC base address */ +#define XTALOSC_BASE (0x30270000u) +/** Peripheral XTALOSC base pointer */ +#define XTALOSC ((XTALOSC_Type *)XTALOSC_BASE) +/** Array initializer of XTALOSC peripheral base addresses */ +#define XTALOSC_BASE_ADDRS { XTALOSC_BASE } +/** Array initializer of XTALOSC peripheral base pointers */ +#define XTALOSC_BASE_PTRS { XTALOSC } + +/*! + * @} + */ /* end of group XTALOSC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MIMX8MQ6_CM4_H_ */ + diff --git a/devices/MIMX8MQ6/MIMX8MQ6_cm4.xml b/devices/MIMX8MQ6/MIMX8MQ6_cm4.xml new file mode 100644 index 000000000..dab148fa3 --- /dev/null +++ b/devices/MIMX8MQ6/MIMX8MQ6_cm4.xml @@ -0,0 +1,408262 @@ + + + nxp.com + MIMX8MQ6_cm4 + 1.0 + MIMX8MQ6CVAHZ,MIMX8MQ6DVAJZ + +Copyright 2016-2018 NXP + +SPDX-License-Identifier: BSD-3-Clause + + + CM4 + r0p1 + little + true + true + true + 4 + false + + 8 + 32 + + + I2S1 + I2S + SAI + SAI + 0x30010000 + + 0 + 0xE4 + registers + + + I2S1 + 95 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x3000000 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_0 + Standard feature set. + 0 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x50708 + 0xFFFFFFFF + + + DATALINE + Number of Datalines + 0 + 4 + read-only + + + FIFO + FIFO Size + 8 + 4 + read-only + + + FRAME + Frame Size + 16 + 4 + read-only + + + + + TCSR + SAI Transmit Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 10 + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 11 + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 12 + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 16 + 1 + read-only + + + FRF_0 + Transmit FIFO watermark has not been reached. + 0 + + + FRF_1 + Transmit FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 17 + 1 + read-only + + + FWF_0 + No enabled transmit FIFO is empty. + 0 + + + FWF_1 + Enabled transmit FIFO is empty. + 0x1 + + + + + FEF + FIFO Error Flag + 18 + 1 + read-write + oneToClear + + + FEF_0 + Transmit underrun not detected. + 0 + + + FEF_1 + Transmit underrun detected. + 0x1 + + + + + SEF + Sync Error Flag + 19 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 20 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 24 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 25 + 1 + write-only + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 28 + 1 + read-write + + + BCE_0 + Transmit bit clock is disabled. + 0 + + + BCE_1 + Transmit bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 29 + 1 + read-write + + + DBGE_0 + Transmitter is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Transmitter is enabled in Debug mode. + 0x1 + + + + + TE + Transmitter Enable + 31 + 1 + read-write + + + TE_0 + Transmitter is disabled. + 0 + + + TE_1 + Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + TCR1 + SAI Transmit Configuration 1 Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TFW + Transmit FIFO Watermark + 0 + 7 + read-write + + + + + TCR2 + SAI Transmit Configuration 2 Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 24 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 25 + 1 + read-write + + + BCP_0 + Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 26 + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 28 + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 29 + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 30 + 2 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with receiver. + 0x1 + + + + + + + TCR3 + SAI Transmit Configuration 3 Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + TCE + Transmit Channel Enable + 16 + 8 + read-write + + + CFR + Channel FIFO Reset + 24 + 8 + write-only + + + + + TCR4 + SAI Transmit Configuration 4 Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + ONDEM + On Demand Mode + 2 + 1 + read-write + + + ONDEM_0 + Internal frame sync is generated continuously. + 0 + + + ONDEM_1 + Internal frame sync is generated when the FIFO warning flag is clear. + 0x1 + + + + + FSE + Frame Sync Early + 3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 4 + 1 + read-write + + + MF_0 + LSB is transmitted first. + 0 + + + MF_1 + MSB is transmitted first. + 0x1 + + + + + CHMOD + Channel Mode + 5 + 1 + read-write + + + CHMOD_0 + TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. + 0 + + + CHMOD_1 + Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. + 0x1 + + + + + SYWD + Sync Width + 8 + 5 + read-write + + + FRSZ + Frame size + 16 + 5 + read-write + + + FPACK + FIFO Packing Mode + 24 + 2 + read-write + + + FPACK_0 + FIFO packing is disabled + 0 + + + FPACK_2 + 8-bit FIFO packing is enabled + 0x2 + + + FPACK_3 + 16-bit FIFO packing is enabled + 0x3 + + + + + FCOMB + FIFO Combine Mode + 26 + 2 + read-write + + + FCOMB_0 + FIFO combine mode disabled. + 0 + + + FCOMB_1 + FIFO combine mode enabled on FIFO reads (from transmit shift registers). + 0x1 + + + FCOMB_2 + FIFO combine mode enabled on FIFO writes (by software). + 0x2 + + + FCOMB_3 + FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + 0x3 + + + + + FCONT + FIFO Continue on Error + 28 + 1 + read-write + + + FCONT_0 + On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + 0 + + + FCONT_1 + On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + 0x1 + + + + + + + TCR5 + SAI Transmit Configuration 5 Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 8 + 5 + read-write + + + W0W + Word 0 Width + 16 + 5 + read-write + + + WNW + Word N Width + 24 + 5 + read-write + + + + + 8 + 0x4 + TDR[%s] + SAI Transmit Data Register + 0x20 + 32 + write-only + 0 + 0xFFFFFFFF + + + TDR + Transmit Data Register + 0 + 32 + write-only + + + + + 8 + 0x4 + TFR[%s] + SAI Transmit FIFO Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 8 + read-only + + + WFP + Write FIFO Pointer + 16 + 8 + read-only + + + WCP + Write Channel Pointer + 31 + 1 + read-only + + + WCP_0 + No effect. + 0 + + + WCP_1 + FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + 0x1 + + + + + + + TMR + SAI Transmit Mask Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + TWM + Transmit Word Mask + 0 + 32 + read-write + + + TWM_0 + Word N is enabled. + 0 + + + TWM_1 + Word N is masked. The transmit data pins are tri-stated or drive zero when masked. + 0x1 + + + + + + + RCSR + SAI Receive Control Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 10 + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 11 + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 12 + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 16 + 1 + read-only + + + FRF_0 + Receive FIFO watermark not reached. + 0 + + + FRF_1 + Receive FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 17 + 1 + read-only + + + FWF_0 + No enabled receive FIFO is full. + 0 + + + FWF_1 + Enabled receive FIFO is full. + 0x1 + + + + + FEF + FIFO Error Flag + 18 + 1 + read-write + oneToClear + + + FEF_0 + Receive overflow not detected. + 0 + + + FEF_1 + Receive overflow detected. + 0x1 + + + + + SEF + Sync Error Flag + 19 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 20 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 24 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 25 + 1 + write-only + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 28 + 1 + read-write + + + BCE_0 + Receive bit clock is disabled. + 0 + + + BCE_1 + Receive bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 29 + 1 + read-write + + + DBGE_0 + Receiver is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Receiver is enabled in Debug mode. + 0x1 + + + + + RE + Receiver Enable + 31 + 1 + read-write + + + RE_0 + Receiver is disabled. + 0 + + + RE_1 + Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + RCR1 + SAI Receive Configuration 1 Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + RFW + Receive FIFO Watermark + 0 + 7 + read-write + + + + + RCR2 + SAI Receive Configuration 2 Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 24 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 25 + 1 + read-write + + + BCP_0 + Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 26 + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 28 + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 29 + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 30 + 2 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with transmitter. + 0x1 + + + + + + + RCR3 + SAI Receive Configuration 3 Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + RCE + Receive Channel Enable + 16 + 8 + read-write + + + CFR + Channel FIFO Reset + 24 + 8 + write-only + + + + + RCR4 + SAI Receive Configuration 4 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame Sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame Sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + ONDEM + On Demand Mode + 2 + 1 + read-write + + + ONDEM_0 + Internal frame sync is generated continuously. + 0 + + + ONDEM_1 + Internal frame sync is generated when the FIFO warning flag is clear. + 0x1 + + + + + FSE + Frame Sync Early + 3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 4 + 1 + read-write + + + MF_0 + LSB is received first. + 0 + + + MF_1 + MSB is received first. + 0x1 + + + + + SYWD + Sync Width + 8 + 5 + read-write + + + FRSZ + Frame Size + 16 + 5 + read-write + + + FPACK + FIFO Packing Mode + 24 + 2 + read-write + + + FPACK_0 + FIFO packing is disabled + 0 + + + FPACK_2 + 8-bit FIFO packing is enabled + 0x2 + + + FPACK_3 + 16-bit FIFO packing is enabled + 0x3 + + + + + FCOMB + FIFO Combine Mode + 26 + 2 + read-write + + + FCOMB_0 + FIFO combine mode disabled. + 0 + + + FCOMB_1 + FIFO combine mode enabled on FIFO writes (from receive shift registers). + 0x1 + + + FCOMB_2 + FIFO combine mode enabled on FIFO reads (by software). + 0x2 + + + FCOMB_3 + FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + 0x3 + + + + + FCONT + FIFO Continue on Error + 28 + 1 + read-write + + + FCONT_0 + On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + 0 + + + FCONT_1 + On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + 0x1 + + + + + + + RCR5 + SAI Receive Configuration 5 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 8 + 5 + read-write + + + W0W + Word 0 Width + 16 + 5 + read-write + + + WNW + Word N Width + 24 + 5 + read-write + + + + + 8 + 0x4 + RDR[%s] + SAI Receive Data Register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDR + Receive Data Register + 0 + 32 + read-only + + + + + 8 + 0x4 + RFR[%s] + SAI Receive FIFO Register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 8 + read-only + + + RCP + Receive Channel Pointer + 15 + 1 + read-only + + + RCP_0 + No effect. + 0 + + + RCP_1 + FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. + 0x1 + + + + + WFP + Write FIFO Pointer + 16 + 8 + read-only + + + + + RMR + SAI Receive Mask Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RWM + Receive Word Mask + 0 + 32 + read-write + + + RWM_0 + Word N is enabled. + 0 + + + RWM_1 + Word N is masked. + 0x1 + + + + + + + + + I2S6 + I2S + SAI + 0x30030000 + + 0 + 0xE4 + registers + + + I2S56 + 90 + + + + I2S5 + I2S + SAI + 0x30040000 + + 0 + 0xE4 + registers + + + I2S56 + 90 + + + + I2S4 + I2S + SAI + 0x30050000 + + 0 + 0xE4 + registers + + + I2S4 + 100 + + + + I2S2 + I2S + SAI + 0x308B0000 + + 0 + 0xE4 + registers + + + I2S2 + 96 + + + + I2S3 + I2S + SAI + 0x308C0000 + + 0 + 0xE4 + registers + + + I2S3 + 50 + + + + AIPSTZ1 + AIPSTZ + AIPSTZ + AIPSTZ + 0x301F0000 + + 0 + 0x54 + registers + + + + MPR + MPR + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MPROT5 + MPROT5. + 8 + 4 + read-write + + + MPROT3 + MPROT3. + 16 + 4 + read-write + + + MPROT2 + MPROT2. + 20 + 4 + read-write + + + MPROT1 + MPROT1. + 24 + 4 + read-write + + + MPROT0 + MPROT0. + 28 + 4 + read-write + + + + + OPACR + OPACR + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + OPAC7 + OPAC7. + 0 + 4 + read-write + + + OPAC6 + OPAC6. + 4 + 4 + read-write + + + OPAC5 + OPAC5. + 8 + 4 + read-write + + + OPAC4 + OPAC4. + 12 + 4 + read-write + + + OPAC3 + OPAC3. + 16 + 4 + read-write + + + OPAC2 + OPAC2. + 20 + 4 + read-write + + + OPAC1 + OPAC1. + 24 + 4 + read-write + + + OPAC0 + OPAC0. + 28 + 4 + read-write + + + + + OPACR1 + OPACR1 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + OPAC15 + OPAC15. + 0 + 4 + read-write + + + OPAC14 + OPAC14. + 4 + 4 + read-write + + + OPAC13 + OPAC13. + 8 + 4 + read-write + + + OPAC12 + OPAC12. + 12 + 4 + read-write + + + OPAC11 + OPAC11. + 16 + 4 + read-write + + + OPAC10 + OPAC10. + 20 + 4 + read-write + + + OPAC9 + OPAC9. + 24 + 4 + read-write + + + OPAC8 + OPAC8. + 28 + 4 + read-write + + + + + OPACR2 + OPACR2 + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + OPAC23 + OPAC23. + 0 + 4 + read-write + + + OPAC22 + OPAC22. + 4 + 4 + read-write + + + OPAC21 + OPAC21. + 8 + 4 + read-write + + + OPAC20 + OPAC20. + 12 + 4 + read-write + + + OPAC19 + OPAC19. + 16 + 4 + read-write + + + OPAC18 + OPAC18. + 20 + 4 + read-write + + + OPAC17 + OPAC17. + 24 + 4 + read-write + + + OPAC16 + OPAC16. + 28 + 4 + read-write + + + + + OPACR3 + OPACR3 + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + OPAC31 + OPAC31. + 0 + 4 + read-write + + + OPAC30 + OPAC30. + 4 + 4 + read-write + + + OPAC29 + OPAC29. + 8 + 4 + read-write + + + OPAC28 + OPAC28. + 12 + 4 + read-write + + + OPAC27 + OPAC27. + 16 + 4 + read-write + + + OPAC26 + OPAC26. + 20 + 4 + read-write + + + OPAC25 + OPAC25. + 24 + 4 + read-write + + + OPAC24 + OPAC24. + 28 + 4 + read-write + + + + + OPACR4 + OPACR4 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + OPAC33 + OPAC33. + 24 + 4 + read-write + + + OPAC32 + OPAC32. + 28 + 4 + read-write + + + + + + + AIPSTZ2 + AIPSTZ + AIPSTZ + 0x305F0000 + + 0 + 0x54 + registers + + + + AIPSTZ3 + AIPSTZ + AIPSTZ + 0x309F0000 + + 0 + 0x54 + registers + + + + AIPSTZ4 + AIPSTZ + AIPSTZ + 0x32DF0000 + + 0 + 0x54 + registers + + + + GPIO1 + GPIO + GPIO + GPIO1_ + GPIO + 0x30200000 + + 0 + 0x20 + registers + + + GPIO1_INT7 + 56 + + + GPIO1_INT6 + 57 + + + GPIO1_INT5 + 58 + + + GPIO1_INT4 + 59 + + + GPIO1_INT3 + 60 + + + GPIO1_INT2 + 61 + + + GPIO1_INT1 + 62 + + + GPIO1_INT0 + 63 + + + GPIO1_Combined_0_15 + 64 + + + GPIO1_Combined_16_31 + 65 + + + + DR + GPIO data register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DR + Data bits + 0 + 32 + read-write + + + + + GDIR + GPIO direction register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GDIR + GPIO direction bits + 0 + 32 + read-write + + + INPUT + GPIO is configured as input. + 0 + + + OUTPUT + GPIO is configured as output. + 0x1 + + + + + + + PSR + GPIO pad status register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PSR + GPIO pad status bits (status bits) + 0 + 32 + read-only + + + + + ICR1 + GPIO interrupt configuration register1 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR0 + Interrupt configuration 1 fields + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR1 + Interrupt configuration 1 fields + 2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR2 + Interrupt configuration 1 fields + 4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR3 + Interrupt configuration 1 fields + 6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR4 + Interrupt configuration 1 fields + 8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR5 + Interrupt configuration 1 fields + 10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR6 + Interrupt configuration 1 fields + 12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR7 + Interrupt configuration 1 fields + 14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR8 + Interrupt configuration 1 fields + 16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR9 + Interrupt configuration 1 fields + 18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR10 + Interrupt configuration 1 fields + 20 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR11 + Interrupt configuration 1 fields + 22 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR12 + Interrupt configuration 1 fields + 24 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR13 + Interrupt configuration 1 fields + 26 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR14 + Interrupt configuration 1 fields + 28 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR15 + Interrupt configuration 1 fields + 30 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + ICR2 + GPIO interrupt configuration register2 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR16 + Interrupt configuration 2 fields + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR17 + Interrupt configuration 2 fields + 2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR18 + Interrupt configuration 2 fields + 4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR19 + Interrupt configuration 2 fields + 6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR20 + Interrupt configuration 2 fields + 8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR21 + Interrupt configuration 2 fields + 10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR22 + Interrupt configuration 2 fields + 12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR23 + Interrupt configuration 2 fields + 14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR24 + Interrupt configuration 2 fields + 16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR25 + Interrupt configuration 2 fields + 18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR26 + Interrupt configuration 2 fields + 20 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR27 + Interrupt configuration 2 fields + 22 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR28 + Interrupt configuration 2 fields + 24 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR29 + Interrupt configuration 2 fields + 26 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR30 + Interrupt configuration 2 fields + 28 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR31 + Interrupt configuration 2 fields + 30 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + IMR + GPIO interrupt mask register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR + Interrupt Mask bits + 0 + 32 + read-write + + + MASKED + Interrupt n is disabled. + 0 + + + UNMASKED + Interrupt n is enabled. + 0x1 + + + + + + + ISR + GPIO interrupt status register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISR + Interrupt status bits - Bit n of this register is asserted (active high) when the active condition (as determined by the corresponding ICR bit) is detected on the GPIO input and is waiting for service + 0 + 32 + read-write + oneToClear + + + + + EDGE_SEL + GPIO edge select register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO_EDGE_SEL + Edge select + 0 + 32 + read-write + + + + + + + GPIO2 + GPIO + GPIO + GPIO2_ + 0x30210000 + + 0 + 0x20 + registers + + + GPIO2_Combined_0_15 + 66 + + + GPIO2_Combined_16_31 + 67 + + + + GPIO3 + GPIO + GPIO + GPIO3_ + 0x30220000 + + 0 + 0x20 + registers + + + GPIO3_Combined_0_15 + 68 + + + GPIO3_Combined_16_31 + 69 + + + + GPIO4 + GPIO + GPIO + GPIO4_ + 0x30230000 + + 0 + 0x20 + registers + + + GPIO4_Combined_0_15 + 70 + + + GPIO4_Combined_16_31 + 71 + + + + GPIO5 + GPIO + GPIO + GPIO5_ + 0x30240000 + + 0 + 0x20 + registers + + + GPIO5_Combined_0_15 + 72 + + + GPIO5_Combined_16_31 + 73 + + + + TMU + TMU + TMU + TMU_ + 0x30260000 + + 0 + 0xF20 + registers + + + + TMR + TMU Mode register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSITE + Monitoring site select + 0 + 16 + read-write + + + ALPF + Average low pass filter setting + 26 + 2 + read-write + + + ALPF_0 + 1.0 + 0 + + + ALPF_1 + 0.5 + 0x1 + + + ALPF_2 + 0.25 + 0x2 + + + ALPF_3 + 0.125 + 0x3 + + + + + ME + Monitor mode enable + 31 + 1 + read-write + + + ME_0 + No monitoring. Power saving mode. + 0 + + + ME_1 + Monitoring of sites as defined by MSITE. + 0x1 + + + + + + + TSR + TMU Status register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + ORH + Out-of-range high temperature measurement detected + 28 + 1 + read-only + + + ORL + Out-of-range low temperature measurement detected + 29 + 1 + read-only + + + MIE + Monitoring interval exceeded + 30 + 1 + read-only + + + MIE_0 + Monitoring interval not exceeded. + 0 + + + MIE_1 + Monitoring interval exceeded. The time required to perform measurement of all monitored sites has exceeded the monitoring interval as defined by TMTMIR. + 0x1 + + + + + + + TMTMIR + TMU Monitor Temperature Measurement Interval register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TMI + Temperature monitoring interval in seconds + 0 + 4 + read-write + + + + + TIER + TMU Interrupt Enable register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATCTEIE + Average temperature critical threshold exceeded interrupt enable. + 29 + 1 + read-write + + + ATCTEIE_0 + Disabled. + 0 + + + ATCTEIE_1 + Interrupt enabled. Generate an interrupt if TIDR[ATCTE] is set. + 0x1 + + + + + ATTEIE + Average temperature threshold exceeded interrupt enable. + 30 + 1 + read-write + + + ATTEIE_0 + Disabled. + 0 + + + ATTEIE_1 + Interrupt enabled. Generate an interrupt if TIDR[ATTE] is set. + 0x1 + + + + + ITTEIE + Immediate temperature threshold exceeded interrupt enable. + 31 + 1 + read-write + + + ITTEIE_0 + Disabled. + 0 + + + ITTEIE_1 + Interrupt enabled. Generate an interrupt if TIDR[ITTE] is set. + 0x1 + + + + + + + TIDR + TMU Interrupt Detect register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATCTE + Average temperature critical threshold exceeded. Write 1 to clear. + 29 + 1 + read-write + oneToClear + + + ATCTE_0 + No threshold exceeded. + 0 + + + ATCTE_1 + Average temperature critical threshold, as defined by TMHTACTR, has been exceeded by one or more monitored sites. The sites which has exceeded the threshold are captured in TICSCR[CASITE]. + 0x1 + + + + + ATTE + Average temperature threshold exceeded. Write 1 to clear. + 30 + 1 + read-write + oneToClear + + + ATTE_0 + No threshold exceeded. + 0 + + + ATTE_1 + Average temperature threshold, as defined by TMHTATR, has been exceeded by one or more monitored sites. The sites which has exceeded the threshold are captured in TISCR[ASITE]. + 0x1 + + + + + ITTE + Immediate temperature threshold exceeded. Write 1 to clear. + 31 + 1 + read-write + oneToClear + + + ITTE_0 + No threshold exceeded. + 0 + + + ITTE_1 + Immediate temperature threshold, as defined by TMHTITR, has been exceeded by one or more monitored sites. This includes an out-of-range measured temperature above 125degree C. The sites which has exceeded the threshold are captured in TISCR[ISITE]. + 0x1 + + + + + + + TISCR + TMU Interrupt Site Capture register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ASITE + Temperature sensor site associated with the setting of TIDR[ATTE] + 0 + 16 + read-write + + + ISITE + Temperature sensor site associated with the setting of TIDR[ITTE] + 16 + 16 + read-write + + + + + TICSCR + TMU Interrupt Critical Site Capture register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + CASITE + Temperature sensor site associated with the setting of TIDR[ATCTE] + 0 + 16 + read-write + + + + + TMHTCRH + TMU Monitor High Temperature Capture register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + TEMP + Highest temperature recorded in degrees Celsius by any enabled monitored site + 0 + 8 + read-only + + + V + Valid reading. (Re-)enabling the TMU will automatically clear this bit and start a new search. + 31 + 1 + read-only + + + V_0 + Temperature reading is not valid due to no measured temperature within the sensor range of 0-125 degree C for an enabled monitored site. + 0 + + + V_1 + Temperature reading is valid. + 0x1 + + + + + + + TMHTCRL + TMU Monitor Low Temperature Capture register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + TEMP + Lowest temperature recorded in degrees Celsius by any enabled monitored site + 0 + 8 + read-only + + + V + Valid reading. (Re-)enabling the TMU will automatically clear this bit and start a new search. + 31 + 1 + read-only + + + V_0 + Temperature reading is not valid due to no measured temperature within the sensor range of 0-125 degree C for an enabled monitored site. + 0 + + + V_1 + Temperature reading is valid. + 0x1 + + + + + + + TMHTITR + TMU Monitor High Temperature Immediate Threshold register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEMP + High temperature immediate threshold value + 0 + 8 + read-write + + + EN + Enable threshold. + 31 + 1 + read-write + + + EN_0 + Disabled. + 0 + + + EN_1 + Threshold enabled. + 0x1 + + + + + + + TMHTATR + TMU Monitor High Temperature Average threshold register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEMP + High temperature average threshold value + 0 + 8 + read-write + + + EN + Enable threshold. + 31 + 1 + read-write + + + EN_0 + Disabled. + 0 + + + EN_1 + Threshold enabled. + 0x1 + + + + + + + TMHTACTR + TMU Monitor High Temperature Average Critical Threshold register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEMP + High temperature average critical threshold value + 0 + 8 + read-write + + + EN + Enable threshold. + 31 + 1 + read-write + + + EN_0 + Disabled. + 0 + + + EN_1 + Threshold enabled. + 0x1 + + + + + + + TTCFGR + TMU Temperature Configuration register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Sensor data. + 0 + 32 + read-write + + + + + TSCFGR + TMU Sensor Configuration register + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Sensor data. + 0 + 32 + read-write + + + + + 16 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + TRITSR%s + TMU Report Immediate Temperature Site register n + 0x100 + 32 + read-only + 0 + 0xFFFFFFFF + + + TEMP + Last temperature reading at site n when V=1. + 0 + 8 + read-only + + + V + Valid measured temperature. + 31 + 1 + read-only + + + V_0 + Not valid. Temperature out of sensor range or first measurement still pending. + 0 + + + V_1 + Valid. + 0x1 + + + + + + + 16 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + TRATSR%s + TMU Report Average Temperature Site register n + 0x104 + 32 + read-only + 0 + 0xFFFFFFFF + + + TEMP + Average temperature reading at site n when V=1. + 0 + 8 + read-only + + + V + Valid measured temperature. + 31 + 1 + read-only + + + V_0 + Not valid. Temperature out of sensor range or first measurement still pending. + 0 + + + V_1 + Valid. + 0x1 + + + + + + + IPBRR0 + IP Block Revision register 0 + 0xBF8 + 32 + read-only + 0x1900100 + 0xFFFFFFFF + + + IP_MN + Minor revision + 0 + 8 + read-only + + + IP_MJ + Major revision + 8 + 8 + read-only + + + IP_ID + IP block ID + 16 + 16 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + TTR%sCR + TMU Temperature Range n Control register + 0xF10 + 32 + read-write + 0xC0000 + 0xFFFFFFFF + + + TEMP + Starting temperature in Celsius for range n. + 0 + 8 + read-write + + + CAL_PTS + Temperature calibration points. 0000 1 point 0001 2 points 0010 3 points ... 1111 16 points + 16 + 4 + read-write + + + + + + + XTALOSC + XTALOSC + XTALOSC + XTALOSC_ + 0x30270000 + + 0 + 0x8008 + registers + + + + OSC25M_CTL_CFG + 25M Oscillator Control Configuration Register + 0 + 32 + read-write + 0x1802070 + 0xFFFFFFFF + + + OSC_ALC_CTL + Automatic Level Controller Enable + 2 + 1 + read-write + + + OSC_ALC_CTL_0 + Enable automatic level controller + 0 + + + OSC_ALC_CTL_1 + Disable automatic level controller + 0x1 + + + + + OSC_HYST_CTL + Hysteresis Control + 3 + 1 + read-write + + + OSC_HYST_CTL_0 + Enable hysteresis control + 0 + + + OSC_HYST_CTL_1 + Disable hysteresis control + 0x1 + + + + + OSC_GM_SEL + Crystal overdrive protection + 4 + 3 + read-write + + + OSC_INT_STU + Crystal oscillator clock interrupt This bit is set by hardware when OSCCNT counter reaches the count value EOCV x 512 + 7 + 1 + read-write + + + OSC_INT_STU_0 + No oscillator clock interrupt occurred + 0 + + + OSC_INT_STU_1 + Oscillator clock interrupt pending + 0x1 + + + + + OSC_DIV + Crystal oscillator clock division factor These bits specify the crystal oscillator output clock division factor + 8 + 5 + read-write + + + OSC_OK_BYPASS + OSC ok output bypass + 13 + 1 + read-write + + + OSC_INT_MASK + Crystal oscillator clock interrupt mask This bit masks the I_OSC interrupt bit. + 15 + 1 + read-write + + + OSC_INT_MASK_0 + Crystal oscillator clock interrupt is masked + 0 + + + OSC_INT_MASK_1 + Crystal oscillator clock interrupt is enabled + 0x1 + + + + + OSC_EOCV + End of Count Value These bits specify the end of count value to be used for comparison by the oscillator stabilization counter OSCCNT after reset or whenever it is switched on from the off state + 16 + 8 + read-write + + + OSC_GM_TST_SEL + Test mode GM measurement + 30 + 1 + read-write + + + OSC_GM_TST_SEL_0 + Normal run mode + 0 + + + OSC_GM_TST_SEL_1 + Enable test mode measurement of GM + 0x1 + + + + + OSC_BYPSS + Crystal Oscillator bypass This bit specifies whether the oscillator should be bypassed or not + 31 + 1 + read-write + + + OSC_BYPSS_0 + Oscillator output is used as root clock. + 0 + + + OSC_BYPSS_1 + EXTAL is used as root clock + 0x1 + + + + + + + OSC25M_TEST_CFG + 25M Oscillator Test Configuration Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + XOSC_TESTEN + 25M Oscillator Test Enable + 31 + 1 + read-write + + + + + OSC27M_CTL_CFG + 27M Oscillator Control Configuration Register + 0x8000 + 32 + read-write + 0x1802070 + 0xFFFFFFFF + + + OSC_ALC_CTL + Automatic Level Controller Enable + 2 + 1 + read-write + + + OSC_ALC_CTL_0 + Enable automatic level controller + 0 + + + OSC_ALC_CTL_1 + Disable automatic level controller + 0x1 + + + + + OSC_HYST_CTL + Hysteresis Control + 3 + 1 + read-write + + + OSC_HYST_CTL_0 + Enable hysteresis control + 0 + + + OSC_HYST_CTL_1 + Disable hysteresis control + 0x1 + + + + + OSC_GM_SEL + Crystal overdrive protection + 4 + 3 + read-write + + + OSC_INT_STU + Crystal oscillator clock interrupt This bit is set by hardware when OSCCNT counter reaches the count value EOCV x 512 + 7 + 1 + read-write + + + OSC_INT_STU_0 + No oscillator clock interrupt occurred + 0 + + + OSC_INT_STU_1 + Oscillator clock interrupt pending + 0x1 + + + + + OSC_DIV + Crystal oscillator clock division factor These bits specify the crystal oscillator output clock division factor + 8 + 5 + read-write + + + OSC_OK_BYPASS + OSC ok output bypass + 13 + 1 + read-write + + + OSC_INT_MASK + Crystal oscillator clock interrupt mask This bit masks the I_OSC interrupt bit. + 15 + 1 + read-write + + + OSC_INT_MASK_0 + Crystal oscillator clock interrupt is masked + 0 + + + OSC_INT_MASK_1 + Crystal oscillator clock interrupt is enabled + 0x1 + + + + + OSC_EOCV + End of Count Value These bits specify the end of count value to be used for comparison by the oscillator stabilization counter OSCCNT after reset or whenever it is switched on from the off state + 16 + 8 + read-write + + + OSC_GM_TST_SEL + Test mode GM measurement + 30 + 1 + read-write + + + OSC_GM_TST_SEL_0 + Normal run mode + 0 + + + OSC_GM_TST_SEL_1 + Enable test mode measurement of GM + 0x1 + + + + + OSC_BYPSS + Crystal Oscillator bypass This bit specifies whether the oscillator should be bypassed or not + 31 + 1 + read-write + + + OSC_BYPSS_0 + Oscillator output is used as root clock. + 0 + + + OSC_BYPSS_1 + EXTAL is used as root clock + 0x1 + + + + + + + OSC27M_TEST_CFG + 27M Oscillator Test Configuration Register + 0x8004 + 32 + read-write + 0 + 0xFFFFFFFF + + + XOSC_TESTEN + 27M Oscillator Test Enable + 31 + 1 + read-write + + + + + + + WDOG1 + WDOG + WDOG + WDOG1_ + WDOG + 0x30280000 + + 0 + 0xA + registers + + + WDOG1 + 78 + + + + WCR + Watchdog Control Register + 0 + 16 + read-write + 0x30 + 0xFFFF + + + WDZST + Watchdog Low Power + 0 + 1 + read-write + + + WDZST_0 + Continue timer operation (Default). + 0 + + + WDZST_1 + Suspend the watchdog timer. + 0x1 + + + + + WDBG + Watchdog DEBUG Enable + 1 + 1 + read-write + + + WDBG_0 + Continue WDOG timer operation (Default). + 0 + + + WDBG_1 + Suspend the watchdog timer. + 0x1 + + + + + WDE + Watchdog Enable + 2 + 1 + read-write + + + WDE_0 + Disable the Watchdog (Default). + 0 + + + WDE_1 + Enable the Watchdog. + 0x1 + + + + + WDT + WDOG_B Time-out assertion + 3 + 1 + read-write + + + WDT_0 + No effect on WDOG_B (Default). + 0 + + + WDT_1 + Assert WDOG_B upon a Watchdog Time-out event. + 0x1 + + + + + SRS + Software Reset Signal + 4 + 1 + read-write + + + SRS_0 + Assert system reset signal. + 0 + + + SRS_1 + No effect on the system (Default). + 0x1 + + + + + WDA + WDOG_B assertion. Controls the software assertion of the WDOG_B signal. + 5 + 1 + read-write + + + WDA_0 + Assert WDOG_B output. + 0 + + + WDA_1 + No effect on system (Default). + 0x1 + + + + + SRE + Software Reset Extension. Required to be set to 1 when used in conjunction with the Software Reset Signal (SRS). + 6 + 1 + read-write + + + SRE_1 + This bit must be set to 1. + 0x1 + + + + + WDW + Watchdog Disable for Wait + 7 + 1 + read-write + + + WDW_0 + Continue WDOG timer operation (Default). + 0 + + + WDW_1 + Suspend WDOG timer operation. + 0x1 + + + + + WT + Watchdog Time-out Field + 8 + 8 + read-write + + + WT_0 + - 0.5 Seconds (Default). + 0 + + + WT_1 + - 1.0 Seconds. + 0x1 + + + WT_2 + - 1.5 Seconds. + 0x2 + + + WT_3 + - 2.0 Seconds. + 0x3 + + + WT_255 + - 128 Seconds. + 0xFF + + + + + + + WSR + Watchdog Service Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + WSR + Watchdog Service Register + 0 + 16 + read-write + + + WSR_21845 + Write to the Watchdog Service Register (WDOG_WSR). + 0x5555 + + + WSR_43690 + Write to the Watchdog Service Register (WDOG_WSR). + 0xAAAA + + + + + + + WRSR + Watchdog Reset Status Register + 0x4 + 16 + read-only + 0 + 0xFFFF + + + SFTW + Software Reset + 0 + 1 + read-only + + + SFTW_0 + Reset is not the result of a software reset. + 0 + + + SFTW_1 + Reset is the result of a software reset. + 0x1 + + + + + TOUT + Timeout. Indicates whether the reset is the result of a WDOG timeout. + 1 + 1 + read-only + + + TOUT_0 + Reset is not the result of a WDOG timeout. + 0 + + + TOUT_1 + Reset is the result of a WDOG timeout. + 0x1 + + + + + POR + Power On Reset. Indicates whether the reset is the result of a power on reset. + 4 + 1 + read-only + + + POR_0 + Reset is not the result of a power on reset. + 0 + + + POR_1 + Reset is the result of a power on reset. + 0x1 + + + + + + + WICR + Watchdog Interrupt Control Register + 0x6 + 16 + read-write + 0x4 + 0xFFFF + + + WICT + Watchdog Interrupt Count Time-out (WICT) field determines, how long before the counter time-out must the interrupt occur + 0 + 8 + read-write + + + WICT_0 + WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + 0 + + + WICT_1 + WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + 0x1 + + + WICT_4 + WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + 0x4 + + + WICT_255 + WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + 0xFF + + + + + WTIS + Watchdog Timer Interrupt Status bit will reflect the timer interrupt status, whether interrupt has occurred or not + 14 + 1 + read-write + oneToClear + + + WTIS_0 + No interrupt has occurred (Default). + 0 + + + WTIS_1 + Interrupt has occurred + 0x1 + + + + + WIE + Watchdog Timer Interrupt enable bit + 15 + 1 + read-write + + + WIE_0 + Disable Interrupt (Default). + 0 + + + WIE_1 + Enable Interrupt. + 0x1 + + + + + + + WMCR + Watchdog Miscellaneous Control Register + 0x8 + 16 + read-write + 0x1 + 0xFFFF + + + PDE + Power Down Enable bit + 0 + 1 + read-write + + + PDE_0 + Power Down Counter of WDOG is disabled. + 0 + + + PDE_1 + Power Down Counter of WDOG is enabled (Default). + 0x1 + + + + + + + + + WDOG2 + WDOG + WDOG + WDOG2_ + 0x30290000 + + 0 + 0xA + registers + + + WDOG2 + 79 + + + + WDOG3 + WDOG + WDOG + WDOG3_ + 0x302A0000 + + 0 + 0xA + registers + + + WDOG3 + 10 + + + + GPT1 + GPT + GPT + GPT1_ + GPT + 0x302D0000 + + 0 + 0x28 + registers + + + GPT1 + 55 + + + + CR + GPT Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + GPT Enable + 0 + 1 + read-write + + + EN_0 + GPT is disabled. + 0 + + + EN_1 + GPT is enabled. + 0x1 + + + + + ENMOD + GPT Enable mode + 1 + 1 + read-write + + + ENMOD_0 + GPT counter will retain its value when it is disabled. + 0 + + + ENMOD_1 + GPT counter value is reset to 0 when it is disabled. + 0x1 + + + + + DBGEN + GPT debug mode enable + 2 + 1 + read-write + + + DBGEN_0 + GPT is disabled in debug mode. + 0 + + + DBGEN_1 + GPT is enabled in debug mode. + 0x1 + + + + + WAITEN + GPT Wait Mode enable + 3 + 1 + read-write + + + WAITEN_0 + GPT is disabled in wait mode. + 0 + + + WAITEN_1 + GPT is enabled in wait mode. + 0x1 + + + + + DOZEEN + GPT Doze Mode Enable + 4 + 1 + read-write + + + DOZEEN_0 + GPT is disabled in doze mode. + 0 + + + DOZEEN_1 + GPT is enabled in doze mode. + 0x1 + + + + + STOPEN + GPT Stop Mode enable + 5 + 1 + read-write + + + STOPEN_0 + GPT is disabled in Stop mode. + 0 + + + STOPEN_1 + GPT is enabled in Stop mode. + 0x1 + + + + + CLKSRC + Clock Source select + 6 + 3 + read-write + + + CLKSRC_0 + No clock + 0 + + + CLKSRC_1 + Peripheral Clock (ipg_clk) + 0x1 + + + CLKSRC_2 + High Frequency Reference Clock (ipg_clk_highfreq) + 0x2 + + + CLKSRC_3 + External Clock + 0x3 + + + CLKSRC_4 + Low Frequency Reference Clock (ipg_clk_32k) + 0x4 + + + CLKSRC_5 + Crystal oscillator as Reference Clock (ipg_clk_24M) + 0x5 + + + + + FRR + Free-Run or Restart mode + 9 + 1 + read-write + + + FRR_0 + Restart mode + 0 + + + FRR_1 + Free-Run mode + 0x1 + + + + + EN_24M + Enable 24 MHz clock input from crystal + 10 + 1 + read-write + + + EN_24M_0 + 24M clock disabled + 0 + + + EN_24M_1 + 24M clock enabled + 0x1 + + + + + SWR + Software reset + 15 + 1 + read-write + + + SWR_0 + GPT is not in reset state + 0 + + + SWR_1 + GPT is in reset state + 0x1 + + + + + IM1 + See IM2 + 16 + 2 + read-write + + + IM2 + IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event + 18 + 2 + read-write + + + IM2_0 + capture disabled + 0 + + + IM2_1 + capture on rising edge only + 0x1 + + + IM2_2 + capture on falling edge only + 0x2 + + + IM2_3 + capture on both edges + 0x3 + + + + + OM1 + See OM3 + 20 + 3 + read-write + + + OM2 + See OM3 + 23 + 3 + read-write + + + OM3 + OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode + 26 + 3 + read-write + + + OM3_0 + Output disconnected. No response on pin. + 0 + + + OM3_1 + Toggle output pin + 0x1 + + + OM3_2 + Clear output pin + 0x2 + + + OM3_3 + Set output pin + 0x3 + + + OM3_4 + Generate an active low pulse (that is one input clock wide) on the output pin. + #1xx + + + + + FO1 + See F03 + 29 + 1 + write-only + + + FO2 + See F03 + 30 + 1 + write-only + + + FO3 + FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register) + 31 + 1 + write-only + + + FO3_0 + Writing a 0 has no effect. + 0 + + + FO3_1 + Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + 0x1 + + + + + + + PR + GPT Prescaler Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALER + Prescaler bits + 0 + 12 + read-write + + + PRESCALER_0 + Divide by 1 + 0 + + + PRESCALER_1 + Divide by 2 + 0x1 + + + PRESCALER_4095 + Divide by 4096 + 0xFFF + + + + + PRESCALER24M + Prescaler bits + 12 + 4 + read-write + + + PRESCALER24M_0 + Divide by 1 + 0 + + + PRESCALER24M_1 + Divide by 2 + 0x1 + + + PRESCALER24M_15 + Divide by 16 + 0xF + + + + + + + SR + GPT Status Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1 + See OF3 + 0 + 1 + read-write + oneToClear + + + OF2 + See OF3 + 1 + 1 + read-write + oneToClear + + + OF3 + OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n + 2 + 1 + read-write + oneToClear + + + OF3_0 + Compare event has not occurred. + 0 + + + OF3_1 + Compare event has occurred. + 0x1 + + + + + IF1 + See IF2 + 3 + 1 + read-write + oneToClear + + + IF2 + IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n + 4 + 1 + read-write + oneToClear + + + IF2_0 + Capture event has not occurred. + 0 + + + IF2_1 + Capture event has occurred. + 0x1 + + + + + ROV + Rollover Flag + 5 + 1 + read-write + oneToClear + + + ROV_0 + Rollover has not occurred. + 0 + + + ROV_1 + Rollover has occurred. + 0x1 + + + + + + + IR + GPT Interrupt Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1IE + See OF3IE + 0 + 1 + read-write + + + OF2IE + See OF3IE + 1 + 1 + read-write + + + OF3IE + OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt + 2 + 1 + read-write + + + OF3IE_0 + Output Compare Channel n interrupt is disabled. + 0 + + + OF3IE_1 + Output Compare Channel n interrupt is enabled. + 0x1 + + + + + IF1IE + See IF2IE + 3 + 1 + read-write + + + IF2IE + IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable + 4 + 1 + read-write + + + IF2IE_0 + IF2IE Input Capture n Interrupt Enable is disabled. + 0 + + + IF2IE_1 + IF2IE Input Capture n Interrupt Enable is enabled. + 0x1 + + + + + ROVIE + Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt. + 5 + 1 + read-write + + + ROVIE_0 + Rollover interrupt is disabled. + 0 + + + ROVIE_1 + Rollover interrupt enabled. + 0x1 + + + + + + + OCR1 + GPT Output Compare Register 1 + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR2 + GPT Output Compare Register 2 + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR3 + GPT Output Compare Register 3 + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + ICR1 + GPT Input Capture Register 1 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + ICR2 + GPT Input Capture Register 2 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + CNT + GPT Counter Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Counter Value. The COUNT bits show the current count value of the GPT counter. + 0 + 32 + read-only + + + + + + + GPT2 + GPT + GPT + GPT2_ + 0x302E0000 + + 0 + 0x28 + registers + + + GPT2 + 54 + + + + GPT3 + GPT + GPT + GPT3_ + 0x302F0000 + + 0 + 0x28 + registers + + + GPT3 + 53 + + + + GPT6 + GPT + GPT + GPT6_ + 0x306E0000 + + 0 + 0x28 + registers + + + GPT6 + 46 + + + + GPT5 + GPT + GPT + GPT5_ + 0x306F0000 + + 0 + 0x28 + registers + + + GPT5 + 51 + + + + GPT4 + GPT + GPT + GPT4_ + 0x30700000 + + 0 + 0x28 + registers + + + GPT4 + 52 + + + + ROMC + ROMC + ROMC + ROMC_ + 0x30310000 + + 0 + 0x20C + registers + + + + 8 + 0x4 + 7,6,5,4,3,2,1,0 + ROMPATCH%sD + ROMC Data Registers + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATAX + Data Fix Registers - Stores the data used for 1-word data fix operations + 0 + 32 + read-write + + + + + ROMPATCHCNTL + ROMC Control Register + 0xF4 + 32 + read-write + 0x8400000 + 0xFFFFFFFF + + + DATAFIX + Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for code patch routine + 0 + 8 + read-write + + + DATAFIX_0 + Address comparator triggers a opcode patch + 0 + + + DATAFIX_1 + Address comparator triggers a data fix + 0x1 + + + + + DIS + ROMC Disable -- This bit, when set, disables all ROMC operations + 29 + 1 + read-write + + + DIS_0 + Does not affect any ROMC functions (default) + 0 + + + DIS_1 + Disable all ROMC functions: data fixing, and opcode patching + 0x1 + + + + + + + ROMPATCHENH + ROMC Enable Register High + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ROMPATCHENL + ROMC Enable Register Low + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable Address Comparator - This bit enables the corresponding address comparator to trigger an event + 0 + 16 + read-write + + + ENABLE_0 + Address comparator disabled + 0 + + + ENABLE_1 + Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + 0x1 + + + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + ROMPATCH%sA + ROMC Address Registers + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + THUMBX + THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch + 0 + 1 + read-write + + + THUMBX_0 + Arm patch + 0 + + + THUMBX_1 + THUMB patch (ignore if data fix) + 0x1 + + + + + ADDRX + Address Comparator Registers - Indicates the memory address to be watched + 1 + 22 + read-write + + + + + ROMPATCHSR + ROMC Status Register + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE + ROMC Source Number - Binary encoding of the number of the address comparator which has an address match in the most recent patch event on ROMC AHB + 0 + 6 + read-only + + + SOURCE_0 + Address Comparator 0 matched + 0 + + + SOURCE_1 + Address Comparator 1 matched + 0x1 + + + SOURCE_15 + Address Comparator 15 matched + 0xF + + + + + SW + ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address comparator matches occurred + 17 + 1 + read-write + oneToClear + + + SW_0 + no event or comparator collisions + 0 + + + SW_1 + a collision has occurred + 0x1 + + + + + + + + + LCDIF + LCDIF Register Reference Index + LCDIF + LCDIF_ + 0x30320000 + + 0 + 0x264 + registers + + + LCDIF + 5 + + + + CTRL + LCDIF General Control Register + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 3 + 1 + read-write + + + MASTER + Set this bit to make the LCDIF act as a bus master. + 5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on + 6 + 1 + read-write + + + RGB_TO_YCBCR422_CSC + Set this bit to 1 to enable conversion from RGB to YCbCr colorspace + 7 + 1 + read-write + + + WORD_LENGTH + Input data format. + 8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 10 + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 12 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 14 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DATA_SELECT + Command Mode polarity bit. This bit should only be changed when RUN is 0. + 16 + 1 + read-write + + + CMD_MODE + Command Mode. LCD_RS signal is Low. + 0 + + + DATA_MODE + Data Mode. LCD_RS signal is High. + 0x1 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 17 + 1 + read-write + + + VSYNC_MODE + Setting this bit to 1 will make the LCDIF hardware go into VSYNC mode + 18 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 19 + 1 + read-write + + + DVI_MODE + Set this bit to 1 to get into the ITU-R BT + 20 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 21 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data + 26 + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + WAIT_FOR_VSYNC_EDGE + Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD + 27 + 1 + read-write + + + READ_WRITEB + By default, LCDIF is in the write mode + 28 + 1 + read-write + + + YCBCR422_INPUT + Zero implies input data is in RGB color space + 29 + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the LCDIF + 31 + 1 + read-write + + + + + CTRL_SET + LCDIF General Control Register + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 3 + 1 + read-write + + + MASTER + Set this bit to make the LCDIF act as a bus master. + 5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on + 6 + 1 + read-write + + + RGB_TO_YCBCR422_CSC + Set this bit to 1 to enable conversion from RGB to YCbCr colorspace + 7 + 1 + read-write + + + WORD_LENGTH + Input data format. + 8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 10 + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 12 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 14 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DATA_SELECT + Command Mode polarity bit. This bit should only be changed when RUN is 0. + 16 + 1 + read-write + + + CMD_MODE + Command Mode. LCD_RS signal is Low. + 0 + + + DATA_MODE + Data Mode. LCD_RS signal is High. + 0x1 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 17 + 1 + read-write + + + VSYNC_MODE + Setting this bit to 1 will make the LCDIF hardware go into VSYNC mode + 18 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 19 + 1 + read-write + + + DVI_MODE + Set this bit to 1 to get into the ITU-R BT + 20 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 21 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data + 26 + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + WAIT_FOR_VSYNC_EDGE + Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD + 27 + 1 + read-write + + + READ_WRITEB + By default, LCDIF is in the write mode + 28 + 1 + read-write + + + YCBCR422_INPUT + Zero implies input data is in RGB color space + 29 + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the LCDIF + 31 + 1 + read-write + + + + + CTRL_CLR + LCDIF General Control Register + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 3 + 1 + read-write + + + MASTER + Set this bit to make the LCDIF act as a bus master. + 5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on + 6 + 1 + read-write + + + RGB_TO_YCBCR422_CSC + Set this bit to 1 to enable conversion from RGB to YCbCr colorspace + 7 + 1 + read-write + + + WORD_LENGTH + Input data format. + 8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 10 + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 12 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 14 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DATA_SELECT + Command Mode polarity bit. This bit should only be changed when RUN is 0. + 16 + 1 + read-write + + + CMD_MODE + Command Mode. LCD_RS signal is Low. + 0 + + + DATA_MODE + Data Mode. LCD_RS signal is High. + 0x1 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 17 + 1 + read-write + + + VSYNC_MODE + Setting this bit to 1 will make the LCDIF hardware go into VSYNC mode + 18 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 19 + 1 + read-write + + + DVI_MODE + Set this bit to 1 to get into the ITU-R BT + 20 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 21 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data + 26 + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + WAIT_FOR_VSYNC_EDGE + Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD + 27 + 1 + read-write + + + READ_WRITEB + By default, LCDIF is in the write mode + 28 + 1 + read-write + + + YCBCR422_INPUT + Zero implies input data is in RGB color space + 29 + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the LCDIF + 31 + 1 + read-write + + + + + CTRL_TOG + LCDIF General Control Register + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 3 + 1 + read-write + + + MASTER + Set this bit to make the LCDIF act as a bus master. + 5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on + 6 + 1 + read-write + + + RGB_TO_YCBCR422_CSC + Set this bit to 1 to enable conversion from RGB to YCbCr colorspace + 7 + 1 + read-write + + + WORD_LENGTH + Input data format. + 8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 10 + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 12 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 14 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DATA_SELECT + Command Mode polarity bit. This bit should only be changed when RUN is 0. + 16 + 1 + read-write + + + CMD_MODE + Command Mode. LCD_RS signal is Low. + 0 + + + DATA_MODE + Data Mode. LCD_RS signal is High. + 0x1 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 17 + 1 + read-write + + + VSYNC_MODE + Setting this bit to 1 will make the LCDIF hardware go into VSYNC mode + 18 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 19 + 1 + read-write + + + DVI_MODE + Set this bit to 1 to get into the ITU-R BT + 20 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 21 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data + 26 + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + WAIT_FOR_VSYNC_EDGE + Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD + 27 + 1 + read-write + + + READ_WRITEB + By default, LCDIF is in the write mode + 28 + 1 + read-write + + + YCBCR422_INPUT + Zero implies input data is in RGB color space + 29 + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the LCDIF + 31 + 1 + read-write + + + + + CTRL1 + LCDIF General Control1 Register + 0x10 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + RESET + Reset bit for the external LCD controller + 0 + 1 + read-write + + + LCDRESET_LOW + LCD_RESET output signal is low. + 0 + + + LCDRESET_HIGH + LCD_RESET output signal is high. + 0x1 + + + + + MODE86 + This bit is used to select between the 8080 and 6800 series of microprocessor modes + 1 + 1 + read-write + + + 8080_MODE + Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + 0 + + + 6800_MODE + Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + 0x1 + + + + + BUSY_ENABLE + This bit enables the use of the interface's busy signal input + 2 + 1 + read-write + + + BUSY_DISABLED + The busy signal from the LCD controller will be ignored. + 0 + + + BUSY_ENABLED + Enable the use of the busy signal from the LCD controller. + 0x1 + + + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 10 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 11 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 12 + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 13 + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 14 + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 15 + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 16 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 20 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 21 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 22 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field + 23 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 24 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 25 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the LCDIF master mode. + 26 + 1 + read-write + + + COMBINE_MPU_WR_STRB + If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode + 27 + 1 + read-write + + + + + CTRL1_SET + LCDIF General Control1 Register + 0x14 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + RESET + Reset bit for the external LCD controller + 0 + 1 + read-write + + + LCDRESET_LOW + LCD_RESET output signal is low. + 0 + + + LCDRESET_HIGH + LCD_RESET output signal is high. + 0x1 + + + + + MODE86 + This bit is used to select between the 8080 and 6800 series of microprocessor modes + 1 + 1 + read-write + + + 8080_MODE + Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + 0 + + + 6800_MODE + Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + 0x1 + + + + + BUSY_ENABLE + This bit enables the use of the interface's busy signal input + 2 + 1 + read-write + + + BUSY_DISABLED + The busy signal from the LCD controller will be ignored. + 0 + + + BUSY_ENABLED + Enable the use of the busy signal from the LCD controller. + 0x1 + + + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 10 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 11 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 12 + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 13 + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 14 + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 15 + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 16 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 20 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 21 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 22 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field + 23 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 24 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 25 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the LCDIF master mode. + 26 + 1 + read-write + + + COMBINE_MPU_WR_STRB + If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode + 27 + 1 + read-write + + + + + CTRL1_CLR + LCDIF General Control1 Register + 0x18 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + RESET + Reset bit for the external LCD controller + 0 + 1 + read-write + + + LCDRESET_LOW + LCD_RESET output signal is low. + 0 + + + LCDRESET_HIGH + LCD_RESET output signal is high. + 0x1 + + + + + MODE86 + This bit is used to select between the 8080 and 6800 series of microprocessor modes + 1 + 1 + read-write + + + 8080_MODE + Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + 0 + + + 6800_MODE + Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + 0x1 + + + + + BUSY_ENABLE + This bit enables the use of the interface's busy signal input + 2 + 1 + read-write + + + BUSY_DISABLED + The busy signal from the LCD controller will be ignored. + 0 + + + BUSY_ENABLED + Enable the use of the busy signal from the LCD controller. + 0x1 + + + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 10 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 11 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 12 + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 13 + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 14 + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 15 + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 16 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 20 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 21 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 22 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field + 23 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 24 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 25 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the LCDIF master mode. + 26 + 1 + read-write + + + COMBINE_MPU_WR_STRB + If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode + 27 + 1 + read-write + + + + + CTRL1_TOG + LCDIF General Control1 Register + 0x1C + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + RESET + Reset bit for the external LCD controller + 0 + 1 + read-write + + + LCDRESET_LOW + LCD_RESET output signal is low. + 0 + + + LCDRESET_HIGH + LCD_RESET output signal is high. + 0x1 + + + + + MODE86 + This bit is used to select between the 8080 and 6800 series of microprocessor modes + 1 + 1 + read-write + + + 8080_MODE + Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + 0 + + + 6800_MODE + Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + 0x1 + + + + + BUSY_ENABLE + This bit enables the use of the interface's busy signal input + 2 + 1 + read-write + + + BUSY_DISABLED + The busy signal from the LCD controller will be ignored. + 0 + + + BUSY_ENABLED + Enable the use of the busy signal from the LCD controller. + 0x1 + + + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 10 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 11 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 12 + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 13 + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 14 + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 15 + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 16 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 20 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 21 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 22 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field + 23 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 24 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 25 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the LCDIF master mode. + 26 + 1 + read-write + + + COMBINE_MPU_WR_STRB + If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode + 27 + 1 + read-write + + + + + CTRL2 + LCDIF General Control2 Register + 0x20 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + INITIAL_DUMMY_READ + The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller + 1 + 3 + read-write + + + READ_MODE_NUM_PACKED_SUBWORDS + Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode + 4 + 3 + read-write + + + READ_MODE_6_BIT_INPUT + Setting this bit to 1 indicates to LCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits, the input data is actually only 6 bits wide and exists on D5-D0 + 8 + 1 + read-write + + + READ_MODE_OUTPUT_IN_RGB_FORMAT + Setting this bit will enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield + 9 + 1 + read-write + + + READ_PACK_DIR + The default value of 0 indicates data is stored in the little endian format + 10 + 1 + read-write + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 12 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 16 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + BURST_LEN_8 + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 20 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master + 21 + 3 + read-write + + + REQ_1 + REQ_1 + 0 + + + REQ_2 + REQ_2 + 0x1 + + + REQ_4 + REQ_4 + 0x2 + + + REQ_8 + REQ_8 + 0x3 + + + REQ_16 + REQ_16 + 0x4 + + + + + + + CTRL2_SET + LCDIF General Control2 Register + 0x24 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + INITIAL_DUMMY_READ + The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller + 1 + 3 + read-write + + + READ_MODE_NUM_PACKED_SUBWORDS + Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode + 4 + 3 + read-write + + + READ_MODE_6_BIT_INPUT + Setting this bit to 1 indicates to LCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits, the input data is actually only 6 bits wide and exists on D5-D0 + 8 + 1 + read-write + + + READ_MODE_OUTPUT_IN_RGB_FORMAT + Setting this bit will enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield + 9 + 1 + read-write + + + READ_PACK_DIR + The default value of 0 indicates data is stored in the little endian format + 10 + 1 + read-write + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 12 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 16 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + BURST_LEN_8 + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 20 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master + 21 + 3 + read-write + + + REQ_1 + REQ_1 + 0 + + + REQ_2 + REQ_2 + 0x1 + + + REQ_4 + REQ_4 + 0x2 + + + REQ_8 + REQ_8 + 0x3 + + + REQ_16 + REQ_16 + 0x4 + + + + + + + CTRL2_CLR + LCDIF General Control2 Register + 0x28 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + INITIAL_DUMMY_READ + The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller + 1 + 3 + read-write + + + READ_MODE_NUM_PACKED_SUBWORDS + Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode + 4 + 3 + read-write + + + READ_MODE_6_BIT_INPUT + Setting this bit to 1 indicates to LCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits, the input data is actually only 6 bits wide and exists on D5-D0 + 8 + 1 + read-write + + + READ_MODE_OUTPUT_IN_RGB_FORMAT + Setting this bit will enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield + 9 + 1 + read-write + + + READ_PACK_DIR + The default value of 0 indicates data is stored in the little endian format + 10 + 1 + read-write + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 12 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 16 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + BURST_LEN_8 + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 20 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master + 21 + 3 + read-write + + + REQ_1 + REQ_1 + 0 + + + REQ_2 + REQ_2 + 0x1 + + + REQ_4 + REQ_4 + 0x2 + + + REQ_8 + REQ_8 + 0x3 + + + REQ_16 + REQ_16 + 0x4 + + + + + + + CTRL2_TOG + LCDIF General Control2 Register + 0x2C + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + INITIAL_DUMMY_READ + The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller + 1 + 3 + read-write + + + READ_MODE_NUM_PACKED_SUBWORDS + Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode + 4 + 3 + read-write + + + READ_MODE_6_BIT_INPUT + Setting this bit to 1 indicates to LCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits, the input data is actually only 6 bits wide and exists on D5-D0 + 8 + 1 + read-write + + + READ_MODE_OUTPUT_IN_RGB_FORMAT + Setting this bit will enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield + 9 + 1 + read-write + + + READ_PACK_DIR + The default value of 0 indicates data is stored in the little endian format + 10 + 1 + read-write + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 12 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 16 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + BURST_LEN_8 + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 20 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master + 21 + 3 + read-write + + + REQ_1 + REQ_1 + 0 + + + REQ_2 + REQ_2 + 0x1 + + + REQ_4 + REQ_4 + 0x2 + + + REQ_8 + REQ_8 + 0x3 + + + REQ_16 + REQ_16 + 0x4 + + + + + + + TRANSFER_COUNT + LCDIF Horizontal and Vertical Valid Data Count Register + 0x30 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + H_COUNT + Total valid data (pixels) in each horizontal line + 0 + 16 + read-write + + + V_COUNT + Number of horizontal lines per frame which contain valid data + 16 + 16 + read-write + + + + + CUR_BUF + LCD Interface Current Buffer Address Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address of the current frame being transmitted by LCDIF. + 0 + 32 + read-write + + + + + NEXT_BUF + LCD Interface Next Buffer Address Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address of the next frame that will be transmitted by LCDIF. + 0 + 32 + read-write + + + + + TIMING + LCD Interface Timing Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_SETUP + Data bus setup time in DISPLAY CLOCK (pix_clk) cycles + 0 + 8 + read-write + + + DATA_HOLD + Data bus hold time in DISPLAY CLOCK (pix_clk) cycles + 8 + 8 + read-write + + + CMD_SETUP + Number of DISPLAY CLOCK (pix_clk) cycles that the LCD_RS signal is active before LCD_CS is asserted + 16 + 8 + read-write + + + CMD_HOLD + Number of DISPLAY CLOCK (pix_clk) cycles that the LCD_RS signal is active after LCD_CS is deasserted + 24 + 8 + read-write + + + + + VDCTRL0 + LCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 18 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 19 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 20 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 21 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 24 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 25 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 26 + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 27 + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 28 + 1 + read-write + + + VSYNC_OEB + 0 means the VSYNC signal is an output, 1 means it is an input + 29 + 1 + read-write + + + VSYNC_OUTPUT + The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. + 0 + + + VSYNC_INPUT + The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + 0x1 + + + + + + + VDCTRL0_SET + LCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 18 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 19 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 20 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 21 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 24 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 25 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 26 + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 27 + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 28 + 1 + read-write + + + VSYNC_OEB + 0 means the VSYNC signal is an output, 1 means it is an input + 29 + 1 + read-write + + + VSYNC_OUTPUT + The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. + 0 + + + VSYNC_INPUT + The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + 0x1 + + + + + + + VDCTRL0_CLR + LCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 18 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 19 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 20 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 21 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 24 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 25 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 26 + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 27 + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 28 + 1 + read-write + + + VSYNC_OEB + 0 means the VSYNC signal is an output, 1 means it is an input + 29 + 1 + read-write + + + VSYNC_OUTPUT + The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. + 0 + + + VSYNC_INPUT + The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + 0x1 + + + + + + + VDCTRL0_TOG + LCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 18 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 19 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 20 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 21 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 24 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 25 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 26 + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 27 + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 28 + 1 + read-write + + + VSYNC_OEB + 0 means the VSYNC signal is an output, 1 means it is an input + 29 + 1 + read-write + + + VSYNC_OUTPUT + The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. + 0 + + + VSYNC_INPUT + The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + 0x1 + + + + + + + VDCTRL1 + LCDIF VSYNC Mode and Dotclk Mode Control Register1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PERIOD + Total number of units between two positive or two negative edges of the VSYNC signal + 0 + 32 + read-write + + + + + VDCTRL2 + LCDIF VSYNC Mode and Dotclk Mode Control Register2 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + HSYNC_PERIOD + Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal + 0 + 18 + read-write + + + HSYNC_PULSE_WIDTH + Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active. + 18 + 14 + read-write + + + + + VDCTRL3 + LCDIF VSYNC Mode and Dotclk Mode Control Register3 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + VERTICAL_WAIT_CNT + In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set + 0 + 16 + read-write + + + HORIZONTAL_WAIT_CNT + In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins + 16 + 12 + read-write + + + VSYNC_ONLY + This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation. + 28 + 1 + read-write + + + MUX_SYNC_SIGNALS + When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins + 29 + 1 + read-write + + + + + VDCTRL4 + LCDIF VSYNC Mode and Dotclk Mode Control Register4 + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOTCLK_H_VALID_DATA_CNT + Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode + 0 + 18 + read-write + + + SYNC_SIGNALS_ON + Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end + 18 + 1 + read-write + + + DOTCLK_DLY_SEL + This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin + 29 + 3 + read-write + + + + + DVICTRL0 + Digital Video Interface Control0 Register + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + H_BLANKING_CNT + Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval. + 0 + 12 + read-write + + + H_ACTIVE_CNT + Number of active video samples to be transmitted + 16 + 12 + read-write + + + + + DVICTRL1 + Digital Video Interface Control1 Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + F2_START_LINE + Vertical line number from which Field 2 begins. + 0 + 10 + read-write + + + F1_END_LINE + Vertical line number at which Field1 ends. + 10 + 10 + read-write + + + F1_START_LINE + Vertical line number from which Field 1 begins. + 20 + 10 + read-write + + + + + DVICTRL2 + Digital Video Interface Control2 Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + V1_BLANK_END_LINE + Vertical line number in the beginning part of Field2 where first Vertical Blanking interval ends. + 0 + 10 + read-write + + + V1_BLANK_START_LINE + Vertical line number towards the end of Field1 where first Vertical Blanking interval starts. + 10 + 10 + read-write + + + F2_END_LINE + Vertical line number at which Field 2 ends. + 20 + 10 + read-write + + + + + DVICTRL3 + Digital Video Interface Control3 Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + V_LINES_CNT + Total number of vertical lines per frame (generally 525 or 625) + 0 + 10 + read-write + + + V2_BLANK_END_LINE + Vertical line number in the beginning part of Field1 where second Vertical Blanking interval ends. + 10 + 10 + read-write + + + V2_BLANK_START_LINE + Vertical line number towards the end of Field2 where second Vertical Blanking interval starts. + 20 + 10 + read-write + + + + + DVICTRL4 + Digital Video Interface Control4 Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + H_FILL_CNT + Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval + 0 + 8 + read-write + + + CR_FILL_VALUE + Value of CR component of filler data. + 8 + 8 + read-write + + + CB_FILL_VALUE + Value of CB component of filler data + 16 + 8 + read-write + + + Y_FILL_VALUE + Value of Y component of filler data + 24 + 8 + read-write + + + + + CSC_COEFF0 + RGB to YCbCr 4:2:2 CSC Coefficient0 Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSC_SUBSAMPLE_FILTER + This register describes the filtering and subsampling scheme to be performed on the chroma components in order to convert from YCbCr 4:4:4 to YCbCr 4:2:2 space + 0 + 2 + read-write + + + SAMPLE_AND_HOLD + No filtering, simply keep every chroma value for samples numbered 2n and discard chroma values associated with all samples numbered 2n+1. + 0 + + + INTERSTITIAL + Chroma samples numbered 2n and 2n+1 are averaged (weights 1/2, 1/2) and that chroma value replaces the two chroma values at 2n and 2n+1. This chroma now exists horizontally halfway between the two luma samples. + 0x2 + + + COSITED + Chroma samples numbered 2n-1, 2n, and 2n+1 are averaged (weights 1/4, 1/2, 1/4) and that chroma value exists at the same site as the luma sample numbered 2n and the chroma samples at 2n+1 are discarded. + 0x3 + + + + + C0 + Two's complement red multiplier coefficient for Y + 16 + 10 + read-write + + + + + CSC_COEFF1 + RGB to YCbCr 4:2:2 CSC Coefficient1 Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + C1 + Two's complement green multiplier coefficient for Y + 0 + 10 + read-write + + + C2 + Two's complement blue multiplier coefficient for Y + 16 + 10 + read-write + + + + + CSC_COEFF2 + RGB to YCbCr 4:2:2 CSC Coefficent2 Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + C3 + Two's complement red multiplier coefficient for Cb + 0 + 10 + read-write + + + C4 + Two's complement green multiplier coefficient for Cb + 16 + 10 + read-write + + + + + CSC_COEFF3 + RGB to YCbCr 4:2:2 CSC Coefficient3 Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + C5 + Two's complement blue multiplier coefficient for Cb + 0 + 10 + read-write + + + C6 + Two's complement red multiplier coefficient for Cr + 16 + 10 + read-write + + + + + CSC_COEFF4 + RGB to YCbCr 4:2:2 CSC Coefficient4 Register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + C7 + Two's complement green multiplier coefficient for Cr + 0 + 10 + read-write + + + C8 + Two's complement blue multiplier coefficient for Cr + 16 + 10 + read-write + + + + + CSC_OFFSET + RGB to YCbCr 4:2:2 CSC Offset Register + 0x160 + 32 + read-write + 0x800010 + 0xFFFFFFFF + + + Y_OFFSET + Two's complement offset for the Y component + 0 + 9 + read-write + + + CBCR_OFFSET + Two's complement offset for the Cb and Cr components + 16 + 9 + read-write + + + + + CSC_LIMIT + RGB to YCbCr 4:2:2 CSC Limit Register + 0x170 + 32 + read-write + 0xFF00FF + 0xFFFFFFFF + + + Y_MAX + Upper limit of Y after RGB to 4:2:2 YCbCr conversion + 0 + 8 + read-write + + + Y_MIN + Lower limit of Y after RGB to 4:2:2 YCbCr conversion + 8 + 8 + read-write + + + CBCR_MAX + Upper limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion + 16 + 8 + read-write + + + CBCR_MIN + Lower limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion + 24 + 8 + read-write + + + + + DATA + LCD Interface Data Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_ZERO + Byte 0 (least significant byte) of data written to LCDIF. + 0 + 8 + read-write + + + DATA_ONE + Byte 1 of data written to LCDIF. + 8 + 8 + read-write + + + DATA_TWO + Byte 2 of data written to LCDIF. + 16 + 8 + read-write + + + DATA_THREE + Byte 3 (most significant byte) of data written to LCDIF. + 24 + 8 + read-write + + + + + BM_ERROR_STAT + Bus Master Error Status Register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Virtual address at which bus master error occurred. + 0 + 32 + read-write + + + + + CRC_STAT + CRC Status Register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CRC_VALUE + Calculated CRC value. + 0 + 32 + read-write + + + + + STAT + LCD Interface Status Register + 0x1B0 + 32 + read-only + 0x95000000 + 0xFFFFFFFF + + + LFIFO_COUNT + Read only view of the current count in Latency buffer (LFIFO). + 0 + 9 + read-only + + + DVI_CURRENT_FIELD + Read only view of the current field being transmitted + 24 + 1 + read-only + + + BUSY + Read only view of the input busy signal from the external LCD controller. + 25 + 1 + read-only + + + TXFIFO_EMPTY + Read only view of the signals that indicates LCD TXFIFO is empty. + 26 + 1 + read-only + + + TXFIFO_FULL + Read only view of the signals that indicates LCD TXFIFO is full. + 27 + 1 + read-only + + + LFIFO_EMPTY + Read only view of the signals that indicates LCD LFIFO is empty. + 28 + 1 + read-only + + + LFIFO_FULL + Read only view of the signals that indicates LCD LFIFO is full. + 29 + 1 + read-only + + + PRESENT + 0: LCDIF not present on this product 1: LCDIF is present. + 31 + 1 + read-only + + + + + THRES + LCDIF Threshold Register + 0x200 + 32 + read-write + 0x100000F + 0xFFFFFFFF + + + PANIC + This value should be set to a value of pixels from 0 to 511 + 0 + 9 + read-write + + + FASTCLOCK + This value should be set to a value of pixels, from 0 to 511 + 16 + 9 + read-write + + + + + AS_CTRL + LCDIF AS Buffer Control Register + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + AS_ENABLE + When this bit is set by software, the LCDIF will start fetching AS buffer data in bus master mode and combine it with another buffer + 0 + 1 + read-write + + + ALPHA_CTRL + Determines how the alpha value is constructed for this alpha surface + 1 + 2 + read-write + + + ENABLE_COLORKEY + Indicates that colorkey functionality is enabled for this alpha surface + 3 + 1 + read-write + + + FORMAT + Indicates the input buffer format for AS + 4 + 4 + read-write + + + ALPHA + Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL[ALPHA_CTRL] + 8 + 8 + read-write + + + ROP + Indicates a raster operation to perform when enabled + 16 + 4 + read-write + + + ALPHA_INVERT + Setting this bit to logic 0 will not alter the alpha value + 20 + 1 + read-write + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes either in the HW_LCDIF_DATA register or those fetched by the AXI master part of LCDIF + 21 + 2 + read-write + + + PS_DISABLE + When this bit is set by software, the LCDIF will disable PS buffer data. + 23 + 1 + read-write + + + RVDS1 + Reserved, always set to zero. + 24 + 3 + read-only + + + CSI_SYNC_ON_IRQ + this bit is set by software to decide which vsync generate mode + 27 + 1 + read-write + + + CSI_SYNC_ON_IRQ_EN + This bit is set to enable an interrupt when LCDIF lock with CSI vsync input. + 28 + 1 + read-write + + + CSI_VSYNC_MODE + this bit is set by software to decide which vsync generate mode + 29 + 1 + read-write + + + CSI_VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 30 + 1 + read-write + + + CSI_VSYNC_ENABLE + When this bit is set by software, the LCDIF work as sync mode with CSI input. + 31 + 1 + read-write + + + + + AS_BUF + Alpha Surface Buffer Pointer + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the alpha surface 0 buffer. + 0 + 32 + read-write + + + + + AS_NEXT_BUF + no description available + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address of the next frame that will be transmitted by LCDIF. + 0 + 32 + read-write + + + + + AS_CLRKEYLOW + LCDIF Overlay Color Key Low + 0x240 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of RGB color key applied to AS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 24 + 8 + read-write + + + + + AS_CLRKEYHIGH + LCDIF Overlay Color Key High + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of RGB color key applied to AS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 24 + 8 + read-write + + + + + SYNC_DELAY + LCD working insync mode with CSI for VSYNC delay + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + H_COUNT_DELAY + LCDIF VSYNC delayed counter for CSI_VSYNC. + 0 + 16 + read-write + + + V_COUNT_DELAY + LCDIF VSYNC delayed counter for CSI_VSYNC. + 16 + 16 + read-write + + + + + + + IOMUXC + IOMUXC + IOMUXC + IOMUXC_ + 0x30330000 + + 0 + 0x534 + registers + + + + SW_MUX_CTL_PAD_PMIC_STBY_REQ + SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + SION + Software Input On Field + 6 + 1 + read-write + + + SION_DISABLED + Input Path of pad PMIC_STBY_REQ is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad PMIC_STBY_REQ + 0x1 + + + + + + + SW_MUX_CTL_PAD_PMIC_ON_REQ + SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + SION + Software Input On Field + 6 + 1 + read-write + + + SION_DISABLED + Input Path of pad PMIC_ON_REQ is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad PMIC_ON_REQ + 0x1 + + + + + + + SW_MUX_CTL_PAD_ONOFF + SW_MUX_CTL_PAD_ONOFF SW MUX Control Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + SION + Software Input On Field + 6 + 1 + read-write + + + SION_DISABLED + Input Path of pad ONOFF is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ONOFF + 0x1 + + + + + + + SW_MUX_CTL_PAD_POR_B + SW_MUX_CTL_PAD_POR_B SW MUX Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SION + Software Input On Field + 6 + 1 + read-write + + + SION_DISABLED + Input Path of pad POR_B is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad POR_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_RTC_RESET_B + SW_MUX_CTL_PAD_RTC_RESET_B SW MUX Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + SION + Software Input On Field + 6 + 1 + read-write + + + SION_DISABLED + Input Path of pad RTC_RESET_B is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad RTC_RESET_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO00 + SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO00 + Select mux mode: ALT0 mux port: IO00 of instance: GPIO1 + 0 + + + ALT1_CCM_ENET_PHY_REF_CLK_ROOT + Select mux mode: ALT1 mux port: ENET_PHY_REF_CLK_ROOT of instance: CCM + 0x1 + + + ALT5_ANAMIX_REF_CLK_32K + Select mux mode: ALT5 mux port: REF_CLK_32K of instance: ANAMIX + 0x5 + + + ALT6_CCM_EXT_CLK1 + Select mux mode: ALT6 mux port: EXT_CLK1 of instance: CCM + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO00 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO01 + SW_MUX_CTL_PAD_GPIO1_IO01 SW MUX Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO01 + Select mux mode: ALT0 mux port: IO01 of instance: GPIO1 + 0 + + + ALT1_PWM1_OUT + Select mux mode: ALT1 mux port: OUT of instance: PWM1 + 0x1 + + + ALT5_ANAMIX_REF_CLK_24M + Select mux mode: ALT5 mux port: REF_CLK_24M of instance: ANAMIX + 0x5 + + + ALT6_CCM_EXT_CLK2 + Select mux mode: ALT6 mux port: EXT_CLK2 of instance: CCM + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO01 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO02 + SW_MUX_CTL_PAD_GPIO1_IO02 SW MUX Control Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO02 + Select mux mode: ALT0 mux port: IO02 of instance: GPIO1 + 0 + + + ALT1_WDOG1_WDOG_B + Select mux mode: ALT1 mux port: WDOG_B of instance: WDOG1 + 0x1 + + + ALT5_WDOG1_WDOG_ANY + Select mux mode: ALT5 mux port: WDOG_ANY of instance: WDOG1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO02 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO03 + SW_MUX_CTL_PAD_GPIO1_IO03 SW MUX Control Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO03 + Select mux mode: ALT0 mux port: IO03 of instance: GPIO1 + 0 + + + ALT1_USDHC1_VSELECT + Select mux mode: ALT1 mux port: VSELECT of instance: USDHC1 + 0x1 + + + ALT5_SDMA1_EXT_EVENT0 + Select mux mode: ALT5 mux port: EXT_EVENT0 of instance: SDMA1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO03 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO04 + SW_MUX_CTL_PAD_GPIO1_IO04 SW MUX Control Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO04 + Select mux mode: ALT0 mux port: IO04 of instance: GPIO1 + 0 + + + ALT1_USDHC2_VSELECT + Select mux mode: ALT1 mux port: VSELECT of instance: USDHC2 + 0x1 + + + ALT5_SDMA1_EXT_EVENT1 + Select mux mode: ALT5 mux port: EXT_EVENT1 of instance: SDMA1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO04 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO05 + SW_MUX_CTL_PAD_GPIO1_IO05 SW MUX Control Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO05 + Select mux mode: ALT0 mux port: IO05 of instance: GPIO1 + 0 + + + ALT1_M4_NMI + Select mux mode: ALT1 mux port: NMI of instance: M4 + 0x1 + + + ALT5_CCM_PMIC_READY + Select mux mode: ALT5 mux port: PMIC_READY of instance: CCM + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO05 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO06 + SW_MUX_CTL_PAD_GPIO1_IO06 SW MUX Control Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO06 + Select mux mode: ALT0 mux port: IO06 of instance: GPIO1 + 0 + + + ALT1_ENET1_MDC + Select mux mode: ALT1 mux port: MDC of instance: ENET1 + 0x1 + + + ALT5_USDHC1_CD_B + Select mux mode: ALT5 mux port: CD_B of instance: USDHC1 + 0x5 + + + ALT6_CCM_EXT_CLK3 + Select mux mode: ALT6 mux port: EXT_CLK3 of instance: CCM + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO06 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO07 + SW_MUX_CTL_PAD_GPIO1_IO07 SW MUX Control Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO07 + Select mux mode: ALT0 mux port: IO07 of instance: GPIO1 + 0 + + + ALT1_ENET1_MDIO + Select mux mode: ALT1 mux port: MDIO of instance: ENET1 + 0x1 + + + ALT5_USDHC1_WP + Select mux mode: ALT5 mux port: WP of instance: USDHC1 + 0x5 + + + ALT6_CCM_EXT_CLK4 + Select mux mode: ALT6 mux port: EXT_CLK4 of instance: CCM + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO07 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO08 + SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Control Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO08 + Select mux mode: ALT0 mux port: IO08 of instance: GPIO1 + 0 + + + ALT1_ENET1_1588_EVENT0_IN + Select mux mode: ALT1 mux port: 1588_EVENT0_IN of instance: ENET1 + 0x1 + + + ALT5_USDHC2_RESET_B + Select mux mode: ALT5 mux port: RESET_B of instance: USDHC2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO08 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO09 + SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Control Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO09 + Select mux mode: ALT0 mux port: IO09 of instance: GPIO1 + 0 + + + ALT1_ENET1_1588_EVENT0_OUT + Select mux mode: ALT1 mux port: 1588_EVENT0_OUT of instance: ENET1 + 0x1 + + + ALT5_SDMA2_EXT_EVENT0 + Select mux mode: ALT5 mux port: EXT_EVENT0 of instance: SDMA2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO09 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO10 + SW_MUX_CTL_PAD_GPIO1_IO10 SW MUX Control Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO10 + Select mux mode: ALT0 mux port: IO10 of instance: GPIO1 + 0 + + + ALT1_USB1_OTG_ID + Select mux mode: ALT1 mux port: OTG_ID of instance: USB1 + 0x1 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO10 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO11 + SW_MUX_CTL_PAD_GPIO1_IO11 SW MUX Control Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO11 + Select mux mode: ALT0 mux port: IO11 of instance: GPIO1 + 0 + + + ALT1_USB2_OTG_ID + Select mux mode: ALT1 mux port: OTG_ID of instance: USB2 + 0x1 + + + ALT5_CCM_PMIC_READY + Select mux mode: ALT5 mux port: PMIC_READY of instance: CCM + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO11 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO12 + SW_MUX_CTL_PAD_GPIO1_IO12 SW MUX Control Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO12 + Select mux mode: ALT0 mux port: IO12 of instance: GPIO1 + 0 + + + ALT1_USB1_OTG_PWR + Select mux mode: ALT1 mux port: OTG_PWR of instance: USB1 + 0x1 + + + ALT5_SDMA2_EXT_EVENT1 + Select mux mode: ALT5 mux port: EXT_EVENT1 of instance: SDMA2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO12 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO13 + SW_MUX_CTL_PAD_GPIO1_IO13 SW MUX Control Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO13 + Select mux mode: ALT0 mux port: IO13 of instance: GPIO1 + 0 + + + ALT1_USB1_OTG_OC + Select mux mode: ALT1 mux port: OTG_OC of instance: USB1 + 0x1 + + + ALT5_PWM2_OUT + Select mux mode: ALT5 mux port: OUT of instance: PWM2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO13 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO14 + SW_MUX_CTL_PAD_GPIO1_IO14 SW MUX Control Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO14 + Select mux mode: ALT0 mux port: IO14 of instance: GPIO1 + 0 + + + ALT1_USB2_OTG_PWR + Select mux mode: ALT1 mux port: OTG_PWR of instance: USB2 + 0x1 + + + ALT5_PWM3_OUT + Select mux mode: ALT5 mux port: OUT of instance: PWM3 + 0x5 + + + ALT6_CCM_CLKO1 + Select mux mode: ALT6 mux port: CLKO1 of instance: CCM + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO14 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO15 + SW_MUX_CTL_PAD_GPIO1_IO15 SW MUX Control Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_GPIO1_IO15 + Select mux mode: ALT0 mux port: IO15 of instance: GPIO1 + 0 + + + ALT1_USB2_OTG_OC + Select mux mode: ALT1 mux port: OTG_OC of instance: USB2 + 0x1 + + + ALT5_PWM4_OUT + Select mux mode: ALT5 mux port: OUT of instance: PWM4 + 0x5 + + + ALT6_CCM_CLKO2 + Select mux mode: ALT6 mux port: CLKO2 of instance: CCM + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad GPIO1_IO15 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad GPIO1_IO15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_MDC + SW_MUX_CTL_PAD_ENET_MDC SW MUX Control Register + 0x68 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_MDC + Select mux mode: ALT0 mux port: MDC of instance: ENET1 + 0 + + + ALT5_GPIO1_IO16 + Select mux mode: ALT5 mux port: IO16 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_MDC is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_MDC + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_MDIO + SW_MUX_CTL_PAD_ENET_MDIO SW MUX Control Register + 0x6C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_MDIO + Select mux mode: ALT0 mux port: MDIO of instance: ENET1 + 0 + + + ALT5_GPIO1_IO17 + Select mux mode: ALT5 mux port: IO17 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_MDIO is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_MDIO + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_TD3 + SW_MUX_CTL_PAD_ENET_TD3 SW MUX Control Register + 0x70 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_RGMII_TD3 + Select mux mode: ALT0 mux port: RGMII_TD3 of instance: ENET1 + 0 + + + ALT5_GPIO1_IO18 + Select mux mode: ALT5 mux port: IO18 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_TD3 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_TD3 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_TD2 + SW_MUX_CTL_PAD_ENET_TD2 SW MUX Control Register + 0x74 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_RGMII_TD2 + Select mux mode: ALT0 mux port: RGMII_TD2 of instance: ENET1 + 0 + + + ALT1_ENET1_TX_CLK + Select mux mode: ALT1 mux port: TX_CLK of instance: ENET1 + 0x1 + + + ALT5_GPIO1_IO19 + Select mux mode: ALT5 mux port: IO19 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_TD2 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_TD2 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_TD1 + SW_MUX_CTL_PAD_ENET_TD1 SW MUX Control Register + 0x78 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_RGMII_TD1 + Select mux mode: ALT0 mux port: RGMII_TD1 of instance: ENET1 + 0 + + + ALT5_GPIO1_IO20 + Select mux mode: ALT5 mux port: IO20 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_TD1 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_TD1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_TD0 + SW_MUX_CTL_PAD_ENET_TD0 SW MUX Control Register + 0x7C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_RGMII_TD0 + Select mux mode: ALT0 mux port: RGMII_TD0 of instance: ENET1 + 0 + + + ALT5_GPIO1_IO21 + Select mux mode: ALT5 mux port: IO21 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_TD0 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_TD0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_TX_CTL + SW_MUX_CTL_PAD_ENET_TX_CTL SW MUX Control Register + 0x80 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_RGMII_TX_CTL + Select mux mode: ALT0 mux port: RGMII_TX_CTL of instance: ENET1 + 0 + + + ALT5_GPIO1_IO22 + Select mux mode: ALT5 mux port: IO22 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_TX_CTL is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_TX_CTL + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_TXC + SW_MUX_CTL_PAD_ENET_TXC SW MUX Control Register + 0x84 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_RGMII_TXC + Select mux mode: ALT0 mux port: RGMII_TXC of instance: ENET1 + 0 + + + ALT1_ENET1_TX_ER + Select mux mode: ALT1 mux port: TX_ER of instance: ENET1 + 0x1 + + + ALT5_GPIO1_IO23 + Select mux mode: ALT5 mux port: IO23 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_TXC is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_TXC + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_RX_CTL + SW_MUX_CTL_PAD_ENET_RX_CTL SW MUX Control Register + 0x88 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_RGMII_RX_CTL + Select mux mode: ALT0 mux port: RGMII_RX_CTL of instance: ENET1 + 0 + + + ALT5_GPIO1_IO24 + Select mux mode: ALT5 mux port: IO24 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_RX_CTL is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_RX_CTL + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_RXC + SW_MUX_CTL_PAD_ENET_RXC SW MUX Control Register + 0x8C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_RGMII_RXC + Select mux mode: ALT0 mux port: RGMII_RXC of instance: ENET1 + 0 + + + ALT1_ENET1_RX_ER + Select mux mode: ALT1 mux port: RX_ER of instance: ENET1 + 0x1 + + + ALT5_GPIO1_IO25 + Select mux mode: ALT5 mux port: IO25 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_RXC is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_RXC + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_RD0 + SW_MUX_CTL_PAD_ENET_RD0 SW MUX Control Register + 0x90 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_RGMII_RD0 + Select mux mode: ALT0 mux port: RGMII_RD0 of instance: ENET1 + 0 + + + ALT5_GPIO1_IO26 + Select mux mode: ALT5 mux port: IO26 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_RD0 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_RD0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_RD1 + SW_MUX_CTL_PAD_ENET_RD1 SW MUX Control Register + 0x94 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_RGMII_RD1 + Select mux mode: ALT0 mux port: RGMII_RD1 of instance: ENET1 + 0 + + + ALT5_GPIO1_IO27 + Select mux mode: ALT5 mux port: IO27 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_RD1 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_RD1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_RD2 + SW_MUX_CTL_PAD_ENET_RD2 SW MUX Control Register + 0x98 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_RGMII_RD2 + Select mux mode: ALT0 mux port: RGMII_RD2 of instance: ENET1 + 0 + + + ALT5_GPIO1_IO28 + Select mux mode: ALT5 mux port: IO28 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_RD2 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_RD2 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET_RD3 + SW_MUX_CTL_PAD_ENET_RD3 SW MUX Control Register + 0x9C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ENET1_RGMII_RD3 + Select mux mode: ALT0 mux port: RGMII_RD3 of instance: ENET1 + 0 + + + ALT5_GPIO1_IO29 + Select mux mode: ALT5 mux port: IO29 of instance: GPIO1 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ENET_RD3 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ENET_RD3 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_CLK + SW_MUX_CTL_PAD_SD1_CLK SW MUX Control Register + 0xA0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC1_CLK + Select mux mode: ALT0 mux port: CLK of instance: USDHC1 + 0 + + + ALT5_GPIO2_IO00 + Select mux mode: ALT5 mux port: IO00 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD1_CLK is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD1_CLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_CMD + SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register + 0xA4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC1_CMD + Select mux mode: ALT0 mux port: CMD of instance: USDHC1 + 0 + + + ALT5_GPIO2_IO01 + Select mux mode: ALT5 mux port: IO01 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD1_CMD is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD1_CMD + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA0 + SW_MUX_CTL_PAD_SD1_DATA0 SW MUX Control Register + 0xA8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC1_DATA0 + Select mux mode: ALT0 mux port: DATA0 of instance: USDHC1 + 0 + + + ALT5_GPIO2_IO02 + Select mux mode: ALT5 mux port: IO02 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD1_DATA0 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD1_DATA0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA1 + SW_MUX_CTL_PAD_SD1_DATA1 SW MUX Control Register + 0xAC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC1_DATA1 + Select mux mode: ALT0 mux port: DATA1 of instance: USDHC1 + 0 + + + ALT5_GPIO2_IO03 + Select mux mode: ALT5 mux port: IO03 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD1_DATA1 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD1_DATA1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA2 + SW_MUX_CTL_PAD_SD1_DATA2 SW MUX Control Register + 0xB0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC1_DATA2 + Select mux mode: ALT0 mux port: DATA2 of instance: USDHC1 + 0 + + + ALT5_GPIO2_IO04 + Select mux mode: ALT5 mux port: IO04 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD1_DATA2 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD1_DATA2 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA3 + SW_MUX_CTL_PAD_SD1_DATA3 SW MUX Control Register + 0xB4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC1_DATA3 + Select mux mode: ALT0 mux port: DATA3 of instance: USDHC1 + 0 + + + ALT5_GPIO2_IO05 + Select mux mode: ALT5 mux port: IO05 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD1_DATA3 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD1_DATA3 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA4 + SW_MUX_CTL_PAD_SD1_DATA4 SW MUX Control Register + 0xB8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC1_DATA4 + Select mux mode: ALT0 mux port: DATA4 of instance: USDHC1 + 0 + + + ALT5_GPIO2_IO06 + Select mux mode: ALT5 mux port: IO06 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD1_DATA4 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD1_DATA4 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA5 + SW_MUX_CTL_PAD_SD1_DATA5 SW MUX Control Register + 0xBC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC1_DATA5 + Select mux mode: ALT0 mux port: DATA5 of instance: USDHC1 + 0 + + + ALT5_GPIO2_IO07 + Select mux mode: ALT5 mux port: IO07 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD1_DATA5 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD1_DATA5 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA6 + SW_MUX_CTL_PAD_SD1_DATA6 SW MUX Control Register + 0xC0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC1_DATA6 + Select mux mode: ALT0 mux port: DATA6 of instance: USDHC1 + 0 + + + ALT5_GPIO2_IO08 + Select mux mode: ALT5 mux port: IO08 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD1_DATA6 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD1_DATA6 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA7 + SW_MUX_CTL_PAD_SD1_DATA7 SW MUX Control Register + 0xC4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC1_DATA7 + Select mux mode: ALT0 mux port: DATA7 of instance: USDHC1 + 0 + + + ALT5_GPIO2_IO09 + Select mux mode: ALT5 mux port: IO09 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD1_DATA7 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD1_DATA7 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_RESET_B + SW_MUX_CTL_PAD_SD1_RESET_B SW MUX Control Register + 0xC8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC1_RESET_B + Select mux mode: ALT0 mux port: RESET_B of instance: USDHC1 + 0 + + + ALT5_GPIO2_IO10 + Select mux mode: ALT5 mux port: IO10 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD1_RESET_B is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD1_RESET_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_STROBE + SW_MUX_CTL_PAD_SD1_STROBE SW MUX Control Register + 0xCC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC1_STROBE + Select mux mode: ALT0 mux port: STROBE of instance: USDHC1 + 0 + + + ALT5_GPIO2_IO11 + Select mux mode: ALT5 mux port: IO11 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD1_STROBE is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD1_STROBE + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD2_CD_B + SW_MUX_CTL_PAD_SD2_CD_B SW MUX Control Register + 0xD0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC2_CD_B + Select mux mode: ALT0 mux port: CD_B of instance: USDHC2 + 0 + + + ALT5_GPIO2_IO12 + Select mux mode: ALT5 mux port: IO12 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD2_CD_B is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD2_CD_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD2_CLK + SW_MUX_CTL_PAD_SD2_CLK SW MUX Control Register + 0xD4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC2_CLK + Select mux mode: ALT0 mux port: CLK of instance: USDHC2 + 0 + + + ALT5_GPIO2_IO13 + Select mux mode: ALT5 mux port: IO13 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD2_CLK is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD2_CLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD2_CMD + SW_MUX_CTL_PAD_SD2_CMD SW MUX Control Register + 0xD8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC2_CMD + Select mux mode: ALT0 mux port: CMD of instance: USDHC2 + 0 + + + ALT5_GPIO2_IO14 + Select mux mode: ALT5 mux port: IO14 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD2_CMD is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD2_CMD + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD2_DATA0 + SW_MUX_CTL_PAD_SD2_DATA0 SW MUX Control Register + 0xDC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC2_DATA0 + Select mux mode: ALT0 mux port: DATA0 of instance: USDHC2 + 0 + + + ALT5_GPIO2_IO15 + Select mux mode: ALT5 mux port: IO15 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD2_DATA0 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD2_DATA0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD2_DATA1 + SW_MUX_CTL_PAD_SD2_DATA1 SW MUX Control Register + 0xE0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC2_DATA1 + Select mux mode: ALT0 mux port: DATA1 of instance: USDHC2 + 0 + + + ALT5_GPIO2_IO16 + Select mux mode: ALT5 mux port: IO16 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD2_DATA1 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD2_DATA1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD2_DATA2 + SW_MUX_CTL_PAD_SD2_DATA2 SW MUX Control Register + 0xE4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC2_DATA2 + Select mux mode: ALT0 mux port: DATA2 of instance: USDHC2 + 0 + + + ALT5_GPIO2_IO17 + Select mux mode: ALT5 mux port: IO17 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD2_DATA2 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD2_DATA2 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD2_DATA3 + SW_MUX_CTL_PAD_SD2_DATA3 SW MUX Control Register + 0xE8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC2_DATA3 + Select mux mode: ALT0 mux port: DATA3 of instance: USDHC2 + 0 + + + ALT5_GPIO2_IO18 + Select mux mode: ALT5 mux port: IO18 of instance: GPIO2 + 0x5 + + + ALT6_SRC_EARLY_RESET + Select mux mode: ALT6 mux port: EARLY_RESET of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD2_DATA3 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD2_DATA3 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD2_RESET_B + SW_MUX_CTL_PAD_SD2_RESET_B SW MUX Control Register + 0xEC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC2_RESET_B + Select mux mode: ALT0 mux port: RESET_B of instance: USDHC2 + 0 + + + ALT5_GPIO2_IO19 + Select mux mode: ALT5 mux port: IO19 of instance: GPIO2 + 0x5 + + + ALT6_SRC_SYSTEM_RESET + Select mux mode: ALT6 mux port: SYSTEM_RESET of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD2_RESET_B is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD2_RESET_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD2_WP + SW_MUX_CTL_PAD_SD2_WP SW MUX Control Register + 0xF0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_USDHC2_WP + Select mux mode: ALT0 mux port: WP of instance: USDHC2 + 0 + + + ALT5_GPIO2_IO20 + Select mux mode: ALT5 mux port: IO20 of instance: GPIO2 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SD2_WP is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SD2_WP + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_ALE + SW_MUX_CTL_PAD_NAND_ALE SW MUX Control Register + 0xF4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_ALE + Select mux mode: ALT0 mux port: ALE of instance: RAWNAND + 0 + + + ALT1_QSPI_A_SCLK + Select mux mode: ALT1 mux port: A_SCLK of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO00 + Select mux mode: ALT5 mux port: IO00 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_ALE is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_ALE + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_CE0_B + SW_MUX_CTL_PAD_NAND_CE0_B SW MUX Control Register + 0xF8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_CE0_B + Select mux mode: ALT0 mux port: CE0_B of instance: RAWNAND + 0 + + + ALT1_QSPI_A_SS0_B + Select mux mode: ALT1 mux port: A_SS0_B of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO01 + Select mux mode: ALT5 mux port: IO01 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_CE0_B is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_CE0_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_CE1_B + SW_MUX_CTL_PAD_NAND_CE1_B SW MUX Control Register + 0xFC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_CE1_B + Select mux mode: ALT0 mux port: CE1_B of instance: RAWNAND + 0 + + + ALT1_QSPI_A_SS1_B + Select mux mode: ALT1 mux port: A_SS1_B of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO02 + Select mux mode: ALT5 mux port: IO02 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_CE1_B is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_CE1_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_CE2_B + SW_MUX_CTL_PAD_NAND_CE2_B SW MUX Control Register + 0x100 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_CE2_B + Select mux mode: ALT0 mux port: CE2_B of instance: RAWNAND + 0 + + + ALT1_QSPI_B_SS0_B + Select mux mode: ALT1 mux port: B_SS0_B of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO03 + Select mux mode: ALT5 mux port: IO03 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_CE2_B is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_CE2_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_CE3_B + SW_MUX_CTL_PAD_NAND_CE3_B SW MUX Control Register + 0x104 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_CE3_B + Select mux mode: ALT0 mux port: CE3_B of instance: RAWNAND + 0 + + + ALT1_QSPI_B_SS1_B + Select mux mode: ALT1 mux port: B_SS1_B of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO04 + Select mux mode: ALT5 mux port: IO04 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_CE3_B is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_CE3_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_CLE + SW_MUX_CTL_PAD_NAND_CLE SW MUX Control Register + 0x108 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_CLE + Select mux mode: ALT0 mux port: CLE of instance: RAWNAND + 0 + + + ALT1_QSPI_B_SCLK + Select mux mode: ALT1 mux port: B_SCLK of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO05 + Select mux mode: ALT5 mux port: IO05 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_CLE is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_CLE + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA00 + SW_MUX_CTL_PAD_NAND_DATA00 SW MUX Control Register + 0x10C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_DATA00 + Select mux mode: ALT0 mux port: DATA00 of instance: RAWNAND + 0 + + + ALT1_QSPI_A_DATA0 + Select mux mode: ALT1 mux port: A_DATA0 of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO06 + Select mux mode: ALT5 mux port: IO06 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_DATA00 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_DATA00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA01 + SW_MUX_CTL_PAD_NAND_DATA01 SW MUX Control Register + 0x110 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_DATA01 + Select mux mode: ALT0 mux port: DATA01 of instance: RAWNAND + 0 + + + ALT1_QSPI_A_DATA1 + Select mux mode: ALT1 mux port: A_DATA1 of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO07 + Select mux mode: ALT5 mux port: IO07 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_DATA01 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_DATA01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA02 + SW_MUX_CTL_PAD_NAND_DATA02 SW MUX Control Register + 0x114 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_DATA02 + Select mux mode: ALT0 mux port: DATA02 of instance: RAWNAND + 0 + + + ALT1_QSPI_A_DATA2 + Select mux mode: ALT1 mux port: A_DATA2 of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO08 + Select mux mode: ALT5 mux port: IO08 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_DATA02 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_DATA02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA03 + SW_MUX_CTL_PAD_NAND_DATA03 SW MUX Control Register + 0x118 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_DATA03 + Select mux mode: ALT0 mux port: DATA03 of instance: RAWNAND + 0 + + + ALT1_QSPI_A_DATA3 + Select mux mode: ALT1 mux port: A_DATA3 of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO09 + Select mux mode: ALT5 mux port: IO09 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_DATA03 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_DATA03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA04 + SW_MUX_CTL_PAD_NAND_DATA04 SW MUX Control Register + 0x11C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_DATA04 + Select mux mode: ALT0 mux port: DATA04 of instance: RAWNAND + 0 + + + ALT1_QSPI_B_DATA0 + Select mux mode: ALT1 mux port: B_DATA0 of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO10 + Select mux mode: ALT5 mux port: IO10 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_DATA04 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_DATA04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA05 + SW_MUX_CTL_PAD_NAND_DATA05 SW MUX Control Register + 0x120 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_DATA05 + Select mux mode: ALT0 mux port: DATA05 of instance: RAWNAND + 0 + + + ALT1_QSPI_B_DATA1 + Select mux mode: ALT1 mux port: B_DATA1 of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO11 + Select mux mode: ALT5 mux port: IO11 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_DATA05 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_DATA05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA06 + SW_MUX_CTL_PAD_NAND_DATA06 SW MUX Control Register + 0x124 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_DATA06 + Select mux mode: ALT0 mux port: DATA06 of instance: RAWNAND + 0 + + + ALT1_QSPI_B_DATA2 + Select mux mode: ALT1 mux port: B_DATA2 of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO12 + Select mux mode: ALT5 mux port: IO12 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_DATA06 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_DATA06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA07 + SW_MUX_CTL_PAD_NAND_DATA07 SW MUX Control Register + 0x128 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_DATA07 + Select mux mode: ALT0 mux port: DATA07 of instance: RAWNAND + 0 + + + ALT1_QSPI_B_DATA3 + Select mux mode: ALT1 mux port: B_DATA3 of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO13 + Select mux mode: ALT5 mux port: IO13 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_DATA07 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_DATA07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DQS + SW_MUX_CTL_PAD_NAND_DQS SW MUX Control Register + 0x12C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_DQS + Select mux mode: ALT0 mux port: DQS of instance: RAWNAND + 0 + + + ALT1_QSPI_A_DQS + Select mux mode: ALT1 mux port: A_DQS of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO14 + Select mux mode: ALT5 mux port: IO14 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_DQS is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_DQS + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_RE_B + SW_MUX_CTL_PAD_NAND_RE_B SW MUX Control Register + 0x130 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_RE_B + Select mux mode: ALT0 mux port: RE_B of instance: RAWNAND + 0 + + + ALT1_QSPI_B_DQS + Select mux mode: ALT1 mux port: B_DQS of instance: QSPI + 0x1 + + + ALT5_GPIO3_IO15 + Select mux mode: ALT5 mux port: IO15 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_RE_B is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_RE_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_READY_B + SW_MUX_CTL_PAD_NAND_READY_B SW MUX Control Register + 0x134 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_READY_B + Select mux mode: ALT0 mux port: READY_B of instance: RAWNAND + 0 + + + ALT5_GPIO3_IO16 + Select mux mode: ALT5 mux port: IO16 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_READY_B is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_READY_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_WE_B + SW_MUX_CTL_PAD_NAND_WE_B SW MUX Control Register + 0x138 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_WE_B + Select mux mode: ALT0 mux port: WE_B of instance: RAWNAND + 0 + + + ALT5_GPIO3_IO17 + Select mux mode: ALT5 mux port: IO17 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_WE_B is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_WE_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_WP_B + SW_MUX_CTL_PAD_NAND_WP_B SW MUX Control Register + 0x13C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_RAWNAND_WP_B + Select mux mode: ALT0 mux port: WP_B of instance: RAWNAND + 0 + + + ALT5_GPIO3_IO18 + Select mux mode: ALT5 mux port: IO18 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad NAND_WP_B is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad NAND_WP_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI5_RXFS + SW_MUX_CTL_PAD_SAI5_RXFS SW MUX Control Register + 0x140 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI5_RX_SYNC + Select mux mode: ALT0 mux port: RX_SYNC of instance: SAI5 + 0 + + + ALT1_SAI1_TX_DATA0 + Select mux mode: ALT1 mux port: TX_DATA0 of instance: SAI1 + 0x1 + + + ALT5_GPIO3_IO19 + Select mux mode: ALT5 mux port: IO19 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI5_RXFS is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI5_RXFS + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI5_RXC + SW_MUX_CTL_PAD_SAI5_RXC SW MUX Control Register + 0x144 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI5_RX_BCLK + Select mux mode: ALT0 mux port: RX_BCLK of instance: SAI5 + 0 + + + ALT1_SAI1_TX_DATA1 + Select mux mode: ALT1 mux port: TX_DATA1 of instance: SAI1 + 0x1 + + + ALT5_GPIO3_IO20 + Select mux mode: ALT5 mux port: IO20 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI5_RXC is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI5_RXC + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI5_RXD0 + SW_MUX_CTL_PAD_SAI5_RXD0 SW MUX Control Register + 0x148 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI5_RX_DATA0 + Select mux mode: ALT0 mux port: RX_DATA0 of instance: SAI5 + 0 + + + ALT1_SAI1_TX_DATA2 + Select mux mode: ALT1 mux port: TX_DATA2 of instance: SAI1 + 0x1 + + + ALT5_GPIO3_IO21 + Select mux mode: ALT5 mux port: IO21 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI5_RXD0 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI5_RXD0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI5_RXD1 + SW_MUX_CTL_PAD_SAI5_RXD1 SW MUX Control Register + 0x14C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI5_RX_DATA1 + Select mux mode: ALT0 mux port: RX_DATA1 of instance: SAI5 + 0 + + + ALT1_SAI1_TX_DATA3 + Select mux mode: ALT1 mux port: TX_DATA3 of instance: SAI1 + 0x1 + + + ALT2_SAI1_TX_SYNC + Select mux mode: ALT2 mux port: TX_SYNC of instance: SAI1 + 0x2 + + + ALT3_SAI5_TX_SYNC + Select mux mode: ALT3 mux port: TX_SYNC of instance: SAI5 + 0x3 + + + ALT5_GPIO3_IO22 + Select mux mode: ALT5 mux port: IO22 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI5_RXD1 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI5_RXD1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI5_RXD2 + SW_MUX_CTL_PAD_SAI5_RXD2 SW MUX Control Register + 0x150 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI5_RX_DATA2 + Select mux mode: ALT0 mux port: RX_DATA2 of instance: SAI5 + 0 + + + ALT1_SAI1_TX_DATA4 + Select mux mode: ALT1 mux port: TX_DATA4 of instance: SAI1 + 0x1 + + + ALT2_SAI1_TX_SYNC + Select mux mode: ALT2 mux port: TX_SYNC of instance: SAI1 + 0x2 + + + ALT3_SAI5_TX_BCLK + Select mux mode: ALT3 mux port: TX_BCLK of instance: SAI5 + 0x3 + + + ALT5_GPIO3_IO23 + Select mux mode: ALT5 mux port: IO23 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI5_RXD2 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI5_RXD2 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI5_RXD3 + SW_MUX_CTL_PAD_SAI5_RXD3 SW MUX Control Register + 0x154 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI5_RX_DATA3 + Select mux mode: ALT0 mux port: RX_DATA3 of instance: SAI5 + 0 + + + ALT1_SAI1_TX_DATA5 + Select mux mode: ALT1 mux port: TX_DATA5 of instance: SAI1 + 0x1 + + + ALT2_SAI1_TX_SYNC + Select mux mode: ALT2 mux port: TX_SYNC of instance: SAI1 + 0x2 + + + ALT3_SAI5_TX_DATA0 + Select mux mode: ALT3 mux port: TX_DATA0 of instance: SAI5 + 0x3 + + + ALT5_GPIO3_IO24 + Select mux mode: ALT5 mux port: IO24 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI5_RXD3 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI5_RXD3 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI5_MCLK + SW_MUX_CTL_PAD_SAI5_MCLK SW MUX Control Register + 0x158 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI5_MCLK + Select mux mode: ALT0 mux port: MCLK of instance: SAI5 + 0 + + + ALT1_SAI1_TX_BCLK + Select mux mode: ALT1 mux port: TX_BCLK of instance: SAI1 + 0x1 + + + ALT2_SAI4_MCLK + Select mux mode: ALT2 mux port: MCLK of instance: SAI4 + 0x2 + + + ALT5_GPIO3_IO25 + Select mux mode: ALT5 mux port: IO25 of instance: GPIO3 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI5_MCLK is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI5_MCLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_RXFS + SW_MUX_CTL_PAD_SAI1_RXFS SW MUX Control Register + 0x15C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_RX_SYNC + Select mux mode: ALT0 mux port: RX_SYNC of instance: SAI1 + 0 + + + ALT1_SAI5_RX_SYNC + Select mux mode: ALT1 mux port: RX_SYNC of instance: SAI5 + 0x1 + + + ALT4_CORESIGHT_TRACE_CLK + Select mux mode: ALT4 mux port: TRACE_CLK of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO00 + Select mux mode: ALT5 mux port: IO00 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_RXFS is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_RXFS + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_RXC + SW_MUX_CTL_PAD_SAI1_RXC SW MUX Control Register + 0x160 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_RX_BCLK + Select mux mode: ALT0 mux port: RX_BCLK of instance: SAI1 + 0 + + + ALT1_SAI5_RX_BCLK + Select mux mode: ALT1 mux port: RX_BCLK of instance: SAI5 + 0x1 + + + ALT4_CORESIGHT_TRACE_CTL + Select mux mode: ALT4 mux port: TRACE_CTL of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO01 + Select mux mode: ALT5 mux port: IO01 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_RXC is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_RXC + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_RXD0 + SW_MUX_CTL_PAD_SAI1_RXD0 SW MUX Control Register + 0x164 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_RX_DATA0 + Select mux mode: ALT0 mux port: RX_DATA0 of instance: SAI1 + 0 + + + ALT1_SAI5_RX_DATA0 + Select mux mode: ALT1 mux port: RX_DATA0 of instance: SAI5 + 0x1 + + + ALT4_CORESIGHT_TRACE0 + Select mux mode: ALT4 mux port: TRACE0 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO02 + Select mux mode: ALT5 mux port: IO02 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG0 + Select mux mode: ALT6 mux port: BOOT_CFG0 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_RXD0 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_RXD0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_RXD1 + SW_MUX_CTL_PAD_SAI1_RXD1 SW MUX Control Register + 0x168 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_RX_DATA1 + Select mux mode: ALT0 mux port: RX_DATA1 of instance: SAI1 + 0 + + + ALT1_SAI5_RX_DATA1 + Select mux mode: ALT1 mux port: RX_DATA1 of instance: SAI5 + 0x1 + + + ALT4_CORESIGHT_TRACE1 + Select mux mode: ALT4 mux port: TRACE1 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO03 + Select mux mode: ALT5 mux port: IO03 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG1 + Select mux mode: ALT6 mux port: BOOT_CFG1 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_RXD1 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_RXD1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_RXD2 + SW_MUX_CTL_PAD_SAI1_RXD2 SW MUX Control Register + 0x16C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_RX_DATA2 + Select mux mode: ALT0 mux port: RX_DATA2 of instance: SAI1 + 0 + + + ALT1_SAI5_RX_DATA2 + Select mux mode: ALT1 mux port: RX_DATA2 of instance: SAI5 + 0x1 + + + ALT4_CORESIGHT_TRACE2 + Select mux mode: ALT4 mux port: TRACE2 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO04 + Select mux mode: ALT5 mux port: IO04 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG2 + Select mux mode: ALT6 mux port: BOOT_CFG2 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_RXD2 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_RXD2 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_RXD3 + SW_MUX_CTL_PAD_SAI1_RXD3 SW MUX Control Register + 0x170 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_RX_DATA3 + Select mux mode: ALT0 mux port: RX_DATA3 of instance: SAI1 + 0 + + + ALT1_SAI5_RX_DATA3 + Select mux mode: ALT1 mux port: RX_DATA3 of instance: SAI5 + 0x1 + + + ALT4_CORESIGHT_TRACE3 + Select mux mode: ALT4 mux port: TRACE3 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO05 + Select mux mode: ALT5 mux port: IO05 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG3 + Select mux mode: ALT6 mux port: BOOT_CFG3 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_RXD3 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_RXD3 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_RXD4 + SW_MUX_CTL_PAD_SAI1_RXD4 SW MUX Control Register + 0x174 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_RX_DATA4 + Select mux mode: ALT0 mux port: RX_DATA4 of instance: SAI1 + 0 + + + ALT1_SAI6_TX_BCLK + Select mux mode: ALT1 mux port: TX_BCLK of instance: SAI6 + 0x1 + + + ALT2_SAI6_RX_BCLK + Select mux mode: ALT2 mux port: RX_BCLK of instance: SAI6 + 0x2 + + + ALT4_CORESIGHT_TRACE4 + Select mux mode: ALT4 mux port: TRACE4 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO06 + Select mux mode: ALT5 mux port: IO06 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG4 + Select mux mode: ALT6 mux port: BOOT_CFG4 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_RXD4 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_RXD4 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_RXD5 + SW_MUX_CTL_PAD_SAI1_RXD5 SW MUX Control Register + 0x178 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_RX_DATA5 + Select mux mode: ALT0 mux port: RX_DATA5 of instance: SAI1 + 0 + + + ALT1_SAI6_TX_DATA0 + Select mux mode: ALT1 mux port: TX_DATA0 of instance: SAI6 + 0x1 + + + ALT2_SAI6_RX_DATA0 + Select mux mode: ALT2 mux port: RX_DATA0 of instance: SAI6 + 0x2 + + + ALT3_SAI1_RX_SYNC + Select mux mode: ALT3 mux port: RX_SYNC of instance: SAI1 + 0x3 + + + ALT4_CORESIGHT_TRACE5 + Select mux mode: ALT4 mux port: TRACE5 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO07 + Select mux mode: ALT5 mux port: IO07 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG5 + Select mux mode: ALT6 mux port: BOOT_CFG5 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_RXD5 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_RXD5 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_RXD6 + SW_MUX_CTL_PAD_SAI1_RXD6 SW MUX Control Register + 0x17C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_RX_DATA6 + Select mux mode: ALT0 mux port: RX_DATA6 of instance: SAI1 + 0 + + + ALT1_SAI6_TX_SYNC + Select mux mode: ALT1 mux port: TX_SYNC of instance: SAI6 + 0x1 + + + ALT2_SAI6_RX_SYNC + Select mux mode: ALT2 mux port: RX_SYNC of instance: SAI6 + 0x2 + + + ALT4_CORESIGHT_TRACE6 + Select mux mode: ALT4 mux port: TRACE6 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO08 + Select mux mode: ALT5 mux port: IO08 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG6 + Select mux mode: ALT6 mux port: BOOT_CFG6 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_RXD6 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_RXD6 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_RXD7 + SW_MUX_CTL_PAD_SAI1_RXD7 SW MUX Control Register + 0x180 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_RX_DATA7 + Select mux mode: ALT0 mux port: RX_DATA7 of instance: SAI1 + 0 + + + ALT1_SAI6_MCLK + Select mux mode: ALT1 mux port: MCLK of instance: SAI6 + 0x1 + + + ALT2_SAI1_TX_SYNC + Select mux mode: ALT2 mux port: TX_SYNC of instance: SAI1 + 0x2 + + + ALT3_SAI1_TX_DATA4 + Select mux mode: ALT3 mux port: TX_DATA4 of instance: SAI1 + 0x3 + + + ALT4_CORESIGHT_TRACE7 + Select mux mode: ALT4 mux port: TRACE7 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO09 + Select mux mode: ALT5 mux port: IO09 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG7 + Select mux mode: ALT6 mux port: BOOT_CFG7 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_RXD7 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_RXD7 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_TXFS + SW_MUX_CTL_PAD_SAI1_TXFS SW MUX Control Register + 0x184 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_TX_SYNC + Select mux mode: ALT0 mux port: TX_SYNC of instance: SAI1 + 0 + + + ALT1_SAI5_TX_SYNC + Select mux mode: ALT1 mux port: TX_SYNC of instance: SAI5 + 0x1 + + + ALT4_CORESIGHT_EVENTO + Select mux mode: ALT4 mux port: EVENTO of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO10 + Select mux mode: ALT5 mux port: IO10 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_TXFS is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_TXFS + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_TXC + SW_MUX_CTL_PAD_SAI1_TXC SW MUX Control Register + 0x188 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_TX_BCLK + Select mux mode: ALT0 mux port: TX_BCLK of instance: SAI1 + 0 + + + ALT1_SAI5_TX_BCLK + Select mux mode: ALT1 mux port: TX_BCLK of instance: SAI5 + 0x1 + + + ALT4_CORESIGHT_EVENTI + Select mux mode: ALT4 mux port: EVENTI of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO11 + Select mux mode: ALT5 mux port: IO11 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_TXC is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_TXC + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_TXD0 + SW_MUX_CTL_PAD_SAI1_TXD0 SW MUX Control Register + 0x18C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_TX_DATA0 + Select mux mode: ALT0 mux port: TX_DATA0 of instance: SAI1 + 0 + + + ALT1_SAI5_TX_DATA0 + Select mux mode: ALT1 mux port: TX_DATA0 of instance: SAI5 + 0x1 + + + ALT4_CORESIGHT_TRACE8 + Select mux mode: ALT4 mux port: TRACE8 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO12 + Select mux mode: ALT5 mux port: IO12 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG8 + Select mux mode: ALT6 mux port: BOOT_CFG8 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_TXD0 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_TXD0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_TXD1 + SW_MUX_CTL_PAD_SAI1_TXD1 SW MUX Control Register + 0x190 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_TX_DATA1 + Select mux mode: ALT0 mux port: TX_DATA1 of instance: SAI1 + 0 + + + ALT1_SAI5_TX_DATA1 + Select mux mode: ALT1 mux port: TX_DATA1 of instance: SAI5 + 0x1 + + + ALT4_CORESIGHT_TRACE9 + Select mux mode: ALT4 mux port: TRACE9 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO13 + Select mux mode: ALT5 mux port: IO13 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG9 + Select mux mode: ALT6 mux port: BOOT_CFG9 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_TXD1 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_TXD1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_TXD2 + SW_MUX_CTL_PAD_SAI1_TXD2 SW MUX Control Register + 0x194 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_TX_DATA2 + Select mux mode: ALT0 mux port: TX_DATA2 of instance: SAI1 + 0 + + + ALT1_SAI5_TX_DATA2 + Select mux mode: ALT1 mux port: TX_DATA2 of instance: SAI5 + 0x1 + + + ALT4_CORESIGHT_TRACE10 + Select mux mode: ALT4 mux port: TRACE10 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO14 + Select mux mode: ALT5 mux port: IO14 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG10 + Select mux mode: ALT6 mux port: BOOT_CFG10 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_TXD2 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_TXD2 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_TXD3 + SW_MUX_CTL_PAD_SAI1_TXD3 SW MUX Control Register + 0x198 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_TX_DATA3 + Select mux mode: ALT0 mux port: TX_DATA3 of instance: SAI1 + 0 + + + ALT1_SAI5_TX_DATA3 + Select mux mode: ALT1 mux port: TX_DATA3 of instance: SAI5 + 0x1 + + + ALT4_CORESIGHT_TRACE11 + Select mux mode: ALT4 mux port: TRACE11 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO15 + Select mux mode: ALT5 mux port: IO15 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG11 + Select mux mode: ALT6 mux port: BOOT_CFG11 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_TXD3 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_TXD3 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_TXD4 + SW_MUX_CTL_PAD_SAI1_TXD4 SW MUX Control Register + 0x19C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_TX_DATA4 + Select mux mode: ALT0 mux port: TX_DATA4 of instance: SAI1 + 0 + + + ALT1_SAI6_RX_BCLK + Select mux mode: ALT1 mux port: RX_BCLK of instance: SAI6 + 0x1 + + + ALT2_SAI6_TX_BCLK + Select mux mode: ALT2 mux port: TX_BCLK of instance: SAI6 + 0x2 + + + ALT4_CORESIGHT_TRACE12 + Select mux mode: ALT4 mux port: TRACE12 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO16 + Select mux mode: ALT5 mux port: IO16 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG12 + Select mux mode: ALT6 mux port: BOOT_CFG12 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_TXD4 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_TXD4 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_TXD5 + SW_MUX_CTL_PAD_SAI1_TXD5 SW MUX Control Register + 0x1A0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_TX_DATA5 + Select mux mode: ALT0 mux port: TX_DATA5 of instance: SAI1 + 0 + + + ALT1_SAI6_RX_DATA0 + Select mux mode: ALT1 mux port: RX_DATA0 of instance: SAI6 + 0x1 + + + ALT2_SAI6_TX_DATA0 + Select mux mode: ALT2 mux port: TX_DATA0 of instance: SAI6 + 0x2 + + + ALT4_CORESIGHT_TRACE13 + Select mux mode: ALT4 mux port: TRACE13 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO17 + Select mux mode: ALT5 mux port: IO17 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG13 + Select mux mode: ALT6 mux port: BOOT_CFG13 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_TXD5 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_TXD5 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_TXD6 + SW_MUX_CTL_PAD_SAI1_TXD6 SW MUX Control Register + 0x1A4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_TX_DATA6 + Select mux mode: ALT0 mux port: TX_DATA6 of instance: SAI1 + 0 + + + ALT1_SAI6_RX_SYNC + Select mux mode: ALT1 mux port: RX_SYNC of instance: SAI6 + 0x1 + + + ALT2_SAI6_TX_SYNC + Select mux mode: ALT2 mux port: TX_SYNC of instance: SAI6 + 0x2 + + + ALT4_CORESIGHT_TRACE14 + Select mux mode: ALT4 mux port: TRACE14 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO18 + Select mux mode: ALT5 mux port: IO18 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG14 + Select mux mode: ALT6 mux port: BOOT_CFG14 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_TXD6 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_TXD6 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_TXD7 + SW_MUX_CTL_PAD_SAI1_TXD7 SW MUX Control Register + 0x1A8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_TX_DATA7 + Select mux mode: ALT0 mux port: TX_DATA7 of instance: SAI1 + 0 + + + ALT1_SAI6_MCLK + Select mux mode: ALT1 mux port: MCLK of instance: SAI6 + 0x1 + + + ALT4_CORESIGHT_TRACE15 + Select mux mode: ALT4 mux port: TRACE15 of instance: CORESIGHT + 0x4 + + + ALT5_GPIO4_IO19 + Select mux mode: ALT5 mux port: IO19 of instance: GPIO4 + 0x5 + + + ALT6_SRC_BOOT_CFG15 + Select mux mode: ALT6 mux port: BOOT_CFG15 of instance: SRC + 0x6 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_TXD7 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_TXD7 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI1_MCLK + SW_MUX_CTL_PAD_SAI1_MCLK SW MUX Control Register + 0x1AC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI1_MCLK + Select mux mode: ALT0 mux port: MCLK of instance: SAI1 + 0 + + + ALT1_SAI5_MCLK + Select mux mode: ALT1 mux port: MCLK of instance: SAI5 + 0x1 + + + ALT2_SAI1_TX_BCLK + Select mux mode: ALT2 mux port: TX_BCLK of instance: SAI1 + 0x2 + + + ALT5_GPIO4_IO20 + Select mux mode: ALT5 mux port: IO20 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI1_MCLK is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI1_MCLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI2_RXFS + SW_MUX_CTL_PAD_SAI2_RXFS SW MUX Control Register + 0x1B0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI2_RX_SYNC + Select mux mode: ALT0 mux port: RX_SYNC of instance: SAI2 + 0 + + + ALT1_SAI5_TX_SYNC + Select mux mode: ALT1 mux port: TX_SYNC of instance: SAI5 + 0x1 + + + ALT5_GPIO4_IO21 + Select mux mode: ALT5 mux port: IO21 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI2_RXFS is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI2_RXFS + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI2_RXC + SW_MUX_CTL_PAD_SAI2_RXC SW MUX Control Register + 0x1B4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI2_RX_BCLK + Select mux mode: ALT0 mux port: RX_BCLK of instance: SAI2 + 0 + + + ALT1_SAI5_TX_BCLK + Select mux mode: ALT1 mux port: TX_BCLK of instance: SAI5 + 0x1 + + + ALT5_GPIO4_IO22 + Select mux mode: ALT5 mux port: IO22 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI2_RXC is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI2_RXC + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI2_RXD0 + SW_MUX_CTL_PAD_SAI2_RXD0 SW MUX Control Register + 0x1B8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI2_RX_DATA0 + Select mux mode: ALT0 mux port: RX_DATA0 of instance: SAI2 + 0 + + + ALT1_SAI5_TX_DATA0 + Select mux mode: ALT1 mux port: TX_DATA0 of instance: SAI5 + 0x1 + + + ALT5_GPIO4_IO23 + Select mux mode: ALT5 mux port: IO23 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI2_RXD0 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI2_RXD0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI2_TXFS + SW_MUX_CTL_PAD_SAI2_TXFS SW MUX Control Register + 0x1BC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI2_TX_SYNC + Select mux mode: ALT0 mux port: TX_SYNC of instance: SAI2 + 0 + + + ALT1_SAI5_TX_DATA1 + Select mux mode: ALT1 mux port: TX_DATA1 of instance: SAI5 + 0x1 + + + ALT5_GPIO4_IO24 + Select mux mode: ALT5 mux port: IO24 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI2_TXFS is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI2_TXFS + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI2_TXC + SW_MUX_CTL_PAD_SAI2_TXC SW MUX Control Register + 0x1C0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI2_TX_BCLK + Select mux mode: ALT0 mux port: TX_BCLK of instance: SAI2 + 0 + + + ALT1_SAI5_TX_DATA2 + Select mux mode: ALT1 mux port: TX_DATA2 of instance: SAI5 + 0x1 + + + ALT5_GPIO4_IO25 + Select mux mode: ALT5 mux port: IO25 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI2_TXC is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI2_TXC + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI2_TXD0 + SW_MUX_CTL_PAD_SAI2_TXD0 SW MUX Control Register + 0x1C4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI2_TX_DATA0 + Select mux mode: ALT0 mux port: TX_DATA0 of instance: SAI2 + 0 + + + ALT1_SAI5_TX_DATA3 + Select mux mode: ALT1 mux port: TX_DATA3 of instance: SAI5 + 0x1 + + + ALT5_GPIO4_IO26 + Select mux mode: ALT5 mux port: IO26 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI2_TXD0 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI2_TXD0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI2_MCLK + SW_MUX_CTL_PAD_SAI2_MCLK SW MUX Control Register + 0x1C8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI2_MCLK + Select mux mode: ALT0 mux port: MCLK of instance: SAI2 + 0 + + + ALT1_SAI5_MCLK + Select mux mode: ALT1 mux port: MCLK of instance: SAI5 + 0x1 + + + ALT5_GPIO4_IO27 + Select mux mode: ALT5 mux port: IO27 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI2_MCLK is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI2_MCLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI3_RXFS + SW_MUX_CTL_PAD_SAI3_RXFS SW MUX Control Register + 0x1CC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI3_RX_SYNC + Select mux mode: ALT0 mux port: RX_SYNC of instance: SAI3 + 0 + + + ALT1_GPT1_CAPTURE1 + Select mux mode: ALT1 mux port: CAPTURE1 of instance: GPT1 + 0x1 + + + ALT2_SAI5_RX_SYNC + Select mux mode: ALT2 mux port: RX_SYNC of instance: SAI5 + 0x2 + + + ALT5_GPIO4_IO28 + Select mux mode: ALT5 mux port: IO28 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI3_RXFS is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI3_RXFS + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI3_RXC + SW_MUX_CTL_PAD_SAI3_RXC SW MUX Control Register + 0x1D0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI3_RX_BCLK + Select mux mode: ALT0 mux port: RX_BCLK of instance: SAI3 + 0 + + + ALT1_GPT1_CAPTURE2 + Select mux mode: ALT1 mux port: CAPTURE2 of instance: GPT1 + 0x1 + + + ALT2_SAI5_RX_BCLK + Select mux mode: ALT2 mux port: RX_BCLK of instance: SAI5 + 0x2 + + + ALT5_GPIO4_IO29 + Select mux mode: ALT5 mux port: IO29 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI3_RXC is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI3_RXC + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI3_RXD + SW_MUX_CTL_PAD_SAI3_RXD SW MUX Control Register + 0x1D4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI3_RX_DATA0 + Select mux mode: ALT0 mux port: RX_DATA0 of instance: SAI3 + 0 + + + ALT1_GPT1_COMPARE1 + Select mux mode: ALT1 mux port: COMPARE1 of instance: GPT1 + 0x1 + + + ALT2_SAI5_RX_DATA0 + Select mux mode: ALT2 mux port: RX_DATA0 of instance: SAI5 + 0x2 + + + ALT5_GPIO4_IO30 + Select mux mode: ALT5 mux port: IO30 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI3_RXD is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI3_RXD + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI3_TXFS + SW_MUX_CTL_PAD_SAI3_TXFS SW MUX Control Register + 0x1D8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI3_TX_SYNC + Select mux mode: ALT0 mux port: TX_SYNC of instance: SAI3 + 0 + + + ALT1_GPT1_CLK + Select mux mode: ALT1 mux port: CLK of instance: GPT1 + 0x1 + + + ALT2_SAI5_RX_DATA1 + Select mux mode: ALT2 mux port: RX_DATA1 of instance: SAI5 + 0x2 + + + ALT5_GPIO4_IO31 + Select mux mode: ALT5 mux port: IO31 of instance: GPIO4 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI3_TXFS is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI3_TXFS + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI3_TXC + SW_MUX_CTL_PAD_SAI3_TXC SW MUX Control Register + 0x1DC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI3_TX_BCLK + Select mux mode: ALT0 mux port: TX_BCLK of instance: SAI3 + 0 + + + ALT1_GPT1_COMPARE2 + Select mux mode: ALT1 mux port: COMPARE2 of instance: GPT1 + 0x1 + + + ALT2_SAI5_RX_DATA2 + Select mux mode: ALT2 mux port: RX_DATA2 of instance: SAI5 + 0x2 + + + ALT5_GPIO5_IO00 + Select mux mode: ALT5 mux port: IO00 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI3_TXC is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI3_TXC + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI3_TXD + SW_MUX_CTL_PAD_SAI3_TXD SW MUX Control Register + 0x1E0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI3_TX_DATA0 + Select mux mode: ALT0 mux port: TX_DATA0 of instance: SAI3 + 0 + + + ALT1_GPT1_COMPARE3 + Select mux mode: ALT1 mux port: COMPARE3 of instance: GPT1 + 0x1 + + + ALT2_SAI5_RX_DATA3 + Select mux mode: ALT2 mux port: RX_DATA3 of instance: SAI5 + 0x2 + + + ALT5_GPIO5_IO01 + Select mux mode: ALT5 mux port: IO01 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI3_TXD is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI3_TXD + 0x1 + + + + + + + SW_MUX_CTL_PAD_SAI3_MCLK + SW_MUX_CTL_PAD_SAI3_MCLK SW MUX Control Register + 0x1E4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SAI3_MCLK + Select mux mode: ALT0 mux port: MCLK of instance: SAI3 + 0 + + + ALT1_PWM4_OUT + Select mux mode: ALT1 mux port: OUT of instance: PWM4 + 0x1 + + + ALT2_SAI5_MCLK + Select mux mode: ALT2 mux port: MCLK of instance: SAI5 + 0x2 + + + ALT5_GPIO5_IO02 + Select mux mode: ALT5 mux port: IO02 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SAI3_MCLK is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SAI3_MCLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_SPDIF_TX + SW_MUX_CTL_PAD_SPDIF_TX SW MUX Control Register + 0x1E8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SPDIF1_OUT + Select mux mode: ALT0 mux port: OUT of instance: SPDIF1 + 0 + + + ALT1_PWM3_OUT + Select mux mode: ALT1 mux port: OUT of instance: PWM3 + 0x1 + + + ALT5_GPIO5_IO03 + Select mux mode: ALT5 mux port: IO03 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SPDIF_TX is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SPDIF_TX + 0x1 + + + + + + + SW_MUX_CTL_PAD_SPDIF_RX + SW_MUX_CTL_PAD_SPDIF_RX SW MUX Control Register + 0x1EC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SPDIF1_IN + Select mux mode: ALT0 mux port: IN of instance: SPDIF1 + 0 + + + ALT1_PWM2_OUT + Select mux mode: ALT1 mux port: OUT of instance: PWM2 + 0x1 + + + ALT5_GPIO5_IO04 + Select mux mode: ALT5 mux port: IO04 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SPDIF_RX is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SPDIF_RX + 0x1 + + + + + + + SW_MUX_CTL_PAD_SPDIF_EXT_CLK + SW_MUX_CTL_PAD_SPDIF_EXT_CLK SW MUX Control Register + 0x1F0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_SPDIF1_EXT_CLK + Select mux mode: ALT0 mux port: EXT_CLK of instance: SPDIF1 + 0 + + + ALT1_PWM1_OUT + Select mux mode: ALT1 mux port: OUT of instance: PWM1 + 0x1 + + + ALT5_GPIO5_IO05 + Select mux mode: ALT5 mux port: IO05 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad SPDIF_EXT_CLK is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad SPDIF_EXT_CLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_ECSPI1_SCLK + SW_MUX_CTL_PAD_ECSPI1_SCLK SW MUX Control Register + 0x1F4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ECSPI1_SCLK + Select mux mode: ALT0 mux port: SCLK of instance: ECSPI1 + 0 + + + ALT1_UART3_RX + Select mux mode: ALT1 mux port: RX of instance: UART3 + 0x1 + + + ALT5_GPIO5_IO06 + Select mux mode: ALT5 mux port: IO06 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ECSPI1_SCLK is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ECSPI1_SCLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_ECSPI1_MOSI + SW_MUX_CTL_PAD_ECSPI1_MOSI SW MUX Control Register + 0x1F8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ECSPI1_MOSI + Select mux mode: ALT0 mux port: MOSI of instance: ECSPI1 + 0 + + + ALT1_UART3_TX + Select mux mode: ALT1 mux port: TX of instance: UART3 + 0x1 + + + ALT5_GPIO5_IO07 + Select mux mode: ALT5 mux port: IO07 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ECSPI1_MOSI is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ECSPI1_MOSI + 0x1 + + + + + + + SW_MUX_CTL_PAD_ECSPI1_MISO + SW_MUX_CTL_PAD_ECSPI1_MISO SW MUX Control Register + 0x1FC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ECSPI1_MISO + Select mux mode: ALT0 mux port: MISO of instance: ECSPI1 + 0 + + + ALT1_UART3_CTS_B + Select mux mode: ALT1 mux port: CTS_B of instance: UART3 + 0x1 + + + ALT5_GPIO5_IO08 + Select mux mode: ALT5 mux port: IO08 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ECSPI1_MISO is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ECSPI1_MISO + 0x1 + + + + + + + SW_MUX_CTL_PAD_ECSPI1_SS0 + SW_MUX_CTL_PAD_ECSPI1_SS0 SW MUX Control Register + 0x200 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ECSPI1_SS0 + Select mux mode: ALT0 mux port: SS0 of instance: ECSPI1 + 0 + + + ALT1_UART3_RTS_B + Select mux mode: ALT1 mux port: RTS_B of instance: UART3 + 0x1 + + + ALT5_GPIO5_IO09 + Select mux mode: ALT5 mux port: IO09 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ECSPI1_SS0 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ECSPI1_SS0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ECSPI2_SCLK + SW_MUX_CTL_PAD_ECSPI2_SCLK SW MUX Control Register + 0x204 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ECSPI2_SCLK + Select mux mode: ALT0 mux port: SCLK of instance: ECSPI2 + 0 + + + ALT1_UART4_RX + Select mux mode: ALT1 mux port: RX of instance: UART4 + 0x1 + + + ALT5_GPIO5_IO10 + Select mux mode: ALT5 mux port: IO10 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ECSPI2_SCLK is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ECSPI2_SCLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_ECSPI2_MOSI + SW_MUX_CTL_PAD_ECSPI2_MOSI SW MUX Control Register + 0x208 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ECSPI2_MOSI + Select mux mode: ALT0 mux port: MOSI of instance: ECSPI2 + 0 + + + ALT1_UART4_TX + Select mux mode: ALT1 mux port: TX of instance: UART4 + 0x1 + + + ALT5_GPIO5_IO11 + Select mux mode: ALT5 mux port: IO11 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ECSPI2_MOSI is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ECSPI2_MOSI + 0x1 + + + + + + + SW_MUX_CTL_PAD_ECSPI2_MISO + SW_MUX_CTL_PAD_ECSPI2_MISO SW MUX Control Register + 0x20C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ECSPI2_MISO + Select mux mode: ALT0 mux port: MISO of instance: ECSPI2 + 0 + + + ALT1_UART4_CTS_B + Select mux mode: ALT1 mux port: CTS_B of instance: UART4 + 0x1 + + + ALT5_GPIO5_IO12 + Select mux mode: ALT5 mux port: IO12 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ECSPI2_MISO is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ECSPI2_MISO + 0x1 + + + + + + + SW_MUX_CTL_PAD_ECSPI2_SS0 + SW_MUX_CTL_PAD_ECSPI2_SS0 SW MUX Control Register + 0x210 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_ECSPI2_SS0 + Select mux mode: ALT0 mux port: SS0 of instance: ECSPI2 + 0 + + + ALT1_UART4_RTS_B + Select mux mode: ALT1 mux port: RTS_B of instance: UART4 + 0x1 + + + ALT5_GPIO5_IO13 + Select mux mode: ALT5 mux port: IO13 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad ECSPI2_SS0 is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad ECSPI2_SS0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_I2C1_SCL + SW_MUX_CTL_PAD_I2C1_SCL SW MUX Control Register + 0x214 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_I2C1_SCL + Select mux mode: ALT0 mux port: SCL of instance: I2C1 + 0 + + + ALT1_ENET1_MDC + Select mux mode: ALT1 mux port: MDC of instance: ENET1 + 0x1 + + + ALT5_GPIO5_IO14 + Select mux mode: ALT5 mux port: IO14 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad I2C1_SCL is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad I2C1_SCL + 0x1 + + + + + + + SW_MUX_CTL_PAD_I2C1_SDA + SW_MUX_CTL_PAD_I2C1_SDA SW MUX Control Register + 0x218 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_I2C1_SDA + Select mux mode: ALT0 mux port: SDA of instance: I2C1 + 0 + + + ALT1_ENET1_MDIO + Select mux mode: ALT1 mux port: MDIO of instance: ENET1 + 0x1 + + + ALT5_GPIO5_IO15 + Select mux mode: ALT5 mux port: IO15 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad I2C1_SDA is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad I2C1_SDA + 0x1 + + + + + + + SW_MUX_CTL_PAD_I2C2_SCL + SW_MUX_CTL_PAD_I2C2_SCL SW MUX Control Register + 0x21C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_I2C2_SCL + Select mux mode: ALT0 mux port: SCL of instance: I2C2 + 0 + + + ALT1_ENET1_1588_EVENT1_IN + Select mux mode: ALT1 mux port: 1588_EVENT1_IN of instance: ENET1 + 0x1 + + + ALT5_GPIO5_IO16 + Select mux mode: ALT5 mux port: IO16 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad I2C2_SCL is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad I2C2_SCL + 0x1 + + + + + + + SW_MUX_CTL_PAD_I2C2_SDA + SW_MUX_CTL_PAD_I2C2_SDA SW MUX Control Register + 0x220 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_I2C2_SDA + Select mux mode: ALT0 mux port: SDA of instance: I2C2 + 0 + + + ALT1_ENET1_1588_EVENT1_OUT + Select mux mode: ALT1 mux port: 1588_EVENT1_OUT of instance: ENET1 + 0x1 + + + ALT5_GPIO5_IO17 + Select mux mode: ALT5 mux port: IO17 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad I2C2_SDA is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad I2C2_SDA + 0x1 + + + + + + + SW_MUX_CTL_PAD_I2C3_SCL + SW_MUX_CTL_PAD_I2C3_SCL SW MUX Control Register + 0x224 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_I2C3_SCL + Select mux mode: ALT0 mux port: SCL of instance: I2C3 + 0 + + + ALT1_PWM4_OUT + Select mux mode: ALT1 mux port: OUT of instance: PWM4 + 0x1 + + + ALT2_GPT2_CLK + Select mux mode: ALT2 mux port: CLK of instance: GPT2 + 0x2 + + + ALT5_GPIO5_IO18 + Select mux mode: ALT5 mux port: IO18 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad I2C3_SCL is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad I2C3_SCL + 0x1 + + + + + + + SW_MUX_CTL_PAD_I2C3_SDA + SW_MUX_CTL_PAD_I2C3_SDA SW MUX Control Register + 0x228 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_I2C3_SDA + Select mux mode: ALT0 mux port: SDA of instance: I2C3 + 0 + + + ALT1_PWM3_OUT + Select mux mode: ALT1 mux port: OUT of instance: PWM3 + 0x1 + + + ALT2_GPT3_CLK + Select mux mode: ALT2 mux port: CLK of instance: GPT3 + 0x2 + + + ALT5_GPIO5_IO19 + Select mux mode: ALT5 mux port: IO19 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad I2C3_SDA is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad I2C3_SDA + 0x1 + + + + + + + SW_MUX_CTL_PAD_I2C4_SCL + SW_MUX_CTL_PAD_I2C4_SCL SW MUX Control Register + 0x22C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_I2C4_SCL + Select mux mode: ALT0 mux port: SCL of instance: I2C4 + 0 + + + ALT1_PWM2_OUT + Select mux mode: ALT1 mux port: OUT of instance: PWM2 + 0x1 + + + ALT2_PCIE1_CLKREQ_B + Select mux mode: ALT2 mux port: CLKREQ_B of instance: PCIE1 + 0x2 + + + ALT5_GPIO5_IO20 + Select mux mode: ALT5 mux port: IO20 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad I2C4_SCL is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad I2C4_SCL + 0x1 + + + + + + + SW_MUX_CTL_PAD_I2C4_SDA + SW_MUX_CTL_PAD_I2C4_SDA SW MUX Control Register + 0x230 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_I2C4_SDA + Select mux mode: ALT0 mux port: SDA of instance: I2C4 + 0 + + + ALT1_PWM1_OUT + Select mux mode: ALT1 mux port: OUT of instance: PWM1 + 0x1 + + + ALT2_PCIE2_CLKREQ_B + Select mux mode: ALT2 mux port: CLKREQ_B of instance: PCIE2 + 0x2 + + + ALT5_GPIO5_IO21 + Select mux mode: ALT5 mux port: IO21 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad I2C4_SDA is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad I2C4_SDA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART1_RXD + SW_MUX_CTL_PAD_UART1_RXD SW MUX Control Register + 0x234 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_UART1_RX + Select mux mode: ALT0 mux port: RX of instance: UART1 + 0 + + + ALT1_ECSPI3_SCLK + Select mux mode: ALT1 mux port: SCLK of instance: ECSPI3 + 0x1 + + + ALT5_GPIO5_IO22 + Select mux mode: ALT5 mux port: IO22 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad UART1_RXD is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad UART1_RXD + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART1_TXD + SW_MUX_CTL_PAD_UART1_TXD SW MUX Control Register + 0x238 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_UART1_TX + Select mux mode: ALT0 mux port: TX of instance: UART1 + 0 + + + ALT1_ECSPI3_MOSI + Select mux mode: ALT1 mux port: MOSI of instance: ECSPI3 + 0x1 + + + ALT5_GPIO5_IO23 + Select mux mode: ALT5 mux port: IO23 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad UART1_TXD is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad UART1_TXD + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART2_RXD + SW_MUX_CTL_PAD_UART2_RXD SW MUX Control Register + 0x23C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_UART2_RX + Select mux mode: ALT0 mux port: RX of instance: UART2 + 0 + + + ALT1_ECSPI3_MISO + Select mux mode: ALT1 mux port: MISO of instance: ECSPI3 + 0x1 + + + ALT5_GPIO5_IO24 + Select mux mode: ALT5 mux port: IO24 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad UART2_RXD is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad UART2_RXD + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART2_TXD + SW_MUX_CTL_PAD_UART2_TXD SW MUX Control Register + 0x240 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_UART2_TX + Select mux mode: ALT0 mux port: TX of instance: UART2 + 0 + + + ALT1_ECSPI3_SS0 + Select mux mode: ALT1 mux port: SS0 of instance: ECSPI3 + 0x1 + + + ALT5_GPIO5_IO25 + Select mux mode: ALT5 mux port: IO25 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad UART2_TXD is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad UART2_TXD + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART3_RXD + SW_MUX_CTL_PAD_UART3_RXD SW MUX Control Register + 0x244 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_UART3_RX + Select mux mode: ALT0 mux port: RX of instance: UART3 + 0 + + + ALT1_UART1_CTS_B + Select mux mode: ALT1 mux port: CTS_B of instance: UART1 + 0x1 + + + ALT5_GPIO5_IO26 + Select mux mode: ALT5 mux port: IO26 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad UART3_RXD is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad UART3_RXD + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART3_TXD + SW_MUX_CTL_PAD_UART3_TXD SW MUX Control Register + 0x248 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_UART3_TX + Select mux mode: ALT0 mux port: TX of instance: UART3 + 0 + + + ALT1_UART1_RTS_B + Select mux mode: ALT1 mux port: RTS_B of instance: UART1 + 0x1 + + + ALT5_GPIO5_IO27 + Select mux mode: ALT5 mux port: IO27 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad UART3_TXD is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad UART3_TXD + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART4_RXD + SW_MUX_CTL_PAD_UART4_RXD SW MUX Control Register + 0x24C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_UART4_RX + Select mux mode: ALT0 mux port: RX of instance: UART4 + 0 + + + ALT1_UART2_CTS_B + Select mux mode: ALT1 mux port: CTS_B of instance: UART2 + 0x1 + + + ALT2_PCIE1_CLKREQ_B + Select mux mode: ALT2 mux port: CLKREQ_B of instance: PCIE1 + 0x2 + + + ALT5_GPIO5_IO28 + Select mux mode: ALT5 mux port: IO28 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad UART4_RXD is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad UART4_RXD + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART4_TXD + SW_MUX_CTL_PAD_UART4_TXD SW MUX Control Register + 0x250 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 3 + read-write + + + ALT0_UART4_TX + Select mux mode: ALT0 mux port: TX of instance: UART4 + 0 + + + ALT1_UART2_RTS_B + Select mux mode: ALT1 mux port: RTS_B of instance: UART2 + 0x1 + + + ALT2_PCIE2_CLKREQ_B + Select mux mode: ALT2 mux port: CLKREQ_B of instance: PCIE2 + 0x2 + + + ALT5_GPIO5_IO29 + Select mux mode: ALT5 mux port: IO29 of instance: GPIO5 + 0x5 + + + + + SION + Software Input On Field + 4 + 1 + read-write + + + SION_DISABLED + Input Path of pad UART4_TXD is determined by functionality + 0 + + + SION_ENABLED + Force Input Path of pad UART4_TXD + 0x1 + + + + + + + SW_PAD_CTL_PAD_TEST_MODE + SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register + 0x254 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_BOOT_MODE0 + SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control Register + 0x258 + 32 + read-write + 0x81 + 0xFFFFFFFF + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_BOOT_MODE1 + SW_PAD_CTL_PAD_BOOT_MODE1 SW PAD Control Register + 0x25C + 32 + read-write + 0x81 + 0xFFFFFFFF + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_MOD + SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register + 0x260 + 32 + read-write + 0x1801 + 0xFFFFFFFF + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_JTAG_TRST_B + SW_PAD_CTL_PAD_JTAG_TRST_B SW PAD Control Register + 0x264 + 32 + read-write + 0x41 + 0xFFFFFFFF + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TDI + SW_PAD_CTL_PAD_JTAG_TDI SW PAD Control Register + 0x268 + 32 + read-write + 0x41 + 0xFFFFFFFF + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TMS + SW_PAD_CTL_PAD_JTAG_TMS SW PAD Control Register + 0x26C + 32 + read-write + 0x41 + 0xFFFFFFFF + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TCK + SW_PAD_CTL_PAD_JTAG_TCK SW PAD Control Register + 0x270 + 32 + read-write + 0x41 + 0xFFFFFFFF + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TDO + SW_PAD_CTL_PAD_JTAG_TDO SW PAD Control Register + 0x274 + 32 + read-write + 0x41 + 0xFFFFFFFF + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_RTC + SW_PAD_CTL_PAD_RTC SW PAD Control Register + 0x278 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_PMIC_STBY_REQ + SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register + 0x27C + 32 + read-write + 0xC + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_PMIC_ON_REQ + SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register + 0x280 + 32 + read-write + 0x186C + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_ONOFF + SW_PAD_CTL_PAD_ONOFF SW PAD Control Register + 0x284 + 32 + read-write + 0xCC + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_POR_B + SW_PAD_CTL_PAD_POR_B SW PAD Control Register + 0x288 + 32 + read-write + 0xCC + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_RTC_RESET_B + SW_PAD_CTL_PAD_RTC_RESET_B SW PAD Control Register + 0x28C + 32 + read-write + 0xCC + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO00 + SW_PAD_CTL_PAD_GPIO1_IO00 SW PAD Control Register + 0x290 + 32 + read-write + 0x14 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO01 + SW_PAD_CTL_PAD_GPIO1_IO01 SW PAD Control Register + 0x294 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO02 + SW_PAD_CTL_PAD_GPIO1_IO02 SW PAD Control Register + 0x298 + 32 + read-write + 0x56 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO03 + SW_PAD_CTL_PAD_GPIO1_IO03 SW PAD Control Register + 0x29C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO04 + SW_PAD_CTL_PAD_GPIO1_IO04 SW PAD Control Register + 0x2A0 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO05 + SW_PAD_CTL_PAD_GPIO1_IO05 SW PAD Control Register + 0x2A4 + 32 + read-write + 0x56 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO06 + SW_PAD_CTL_PAD_GPIO1_IO06 SW PAD Control Register + 0x2A8 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO07 + SW_PAD_CTL_PAD_GPIO1_IO07 SW PAD Control Register + 0x2AC + 32 + read-write + 0x1816 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO08 + SW_PAD_CTL_PAD_GPIO1_IO08 SW PAD Control Register + 0x2B0 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO09 + SW_PAD_CTL_PAD_GPIO1_IO09 SW PAD Control Register + 0x2B4 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO10 + SW_PAD_CTL_PAD_GPIO1_IO10 SW PAD Control Register + 0x2B8 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO11 + SW_PAD_CTL_PAD_GPIO1_IO11 SW PAD Control Register + 0x2BC + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO12 + SW_PAD_CTL_PAD_GPIO1_IO12 SW PAD Control Register + 0x2C0 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO13 + SW_PAD_CTL_PAD_GPIO1_IO13 SW PAD Control Register + 0x2C4 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO14 + SW_PAD_CTL_PAD_GPIO1_IO14 SW PAD Control Register + 0x2C8 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO15 + SW_PAD_CTL_PAD_GPIO1_IO15 SW PAD Control Register + 0x2CC + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET_MDC + SW_PAD_CTL_PAD_ENET_MDC SW PAD Control Register + 0x2D0 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET_MDIO + SW_PAD_CTL_PAD_ENET_MDIO SW PAD Control Register + 0x2D4 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET_TD3 + SW_PAD_CTL_PAD_ENET_TD3 SW PAD Control Register + 0x2D8 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + 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55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET_TD1 + SW_PAD_CTL_PAD_ENET_TD1 SW PAD Control Register + 0x2E0 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + 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0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET_TX_CTL + SW_PAD_CTL_PAD_ENET_TX_CTL SW PAD Control Register + 0x2E8 + 32 + read-write + 0x1816 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_ENET_TXC + SW_PAD_CTL_PAD_ENET_TXC SW PAD Control Register + 0x2EC + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET_RX_CTL + SW_PAD_CTL_PAD_ENET_RX_CTL SW PAD Control Register + 0x2F0 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET_RXC + SW_PAD_CTL_PAD_ENET_RXC SW PAD Control Register + 0x2F4 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET_RD0 + SW_PAD_CTL_PAD_ENET_RD0 SW PAD Control Register + 0x2F8 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET_RD1 + SW_PAD_CTL_PAD_ENET_RD1 SW PAD Control Register + 0x2FC + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET_RD2 + SW_PAD_CTL_PAD_ENET_RD2 SW PAD Control Register + 0x300 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET_RD3 + SW_PAD_CTL_PAD_ENET_RD3 SW PAD Control Register + 0x304 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_CLK + SW_PAD_CTL_PAD_SD1_CLK SW PAD Control Register + 0x308 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_CMD + SW_PAD_CTL_PAD_SD1_CMD SW PAD Control Register + 0x30C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA0 + SW_PAD_CTL_PAD_SD1_DATA0 SW PAD Control Register + 0x310 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA1 + SW_PAD_CTL_PAD_SD1_DATA1 SW PAD Control Register + 0x314 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA2 + SW_PAD_CTL_PAD_SD1_DATA2 SW PAD Control Register + 0x318 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA3 + SW_PAD_CTL_PAD_SD1_DATA3 SW PAD Control Register + 0x31C + 32 + read-write + 0x1816 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA4 + SW_PAD_CTL_PAD_SD1_DATA4 SW PAD Control Register + 0x320 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA5 + SW_PAD_CTL_PAD_SD1_DATA5 SW PAD Control Register + 0x324 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA6 + SW_PAD_CTL_PAD_SD1_DATA6 SW PAD Control Register + 0x328 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA7 + SW_PAD_CTL_PAD_SD1_DATA7 SW PAD Control Register + 0x32C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_RESET_B + SW_PAD_CTL_PAD_SD1_RESET_B SW PAD Control Register + 0x330 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_STROBE + SW_PAD_CTL_PAD_SD1_STROBE SW PAD Control Register + 0x334 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD2_CD_B + SW_PAD_CTL_PAD_SD2_CD_B SW PAD Control Register + 0x338 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD2_CLK + SW_PAD_CTL_PAD_SD2_CLK SW PAD Control Register + 0x33C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD2_CMD + SW_PAD_CTL_PAD_SD2_CMD SW PAD Control Register + 0x340 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD2_DATA0 + SW_PAD_CTL_PAD_SD2_DATA0 SW PAD Control Register + 0x344 + 32 + read-write + 0x1816 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_SD2_DATA1 + SW_PAD_CTL_PAD_SD2_DATA1 SW PAD Control Register + 0x348 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD2_DATA2 + SW_PAD_CTL_PAD_SD2_DATA2 SW PAD Control Register + 0x34C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD2_DATA3 + SW_PAD_CTL_PAD_SD2_DATA3 SW PAD Control Register + 0x350 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD2_RESET_B + SW_PAD_CTL_PAD_SD2_RESET_B SW PAD Control Register + 0x354 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD2_WP + SW_PAD_CTL_PAD_SD2_WP SW PAD Control Register + 0x358 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_ALE + SW_PAD_CTL_PAD_NAND_ALE SW PAD Control Register + 0x35C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_CE0_B + SW_PAD_CTL_PAD_NAND_CE0_B SW PAD Control Register + 0x360 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_CE1_B + SW_PAD_CTL_PAD_NAND_CE1_B SW PAD Control Register + 0x364 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_CE2_B + SW_PAD_CTL_PAD_NAND_CE2_B SW PAD Control Register + 0x368 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_CE3_B + SW_PAD_CTL_PAD_NAND_CE3_B SW PAD Control Register + 0x36C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_CLE + SW_PAD_CTL_PAD_NAND_CLE SW PAD Control Register + 0x370 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA00 + SW_PAD_CTL_PAD_NAND_DATA00 SW PAD Control Register + 0x374 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA01 + SW_PAD_CTL_PAD_NAND_DATA01 SW PAD Control Register + 0x378 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA02 + SW_PAD_CTL_PAD_NAND_DATA02 SW PAD Control Register + 0x37C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA03 + SW_PAD_CTL_PAD_NAND_DATA03 SW PAD Control Register + 0x380 + 32 + read-write + 0x1816 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA04 + SW_PAD_CTL_PAD_NAND_DATA04 SW PAD Control Register + 0x384 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA05 + SW_PAD_CTL_PAD_NAND_DATA05 SW PAD Control Register + 0x388 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA06 + SW_PAD_CTL_PAD_NAND_DATA06 SW PAD Control Register + 0x38C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA07 + SW_PAD_CTL_PAD_NAND_DATA07 SW PAD Control Register + 0x390 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DQS + SW_PAD_CTL_PAD_NAND_DQS SW PAD Control Register + 0x394 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_RE_B + SW_PAD_CTL_PAD_NAND_RE_B SW PAD Control Register + 0x398 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_READY_B + SW_PAD_CTL_PAD_NAND_READY_B SW PAD Control Register + 0x39C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_WE_B + SW_PAD_CTL_PAD_NAND_WE_B SW PAD Control Register + 0x3A0 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_WP_B + SW_PAD_CTL_PAD_NAND_WP_B SW PAD Control Register + 0x3A4 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI5_RXFS + SW_PAD_CTL_PAD_SAI5_RXFS SW PAD Control Register + 0x3A8 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt 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DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI5_RXD1 + SW_PAD_CTL_PAD_SAI5_RXD1 SW PAD Control Register + 0x3B4 + 32 + read-write + 0x1816 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_SAI5_RXD2 + SW_PAD_CTL_PAD_SAI5_RXD2 SW PAD Control Register + 0x3B8 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI5_RXD3 + SW_PAD_CTL_PAD_SAI5_RXD3 SW PAD Control Register + 0x3BC + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI5_MCLK + SW_PAD_CTL_PAD_SAI5_MCLK SW PAD Control Register + 0x3C0 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + 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@1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_RXC + SW_PAD_CTL_PAD_SAI1_RXC SW PAD Control Register + 0x3C8 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_RXD0 + SW_PAD_CTL_PAD_SAI1_RXD0 SW PAD Control Register + 0x3CC + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_RXD1 + SW_PAD_CTL_PAD_SAI1_RXD1 SW PAD Control Register + 0x3D0 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_RXD2 + SW_PAD_CTL_PAD_SAI1_RXD2 SW PAD Control Register + 0x3D4 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_RXD3 + SW_PAD_CTL_PAD_SAI1_RXD3 SW PAD Control Register + 0x3D8 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_RXD4 + SW_PAD_CTL_PAD_SAI1_RXD4 SW PAD Control Register + 0x3DC + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_RXD5 + SW_PAD_CTL_PAD_SAI1_RXD5 SW PAD Control Register + 0x3E0 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_RXD6 + SW_PAD_CTL_PAD_SAI1_RXD6 SW PAD Control Register + 0x3E4 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_RXD7 + SW_PAD_CTL_PAD_SAI1_RXD7 SW PAD Control Register + 0x3E8 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_TXFS + SW_PAD_CTL_PAD_SAI1_TXFS SW PAD Control Register + 0x3EC + 32 + read-write + 0x1816 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_SAI1_TXC + SW_PAD_CTL_PAD_SAI1_TXC SW PAD Control Register + 0x3F0 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_TXD0 + SW_PAD_CTL_PAD_SAI1_TXD0 SW PAD Control Register + 0x3F4 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_TXD1 + SW_PAD_CTL_PAD_SAI1_TXD1 SW PAD Control Register + 0x3F8 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open 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65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_TXD3 + SW_PAD_CTL_PAD_SAI1_TXD3 SW PAD Control Register + 0x400 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_TXD4 + SW_PAD_CTL_PAD_SAI1_TXD4 SW PAD Control Register + 0x404 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_TXD5 + SW_PAD_CTL_PAD_SAI1_TXD5 SW PAD Control Register + 0x408 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_TXD6 + SW_PAD_CTL_PAD_SAI1_TXD6 SW PAD Control Register + 0x40C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_TXD7 + SW_PAD_CTL_PAD_SAI1_TXD7 SW PAD Control Register + 0x410 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI1_MCLK + SW_PAD_CTL_PAD_SAI1_MCLK SW PAD Control Register + 0x414 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI2_RXFS + SW_PAD_CTL_PAD_SAI2_RXFS SW PAD Control Register + 0x418 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI2_RXC + SW_PAD_CTL_PAD_SAI2_RXC SW PAD Control Register + 0x41C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI2_RXD0 + SW_PAD_CTL_PAD_SAI2_RXD0 SW PAD Control Register + 0x420 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI2_TXFS + SW_PAD_CTL_PAD_SAI2_TXFS SW PAD Control Register + 0x424 + 32 + read-write + 0x1816 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_SAI2_TXC + SW_PAD_CTL_PAD_SAI2_TXC SW PAD Control Register + 0x428 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI2_TXD0 + SW_PAD_CTL_PAD_SAI2_TXD0 SW PAD Control Register + 0x42C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI2_MCLK + SW_PAD_CTL_PAD_SAI2_MCLK SW PAD Control Register + 0x430 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI3_RXFS + SW_PAD_CTL_PAD_SAI3_RXFS SW PAD Control Register + 0x434 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI3_RXC + SW_PAD_CTL_PAD_SAI3_RXC SW PAD Control Register + 0x438 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI3_RXD + SW_PAD_CTL_PAD_SAI3_RXD SW PAD Control Register + 0x43C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI3_TXFS + SW_PAD_CTL_PAD_SAI3_TXFS SW PAD Control Register + 0x440 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI3_TXC + SW_PAD_CTL_PAD_SAI3_TXC SW PAD Control Register + 0x444 + 32 + read-write + 0x1816 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_SAI3_TXD + SW_PAD_CTL_PAD_SAI3_TXD SW PAD Control Register + 0x448 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SAI3_MCLK + SW_PAD_CTL_PAD_SAI3_MCLK SW PAD Control Register + 0x44C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SPDIF_TX + SW_PAD_CTL_PAD_SPDIF_TX SW PAD Control Register + 0x450 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SPDIF_RX + SW_PAD_CTL_PAD_SPDIF_RX SW PAD Control Register + 0x454 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SPDIF_EXT_CLK + SW_PAD_CTL_PAD_SPDIF_EXT_CLK SW PAD Control Register + 0x458 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ECSPI1_SCLK + SW_PAD_CTL_PAD_ECSPI1_SCLK SW PAD Control Register + 0x45C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ECSPI1_MOSI + SW_PAD_CTL_PAD_ECSPI1_MOSI SW PAD Control Register + 0x460 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ECSPI1_MISO + SW_PAD_CTL_PAD_ECSPI1_MISO SW PAD Control Register + 0x464 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ECSPI1_SS0 + SW_PAD_CTL_PAD_ECSPI1_SS0 SW PAD Control Register + 0x468 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ECSPI2_SCLK + SW_PAD_CTL_PAD_ECSPI2_SCLK SW PAD Control Register + 0x46C + 32 + read-write + 0x1816 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_ECSPI2_MOSI + SW_PAD_CTL_PAD_ECSPI2_MOSI SW PAD Control Register + 0x470 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ECSPI2_MISO + SW_PAD_CTL_PAD_ECSPI2_MISO SW PAD Control Register + 0x474 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ECSPI2_SS0 + SW_PAD_CTL_PAD_ECSPI2_SS0 SW PAD Control Register + 0x478 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_I2C1_SCL + SW_PAD_CTL_PAD_I2C1_SCL SW PAD Control Register + 0x47C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_I2C1_SDA + SW_PAD_CTL_PAD_I2C1_SDA SW PAD Control Register + 0x480 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_I2C2_SCL + SW_PAD_CTL_PAD_I2C2_SCL SW PAD Control Register + 0x484 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_I2C2_SDA + SW_PAD_CTL_PAD_I2C2_SDA SW PAD Control Register + 0x488 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_I2C3_SCL + SW_PAD_CTL_PAD_I2C3_SCL SW PAD Control Register + 0x48C + 32 + read-write + 0x1816 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_I2C3_SDA + SW_PAD_CTL_PAD_I2C3_SDA SW PAD Control Register + 0x490 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_I2C4_SCL + SW_PAD_CTL_PAD_I2C4_SCL SW PAD Control Register + 0x494 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_I2C4_SDA + SW_PAD_CTL_PAD_I2C4_SDA SW PAD Control Register + 0x498 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART1_RXD + SW_PAD_CTL_PAD_UART1_RXD SW PAD Control Register + 0x49C + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART1_TXD + SW_PAD_CTL_PAD_UART1_TXD SW PAD Control Register + 0x4A0 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART2_RXD + SW_PAD_CTL_PAD_UART2_RXD SW PAD Control Register + 0x4A4 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART2_TXD + SW_PAD_CTL_PAD_UART2_TXD SW PAD Control Register + 0x4A8 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART3_RXD + SW_PAD_CTL_PAD_UART3_RXD SW PAD Control Register + 0x4AC + 32 + read-write + 0x1816 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + VSEL + Voltage Select Field + 11 + 3 + read-write + + + VSEL_0_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0 + + + VSEL_1_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x1 + + + VSEL_2_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x2 + + + VSEL_3_Auto_Detct_Mode + Auto Detect 3.3/2.5/1.2/1.8 V mode + 0x3 + + + VSEL_4_Manual_3p3V_Mode + Manually Set 3.3V mode + 0x4 + + + VSEL_5_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x5 + + + VSEL_6_Manual_2p5V_Mode + Manually Set 2.5V mode + 0x6 + + + VSEL_7_Manual_1p2_1p8V_Mode + Manually Set 1.2V/1.8V mode + 0x7 + + + + + + + SW_PAD_CTL_PAD_UART3_TXD + SW_PAD_CTL_PAD_UART3_TXD SW PAD Control Register + 0x4B0 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART4_RXD + SW_PAD_CTL_PAD_UART4_RXD SW PAD Control Register + 0x4B4 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART4_TXD + SW_PAD_CTL_PAD_UART4_TXD SW PAD Control Register + 0x4B8 + 32 + read-write + 0x16 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + 255_OHM + 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V + 0x1 + + + 105_OHM + 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V + 0x2 + + + 75_OHM + 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V + 0x3 + + + 85_OHM + 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V + 0x4 + + + 65_OHM + 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V + 0x5 + + + 45_OHM + 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V + 0x6 + + + 40_OHM + 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V + 0x7 + + + + + SRE + Slew Rate Field + 3 + 2 + read-write + + + SLOW + Slow Frequency Slew Rate (50Mhz) + 0 + + + MEDIUM + Medium Frequency Slew Rate (100Mhz) + 0x1 + + + FAST + Fast Frequency Slew Rate (150Mhz) + 0x2 + + + MAX + Max Frequency Slew Rate (200Mhz) + 0x3 + + + + + ODE + Open Drain Enable Field + 5 + 1 + read-write + + + Disabled + Open Drain Disabled + 0 + + + Enabled + Open Drain Enabled + 0x1 + + + + + PUE + Pull Up Enable Field + 6 + 1 + read-write + + + Disabled + Pull Up Resistor Disabled + 0 + + + Enabled + Pull Up Resistor Enabled + 0x1 + + + + + HYS + Schmitt trigger Enable Field + 7 + 1 + read-write + + + Disabled + Schmitt Trigger Disabled + 0 + + + Enabled + Schmitt Trigger Enabled + 0x1 + + + + + LVTTL + Lvttl Enable Field + 8 + 1 + read-write + + + Disabled + LVTTL Disabled + 0 + + + Enabled + LVTTL Enabled + 0x1 + + + + + + + CCM_PMIC_READY_SELECT_INPUT + CCM_PMIC_READY_SELECT_INPUT DAISY Register + 0x4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + + + ENET1_MDIO_SELECT_INPUT + ENET1_MDIO_SELECT_INPUT DAISY Register + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + + + SAI1_RX_SYNC_SELECT_INPUT + SAI1_RX_SYNC_SELECT_INPUT DAISY Register + 0x4C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + SAI1_RXFS_ALT0 + Selecting Pad: SAI1_RXFS Mode: ALT0 for SAI1_RX_SYNC + 0 + + + SAI1_RXD5_ALT3 + Selecting Pad: SAI1_RXD5 Mode: ALT3 for SAI1_RX_SYNC + 0x1 + + + + + + + SAI1_TX_BCLK_SELECT_INPUT + SAI1_TX_BCLK_SELECT_INPUT DAISY Register + 0x4C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + SAI5_MCLK_ALT1 + Selecting Pad: SAI5_MCLK Mode: ALT1 for SAI1_TX_BCLK + 0 + + + SAI1_TXC_ALT0 + Selecting Pad: SAI1_TXC Mode: ALT0 for SAI1_TX_BCLK + 0x1 + + + SAI1_MCLK_ALT2 + Selecting Pad: SAI1_MCLK Mode: ALT2 for SAI1_TX_BCLK + 0x2 + + + + + + + SAI1_TX_SYNC_SELECT_INPUT + SAI1_TX_SYNC_SELECT_INPUT DAISY Register + 0x4CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 3 + read-write + + + SAI5_RXD1_ALT2 + Selecting Pad: SAI5_RXD1 Mode: ALT2 for SAI1_TX_SYNC + 0 + + + SAI5_RXD2_ALT2 + Selecting Pad: SAI5_RXD2 Mode: ALT2 for SAI1_TX_SYNC + 0x1 + + + SAI5_RXD3_ALT2 + Selecting Pad: SAI5_RXD3 Mode: ALT2 for SAI1_TX_SYNC + 0x2 + + + SAI1_TXFS_ALT0 + Selecting Pad: SAI1_TXFS Mode: ALT0 for SAI1_TX_SYNC + 0x3 + + + SAI1_RXD7_ALT2 + Selecting Pad: SAI1_RXD7 Mode: ALT2 for SAI1_TX_SYNC + 0x4 + + + + + + + SAI5_RX_BCLK_SELECT_INPUT + SAI5_RX_BCLK_SELECT_INPUT DAISY Register + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + + + SAI5_RXD0_SELECT_INPUT + SAI5_RXD0_SELECT_INPUT DAISY Register + 0x4D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + + + SAI5_RXD1_SELECT_INPUT + SAI5_RXD1_SELECT_INPUT DAISY Register + 0x4D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + + + SAI5_RXD2_SELECT_INPUT + SAI5_RXD2_SELECT_INPUT DAISY Register + 0x4DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + + + SAI5_RXD3_SELECT_INPUT + SAI5_RXD3_SELECT_INPUT DAISY Register + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + + + SAI5_RX_SYNC_SELECT_INPUT + SAI5_RX_SYNC_SELECT_INPUT DAISY Register + 0x4E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + + + SAI5_TX_BCLK_SELECT_INPUT + SAI5_TX_BCLK_SELECT_INPUT DAISY Register + 0x4E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + SAI5_RXD2_ALT3 + Selecting Pad: SAI5_RXD2 Mode: ALT3 for SAI5_TX_BCLK + 0 + + + SAI1_TXC_ALT1 + Selecting Pad: SAI1_TXC Mode: ALT1 for SAI5_TX_BCLK + 0x1 + + + SAI2_RXC_ALT1 + Selecting Pad: SAI2_RXC Mode: ALT1 for SAI5_TX_BCLK + 0x2 + + + + + + + SAI5_TX_SYNC_SELECT_INPUT + SAI5_TX_SYNC_SELECT_INPUT DAISY Register + 0x4EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + SAI5_RXD1_ALT3 + Selecting Pad: SAI5_RXD1 Mode: ALT3 for SAI5_TX_SYNC + 0 + + + SAI1_TXFS_ALT1 + Selecting Pad: SAI1_TXFS Mode: ALT1 for SAI5_TX_SYNC + 0x1 + + + SAI2_RXFS_ALT1 + Selecting Pad: SAI2_RXFS Mode: ALT1 for SAI5_TX_SYNC + 0x2 + + + + + + + UART1_RTS_B_SELECT_INPUT + UART1_RTS_B_SELECT_INPUT DAISY Register + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + UART3_RXD_ALT1 + Selecting Pad: UART3_RXD Mode: ALT1 for UART1_RTS_B + 0 + + + UART3_TXD_ALT1 + Selecting Pad: UART3_TXD Mode: ALT1 for UART1_RTS_B + 0x1 + + + + + + + UART1_RXD_SELECT_INPUT + UART1_RXD_SELECT_INPUT DAISY Register + 0x4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + UART1_RXD_ALT0 + Selecting Pad: UART1_RXD Mode: ALT0 for UART1_RXD + 0 + + + UART1_TXD_ALT0 + Selecting Pad: UART1_TXD Mode: ALT0 for UART1_RXD + 0x1 + + + + + + + UART2_RTS_B_SELECT_INPUT + UART2_RTS_B_SELECT_INPUT DAISY Register + 0x4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + UART4_RXD_ALT1 + Selecting Pad: UART4_RXD Mode: ALT1 for UART2_RTS_B + 0 + + + UART4_TXD_ALT1 + Selecting Pad: UART4_TXD Mode: ALT1 for UART2_RTS_B + 0x1 + + + + + + + UART2_RXD_SELECT_INPUT + UART2_RXD_SELECT_INPUT DAISY Register + 0x4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + UART2_RXD_ALT0 + Selecting Pad: UART2_RXD Mode: ALT0 for UART2_RXD + 0 + + + UART2_TXD_ALT0 + Selecting Pad: UART2_TXD Mode: ALT0 for UART2_RXD + 0x1 + + + + + + + UART3_RTS_B_SELECT_INPUT + UART3_RTS_B_SELECT_INPUT DAISY Register + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + ECSPI1_MISO_ALT1 + Selecting Pad: ECSPI1_MISO Mode: ALT1 for UART3_RTS_B + 0 + + + ECSPI1_SS0_ALT1 + Selecting Pad: ECSPI1_SS0 Mode: ALT1 for UART3_RTS_B + 0x1 + + + + + + + UART3_RXD_SELECT_INPUT + UART3_RXD_SELECT_INPUT DAISY Register + 0x504 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + ECSPI1_SCLK_ALT1 + Selecting Pad: ECSPI1_SCLK Mode: ALT1 for UART3_RXD + 0 + + + ECSPI1_MOSI_ALT1 + Selecting Pad: ECSPI1_MOSI Mode: ALT1 for UART3_RXD + 0x1 + + + UART3_RXD_ALT0 + Selecting Pad: UART3_RXD Mode: ALT0 for UART3_RXD + 0x2 + + + UART3_TXD_ALT0 + Selecting Pad: UART3_TXD Mode: ALT0 for UART3_RXD + 0x3 + + + + + + + UART4_RTS_B_SELECT_INPUT + UART4_RTS_B_SELECT_INPUT DAISY Register + 0x508 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + ECSPI2_MISO_ALT1 + Selecting Pad: ECSPI2_MISO Mode: ALT1 for UART4_RTS_B + 0 + + + ECSPI2_SS0_ALT1 + Selecting Pad: ECSPI2_SS0 Mode: ALT1 for UART4_RTS_B + 0x1 + + + + + + + UART4_RXD_SELECT_INPUT + UART4_RXD_SELECT_INPUT DAISY Register + 0x50C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + ECSPI2_SCLK_ALT1 + Selecting Pad: ECSPI2_SCLK Mode: ALT1 for UART4_RXD + 0 + + + ECSPI2_MOSI_ALT1 + Selecting Pad: ECSPI2_MOSI Mode: ALT1 for UART4_RXD + 0x1 + + + UART4_RXD_ALT0 + Selecting Pad: UART4_RXD Mode: ALT0 for UART4_RXD + 0x2 + + + + + + + SAI6_RX_BCLK_SELECT_INPUT + SAI6_RX_BCLK_SELECT_INPUT DAISY Register + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + + + SAI6_RXD0_SELECT_INPUT + SAI6_RXD0_SELECT_INPUT DAISY Register + 0x514 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + + + SAI6_RX_SYNC_SELECT_INPUT + SAI6_RX_SYNC_SELECT_INPUT DAISY Register + 0x518 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + + + SAI6_TX_BCLK_SELECT_INPUT + SAI6_TX_BCLK_SELECT_INPUT DAISY Register + 0x51C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + SAI1_RXD4_ALT1 + Selecting Pad: SAI1_RXD4 Mode: ALT1 for SAI6_TX_BCLK + 0 + + + SAI1_TXD4_ALT2 + Selecting Pad: SAI1_TXD4 Mode: ALT2 for SAI6_TX_BCLK + 0x1 + + + + + + + SAI6_TX_SYNC_SELECT_INPUT + SAI6_TX_SYNC_SELECT_INPUT DAISY Register + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + SAI1_RXD6_ALT1 + Selecting Pad: SAI1_RXD6 Mode: ALT1 for SAI6_TX_SYNC + 0 + + + SAI1_TXD6_ALT2 + Selecting Pad: SAI1_TXD6 Mode: ALT2 for SAI6_TX_SYNC + 0x1 + + + + + + + PCIE1_CLKREQ_B_SELECT_INPUT + PCIE1_CLKREQ_B_SELECT_INPUT DAISY Register + 0x524 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + I2C4_SCL_ALT2 + Selecting Pad: I2C4_SCL Mode: ALT2 for PCIE1_CLKREQ_B + 0 + + + UART4_RXD_ALT2 + Selecting Pad: UART4_RXD Mode: ALT2 for PCIE1_CLKREQ_B + 0x1 + + + + + + + PCIE2_CLKREQ_B_SELECT_INPUT + PCIE2_CLKREQ_B_SELECT_INPUT DAISY Register + 0x528 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + I2C4_SDA_ALT2 + Selecting Pad: I2C4_SDA Mode: ALT2 for PCIE2_CLKREQ_B + 0 + + + UART4_TXD_ALT2 + Selecting Pad: UART4_TXD Mode: ALT2 for PCIE2_CLKREQ_B + 0x1 + + + + + + + SAI5_MCLK_SELECT_INPUT + SAI5_MCLK_SELECT_INPUT DAISY Register + 0x52C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + SAI5_MCLK_ALT0 + Selecting Pad: SAI5_MCLK Mode: ALT0 for SAI5_MCLK + 0 + + + SAI1_MCLK_ALT1 + Selecting Pad: SAI1_MCLK Mode: ALT1 for SAI5_MCLK + 0x1 + + + SAI2_MCLK_ALT1 + Selecting Pad: SAI2_MCLK Mode: ALT1 for SAI5_MCLK + 0x2 + + + SAI3_MCLK_ALT2 + Selecting Pad: SAI3_MCLK Mode: ALT2 for SAI5_MCLK + 0x3 + + + + + + + SAI6_MCLK_SELECT_INPUT + SAI6_MCLK_SELECT_INPUT DAISY Register + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + SAI1_RXD7_ALT1 + Selecting Pad: SAI1_RXD7 Mode: ALT1 for SAI6_MCLK + 0 + + + SAI1_TXD7_ALT1 + Selecting Pad: SAI1_TXD7 Mode: ALT1 for SAI6_MCLK + 0x1 + + + + + + + + + IOMUXC_GPR + IOMUXC_GPR + IOMUXC_GPR + IOMUXC_GPR_ + 0x30340000 + + 0 + 0xC0 + registers + + + + GPR0 + GPR0 General Purpose Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR1 + GPR1 General Purpose Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ + Interrupt signal which is connected to CPU IRQS[0] + 12 + 1 + read-write + + + ENET1_TX_CLK_SEL + ENET1 reference clock mode select + 13 + 1 + read-write + + + ENET1_TX_CLK_SEL_0 + Gets ENET1 TX reference clk. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. + 0 + + + ENET1_TX_CLK_SEL_1 + Gets ENET1 TX reference clk from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller + 0x1 + + + + + GPR_ANAMIX_IPT_MODE + GPR_ANAMIX_IPT_MODE + 15 + 1 + read-write + + + TZASC1_SECURE_BOOT_LOCK + TZASC-1 Secure Boot Lock + 23 + 1 + read-write + + + TZASC1_SECURE_BOOT_LOCK_0 + Secure boot lock is disabled + 0 + + + TZASC1_SECURE_BOOT_LOCK_1 + Secure boot lock is enabled + 0x1 + + + + + DBG_ACK + Debug Acknowledge + 28 + 4 + read-write + + + + + GPR2 + GPR2 General Purpose Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR_SAI1_EXT_MCLK_EN + SAI1 External MCLK Enable + 0 + 1 + read-write + + + GPR_SAI2_EXT_MCLK_EN + SAI2 External MCLK Enable + 1 + 1 + read-write + + + GPR_SAI3_EXT_MCLK_EN + SAI3 External MCLK Enable + 2 + 1 + read-write + + + GPR_SAI4_EXT_MCLK_EN + SAI4 External MCLK Enable + 3 + 1 + read-write + + + GPR_SAI5_EXT_MCLK_EN + SAI5 External MCLK Enable + 4 + 1 + read-write + + + GPR_SAI6_EXT_MCLK_EN + SAI6 External MCLK Enable + 5 + 1 + read-write + + + + + GPR3 + GPR3 General Purpose Register + 0xC + 32 + read-write + 0xFF + 0xFFFFFFFF + + + RDATA_WAIT_EN + On-chip RAM read data wait state control When the read data wait state is enabled, it will cost 2 cycles for each read access, (each beat of a read burst) + 0 + 1 + read-write + + + RDATA_WAIT_EN_0 + read data wait state disabled + 0 + + + RDATA_WAIT_EN_1 + read data wait state enabled + 0x1 + + + + + RADDR_PIPE_EN + On-chip RAM read address pipeline enable When this feature is enabled, the read address from the AXI master would be delayed 1 cycle before it can be accepted by the on-chip RAM + 1 + 1 + read-write + + + RADDR_PIPE_EN_0 + read address pipeline is disabled + 0 + + + RADDR_PIPE_EN_1 + read address pipeline is enabled + 0x1 + + + + + WDATA_PIPE_EN + On-chip RAM write data pipeline enable When this feature is enabled, the write data from the AXI master would be delayed 1 cycle before it can be accepted by the on-chip RAM + 2 + 1 + read-write + + + WDATA_PIPE_EN_0 + write data pipeline is disabled + 0 + + + WDATA_PIPE_EN_1 + write data pipeline is enabled + 0x1 + + + + + WADDR_PIPE_EN + On-chip RAM write address pipeline enable When this feature is enabled, the write address from the AXI master would be delayed 1 cycle before it can be accepted by the on-chip RAM + 3 + 1 + read-write + + + WADDR_PIPE_EN_0 + write address pipeline is disabled + 0 + + + WADDR_PIPE_EN_1 + write address pipeline is enabled + 0x1 + + + + + S_RDATA_WAIT_EN + State Retention On-chip RAM read data wait state control For description, please refer to RDATA_WAIT_EN bit + 4 + 1 + read-write + + + S_RADDR_PIPE_EN + State Retention On-chip RAM read address pipeline enable For description, please refer to RADDR_PIPE_EN bit + 5 + 1 + read-write + + + S_WDATA_PIPE_EN + State Retention On-chip RAM write data pipeline enable For description, please refer to WDATA_PIPE_EN bit + 6 + 1 + read-write + + + S_WADDR_PIPE_EN + State Retention On-chip RAM write address pipeline enable For description, please refer to WADDR_PIPE_EN bit + 7 + 1 + read-write + + + RDATA_WAIT_EN_PDG + On-chip RAM read data wait state control update is pending + 16 + 1 + read-only + + + RDATA_WAIT_EN_PDG_0 + read data wait state control configuration valid + 0 + + + RDATA_WAIT_EN_PDG_1 + read data wait state control bit changed + 0x1 + + + + + RADDR_PIPE_EN_PDG + On-chip RAM read address pipeline enable update is pending + 17 + 1 + read-only + + + RADDR_PIPE_EN_PDG_0 + read address pipeline enable configuration valid + 0 + + + RADDR_PIPE_EN_PDG_1 + read address pipeline enable bit changed + 0x1 + + + + + WDATA_PIPE_EN_PDG + On-chip RAM write data pipeline enable update is pending + 18 + 1 + read-only + + + WDATA_PIPE_EN_PDG_0 + write data pipeline enable configuration valid + 0 + + + WDATA_PIPE_EN_PDG_1 + write data pipeline enable bit changed + 0x1 + + + + + WADDR_PIPE_EN_PNDG + On-chip RAM write address pipeline enable update is pending + 19 + 1 + read-only + + + WADDR_PIPE_EN_PNDG_0 + write address pipeline enable configuration valid + 0 + + + WADDR_PIPE_EN_PNDG_1 + write address pipeline enable bit changed + 0x1 + + + + + S_RDATA_WAIT_EN_PNDG + State Retention On-chip RAM read data wait state control update is pending + 20 + 1 + read-only + + + S_RDATA_WAIT_EN_PNDG_0 + read data wait state control configuration valid + 0 + + + S_RDATA_WAIT_EN_PNDG_1 + read data wait state control bit changed + 0x1 + + + + + S_RADDR_PIPE_EN_PNDG + State Retention On-chip RAM read address pipeline enable update is pending + 21 + 1 + read-only + + + S_RADDR_PIPE_EN_PNDG_0 + read address pipeline enable configuration valid + 0 + + + S_RADDR_PIPE_EN_PNDG_1 + read address pipeline enable bit changed + 0x1 + + + + + S_WDATA_PIPE_EN_PNDG + State Retention On-chip RAM write data pipeline enable update is pending + 22 + 1 + read-only + + + S_WDATA_PIPE_EN_PNDG_0 + write data pipeline enable configuration valid + 0 + + + S_WDATA_PIPE_EN_PNDG_1 + write data pipeline enable bit changed + 0x1 + + + + + S_WADDR_PIPE_EN_PNDG + State Retention On-chip RAM write address pipeline enable update is pending + 23 + 1 + read-only + + + S_WADDR_PIPE_EN_PNDG_0 + write address pipeline enable configuration valid + 0 + + + S_WADDR_PIPE_EN_PNDG_1 + write address pipeline enable bit changed + 0x1 + + + + + + + GPR4 + GPR4 General Purpose Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDMA1_IPG_STOP + SDMA1 stop request + 0 + 1 + read-write + + + SDMA1_IPG_STOP_0 + stop request off + 0 + + + SDMA1_IPG_STOP_1 + stop request on + 0x1 + + + + + ENET1_IPD_REQ_TIMER_SEL0 + ENET1 IPD_REQ Timer Select 0 + 1 + 1 + read-write + + + ENET1_IPD_REQ_TIMER_SEL0_0 + Select ipd_req_mac0_timer2 to SDMA IRQ 45 + 0 + + + ENET1_IPD_REQ_TIMER_SEL0_1 + Select ipd_req_mac0_timer0 to SDMA IRQ 45 + 0x1 + + + + + ENET1_IPD_REQ_TIMER_SEL1 + ENET1 IPD_REQ Timer Select 1 + 2 + 1 + read-write + + + ENET1_IPD_REQ_TIMER_SEL1_0 + Select ipd_req_mac0_timer3 to SDMA IRQ 47 + 0 + + + ENET1_IPD_REQ_TIMER_SEL1_1 + Select ipd_req_mac0_timer1 to SDMA IRQ 47 + 0x1 + + + + + ENET1_IPG_STOP + ENET1 stop request + 3 + 1 + read-write + + + ENET1_IPG_STOP_0 + stop request off + 0 + + + ENET1_IPG_STOP_1 + stop request on + 0x1 + + + + + SDMA2_IPG_STOP + SDMA2 stop request + 4 + 1 + read-write + + + SDMA2_IPG_STOP_0 + stop request off + 0 + + + SDMA2_IPG_STOP_1 + stop request on + 0x1 + + + + + SDMA1_IPG_STOP_ACK + SDMA1 stop acknowledge + 16 + 1 + read-only + + + SDMA1_IPG_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + SDMA1_IPG_STOP_ACK_1 + stop acknowledge is asserted, peripheral is in STOP mode + 0x1 + + + + + ENET1_IPG_STOP_ACK + ENET1 stop acknowledge + 19 + 1 + read-only + + + ENET1_IPG_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + ENET1_IPG_STOP_ACK_1 + stop acknowledge is asserted, peripheral is in STOP mode + 0x1 + + + + + SDMA2_IPG_STOP_ACK + SDMA2 stop acknowledge + 20 + 1 + read-only + + + SDMA2_IPG_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + SDMA2_IPG_STOP_ACK_1 + stop acknowledge is asserted, peripheral is in STOP mode + 0x1 + + + + + SAI1_IPG_STOP_ACK + SAI1 stop acknowledge + 21 + 1 + read-only + + + SAI1_IPG_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + SAI1_IPG_STOP_ACK_1 + stop acknowledge is asserted, peripheral is in STOP mode + 0x1 + + + + + SAI2_IPG_STOP_ACK + SAI2 stop acknowledge + 22 + 1 + read-only + + + SAI2_IPG_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + SAI2_IPG_STOP_ACK_1 + stop acknowledge is asserted, peripheral is in STOP mode + 0x1 + + + + + SAI3_IPG_STOP_ACK + SAI3 stop acknowledge + 23 + 1 + read-only + + + SAI3_IPG_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + SAI3_IPG_STOP_ACK_1 + stop acknowledge is asserted, peripheral is in STOP mode + 0x1 + + + + + SAI4_IPG_STOP_ACK + SAI4 stop acknowledge + 24 + 1 + read-only + + + SAI4_IPG_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + SAI4_IPG_STOP_ACK_1 + stop acknowledge is asserted, peripheral is in STOP mode + 0x1 + + + + + SAI5_IPG_STOP_ACK + SAI5 stop acknowledge + 25 + 1 + read-only + + + SAI5_IPG_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + SAI5_IPG_STOP_ACK_1 + stop acknowledge is asserted, peripheral is in STOP mode + 0x1 + + + + + SAI6_IPG_STOP_ACK + SAI6 stop acknowledge + 26 + 1 + read-only + + + SAI6_IPG_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + SAI6_IPG_STOP_ACK_1 + stop acknowledge is asserted, peripheral is in STOP mode + 0x1 + + + + + + + GPR5 + GPR5 General Purpose Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + HDMI_HPD_PD + Connect to hdmi_hpd_pd_pad + 0 + 1 + read-write + + + HDMI_DDC_SDA_PD + Connect to hdmi_ddc_sda_pd_pad + 1 + 1 + read-write + + + HDMI_DDC_SCL_PD + Connect to hdmi_ddc_scl_pd_pad + 2 + 1 + read-write + + + HDMI_CEC_PD + Connect to hdmi_cec_pd_pad + 3 + 1 + read-write + + + WDOG1_MASK + WDOG1 Timeout Mask + 6 + 1 + read-write + + + WDOG1_MASK_0 + WDOG1 Timeout behaves normally + 0 + + + WDOG1_MASK_1 + WDOG1 Timeout is masked + 0x1 + + + + + WDOG2_MASK + WDOG2 Timeout Mask + 7 + 1 + read-write + + + WDOG2_MASK_0 + WDOG2 Timeout behaves normally + 0 + + + WDOG2_MASK_1 + WDOG2 Timeout is masked + 0x1 + + + + + WDOG3_MASK + WDOG3 Timeout Mask + 20 + 1 + read-write + + + WDOG3_MASK_0 + WDOG3 Timeout behaves normally + 0 + + + WDOG3_MASK_1 + WDOG3 Timeout is masked + 0x1 + + + + + + + GPR6 + GPR6 General Purpose Register + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR7 + GPR7 General Purpose Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR8 + GPR8 General Purpose Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR9 + GPR9 General Purpose Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR10 + GPR10 General Purpose Register + 0x28 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + TZASC_EN + Connect to tzasc_en input on tzasc_id_wrap + 0 + 1 + read-write + + + TZASC_ID_SWAP_BYPASS + Connect to id_swap_bypass input on tzasc_id_wrap + 1 + 1 + read-write + + + SEC_ERR_RESP_EN + Security error response enable for all security gaskets (on both AHB and AXI busses) This is a "lock" type bit + 2 + 1 + read-write + + + SEC_ERR_RESP_EN_0 + OKAY response + 0 + + + SEC_ERR_RESP_EN_1 + SLVERR response + 0x1 + + + + + EXC_ERR_RESP_EN + Security exclusive access error response enable for all security gaskets (on both AHB and AXI busses) + 3 + 1 + read-write + + + EXC_ERR_RESP_EN_0 + OK response on the AXI for an exclusive access error + 0 + + + EXC_ERR_RESP_EN_1 + ERR response on the AXI for an exclusive access error + 0x1 + + + + + TZASC_EN_LOCK + Lock bit for TZASC_EN + 16 + 1 + read-write + + + TZASC_ID_SWAP_BYPASS_LOCK + Lock bit for TZASC_ID_SWAP_BYPASS + 17 + 1 + read-write + + + SEC_ERR_RESP_EN_LOCK + Lock bit for SEC_ERR_RESP_EN + 18 + 1 + read-write + + + EXC_ERR_RESP_EN_LOCK + Lock bit for EXC_ERR_RESP_EN + 19 + 1 + read-write + + + + + GPR11 + GPR11 General Purpose Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + OCRAM_TZ_EN + OCRAM TrustZone (TZ) enable This is a "lock" type bit + 0 + 1 + read-write + + + OCRAM_TZ_EN_0 + The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + 0 + + + OCRAM_TZ_EN_1 + The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. + 0x1 + + + + + OCRAM_TZ_ADDR + OCRAM TrustZone (TZ) start address + 1 + 5 + read-write + + + OCRAM_S_TZ_EN + State Retention OCRAM TrustZone (TZ) enable This is a "lock" type bit + 10 + 1 + read-write + + + OCRAM_S_TZ_EN_0 + The TrustZone feature is disabled. Entire State Retention OCRAM space is available for all access types (secure/non-secure/user/supervisor). + 0 + + + OCRAM_S_TZ_EN_1 + The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. + 0x1 + + + + + OCRAM_S_TZ_ADDR + State Retention OCRAM TrustZone (TZ) start address + 11 + 3 + read-write + + + OCRAM_TZ_EN_LOCK + Lock Bit + 16 + 1 + read-write + + + OCRAM_TZ_ADDR_LOCK + Lock Bits + 17 + 5 + read-write + + + OCRAM_S_TZ_EN_LOCK + Lock Bit + 26 + 1 + read-write + + + OCRAM_S_TZ_ADDR_LOCK + Lock Bits + 27 + 3 + read-write + + + + + GPR12 + GPR12 General Purpose Register + 0x30 + 32 + read-write + 0x4400 + 0xFFFFFFFF + + + PCIE2_CTRL_DEVICE_TYPE + PCI Express device/port type + 8 + 4 + read-write + + + PCIE2_CTRL_DEVICE_TYPE_0 + PCI Express endpoint + 0 + + + PCIE2_CTRL_DEVICE_TYPE_1 + Legacy PCI Express endpoint + 0x1 + + + PCIE2_CTRL_DEVICE_TYPE_4 + Root port of PCI Express root complex + 0x4 + + + + + PCIE1_CTRL_DEVICE_TYPE + PCI Express device/port type + 12 + 4 + read-write + + + PCIE1_CTRL_DEVICE_TYPE_0 + PCI Express endpoint + 0 + + + PCIE1_CTRL_DEVICE_TYPE_1 + Legacy PCI Express endpoint + 0x1 + + + PCIE1_CTRL_DEVICE_TYPE_4 + Root port of PCI Express root complex + 0x4 + + + + + PCIE1_CTRL_DIAG_STATUS_BUS_SELECT + PCI Express Diagnostic Status Bus Select + 17 + 4 + read-write + + + PCIE1_CTRL_DIAG_CTRL_BUS + PCI Express Diagnostic Control Bus + 21 + 2 + read-write + + + PCIE2_CTRL_DIAG_STATUS_BUS_SELECT + PCI Express Diagnostic Status Bus Select + 25 + 4 + read-write + + + PCIE2_CTRL_DIAG_CTRL_BUS + PCI Express Diagnostic Control Bus + 29 + 2 + read-write + + + PCIE_DIAG_BUS_SEL + Control the source of the PCIE DIAG STATUS bus, PCIe1 or PCIe2. + 31 + 1 + read-write + + + + + GPR13 + GPR13 General Purpose Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARCACHE_USDHC + USDHC 1-3 AXI Master ARCACHE Override Value Note: this bit always overrides + 0 + 1 + read-write + + + ARCACHE_USDHC_0 + Drive USDHC AXI Master ARCACHE[1] to 0 + 0 + + + ARCACHE_USDHC_1 + Drive USDHC AXI Master ARCACHE[1] to 1 + 0x1 + + + + + AWCACHE_USDHC + USDHC 1-3 AXI Master AWCACHE Override Value Note: this bit always overrides + 1 + 1 + read-write + + + AWCACHE_USDHC_0 + Drive USDHC AXI Master AWCACHE[1] to 0 + 0 + + + AWCACHE_USDHC_1 + Drive USDHC AXI Master AWCACHE[1] to 1 + 0x1 + + + + + MIPI_MUX_SEL + MIPI MUX SEL + 2 + 1 + read-write + + + MIPI_MUX_INV + MIPI MUX INV + 3 + 1 + read-write + + + ARCACHE_PCIE1 + PCIe AXI Master Port ARCACHE Override Value Note: this bit only takes effect when ARCACHE_PCIE_EN = 1 + 4 + 1 + read-write + + + ARCACHE_PCIE1_0 + Drive PCIe AXI Master Port ARCACHE[1] to 0 + 0 + + + ARCACHE_PCIE1_1 + Drive PCIe AXI Master Port ARCACHE[1] to 1 + 0x1 + + + + + AWCACHE_PCIE1 + PCIe AXI Master Port AWCACHE Override Value Note: this bit only takes effect when AWCACHE_PCIE_EN = 1 + 5 + 1 + read-write + + + AWCACHE_PCIE1_0 + Drive PCIe AXI Master Port AWCACHE[1] to 0 + 0 + + + AWCACHE_PCIE1_1 + Drive PCIe AXI Master Port AWCACHE[1] to 1 + 0x1 + + + + + ARCACHE_LCDIF + LCDIF AXI Master Port ARCACHE Override Value Note: this bit only takes effect when ARCACHE_LCDIF_EN = 1 + 6 + 1 + read-write + + + ARCACHE_LCDIF_0 + Drive LCDIF AXI Master Port ARCACHE[1] to 0 + 0 + + + ARCACHE_LCDIF_1 + Drive LCDIF AXI Master Port ARCACHE[1] to 1 + 0x1 + + + + + ARCACHE_PCIE2_EN + PCIe AXI Master Port ARCACHE Override Enable + 8 + 1 + read-write + + + ARCACHE_PCIE2_EN_0 + PCIE Primary AXI Master Port ARCACHE[1] driven by PCIE + 0 + + + ARCACHE_PCIE2_EN_1 + PCIE Primary AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_PCIE2 bit + 0x1 + + + + + AWCACHE_PCIE2_EN + PCIe AXI Master Port AWCACHE Override Enable + 9 + 1 + read-write + + + AWCACHE_PCIE2_EN_0 + PCIE Primary AXI Master Port AWCACHE[1] driven by PCIE + 0 + + + AWCACHE_PCIE2_EN_1 + PXP Primary AXI Master Port AWCACHE[1] driven to constant value specified by the AWCACHE_PCIE2 bit + 0x1 + + + + + ARCACHE_PCIE1_EN + PCIe AXI Master Port ARCACHE Override Enable + 10 + 1 + read-write + + + ARCACHE_PCIE1_EN_0 + PCIe AXI Master Port ARCACHE[1] driven by PCIe + 0 + + + ARCACHE_PCIE1_EN_1 + PCIe AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_PXP1 bit + 0x1 + + + + + AWCACHE_PCIE1_EN + PCIe AXI Master Port AWCACHE Override Enable + 11 + 1 + read-write + + + AWCACHE_PCIE1_EN_0 + PCIe AXI Master Port AWCACHE[1] driven by PCIe + 0 + + + AWCACHE_PCIE1_EN_1 + PCIe AXI Master Port AWCACHE[1] driven to constant value specified by the AWCACHE_PCIE1 bit + 0x1 + + + + + ARCACHE_LCDIF_EN + LCDIF AXI Master Port ARCACHE Override Enable + 12 + 1 + read-write + + + ARCACHE_LCDIF_EN_0 + LCDIF AXI Master Port ARCACHE[1] driven by LCDIF + 0 + + + ARCACHE_LCDIF_EN_1 + LCDIF AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_LCDIF bit + 0x1 + + + + + ARCACHE_PCIE2 + PCIe AXI Master Port ARCACHE Override Value Note: this bit only takes effect when ARCACHE_PCIE_EN = 1 + 13 + 1 + read-write + + + ARCACHE_PCIE2_0 + Drive PCIe AXI Master Port ARCACHE[1] to 0 + 0 + + + ARCACHE_PCIE2_1 + Drive PCIe AXI Master Port ARCACHE[1] to 1 + 0x1 + + + + + AWCACHE_PCIE2 + PCIe AXI Master Port AWCACHE Override Value Note: this bit only takes effect when AWCACHE_PCIE_EN = 1 + 14 + 1 + read-write + + + AWCACHE_PCIE2_0 + Drive PCIe AXI Master Port AWCACHE[1] to 0 + 0 + + + AWCACHE_PCIE2_1 + Drive PCIe AXI Master Port AWCACHE[1] to 1 + 0x1 + + + + + + + GPR14 + GPR14 General Purpose Register + 0x38 + 32 + read-write + 0x49409100 + 0xFFFFFFFF + + + PCIE1_APP_CLK_PM_EN + To PCIe PHY + 8 + 1 + read-write + + + PCIE1_REF_USE_PAD + To PCIe PHY + 9 + 1 + read-write + + + PCIE1_CLKREQ_B_OVERRIDE_EN + Control the PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller + 10 + 1 + read-write + + + PCIE1_CLKREQ_B_OVERRIDE + Control the PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller + 11 + 1 + read-write + + + PCIE1_VREG_BYPASS + To PCIe PHY + 12 + 1 + read-write + + + PCIE1_PHY_TX_VBOOST_LVL + To PCIe PHY + 13 + 3 + read-write + + + PCIE1_PHY_TX0_TERM_OFFSET + To PCIe PHY + 16 + 5 + read-write + + + PCIE1_PHY_RX0_EQ + To PCIe PHY + 21 + 3 + read-write + + + PCIE1_PHY_LOS_LEVEL + To PCIe PHY + 24 + 5 + read-write + + + PCIE1_PHY_LOS_BIAS + To PCIe PHY + 29 + 3 + read-write + + + + + GPR15 + GPR15 General Purpose Register + 0x3C + 32 + read-write + 0x6188FFFF + 0xFFFFFFFF + + + PCIE1_PCS_TX_SWING_LOW + To PCIe PHY + 0 + 7 + read-write + + + PCIE1_PCS_TX_SWING_FULL + To PCIe PHY + 7 + 7 + read-write + + + PCIE1_PCS_TX_DEEMPH_GEN2_6DB + To PCIe PHY + 14 + 6 + read-write + + + PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB + To PCIe PHY + 20 + 6 + read-write + + + PCIE1_PCS_TX_DEEMPH_GEN1 + To PCIe PHY + 26 + 6 + read-write + + + + + GPR16 + GPR16 General Purpose Register + 0x40 + 32 + read-write + 0x49409100 + 0xFFFFFFFF + + + PCIE2_APP_CLK_PM_EN + To PCIe PHY + 8 + 1 + read-write + + + PCIE2_REF_USE_PAD + To PCIe PHY + 9 + 1 + read-write + + + PCIE2_CLKREQ_B_OVERRIDE_EN + Control the PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller + 10 + 1 + read-write + + + PCIE2_CLKREQ_B_OVERRIDE + Control the PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller + 11 + 1 + read-write + + + PCIE2_VREG_BYPASS + To PCIe PHY + 12 + 1 + read-write + + + PCIE2_PHY_TX_VBOOST_LVL + To PCIe PHY + 13 + 3 + read-write + + + PCIE2_PHY_TX0_TERM_OFFSET + To PCIe PHY + 16 + 5 + read-write + + + PCIE2_PHY_RX0_EQ + To PCIe PHY + 21 + 3 + read-write + + + PCIE2_PHY_LOS_LEVEL + To PCIe PHY + 24 + 5 + read-write + + + PCIE2_PHY_LOS_BIAS + To PCIe PHY + 29 + 3 + read-write + + + + + GPR17 + GPR17 General Purpose Register + 0x44 + 32 + read-write + 0x6188FFFF + 0xFFFFFFFF + + + PCIE2_PCS_TX_SWING_LOW + To PCIe PHY + 0 + 7 + read-write + + + PCIE2_PCS_TX_SWING_FULL + To PCIe PHY + 7 + 7 + read-write + + + PCIE2_PCS_TX_DEEMPH_GEN2_6DB + To PCIe PHY + 14 + 6 + read-write + + + PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB + To PCIe PHY + 20 + 6 + read-write + + + PCIE2_PCS_TX_DEEMPH_GEN1 + To PCIe PHY + 26 + 6 + read-write + + + + + GPR18 + GPR18 General Purpose Register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR19 + GPR19 General Purpose Register + 0x4C + 32 + read-only + 0 + 0xFFFFFFFF + + + PCIE_DIAG_STATUS + PCIe DIAG Status Bus + 0 + 32 + read-only + + + + + GPR20 + GPR20 General Purpose Register + 0x50 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR21 + GPR21 General Purpose Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR22 + GPR22 General Purpose Register + 0x58 + 32 + read-only + 0 + 0xFFFFFFFF + + + CPU_STANDBYWFI + Status of CPU STANDBYWFI low power states MSB: status of core 3 STANDBYWFI low power state LSB: status of core 0 STANDBYWFI low power state + 16 + 4 + read-only + + + CPU_STANDBYWFE + Status of CPU STANDBYWFE low power states MSB: status of core 3 STANDBYWFE low power state LSB: status of core 0 STANDBYWFE low power state + 20 + 4 + read-only + + + + + GPR23 + GPR23 General Purpose Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + DSI_RX_RCAL + For DSI Control + 0 + 2 + read-write + + + DSI_RTERM_SEL + For DSI Control + 2 + 1 + read-write + + + DSI_RCALT + For DSI Control + 3 + 2 + read-write + + + DSI_NOCAL + For DSI Control + 5 + 1 + read-write + + + DSI_HSEL + For DSI Control + 6 + 1 + read-write + + + DSI_TX_ULPS_ENABLE + For DSI Control + 7 + 5 + read-write + + + DSI_TRIGGER_SEND + For DSI Control + 12 + 2 + read-write + + + DSI_TRIGGER_REQ + For DSI Control + 14 + 1 + read-write + + + DDSI_DPHY_TURNAROUND + For DSI Control + 15 + 1 + read-write + + + + + GPR24 + GPR24 General Purpose Register + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + DSI_TWO_BIT_ERR + for DSI status + 0 + 1 + read-only + + + DSI_ECC_ONE_BIT_ERR_POS + for DSI status + 1 + 5 + read-only + + + DSI_ECC_ONE_BIT_ERR + for DSI status + 6 + 1 + read-only + + + DSI_ECC_ERR_POS + for DSI status + 7 + 3 + read-only + + + DSI_ECC_ERR + for DSI status + 10 + 1 + read-only + + + DSI_HOST_UNDERRUN_ERR + for DSI status + 11 + 1 + read-only + + + DSI_TRIGGER_ACK + for DSI status + 12 + 1 + read-only + + + DSI_LP_RX_TIMEOUT + for DSI status + 13 + 1 + read-only + + + DSI_HS_TX_TIMEOUT + for DSI status + 14 + 1 + read-only + + + DSI_HOST_BTA_TIMEOUT + for DSI status + 15 + 1 + read-only + + + DSI_DPHY_DIRECTION + for DSI status + 16 + 1 + read-only + + + DSI_CRC_ERR + for DSI status + 17 + 1 + read-only + + + DSI_CALOUT + for DSI status + 18 + 2 + read-only + + + DSI_CALCOMPL + for DSI status + 20 + 1 + read-only + + + DSI_ULPS_ACTIVE + for DSI status + 21 + 5 + read-only + + + + + GPR25 + GPR25 General Purpose Register + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + DSI_UI_STATUS3_RO + for DSI status: host_ui_status[125:96] + 0 + 30 + read-only + + + + + GPR26 + GPR26 General Purpose Register + 0x68 + 32 + read-only + 0 + 0xFFFFFFFF + + + DSI_UI_STATUS2_RO + for DSI status: host_ui_status[95:64] + 0 + 32 + read-only + + + + + GPR27 + GPR27 General Purpose Register + 0x6C + 32 + read-only + 0 + 0xFFFFFFFF + + + DSI_UI_STATUS1_RO + for DSI status: host_ui_status[63:32] + 0 + 32 + read-only + + + + + GPR28 + GPR28 General Purpose Register + 0x70 + 32 + read-only + 0 + 0xFFFFFFFF + + + DSI_UI_STATUS0_RO + for DSI status: host_ui_status[31:0] + 0 + 32 + read-only + + + + + GPR29 + GPR29 General Purpose Register + 0x74 + 32 + read-only + 0 + 0xFFFFFFFF + + + DSI_TEST_PATTERN + for DSI test control + 0 + 32 + read-only + + + + + GPR30 + GPR30 General Purpose Register + 0x78 + 32 + read-only + 0 + 0xFFFFFFFF + + + DSI_D0_INT_LB_BYTE_CNT + for DSI test status + 0 + 10 + read-only + + + DSI_D0_INT_LB_ERR_CNT + for DSI test status + 10 + 10 + read-only + + + DSI_D0_LB_ACTIVE + for DSI test status + 20 + 1 + read-only + + + + + GPR31 + GPR31 General Purpose Register + 0x7C + 32 + read-only + 0 + 0xFFFFFFFF + + + DSI_D1_INT_LB_BYTE_CNT + for DSI test status + 0 + 10 + read-only + + + DSI_D1_INT_LB_ERR_CNT + for DSI test status + 10 + 10 + read-only + + + DSI_D1_LB_ACTIVE + for DSI test status + 20 + 1 + read-only + + + + + GPR32 + GPR32 General Purpose Register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + DSI_D2_INT_LB_BYTE_CNT + for DSI test status + 0 + 10 + read-only + + + DSI_D2_INT_LB_ERR_CNT + for DSI test status + 10 + 10 + read-only + + + DSI_D2_LB_ACTIVE + for DSI test status + 20 + 1 + read-only + + + + + GPR33 + GPR33 General Purpose Register + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + DSI_D3_INT_LB_BYTE_CNT + for DSI test status + 0 + 10 + read-only + + + DSI_D3_INT_LB_ERR_CNT + for DSI test status + 10 + 10 + read-only + + + DSI_D3_LB_ACTIVE + for DSI test status + 20 + 1 + read-only + + + + + GPR34 + GPR34 General Purpose Register + 0x88 + 32 + read-write + 0x800 + 0xFFFFFFFF + + + CSI2_1_RX_RCAL + for CSI2_1 control + 0 + 2 + read-write + + + CSI2_1_S_PRG_RXHS_SETTLE + for DSI test status + 2 + 6 + read-write + + + CSI2_1_CONT_CLK_MODE + for DSI test status + 8 + 1 + read-write + + + CSI2_1_AUTO_PD_EN + for DSI test status + 9 + 1 + read-write + + + CSI2_1_HSEL + for DSI test status + 10 + 1 + read-write + + + CSI2_1_PD_RX + for DSI test status + 11 + 1 + read-write + + + CSI2_1_VID_INTFC_ENB + for DSI test status + 12 + 1 + read-write + + + CSI2_1_RX_ENABLE + for DSI test status + 13 + 1 + read-write + + + + + GPR35 + GPR35 General Purpose Register + 0x8C + 32 + read-only + 0 + 0xFFFFFFFF + + + CSI2_1_ECC_TWO_BIT_ERROR + for CSI2_1 status + 0 + 1 + read-only + + + CSI2_1_ECC_ONE_BIT_ERR_POS + for CSI2_1 status + 1 + 5 + read-only + + + CSI2_1_ECC_ONE_BIT_ERROR + for CSI2_1 status + 6 + 1 + read-only + + + CSI2_1_ECC_ERR_POS + for CSI2_1 status + 7 + 3 + read-only + + + CSI2_1_ECC_ERR + for CSI2_1 status + 10 + 1 + read-only + + + CSI2_1_ULPS_MARK_ACTIVE + for CSI2_1 status + 11 + 5 + read-only + + + CSI2_1_RX_DPHY_RDY + for CSI2_1 status + 16 + 1 + read-only + + + CSI2_1_CRC_ERR + for CSI2_1 status + 17 + 1 + read-only + + + CSI2_1_ULPS_ACTIVE + for CSI2_1 status + 18 + 5 + read-only + + + CSI2_1_ERR_FIFO_WR_OVFL + for CSI2_1 status + 23 + 1 + read-only + + + CSI2_1_ERR_SEND_LEVEL + for CSI2_1 status + 24 + 1 + read-only + + + + + GPR36 + GPR36 General Purpose Register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + CSI2_1_TEST_PATTERN + for CSI2_1 test control + 0 + 32 + read-only + + + + + GPR37 + GPR37 General Purpose Register + 0x94 + 32 + read-only + 0 + 0xFFFFFFFF + + + CSI2_1_D0_INT_LB_BYTE_CNT + for DSI test status + 0 + 10 + read-only + + + CSI2_1_D0_INT_LB_ERR_CNT + for DSI test status + 10 + 10 + read-only + + + CSI2_1_D0_LB_ACTIVE + for DSI test status + 20 + 1 + read-only + + + + + GPR38 + GPR38 General Purpose Register + 0x98 + 32 + read-only + 0 + 0xFFFFFFFF + + + CSI2_1_D1_INT_LB_BYTE_CNT + for DSI test status + 0 + 10 + read-only + + + CSI2_1_D1_INT_LB_ERR_CNT + for DSI test status + 10 + 10 + read-only + + + CSI2_1_D1_LB_ACTIVE + for DSI test status + 20 + 1 + read-only + + + + + GPR39 + GPR39 General Purpose Register + 0x9C + 32 + read-only + 0 + 0xFFFFFFFF + + + CSI2_1_D2_INT_LB_BYTE_CNT + for DSI test status + 0 + 10 + read-only + + + CSI2_1_D2_INT_LB_ERR_CNT + for DSI test status + 10 + 10 + read-only + + + CSI2_1_D2_LB_ACTIVE + for DSI test status + 20 + 1 + read-only + + + + + GPR40 + GPR40 General Purpose Register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + CSI2_1_D3_INT_LB_BYTE_CNT + for DSI test status + 0 + 10 + read-only + + + CSI2_1_D3_INT_LB_ERR_CNT + for DSI test status + 10 + 10 + read-only + + + CSI2_1_D3_LB_ACTIVE + for DSI test status + 20 + 1 + read-only + + + + + GPR41 + GPR41 General Purpose Register + 0xA4 + 32 + read-write + 0x800 + 0xFFFFFFFF + + + CSI2_2_RX_RCAL + for CSI2_2 control + 0 + 2 + read-write + + + CSI2_2_S_PRG_RXHS_SETTLE + for DSI test status + 2 + 6 + read-write + + + CSI2_2_CONT_CLK_MODE + for DSI test status + 8 + 1 + read-write + + + CSI2_2_AUTO_PD_EN + for DSI test status + 9 + 1 + read-write + + + CSI2_2_HSEL + for DSI test status + 10 + 1 + read-write + + + CSI2_2_PD_RX + for DSI test status + 11 + 1 + read-write + + + CSI2_2_VID_INTFC_ENB + for DSI test status + 12 + 1 + read-write + + + CSI2_2_RX_ENABLE + for DSI test status + 13 + 1 + read-write + + + + + GPR42 + GPR42 General Purpose Register + 0xA8 + 32 + read-only + 0 + 0xFFFFFFFF + + + CSI2_2_ECC_TWO_BIT_ERROR + for CSI2_2 status + 0 + 1 + read-only + + + CSI2_2_ECC_ONE_BIT_ERR_POS + for CSI2_2 status + 1 + 5 + read-only + + + CSI2_2_ECC_ONE_BIT_ERROR + for CSI2_2 status + 6 + 1 + read-only + + + CSI2_2_ECC_ERR_POS + for CSI2_2 status + 7 + 3 + read-only + + + CSI2_2_ECC_ERR + for CSI2_2 status + 10 + 1 + read-only + + + CSI2_2_ULPS_MARK_ACTIVE + for CSI2_2 status + 11 + 5 + read-only + + + CSI2_2_RX_DPHY_RDY + for CSI2_2 status + 16 + 1 + read-only + + + CSI2_2_CRC_ERR + for CSI2_2 status + 17 + 1 + read-only + + + CSI2_2_ULPS_ACTIVE + for CSI2_2 status + 18 + 5 + read-only + + + CSI2_2_ERR_FIFO_WR_OVFL + for CSI2_2 status + 23 + 1 + read-only + + + CSI2_2_ERR_SEND_LEVEL + for CSI2_2 status + 24 + 1 + read-only + + + + + GPR43 + GPR43 General Purpose Register + 0xAC + 32 + read-only + 0 + 0xFFFFFFFF + + + CSI2_2_TEST_PATTERN + for CSI2_2 test control + 0 + 32 + read-only + + + + + GPR44 + GPR44 General Purpose Register + 0xB0 + 32 + read-only + 0 + 0xFFFFFFFF + + + CSI2_2_D0_INT_LB_BYTE_CNT + for DSI test status + 0 + 10 + read-only + + + CSI2_2_D0_INT_LB_ERR_CNT + for DSI test status + 10 + 10 + read-only + + + CSI2_2_D0_LB_ACTIVE + for DSI test status + 20 + 1 + read-only + + + + + GPR45 + GPR45 General Purpose Register + 0xB4 + 32 + read-only + 0 + 0xFFFFFFFF + + + CSI2_2_D1_INT_LB_BYTE_CNT + for DSI test status + 0 + 10 + read-only + + + CSI2_2_D1_INT_LB_ERR_CNT + for DSI test status + 10 + 10 + read-only + + + CSI2_2_D1_LB_ACTIVE + for DSI test status + 20 + 1 + read-only + + + + + GPR46 + GPR46 General Purpose Register + 0xB8 + 32 + read-only + 0 + 0xFFFFFFFF + + + CSI2_2_D2_INT_LB_BYTE_CNT + for DSI test status + 0 + 10 + read-only + + + CSI2_2_D2_INT_LB_ERR_CNT + for DSI test status + 10 + 10 + read-only + + + CSI2_2_D2_LB_ACTIVE + for DSI test status + 20 + 1 + read-only + + + + + GPR47 + GPR47 General Purpose Register + 0xBC + 32 + read-only + 0 + 0xFFFFFFFF + + + CSI2_2_D3_INT_LB_BYTE_CNT + for DSI test status + 0 + 10 + read-only + + + CSI2_2_D3_INT_LB_ERR_CNT + for DSI test status + 10 + 10 + read-only + + + CSI2_2_D3_LB_ACTIVE + for DSI test status + 20 + 1 + read-only + + + + + + + OCOTP + OCOTP Register Reference Index + OCOTP + OCOTP_ + 0x30350000 + + 0 + 0x13B4 + registers + + + + HW_CTRL + OTP Controller Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 8 + read-write + + + BUSY + OTP controller status bit + 8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 10 + 1 + read-write + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 16 + 16 + read-write + + + + + HW_CTRL_SET + OTP Controller Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 8 + read-write + + + BUSY + OTP controller status bit + 8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 10 + 1 + read-write + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 16 + 16 + read-write + + + + + HW_CTRL_CLR + OTP Controller Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 8 + read-write + + + BUSY + OTP controller status bit + 8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 10 + 1 + read-write + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 16 + 16 + read-write + + + + + HW_CTRL_TOG + OTP Controller Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 8 + read-write + + + BUSY + OTP controller status bit + 8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 10 + 1 + read-write + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 16 + 16 + read-write + + + + + HW_TIMING + OTP Controller Timing Register + 0x10 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + STROBE_PROG + This count value specifies the strobe period in one time write OTP + 0 + 12 + read-write + + + RELAX + This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd + 12 + 4 + read-write + + + STROBE_READ + This count value specifies the strobe period in one time read OTP + 16 + 6 + read-write + + + WAIT + This count value specifies time interval between auto read and write access in one time program + 22 + 6 + read-write + + + RSRVD0 + These bits always read back zero. + 28 + 4 + read-only + + + + + HW_DATA + OTP Controller Write Data Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Used to initiate a write to OTP + 0 + 32 + read-write + + + + + HW_READ_CTRL + OTP Controller Write Data Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + READ_FUSE + Used to initiate a read to OTP + 0 + 1 + read-write + + + RSVD0 + Reserved + 1 + 31 + read-only + + + + + HW_READ_FUSE_DATA + OTP Controller Read Data Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + The data read from OTP + 0 + 32 + read-write + + + + + HW_SW_STICKY + Sticky bit Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Reserved + 0 + 1 + read-only + + + SRK_REVOKE_LOCK + Shadow register write and OTP write lock for SRK_REVOKE region + 1 + 1 + read-write + + + FIELD_RETURN_LOCK + Shadow register write and OTP write lock for FIELD_RETURN region + 2 + 1 + read-write + + + BLOCK_ROM_PART + Set by ARM during Boot after DTCP is initialized and before test mode entry, if ROM_PART_LOCK=1 + 3 + 1 + read-write + + + JTAG_BLOCK_RELEASE + Set by ARM during Boot after DTCP is initialized and before test mode entry + 4 + 1 + read-write + + + DISABLE_READ_GROUP_MASK + Shadow register write and OTP write lock for GROUP_MASK region + 5 + 1 + read-write + + + DISABLE_READ_HDMI_FW_SRK + Shadow register write and OTP write lock for HDMI_FW_SRK region + 6 + 1 + read-write + + + DISABLE_READ_HDMI_KMEK + Shadow register write and OTP write lock for HDMI_KMEK region + 7 + 1 + read-write + + + DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT + Shadow register write and OTP write lock for HDCP_TX_GLOBAL_CONSTANT region + 8 + 1 + read-write + + + DISABLE_READ_HDCP_TX_CERT + Shadow register write and OTP write lock for HDCP_TX_CERT region + 9 + 1 + read-write + + + DISABLE_READ_HDCP_DEVICE_KEY + Shadow register write and OTP write lock for HDCP_DEVICE_HDCP region + 10 + 1 + read-write + + + RSVD1 + Reserved + 11 + 21 + read-only + + + + + HW_SCS + Software Controllable Signals Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 31 + 1 + read-write + + + + + HW_SCS_SET + Software Controllable Signals Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 31 + 1 + read-write + + + + + HW_SCS_CLR + Software Controllable Signals Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 31 + 1 + read-write + + + + + HW_SCS_TOG + Software Controllable Signals Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 31 + 1 + read-write + + + + + HW_VERSION + OTP Controller Version Register + 0x90 + 32 + read-only + 0x1481299 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 24 + 8 + read-only + + + + + HW_LOCK + Value of OTP Bank0 Word0 (Lock controls) + 0x400 + 32 + read-only + 0 + 0xFFFFFFFF + + + TESTER + Status of shadow register and OTP write lock for tester region + 0 + 2 + read-only + + + BOOT_CFG + Status of shadow register and OTP write lock for boot_cfg region + 2 + 2 + read-only + + + MEM_TRIM + Status of shadow register and OTP write lock for mem_trim region + 4 + 2 + read-only + + + ANALOG + Status of shadow register and OTP write lock for analog region + 6 + 2 + read-only + + + OTPMK + Status of shadow register read and write, OTP read and write lock for otpmk region + 8 + 1 + read-only + + + SRK + Status of shadow register and OTP write lock for srk region + 9 + 1 + read-only + + + SJC_RESP + Status of shadow register read and write, OTP read and write lock for sjc_resp region + 10 + 1 + read-only + + + GROUP_MASK + Status of shadow register and OTP write lock for group mask region + 11 + 1 + read-only + + + USB_ID + Status of shadow register and OTP write lock for usb_id region + 12 + 2 + read-only + + + MAC_ADDR + Status of shadow register and OTP write lock for mac_addr region + 14 + 2 + read-only + + + MAU_KEY + Status of shadow register read and write, OTP read and write lock for manufacture_key region + 16 + 1 + read-only + + + ROM_PATCH + Status of shadow register and OTP write lock for rom_patch region + 17 + 1 + read-only + + + GP_CRC + Status of shadow register and OTP write lock for gp_crc region + 18 + 2 + read-only + + + GP1 + Status of shadow register and OTP write lock for gp1 region + 20 + 2 + read-only + + + GP2 + Status of shadow register and OTP write lock for gp2 region + 22 + 2 + read-only + + + HDMI_KEY + Status of shadow register write and read, OTP write and read lock for hdmi_key region + 24 + 2 + read-only + + + HDMI_CRC + Status of shadow register write and read, OTP write and read lock for hdcp_crc region + 26 + 2 + read-only + + + HDCP_KEY + Status of shadow register write and read, OTP write and read lock for hdcp_key region + 28 + 2 + read-only + + + HDCP_CRC + Status of shadow register write and read, OTP write and read lock for hdcp_crc region + 30 + 2 + read-only + + + + + HW_TESTER0 + Value of OTP Bank0 Word1 (Tester Info.) + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 1 + 0 + 32 + read-write + + + + + HW_TESTER1 + Value of OTP Bank0 Word2 (tester Info.) + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 2 + 0 + 32 + read-write + + + + + HW_TESTER2 + Value of OTP Bank0 Word3 (Tester Info.) + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 3 + 0 + 32 + read-write + + + + + HW_TESTER3 + Value of OTP Bank1 Word0 (Tester Info.) + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 1, word 0 + 0 + 32 + read-write + + + + + HW_TESTER4 + Value of OTP Bank1 Word1 (Tester Info.) + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 1, word 1 + 0 + 32 + read-write + + + + + HW_TESTER5 + Value of OTP Bank1 Word2 (Tester Info.) + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 1, word 2 + 0 + 32 + read-write + + + + + HW_BOOT_CFG0 + Value of OTP Bank1 Word3 (Boot Configuration Info.) + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 1, word 3 + 0 + 32 + read-write + + + + + HW_BOOT_CFG1 + Value of OTP Bank2 Word0 (Boot Configuration Info.) + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 2, word 0 + 0 + 32 + read-write + + + + + HW_BOOT_CFG2 + Value of OTP Bank2 Word1 (Boot Configuration Info.) + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 2, word 1 + 0 + 32 + read-write + + + + + HW_BOOT_CFG3 + Value of OTP Bank2 Word2 (Boot Configuration Info.) + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 2, word 2 + 0 + 32 + read-write + + + + + HW_BOOT_CFG4 + Value of OTP Bank2 Word3 (BOOT Configuration Info.) + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 2, word 3 + 0 + 32 + read-write + + + + + HW_MEM_TRIM0 + Value of OTP Bank3 Word0 (Memory Related Info.) + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 3, word 0 + 0 + 32 + read-write + + + + + HW_MEM_TRIM1 + Value of OTP Bank3 Word1 (Memory Related Info.) + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 3, word 1 + 0 + 32 + read-write + + + + + HW_ANA0 + Value of OTP Bank3 Word2 (Analog Info.) + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 3, word 2 + 0 + 32 + read-write + + + + + HW_ANA1 + Value of OTP Bank3 Word3 (Analog Info.) + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 3, word 3 + 0 + 32 + read-write + + + + + HW_SRK0 + Shadow Register for OTP Bank6 Word0 (SRK Hash) + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word0 (Copy of OTP Bank 6, word 0) + 0 + 32 + read-write + + + + + HW_SRK1 + Shadow Register for OTP Bank6 Word1 (SRK Hash) + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word1 (Copy of OTP Bank 6, word 1) + 0 + 32 + read-write + + + + + HW_SRK2 + Shadow Register for OTP Bank6 Word2 (SRK Hash) + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word2 (Copy of OTP Bank 6, word 2) + 0 + 32 + read-write + + + + + HW_SRK3 + Shadow Register for OTP Bank6 Word3 (SRK Hash) + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word3 (Copy of OTP Bank 6, word 3) + 0 + 32 + read-write + + + + + HW_SRK4 + Shadow Register for OTP Bank7 Word0 (SRK Hash) + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word4 (Copy of OTP Bank 7, word 0) + 0 + 32 + read-write + + + + + HW_SRK5 + Shadow Register for OTP Bank7 Word1 (SRK Hash) + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word5 (Copy of OTP Bank 7, word 1) + 0 + 32 + read-write + + + + + HW_SRK6 + Shadow Register for OTP Bank7 Word2 (SRK Hash) + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word6 (Copy of OTP Bank 7, word 2) + 0 + 32 + read-write + + + + + HW_SRK7 + Shadow Register for OTP Bank7 Word3 (SRK Hash) + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word7 (Copy of OTP Bank 7, word 3) + 0 + 32 + read-write + + + + + HW_SJC_RESP0 + Value of OTP Bank8 Word0 (Secure JTAG Response Field) + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 8, word 0) + 0 + 32 + read-write + + + + + HW_SJC_RESP1 + Value of OTP Bank8 Word1 (Secure JTAG Response Field) + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 8, word 1) + 0 + 32 + read-write + + + + + HW_USB_ID + Value of OTP Bank8 Word2 (USB ID info) + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 2. + 0 + 32 + read-write + + + + + HW_FIELD_RETURN + Value of OTP Bank5 Word6 (Field Return) + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 3. + 0 + 32 + read-write + + + + + HW_MAC_ADDR0 + Value of OTP Bank9 Word0 (MAC Address) + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 9, word 0. + 0 + 32 + read-write + + + + + HW_MAC_ADDR1 + Value of OTP Bank9 Word1 (MAC Address) + 0x650 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 9, word 1. + 0 + 32 + read-write + + + + + HW_MAC_ADDR2 + Value of OTP Bank9 Word2 (MAC Address) + 0x660 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 9, word 2. + 0 + 32 + read-write + + + + + HW_SRK_REVOKE + Value of OTP Bank9 Word3 (SRK Revoke) + 0x670 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 9, word 3. + 0 + 32 + read-write + + + + + HW_MAU_KEY0 + Shadow Register for OTP Bank10 Word0 (MAU Key) + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the MAU Key word0 (Copy of OTP Bank 10, word 0) + 0 + 32 + read-write + + + + + HW_MAU_KEY1 + Shadow Register for OTP Bank10 Word1 (MAU Key) + 0x690 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the MAU Key word1 (Copy of OTP Bank 10, word 1) + 0 + 32 + read-write + + + + + HW_MAU_KEY2 + Shadow Register for OTP Bank10 Word2 (MAU Key) + 0x6A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the MAU Key word2 (Copy of OTP Bank 10, word 2) + 0 + 32 + read-write + + + + + HW_MAU_KEY3 + Shadow Register for OTP Bank10 Word3 (MAU Key) + 0x6B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the MAU Key word3 (Copy of OTP Bank 10, word 3) + 0 + 32 + read-write + + + + + HW_MAU_KEY4 + Shadow Register for OTP Bank11 Word0 (MAU Key) + 0x6C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the MAU Key word4 (Copy of OTP Bank 11, word 0) + 0 + 32 + read-write + + + + + HW_MAU_KEY5 + Shadow Register for OTP Bank11 Word1 (MAU Key) + 0x6D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the MAU Key word5 (Copy of OTP Bank 11, word 1) + 0 + 32 + read-write + + + + + HW_MAU_KEY6 + Shadow Register for OTP Bank11 Word2 (MAU Key) + 0x6E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the MAU Key word6 (Copy of OTP Bank 11, word 2) + 0 + 32 + read-write + + + + + HW_MAU_KEY7 + Shadow Register for OTP Bank11 Word3 (MAU Key) + 0x6F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the MAU Key word7 (Copy of OTP Bank 11, word 3) + 0 + 32 + read-write + + + + + HW_GP10 + Value of OTP Bank14 Word0 () + 0x780 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 14, word 0. + 0 + 32 + read-write + + + + + HW_GP11 + Value of OTP Bank14 Word1 () + 0x790 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 14, word 1. + 0 + 32 + read-write + + + + + HW_GP20 + Value of OTP Bank14 Word2 () + 0x7A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 14, word 2. + 0 + 32 + read-write + + + + + HW_GP21 + Value of OTP Bank14 Word3 () + 0x7B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 14, word 3. + 0 + 32 + read-write + + + + + HW_GP_CRC0 + Value of OTP Bank15 Word0 (CRC Key) + 0x7C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 15, word 0. + 0 + 32 + read-write + + + + + HW_GP_CRC1 + Value of OTP Bank15 Word1 (CRC Key) + 0x7D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 15, word 1. + 0 + 32 + read-write + + + + + HW_GP_CRC2 + Value of OTP Bank15 Word2 (CRC Key) + 0x7E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 15, word 2. + 0 + 32 + read-write + + + + + HW_GROUP_MASK + Value of OTP Bank15 Word3 (CRC Key) + 0x7F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 15, word 3. + 0 + 32 + read-write + + + + + HW_HDMI_FW_SRK0 + Value of OTP Bank16 Word0 (HDCP Key) + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDMI_FW_SRK1 + Value of OTP Bank16 Word1 (HDCP Key) + 0x810 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 1. + 0 + 32 + read-write + + + + + HW_HDMI_FW_SRK2 + Value of OTP Bank16 Word0 (HDCP Key) + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 2. + 0 + 32 + read-write + + + + + HW_HDMI_FW_SRK3 + Value of OTP Bank16 Word0 (HDCP Key) + 0x830 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDMI_FW_SRK4 + Value of OTP Bank17 Word0 (HDCP Key) + 0x840 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDMI_FW_SRK5 + Value of OTP Bank17 Word1 (HDCP Key) + 0x850 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDMI_FW_SRK6 + Value of OTP Bank16 Word0 (HDCP Key) + 0x860 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDMI_FW_SRK7 + Value of OTP Bank16 Word0 (HDCP Key) + 0x870 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDMI_KMEK0 + Value of OTP Bank16 Word0 (HDCP Key) + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDMI_KMEK1 + Value of OTP Bank16 Word0 (HDCP Key) + 0x890 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDMI_KMEK2 + Value of OTP Bank16 Word0 (HDCP Key) + 0x8A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDMI_KMEK3 + Value of OTP Bank16 Word0 (HDCP Key) + 0x8B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CONS0 + Value of OTP Bank16 Word0 (HDCP Key) + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CONS1 + Value of OTP Bank16 Word1 (HDCP Key) + 0x910 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CONS2 + Value of OTP Bank16 Word0 (HDCP Key) + 0x920 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 2. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CONS3 + Value of OTP Bank16 Word0 (HDCP Key) + 0x930 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT0 + Value of OTP Bank17 Word0 (HDCP Key) + 0x940 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT1 + Value of OTP Bank17 Word1 (HDCP Key) + 0x950 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT2 + Value of OTP Bank16 Word0 (HDCP Key) + 0x960 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT3 + Value of OTP Bank16 Word0 (HDCP Key) + 0x970 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT4 + Value of OTP Bank16 Word0 (HDCP Key) + 0x980 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT5 + Value of OTP Bank16 Word0 (HDCP Key) + 0x990 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT6 + Value of OTP Bank16 Word0 (HDCP Key) + 0x9A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT7 + Value of OTP Bank16 Word0 (HDCP Key) + 0x9B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT8 + Value of OTP Bank17 Word0 (HDCP Key) + 0x9C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT9 + Value of OTP Bank17 Word1 (HDCP Key) + 0x9D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT10 + Value of OTP Bank16 Word0 (HDCP Key) + 0x9E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT11 + Value of OTP Bank16 Word0 (HDCP Key) + 0x9F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT12 + Value of OTP Bank16 Word0 (HDCP Key) + 0xA00 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT13 + Value of OTP Bank16 Word1 (HDCP Key) + 0xA10 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT14 + Value of OTP Bank16 Word0 (HDCP Key) + 0xA20 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 2. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT15 + Value of OTP Bank16 Word0 (HDCP Key) + 0xA30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT16 + Value of OTP Bank17 Word0 (HDCP Key) + 0xA40 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT17 + Value of OTP Bank17 Word1 (HDCP Key) + 0xA50 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT18 + Value of OTP Bank16 Word0 (HDCP Key) + 0xA60 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT19 + Value of OTP Bank16 Word0 (HDCP Key) + 0xA70 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT20 + Value of OTP Bank16 Word0 (HDCP Key) + 0xA80 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT21 + Value of OTP Bank16 Word0 (HDCP Key) + 0xA90 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT22 + Value of OTP Bank16 Word0 (HDCP Key) + 0xAA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT23 + Value of OTP Bank16 Word0 (HDCP Key) + 0xAB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT24 + Value of OTP Bank17 Word0 (HDCP Key) + 0xAC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT25 + Value of OTP Bank17 Word1 (HDCP Key) + 0xAD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT26 + Value of OTP Bank16 Word0 (HDCP Key) + 0xAE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT27 + Value of OTP Bank16 Word0 (HDCP Key) + 0xAF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT28 + Value of OTP Bank16 Word0 (HDCP Key) + 0xB00 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT29 + Value of OTP Bank16 Word1 (HDCP Key) + 0xB10 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT30 + Value of OTP Bank16 Word0 (HDCP Key) + 0xB20 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 2. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT31 + Value of OTP Bank16 Word0 (HDCP Key) + 0xB30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT32 + Value of OTP Bank17 Word0 (HDCP Key) + 0xB40 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT33 + Value of OTP Bank17 Word1 (HDCP Key) + 0xB50 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT34 + Value of OTP Bank16 Word0 (HDCP Key) + 0xB60 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT35 + Value of OTP Bank16 Word0 (HDCP Key) + 0xB70 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT36 + Value of OTP Bank16 Word0 (HDCP Key) + 0xB80 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT37 + Value of OTP Bank16 Word0 (HDCP Key) + 0xB90 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT38 + Value of OTP Bank16 Word0 (HDCP Key) + 0xBA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT39 + Value of OTP Bank16 Word0 (HDCP Key) + 0xBB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT40 + Value of OTP Bank17 Word0 (HDCP Key) + 0xBC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT41 + Value of OTP Bank17 Word1 (HDCP Key) + 0xBD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT42 + Value of OTP Bank16 Word0 (HDCP Key) + 0xBE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT43 + Value of OTP Bank16 Word0 (HDCP Key) + 0xBF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT44 + Value of OTP Bank16 Word0 (HDCP Key) + 0xC00 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT45 + Value of OTP Bank16 Word1 (HDCP Key) + 0xC10 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT46 + Value of OTP Bank16 Word0 (HDCP Key) + 0xC20 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 2. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT47 + Value of OTP Bank16 Word0 (HDCP Key) + 0xC30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT48 + Value of OTP Bank17 Word0 (HDCP Key) + 0xC40 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT49 + Value of OTP Bank17 Word1 (HDCP Key) + 0xC50 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT50 + Value of OTP Bank16 Word0 (HDCP Key) + 0xC60 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT51 + Value of OTP Bank16 Word0 (HDCP Key) + 0xC70 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT52 + Value of OTP Bank16 Word0 (HDCP Key) + 0xC80 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT53 + Value of OTP Bank16 Word0 (HDCP Key) + 0xC90 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT54 + Value of OTP Bank16 Word0 (HDCP Key) + 0xCA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT55 + Value of OTP Bank16 Word0 (HDCP Key) + 0xCB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT56 + Value of OTP Bank17 Word0 (HDCP Key) + 0xCC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT57 + Value of OTP Bank17 Word1 (HDCP Key) + 0xCD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT58 + Value of OTP Bank16 Word0 (HDCP Key) + 0xCE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT59 + Value of OTP Bank16 Word0 (HDCP Key) + 0xCF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT60 + Value of OTP Bank16 Word0 (HDCP Key) + 0xD00 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT61 + Value of OTP Bank16 Word1 (HDCP Key) + 0xD10 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT62 + Value of OTP Bank16 Word0 (HDCP Key) + 0xD20 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 2. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT63 + Value of OTP Bank16 Word0 (HDCP Key) + 0xD30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT64 + Value of OTP Bank17 Word0 (HDCP Key) + 0xD40 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT65 + Value of OTP Bank17 Word1 (HDCP Key) + 0xD50 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT66 + Value of OTP Bank16 Word0 (HDCP Key) + 0xD60 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT67 + Value of OTP Bank16 Word0 (HDCP Key) + 0xD70 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT68 + Value of OTP Bank16 Word0 (HDCP Key) + 0xD80 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT69 + Value of OTP Bank16 Word0 (HDCP Key) + 0xD90 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT70 + Value of OTP Bank16 Word0 (HDCP Key) + 0xDA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT71 + Value of OTP Bank16 Word0 (HDCP Key) + 0xDB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT72 + Value of OTP Bank17 Word0 (HDCP Key) + 0xDC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT73 + Value of OTP Bank17 Word1 (HDCP Key) + 0xDD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT74 + Value of OTP Bank16 Word0 (HDCP Key) + 0xDE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT75 + Value of OTP Bank16 Word0 (HDCP Key) + 0xDF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT76 + Value of OTP Bank16 Word0 (HDCP Key) + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT77 + Value of OTP Bank16 Word1 (HDCP Key) + 0xE10 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT78 + Value of OTP Bank16 Word0 (HDCP Key) + 0xE20 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 2. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT79 + Value of OTP Bank16 Word0 (HDCP Key) + 0xE30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT80 + Value of OTP Bank17 Word0 (HDCP Key) + 0xE40 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT81 + Value of OTP Bank17 Word1 (HDCP Key) + 0xE50 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT82 + Value of OTP Bank16 Word0 (HDCP Key) + 0xE60 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT83 + Value of OTP Bank16 Word0 (HDCP Key) + 0xE70 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT84 + Value of OTP Bank16 Word0 (HDCP Key) + 0xE80 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT85 + Value of OTP Bank16 Word0 (HDCP Key) + 0xE90 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT86 + Value of OTP Bank16 Word0 (HDCP Key) + 0xEA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT87 + Value of OTP Bank16 Word0 (HDCP Key) + 0xEB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT88 + Value of OTP Bank17 Word0 (HDCP Key) + 0xEC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT89 + Value of OTP Bank17 Word1 (HDCP Key) + 0xED0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT90 + Value of OTP Bank16 Word0 (HDCP Key) + 0xEE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT91 + Value of OTP Bank16 Word0 (HDCP Key) + 0xEF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT92 + Value of OTP Bank16 Word0 (HDCP Key) + 0xF00 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT93 + Value of OTP Bank16 Word1 (HDCP Key) + 0xF10 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT94 + Value of OTP Bank16 Word0 (HDCP Key) + 0xF20 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 2. + 0 + 32 + read-write + + + + + HW_HDCP_TX_CERT95 + Value of OTP Bank16 Word0 (HDCP Key) + 0xF30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_KEY0 + Value of OTP Bank17 Word0 (HDCP Key) + 0xF40 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY1 + Value of OTP Bank17 Word1 (HDCP Key) + 0xF50 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_KEY2 + Value of OTP Bank16 Word0 (HDCP Key) + 0xF60 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY3 + Value of OTP Bank16 Word0 (HDCP Key) + 0xF70 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY4 + Value of OTP Bank16 Word0 (HDCP Key) + 0xF80 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY5 + Value of OTP Bank16 Word0 (HDCP Key) + 0xF90 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY6 + Value of OTP Bank16 Word0 (HDCP Key) + 0xFA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY7 + Value of OTP Bank16 Word0 (HDCP Key) + 0xFB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_KEY8 + Value of OTP Bank17 Word0 (HDCP Key) + 0xFC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY9 + Value of OTP Bank17 Word1 (HDCP Key) + 0xFD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_KEY10 + Value of OTP Bank16 Word0 (HDCP Key) + 0xFE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY11 + Value of OTP Bank16 Word0 (HDCP Key) + 0xFF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY12 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1000 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY13 + Value of OTP Bank16 Word1 (HDCP Key) + 0x1010 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_KEY14 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1020 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 2. + 0 + 32 + read-write + + + + + HW_HDCP_KEY15 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1030 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_KEY16 + Value of OTP Bank17 Word0 (HDCP Key) + 0x1040 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY17 + Value of OTP Bank17 Word1 (HDCP Key) + 0x1050 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_KEY18 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1060 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY19 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1070 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY20 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1080 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY21 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1090 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY22 + Value of OTP Bank16 Word0 (HDCP Key) + 0x10A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY23 + Value of OTP Bank16 Word0 (HDCP Key) + 0x10B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_KEY24 + Value of OTP Bank17 Word0 (HDCP Key) + 0x10C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY25 + Value of OTP Bank17 Word1 (HDCP Key) + 0x10D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_KEY26 + Value of OTP Bank16 Word0 (HDCP Key) + 0x10E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY27 + Value of OTP Bank16 Word0 (HDCP Key) + 0x10F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY28 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1100 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY29 + Value of OTP Bank16 Word1 (HDCP Key) + 0x1110 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_KEY30 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1120 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 2. + 0 + 32 + read-write + + + + + HW_HDCP_KEY31 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1130 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_KEY32 + Value of OTP Bank17 Word0 (HDCP Key) + 0x1140 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY33 + Value of OTP Bank17 Word1 (HDCP Key) + 0x1150 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_KEY34 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1160 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY35 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1170 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY36 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1180 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY37 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1190 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY38 + Value of OTP Bank16 Word0 (HDCP Key) + 0x11A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY39 + Value of OTP Bank16 Word0 (HDCP Key) + 0x11B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_KEY40 + Value of OTP Bank17 Word0 (HDCP Key) + 0x11C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY41 + Value of OTP Bank17 Word1 (HDCP Key) + 0x11D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_KEY42 + Value of OTP Bank16 Word0 (HDCP Key) + 0x11E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY43 + Value of OTP Bank16 Word0 (HDCP Key) + 0x11F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY44 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1200 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY45 + Value of OTP Bank16 Word1 (HDCP Key) + 0x1210 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_KEY46 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1220 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 2. + 0 + 32 + read-write + + + + + HW_HDCP_KEY47 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1230 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_KEY48 + Value of OTP Bank17 Word0 (HDCP Key) + 0x1240 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY49 + Value of OTP Bank17 Word1 (HDCP Key) + 0x1250 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_KEY50 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1260 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY51 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1270 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY52 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1280 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY53 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1290 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY54 + Value of OTP Bank16 Word0 (HDCP Key) + 0x12A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY55 + Value of OTP Bank16 Word0 (HDCP Key) + 0x12B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_KEY56 + Value of OTP Bank17 Word0 (HDCP Key) + 0x12C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY57 + Value of OTP Bank17 Word1 (HDCP Key) + 0x12D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_KEY58 + Value of OTP Bank16 Word0 (HDCP Key) + 0x12E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY59 + Value of OTP Bank16 Word0 (HDCP Key) + 0x12F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY60 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1300 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY61 + Value of OTP Bank16 Word1 (HDCP Key) + 0x1310 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_KEY62 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1320 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 2. + 0 + 32 + read-write + + + + + HW_HDCP_KEY63 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1330 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + HW_HDCP_KEY64 + Value of OTP Bank17 Word0 (HDCP Key) + 0x1340 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY65 + Value of OTP Bank17 Word1 (HDCP Key) + 0x1350 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 17, word 1. + 0 + 32 + read-write + + + + + HW_HDCP_KEY66 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1360 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY67 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1370 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY68 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1380 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY69 + Value of OTP Bank16 Word0 (HDCP Key) + 0x1390 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY70 + Value of OTP Bank16 Word0 (HDCP Key) + 0x13A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 0. + 0 + 32 + read-write + + + + + HW_HDCP_KEY71 + Value of OTP Bank16 Word0 (HDCP Key) + 0x13B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 16, word 3. + 0 + 32 + read-write + + + + + + + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG_ + 0x30360000 + + 0 + 0x80 + registers + + + + AUDIO_PLL1_CFG0 + AUDIO PLL1 Configuration 0 Register + 0 + 32 + read-write + 0x20C081 + 0xFFFFFFFF + + + PLL_OUTPUT_DIV_VAL + PLL output clock divide value Settings must maintain the PLL operational range + 0 + 5 + read-write + + + PLL_REFCLK_DIV_VAL + PLL reference clock divide value + 5 + 6 + read-write + + + PLL_NEWDIV_ACK + PLL new fraction divide handshake signal + 11 + 1 + read-only + + + PLL_NEWDIV_VAL + PLL new fraction divide input control active high + 12 + 1 + read-write + + + PLL_COUNTCLK_SEL + PLL maximum lock time counter clock select + 13 + 1 + read-write + + + PLL_COUNTCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_COUNTCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + + + PLL_BYPASS + PLL bypass control active high + 14 + 1 + read-write + + + PLL_LOCK_SEL + PLL Lock signal select + 15 + 1 + read-write + + + PLL_LOCK_SEL_0 + Select PLL lock output + 0 + + + PLL_LOCK_SEL_1 + Select maximum lock time counter output + 0x1 + + + + + PLL_REFCLK_SEL + PLL reference clocks select + 16 + 2 + read-write + + + PLL_REFCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_REFCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + PLL_REFCLK_SEL_2 + HDMI_PHY_27M_CLK + 0x2 + + + PLL_REFCLK_SEL_3 + CLK_P_N + 0x3 + + + + + PLL_PD_OVERRIDE + Override the PLL_PD, clock gating enable signal from CCM block active high + 18 + 1 + read-write + + + PLL_PD + PLL output clock clock gating enable active high + 19 + 1 + read-write + + + PLL_CLKE_OVERRIDE + Override the PLL_CLKE, clock gating enable signal from CCM block active high + 20 + 1 + read-write + + + PLL_CLKE + PLL output clock clock gating enable active high + 21 + 1 + read-write + + + PLL_LOCK + PLL lock status active high + 31 + 1 + read-only + + + + + AUDIO_PLL1_CFG1 + AUDIO PLL1 Configuration 1 Register + 0x4 + 32 + read-write + 0x40 + 0xFFFFFFFF + + + PLL_INT_DIV_CTL + PLL Integer divide control Settings must maintain the PLL operational range + 0 + 7 + read-write + + + PLL_FRAC_DIV_CTL + PLL fraction divide control Settings must maintain the PLL operational range + 7 + 24 + read-write + + + + + AUDIO_PLL2_CFG0 + AUDIO PLL2 Configuration 0 Register + 0x8 + 32 + read-write + 0x20C081 + 0xFFFFFFFF + + + PLL_OUTPUT_DIV_VAL + PLL output clock divide value Settings must maintain the PLL operational range + 0 + 5 + read-write + + + PLL_REFCLK_DIV_VAL + PLL reference clock divide value + 5 + 6 + read-write + + + PLL_NEWDIV_ACK + PLL new fraction divide handshake signal + 11 + 1 + read-only + + + PLL_NEWDIV_VAL + PLL new fraction divide input control active high + 12 + 1 + read-write + + + PLL_COUNTCLK_SEL + PLL maximum lock time counter clock select + 13 + 1 + read-write + + + PLL_COUNTCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_COUNTCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + + + PLL_BYPASS + PLL bypass control active high + 14 + 1 + read-write + + + PLL_LOCK_SEL + PLL Lock signal select + 15 + 1 + read-write + + + PLL_LOCK_SEL_0 + Select PLL lock output + 0 + + + PLL_LOCK_SEL_1 + Select maximum lock time counter output + 0x1 + + + + + PLL_REFCLK_SEL + PLL reference clocks select + 16 + 2 + read-write + + + PLL_REFCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_REFCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + PLL_REFCLK_SEL_2 + HDMI_PHY_27M_CLK + 0x2 + + + PLL_REFCLK_SEL_3 + CLK_P_N + 0x3 + + + + + PLL_PD_OVERRIDE + Override the PLL_PD, clock gating enable signal from CCM block active high + 18 + 1 + read-write + + + PLL_PD + PLL output clock clock gating enable active high + 19 + 1 + read-write + + + PLL_CLKE_OVERRIDE + Override the PLL_CLKE, clock gating enable signal from CCM block active high + 20 + 1 + read-write + + + PLL_CLKE + PLL output clock clock gating enable active high + 21 + 1 + read-write + + + PLL_LOCK + PLL lock status active high + 31 + 1 + read-only + + + + + AUDIO_PLL2_CFG1 + AUDIO PLL2 Configuration 1 Register + 0xC + 32 + read-write + 0x40 + 0xFFFFFFFF + + + PLL_INT_DIV_CTL + PLL Integer divide control Settings must maintain the PLL operational range + 0 + 7 + read-write + + + PLL_FRAC_DIV_CTL + PLL fraction divide control Settings must maintain the PLL operational range + 7 + 24 + read-write + + + + + VIDEO_PLL1_CFG0 + VIDEO PLL Configuration 0 Register + 0x10 + 32 + read-write + 0x20C081 + 0xFFFFFFFF + + + PLL_OUTPUT_DIV_VAL + PLL output clock divide value Settings must maintain the PLL operational range + 0 + 5 + read-write + + + PLL_REFCLK_DIV_VAL + PLL reference clock divide value + 5 + 6 + read-write + + + PLL_NEWDIV_ACK + PLL new fraction divide handshake signal + 11 + 1 + read-only + + + PLL_NEWDIV_VAL + PLL new fraction divide input control active high + 12 + 1 + read-write + + + PLL_COUNTCLK_SEL + PLL maximum lock time counter clock select + 13 + 1 + read-write + + + PLL_COUNTCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_COUNTCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + + + PLL_BYPASS + PLL bypass control active high + 14 + 1 + read-write + + + PLL_LOCK_SEL + PLL Lock signal select + 15 + 1 + read-write + + + PLL_LOCK_SEL_0 + Select PLL lock output + 0 + + + PLL_LOCK_SEL_1 + Select maximum lock time counter output + 0x1 + + + + + PLL_REFCLK_SEL + PLL reference clocks select + 16 + 2 + read-write + + + PLL_REFCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_REFCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + PLL_REFCLK_SEL_2 + HDMI_PHY_27M_CLK + 0x2 + + + PLL_REFCLK_SEL_3 + CLK_P_N + 0x3 + + + + + PLL_PD_OVERRIDE + Override the PLL_PD, clock gating enable signal from CCM block active high + 18 + 1 + read-write + + + PLL_PD + PLL output clock clock gating enable active high + 19 + 1 + read-write + + + PLL_CLKE_OVERRIDE + Override the PLL_CLKE, clock gating enable signal from CCM block active high + 20 + 1 + read-write + + + PLL_CLKE + PLL output clock clock gating enable active high + 21 + 1 + read-write + + + PLL_LOCK + PLL lock status active high + 31 + 1 + read-only + + + + + VIDEO_PLL1_CFG1 + VIDEO PLL Configuration 1 Register + 0x14 + 32 + read-write + 0x40 + 0xFFFFFFFF + + + PLL_INT_DIV_CTL + PLL Integer divide control Settings must maintain the PLL operational range + 0 + 7 + read-write + + + PLL_FRAC_DIV_CTL + PLL fraction divide control Settings must maintain the PLL operational range + 7 + 24 + read-write + + + + + GPU_PLL_CFG0 + GPU PLL Configuration 0 Register + 0x18 + 32 + read-write + 0x20C081 + 0xFFFFFFFF + + + PLL_OUTPUT_DIV_VAL + PLL output clock divide value Settings must maintain the PLL operational range + 0 + 5 + read-write + + + PLL_REFCLK_DIV_VAL + PLL reference clock divide value + 5 + 6 + read-write + + + PLL_NEWDIV_ACK + PLL new fraction divide handshake signal + 11 + 1 + read-only + + + PLL_NEWDIV_VAL + PLL new fraction divide input control active high + 12 + 1 + read-write + + + PLL_COUNTCLK_SEL + PLL maximum lock time counter clock select + 13 + 1 + read-write + + + PLL_COUNTCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_COUNTCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + + + PLL_BYPASS + PLL bypass control active high + 14 + 1 + read-write + + + PLL_LOCK_SEL + PLL Lock signal select + 15 + 1 + read-write + + + PLL_LOCK_SEL_0 + Select PLL lock output + 0 + + + PLL_LOCK_SEL_1 + Select maximum lock time counter output + 0x1 + + + + + PLL_REFCLK_SEL + PLL reference clocks select + 16 + 2 + read-write + + + PLL_REFCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_REFCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + PLL_REFCLK_SEL_2 + HDMI_PHY_27M_CLK + 0x2 + + + PLL_REFCLK_SEL_3 + CLK_P_N + 0x3 + + + + + PLL_PD_OVERRIDE + Override the PLL_PD, clock gating enable signal from CCM block active high + 18 + 1 + read-write + + + PLL_PD + PLL output clock clock gating enable active high + 19 + 1 + read-write + + + PLL_CLKE_OVERRIDE + Override the PLL_CLKE, clock gating enable signal from CCM block active high + 20 + 1 + read-write + + + PLL_CLKE + PLL output clock clock gating enable active high + 21 + 1 + read-write + + + PLL_LOCK + PLL lock status active high + 31 + 1 + read-only + + + + + GPU_PLL_CFG1 + GPU PLL Configuration 1 Register + 0x1C + 32 + read-write + 0x4F + 0xFFFFFFFF + + + PLL_INT_DIV_CTL + PLL Integer divide control Settings must maintain the PLL operational range + 0 + 7 + read-write + + + PLL_FRAC_DIV_CTL + PLL fraction divide control Settings must maintain the PLL operational range + 7 + 24 + read-write + + + + + VPU_PLL_CFG0 + VPU PLL Configuration 0 Register + 0x20 + 32 + read-write + 0x20C081 + 0xFFFFFFFF + + + PLL_OUTPUT_DIV_VAL + PLL output clock divide value Settings must maintain the PLL operational range + 0 + 5 + read-write + + + PLL_REFCLK_DIV_VAL + PLL reference clock divide value + 5 + 6 + read-write + + + PLL_NEWDIV_ACK + PLL new fraction divide handshake signal + 11 + 1 + read-only + + + PLL_NEWDIV_VAL + PLL new fraction divide input control active high + 12 + 1 + read-write + + + PLL_COUNTCLK_SEL + PLL maximum lock time counter clock select + 13 + 1 + read-write + + + PLL_COUNTCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_COUNTCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + + + PLL_BYPASS + PLL bypass control active high + 14 + 1 + read-write + + + PLL_LOCK_SEL + PLL Lock signal select + 15 + 1 + read-write + + + PLL_LOCK_SEL_0 + Select PLL lock output + 0 + + + PLL_LOCK_SEL_1 + Select maximum lock time counter output + 0x1 + + + + + PLL_REFCLK_SEL + PLL reference clocks select + 16 + 2 + read-write + + + PLL_REFCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_REFCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + PLL_REFCLK_SEL_2 + HDMI_PHY_27M_CLK + 0x2 + + + PLL_REFCLK_SEL_3 + CLK_P_N + 0x3 + + + + + PLL_PD_OVERRIDE + Override the PLL_PD, clock gating enable signal from CCM block active high + 18 + 1 + read-write + + + PLL_PD + PLL output clock clock gating enable active high + 19 + 1 + read-write + + + PLL_CLKE_OVERRIDE + Override the PLL_CLKE, clock gating enable signal from CCM block active high + 20 + 1 + read-write + + + PLL_CLKE + PLL output clock clock gating enable active high + 21 + 1 + read-write + + + PLL_LOCK + PLL lock status active high + 31 + 1 + read-only + + + + + VPU_PLL_CFG1 + VPU PLL Configuration 1 Register + 0x24 + 32 + read-write + 0x3B + 0xFFFFFFFF + + + PLL_INT_DIV_CTL + PLL Integer divide control Settings must maintain the PLL operational range + 0 + 7 + read-write + + + PLL_FRAC_DIV_CTL + PLL fraction divide control Settings must maintain the PLL operational range + 7 + 24 + read-write + + + + + ARM_PLL_CFG0 + ARM PLL Configuration 0 Register + 0x28 + 32 + read-write + 0x20C080 + 0xFFFFFFFF + + + PLL_OUTPUT_DIV_VAL + PLL output clock divide value Settings must maintain the PLL operational range + 0 + 5 + read-write + + + PLL_REFCLK_DIV_VAL + PLL reference clock divide value + 5 + 6 + read-write + + + PLL_NEWDIV_ACK + PLL new fraction divide handshake signal + 11 + 1 + read-only + + + PLL_NEWDIV_VAL + PLL new fraction divide input control active high + 12 + 1 + read-write + + + PLL_COUNTCLK_SEL + PLL maximum lock time counter clock select + 13 + 1 + read-write + + + PLL_COUNTCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_COUNTCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + + + PLL_BYPASS + PLL bypass control active high + 14 + 1 + read-write + + + PLL_LOCK_SEL + PLL Lock signal select + 15 + 1 + read-write + + + PLL_LOCK_SEL_0 + Select PLL lock output + 0 + + + PLL_LOCK_SEL_1 + Select maximum lock time counter output + 0x1 + + + + + PLL_REFCLK_SEL + PLL reference clocks select + 16 + 2 + read-write + + + PLL_REFCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_REFCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + PLL_REFCLK_SEL_2 + HDMI_PHY_27M_CLK + 0x2 + + + PLL_REFCLK_SEL_3 + CLK_P_N + 0x3 + + + + + PLL_PD_OVERRIDE + Override the PLL_PD, clock gating enable signal from CCM block active high + 18 + 1 + read-write + + + PLL_PD + PLL output clock clock gating enable active high + 19 + 1 + read-write + + + PLL_CLKE_OVERRIDE + Override the PLL_CLKE, clock gating enable signal from CCM block active high + 20 + 1 + read-write + + + PLL_CLKE + PLL output clock clock gating enable active high + 21 + 1 + read-write + + + PLL_LOCK + PLL lock status active high + 31 + 1 + read-only + + + + + ARM_PLL_CFG1 + ARM PLL Configuration 1 Register + 0x2C + 32 + read-write + 0x4F + 0xFFFFFFFF + + + PLL_INT_DIV_CTL + PLL Integer divide control Settings must maintain the PLL operational range + 0 + 7 + read-write + + + PLL_FRAC_DIV_CTL + PLL fraction divide control Settings must maintain the PLL operational range + 7 + 24 + read-write + + + + + SYS_PLL1_CFG0 + System PLL Configuration 0 Register + 0x30 + 32 + read-write + 0x2AAAA38 + 0xFFFFFFFF + + + PLL_REFCLK_SEL + PLL reference clocks select + 0 + 2 + read-write + + + PLL_REFCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_REFCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + PLL_REFCLK_SEL_2 + HDMI_PHY_27M_CLK + 0x2 + + + PLL_REFCLK_SEL_3 + CLK_P_N + 0x3 + + + + + PLL_COUNTCLK_SEL + PLL maximum lock time counter clock select + 2 + 1 + read-write + + + PLL_COUNTCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_COUNTCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + + + PLL_LOCK_SEL + PLL Lock signal select + 3 + 1 + read-write + + + PLL_LOCK_SEL_0 + Select PLL lock output + 0 + + + PLL_LOCK_SEL_1 + Select maximum lock time counter output + 0x1 + + + + + PLL_BYPASS2 + Internal PLL2 bypass control active high + 4 + 1 + read-write + + + PLL_BYPASS1 + Internal PLL1 bypass control active high + 5 + 1 + read-write + + + PLL_PD_OVERRIDE + Override the PLL_PD, clock gating enable signal from CCM block active high + 6 + 1 + read-write + + + PLL_PD + PLL output clock clock gating enable active high + 7 + 1 + read-write + + + PLL_DIV20_OVERRIDE + Override the PLL_DIV20_CLKE, clock gating enable signal from CCM block active high + 8 + 1 + read-write + + + PLL_DIV20_CLKE + PLL output clock divide by 20 clock gating enable active high + 9 + 1 + read-write + + + PLL_DIV10_OVERRIDE + Override the PLL_DIV10_CLKE, clock gating enable signal from CCM block active high + 10 + 1 + read-write + + + PLL_DIV10_CLKE + PLL output clock divide by 10 clock gating enable active high + 11 + 1 + read-write + + + PLL_DIV8_OVERRIDE + Override the PLL_DIV8_CLKE, clock gating enable signal from CCM block active high + 12 + 1 + read-write + + + PLL_DIV8_CLKE + PLL output clock divide by 8 clock gating enable active high + 13 + 1 + read-write + + + PLL_DIV6_OVERRIDE + Override the PLL_DIV6_CLKE, clock gating enable signal from CCM block active high + 14 + 1 + read-write + + + PLL_DIV6_CLKE + PLL output clock divide by 6 clock gating enable active high + 15 + 1 + read-write + + + PLL_DIV5_OVERRIDE + Override the PLL_DIV5_CLKE, clock gating enable signal from CCM block active high + 16 + 1 + read-write + + + PLL_DIV5_CLKE + PLL output clock divide by 5 clock gating enable active high + 17 + 1 + read-write + + + PLL_DIV4_OVERRIDE + Override the PLL_DIV4_CLKE, clock gating enable signal from CCM block active high + 18 + 1 + read-write + + + PLL_DIV4_CLKE + PLL output clock divide by 4 clock gating enable active high + 19 + 1 + read-write + + + PLL_DIV3_OVERRIDE + Override the PLL_DIV3_CLKE, clock gating enable signal from CCM block active high + 20 + 1 + read-write + + + PLL_DIV3_CLKE + PLL output clock divide by 3 clock gating enable active high + 21 + 1 + read-write + + + PLL_DIV2_OVERRIDE + Override the PLL_DIV2_CLKE, clock gating enable signal from CCM block active high + 22 + 1 + read-write + + + PLL_DIV2_CLKE + PLL output clock divide by 2 clock gating enable active high + 23 + 1 + read-write + + + PLL_CLKE_OVERRIDE + Override the PLL_CLKE, clock gating enable signal from CCM block active high + 24 + 1 + read-write + + + PLL_CLKE + PLL output clock clock gating enable active high + 25 + 1 + read-write + + + PLL_LOCK + PLL lock status active high + 31 + 1 + read-only + + + + + SYS_PLL1_CFG1 + System_PLL Configuration 1 Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PLL_SSE + Enables Spread Spectrum Mode active high + 0 + 1 + read-write + + + PLL_SSMF + Controls Spread Spectrum Modulation Frequency Fmod = SSMF[3:0]*2*Fvco1/251658 + 1 + 4 + read-write + + + PLL_SSMD + Controls Spread Spectrum modulation depth + 5 + 3 + read-write + + + PLL_SSMD_0 + 0.25 + 0 + + + PLL_SSMD_1 + 0.5 + 0x1 + + + PLL_SSMD_2 + 0.75 + 0x2 + + + PLL_SSMD_3 + 1.0 + 0x3 + + + PLL_SSMD_4 + 1.5 + 0x4 + + + PLL_SSMD_5 + 2.0 + 0x5 + + + PLL_SSMD_6 + 3.0 + 0x6 + + + PLL_SSMD_7 + 4.0 + 0x7 + + + + + PLL_SSDS + Selects between Spread Spectrum Center Spread and Down Spread Modes. + 8 + 1 + read-write + + + PLL_SSDS_0 + Center Spread + 0 + + + PLL_SSDS_1 + Down Spread + 0x1 + + + + + + + SYS_PLL1_CFG2 + System_PLL Configuration 2 Register + 0x38 + 32 + read-write + 0xBBE580 + 0xFFFFFFFF + + + PLL_FILTER_RANGE + This sets the internal PLL1 loop filter to work with the post-reference divider frequency. + 0 + 1 + read-write + + + PLL_FILTER_RANGE_0 + 25 to 35 MHz + 0 + + + PLL_FILTER_RANGE_1 + 35 to 54 MHz + 0x1 + + + + + PLL_OUTPUT_DIV_VAL + Internal PLL2 output clock divider value Fout must be within the range 20MHz ~ 1200MHz + 1 + 6 + read-write + + + PLL_FEEDBACK_DIVF2 + Internal PLL2 reference clock divider value + 7 + 6 + read-write + + + PLL_FEEDBACK_DIVF1 + Internal PLL1 reference clock divider value + 13 + 6 + read-write + + + PLL_REF_DIVR2 + Internal PLL2 reference clock divider value + 19 + 6 + read-write + + + PLL_REF_DIVR1 + Internal PLL1 reference clock divider value + 25 + 3 + read-write + + + + + SYS_PLL2_CFG0 + System PLL Configuration 0 Register + 0x3C + 32 + read-write + 0x2AAAA38 + 0xFFFFFFFF + + + PLL_REFCLK_SEL + PLL reference clocks select + 0 + 2 + read-write + + + PLL_REFCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_REFCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + PLL_REFCLK_SEL_2 + HDMI_PHY_27M_CLK + 0x2 + + + PLL_REFCLK_SEL_3 + CLK_P_N + 0x3 + + + + + PLL_COUNTCLK_SEL + PLL maximum lock time counter clock select + 2 + 1 + read-write + + + PLL_COUNTCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_COUNTCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + + + PLL_LOCK_SEL + PLL Lock signal select + 3 + 1 + read-write + + + PLL_LOCK_SEL_0 + Select PLL lock output + 0 + + + PLL_LOCK_SEL_1 + Select maximum lock time counter output + 0x1 + + + + + PLL_BYPASS2 + Internal PLL2 bypass control active high + 4 + 1 + read-write + + + PLL_BYPASS1 + Internal PLL1 bypass control active high + 5 + 1 + read-write + + + PLL_PD_OVERRIDE + Override the PLL_PD, clock gating enable signal from CCM block active high + 6 + 1 + read-write + + + PLL_PD + PLL output clock clock gating enable active high + 7 + 1 + read-write + + + PLL_DIV20_OVERRIDE + Override the PLL_DIV20_CLKE, clock gating enable signal from CCM block active high + 8 + 1 + read-write + + + PLL_DIV20_CLKE + PLL output clock divide by 20 clock gating enable active high + 9 + 1 + read-write + + + PLL_DIV10_OVERRIDE + Override the PLL_DIV10_CLKE, clock gating enable signal from CCM block active high + 10 + 1 + read-write + + + PLL_DIV10_CLKE + PLL output clock divide by 10 clock gating enable active high + 11 + 1 + read-write + + + PLL_DIV8_OVERRIDE + Override the PLL_DIV8_CLKE, clock gating enable signal from CCM block active high + 12 + 1 + read-write + + + PLL_DIV8_CLKE + PLL output clock divide by 8 clock gating enable active high + 13 + 1 + read-write + + + PLL_DIV6_OVERRIDE + Override the PLL_DIV6_CLKE, clock gating enable signal from CCM block active high + 14 + 1 + read-write + + + PLL_DIV6_CLKE + PLL output clock divide by 6 clock gating enable active high + 15 + 1 + read-write + + + PLL_DIV5_OVERRIDE + Override the PLL_DIV5_CLKE, clock gating enable signal from CCM block active high + 16 + 1 + read-write + + + PLL_DIV5_CLKE + PLL output clock divide by 5 clock gating enable active high + 17 + 1 + read-write + + + PLL_DIV4_OVERRIDE + Override the PLL_DIV4_CLKE, clock gating enable signal from CCM block active high + 18 + 1 + read-write + + + PLL_DIV4_CLKE + PLL output clock divide by 4 clock gating enable active high + 19 + 1 + read-write + + + PLL_DIV3_OVERRIDE + Override the PLL_DIV3_CLKE, clock gating enable signal from CCM block active high + 20 + 1 + read-write + + + PLL_DIV3_CLKE + PLL output clock divide by 3 clock gating enable active high + 21 + 1 + read-write + + + PLL_DIV2_OVERRIDE + Override the PLL_DIV2_CLKE, clock gating enable signal from CCM block active high + 22 + 1 + read-write + + + PLL_DIV2_CLKE + PLL output clock divide by 2 clock gating enable active high + 23 + 1 + read-write + + + PLL_CLKE_OVERRIDE + Override the PLL_CLKE, clock gating enable signal from CCM block active high + 24 + 1 + read-write + + + PLL_CLKE + PLL output clock clock gating enable active high + 25 + 1 + read-write + + + PLL_LOCK + PLL lock status active high + 31 + 1 + read-only + + + + + SYS_PLL2_CFG1 + System_PLL Configuration 1 Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + PLL_SSE + Enables Spread Spectrum Mode active high + 0 + 1 + read-write + + + PLL_SSMF + Controls Spread Spectrum Modulation Frequency Fmod = SSMF[3:0]*2*Fvco1/251658 + 1 + 4 + read-write + + + PLL_SSMD + Controls Spread Spectrum modulation depth + 5 + 3 + read-write + + + PLL_SSMD_0 + 0.25 + 0 + + + PLL_SSMD_1 + 0.5 + 0x1 + + + PLL_SSMD_2 + 0.75 + 0x2 + + + PLL_SSMD_3 + 1.0 + 0x3 + + + PLL_SSMD_4 + 1.5 + 0x4 + + + PLL_SSMD_5 + 2.0 + 0x5 + + + PLL_SSMD_6 + 3.0 + 0x6 + + + PLL_SSMD_7 + 4.0 + 0x7 + + + + + PLL_SSDS + Selects between Spread Spectrum Center Spread and Down Spread Modes. + 8 + 1 + read-write + + + PLL_SSDS_0 + Center Spread + 0 + + + PLL_SSDS_1 + Down Spread + 0x1 + + + + + + + SYS_PLL2_CFG2 + System_PLL Configuration 2 Register + 0x44 + 32 + read-write + 0xBBE700 + 0xFFFFFFFF + + + PLL_FILTER_RANGE + This sets the internal PLL1 loop filter to work with the post-reference divider frequency. + 0 + 1 + read-write + + + PLL_FILTER_RANGE_0 + 25 to 35 MHz + 0 + + + PLL_FILTER_RANGE_1 + 35 to 54 MHz + 0x1 + + + + + PLL_OUTPUT_DIV_VAL + Internal PLL2 output clock divider value Fout must be within the range 20MHz ~ 1200MHz + 1 + 6 + read-write + + + PLL_FEEDBACK_DIVF2 + Internal PLL2 reference clock divider value + 7 + 6 + read-write + + + PLL_FEEDBACK_DIVF1 + Internal PLL1 reference clock divider value + 13 + 6 + read-write + + + PLL_REF_DIVR2 + Internal PLL2 reference clock divider value + 19 + 6 + read-write + + + PLL_REF_DIVR1 + Internal PLL1 reference clock divider value + 25 + 3 + read-write + + + + + SYS_PLL3_CFG0 + System PLL Configuration 0 Register + 0x48 + 32 + read-write + 0x238 + 0xFFFFFFFF + + + PLL_REFCLK_SEL + PLL reference clocks select + 0 + 2 + read-write + + + PLL_REFCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_REFCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + PLL_REFCLK_SEL_2 + HDMI_PHY_27M_CLK + 0x2 + + + PLL_REFCLK_SEL_3 + CLK_P_N + 0x3 + + + + + PLL_COUNTCLK_SEL + PLL maximum lock time counter clock select + 2 + 1 + read-write + + + PLL_COUNTCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_COUNTCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + + + PLL_LOCK_SEL + PLL Lock signal select + 3 + 1 + read-write + + + PLL_LOCK_SEL_0 + Select PLL lock output + 0 + + + PLL_LOCK_SEL_1 + Select maximum lock time counter output + 0x1 + + + + + PLL_BYPASS2 + Internal PLL2 bypass control active high + 4 + 1 + read-write + + + PLL_BYPASS1 + Internal PLL1 bypass control active high + 5 + 1 + read-write + + + PLL_PD_OVERRIDE + Override the PLL_PD, clock gating enable signal from CCM block active high + 6 + 1 + read-write + + + PLL_PD + PLL output clock clock gating enable active high + 7 + 1 + read-write + + + PLL_DIV20_OVERRIDE + Override the PLL_DIV20_CLKE, clock gating enable signal from CCM block active high + 8 + 1 + read-write + + + PLL_DIV20_CLKE + PLL output clock divide by 20 clock gating enable active high + 9 + 1 + read-write + + + PLL_DIV10_OVERRIDE + Override the PLL_DIV10_CLKE, clock gating enable signal from CCM block active high + 10 + 1 + read-write + + + PLL_DIV10_CLKE + PLL output clock divide by 10 clock gating enable active high + 11 + 1 + read-write + + + PLL_DIV8_OVERRIDE + Override the PLL_DIV8_CLKE, clock gating enable signal from CCM block active high + 12 + 1 + read-write + + + PLL_DIV8_CLKE + PLL output clock divide by 8 clock gating enable active high + 13 + 1 + read-write + + + PLL_DIV6_OVERRIDE + Override the PLL_DIV6_CLKE, clock gating enable signal from CCM block active high + 14 + 1 + read-write + + + PLL_DIV6_CLKE + PLL output clock divide by 6 clock gating enable active high + 15 + 1 + read-write + + + PLL_DIV5_OVERRIDE + Override the PLL_DIV5_CLKE, clock gating enable signal from CCM block active high + 16 + 1 + read-write + + + PLL_DIV5_CLKE + PLL output clock divide by 5 clock gating enable active high + 17 + 1 + read-write + + + PLL_DIV4_OVERRIDE + Override the PLL_DIV4_CLKE, clock gating enable signal from CCM block active high + 18 + 1 + read-write + + + PLL_DIV4_CLKE + PLL output clock divide by 4 clock gating enable active high + 19 + 1 + read-write + + + PLL_DIV3_OVERRIDE + Override the PLL_DIV3_CLKE, clock gating enable signal from CCM block active high + 20 + 1 + read-write + + + PLL_DIV3_CLKE + PLL output clock divide by 3 clock gating enable active high + 21 + 1 + read-write + + + PLL_DIV2_OVERRIDE + Override the PLL_DIV2_CLKE, clock gating enable signal from CCM block active high + 22 + 1 + read-write + + + PLL_DIV2_CLKE + PLL output clock divide by 2 clock gating enable active high + 23 + 1 + read-write + + + PLL_CLKE_OVERRIDE + Override the PLL_CLKE, clock gating enable signal from CCM block active high + 24 + 1 + read-write + + + PLL_CLKE + PLL output clock clock gating enable active high + 25 + 1 + read-write + + + PLL_LOCK + PLL lock status active high + 31 + 1 + read-only + + + + + SYS_PLL3_CFG1 + System_PLL Configuration 1 Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + PLL_SSE + Enables Spread Spectrum Mode active high + 0 + 1 + read-write + + + PLL_SSMF + Controls Spread Spectrum Modulation Frequency Fmod = SSMF[3:0]*2*Fvco1/251658 + 1 + 4 + read-write + + + PLL_SSMD + Controls Spread Spectrum modulation depth + 5 + 3 + read-write + + + PLL_SSMD_0 + 0.25 + 0 + + + PLL_SSMD_1 + 0.5 + 0x1 + + + PLL_SSMD_2 + 0.75 + 0x2 + + + PLL_SSMD_3 + 1.0 + 0x3 + + + PLL_SSMD_4 + 1.5 + 0x4 + + + PLL_SSMD_5 + 2.0 + 0x5 + + + PLL_SSMD_6 + 3.0 + 0x6 + + + PLL_SSMD_7 + 4.0 + 0x7 + + + + + PLL_SSDS + Selects between Spread Spectrum Center Spread and Down Spread Modes. + 8 + 1 + read-write + + + PLL_SSDS_0 + Center Spread + 0 + + + PLL_SSDS_1 + Down Spread + 0x1 + + + + + + + SYS_PLL3_CFG2 + System_PLL Configuration 2 Register + 0x50 + 32 + read-write + 0xBBE700 + 0xFFFFFFFF + + + PLL_FILTER_RANGE + This sets the internal PLL1 loop filter to work with the post-reference divider frequency. + 0 + 1 + read-write + + + PLL_FILTER_RANGE_0 + 25 to 35 MHz + 0 + + + PLL_FILTER_RANGE_1 + 35 to 54 MHz + 0x1 + + + + + PLL_OUTPUT_DIV_VAL + Internal PLL2 output clock divider value Fout must be within the range 20MHz ~ 1200MHz + 1 + 6 + read-write + + + PLL_FEEDBACK_DIVF2 + Internal PLL2 reference clock divider value + 7 + 6 + read-write + + + PLL_FEEDBACK_DIVF1 + Internal PLL1 reference clock divider value + 13 + 6 + read-write + + + PLL_REF_DIVR2 + Internal PLL2 reference clock divider value + 19 + 6 + read-write + + + PLL_REF_DIVR1 + Internal PLL1 reference clock divider value + 25 + 3 + read-write + + + + + VIDEO_PLL2_CFG0 + VIDEO PLL2 Configuration 0 Register + 0x54 + 32 + read-write + 0x238 + 0xFFFFFFFF + + + PLL_REFCLK_SEL + PLL reference clocks select + 0 + 2 + read-write + + + PLL_REFCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_REFCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + PLL_REFCLK_SEL_2 + HDMI_PHY_27M_CLK + 0x2 + + + PLL_REFCLK_SEL_3 + CLK_P_N + 0x3 + + + + + PLL_COUNTCLK_SEL + PLL maximum lock time counter clock select + 2 + 1 + read-write + + + PLL_COUNTCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_COUNTCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + + + PLL_LOCK_SEL + PLL Lock signal select + 3 + 1 + read-write + + + PLL_LOCK_SEL_0 + Select PLL lock output + 0 + + + PLL_LOCK_SEL_1 + Select maximum lock time counter output + 0x1 + + + + + PLL_BYPASS2 + Internal PLL2 bypass control active high + 4 + 1 + read-write + + + PLL_BYPASS1 + Internal PLL1 bypass control active high + 5 + 1 + read-write + + + PLL_PD_OVERRIDE + Override the PLL_PD, clock gating enable signal from CCM block active high + 6 + 1 + read-write + + + PLL_PD + PLL output clock clock gating enable active high + 7 + 1 + read-write + + + PLL_CLKE_OVERRIDE + Override the PLL_CLKE, clock gating enable signal from CCM block active high + 8 + 1 + read-write + + + PLL_CLKE + PLL output clock clock gating enable active high + 9 + 1 + read-write + + + PLL_LOCK + PLL lock status active high + 31 + 1 + read-only + + + + + VIDEO_PLL2_CFG1 + VIDEO PLL2 Configuration 1 Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + PLL_SSE + Enables Spread Spectrum Mode active high + 0 + 1 + read-write + + + PLL_SSMF + Controls Spread Spectrum Modulation Frequency Fmod = SSMF[3:0]*2*Fvco1/251658 + 1 + 4 + read-write + + + PLL_SSMD + Controls Spread Spectrum modulation depth + 5 + 3 + read-write + + + PLL_SSMD_0 + 0.25 + 0 + + + PLL_SSMD_1 + 0.5 + 0x1 + + + PLL_SSMD_2 + 0.75 + 0x2 + + + PLL_SSMD_3 + 1.0 + 0x3 + + + PLL_SSMD_4 + 1.5 + 0x4 + + + PLL_SSMD_5 + 2.0 + 0x5 + + + PLL_SSMD_6 + 3.0 + 0x6 + + + PLL_SSMD_7 + 4.0 + 0x7 + + + + + PLL_SSDS + Selects between Spread Spectrum Center Spread and Down Spread Modes. + 8 + 1 + read-write + + + PLL_SSDS_0 + Center Spread + 0 + + + PLL_SSDS_1 + Down Spread + 0x1 + + + + + + + VIDEO_PLL2_CFG2 + VIDEO PLL2 Configuration 2 Register + 0x5C + 32 + read-write + 0xEC6480 + 0xFFFFFFFF + + + PLL_FILTER_RANGE + This sets the internal PLL1 loop filter to work with the post-reference divider frequency. + 0 + 1 + read-write + + + PLL_FILTER_RANGE_0 + 25 to 35 MHz + 0 + + + PLL_FILTER_RANGE_1 + 35 to 54 MHz + 0x1 + + + + + PLL_OUTPUT_DIV_VAL + Internal PLL2 output clock divider value Fout must be within the range 20MHz ~ 1200MHz + 1 + 6 + read-write + + + PLL_FEEDBACK_DIVF2 + Internal PLL2 reference clock divider value + 7 + 6 + read-write + + + PLL_FEEDBACK_DIVF1 + Internal PLL1 reference clock divider value + 13 + 6 + read-write + + + PLL_REF_DIVR2 + Internal PLL2 reference clock divider value + 19 + 6 + read-write + + + PLL_REF_DIVR1 + Internal PLL1 reference clock divider value + 25 + 3 + read-write + + + + + DRAM_PLL_CFG0 + DRAM PLL Configuration 0 Register + 0x60 + 32 + read-write + 0x238 + 0xFFFFFFFF + + + PLL_REFCLK_SEL + PLL reference clocks select + 0 + 2 + read-write + + + PLL_REFCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_REFCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + PLL_REFCLK_SEL_2 + HDMI_PHY_27M_CLK + 0x2 + + + PLL_REFCLK_SEL_3 + CLK_P_N + 0x3 + + + + + PLL_COUNTCLK_SEL + PLL maximum lock time counter clock select + 2 + 1 + read-write + + + PLL_COUNTCLK_SEL_0 + 25M_REF_CLK + 0 + + + PLL_COUNTCLK_SEL_1 + 27M_REF_CLK + 0x1 + + + + + PLL_LOCK_SEL + PLL Lock signal select + 3 + 1 + read-write + + + PLL_LOCK_SEL_0 + Select PLL lock output + 0 + + + PLL_LOCK_SEL_1 + Select maximum lock time counter output + 0x1 + + + + + PLL_BYPASS2 + Internal PLL2 bypass control active high + 4 + 1 + read-write + + + PLL_BYPASS1 + Internal PLL1 bypass control active high + 5 + 1 + read-write + + + PLL_PD_OVERRIDE + Override the PLL_PD, clock gating enable signal from CCM block active high + 6 + 1 + read-write + + + PLL_PD + PLL output clock clock gating enable active high + 7 + 1 + read-write + + + PLL_CLKE_OVERRIDE + Override the PLL_CLKE, clock gating enable signal from CCM block active high + 8 + 1 + read-write + + + PLL_CLKE + PLL output clock clock gating enable active high + 9 + 1 + read-write + + + PLL_LOCK + PLL lock status active high + 31 + 1 + read-only + + + + + DRAM_PLL_CFG1 + DRAM PLL Configuration 1 Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + PLL_SSE + Enables Spread Spectrum Mode active high + 0 + 1 + read-write + + + PLL_SSMF + Controls Spread Spectrum Modulation Frequency Fmod = SSMF[3:0]*2*Fvco1/251658 + 1 + 4 + read-write + + + PLL_SSMD + Controls Spread Spectrum modulation depth + 5 + 3 + read-write + + + PLL_SSMD_0 + 0.25 + 0 + + + PLL_SSMD_1 + 0.5 + 0x1 + + + PLL_SSMD_2 + 0.75 + 0x2 + + + PLL_SSMD_3 + 1.0 + 0x3 + + + PLL_SSMD_4 + 1.5 + 0x4 + + + PLL_SSMD_5 + 2.0 + 0x5 + + + PLL_SSMD_6 + 3.0 + 0x6 + + + PLL_SSMD_7 + 4.0 + 0x7 + + + + + PLL_SSDS + Selects between Spread Spectrum Center Spread and Down Spread Modes. + 8 + 1 + read-write + + + PLL_SSDS_0 + Center Spread + 0 + + + PLL_SSDS_1 + Down Spread + 0x1 + + + + + + + DRAM_PLL_CFG2 + DRAM PLL Configuration 2 Register + 0x68 + 32 + read-write + 0xBBE580 + 0xFFFFFFFF + + + PLL_FILTER_RANGE + This sets the internal PLL1 loop filter to work with the post-reference divider frequency. + 0 + 1 + read-write + + + PLL_FILTER_RANGE_0 + 25 to 35 MHz + 0 + + + PLL_FILTER_RANGE_1 + 35 to 54 MHz + 0x1 + + + + + PLL_OUTPUT_DIV_VAL + Internal PLL2 output clock divider value Fout must be within the range 20MHz ~ 1200MHz + 1 + 6 + read-write + + + PLL_FEEDBACK_DIVF2 + Internal PLL2 reference clock divider value + 7 + 6 + read-write + + + PLL_FEEDBACK_DIVF1 + Internal PLL1 reference clock divider value + 13 + 6 + read-write + + + PLL_REF_DIVR2 + Internal PLL2 reference clock divider value + 19 + 6 + read-write + + + PLL_REF_DIVR1 + Internal PLL1 reference clock divider value + 25 + 3 + read-write + + + + + DIGPROG + DIGPROG Register + 0x6C + 32 + read-only + 0x824010 + 0xFFFFFFFF + + + DIGPROG_MINOR + Bit[7:4] is the base layer revision, Bit[3:0] is the metal layer revision 0x10 stands for Tapeout 1 + 0 + 8 + read-only + + + DIGPROG_MAJOR_LOWER + Bit[7:4] is 0x4, stands for "Quad" Bit[3:0] is 0x0, stands for "Lite" + 8 + 8 + read-only + + + DIGPROG_MAJOR_UPPER + Bit[7:4] is 0x8, stands for "i.MX8" Bit[3:0] is 0x2, stands for "M" + 16 + 8 + read-only + + + + + OSC_MISC_CFG + Osc Misc Configuration Register + 0x70 + 32 + read-write + 0x14 + 0xFFFFFFFF + + + OSC_32K_SEL + 32KHz OSC input select + 0 + 1 + read-write + + + OSC_32K_SEL_0 + 25M_REF_CLK_DIV800 + 0 + + + OSC_32K_SEL_1 + RTC + 0x1 + + + + + OSC_25M_CLKE_OVERRIDE + Override the OSC_27M_CLKE, clock gating enable signal from CCM block active high + 1 + 1 + read-write + + + OSC_25M_CLKE + 25MHz OSC output clock gating enable active high + 2 + 1 + read-write + + + OSC_27M_CLKE_OVERRIDE + Override the OSC_27M_CLKE, clock gating enable signal from CCM block active high + 3 + 1 + read-write + + + OSC_27M_CLKE + 27MHz OSC output clock gating enable active high + 4 + 1 + read-write + + + + + PLLOUT_MONITOR_CFG + PLLOUT Monitor Configuration Register + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + PLLOUT_MONITOR_CLK_SEL + Clock monitor output clock + 0 + 4 + read-write + + + PLLOUT_MONITOR_CKE + Clock monitor output clock gating enable active high + 4 + 1 + read-write + + + + + FRAC_PLLOUT_DIV_CFG + Fractional PLLOUT Divider Configuration Register + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUDIO_PLL1_DIV_VAL + AUDIO PLL1 clock divider value, for test purpose. + 0 + 3 + read-write + + + AUDIO_PLL1_DIV_VAL_0 + Divide by 1 + 0 + + + AUDIO_PLL1_DIV_VAL_1 + Divide by 2 + 0x1 + + + AUDIO_PLL1_DIV_VAL_2 + Divide by 3 + 0x2 + + + AUDIO_PLL1_DIV_VAL_3 + Divide by 4 + 0x3 + + + AUDIO_PLL1_DIV_VAL_4 + Divide by 5 + 0x4 + + + AUDIO_PLL1_DIV_VAL_5 + Divide by 6 + 0x5 + + + AUDIO_PLL1_DIV_VAL_6 + Divide by 7 + 0x6 + + + AUDIO_PLL1_DIV_VAL_7 + Divide by 8 + 0x7 + + + + + AUDIO_PLL2_DIV_VAL + AUDIO PLL2 clock divider value, for test purpose. + 4 + 3 + read-write + + + AUDIO_PLL2_DIV_VAL_0 + Divide by 1 + 0 + + + AUDIO_PLL2_DIV_VAL_1 + Divide by 2 + 0x1 + + + AUDIO_PLL2_DIV_VAL_2 + Divide by 3 + 0x2 + + + AUDIO_PLL2_DIV_VAL_3 + Divide by 4 + 0x3 + + + AUDIO_PLL2_DIV_VAL_4 + Divide by 5 + 0x4 + + + AUDIO_PLL2_DIV_VAL_5 + Divide by 6 + 0x5 + + + AUDIO_PLL2_DIV_VAL_6 + Divide by 7 + 0x6 + + + AUDIO_PLL2_DIV_VAL_7 + Divide by 8 + 0x7 + + + + + VIDEO_PLL1_DIV_VAL + VIDEO PLL1 clock divider value, for test purpose. + 8 + 3 + read-write + + + VIDEO_PLL1_DIV_VAL_0 + Divide by 1 + 0 + + + VIDEO_PLL1_DIV_VAL_1 + Divide by 2 + 0x1 + + + VIDEO_PLL1_DIV_VAL_2 + Divide by 3 + 0x2 + + + VIDEO_PLL1_DIV_VAL_3 + Divide by 4 + 0x3 + + + VIDEO_PLL1_DIV_VAL_4 + Divide by 5 + 0x4 + + + VIDEO_PLL1_DIV_VAL_5 + Divide by 6 + 0x5 + + + VIDEO_PLL1_DIV_VAL_6 + Divide by 7 + 0x6 + + + VIDEO_PLL1_DIV_VAL_7 + Divide by 8 + 0x7 + + + + + GPU_PLL_DIV_VAL + GPU PLL clock divider value, for test purpose. + 12 + 3 + read-write + + + GPU_PLL_DIV_VAL_0 + Divide by 1 + 0 + + + GPU_PLL_DIV_VAL_1 + Divide by 2 + 0x1 + + + GPU_PLL_DIV_VAL_2 + Divide by 3 + 0x2 + + + GPU_PLL_DIV_VAL_3 + Divide by 4 + 0x3 + + + GPU_PLL_DIV_VAL_4 + Divide by 5 + 0x4 + + + GPU_PLL_DIV_VAL_5 + Divide by 6 + 0x5 + + + GPU_PLL_DIV_VAL_6 + Divide by 7 + 0x6 + + + GPU_PLL_DIV_VAL_7 + Divide by 8 + 0x7 + + + + + VPU_PLL_DIV_VAL + VPU PLL clock divider value, for test purpose. + 16 + 3 + read-write + + + VPU_PLL_DIV_VAL_0 + Divide by 1 + 0 + + + VPU_PLL_DIV_VAL_1 + Divide by 2 + 0x1 + + + VPU_PLL_DIV_VAL_2 + Divide by 3 + 0x2 + + + VPU_PLL_DIV_VAL_3 + Divide by 4 + 0x3 + + + VPU_PLL_DIV_VAL_4 + Divide by 5 + 0x4 + + + VPU_PLL_DIV_VAL_5 + Divide by 6 + 0x5 + + + VPU_PLL_DIV_VAL_6 + Divide by 7 + 0x6 + + + VPU_PLL_DIV_VAL_7 + Divide by 8 + 0x7 + + + + + ARM_PLL_DIV_VAL + ARM PLL clock divider value, for test purpose. + 20 + 3 + read-write + + + ARM_PLL_DIV_VAL_0 + Divide by 1 + 0 + + + ARM_PLL_DIV_VAL_1 + Divide by 2 + 0x1 + + + ARM_PLL_DIV_VAL_2 + Divide by 3 + 0x2 + + + ARM_PLL_DIV_VAL_3 + Divide by 4 + 0x3 + + + ARM_PLL_DIV_VAL_4 + Divide by 5 + 0x4 + + + ARM_PLL_DIV_VAL_5 + Divide by 6 + 0x5 + + + ARM_PLL_DIV_VAL_6 + Divide by 7 + 0x6 + + + ARM_PLL_DIV_VAL_7 + Divide by 8 + 0x7 + + + + + + + SCCG_PLLOUT_DIV_CFG + SCCG PLLOUT Divider Configuration Register + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + SYSTEM_PLL1_DIV_VAL + System PLL1 clock divider value, for test purpose. + 0 + 3 + read-write + + + SYSTEM_PLL1_DIV_VAL_0 + Divide by 1 + 0 + + + SYSTEM_PLL1_DIV_VAL_1 + Divide by 2 + 0x1 + + + SYSTEM_PLL1_DIV_VAL_2 + Divide by 3 + 0x2 + + + SYSTEM_PLL1_DIV_VAL_3 + Divide by 4 + 0x3 + + + SYSTEM_PLL1_DIV_VAL_4 + Divide by 5 + 0x4 + + + SYSTEM_PLL1_DIV_VAL_5 + Divide by 6 + 0x5 + + + SYSTEM_PLL1_DIV_VAL_6 + Divide by 7 + 0x6 + + + SYSTEM_PLL1_DIV_VAL_7 + Divide by 8 + 0x7 + + + + + SYSTEM_PLL2_DIV_VAL + System PLL2 clock divider value, for test purpose. + 4 + 3 + read-write + + + SYSTEM_PLL2_DIV_VAL_0 + Divide by 1 + 0 + + + SYSTEM_PLL2_DIV_VAL_1 + Divide by 2 + 0x1 + + + SYSTEM_PLL2_DIV_VAL_2 + Divide by 3 + 0x2 + + + SYSTEM_PLL2_DIV_VAL_3 + Divide by 4 + 0x3 + + + SYSTEM_PLL2_DIV_VAL_4 + Divide by 5 + 0x4 + + + SYSTEM_PLL2_DIV_VAL_5 + Divide by 6 + 0x5 + + + SYSTEM_PLL2_DIV_VAL_6 + Divide by 7 + 0x6 + + + SYSTEM_PLL2_DIV_VAL_7 + Divide by 8 + 0x7 + + + + + SYSTEM_PLL3_DIV_VAL + System PLL3 clock divider value, for test purpose. + 8 + 3 + read-write + + + SYSTEM_PLL3_DIV_VAL_0 + Divide by 1 + 0 + + + SYSTEM_PLL3_DIV_VAL_1 + Divide by 2 + 0x1 + + + SYSTEM_PLL3_DIV_VAL_2 + Divide by 3 + 0x2 + + + SYSTEM_PLL3_DIV_VAL_3 + Divide by 4 + 0x3 + + + SYSTEM_PLL3_DIV_VAL_4 + Divide by 5 + 0x4 + + + SYSTEM_PLL3_DIV_VAL_5 + Divide by 6 + 0x5 + + + SYSTEM_PLL3_DIV_VAL_6 + Divide by 7 + 0x6 + + + SYSTEM_PLL3_DIV_VAL_7 + Divide by 8 + 0x7 + + + + + DRAM_PLL_DIV_VAL + DRAM PLL clock divider value, for test purpose. + 12 + 3 + read-write + + + DRAM_PLL_DIV_VAL_0 + Divide by 1 + 0 + + + DRAM_PLL_DIV_VAL_1 + Divide by 2 + 0x1 + + + DRAM_PLL_DIV_VAL_2 + Divide by 3 + 0x2 + + + DRAM_PLL_DIV_VAL_3 + Divide by 4 + 0x3 + + + DRAM_PLL_DIV_VAL_4 + Divide by 5 + 0x4 + + + DRAM_PLL_DIV_VAL_5 + Divide by 6 + 0x5 + + + DRAM_PLL_DIV_VAL_6 + Divide by 7 + 0x6 + + + DRAM_PLL_DIV_VAL_7 + Divide by 8 + 0x7 + + + + + VIDEO_PLL2_DIV_VAL + VIDEO PLL2 clock divider value, for test purpose. + 16 + 3 + read-write + + + VIDEO_PLL2_DIV_VAL_0 + Divide by 1 + 0 + + + VIDEO_PLL2_DIV_VAL_1 + Divide by 2 + 0x1 + + + VIDEO_PLL2_DIV_VAL_2 + Divide by 3 + 0x2 + + + VIDEO_PLL2_DIV_VAL_3 + Divide by 4 + 0x3 + + + VIDEO_PLL2_DIV_VAL_4 + Divide by 5 + 0x4 + + + VIDEO_PLL2_DIV_VAL_5 + Divide by 6 + 0x5 + + + VIDEO_PLL2_DIV_VAL_6 + Divide by 7 + 0x6 + + + VIDEO_PLL2_DIV_VAL_7 + Divide by 8 + 0x7 + + + + + + + + + SNVS + SNVS + SNVS + 0x30370000 + + 0 + 0x10000 + registers + + + SNVS + 4 + + + SNVS_Consolidated + 19 + + + SNVS_Security + 20 + + + + HPLR + SNVS_HP Lock Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK_WSL + Zeroizable Master Key Write Soft Lock When set, prevents any writes (software and hardware) to the ZMK registers and the ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR + 0 + 1 + read-write + + + WRITE_ALLOWED + Write access is allowed + 0 + + + WRITE_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + ZMK_RSL + Zeroizable Master Key Read Soft Lock When set, prevents any software reads to the ZMK Registers and ZMK_ECC_VALUE field of the LPMKCR + 1 + 1 + read-write + + + READ_ALLOWED + Read access is allowed (only in software Programming mode) + 0 + + + READ_NOT_ALLOWED + Read access is not allowed + 0x1 + + + + + SRTC_SL + Secure Real Time Counter Soft Lock When set, prevents any writes to the SRTC Registers, SRTC_ENV, and SRTC_INV_EN bits + 2 + 1 + read-write + + + WRITE_ALLOWED + Write access is allowed + 0 + + + WRITE_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + LPCALB_SL + LP Calibration Soft Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) + 3 + 1 + read-write + + + WRITE_ALLOWED + Write access is allowed + 0 + + + WRITE_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + MC_SL + Monotonic Counter Soft Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit + 4 + 1 + read-write + + + WRITE_ALLOWED + Write access (increment) is allowed + 0 + + + WRITE_NOT_ALLOWED + Write access (increment) is not allowed + 0x1 + + + + + GPR_SL + General Purpose Register Soft Lock When set, prevents any writes to the GPR + 5 + 1 + read-write + + + WRITE_ALLOWED + Write access is allowed + 0 + + + WRITE_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + LPSVCR_SL + LP Security Violation Control Register Soft Lock When set, prevents any writes to the LPSVCR + 6 + 1 + read-write + + + LPSVCR_SL_0 + Write access is allowed + 0 + + + LPSVCR_SL_1 + Write access is not allowed + 0x1 + + + + + LPSECR_SL + LP Security Events Configuration Register Soft Lock When set, prevents any writes to the LPSECR + 8 + 1 + read-write + + + LPSECR_SL_0 + Write access is allowed + 0 + + + LPSECR_SL_1 + Write access is not allowed + 0x1 + + + + + MKS_SL + Master Key Select Soft Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LPMKCR + 9 + 1 + read-write + + + MKS_SL_0 + Write access is allowed + 0 + + + MKS_SL_1 + Write access is not allowed + 0x1 + + + + + HPSVCR_L + HP Security Violation Control Register Lock When set, prevents any writes to the HPSVCR + 16 + 1 + read-write + + + HPSVCR_L_0 + Write access is allowed + 0 + + + HPSVCR_L_1 + Write access is not allowed + 0x1 + + + + + HPSICR_L + HP Security Interrupt Control Register Lock When set, prevents any writes to the HPSICR + 17 + 1 + read-write + + + HPSICR_L_0 + Write access is allowed + 0 + + + HPSICR_L_1 + Write access is not allowed + 0x1 + + + + + HAC_L + High Assurance Counter Lock When set, prevents any writes to HPHACIVR, HPHACR, and HAC_EN bit of HPCOMR + 18 + 1 + read-write + + + HAC_L_0 + Write access is allowed + 0 + + + HAC_L_1 + Write access is not allowed + 0x1 + + + + + + + HPCOMR + SNVS_HP Command Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSM_ST + SSM State Transition Transition state of the system security monitor + 0 + 1 + write-only + + + SSM_ST_DIS + SSM Secure to Trusted State Transition Disable When set, disables the SSM transition from secure to trusted state + 1 + 1 + read-write + + + SSM_ST_DIS_0 + Secure to Trusted State transition is enabled + 0 + + + SSM_ST_DIS_1 + Secure to Trusted State transition is disabled + 0x1 + + + + + SSM_SFNS_DIS + SSM Soft Fail to Non-Secure State Transition Disable When set, it disables the SSM transition from soft fail to non-secure state + 2 + 1 + read-write + + + SSM_SFNS_DIS_0 + Soft Fail to Non-Secure State transition is enabled + 0 + + + SSM_SFNS_DIS_1 + Soft Fail to Non-Secure State transition is disabled + 0x1 + + + + + LP_SWR + LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set + 4 + 1 + write-only + + + LP_SWR_0 + No Action + 0 + + + LP_SWR_1 + Reset LP section + 0x1 + + + + + LP_SWR_DIS + LP Software Reset Disable When set, disables the LP software reset + 5 + 1 + read-write + + + LP_SWR_DIS_0 + LP software reset is enabled + 0 + + + LP_SWR_DIS_1 + LP software reset is disabled + 0x1 + + + + + SW_SV + Software Security Violation When set, the system security monitor treats this bit as a non-fatal security violation + 8 + 1 + read-write + + + SW_FSV + Software Fatal Security Violation When set, the system security monitor treats this bit as a fatal security violation + 9 + 1 + read-write + + + SW_LPSV + LP Software Security Violation When set, SNVS_LP treats this bit as a security violation + 10 + 1 + read-write + + + PROG_ZMK + Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism + 12 + 1 + write-only + + + PROG_ZMK_0 + No Action + 0 + + + PROG_ZMK_1 + Activate hardware key programming mechanism + 0x1 + + + + + MKS_EN + Master Key Select Enable When not set, the one time programmable (OTP) master key is selected by default + 13 + 1 + read-write + + + MKS_EN_0 + no description available + 0 + + + MKS_EN_1 + no description available + 0x1 + + + + + HAC_EN + High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state + 16 + 1 + read-write + + + HAC_EN_0 + High Assurance Counter is disabled + 0 + + + HAC_EN_1 + High Assurance Counter is enabled + 0x1 + + + + + HAC_LOAD + High Assurance Counter Load When set, it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register + 17 + 1 + write-only + + + HAC_LOAD_0 + No Action + 0 + + + HAC_LOAD_1 + Load the HAC + 0x1 + + + + + HAC_CLEAR + High Assurance Counter Clear When set, it clears the High Assurance Counter Register + 18 + 1 + write-only + + + HAC_CLEAR_0 + No Action + 0 + + + HAC_CLEAR_1 + Clear the HAC + 0x1 + + + + + HAC_STOP + High Assurance Counter Stop This bit can be set only when SSM is in soft fail state + 19 + 1 + read-write + + + NPSWA_EN + Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only + 31 + 1 + read-write + + + + + HPCR + SNVS_HP Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC_EN + HP Real Time Counter Enable + 0 + 1 + read-write + + + RTC_EN_0 + RTC is disabled + 0 + + + RTC_EN_1 + RTC is enabled + 0x1 + + + + + HPTA_EN + HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter + 1 + 1 + read-write + + + HPTA_EN_0 + HP Time Alarm Interrupt is disabled + 0 + + + HPTA_EN_1 + HP Time Alarm Interrupt is enabled + 0x1 + + + + + DIS_PI + Disable periodic interrupt in the functional interrupt + 2 + 1 + read-write + + + DIS_PI_0 + Periodic interrupt will trigger a functional interrupt + 0 + + + DIS_PI_1 + Disable periodic interrupt in the function interrupt + 0x1 + + + + + PI_EN + HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled + 3 + 1 + read-write + + + PI_EN_0 + HP Periodic Interrupt is disabled + 0 + + + PI_EN_1 + HP Periodic Interrupt is enabled + 0x1 + + + + + PI_FREQ + Periodic Interrupt Frequency Defines frequency of the periodic interrupt + 4 + 4 + read-write + + + PI_FREQ_0 + - bit 0 of the HPRTCLR is selected as a source of the periodic interrupt + 0 + + + PI_FREQ_1 + - bit 1 of the HPRTCLR is selected as a source of the periodic interrupt + 0x1 + + + PI_FREQ_2 + - bit 2 of the HPRTCLR is selected as a source of the periodic interrupt + 0x2 + + + PI_FREQ_3 + - bit 3 of the HPRTCLR is selected as a source of the periodic interrupt + 0x3 + + + PI_FREQ_4 + - bit 4 of the HPRTCLR is selected as a source of the periodic interrupt + 0x4 + + + PI_FREQ_5 + - bit 5 of the HPRTCLR is selected as a source of the periodic interrupt + 0x5 + + + PI_FREQ_6 + - bit 6 of the HPRTCLR is selected as a source of the periodic interrupt + 0x6 + + + PI_FREQ_7 + - bit 7 of the HPRTCLR is selected as a source of the periodic interrupt + 0x7 + + + PI_FREQ_8 + - bit 8 of the HPRTCLR is selected as a source of the periodic interrupt + 0x8 + + + PI_FREQ_9 + - bit 9 of the HPRTCLR is selected as a source of the periodic interrupt + 0x9 + + + PI_FREQ_10 + - bit 10 of the HPRTCLR is selected as a source of the periodic interrupt + 0xA + + + PI_FREQ_11 + - bit 11 of the HPRTCLR is selected as a source of the periodic interrupt + 0xB + + + PI_FREQ_12 + - bit 12 of the HPRTCLR is selected as a source of the periodic interrupt + 0xC + + + PI_FREQ_13 + - bit 13 of the HPRTCLR is selected as a source of the periodic interrupt + 0xD + + + PI_FREQ_14 + - bit 14 of the HPRTCLR is selected as a source of the periodic interrupt + 0xE + + + PI_FREQ_15 + - bit 15 of the HPRTCLR is selected as a source of the periodic interrupt + 0xF + + + + + HPCALB_EN + HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled. + 8 + 1 + read-write + + + HPCALB_EN_0 + HP Timer calibration disabled + 0 + + + HPCALB_EN_1 + HP Timer calibration enabled + 0x1 + + + + + HPCALB_VAL + HP Calibration Value Defines signed calibration value for the HP Real Time Counter + 10 + 5 + read-write + + + HPCALB_VAL_0 + +0 counts per each 32768 ticks of the counter + 0 + + + HPCALB_VAL_1 + +1 counts per each 32768 ticks of the counter + 0x1 + + + HPCALB_VAL_2 + +2 counts per each 32768 ticks of the counter + 0x2 + + + HPCALB_VAL_15 + +15 counts per each 32768 ticks of the counter + 0xF + + + HPCALB_VAL_16 + -16 counts per each 32768 ticks of the counter + 0x10 + + + HPCALB_VAL_17 + -15 counts per each 32768 ticks of the counter + 0x11 + + + HPCALB_VAL_30 + -2 counts per each 32768 ticks of the counter + 0x1E + + + HPCALB_VAL_31 + -1 counts per each 32768 ticks of the counter + 0x1F + + + + + HP_TS + HP Time Synchronize + 16 + 1 + read-write + + + HP_TS_0 + No Action + 0 + + + HP_TS_1 + Synchronize the HP Time Counter to the LP Time Counter + 0x1 + + + + + BTN_CONFIG + Button Configuration + 24 + 3 + read-write + + + BTN_MASK + Button interrupt mask + 27 + 1 + read-write + + + + + HPSICR + SNVS_HP Security Interrupt Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_EN + Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation + 0 + 1 + read-write + + + SV0_EN_0 + Security Violation 0 Interrupt is Disabled + 0 + + + SV0_EN_1 + Security Violation 0 Interrupt is Enabled + 0x1 + + + + + SV1_EN + Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation + 1 + 1 + read-write + + + SV1_EN_0 + Security Violation 1 Interrupt is Disabled + 0 + + + SV1_EN_1 + Security Violation 1 Interrupt is Enabled + 0x1 + + + + + SV2_EN + Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation + 2 + 1 + read-write + + + SV2_EN_0 + Security Violation 2 Interrupt is Disabled + 0 + + + SV2_EN_1 + Security Violation 2 Interrupt is Enabled + 0x1 + + + + + SV3_EN + Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation + 3 + 1 + read-write + + + SV3_EN_0 + Security Violation 3 Interrupt is Disabled + 0 + + + SV3_EN_1 + Security Violation 3 Interrupt is Enabled + 0x1 + + + + + SV4_EN + Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation + 4 + 1 + read-write + + + SV4_EN_0 + Security Violation 4 Interrupt is Disabled + 0 + + + SV4_EN_1 + Security Violation 4 Interrupt is Enabled + 0x1 + + + + + SV5_EN + Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation + 5 + 1 + read-write + + + SV5_EN_0 + Security Violation 5 Interrupt is Disabled + 0 + + + SV5_EN_1 + Security Violation 5 Interrupt is Enabled + 0x1 + + + + + LPSVI_EN + LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section + 31 + 1 + read-write + + + LPSVI_EN_0 + LP Security Violation Interrupt is Disabled + 0 + + + LPSVI_EN_1 + LP Security Violation Interrupt is Enabled + 0x1 + + + + + + + HPSVCR + SNVS_HP Security Violation Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_CFG + Security Violation 0 Security Violation Configuration This field configures the Security Violation 0 Security Violation Input + 0 + 1 + read-write + + + SV0_CFG_0 + Security Violation 0 is a non-fatal violation + 0 + + + SV0_CFG_1 + Security Violation 0 is a fatal violation + 0x1 + + + + + SV1_CFG + Security Violation 1 Security Violation Configuration This field configures the Security Violation 1 Security Violation Input + 1 + 1 + read-write + + + SV1_CFG_0 + Security Violation 1 is a non-fatal violation + 0 + + + SV1_CFG_1 + Security Violation 1 is a fatal violation + 0x1 + + + + + SV2_CFG + Security Violation 2 Security Violation Configuration This field configures the Security Violation 2 Security Violation Input + 2 + 1 + read-write + + + SV2_CFG_0 + Security Violation 2 is a non-fatal violation + 0 + + + SV2_CFG_1 + Security Violation 2 is a fatal violation + 0x1 + + + + + SV3_CFG + Security Violation 3 Security Violation Configuration This field configures the Security Violation 3 Security Violation Input + 3 + 1 + read-write + + + SV3_CFG_0 + Security Violation 3 is a non-fatal violation + 0 + + + SV3_CFG_1 + Security Violation 3 is a fatal violation + 0x1 + + + + + SV4_CFG + Security Violation 4 Security Violation Configuration This field configures the Security Violation 4 Security Violation Input + 4 + 1 + read-write + + + SV4_CFG_0 + Security Violation 4 is a non-fatal violation + 0 + + + SV4_CFG_1 + Security Violation 4 is a fatal violation + 0x1 + + + + + SV5_CFG + Security Violation 5 Security Violation Configuration This field configures the Security Violation 5 Security Violation Input + 5 + 2 + read-write + + + SV5_CFG_0 + Security Violation 5 is disabled + 0 + + + SV5_CFG_1 + Security Violation 5 is a non-fatal violation + 0x1 + + + SV5_CFG_2 + Security Violation 5 is a fatal violation + #1x + + + + + LPSV_CFG + LP Security Violation Configuration This field configures the LP security violation source. + 30 + 2 + read-write + + + LPSV_CFG_0 + LP security violation is disabled + 0 + + + LPSV_CFG_1 + LP security violation is a non-fatal violation + 0x1 + + + LPSV_CFG_2 + LP security violation is a fatal violation + #1x + + + + + + + HPSR + SNVS_HP Status Register + 0x14 + 32 + read-write + 0x80003000 + 0xFFFFFFFF + + + HPTA + HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared. + 0 + 1 + read-write + oneToClear + + + HPTA_0 + No time alarm interrupt occurred. + 0 + + + HPTA_1 + A time alarm interrupt occurred. + 0x1 + + + + + PI + Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared. + 1 + 1 + read-write + oneToClear + + + PI_0 + No periodic interrupt occurred. + 0 + + + PI_1 + A periodic interrupt occurred. + 0x1 + + + + + LPDIS + Low Power Disable If 1, the low power section has been disabled by means of an input signal to SNVS + 4 + 1 + read-only + + + BTN + Button Value of the BTN input + 6 + 1 + read-only + + + BI + Button Interrupt Signal ipi_snvs_btn_int_b was asserted. + 7 + 1 + read-write + oneToClear + + + SSM_STATE + System Security Monitor State This field contains the encoded state of the SSM's state machine + 8 + 4 + read-only + + + SSM_STATE_0 + Init + 0 + + + SSM_STATE_1 + Hard Fail + 0x1 + + + SSM_STATE_3 + Soft Fail + 0x3 + + + SSM_STATE_8 + Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) + 0x8 + + + SSM_STATE_9 + Check + 0x9 + + + SSM_STATE_11 + Non-Secure + 0xB + + + SSM_STATE_13 + Trusted + 0xD + + + SSM_STATE_15 + Secure + 0xF + + + + + SECURITY_CONFIG + Security Configuration This field reflects the settings of the sys_secure_boot input and the three security configuration inputs to SNVS + 12 + 4 + read-only + + + FAB_CONFIG + FAB configuration + 0 + + + OPEN_CONFIG + OPEN configuration + 0x1 + + + OPEN_CONFIG + OPEN configuration + 0x2 + + + OPEN_CONFIG + OPEN configuration + 0x3 + + + FIELD_RETURN_CONFIG + FIELD RETURN configuration + #x1xx + + + FAB_CONFIG + FAB configuration + 0x8 + + + CLOSED_CONFIG + CLOSED configuration + 0x9 + + + CLOSED_CONFIG + CLOSED configuration + 0xA + + + CLOSED_CONFIG + CLOSED configuration + 0xB + + + + + OTPMK_SYNDROME + One Time Programmable Master Key Syndrome In the case of a single-bit error, the eight lower bits of this value indicate the bit number of error location + 16 + 9 + read-only + + + OTPMK_ZERO + One Time Programmable Master Key is Equal to Zero + 27 + 1 + read-only + + + OTPMK_ZERO_0 + The OTPMK is not zero. + 0 + + + OTPMK_ZERO_1 + The OTPMK is zero. + 0x1 + + + + + ZMK_ZERO + Zeroizable Master Key is Equal to Zero + 31 + 1 + read-only + + + ZMK_ZERO_0 + The ZMK is not zero. + 0 + + + ZMK_ZERO_1 + The ZMK is zero. + 0x1 + + + + + + + HPSVSR + SNVS_HP Security Violation Status Register + 0x18 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + SV0 + Security Violation 0 security violation was detected. + 0 + 1 + read-write + oneToClear + + + SV0_0 + No Security Violation 0 security violation was detected. + 0 + + + SV0_1 + Security Violation 0 security violation was detected. + 0x1 + + + + + SV1 + Security Violation 1 security violation was detected. + 1 + 1 + read-write + oneToClear + + + SV1_0 + No Security Violation 1 security violation was detected. + 0 + + + SV1_1 + Security Violation 1 security violation was detected. + 0x1 + + + + + SV2 + Security Violation 2 security violation was detected. + 2 + 1 + read-write + oneToClear + + + SV2_0 + No Security Violation 2 security violation was detected. + 0 + + + SV2_1 + Security Violation 2 security violation was detected. + 0x1 + + + + + SV3 + Security Violation 3 security violation was detected. + 3 + 1 + read-write + oneToClear + + + SV3_0 + No Security Violation 3 security violation was detected. + 0 + + + SV3_1 + Security Violation 3 security violation was detected. + 0x1 + + + + + SV4 + Security Violation 4 security violation was detected. + 4 + 1 + read-write + oneToClear + + + SV4_0 + No Security Violation 4 security violation was detected. + 0 + + + SV4_1 + Security Violation 4 security violation was detected. + 0x1 + + + + + SV5 + Security Violation 5 security violation was detected. + 5 + 1 + read-write + oneToClear + + + SV5_0 + No Security Violation 5 security violation was detected. + 0 + + + SV5_1 + Security Violation 5 security violation was detected. + 0x1 + + + + + SW_SV + Software Security Violation This bit is a read-only copy of the SW_SV bit in the HP Command Register + 13 + 1 + read-only + + + SW_FSV + Software Fatal Security Violation This bit is a read-only copy of the SW_FSV bit in the HP Command Register + 14 + 1 + read-only + + + SW_LPSV + LP Software Security Violation This bit is a read-only copy of the SW_LPSV bit in the HP Command Register + 15 + 1 + read-only + + + ZMK_SYNDROME + Zeroizable Master Key Syndrome The ZMK syndrome indicates the single-bit error location and parity for the ZMK register + 16 + 9 + read-only + + + ZMK_ECC_FAIL + Zeroizable Master Key Error Correcting Code Check Failure When set, this bit triggers a bad key violation to the SSM and a security violation to the SNVS_LP section, which clears security sensitive data + 27 + 1 + read-write + oneToClear + + + ZMK_ECC_FAIL_0 + ZMK ECC Failure was not detected. + 0 + + + ZMK_ECC_FAIL_1 + ZMK ECC Failure was detected. + 0x1 + + + + + LP_SEC_VIO + LP Security Violation A security volation was detected in the SNVS low power section. + 31 + 1 + read-only + + + + + HPHACIVR + SNVS_HP High Assurance Counter IV Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + HAC_COUNTER_IV + High Assurance Counter Initial Value This register is used to set the starting count value to the high assurance counter + 0 + 32 + read-write + + + + + HPHACR + SNVS_HP High Assurance Counter Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + HAC_COUNTER + High Assurance Counter When the HAC_EN bit is set and the SSM is in the soft fail state, this counter starts to count down with the system clock + 0 + 32 + read-only + + + + + HPRTCMR + SNVS_HP Real Time Counter MSB Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real Time Counter The most-significant 15 bits of the RTC + 0 + 15 + read-write + + + + + HPRTCLR + SNVS_HP Real Time Counter LSB Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real Time Counter least-significant 32 bits + 0 + 32 + read-write + + + + + HPTAMR + SNVS_HP Time Alarm MSB Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA_MS + HP Time Alarm, most-significant 15 bits + 0 + 15 + read-write + + + + + HPTALR + SNVS_HP Time Alarm LSB Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA_LS + HP Time Alarm, 32 least-significant bits + 0 + 32 + read-write + + + + + LPLR + SNVS_LP Lock Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK_WHL + Zeroizable Master Key Write Hard Lock When set, prevents any writes (software and hardware) to the ZMK registers and ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR + 0 + 1 + read-write + + + ZMK_WHL_0 + Write access is allowed. + 0 + + + ZMK_WHL_1 + Write access is not allowed. + 0x1 + + + + + ZMK_RHL + Zeroizable Master Key Read Hard Lock When set, prevents any software reads to the ZMK registers and ZMK_ECC_VALUE field of the LPMKCR + 1 + 1 + read-write + + + ZMK_RHL_0 + Read access is allowed (only in software programming mode). + 0 + + + ZMK_RHL_1 + Read access is not allowed. + 0x1 + + + + + SRTC_HL + Secure Real Time Counter Hard Lock When set, prevents any writes to the SRTC registers, SRTC_ENV, and SRTC_INV_EN bits + 2 + 1 + read-write + + + SRTC_HL_0 + Write access is allowed. + 0 + + + SRTC_HL_1 + Write access is not allowed. + 0x1 + + + + + LPCALB_HL + LP Calibration Hard Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) + 3 + 1 + read-write + + + LPCALB_HL_0 + Write access is allowed. + 0 + + + LPCALB_HL_1 + Write access is not allowed. + 0x1 + + + + + MC_HL + Monotonic Counter Hard Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit + 4 + 1 + read-write + + + MC_HL_0 + Write access (increment) is allowed. + 0 + + + MC_HL_1 + Write access (increment) is not allowed. + 0x1 + + + + + GPR_HL + General Purpose Register Hard Lock When set, prevents any writes to the GPR + 5 + 1 + read-write + + + GPR_HL_0 + Write access is allowed. + 0 + + + GPR_HL_1 + Write access is not allowed. + 0x1 + + + + + LPSVCR_HL + LP Security Violation Control Register Hard Lock When set, prevents any writes to the LPSVCR + 6 + 1 + read-write + + + LPSVCR_HL_0 + Write access is allowed. + 0 + + + LPSVCR_HL_1 + Write access is not allowed. + 0x1 + + + + + LPSECR_HL + LP Security Events Configuration Register Hard Lock When set, prevents any writes to the LPSECR + 8 + 1 + read-write + + + LPSECR_HL_0 + Write access is allowed. + 0 + + + LPSECR_HL_1 + Write access is not allowed. + 0x1 + + + + + MKS_HL + Master Key Select Hard Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LP Master Key Control Register + 9 + 1 + read-write + + + MKS_HL_0 + Write access is allowed. + 0 + + + MKS_HL_1 + Write access is not allowed. + 0x1 + + + + + + + LPCR + SNVS_LP Control Register + 0x38 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + SRTC_ENV + Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational + 0 + 1 + read-write + + + SRTC_ENV_0 + SRTC is disabled or invalid. + 0 + + + SRTC_ENV_1 + SRTC is enabled and valid. + 0x1 + + + + + LPTA_EN + LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter + 1 + 1 + read-write + + + LPTA_EN_0 + LP time alarm interrupt is disabled. + 0 + + + LPTA_EN_1 + LP time alarm interrupt is enabled. + 0x1 + + + + + MC_ENV + Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR) + 2 + 1 + read-write + + + MC_ENV_0 + MC is disabled or invalid. + 0 + + + MC_ENV_1 + MC is enabled and valid. + 0x1 + + + + + LPWUI_EN + LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (MC rollover, SRTC rollover, or time alarm ) + 3 + 1 + read-write + + + SRTC_INV_EN + If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared) + 4 + 1 + read-write + + + SRTC_INV_EN_0 + SRTC stays valid in the case of security violation. + 0 + + + SRTC_INV_EN_1 + SRTC is invalidated in the case of security violation. + 0x1 + + + + + DP_EN + Dumb PMIC Enabled When set, software can control the system power + 5 + 1 + read-write + + + DP_EN_0 + Smart PMIC enabled. + 0 + + + DP_EN_1 + Dumb PMIC enabled. + 0x1 + + + + + TOP + Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power + 6 + 1 + read-write + + + TOP_0 + Leave system power on. + 0 + + + TOP_1 + Turn off system power. + 0x1 + + + + + PWR_GLITCH_EN + Power Glitch Enable By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted + 7 + 1 + read-write + + + LPCALB_EN + LP Calibration Enable When set, enables the SRTC calibration mechanism + 8 + 1 + read-write + + + LPCALB_EN_0 + SRTC Time calibration is disabled. + 0 + + + LPCALB_EN_1 + SRTC Time calibration is enabled. + 0x1 + + + + + LPCALB_VAL + LP Calibration Value Defines signed calibration value for SRTC + 10 + 5 + read-write + + + LPCALB_VAL_0 + +0 counts per each 32768 ticks of the counter clock + 0 + + + LPCALB_VAL_1 + +1 counts per each 32768 ticks of the counter clock + 0x1 + + + LPCALB_VAL_2 + +2 counts per each 32768 ticks of the counter clock + 0x2 + + + LPCALB_VAL_15 + +15 counts per each 32768 ticks of the counter clock + 0xF + + + LPCALB_VAL_16 + -16 counts per each 32768 ticks of the counter clock + 0x10 + + + LPCALB_VAL_17 + -15 counts per each 32768 ticks of the counter clock + 0x11 + + + LPCALB_VAL_30 + -2 counts per each 32768 ticks of the counter clock + 0x1E + + + LPCALB_VAL_31 + -1 counts per each 32768 ticks of the counter clock + 0x1F + + + + + BTN_PRESS_TIME + This field configures the button press time out values for the PMIC Logic + 16 + 2 + read-write + + + DEBOUNCE + This field configures the amount of debounce time for the BTN input signal + 18 + 2 + read-write + + + ON_TIME + The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power + 20 + 2 + read-write + + + PK_EN + PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en + 22 + 1 + read-write + + + PK_OVERRIDE + PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override + 23 + 1 + read-write + + + GPR_Z_DIS + General Purpose Registers Zeroization Disable + 24 + 1 + read-write + + + + + LPMKCR + SNVS_LP Master Key Control Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + MASTER_KEY_SEL + Master Key Select These bits select the SNVS Master Key output when Master Key Select bits are enabled by MKS_EN bit in the HPCOMR + 0 + 2 + read-write + + + MASTER_KEY_SEL_0 + Select one time programmable master key. + #0x + + + MASTER_KEY_SEL_2 + no description available + 0x2 + + + MASTER_KEY_SEL_3 + no description available + 0x3 + + + + + ZMK_HWP + Zeroizable Master Key hardware Programming mode When set, only the hardware key programming mechanism can set the ZMK and software cannot read it + 2 + 1 + read-write + + + ZMK_HWP_0 + ZMK is in the software programming mode. + 0 + + + ZMK_HWP_1 + ZMK is in the hardware programming mode. + 0x1 + + + + + ZMK_VAL + Zeroizable Master Key Valid When set, the ZMK value can be selected by the master key control block for use by cryptographic modules + 3 + 1 + read-write + + + ZMK_VAL_0 + ZMK is not valid. + 0 + + + ZMK_VAL_1 + ZMK is valid. + 0x1 + + + + + ZMK_ECC_EN + Zeroizable Master Key Error Correcting Code Check Enable Writing one to this field automatically calculates and sets the ZMK ECC value in the ZMK_ECC_VALUE field of this register + 4 + 1 + read-write + + + ZMK_ECC_EN_0 + ZMK ECC check is disabled. + 0 + + + ZMK_ECC_EN_1 + ZMK ECC check is enabled. + 0x1 + + + + + ZMK_ECC_VALUE + Zeroizable Master Key Error Correcting Code Value This field is automatically calculated and set when one is written into ZMK_ECC_EN bit of this register + 7 + 9 + read-only + + + + + LPSVCR + SNVS_LP Security Violation Control Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_EN + Security Violation 0 Enable This bit enables Security Violation 0 Input + 0 + 1 + read-write + + + SV0_EN_0 + Security Violation 0 is disabled in the LP domain. + 0 + + + SV0_EN_1 + Security Violation 0 is enabled in the LP domain. + 0x1 + + + + + SV1_EN + Security Violation 1 Enable This bit enables Security Violation 1 Input + 1 + 1 + read-write + + + SV1_EN_0 + Security Violation 1 is disabled in the LP domain. + 0 + + + SV1_EN_1 + Security Violation 1 is enabled in the LP domain. + 0x1 + + + + + SV2_EN + Security Violation 2 Enable This bit enables Security Violation 2 Input + 2 + 1 + read-write + + + SV2_EN_0 + Security Violation 2 is disabled in the LP domain. + 0 + + + SV2_EN_1 + Security Violation 2 is enabled in the LP domain. + 0x1 + + + + + SV3_EN + Security Violation 3 Enable This bit enables Security Violation 3 Input + 3 + 1 + read-write + + + SV3_EN_0 + Security Violation 3 is disabled in the LP domain. + 0 + + + SV3_EN_1 + Security Violation 3 is enabled in the LP domain. + 0x1 + + + + + SV4_EN + Security Violation 4 Enable This bit enables Security Violation 4 Input + 4 + 1 + read-write + + + SV4_EN_0 + Security Violation 4 is disabled in the LP domain. + 0 + + + SV4_EN_1 + Security Violation 4 is enabled in the LP domain. + 0x1 + + + + + SV5_EN + Security Violation 5 Enable This bit enables Security Violation 5 Input + 5 + 1 + read-write + + + SV5_EN_0 + Security Violation 5 is disabled in the LP domain. + 0 + + + SV5_EN_1 + Security Violation 5 is enabled in the LP domain. + 0x1 + + + + + + + LPSECR + SNVS_LP Security Events Configuration Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTCR_EN + SRTC Rollover Enable When set, an SRTC rollover event generates an LP security violation. + 1 + 1 + read-write + + + SRTCR_EN_0 + SRTC rollover is disabled. + 0 + + + SRTCR_EN_1 + SRTC rollover is enabled. + 0x1 + + + + + MCR_EN + MC Rollover Enable When set, an MC Rollover event generates an LP security violation. + 2 + 1 + read-write + + + MCR_EN_0 + MC rollover is disabled. + 0 + + + MCR_EN_1 + MC rollover is enabled. + 0x1 + + + + + PFD_OBSERV + System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block) + 14 + 1 + read-write + + + POR_OBSERV + Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS + 15 + 1 + read-write + + + LTDC + Low Temp Detect Configuration These configuration bits are wired as an output of the module. + 16 + 3 + read-write + + + HTDC + High Temperature Detect Configuration These configuration bits are wired as an output of the module + 20 + 3 + read-write + + + VRC + Voltage Reference Configuration These configuration bits are wired as an output of the module. + 24 + 3 + read-write + + + OSCB + Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted + 28 + 1 + read-write + + + OSCB_0 + Normal SRTC clock oscillator not bypassed. + 0 + + + OSCB_1 + Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. + 0x1 + + + + + + + LPSR + SNVS_LP Status Register + 0x4C + 32 + read-write + 0x8 + 0xFFFFFFFF + + + LPTA + LP Time Alarm + 0 + 1 + read-write + oneToClear + + + LPTA_0 + No time alarm interrupt occurred. + 0 + + + LPTA_1 + A time alarm interrupt occurred. + 0x1 + + + + + SRTCR + Secure Real Time Counter Rollover + 1 + 1 + read-write + oneToClear + + + SRTCR_0 + SRTC has not reached its maximum value. + 0 + + + SRTCR_1 + SRTC has reached its maximum value. + 0x1 + + + + + MCR + Monotonic Counter Rollover + 2 + 1 + read-write + oneToClear + + + MCR_0 + MC has not reached its maximum value. + 0 + + + MCR_1 + MC has reached its maximum value. + 0x1 + + + + + PGD + Power Supply Glitch Detected 0 No power supply glitch. 1 Power supply glitch is detected. + 3 + 1 + read-write + oneToClear + + + ESVD + External Security Violation Detected Indicates that a security violation is detected on one of the HP security violation ports + 16 + 1 + read-write + oneToClear + + + ESVD_0 + No external security violation. + 0 + + + ESVD_1 + External security violation is detected. + 0x1 + + + + + EO + Emergency Off This bit is set when a power off is requested. + 17 + 1 + read-write + oneToClear + + + EO_0 + Emergency off was not detected. + 0 + + + EO_1 + Emergency off was detected. + 0x1 + + + + + SPO + Set Power Off The SPO bit is set when the power button is pressed longer than the configured debounce time + 18 + 1 + read-write + oneToClear + + + SPO_0 + Set Power Off was not detected. + 0 + + + SPO_1 + Set Power Off was detected. + 0x1 + + + + + LPNS + LP Section is Non-Secured Indicates that LP section was provisioned/programmed in the non-secure state + 30 + 1 + read-only + + + LPNS_0 + LP section was not programmed in the non-secure state. + 0 + + + LPNS_1 + LP section was programmed in the non-secure state. + 0x1 + + + + + LPS + LP Section is Secured Indicates that the LP section is provisioned/programmed in the secure or trusted state + 31 + 1 + read-only + + + LPS_0 + LP section was not programmed in secure or trusted state. + 0 + + + LPS_1 + LP section was programmed in secure or trusted state. + 0x1 + + + + + + + LPSRTCMR + SNVS_LP Secure Real Time Counter MSB Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTC + LP Secure Real Time Counter The most-significant 15 bits of the SRTC + 0 + 15 + read-write + + + + + LPSRTCLR + SNVS_LP Secure Real Time Counter LSB Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTC + LP Secure Real Time Counter least-significant 32 bits This register can be programmed only when SRTC is not active and not locked, meaning the SRTC_ENV, SRTC_SL, and SRTC_HL bits are not set + 0 + 32 + read-write + + + + + LPTAR + SNVS_LP Time Alarm Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPTA + LP Time Alarm This register can be programmed only when the LP time alarm is disabled (LPTA_EN bit is not set) + 0 + 32 + read-write + + + + + LPSMCMR + SNVS_LP Secure Monotonic Counter MSB Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter most-significant 16 Bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR register is detected + 0 + 16 + read-only + + + MC_ERA_BITS + Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses + 16 + 16 + read-only + + + + + LPSMCLR + SNVS_LP Secure Monotonic Counter LSB Register + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR Register is detected + 0 + 32 + read-only + + + + + LPPGDR + SNVS_LP Power Glitch Detector Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + PGD + Power Glitch Detector Value + 0 + 32 + read-write + + + + + LPGPR0_legacy_alias + SNVS_LP General Purpose Register 0 (legacy alias) + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + 8 + 0x4 + LPZMKR[%s] + SNVS_LP Zeroizable Master Key Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK + Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value + 0 + 32 + read-write + + + + + 4 + 0x4 + LPGPR_alias[%s] + SNVS_LP General Purpose Registers 0 .. 3 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + 4 + 0x4 + LPGPR[%s] + SNVS_LP General Purpose Registers 0 .. 3 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + HPVIDR1 + SNVS_HP Version ID Register 1 + 0xBF8 + 32 + read-only + 0x3E0103 + 0xFFFFFFFF + + + MINOR_REV + SNVS block minor version number + 0 + 8 + read-only + + + MAJOR_REV + SNVS block major version number + 8 + 8 + read-only + + + IP_ID + SNVS block ID + 16 + 16 + read-only + + + + + HPVIDR2 + SNVS_HP Version ID Register 2 + 0xBFC + 32 + read-only + 0x6000300 + 0xFFFFFFFF + + + CONFIG_OPT + SNVS Configuration Options + 0 + 8 + read-only + + + ECO_REV + SNVS ECO Revision + 8 + 8 + read-only + + + INTG_OPT + SNVS Integration Options + 16 + 8 + read-only + + + IP_ERA + IP Era 00h - Era 1 or 2 03h - Era 3 04h - Era 4 05h - Era 5 + 24 + 8 + read-only + + + + + + + CCM + CCM_UNIFIED + CCM + CCM_ + 0x30380000 + + 0 + 0xC700 + registers + + + CCM_IRQ1 + 85 + + + CCM_IRQ2 + 86 + + + + GPR0 + General Purpose Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + GP0 + Timeout cycle count of ipg_clk, when perform read and write. + 0 + 32 + read-write + + + + + GPR0_SET + General Purpose Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GP0 + Timeout cycle count of ipg_clk, when perform read and write. + 0 + 32 + read-write + + + + + GPR0_CLR + General Purpose Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + GP0 + Timeout cycle count of ipg_clk, when perform read and write. + 0 + 32 + read-write + + + + + GPR0_TOG + General Purpose Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + GP0 + Timeout cycle count of ipg_clk, when perform read and write. + 0 + 32 + read-write + + + + + 39 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38 + PLL_CTRL%s + CCM PLL Control Register + 0x800 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + SETTING0 + Clock gate control setting for domain 0. This field can only be written by domain 0. + 0 + 2 + read-write + + + SETTING0_0 + Domain clocks not needed + 0 + + + SETTING0_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING0_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING0_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING1 + Clock gate control setting for domain 1. This field can only be written by domain 1. + 4 + 2 + read-write + + + SETTING1_0 + Domain clocks not needed + 0 + + + SETTING1_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING1_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING1_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING2 + Clock gate control setting for domain 2. This field can only be written by domain 2 + 8 + 2 + read-write + + + SETTING2_0 + Domain clocks not needed + 0 + + + SETTING2_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING2_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING2_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING3 + Clock gate control setting for domain 3. This field can only be written by domain 3 + 12 + 2 + read-write + + + SETTING3_0 + Domain clocks not needed + 0 + + + SETTING3_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING3_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING3_3 + Domain clocks needed all the time + 0x3 + + + + + + + 39 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38 + PLL_CTRL%s_SET + CCM PLL Control Register + 0x804 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + SETTING0 + Clock gate control setting for domain 0. This field can only be written by domain 0. + 0 + 2 + read-write + + + SETTING0_0 + Domain clocks not needed + 0 + + + SETTING0_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING0_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING0_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING1 + Clock gate control setting for domain 1. This field can only be written by domain 1. + 4 + 2 + read-write + + + SETTING1_0 + Domain clocks not needed + 0 + + + SETTING1_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING1_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING1_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING2 + Clock gate control setting for domain 2. This field can only be written by domain 2 + 8 + 2 + read-write + + + SETTING2_0 + Domain clocks not needed + 0 + + + SETTING2_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING2_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING2_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING3 + Clock gate control setting for domain 3. This field can only be written by domain 3 + 12 + 2 + read-write + + + SETTING3_0 + Domain clocks not needed + 0 + + + SETTING3_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING3_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING3_3 + Domain clocks needed all the time + 0x3 + + + + + + + 39 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38 + PLL_CTRL%s_CLR + CCM PLL Control Register + 0x808 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + SETTING0 + Clock gate control setting for domain 0. This field can only be written by domain 0. + 0 + 2 + read-write + + + SETTING0_0 + Domain clocks not needed + 0 + + + SETTING0_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING0_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING0_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING1 + Clock gate control setting for domain 1. This field can only be written by domain 1. + 4 + 2 + read-write + + + SETTING1_0 + Domain clocks not needed + 0 + + + SETTING1_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING1_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING1_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING2 + Clock gate control setting for domain 2. This field can only be written by domain 2 + 8 + 2 + read-write + + + SETTING2_0 + Domain clocks not needed + 0 + + + SETTING2_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING2_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING2_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING3 + Clock gate control setting for domain 3. This field can only be written by domain 3 + 12 + 2 + read-write + + + SETTING3_0 + Domain clocks not needed + 0 + + + SETTING3_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING3_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING3_3 + Domain clocks needed all the time + 0x3 + + + + + + + 39 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38 + PLL_CTRL%s_TOG + CCM PLL Control Register + 0x80C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + SETTING0 + Clock gate control setting for domain 0. This field can only be written by domain 0. + 0 + 2 + read-write + + + SETTING0_0 + Domain clocks not needed + 0 + + + SETTING0_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING0_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING0_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING1 + Clock gate control setting for domain 1. This field can only be written by domain 1. + 4 + 2 + read-write + + + SETTING1_0 + Domain clocks not needed + 0 + + + SETTING1_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING1_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING1_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING2 + Clock gate control setting for domain 2. This field can only be written by domain 2 + 8 + 2 + read-write + + + SETTING2_0 + Domain clocks not needed + 0 + + + SETTING2_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING2_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING2_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING3 + Clock gate control setting for domain 3. This field can only be written by domain 3 + 12 + 2 + read-write + + + SETTING3_0 + Domain clocks not needed + 0 + + + SETTING3_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING3_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING3_3 + Domain clocks needed all the time + 0x3 + + + + + + + 191 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190 + CCGR%s + CCM Clock Gating Register + 0x4000 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + SETTING0 + Clock gate control setting for domain 0. This field can only be written by domain 0. + 0 + 2 + read-write + + + SETTING0_0 + Domain clocks not needed + 0 + + + SETTING0_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING0_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING0_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING1 + Clock gate control setting for domain 1. This field can only be written by domain 1. + 4 + 2 + read-write + + + SETTING1_0 + Domain clocks not needed + 0 + + + SETTING1_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING1_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING1_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING2 + Clock gate control setting for domain 2. This field can only be written by domain 2 + 8 + 2 + read-write + + + SETTING2_0 + Domain clocks not needed + 0 + + + SETTING2_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING2_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING2_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING3 + Clock gate control setting for domain 3. This field can only be written by domain 3 + 12 + 2 + read-write + + + SETTING3_0 + Domain clocks not needed + 0 + + + SETTING3_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING3_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING3_3 + Domain clocks needed all the time + 0x3 + + + + + + + 191 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190 + CCGR%s_SET + CCM Clock Gating Register + 0x4004 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + SETTING0 + Clock gate control setting for domain 0. This field can only be written by domain 0. + 0 + 2 + read-write + + + SETTING0_0 + Domain clocks not needed + 0 + + + SETTING0_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING0_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING0_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING1 + Clock gate control setting for domain 1. This field can only be written by domain 1. + 4 + 2 + read-write + + + SETTING1_0 + Domain clocks not needed + 0 + + + SETTING1_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING1_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING1_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING2 + Clock gate control setting for domain 2. This field can only be written by domain 2 + 8 + 2 + read-write + + + SETTING2_0 + Domain clocks not needed + 0 + + + SETTING2_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING2_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING2_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING3 + Clock gate control setting for domain 3. This field can only be written by domain 3 + 12 + 2 + read-write + + + SETTING3_0 + Domain clocks not needed + 0 + + + SETTING3_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING3_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING3_3 + Domain clocks needed all the time + 0x3 + + + + + + + 191 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190 + CCGR%s_CLR + CCM Clock Gating Register + 0x4008 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + SETTING0 + Clock gate control setting for domain 0. This field can only be written by domain 0. + 0 + 2 + read-write + + + SETTING0_0 + Domain clocks not needed + 0 + + + SETTING0_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING0_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING0_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING1 + Clock gate control setting for domain 1. This field can only be written by domain 1. + 4 + 2 + read-write + + + SETTING1_0 + Domain clocks not needed + 0 + + + SETTING1_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING1_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING1_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING2 + Clock gate control setting for domain 2. This field can only be written by domain 2 + 8 + 2 + read-write + + + SETTING2_0 + Domain clocks not needed + 0 + + + SETTING2_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING2_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING2_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING3 + Clock gate control setting for domain 3. This field can only be written by domain 3 + 12 + 2 + read-write + + + SETTING3_0 + Domain clocks not needed + 0 + + + SETTING3_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING3_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING3_3 + Domain clocks needed all the time + 0x3 + + + + + + + 191 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190 + CCGR%s_TOG + CCM Clock Gating Register + 0x400C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + SETTING0 + Clock gate control setting for domain 0. This field can only be written by domain 0. + 0 + 2 + read-write + + + SETTING0_0 + Domain clocks not needed + 0 + + + SETTING0_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING0_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING0_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING1 + Clock gate control setting for domain 1. This field can only be written by domain 1. + 4 + 2 + read-write + + + SETTING1_0 + Domain clocks not needed + 0 + + + SETTING1_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING1_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING1_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING2 + Clock gate control setting for domain 2. This field can only be written by domain 2 + 8 + 2 + read-write + + + SETTING2_0 + Domain clocks not needed + 0 + + + SETTING2_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING2_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING2_3 + Domain clocks needed all the time + 0x3 + + + + + SETTING3 + Clock gate control setting for domain 3. This field can only be written by domain 3 + 12 + 2 + read-write + + + SETTING3_0 + Domain clocks not needed + 0 + + + SETTING3_1 + Domain clocks needed when in RUN + 0x1 + + + SETTING3_2 + Domain clocks needed when in RUN and WAIT + 0x2 + + + SETTING3_3 + Domain clocks needed all the time + 0x3 + + + + + + + TARGET_ROOT0 + Target Register + 0x8000 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT0_SET + Target Register + 0x8004 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT0_CLR + Target Register + 0x8008 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT0_TOG + Target Register + 0x800C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC0 + Miscellaneous Register + 0x8010 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT0_SET + Miscellaneous Register + 0x8014 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT0_CLR + Miscellaneous Register + 0x8018 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT0_TOG + Miscellaneous Register + 0x801C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST0 + Post Divider Register + 0x8020 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT0_SET + Post Divider Register + 0x8024 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT0_CLR + Post Divider Register + 0x8028 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT0_TOG + Post Divider Register + 0x802C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE0 + Pre Divider Register + 0x8030 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT0_SET + Pre Divider Register + 0x8034 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT0_CLR + Pre Divider Register + 0x8038 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT0_TOG + Pre Divider Register + 0x803C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL0 + Access Control Register + 0x8070 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT0_SET + Access Control Register + 0x8074 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT0_CLR + Access Control Register + 0x8078 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT0_TOG + Access Control Register + 0x807C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT1 + Target Register + 0x8080 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT1_SET + Target Register + 0x8084 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT1_CLR + Target Register + 0x8088 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT1_TOG + Target Register + 0x808C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC1 + Miscellaneous Register + 0x8090 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT1_SET + Miscellaneous Register + 0x8094 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT1_CLR + Miscellaneous Register + 0x8098 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT1_TOG + Miscellaneous Register + 0x809C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST1 + Post Divider Register + 0x80A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT1_SET + Post Divider Register + 0x80A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT1_CLR + Post Divider Register + 0x80A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT1_TOG + Post Divider Register + 0x80AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE1 + Pre Divider Register + 0x80B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT1_SET + Pre Divider Register + 0x80B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT1_CLR + Pre Divider Register + 0x80B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT1_TOG + Pre Divider Register + 0x80BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL1 + Access Control Register + 0x80F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT1_SET + Access Control Register + 0x80F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT1_CLR + Access Control Register + 0x80F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT1_TOG + Access Control Register + 0x80FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT2 + Target Register + 0x8100 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT2_SET + Target Register + 0x8104 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT2_CLR + Target Register + 0x8108 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT2_TOG + Target Register + 0x810C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC2 + Miscellaneous Register + 0x8110 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT2_SET + Miscellaneous Register + 0x8114 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT2_CLR + Miscellaneous Register + 0x8118 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT2_TOG + Miscellaneous Register + 0x811C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST2 + Post Divider Register + 0x8120 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT2_SET + Post Divider Register + 0x8124 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT2_CLR + Post Divider Register + 0x8128 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT2_TOG + Post Divider Register + 0x812C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE2 + Pre Divider Register + 0x8130 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT2_SET + Pre Divider Register + 0x8134 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT2_CLR + Pre Divider Register + 0x8138 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT2_TOG + Pre Divider Register + 0x813C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL2 + Access Control Register + 0x8170 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT2_SET + Access Control Register + 0x8174 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT2_CLR + Access Control Register + 0x8178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT2_TOG + Access Control Register + 0x817C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT3 + Target Register + 0x8180 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT3_SET + Target Register + 0x8184 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT3_CLR + Target Register + 0x8188 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT3_TOG + Target Register + 0x818C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC3 + Miscellaneous Register + 0x8190 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT3_SET + Miscellaneous Register + 0x8194 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT3_CLR + Miscellaneous Register + 0x8198 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT3_TOG + Miscellaneous Register + 0x819C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST3 + Post Divider Register + 0x81A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT3_SET + Post Divider Register + 0x81A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT3_CLR + Post Divider Register + 0x81A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT3_TOG + Post Divider Register + 0x81AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE3 + Pre Divider Register + 0x81B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT3_SET + Pre Divider Register + 0x81B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT3_CLR + Pre Divider Register + 0x81B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT3_TOG + Pre Divider Register + 0x81BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL3 + Access Control Register + 0x81F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT3_SET + Access Control Register + 0x81F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT3_CLR + Access Control Register + 0x81F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT3_TOG + Access Control Register + 0x81FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT4 + Target Register + 0x8200 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT4_SET + Target Register + 0x8204 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT4_CLR + Target Register + 0x8208 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT4_TOG + Target Register + 0x820C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC4 + Miscellaneous Register + 0x8210 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT4_SET + Miscellaneous Register + 0x8214 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT4_CLR + Miscellaneous Register + 0x8218 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT4_TOG + Miscellaneous Register + 0x821C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST4 + Post Divider Register + 0x8220 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT4_SET + Post Divider Register + 0x8224 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT4_CLR + Post Divider Register + 0x8228 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT4_TOG + Post Divider Register + 0x822C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE4 + Pre Divider Register + 0x8230 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT4_SET + Pre Divider Register + 0x8234 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT4_CLR + Pre Divider Register + 0x8238 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT4_TOG + Pre Divider Register + 0x823C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL4 + Access Control Register + 0x8270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT4_SET + Access Control Register + 0x8274 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT4_CLR + Access Control Register + 0x8278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT4_TOG + Access Control Register + 0x827C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT16 + Target Register + 0x8800 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT16_SET + Target Register + 0x8804 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT16_CLR + Target Register + 0x8808 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT16_TOG + Target Register + 0x880C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC16 + Miscellaneous Register + 0x8810 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT16_SET + Miscellaneous Register + 0x8814 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT16_CLR + Miscellaneous Register + 0x8818 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT16_TOG + Miscellaneous Register + 0x881C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST16 + Post Divider Register + 0x8820 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT16_SET + Post Divider Register + 0x8824 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT16_CLR + Post Divider Register + 0x8828 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT16_TOG + Post Divider Register + 0x882C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE16 + Pre Divider Register + 0x8830 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT16_SET + Pre Divider Register + 0x8834 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT16_CLR + Pre Divider Register + 0x8838 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT16_TOG + Pre Divider Register + 0x883C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL16 + Access Control Register + 0x8870 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT16_SET + Access Control Register + 0x8874 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT16_CLR + Access Control Register + 0x8878 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT16_TOG + Access Control Register + 0x887C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT17 + Target Register + 0x8880 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT17_SET + Target Register + 0x8884 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT17_CLR + Target Register + 0x8888 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT17_TOG + Target Register + 0x888C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC17 + Miscellaneous Register + 0x8890 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT17_SET + Miscellaneous Register + 0x8894 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT17_CLR + Miscellaneous Register + 0x8898 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT17_TOG + Miscellaneous Register + 0x889C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST17 + Post Divider Register + 0x88A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT17_SET + Post Divider Register + 0x88A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT17_CLR + Post Divider Register + 0x88A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT17_TOG + Post Divider Register + 0x88AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE17 + Pre Divider Register + 0x88B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT17_SET + Pre Divider Register + 0x88B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT17_CLR + Pre Divider Register + 0x88B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT17_TOG + Pre Divider Register + 0x88BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL17 + Access Control Register + 0x88F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT17_SET + Access Control Register + 0x88F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT17_CLR + Access Control Register + 0x88F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT17_TOG + Access Control Register + 0x88FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT18 + Target Register + 0x8900 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT18_SET + Target Register + 0x8904 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT18_CLR + Target Register + 0x8908 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT18_TOG + Target Register + 0x890C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC18 + Miscellaneous Register + 0x8910 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT18_SET + Miscellaneous Register + 0x8914 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT18_CLR + Miscellaneous Register + 0x8918 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT18_TOG + Miscellaneous Register + 0x891C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST18 + Post Divider Register + 0x8920 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT18_SET + Post Divider Register + 0x8924 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT18_CLR + Post Divider Register + 0x8928 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT18_TOG + Post Divider Register + 0x892C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE18 + Pre Divider Register + 0x8930 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT18_SET + Pre Divider Register + 0x8934 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT18_CLR + Pre Divider Register + 0x8938 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT18_TOG + Pre Divider Register + 0x893C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL18 + Access Control Register + 0x8970 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT18_SET + Access Control Register + 0x8974 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT18_CLR + Access Control Register + 0x8978 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT18_TOG + Access Control Register + 0x897C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT19 + Target Register + 0x8980 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT19_SET + Target Register + 0x8984 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT19_CLR + Target Register + 0x8988 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT19_TOG + Target Register + 0x898C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC19 + Miscellaneous Register + 0x8990 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT19_SET + Miscellaneous Register + 0x8994 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT19_CLR + Miscellaneous Register + 0x8998 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT19_TOG + Miscellaneous Register + 0x899C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST19 + Post Divider Register + 0x89A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT19_SET + Post Divider Register + 0x89A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT19_CLR + Post Divider Register + 0x89A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT19_TOG + Post Divider Register + 0x89AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE19 + Pre Divider Register + 0x89B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT19_SET + Pre Divider Register + 0x89B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT19_CLR + Pre Divider Register + 0x89B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT19_TOG + Pre Divider Register + 0x89BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL19 + Access Control Register + 0x89F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT19_SET + Access Control Register + 0x89F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT19_CLR + Access Control Register + 0x89F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT19_TOG + Access Control Register + 0x89FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT20 + Target Register + 0x8A00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT20_SET + Target Register + 0x8A04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT20_CLR + Target Register + 0x8A08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT20_TOG + Target Register + 0x8A0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC20 + Miscellaneous Register + 0x8A10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT20_SET + Miscellaneous Register + 0x8A14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT20_CLR + Miscellaneous Register + 0x8A18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT20_TOG + Miscellaneous Register + 0x8A1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST20 + Post Divider Register + 0x8A20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT20_SET + Post Divider Register + 0x8A24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT20_CLR + Post Divider Register + 0x8A28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT20_TOG + Post Divider Register + 0x8A2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE20 + Pre Divider Register + 0x8A30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT20_SET + Pre Divider Register + 0x8A34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT20_CLR + Pre Divider Register + 0x8A38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT20_TOG + Pre Divider Register + 0x8A3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL20 + Access Control Register + 0x8A70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT20_SET + Access Control Register + 0x8A74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT20_CLR + Access Control Register + 0x8A78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT20_TOG + Access Control Register + 0x8A7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT21 + Target Register + 0x8A80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT21_SET + Target Register + 0x8A84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT21_CLR + Target Register + 0x8A88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT21_TOG + Target Register + 0x8A8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC21 + Miscellaneous Register + 0x8A90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT21_SET + Miscellaneous Register + 0x8A94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT21_CLR + Miscellaneous Register + 0x8A98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT21_TOG + Miscellaneous Register + 0x8A9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST21 + Post Divider Register + 0x8AA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT21_SET + Post Divider Register + 0x8AA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT21_CLR + Post Divider Register + 0x8AA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT21_TOG + Post Divider Register + 0x8AAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE21 + Pre Divider Register + 0x8AB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT21_SET + Pre Divider Register + 0x8AB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT21_CLR + Pre Divider Register + 0x8AB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT21_TOG + Pre Divider Register + 0x8ABC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL21 + Access Control Register + 0x8AF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT21_SET + Access Control Register + 0x8AF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT21_CLR + Access Control Register + 0x8AF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT21_TOG + Access Control Register + 0x8AFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT22 + Target Register + 0x8B00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT22_SET + Target Register + 0x8B04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT22_CLR + Target Register + 0x8B08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT22_TOG + Target Register + 0x8B0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC22 + Miscellaneous Register + 0x8B10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT22_SET + Miscellaneous Register + 0x8B14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT22_CLR + Miscellaneous Register + 0x8B18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT22_TOG + Miscellaneous Register + 0x8B1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST22 + Post Divider Register + 0x8B20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT22_SET + Post Divider Register + 0x8B24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT22_CLR + Post Divider Register + 0x8B28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT22_TOG + Post Divider Register + 0x8B2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE22 + Pre Divider Register + 0x8B30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT22_SET + Pre Divider Register + 0x8B34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT22_CLR + Pre Divider Register + 0x8B38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT22_TOG + Pre Divider Register + 0x8B3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL22 + Access Control Register + 0x8B70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT22_SET + Access Control Register + 0x8B74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT22_CLR + Access Control Register + 0x8B78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT22_TOG + Access Control Register + 0x8B7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT23 + Target Register + 0x8B80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT23_SET + Target Register + 0x8B84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT23_CLR + Target Register + 0x8B88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT23_TOG + Target Register + 0x8B8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC23 + Miscellaneous Register + 0x8B90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT23_SET + Miscellaneous Register + 0x8B94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT23_CLR + Miscellaneous Register + 0x8B98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT23_TOG + Miscellaneous Register + 0x8B9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST23 + Post Divider Register + 0x8BA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT23_SET + Post Divider Register + 0x8BA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT23_CLR + Post Divider Register + 0x8BA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT23_TOG + Post Divider Register + 0x8BAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE23 + Pre Divider Register + 0x8BB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT23_SET + Pre Divider Register + 0x8BB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT23_CLR + Pre Divider Register + 0x8BB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT23_TOG + Pre Divider Register + 0x8BBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL23 + Access Control Register + 0x8BF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT23_SET + Access Control Register + 0x8BF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT23_CLR + Access Control Register + 0x8BF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT23_TOG + Access Control Register + 0x8BFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT24 + Target Register + 0x8C00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT24_SET + Target Register + 0x8C04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT24_CLR + Target Register + 0x8C08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT24_TOG + Target Register + 0x8C0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC24 + Miscellaneous Register + 0x8C10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT24_SET + Miscellaneous Register + 0x8C14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT24_CLR + Miscellaneous Register + 0x8C18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT24_TOG + Miscellaneous Register + 0x8C1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST24 + Post Divider Register + 0x8C20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT24_SET + Post Divider Register + 0x8C24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT24_CLR + Post Divider Register + 0x8C28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT24_TOG + Post Divider Register + 0x8C2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE24 + Pre Divider Register + 0x8C30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT24_SET + Pre Divider Register + 0x8C34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT24_CLR + Pre Divider Register + 0x8C38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT24_TOG + Pre Divider Register + 0x8C3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL24 + Access Control Register + 0x8C70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT24_SET + Access Control Register + 0x8C74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT24_CLR + Access Control Register + 0x8C78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT24_TOG + Access Control Register + 0x8C7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT25 + Target Register + 0x8C80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT25_SET + Target Register + 0x8C84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT25_CLR + Target Register + 0x8C88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT25_TOG + Target Register + 0x8C8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC25 + Miscellaneous Register + 0x8C90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT25_SET + Miscellaneous Register + 0x8C94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT25_CLR + Miscellaneous Register + 0x8C98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT25_TOG + Miscellaneous Register + 0x8C9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST25 + Post Divider Register + 0x8CA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT25_SET + Post Divider Register + 0x8CA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT25_CLR + Post Divider Register + 0x8CA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT25_TOG + Post Divider Register + 0x8CAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE25 + Pre Divider Register + 0x8CB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT25_SET + Pre Divider Register + 0x8CB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT25_CLR + Pre Divider Register + 0x8CB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT25_TOG + Pre Divider Register + 0x8CBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL25 + Access Control Register + 0x8CF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT25_SET + Access Control Register + 0x8CF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT25_CLR + Access Control Register + 0x8CF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT25_TOG + Access Control Register + 0x8CFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT26 + Target Register + 0x8D00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT26_SET + Target Register + 0x8D04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT26_CLR + Target Register + 0x8D08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT26_TOG + Target Register + 0x8D0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC26 + Miscellaneous Register + 0x8D10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT26_SET + Miscellaneous Register + 0x8D14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT26_CLR + Miscellaneous Register + 0x8D18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT26_TOG + Miscellaneous Register + 0x8D1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST26 + Post Divider Register + 0x8D20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT26_SET + Post Divider Register + 0x8D24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT26_CLR + Post Divider Register + 0x8D28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT26_TOG + Post Divider Register + 0x8D2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE26 + Pre Divider Register + 0x8D30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT26_SET + Pre Divider Register + 0x8D34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT26_CLR + Pre Divider Register + 0x8D38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT26_TOG + Pre Divider Register + 0x8D3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL26 + Access Control Register + 0x8D70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT26_SET + Access Control Register + 0x8D74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT26_CLR + Access Control Register + 0x8D78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT26_TOG + Access Control Register + 0x8D7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT27 + Target Register + 0x8D80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT27_SET + Target Register + 0x8D84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT27_CLR + Target Register + 0x8D88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT27_TOG + Target Register + 0x8D8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC27 + Miscellaneous Register + 0x8D90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT27_SET + Miscellaneous Register + 0x8D94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT27_CLR + Miscellaneous Register + 0x8D98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT27_TOG + Miscellaneous Register + 0x8D9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST27 + Post Divider Register + 0x8DA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT27_SET + Post Divider Register + 0x8DA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT27_CLR + Post Divider Register + 0x8DA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT27_TOG + Post Divider Register + 0x8DAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE27 + Pre Divider Register + 0x8DB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT27_SET + Pre Divider Register + 0x8DB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT27_CLR + Pre Divider Register + 0x8DB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT27_TOG + Pre Divider Register + 0x8DBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL27 + Access Control Register + 0x8DF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT27_SET + Access Control Register + 0x8DF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT27_CLR + Access Control Register + 0x8DF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT27_TOG + Access Control Register + 0x8DFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT32 + Target Register + 0x9000 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT32_SET + Target Register + 0x9004 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT32_CLR + Target Register + 0x9008 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT32_TOG + Target Register + 0x900C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC32 + Miscellaneous Register + 0x9010 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT32_SET + Miscellaneous Register + 0x9014 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT32_CLR + Miscellaneous Register + 0x9018 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT32_TOG + Miscellaneous Register + 0x901C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST32 + Post Divider Register + 0x9020 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT32_SET + Post Divider Register + 0x9024 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT32_CLR + Post Divider Register + 0x9028 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT32_TOG + Post Divider Register + 0x902C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE32 + Pre Divider Register + 0x9030 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT32_SET + Pre Divider Register + 0x9034 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT32_CLR + Pre Divider Register + 0x9038 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT32_TOG + Pre Divider Register + 0x903C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL32 + Access Control Register + 0x9070 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT32_SET + Access Control Register + 0x9074 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT32_CLR + Access Control Register + 0x9078 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT32_TOG + Access Control Register + 0x907C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT33 + Target Register + 0x9080 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT33_SET + Target Register + 0x9084 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT33_CLR + Target Register + 0x9088 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT33_TOG + Target Register + 0x908C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC33 + Miscellaneous Register + 0x9090 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT33_SET + Miscellaneous Register + 0x9094 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT33_CLR + Miscellaneous Register + 0x9098 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT33_TOG + Miscellaneous Register + 0x909C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST33 + Post Divider Register + 0x90A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT33_SET + Post Divider Register + 0x90A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT33_CLR + Post Divider Register + 0x90A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT33_TOG + Post Divider Register + 0x90AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE33 + Pre Divider Register + 0x90B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT33_SET + Pre Divider Register + 0x90B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT33_CLR + Pre Divider Register + 0x90B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT33_TOG + Pre Divider Register + 0x90BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL33 + Access Control Register + 0x90F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT33_SET + Access Control Register + 0x90F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT33_CLR + Access Control Register + 0x90F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT33_TOG + Access Control Register + 0x90FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT34 + Target Register + 0x9100 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT34_SET + Target Register + 0x9104 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT34_CLR + Target Register + 0x9108 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT34_TOG + Target Register + 0x910C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC34 + Miscellaneous Register + 0x9110 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT34_SET + Miscellaneous Register + 0x9114 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT34_CLR + Miscellaneous Register + 0x9118 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT34_TOG + Miscellaneous Register + 0x911C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST34 + Post Divider Register + 0x9120 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT34_SET + Post Divider Register + 0x9124 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT34_CLR + Post Divider Register + 0x9128 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT34_TOG + Post Divider Register + 0x912C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE34 + Pre Divider Register + 0x9130 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT34_SET + Pre Divider Register + 0x9134 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT34_CLR + Pre Divider Register + 0x9138 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT34_TOG + Pre Divider Register + 0x913C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL34 + Access Control Register + 0x9170 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT34_SET + Access Control Register + 0x9174 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT34_CLR + Access Control Register + 0x9178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT34_TOG + Access Control Register + 0x917C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT35 + Target Register + 0x9180 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT35_SET + Target Register + 0x9184 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT35_CLR + Target Register + 0x9188 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT35_TOG + Target Register + 0x918C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC35 + Miscellaneous Register + 0x9190 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT35_SET + Miscellaneous Register + 0x9194 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT35_CLR + Miscellaneous Register + 0x9198 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT35_TOG + Miscellaneous Register + 0x919C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST35 + Post Divider Register + 0x91A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT35_SET + Post Divider Register + 0x91A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT35_CLR + Post Divider Register + 0x91A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT35_TOG + Post Divider Register + 0x91AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE35 + Pre Divider Register + 0x91B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT35_SET + Pre Divider Register + 0x91B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT35_CLR + Pre Divider Register + 0x91B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT35_TOG + Pre Divider Register + 0x91BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL35 + Access Control Register + 0x91F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT35_SET + Access Control Register + 0x91F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT35_CLR + Access Control Register + 0x91F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT35_TOG + Access Control Register + 0x91FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT36 + Target Register + 0x9200 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT36_SET + Target Register + 0x9204 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT36_CLR + Target Register + 0x9208 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT36_TOG + Target Register + 0x920C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC36 + Miscellaneous Register + 0x9210 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT36_SET + Miscellaneous Register + 0x9214 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT36_CLR + Miscellaneous Register + 0x9218 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT36_TOG + Miscellaneous Register + 0x921C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST36 + Post Divider Register + 0x9220 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT36_SET + Post Divider Register + 0x9224 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT36_CLR + Post Divider Register + 0x9228 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT36_TOG + Post Divider Register + 0x922C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE36 + Pre Divider Register + 0x9230 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT36_SET + Pre Divider Register + 0x9234 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT36_CLR + Pre Divider Register + 0x9238 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT36_TOG + Pre Divider Register + 0x923C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL36 + Access Control Register + 0x9270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT36_SET + Access Control Register + 0x9274 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT36_CLR + Access Control Register + 0x9278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT36_TOG + Access Control Register + 0x927C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT37 + Target Register + 0x9280 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT37_SET + Target Register + 0x9284 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT37_CLR + Target Register + 0x9288 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT37_TOG + Target Register + 0x928C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC37 + Miscellaneous Register + 0x9290 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT37_SET + Miscellaneous Register + 0x9294 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT37_CLR + Miscellaneous Register + 0x9298 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT37_TOG + Miscellaneous Register + 0x929C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST37 + Post Divider Register + 0x92A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT37_SET + Post Divider Register + 0x92A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT37_CLR + Post Divider Register + 0x92A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT37_TOG + Post Divider Register + 0x92AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE37 + Pre Divider Register + 0x92B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT37_SET + Pre Divider Register + 0x92B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT37_CLR + Pre Divider Register + 0x92B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT37_TOG + Pre Divider Register + 0x92BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL37 + Access Control Register + 0x92F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT37_SET + Access Control Register + 0x92F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT37_CLR + Access Control Register + 0x92F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT37_TOG + Access Control Register + 0x92FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT48 + Target Register + 0x9800 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT48_SET + Target Register + 0x9804 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT48_CLR + Target Register + 0x9808 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT48_TOG + Target Register + 0x980C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC48 + Miscellaneous Register + 0x9810 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT48_SET + Miscellaneous Register + 0x9814 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT48_CLR + Miscellaneous Register + 0x9818 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT48_TOG + Miscellaneous Register + 0x981C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST48 + Post Divider Register + 0x9820 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT48_SET + Post Divider Register + 0x9824 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT48_CLR + Post Divider Register + 0x9828 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT48_TOG + Post Divider Register + 0x982C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE48 + Pre Divider Register + 0x9830 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT48_SET + Pre Divider Register + 0x9834 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT48_CLR + Pre Divider Register + 0x9838 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT48_TOG + Pre Divider Register + 0x983C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL48 + Access Control Register + 0x9870 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT48_SET + Access Control Register + 0x9874 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT48_CLR + Access Control Register + 0x9878 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT48_TOG + Access Control Register + 0x987C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT49 + Target Register + 0x9880 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT49_SET + Target Register + 0x9884 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT49_CLR + Target Register + 0x9888 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT49_TOG + Target Register + 0x988C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC49 + Miscellaneous Register + 0x9890 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT49_SET + Miscellaneous Register + 0x9894 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT49_CLR + Miscellaneous Register + 0x9898 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT49_TOG + Miscellaneous Register + 0x989C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST49 + Post Divider Register + 0x98A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT49_SET + Post Divider Register + 0x98A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT49_CLR + Post Divider Register + 0x98A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT49_TOG + Post Divider Register + 0x98AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE49 + Pre Divider Register + 0x98B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT49_SET + Pre Divider Register + 0x98B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT49_CLR + Pre Divider Register + 0x98B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT49_TOG + Pre Divider Register + 0x98BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL49 + Access Control Register + 0x98F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT49_SET + Access Control Register + 0x98F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT49_CLR + Access Control Register + 0x98F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT49_TOG + Access Control Register + 0x98FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT64 + Target Register + 0xA000 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT64_SET + Target Register + 0xA004 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT64_CLR + Target Register + 0xA008 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT64_TOG + Target Register + 0xA00C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC64 + Miscellaneous Register + 0xA010 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT64_SET + Miscellaneous Register + 0xA014 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT64_CLR + Miscellaneous Register + 0xA018 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT64_TOG + Miscellaneous Register + 0xA01C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST64 + Post Divider Register + 0xA020 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT64_SET + Post Divider Register + 0xA024 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT64_CLR + Post Divider Register + 0xA028 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT64_TOG + Post Divider Register + 0xA02C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE64 + Pre Divider Register + 0xA030 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT64_SET + Pre Divider Register + 0xA034 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT64_CLR + Pre Divider Register + 0xA038 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT64_TOG + Pre Divider Register + 0xA03C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL64 + Access Control Register + 0xA070 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT64_SET + Access Control Register + 0xA074 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT64_CLR + Access Control Register + 0xA078 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT64_TOG + Access Control Register + 0xA07C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT65 + Target Register + 0xA080 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT65_SET + Target Register + 0xA084 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT65_CLR + Target Register + 0xA088 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT65_TOG + Target Register + 0xA08C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC65 + Miscellaneous Register + 0xA090 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT65_SET + Miscellaneous Register + 0xA094 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT65_CLR + Miscellaneous Register + 0xA098 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT65_TOG + Miscellaneous Register + 0xA09C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST65 + Post Divider Register + 0xA0A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT65_SET + Post Divider Register + 0xA0A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT65_CLR + Post Divider Register + 0xA0A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT65_TOG + Post Divider Register + 0xA0AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE65 + Pre Divider Register + 0xA0B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT65_SET + Pre Divider Register + 0xA0B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT65_CLR + Pre Divider Register + 0xA0B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT65_TOG + Pre Divider Register + 0xA0BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL65 + Access Control Register + 0xA0F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT65_SET + Access Control Register + 0xA0F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT65_CLR + Access Control Register + 0xA0F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT65_TOG + Access Control Register + 0xA0FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT66 + Target Register + 0xA100 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT66_SET + Target Register + 0xA104 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT66_CLR + Target Register + 0xA108 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT66_TOG + Target Register + 0xA10C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC66 + Miscellaneous Register + 0xA110 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT66_SET + Miscellaneous Register + 0xA114 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT66_CLR + Miscellaneous Register + 0xA118 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT66_TOG + Miscellaneous Register + 0xA11C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST66 + Post Divider Register + 0xA120 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT66_SET + Post Divider Register + 0xA124 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT66_CLR + Post Divider Register + 0xA128 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT66_TOG + Post Divider Register + 0xA12C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE66 + Pre Divider Register + 0xA130 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT66_SET + Pre Divider Register + 0xA134 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT66_CLR + Pre Divider Register + 0xA138 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT66_TOG + Pre Divider Register + 0xA13C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL66 + Access Control Register + 0xA170 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT66_SET + Access Control Register + 0xA174 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT66_CLR + Access Control Register + 0xA178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT66_TOG + Access Control Register + 0xA17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT67 + Target Register + 0xA180 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT67_SET + Target Register + 0xA184 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT67_CLR + Target Register + 0xA188 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT67_TOG + Target Register + 0xA18C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC67 + Miscellaneous Register + 0xA190 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT67_SET + Miscellaneous Register + 0xA194 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT67_CLR + Miscellaneous Register + 0xA198 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT67_TOG + Miscellaneous Register + 0xA19C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST67 + Post Divider Register + 0xA1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT67_SET + Post Divider Register + 0xA1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT67_CLR + Post Divider Register + 0xA1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT67_TOG + Post Divider Register + 0xA1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE67 + Pre Divider Register + 0xA1B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT67_SET + Pre Divider Register + 0xA1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT67_CLR + Pre Divider Register + 0xA1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT67_TOG + Pre Divider Register + 0xA1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL67 + Access Control Register + 0xA1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT67_SET + Access Control Register + 0xA1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT67_CLR + Access Control Register + 0xA1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT67_TOG + Access Control Register + 0xA1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT68 + Target Register + 0xA200 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT68_SET + Target Register + 0xA204 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT68_CLR + Target Register + 0xA208 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT68_TOG + Target Register + 0xA20C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC68 + Miscellaneous Register + 0xA210 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT68_SET + Miscellaneous Register + 0xA214 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT68_CLR + Miscellaneous Register + 0xA218 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT68_TOG + Miscellaneous Register + 0xA21C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST68 + Post Divider Register + 0xA220 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT68_SET + Post Divider Register + 0xA224 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT68_CLR + Post Divider Register + 0xA228 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT68_TOG + Post Divider Register + 0xA22C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE68 + Pre Divider Register + 0xA230 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT68_SET + Pre Divider Register + 0xA234 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT68_CLR + Pre Divider Register + 0xA238 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT68_TOG + Pre Divider Register + 0xA23C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL68 + Access Control Register + 0xA270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT68_SET + Access Control Register + 0xA274 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT68_CLR + Access Control Register + 0xA278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT68_TOG + Access Control Register + 0xA27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT69 + Target Register + 0xA280 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT69_SET + Target Register + 0xA284 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT69_CLR + Target Register + 0xA288 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT69_TOG + Target Register + 0xA28C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC69 + Miscellaneous Register + 0xA290 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT69_SET + Miscellaneous Register + 0xA294 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT69_CLR + Miscellaneous Register + 0xA298 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT69_TOG + Miscellaneous Register + 0xA29C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST69 + Post Divider Register + 0xA2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT69_SET + Post Divider Register + 0xA2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT69_CLR + Post Divider Register + 0xA2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT69_TOG + Post Divider Register + 0xA2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE69 + Pre Divider Register + 0xA2B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT69_SET + Pre Divider Register + 0xA2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT69_CLR + Pre Divider Register + 0xA2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT69_TOG + Pre Divider Register + 0xA2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL69 + Access Control Register + 0xA2F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT69_SET + Access Control Register + 0xA2F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT69_CLR + Access Control Register + 0xA2F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT69_TOG + Access Control Register + 0xA2FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT70 + Target Register + 0xA300 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT70_SET + Target Register + 0xA304 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT70_CLR + Target Register + 0xA308 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT70_TOG + Target Register + 0xA30C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC70 + Miscellaneous Register + 0xA310 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT70_SET + Miscellaneous Register + 0xA314 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT70_CLR + Miscellaneous Register + 0xA318 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT70_TOG + Miscellaneous Register + 0xA31C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST70 + Post Divider Register + 0xA320 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT70_SET + Post Divider Register + 0xA324 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT70_CLR + Post Divider Register + 0xA328 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT70_TOG + Post Divider Register + 0xA32C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE70 + Pre Divider Register + 0xA330 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT70_SET + Pre Divider Register + 0xA334 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT70_CLR + Pre Divider Register + 0xA338 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT70_TOG + Pre Divider Register + 0xA33C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL70 + Access Control Register + 0xA370 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT70_SET + Access Control Register + 0xA374 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT70_CLR + Access Control Register + 0xA378 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT70_TOG + Access Control Register + 0xA37C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT71 + Target Register + 0xA380 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT71_SET + Target Register + 0xA384 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT71_CLR + Target Register + 0xA388 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT71_TOG + Target Register + 0xA38C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC71 + Miscellaneous Register + 0xA390 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT71_SET + Miscellaneous Register + 0xA394 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT71_CLR + Miscellaneous Register + 0xA398 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT71_TOG + Miscellaneous Register + 0xA39C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST71 + Post Divider Register + 0xA3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT71_SET + Post Divider Register + 0xA3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT71_CLR + Post Divider Register + 0xA3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT71_TOG + Post Divider Register + 0xA3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE71 + Pre Divider Register + 0xA3B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT71_SET + Pre Divider Register + 0xA3B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT71_CLR + Pre Divider Register + 0xA3B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT71_TOG + Pre Divider Register + 0xA3BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL71 + Access Control Register + 0xA3F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT71_SET + Access Control Register + 0xA3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT71_CLR + Access Control Register + 0xA3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT71_TOG + Access Control Register + 0xA3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT72 + Target Register + 0xA400 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT72_SET + Target Register + 0xA404 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT72_CLR + Target Register + 0xA408 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT72_TOG + Target Register + 0xA40C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC72 + Miscellaneous Register + 0xA410 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT72_SET + Miscellaneous Register + 0xA414 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT72_CLR + Miscellaneous Register + 0xA418 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT72_TOG + Miscellaneous Register + 0xA41C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST72 + Post Divider Register + 0xA420 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT72_SET + Post Divider Register + 0xA424 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT72_CLR + Post Divider Register + 0xA428 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT72_TOG + Post Divider Register + 0xA42C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE72 + Pre Divider Register + 0xA430 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT72_SET + Pre Divider Register + 0xA434 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT72_CLR + Pre Divider Register + 0xA438 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT72_TOG + Pre Divider Register + 0xA43C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL72 + Access Control Register + 0xA470 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT72_SET + Access Control Register + 0xA474 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT72_CLR + Access Control Register + 0xA478 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT72_TOG + Access Control Register + 0xA47C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT73 + Target Register + 0xA480 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT73_SET + Target Register + 0xA484 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT73_CLR + Target Register + 0xA488 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT73_TOG + Target Register + 0xA48C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC73 + Miscellaneous Register + 0xA490 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT73_SET + Miscellaneous Register + 0xA494 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT73_CLR + Miscellaneous Register + 0xA498 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT73_TOG + Miscellaneous Register + 0xA49C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST73 + Post Divider Register + 0xA4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT73_SET + Post Divider Register + 0xA4A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT73_CLR + Post Divider Register + 0xA4A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT73_TOG + Post Divider Register + 0xA4AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE73 + Pre Divider Register + 0xA4B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT73_SET + Pre Divider Register + 0xA4B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT73_CLR + Pre Divider Register + 0xA4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT73_TOG + Pre Divider Register + 0xA4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL73 + Access Control Register + 0xA4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT73_SET + Access Control Register + 0xA4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT73_CLR + Access Control Register + 0xA4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT73_TOG + Access Control Register + 0xA4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT74 + Target Register + 0xA500 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT74_SET + Target Register + 0xA504 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT74_CLR + Target Register + 0xA508 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT74_TOG + Target Register + 0xA50C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC74 + Miscellaneous Register + 0xA510 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT74_SET + Miscellaneous Register + 0xA514 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT74_CLR + Miscellaneous Register + 0xA518 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT74_TOG + Miscellaneous Register + 0xA51C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST74 + Post Divider Register + 0xA520 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT74_SET + Post Divider Register + 0xA524 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT74_CLR + Post Divider Register + 0xA528 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT74_TOG + Post Divider Register + 0xA52C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE74 + Pre Divider Register + 0xA530 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT74_SET + Pre Divider Register + 0xA534 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT74_CLR + Pre Divider Register + 0xA538 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT74_TOG + Pre Divider Register + 0xA53C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL74 + Access Control Register + 0xA570 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT74_SET + Access Control Register + 0xA574 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT74_CLR + Access Control Register + 0xA578 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT74_TOG + Access Control Register + 0xA57C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT75 + Target Register + 0xA580 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT75_SET + Target Register + 0xA584 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT75_CLR + Target Register + 0xA588 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT75_TOG + Target Register + 0xA58C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC75 + Miscellaneous Register + 0xA590 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT75_SET + Miscellaneous Register + 0xA594 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT75_CLR + Miscellaneous Register + 0xA598 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT75_TOG + Miscellaneous Register + 0xA59C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST75 + Post Divider Register + 0xA5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT75_SET + Post Divider Register + 0xA5A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT75_CLR + Post Divider Register + 0xA5A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT75_TOG + Post Divider Register + 0xA5AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE75 + Pre Divider Register + 0xA5B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT75_SET + Pre Divider Register + 0xA5B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT75_CLR + Pre Divider Register + 0xA5B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT75_TOG + Pre Divider Register + 0xA5BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL75 + Access Control Register + 0xA5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT75_SET + Access Control Register + 0xA5F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT75_CLR + Access Control Register + 0xA5F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT75_TOG + Access Control Register + 0xA5FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT76 + Target Register + 0xA600 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT76_SET + Target Register + 0xA604 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT76_CLR + Target Register + 0xA608 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT76_TOG + Target Register + 0xA60C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC76 + Miscellaneous Register + 0xA610 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT76_SET + Miscellaneous Register + 0xA614 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT76_CLR + Miscellaneous Register + 0xA618 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT76_TOG + Miscellaneous Register + 0xA61C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST76 + Post Divider Register + 0xA620 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT76_SET + Post Divider Register + 0xA624 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT76_CLR + Post Divider Register + 0xA628 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT76_TOG + Post Divider Register + 0xA62C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE76 + Pre Divider Register + 0xA630 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT76_SET + Pre Divider Register + 0xA634 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT76_CLR + Pre Divider Register + 0xA638 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT76_TOG + Pre Divider Register + 0xA63C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL76 + Access Control Register + 0xA670 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT76_SET + Access Control Register + 0xA674 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT76_CLR + Access Control Register + 0xA678 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT76_TOG + Access Control Register + 0xA67C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT77 + Target Register + 0xA680 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT77_SET + Target Register + 0xA684 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT77_CLR + Target Register + 0xA688 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT77_TOG + Target Register + 0xA68C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC77 + Miscellaneous Register + 0xA690 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT77_SET + Miscellaneous Register + 0xA694 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT77_CLR + Miscellaneous Register + 0xA698 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT77_TOG + Miscellaneous Register + 0xA69C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST77 + Post Divider Register + 0xA6A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT77_SET + Post Divider Register + 0xA6A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT77_CLR + Post Divider Register + 0xA6A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT77_TOG + Post Divider Register + 0xA6AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE77 + Pre Divider Register + 0xA6B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT77_SET + Pre Divider Register + 0xA6B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT77_CLR + Pre Divider Register + 0xA6B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT77_TOG + Pre Divider Register + 0xA6BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL77 + Access Control Register + 0xA6F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT77_SET + Access Control Register + 0xA6F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT77_CLR + Access Control Register + 0xA6F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT77_TOG + Access Control Register + 0xA6FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT78 + Target Register + 0xA700 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT78_SET + Target Register + 0xA704 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT78_CLR + Target Register + 0xA708 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT78_TOG + Target Register + 0xA70C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC78 + Miscellaneous Register + 0xA710 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT78_SET + Miscellaneous Register + 0xA714 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT78_CLR + Miscellaneous Register + 0xA718 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT78_TOG + Miscellaneous Register + 0xA71C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST78 + Post Divider Register + 0xA720 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT78_SET + Post Divider Register + 0xA724 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT78_CLR + Post Divider Register + 0xA728 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT78_TOG + Post Divider Register + 0xA72C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE78 + Pre Divider Register + 0xA730 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT78_SET + Pre Divider Register + 0xA734 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT78_CLR + Pre Divider Register + 0xA738 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT78_TOG + Pre Divider Register + 0xA73C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL78 + Access Control Register + 0xA770 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT78_SET + Access Control Register + 0xA774 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT78_CLR + Access Control Register + 0xA778 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT78_TOG + Access Control Register + 0xA77C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT79 + Target Register + 0xA780 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT79_SET + Target Register + 0xA784 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT79_CLR + Target Register + 0xA788 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT79_TOG + Target Register + 0xA78C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC79 + Miscellaneous Register + 0xA790 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT79_SET + Miscellaneous Register + 0xA794 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT79_CLR + Miscellaneous Register + 0xA798 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT79_TOG + Miscellaneous Register + 0xA79C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST79 + Post Divider Register + 0xA7A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT79_SET + Post Divider Register + 0xA7A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT79_CLR + Post Divider Register + 0xA7A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT79_TOG + Post Divider Register + 0xA7AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE79 + Pre Divider Register + 0xA7B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT79_SET + Pre Divider Register + 0xA7B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT79_CLR + Pre Divider Register + 0xA7B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT79_TOG + Pre Divider Register + 0xA7BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL79 + Access Control Register + 0xA7F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT79_SET + Access Control Register + 0xA7F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT79_CLR + Access Control Register + 0xA7F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT79_TOG + Access Control Register + 0xA7FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT80 + Target Register + 0xA800 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT80_SET + Target Register + 0xA804 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT80_CLR + Target Register + 0xA808 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT80_TOG + Target Register + 0xA80C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC80 + Miscellaneous Register + 0xA810 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT80_SET + Miscellaneous Register + 0xA814 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT80_CLR + Miscellaneous Register + 0xA818 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT80_TOG + Miscellaneous Register + 0xA81C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST80 + Post Divider Register + 0xA820 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT80_SET + Post Divider Register + 0xA824 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT80_CLR + Post Divider Register + 0xA828 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT80_TOG + Post Divider Register + 0xA82C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE80 + Pre Divider Register + 0xA830 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT80_SET + Pre Divider Register + 0xA834 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT80_CLR + Pre Divider Register + 0xA838 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT80_TOG + Pre Divider Register + 0xA83C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL80 + Access Control Register + 0xA870 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT80_SET + Access Control Register + 0xA874 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT80_CLR + Access Control Register + 0xA878 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT80_TOG + Access Control Register + 0xA87C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT81 + Target Register + 0xA880 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT81_SET + Target Register + 0xA884 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT81_CLR + Target Register + 0xA888 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT81_TOG + Target Register + 0xA88C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC81 + Miscellaneous Register + 0xA890 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT81_SET + Miscellaneous Register + 0xA894 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT81_CLR + Miscellaneous Register + 0xA898 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT81_TOG + Miscellaneous Register + 0xA89C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST81 + Post Divider Register + 0xA8A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT81_SET + Post Divider Register + 0xA8A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT81_CLR + Post Divider Register + 0xA8A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT81_TOG + Post Divider Register + 0xA8AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE81 + Pre Divider Register + 0xA8B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT81_SET + Pre Divider Register + 0xA8B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT81_CLR + Pre Divider Register + 0xA8B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT81_TOG + Pre Divider Register + 0xA8BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL81 + Access Control Register + 0xA8F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT81_SET + Access Control Register + 0xA8F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT81_CLR + Access Control Register + 0xA8F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT81_TOG + Access Control Register + 0xA8FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT82 + Target Register + 0xA900 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT82_SET + Target Register + 0xA904 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT82_CLR + Target Register + 0xA908 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT82_TOG + Target Register + 0xA90C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC82 + Miscellaneous Register + 0xA910 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT82_SET + Miscellaneous Register + 0xA914 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT82_CLR + Miscellaneous Register + 0xA918 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT82_TOG + Miscellaneous Register + 0xA91C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST82 + Post Divider Register + 0xA920 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT82_SET + Post Divider Register + 0xA924 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT82_CLR + Post Divider Register + 0xA928 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT82_TOG + Post Divider Register + 0xA92C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE82 + Pre Divider Register + 0xA930 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT82_SET + Pre Divider Register + 0xA934 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT82_CLR + Pre Divider Register + 0xA938 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT82_TOG + Pre Divider Register + 0xA93C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL82 + Access Control Register + 0xA970 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT82_SET + Access Control Register + 0xA974 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT82_CLR + Access Control Register + 0xA978 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT82_TOG + Access Control Register + 0xA97C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT83 + Target Register + 0xA980 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT83_SET + Target Register + 0xA984 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT83_CLR + Target Register + 0xA988 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT83_TOG + Target Register + 0xA98C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC83 + Miscellaneous Register + 0xA990 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT83_SET + Miscellaneous Register + 0xA994 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT83_CLR + Miscellaneous Register + 0xA998 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT83_TOG + Miscellaneous Register + 0xA99C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST83 + Post Divider Register + 0xA9A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT83_SET + Post Divider Register + 0xA9A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT83_CLR + Post Divider Register + 0xA9A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT83_TOG + Post Divider Register + 0xA9AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE83 + Pre Divider Register + 0xA9B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT83_SET + Pre Divider Register + 0xA9B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT83_CLR + Pre Divider Register + 0xA9B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT83_TOG + Pre Divider Register + 0xA9BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL83 + Access Control Register + 0xA9F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT83_SET + Access Control Register + 0xA9F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT83_CLR + Access Control Register + 0xA9F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT83_TOG + Access Control Register + 0xA9FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT84 + Target Register + 0xAA00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT84_SET + Target Register + 0xAA04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT84_CLR + Target Register + 0xAA08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT84_TOG + Target Register + 0xAA0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC84 + Miscellaneous Register + 0xAA10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT84_SET + Miscellaneous Register + 0xAA14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT84_CLR + Miscellaneous Register + 0xAA18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT84_TOG + Miscellaneous Register + 0xAA1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST84 + Post Divider Register + 0xAA20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT84_SET + Post Divider Register + 0xAA24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT84_CLR + Post Divider Register + 0xAA28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT84_TOG + Post Divider Register + 0xAA2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE84 + Pre Divider Register + 0xAA30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT84_SET + Pre Divider Register + 0xAA34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT84_CLR + Pre Divider Register + 0xAA38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT84_TOG + Pre Divider Register + 0xAA3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL84 + Access Control Register + 0xAA70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT84_SET + Access Control Register + 0xAA74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT84_CLR + Access Control Register + 0xAA78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT84_TOG + Access Control Register + 0xAA7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT85 + Target Register + 0xAA80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT85_SET + Target Register + 0xAA84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT85_CLR + Target Register + 0xAA88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT85_TOG + Target Register + 0xAA8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC85 + Miscellaneous Register + 0xAA90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT85_SET + Miscellaneous Register + 0xAA94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT85_CLR + Miscellaneous Register + 0xAA98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT85_TOG + Miscellaneous Register + 0xAA9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST85 + Post Divider Register + 0xAAA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT85_SET + Post Divider Register + 0xAAA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT85_CLR + Post Divider Register + 0xAAA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT85_TOG + Post Divider Register + 0xAAAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE85 + Pre Divider Register + 0xAAB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT85_SET + Pre Divider Register + 0xAAB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT85_CLR + Pre Divider Register + 0xAAB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT85_TOG + Pre Divider Register + 0xAABC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL85 + Access Control Register + 0xAAF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT85_SET + Access Control Register + 0xAAF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT85_CLR + Access Control Register + 0xAAF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT85_TOG + Access Control Register + 0xAAFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT86 + Target Register + 0xAB00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT86_SET + Target Register + 0xAB04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT86_CLR + Target Register + 0xAB08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT86_TOG + Target Register + 0xAB0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC86 + Miscellaneous Register + 0xAB10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT86_SET + Miscellaneous Register + 0xAB14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT86_CLR + Miscellaneous Register + 0xAB18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT86_TOG + Miscellaneous Register + 0xAB1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST86 + Post Divider Register + 0xAB20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT86_SET + Post Divider Register + 0xAB24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT86_CLR + Post Divider Register + 0xAB28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT86_TOG + Post Divider Register + 0xAB2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE86 + Pre Divider Register + 0xAB30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT86_SET + Pre Divider Register + 0xAB34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT86_CLR + Pre Divider Register + 0xAB38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT86_TOG + Pre Divider Register + 0xAB3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL86 + Access Control Register + 0xAB70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT86_SET + Access Control Register + 0xAB74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT86_CLR + Access Control Register + 0xAB78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT86_TOG + Access Control Register + 0xAB7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT87 + Target Register + 0xAB80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT87_SET + Target Register + 0xAB84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT87_CLR + Target Register + 0xAB88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT87_TOG + Target Register + 0xAB8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC87 + Miscellaneous Register + 0xAB90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT87_SET + Miscellaneous Register + 0xAB94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT87_CLR + Miscellaneous Register + 0xAB98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT87_TOG + Miscellaneous Register + 0xAB9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST87 + Post Divider Register + 0xABA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT87_SET + Post Divider Register + 0xABA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT87_CLR + Post Divider Register + 0xABA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT87_TOG + Post Divider Register + 0xABAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE87 + Pre Divider Register + 0xABB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT87_SET + Pre Divider Register + 0xABB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT87_CLR + Pre Divider Register + 0xABB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT87_TOG + Pre Divider Register + 0xABBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL87 + Access Control Register + 0xABF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT87_SET + Access Control Register + 0xABF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT87_CLR + Access Control Register + 0xABF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT87_TOG + Access Control Register + 0xABFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT88 + Target Register + 0xAC00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT88_SET + Target Register + 0xAC04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT88_CLR + Target Register + 0xAC08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT88_TOG + Target Register + 0xAC0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC88 + Miscellaneous Register + 0xAC10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT88_SET + Miscellaneous Register + 0xAC14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT88_CLR + Miscellaneous Register + 0xAC18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT88_TOG + Miscellaneous Register + 0xAC1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST88 + Post Divider Register + 0xAC20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT88_SET + Post Divider Register + 0xAC24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT88_CLR + Post Divider Register + 0xAC28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT88_TOG + Post Divider Register + 0xAC2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE88 + Pre Divider Register + 0xAC30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT88_SET + Pre Divider Register + 0xAC34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT88_CLR + Pre Divider Register + 0xAC38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT88_TOG + Pre Divider Register + 0xAC3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL88 + Access Control Register + 0xAC70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT88_SET + Access Control Register + 0xAC74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT88_CLR + Access Control Register + 0xAC78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT88_TOG + Access Control Register + 0xAC7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT89 + Target Register + 0xAC80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT89_SET + Target Register + 0xAC84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT89_CLR + Target Register + 0xAC88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT89_TOG + Target Register + 0xAC8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC89 + Miscellaneous Register + 0xAC90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT89_SET + Miscellaneous Register + 0xAC94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT89_CLR + Miscellaneous Register + 0xAC98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT89_TOG + Miscellaneous Register + 0xAC9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST89 + Post Divider Register + 0xACA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT89_SET + Post Divider Register + 0xACA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT89_CLR + Post Divider Register + 0xACA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT89_TOG + Post Divider Register + 0xACAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE89 + Pre Divider Register + 0xACB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT89_SET + Pre Divider Register + 0xACB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT89_CLR + Pre Divider Register + 0xACB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT89_TOG + Pre Divider Register + 0xACBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL89 + Access Control Register + 0xACF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT89_SET + Access Control Register + 0xACF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT89_CLR + Access Control Register + 0xACF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT89_TOG + Access Control Register + 0xACFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT90 + Target Register + 0xAD00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT90_SET + Target Register + 0xAD04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT90_CLR + Target Register + 0xAD08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT90_TOG + Target Register + 0xAD0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC90 + Miscellaneous Register + 0xAD10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT90_SET + Miscellaneous Register + 0xAD14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT90_CLR + Miscellaneous Register + 0xAD18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT90_TOG + Miscellaneous Register + 0xAD1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST90 + Post Divider Register + 0xAD20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT90_SET + Post Divider Register + 0xAD24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT90_CLR + Post Divider Register + 0xAD28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT90_TOG + Post Divider Register + 0xAD2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE90 + Pre Divider Register + 0xAD30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT90_SET + Pre Divider Register + 0xAD34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT90_CLR + Pre Divider Register + 0xAD38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT90_TOG + Pre Divider Register + 0xAD3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL90 + Access Control Register + 0xAD70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT90_SET + Access Control Register + 0xAD74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT90_CLR + Access Control Register + 0xAD78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT90_TOG + Access Control Register + 0xAD7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT91 + Target Register + 0xAD80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT91_SET + Target Register + 0xAD84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT91_CLR + Target Register + 0xAD88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT91_TOG + Target Register + 0xAD8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC91 + Miscellaneous Register + 0xAD90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT91_SET + Miscellaneous Register + 0xAD94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT91_CLR + Miscellaneous Register + 0xAD98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT91_TOG + Miscellaneous Register + 0xAD9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST91 + Post Divider Register + 0xADA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT91_SET + Post Divider Register + 0xADA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT91_CLR + Post Divider Register + 0xADA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT91_TOG + Post Divider Register + 0xADAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE91 + Pre Divider Register + 0xADB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT91_SET + Pre Divider Register + 0xADB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT91_CLR + Pre Divider Register + 0xADB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT91_TOG + Pre Divider Register + 0xADBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL91 + Access Control Register + 0xADF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT91_SET + Access Control Register + 0xADF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT91_CLR + Access Control Register + 0xADF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT91_TOG + Access Control Register + 0xADFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT92 + Target Register + 0xAE00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT92_SET + Target Register + 0xAE04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT92_CLR + Target Register + 0xAE08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT92_TOG + Target Register + 0xAE0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC92 + Miscellaneous Register + 0xAE10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT92_SET + Miscellaneous Register + 0xAE14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT92_CLR + Miscellaneous Register + 0xAE18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT92_TOG + Miscellaneous Register + 0xAE1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST92 + Post Divider Register + 0xAE20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT92_SET + Post Divider Register + 0xAE24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT92_CLR + Post Divider Register + 0xAE28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT92_TOG + Post Divider Register + 0xAE2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE92 + Pre Divider Register + 0xAE30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT92_SET + Pre Divider Register + 0xAE34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT92_CLR + Pre Divider Register + 0xAE38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT92_TOG + Pre Divider Register + 0xAE3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL92 + Access Control Register + 0xAE70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT92_SET + Access Control Register + 0xAE74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT92_CLR + Access Control Register + 0xAE78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT92_TOG + Access Control Register + 0xAE7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT93 + Target Register + 0xAE80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT93_SET + Target Register + 0xAE84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT93_CLR + Target Register + 0xAE88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT93_TOG + Target Register + 0xAE8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC93 + Miscellaneous Register + 0xAE90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT93_SET + Miscellaneous Register + 0xAE94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT93_CLR + Miscellaneous Register + 0xAE98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT93_TOG + Miscellaneous Register + 0xAE9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST93 + Post Divider Register + 0xAEA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT93_SET + Post Divider Register + 0xAEA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT93_CLR + Post Divider Register + 0xAEA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT93_TOG + Post Divider Register + 0xAEAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE93 + Pre Divider Register + 0xAEB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT93_SET + Pre Divider Register + 0xAEB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT93_CLR + Pre Divider Register + 0xAEB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT93_TOG + Pre Divider Register + 0xAEBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL93 + Access Control Register + 0xAEF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT93_SET + Access Control Register + 0xAEF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT93_CLR + Access Control Register + 0xAEF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT93_TOG + Access Control Register + 0xAEFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT94 + Target Register + 0xAF00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT94_SET + Target Register + 0xAF04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT94_CLR + Target Register + 0xAF08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT94_TOG + Target Register + 0xAF0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC94 + Miscellaneous Register + 0xAF10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT94_SET + Miscellaneous Register + 0xAF14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT94_CLR + Miscellaneous Register + 0xAF18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT94_TOG + Miscellaneous Register + 0xAF1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST94 + Post Divider Register + 0xAF20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT94_SET + Post Divider Register + 0xAF24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT94_CLR + Post Divider Register + 0xAF28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT94_TOG + Post Divider Register + 0xAF2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE94 + Pre Divider Register + 0xAF30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT94_SET + Pre Divider Register + 0xAF34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT94_CLR + Pre Divider Register + 0xAF38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT94_TOG + Pre Divider Register + 0xAF3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL94 + Access Control Register + 0xAF70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT94_SET + Access Control Register + 0xAF74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT94_CLR + Access Control Register + 0xAF78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT94_TOG + Access Control Register + 0xAF7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT95 + Target Register + 0xAF80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT95_SET + Target Register + 0xAF84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT95_CLR + Target Register + 0xAF88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT95_TOG + Target Register + 0xAF8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC95 + Miscellaneous Register + 0xAF90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT95_SET + Miscellaneous Register + 0xAF94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT95_CLR + Miscellaneous Register + 0xAF98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT95_TOG + Miscellaneous Register + 0xAF9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST95 + Post Divider Register + 0xAFA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT95_SET + Post Divider Register + 0xAFA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT95_CLR + Post Divider Register + 0xAFA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT95_TOG + Post Divider Register + 0xAFAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE95 + Pre Divider Register + 0xAFB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT95_SET + Pre Divider Register + 0xAFB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT95_CLR + Pre Divider Register + 0xAFB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT95_TOG + Pre Divider Register + 0xAFBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL95 + Access Control Register + 0xAFF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT95_SET + Access Control Register + 0xAFF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT95_CLR + Access Control Register + 0xAFF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT95_TOG + Access Control Register + 0xAFFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT96 + Target Register + 0xB000 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT96_SET + Target Register + 0xB004 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT96_CLR + Target Register + 0xB008 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT96_TOG + Target Register + 0xB00C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC96 + Miscellaneous Register + 0xB010 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT96_SET + Miscellaneous Register + 0xB014 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT96_CLR + Miscellaneous Register + 0xB018 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT96_TOG + Miscellaneous Register + 0xB01C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST96 + Post Divider Register + 0xB020 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT96_SET + Post Divider Register + 0xB024 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT96_CLR + Post Divider Register + 0xB028 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT96_TOG + Post Divider Register + 0xB02C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE96 + Pre Divider Register + 0xB030 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT96_SET + Pre Divider Register + 0xB034 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT96_CLR + Pre Divider Register + 0xB038 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT96_TOG + Pre Divider Register + 0xB03C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL96 + Access Control Register + 0xB070 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT96_SET + Access Control Register + 0xB074 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT96_CLR + Access Control Register + 0xB078 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT96_TOG + Access Control Register + 0xB07C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT97 + Target Register + 0xB080 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT97_SET + Target Register + 0xB084 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT97_CLR + Target Register + 0xB088 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT97_TOG + Target Register + 0xB08C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC97 + Miscellaneous Register + 0xB090 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT97_SET + Miscellaneous Register + 0xB094 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT97_CLR + Miscellaneous Register + 0xB098 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT97_TOG + Miscellaneous Register + 0xB09C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST97 + Post Divider Register + 0xB0A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT97_SET + Post Divider Register + 0xB0A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT97_CLR + Post Divider Register + 0xB0A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT97_TOG + Post Divider Register + 0xB0AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE97 + Pre Divider Register + 0xB0B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT97_SET + Pre Divider Register + 0xB0B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT97_CLR + Pre Divider Register + 0xB0B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT97_TOG + Pre Divider Register + 0xB0BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL97 + Access Control Register + 0xB0F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT97_SET + Access Control Register + 0xB0F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT97_CLR + Access Control Register + 0xB0F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT97_TOG + Access Control Register + 0xB0FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT98 + Target Register + 0xB100 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT98_SET + Target Register + 0xB104 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT98_CLR + Target Register + 0xB108 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT98_TOG + Target Register + 0xB10C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC98 + Miscellaneous Register + 0xB110 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT98_SET + Miscellaneous Register + 0xB114 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT98_CLR + Miscellaneous Register + 0xB118 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT98_TOG + Miscellaneous Register + 0xB11C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST98 + Post Divider Register + 0xB120 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT98_SET + Post Divider Register + 0xB124 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT98_CLR + Post Divider Register + 0xB128 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT98_TOG + Post Divider Register + 0xB12C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE98 + Pre Divider Register + 0xB130 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT98_SET + Pre Divider Register + 0xB134 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT98_CLR + Pre Divider Register + 0xB138 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT98_TOG + Pre Divider Register + 0xB13C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL98 + Access Control Register + 0xB170 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT98_SET + Access Control Register + 0xB174 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT98_CLR + Access Control Register + 0xB178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT98_TOG + Access Control Register + 0xB17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT99 + Target Register + 0xB180 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT99_SET + Target Register + 0xB184 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT99_CLR + Target Register + 0xB188 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT99_TOG + Target Register + 0xB18C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC99 + Miscellaneous Register + 0xB190 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT99_SET + Miscellaneous Register + 0xB194 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT99_CLR + Miscellaneous Register + 0xB198 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT99_TOG + Miscellaneous Register + 0xB19C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST99 + Post Divider Register + 0xB1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT99_SET + Post Divider Register + 0xB1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT99_CLR + Post Divider Register + 0xB1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT99_TOG + Post Divider Register + 0xB1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE99 + Pre Divider Register + 0xB1B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT99_SET + Pre Divider Register + 0xB1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT99_CLR + Pre Divider Register + 0xB1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT99_TOG + Pre Divider Register + 0xB1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL99 + Access Control Register + 0xB1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT99_SET + Access Control Register + 0xB1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT99_CLR + Access Control Register + 0xB1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT99_TOG + Access Control Register + 0xB1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT100 + Target Register + 0xB200 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT100_SET + Target Register + 0xB204 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT100_CLR + Target Register + 0xB208 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT100_TOG + Target Register + 0xB20C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC100 + Miscellaneous Register + 0xB210 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT100_SET + Miscellaneous Register + 0xB214 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT100_CLR + Miscellaneous Register + 0xB218 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT100_TOG + Miscellaneous Register + 0xB21C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST100 + Post Divider Register + 0xB220 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT100_SET + Post Divider Register + 0xB224 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT100_CLR + Post Divider Register + 0xB228 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT100_TOG + Post Divider Register + 0xB22C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE100 + Pre Divider Register + 0xB230 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT100_SET + Pre Divider Register + 0xB234 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT100_CLR + Pre Divider Register + 0xB238 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT100_TOG + Pre Divider Register + 0xB23C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL100 + Access Control Register + 0xB270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT100_SET + Access Control Register + 0xB274 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT100_CLR + Access Control Register + 0xB278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT100_TOG + Access Control Register + 0xB27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT101 + Target Register + 0xB280 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT101_SET + Target Register + 0xB284 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT101_CLR + Target Register + 0xB288 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT101_TOG + Target Register + 0xB28C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC101 + Miscellaneous Register + 0xB290 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT101_SET + Miscellaneous Register + 0xB294 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT101_CLR + Miscellaneous Register + 0xB298 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT101_TOG + Miscellaneous Register + 0xB29C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST101 + Post Divider Register + 0xB2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT101_SET + Post Divider Register + 0xB2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT101_CLR + Post Divider Register + 0xB2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT101_TOG + Post Divider Register + 0xB2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE101 + Pre Divider Register + 0xB2B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT101_SET + Pre Divider Register + 0xB2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT101_CLR + Pre Divider Register + 0xB2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT101_TOG + Pre Divider Register + 0xB2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL101 + Access Control Register + 0xB2F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT101_SET + Access Control Register + 0xB2F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT101_CLR + Access Control Register + 0xB2F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT101_TOG + Access Control Register + 0xB2FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT102 + Target Register + 0xB300 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT102_SET + Target Register + 0xB304 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT102_CLR + Target Register + 0xB308 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT102_TOG + Target Register + 0xB30C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC102 + Miscellaneous Register + 0xB310 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT102_SET + Miscellaneous Register + 0xB314 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT102_CLR + Miscellaneous Register + 0xB318 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT102_TOG + Miscellaneous Register + 0xB31C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST102 + Post Divider Register + 0xB320 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT102_SET + Post Divider Register + 0xB324 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT102_CLR + Post Divider Register + 0xB328 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT102_TOG + Post Divider Register + 0xB32C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE102 + Pre Divider Register + 0xB330 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT102_SET + Pre Divider Register + 0xB334 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT102_CLR + Pre Divider Register + 0xB338 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT102_TOG + Pre Divider Register + 0xB33C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL102 + Access Control Register + 0xB370 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT102_SET + Access Control Register + 0xB374 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT102_CLR + Access Control Register + 0xB378 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT102_TOG + Access Control Register + 0xB37C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT103 + Target Register + 0xB380 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT103_SET + Target Register + 0xB384 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT103_CLR + Target Register + 0xB388 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT103_TOG + Target Register + 0xB38C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC103 + Miscellaneous Register + 0xB390 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT103_SET + Miscellaneous Register + 0xB394 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT103_CLR + Miscellaneous Register + 0xB398 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT103_TOG + Miscellaneous Register + 0xB39C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST103 + Post Divider Register + 0xB3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT103_SET + Post Divider Register + 0xB3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT103_CLR + Post Divider Register + 0xB3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT103_TOG + Post Divider Register + 0xB3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE103 + Pre Divider Register + 0xB3B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT103_SET + Pre Divider Register + 0xB3B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT103_CLR + Pre Divider Register + 0xB3B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT103_TOG + Pre Divider Register + 0xB3BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL103 + Access Control Register + 0xB3F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT103_SET + Access Control Register + 0xB3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT103_CLR + Access Control Register + 0xB3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT103_TOG + Access Control Register + 0xB3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT104 + Target Register + 0xB400 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT104_SET + Target Register + 0xB404 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT104_CLR + Target Register + 0xB408 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT104_TOG + Target Register + 0xB40C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC104 + Miscellaneous Register + 0xB410 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT104_SET + Miscellaneous Register + 0xB414 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT104_CLR + Miscellaneous Register + 0xB418 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT104_TOG + Miscellaneous Register + 0xB41C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST104 + Post Divider Register + 0xB420 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT104_SET + Post Divider Register + 0xB424 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT104_CLR + Post Divider Register + 0xB428 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT104_TOG + Post Divider Register + 0xB42C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE104 + Pre Divider Register + 0xB430 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT104_SET + Pre Divider Register + 0xB434 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT104_CLR + Pre Divider Register + 0xB438 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT104_TOG + Pre Divider Register + 0xB43C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL104 + Access Control Register + 0xB470 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT104_SET + Access Control Register + 0xB474 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT104_CLR + Access Control Register + 0xB478 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT104_TOG + Access Control Register + 0xB47C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT105 + Target Register + 0xB480 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT105_SET + Target Register + 0xB484 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT105_CLR + Target Register + 0xB488 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT105_TOG + Target Register + 0xB48C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC105 + Miscellaneous Register + 0xB490 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT105_SET + Miscellaneous Register + 0xB494 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT105_CLR + Miscellaneous Register + 0xB498 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT105_TOG + Miscellaneous Register + 0xB49C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST105 + Post Divider Register + 0xB4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT105_SET + Post Divider Register + 0xB4A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT105_CLR + Post Divider Register + 0xB4A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT105_TOG + Post Divider Register + 0xB4AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE105 + Pre Divider Register + 0xB4B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT105_SET + Pre Divider Register + 0xB4B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT105_CLR + Pre Divider Register + 0xB4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT105_TOG + Pre Divider Register + 0xB4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL105 + Access Control Register + 0xB4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT105_SET + Access Control Register + 0xB4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT105_CLR + Access Control Register + 0xB4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT105_TOG + Access Control Register + 0xB4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT106 + Target Register + 0xB500 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT106_SET + Target Register + 0xB504 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT106_CLR + Target Register + 0xB508 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT106_TOG + Target Register + 0xB50C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC106 + Miscellaneous Register + 0xB510 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT106_SET + Miscellaneous Register + 0xB514 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT106_CLR + Miscellaneous Register + 0xB518 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT106_TOG + Miscellaneous Register + 0xB51C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST106 + Post Divider Register + 0xB520 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT106_SET + Post Divider Register + 0xB524 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT106_CLR + Post Divider Register + 0xB528 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT106_TOG + Post Divider Register + 0xB52C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE106 + Pre Divider Register + 0xB530 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT106_SET + Pre Divider Register + 0xB534 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT106_CLR + Pre Divider Register + 0xB538 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT106_TOG + Pre Divider Register + 0xB53C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL106 + Access Control Register + 0xB570 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT106_SET + Access Control Register + 0xB574 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT106_CLR + Access Control Register + 0xB578 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT106_TOG + Access Control Register + 0xB57C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT107 + Target Register + 0xB580 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT107_SET + Target Register + 0xB584 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT107_CLR + Target Register + 0xB588 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT107_TOG + Target Register + 0xB58C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC107 + Miscellaneous Register + 0xB590 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT107_SET + Miscellaneous Register + 0xB594 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT107_CLR + Miscellaneous Register + 0xB598 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT107_TOG + Miscellaneous Register + 0xB59C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST107 + Post Divider Register + 0xB5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT107_SET + Post Divider Register + 0xB5A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT107_CLR + Post Divider Register + 0xB5A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT107_TOG + Post Divider Register + 0xB5AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE107 + Pre Divider Register + 0xB5B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT107_SET + Pre Divider Register + 0xB5B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT107_CLR + Pre Divider Register + 0xB5B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT107_TOG + Pre Divider Register + 0xB5BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL107 + Access Control Register + 0xB5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT107_SET + Access Control Register + 0xB5F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT107_CLR + Access Control Register + 0xB5F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT107_TOG + Access Control Register + 0xB5FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT108 + Target Register + 0xB600 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT108_SET + Target Register + 0xB604 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT108_CLR + Target Register + 0xB608 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT108_TOG + Target Register + 0xB60C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC108 + Miscellaneous Register + 0xB610 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT108_SET + Miscellaneous Register + 0xB614 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT108_CLR + Miscellaneous Register + 0xB618 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT108_TOG + Miscellaneous Register + 0xB61C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST108 + Post Divider Register + 0xB620 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT108_SET + Post Divider Register + 0xB624 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT108_CLR + Post Divider Register + 0xB628 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT108_TOG + Post Divider Register + 0xB62C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE108 + Pre Divider Register + 0xB630 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT108_SET + Pre Divider Register + 0xB634 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT108_CLR + Pre Divider Register + 0xB638 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT108_TOG + Pre Divider Register + 0xB63C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL108 + Access Control Register + 0xB670 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT108_SET + Access Control Register + 0xB674 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT108_CLR + Access Control Register + 0xB678 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT108_TOG + Access Control Register + 0xB67C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT109 + Target Register + 0xB680 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT109_SET + Target Register + 0xB684 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT109_CLR + Target Register + 0xB688 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT109_TOG + Target Register + 0xB68C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC109 + Miscellaneous Register + 0xB690 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT109_SET + Miscellaneous Register + 0xB694 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT109_CLR + Miscellaneous Register + 0xB698 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT109_TOG + Miscellaneous Register + 0xB69C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST109 + Post Divider Register + 0xB6A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT109_SET + Post Divider Register + 0xB6A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT109_CLR + Post Divider Register + 0xB6A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT109_TOG + Post Divider Register + 0xB6AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE109 + Pre Divider Register + 0xB6B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT109_SET + Pre Divider Register + 0xB6B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT109_CLR + Pre Divider Register + 0xB6B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT109_TOG + Pre Divider Register + 0xB6BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL109 + Access Control Register + 0xB6F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT109_SET + Access Control Register + 0xB6F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT109_CLR + Access Control Register + 0xB6F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT109_TOG + Access Control Register + 0xB6FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT110 + Target Register + 0xB700 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT110_SET + Target Register + 0xB704 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT110_CLR + Target Register + 0xB708 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT110_TOG + Target Register + 0xB70C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC110 + Miscellaneous Register + 0xB710 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT110_SET + Miscellaneous Register + 0xB714 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT110_CLR + Miscellaneous Register + 0xB718 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT110_TOG + Miscellaneous Register + 0xB71C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST110 + Post Divider Register + 0xB720 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT110_SET + Post Divider Register + 0xB724 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT110_CLR + Post Divider Register + 0xB728 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT110_TOG + Post Divider Register + 0xB72C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE110 + Pre Divider Register + 0xB730 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT110_SET + Pre Divider Register + 0xB734 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT110_CLR + Pre Divider Register + 0xB738 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT110_TOG + Pre Divider Register + 0xB73C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL110 + Access Control Register + 0xB770 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT110_SET + Access Control Register + 0xB774 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT110_CLR + Access Control Register + 0xB778 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT110_TOG + Access Control Register + 0xB77C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT111 + Target Register + 0xB780 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT111_SET + Target Register + 0xB784 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT111_CLR + Target Register + 0xB788 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT111_TOG + Target Register + 0xB78C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC111 + Miscellaneous Register + 0xB790 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT111_SET + Miscellaneous Register + 0xB794 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT111_CLR + Miscellaneous Register + 0xB798 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT111_TOG + Miscellaneous Register + 0xB79C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST111 + Post Divider Register + 0xB7A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT111_SET + Post Divider Register + 0xB7A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT111_CLR + Post Divider Register + 0xB7A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT111_TOG + Post Divider Register + 0xB7AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE111 + Pre Divider Register + 0xB7B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT111_SET + Pre Divider Register + 0xB7B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT111_CLR + Pre Divider Register + 0xB7B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT111_TOG + Pre Divider Register + 0xB7BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL111 + Access Control Register + 0xB7F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT111_SET + Access Control Register + 0xB7F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT111_CLR + Access Control Register + 0xB7F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT111_TOG + Access Control Register + 0xB7FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT112 + Target Register + 0xB800 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT112_SET + Target Register + 0xB804 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT112_CLR + Target Register + 0xB808 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT112_TOG + Target Register + 0xB80C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC112 + Miscellaneous Register + 0xB810 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT112_SET + Miscellaneous Register + 0xB814 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT112_CLR + Miscellaneous Register + 0xB818 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT112_TOG + Miscellaneous Register + 0xB81C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST112 + Post Divider Register + 0xB820 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT112_SET + Post Divider Register + 0xB824 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT112_CLR + Post Divider Register + 0xB828 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT112_TOG + Post Divider Register + 0xB82C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE112 + Pre Divider Register + 0xB830 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT112_SET + Pre Divider Register + 0xB834 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT112_CLR + Pre Divider Register + 0xB838 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT112_TOG + Pre Divider Register + 0xB83C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL112 + Access Control Register + 0xB870 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT112_SET + Access Control Register + 0xB874 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT112_CLR + Access Control Register + 0xB878 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT112_TOG + Access Control Register + 0xB87C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT113 + Target Register + 0xB880 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT113_SET + Target Register + 0xB884 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT113_CLR + Target Register + 0xB888 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT113_TOG + Target Register + 0xB88C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC113 + Miscellaneous Register + 0xB890 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT113_SET + Miscellaneous Register + 0xB894 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT113_CLR + Miscellaneous Register + 0xB898 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT113_TOG + Miscellaneous Register + 0xB89C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST113 + Post Divider Register + 0xB8A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT113_SET + Post Divider Register + 0xB8A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT113_CLR + Post Divider Register + 0xB8A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT113_TOG + Post Divider Register + 0xB8AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE113 + Pre Divider Register + 0xB8B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT113_SET + Pre Divider Register + 0xB8B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT113_CLR + Pre Divider Register + 0xB8B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT113_TOG + Pre Divider Register + 0xB8BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL113 + Access Control Register + 0xB8F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT113_SET + Access Control Register + 0xB8F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT113_CLR + Access Control Register + 0xB8F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT113_TOG + Access Control Register + 0xB8FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT114 + Target Register + 0xB900 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT114_SET + Target Register + 0xB904 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT114_CLR + Target Register + 0xB908 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT114_TOG + Target Register + 0xB90C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC114 + Miscellaneous Register + 0xB910 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT114_SET + Miscellaneous Register + 0xB914 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT114_CLR + Miscellaneous Register + 0xB918 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT114_TOG + Miscellaneous Register + 0xB91C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST114 + Post Divider Register + 0xB920 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT114_SET + Post Divider Register + 0xB924 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT114_CLR + Post Divider Register + 0xB928 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT114_TOG + Post Divider Register + 0xB92C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE114 + Pre Divider Register + 0xB930 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT114_SET + Pre Divider Register + 0xB934 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT114_CLR + Pre Divider Register + 0xB938 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT114_TOG + Pre Divider Register + 0xB93C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL114 + Access Control Register + 0xB970 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT114_SET + Access Control Register + 0xB974 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT114_CLR + Access Control Register + 0xB978 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT114_TOG + Access Control Register + 0xB97C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT115 + Target Register + 0xB980 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT115_SET + Target Register + 0xB984 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT115_CLR + Target Register + 0xB988 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT115_TOG + Target Register + 0xB98C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC115 + Miscellaneous Register + 0xB990 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT115_SET + Miscellaneous Register + 0xB994 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT115_CLR + Miscellaneous Register + 0xB998 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT115_TOG + Miscellaneous Register + 0xB99C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST115 + Post Divider Register + 0xB9A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT115_SET + Post Divider Register + 0xB9A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT115_CLR + Post Divider Register + 0xB9A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT115_TOG + Post Divider Register + 0xB9AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE115 + Pre Divider Register + 0xB9B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT115_SET + Pre Divider Register + 0xB9B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT115_CLR + Pre Divider Register + 0xB9B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT115_TOG + Pre Divider Register + 0xB9BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL115 + Access Control Register + 0xB9F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT115_SET + Access Control Register + 0xB9F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT115_CLR + Access Control Register + 0xB9F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT115_TOG + Access Control Register + 0xB9FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT116 + Target Register + 0xBA00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT116_SET + Target Register + 0xBA04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT116_CLR + Target Register + 0xBA08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT116_TOG + Target Register + 0xBA0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC116 + Miscellaneous Register + 0xBA10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT116_SET + Miscellaneous Register + 0xBA14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT116_CLR + Miscellaneous Register + 0xBA18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT116_TOG + Miscellaneous Register + 0xBA1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST116 + Post Divider Register + 0xBA20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT116_SET + Post Divider Register + 0xBA24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT116_CLR + Post Divider Register + 0xBA28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT116_TOG + Post Divider Register + 0xBA2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE116 + Pre Divider Register + 0xBA30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT116_SET + Pre Divider Register + 0xBA34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT116_CLR + Pre Divider Register + 0xBA38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT116_TOG + Pre Divider Register + 0xBA3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL116 + Access Control Register + 0xBA70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT116_SET + Access Control Register + 0xBA74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT116_CLR + Access Control Register + 0xBA78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT116_TOG + Access Control Register + 0xBA7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT117 + Target Register + 0xBA80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT117_SET + Target Register + 0xBA84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT117_CLR + Target Register + 0xBA88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT117_TOG + Target Register + 0xBA8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC117 + Miscellaneous Register + 0xBA90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT117_SET + Miscellaneous Register + 0xBA94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT117_CLR + Miscellaneous Register + 0xBA98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT117_TOG + Miscellaneous Register + 0xBA9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST117 + Post Divider Register + 0xBAA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT117_SET + Post Divider Register + 0xBAA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT117_CLR + Post Divider Register + 0xBAA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT117_TOG + Post Divider Register + 0xBAAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE117 + Pre Divider Register + 0xBAB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT117_SET + Pre Divider Register + 0xBAB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT117_CLR + Pre Divider Register + 0xBAB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT117_TOG + Pre Divider Register + 0xBABC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL117 + Access Control Register + 0xBAF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT117_SET + Access Control Register + 0xBAF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT117_CLR + Access Control Register + 0xBAF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT117_TOG + Access Control Register + 0xBAFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT118 + Target Register + 0xBB00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT118_SET + Target Register + 0xBB04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT118_CLR + Target Register + 0xBB08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT118_TOG + Target Register + 0xBB0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC118 + Miscellaneous Register + 0xBB10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT118_SET + Miscellaneous Register + 0xBB14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT118_CLR + Miscellaneous Register + 0xBB18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT118_TOG + Miscellaneous Register + 0xBB1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST118 + Post Divider Register + 0xBB20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT118_SET + Post Divider Register + 0xBB24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT118_CLR + Post Divider Register + 0xBB28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT118_TOG + Post Divider Register + 0xBB2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE118 + Pre Divider Register + 0xBB30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT118_SET + Pre Divider Register + 0xBB34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT118_CLR + Pre Divider Register + 0xBB38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT118_TOG + Pre Divider Register + 0xBB3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL118 + Access Control Register + 0xBB70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT118_SET + Access Control Register + 0xBB74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT118_CLR + Access Control Register + 0xBB78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT118_TOG + Access Control Register + 0xBB7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT119 + Target Register + 0xBB80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT119_SET + Target Register + 0xBB84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT119_CLR + Target Register + 0xBB88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT119_TOG + Target Register + 0xBB8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC119 + Miscellaneous Register + 0xBB90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT119_SET + Miscellaneous Register + 0xBB94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT119_CLR + Miscellaneous Register + 0xBB98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT119_TOG + Miscellaneous Register + 0xBB9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST119 + Post Divider Register + 0xBBA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT119_SET + Post Divider Register + 0xBBA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT119_CLR + Post Divider Register + 0xBBA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT119_TOG + Post Divider Register + 0xBBAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE119 + Pre Divider Register + 0xBBB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT119_SET + Pre Divider Register + 0xBBB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT119_CLR + Pre Divider Register + 0xBBB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT119_TOG + Pre Divider Register + 0xBBBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL119 + Access Control Register + 0xBBF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT119_SET + Access Control Register + 0xBBF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT119_CLR + Access Control Register + 0xBBF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT119_TOG + Access Control Register + 0xBBFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT120 + Target Register + 0xBC00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT120_SET + Target Register + 0xBC04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT120_CLR + Target Register + 0xBC08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT120_TOG + Target Register + 0xBC0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC120 + Miscellaneous Register + 0xBC10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT120_SET + Miscellaneous Register + 0xBC14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT120_CLR + Miscellaneous Register + 0xBC18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT120_TOG + Miscellaneous Register + 0xBC1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST120 + Post Divider Register + 0xBC20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT120_SET + Post Divider Register + 0xBC24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT120_CLR + Post Divider Register + 0xBC28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT120_TOG + Post Divider Register + 0xBC2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE120 + Pre Divider Register + 0xBC30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT120_SET + Pre Divider Register + 0xBC34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT120_CLR + Pre Divider Register + 0xBC38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT120_TOG + Pre Divider Register + 0xBC3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL120 + Access Control Register + 0xBC70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT120_SET + Access Control Register + 0xBC74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT120_CLR + Access Control Register + 0xBC78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT120_TOG + Access Control Register + 0xBC7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT121 + Target Register + 0xBC80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT121_SET + Target Register + 0xBC84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT121_CLR + Target Register + 0xBC88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT121_TOG + Target Register + 0xBC8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC121 + Miscellaneous Register + 0xBC90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT121_SET + Miscellaneous Register + 0xBC94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT121_CLR + Miscellaneous Register + 0xBC98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT121_TOG + Miscellaneous Register + 0xBC9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST121 + Post Divider Register + 0xBCA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT121_SET + Post Divider Register + 0xBCA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT121_CLR + Post Divider Register + 0xBCA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT121_TOG + Post Divider Register + 0xBCAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE121 + Pre Divider Register + 0xBCB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT121_SET + Pre Divider Register + 0xBCB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT121_CLR + Pre Divider Register + 0xBCB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT121_TOG + Pre Divider Register + 0xBCBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL121 + Access Control Register + 0xBCF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT121_SET + Access Control Register + 0xBCF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT121_CLR + Access Control Register + 0xBCF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT121_TOG + Access Control Register + 0xBCFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT122 + Target Register + 0xBD00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT122_SET + Target Register + 0xBD04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT122_CLR + Target Register + 0xBD08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT122_TOG + Target Register + 0xBD0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC122 + Miscellaneous Register + 0xBD10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT122_SET + Miscellaneous Register + 0xBD14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT122_CLR + Miscellaneous Register + 0xBD18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT122_TOG + Miscellaneous Register + 0xBD1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST122 + Post Divider Register + 0xBD20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT122_SET + Post Divider Register + 0xBD24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT122_CLR + Post Divider Register + 0xBD28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT122_TOG + Post Divider Register + 0xBD2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE122 + Pre Divider Register + 0xBD30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT122_SET + Pre Divider Register + 0xBD34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT122_CLR + Pre Divider Register + 0xBD38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT122_TOG + Pre Divider Register + 0xBD3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL122 + Access Control Register + 0xBD70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT122_SET + Access Control Register + 0xBD74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT122_CLR + Access Control Register + 0xBD78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT122_TOG + Access Control Register + 0xBD7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT123 + Target Register + 0xBD80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT123_SET + Target Register + 0xBD84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT123_CLR + Target Register + 0xBD88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT123_TOG + Target Register + 0xBD8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC123 + Miscellaneous Register + 0xBD90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT123_SET + Miscellaneous Register + 0xBD94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT123_CLR + Miscellaneous Register + 0xBD98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT123_TOG + Miscellaneous Register + 0xBD9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST123 + Post Divider Register + 0xBDA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT123_SET + Post Divider Register + 0xBDA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT123_CLR + Post Divider Register + 0xBDA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT123_TOG + Post Divider Register + 0xBDAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE123 + Pre Divider Register + 0xBDB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT123_SET + Pre Divider Register + 0xBDB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT123_CLR + Pre Divider Register + 0xBDB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT123_TOG + Pre Divider Register + 0xBDBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL123 + Access Control Register + 0xBDF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT123_SET + Access Control Register + 0xBDF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT123_CLR + Access Control Register + 0xBDF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT123_TOG + Access Control Register + 0xBDFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT124 + Target Register + 0xBE00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT124_SET + Target Register + 0xBE04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT124_CLR + Target Register + 0xBE08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT124_TOG + Target Register + 0xBE0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC124 + Miscellaneous Register + 0xBE10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT124_SET + Miscellaneous Register + 0xBE14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT124_CLR + Miscellaneous Register + 0xBE18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT124_TOG + Miscellaneous Register + 0xBE1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST124 + Post Divider Register + 0xBE20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT124_SET + Post Divider Register + 0xBE24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT124_CLR + Post Divider Register + 0xBE28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT124_TOG + Post Divider Register + 0xBE2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE124 + Pre Divider Register + 0xBE30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT124_SET + Pre Divider Register + 0xBE34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT124_CLR + Pre Divider Register + 0xBE38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT124_TOG + Pre Divider Register + 0xBE3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL124 + Access Control Register + 0xBE70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT124_SET + Access Control Register + 0xBE74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT124_CLR + Access Control Register + 0xBE78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT124_TOG + Access Control Register + 0xBE7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT125 + Target Register + 0xBE80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT125_SET + Target Register + 0xBE84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT125_CLR + Target Register + 0xBE88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT125_TOG + Target Register + 0xBE8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC125 + Miscellaneous Register + 0xBE90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT125_SET + Miscellaneous Register + 0xBE94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT125_CLR + Miscellaneous Register + 0xBE98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT125_TOG + Miscellaneous Register + 0xBE9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST125 + Post Divider Register + 0xBEA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT125_SET + Post Divider Register + 0xBEA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT125_CLR + Post Divider Register + 0xBEA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT125_TOG + Post Divider Register + 0xBEAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE125 + Pre Divider Register + 0xBEB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT125_SET + Pre Divider Register + 0xBEB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT125_CLR + Pre Divider Register + 0xBEB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT125_TOG + Pre Divider Register + 0xBEBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL125 + Access Control Register + 0xBEF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT125_SET + Access Control Register + 0xBEF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT125_CLR + Access Control Register + 0xBEF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT125_TOG + Access Control Register + 0xBEFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT126 + Target Register + 0xBF00 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT126_SET + Target Register + 0xBF04 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT126_CLR + Target Register + 0xBF08 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT126_TOG + Target Register + 0xBF0C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC126 + Miscellaneous Register + 0xBF10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT126_SET + Miscellaneous Register + 0xBF14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT126_CLR + Miscellaneous Register + 0xBF18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT126_TOG + Miscellaneous Register + 0xBF1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST126 + Post Divider Register + 0xBF20 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT126_SET + Post Divider Register + 0xBF24 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT126_CLR + Post Divider Register + 0xBF28 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT126_TOG + Post Divider Register + 0xBF2C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE126 + Pre Divider Register + 0xBF30 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT126_SET + Pre Divider Register + 0xBF34 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT126_CLR + Pre Divider Register + 0xBF38 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT126_TOG + Pre Divider Register + 0xBF3C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL126 + Access Control Register + 0xBF70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT126_SET + Access Control Register + 0xBF74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT126_CLR + Access Control Register + 0xBF78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT126_TOG + Access Control Register + 0xBF7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT127 + Target Register + 0xBF80 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT127_SET + Target Register + 0xBF84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT127_CLR + Target Register + 0xBF88 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT127_TOG + Target Register + 0xBF8C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC127 + Miscellaneous Register + 0xBF90 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT127_SET + Miscellaneous Register + 0xBF94 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT127_CLR + Miscellaneous Register + 0xBF98 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT127_TOG + Miscellaneous Register + 0xBF9C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST127 + Post Divider Register + 0xBFA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT127_SET + Post Divider Register + 0xBFA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT127_CLR + Post Divider Register + 0xBFA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT127_TOG + Post Divider Register + 0xBFAC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE127 + Pre Divider Register + 0xBFB0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT127_SET + Pre Divider Register + 0xBFB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT127_CLR + Pre Divider Register + 0xBFB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT127_TOG + Pre Divider Register + 0xBFBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL127 + Access Control Register + 0xBFF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT127_SET + Access Control Register + 0xBFF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT127_CLR + Access Control Register + 0xBFF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT127_TOG + Access Control Register + 0xBFFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT128 + Target Register + 0xC000 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT128_SET + Target Register + 0xC004 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT128_CLR + Target Register + 0xC008 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT128_TOG + Target Register + 0xC00C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC128 + Miscellaneous Register + 0xC010 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT128_SET + Miscellaneous Register + 0xC014 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT128_CLR + Miscellaneous Register + 0xC018 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT128_TOG + Miscellaneous Register + 0xC01C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST128 + Post Divider Register + 0xC020 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT128_SET + Post Divider Register + 0xC024 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT128_CLR + Post Divider Register + 0xC028 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT128_TOG + Post Divider Register + 0xC02C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE128 + Pre Divider Register + 0xC030 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT128_SET + Pre Divider Register + 0xC034 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT128_CLR + Pre Divider Register + 0xC038 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT128_TOG + Pre Divider Register + 0xC03C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL128 + Access Control Register + 0xC070 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT128_SET + Access Control Register + 0xC074 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT128_CLR + Access Control Register + 0xC078 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT128_TOG + Access Control Register + 0xC07C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT129 + Target Register + 0xC080 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT129_SET + Target Register + 0xC084 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT129_CLR + Target Register + 0xC088 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT129_TOG + Target Register + 0xC08C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC129 + Miscellaneous Register + 0xC090 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT129_SET + Miscellaneous Register + 0xC094 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT129_CLR + Miscellaneous Register + 0xC098 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT129_TOG + Miscellaneous Register + 0xC09C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST129 + Post Divider Register + 0xC0A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT129_SET + Post Divider Register + 0xC0A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT129_CLR + Post Divider Register + 0xC0A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT129_TOG + Post Divider Register + 0xC0AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE129 + Pre Divider Register + 0xC0B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT129_SET + Pre Divider Register + 0xC0B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT129_CLR + Pre Divider Register + 0xC0B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT129_TOG + Pre Divider Register + 0xC0BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL129 + Access Control Register + 0xC0F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT129_SET + Access Control Register + 0xC0F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT129_CLR + Access Control Register + 0xC0F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT129_TOG + Access Control Register + 0xC0FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT130 + Target Register + 0xC100 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT130_SET + Target Register + 0xC104 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT130_CLR + Target Register + 0xC108 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT130_TOG + Target Register + 0xC10C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC130 + Miscellaneous Register + 0xC110 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT130_SET + Miscellaneous Register + 0xC114 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT130_CLR + Miscellaneous Register + 0xC118 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT130_TOG + Miscellaneous Register + 0xC11C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST130 + Post Divider Register + 0xC120 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT130_SET + Post Divider Register + 0xC124 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT130_CLR + Post Divider Register + 0xC128 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT130_TOG + Post Divider Register + 0xC12C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE130 + Pre Divider Register + 0xC130 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT130_SET + Pre Divider Register + 0xC134 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT130_CLR + Pre Divider Register + 0xC138 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT130_TOG + Pre Divider Register + 0xC13C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL130 + Access Control Register + 0xC170 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT130_SET + Access Control Register + 0xC174 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT130_CLR + Access Control Register + 0xC178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT130_TOG + Access Control Register + 0xC17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT131 + Target Register + 0xC180 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT131_SET + Target Register + 0xC184 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT131_CLR + Target Register + 0xC188 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT131_TOG + Target Register + 0xC18C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC131 + Miscellaneous Register + 0xC190 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT131_SET + Miscellaneous Register + 0xC194 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT131_CLR + Miscellaneous Register + 0xC198 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT131_TOG + Miscellaneous Register + 0xC19C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST131 + Post Divider Register + 0xC1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT131_SET + Post Divider Register + 0xC1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT131_CLR + Post Divider Register + 0xC1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT131_TOG + Post Divider Register + 0xC1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE131 + Pre Divider Register + 0xC1B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT131_SET + Pre Divider Register + 0xC1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT131_CLR + Pre Divider Register + 0xC1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT131_TOG + Pre Divider Register + 0xC1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL131 + Access Control Register + 0xC1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT131_SET + Access Control Register + 0xC1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT131_CLR + Access Control Register + 0xC1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT131_TOG + Access Control Register + 0xC1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT132 + Target Register + 0xC200 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT132_SET + Target Register + 0xC204 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT132_CLR + Target Register + 0xC208 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT132_TOG + Target Register + 0xC20C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC132 + Miscellaneous Register + 0xC210 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT132_SET + Miscellaneous Register + 0xC214 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT132_CLR + Miscellaneous Register + 0xC218 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT132_TOG + Miscellaneous Register + 0xC21C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST132 + Post Divider Register + 0xC220 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT132_SET + Post Divider Register + 0xC224 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT132_CLR + Post Divider Register + 0xC228 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT132_TOG + Post Divider Register + 0xC22C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE132 + Pre Divider Register + 0xC230 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT132_SET + Pre Divider Register + 0xC234 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT132_CLR + Pre Divider Register + 0xC238 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT132_TOG + Pre Divider Register + 0xC23C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL132 + Access Control Register + 0xC270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT132_SET + Access Control Register + 0xC274 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT132_CLR + Access Control Register + 0xC278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT132_TOG + Access Control Register + 0xC27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT133 + Target Register + 0xC280 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT133_SET + Target Register + 0xC284 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT133_CLR + Target Register + 0xC288 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT133_TOG + Target Register + 0xC28C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC133 + Miscellaneous Register + 0xC290 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT133_SET + Miscellaneous Register + 0xC294 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT133_CLR + Miscellaneous Register + 0xC298 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT133_TOG + Miscellaneous Register + 0xC29C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST133 + Post Divider Register + 0xC2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT133_SET + Post Divider Register + 0xC2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT133_CLR + Post Divider Register + 0xC2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT133_TOG + Post Divider Register + 0xC2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE133 + Pre Divider Register + 0xC2B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT133_SET + Pre Divider Register + 0xC2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT133_CLR + Pre Divider Register + 0xC2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT133_TOG + Pre Divider Register + 0xC2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL133 + Access Control Register + 0xC2F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT133_SET + Access Control Register + 0xC2F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT133_CLR + Access Control Register + 0xC2F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT133_TOG + Access Control Register + 0xC2FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT134 + Target Register + 0xC300 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT134_SET + Target Register + 0xC304 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT134_CLR + Target Register + 0xC308 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT134_TOG + Target Register + 0xC30C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC134 + Miscellaneous Register + 0xC310 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT134_SET + Miscellaneous Register + 0xC314 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT134_CLR + Miscellaneous Register + 0xC318 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT134_TOG + Miscellaneous Register + 0xC31C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST134 + Post Divider Register + 0xC320 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT134_SET + Post Divider Register + 0xC324 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT134_CLR + Post Divider Register + 0xC328 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT134_TOG + Post Divider Register + 0xC32C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE134 + Pre Divider Register + 0xC330 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT134_SET + Pre Divider Register + 0xC334 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT134_CLR + Pre Divider Register + 0xC338 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT134_TOG + Pre Divider Register + 0xC33C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL134 + Access Control Register + 0xC370 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT134_SET + Access Control Register + 0xC374 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT134_CLR + Access Control Register + 0xC378 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT134_TOG + Access Control Register + 0xC37C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT135 + Target Register + 0xC380 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT135_SET + Target Register + 0xC384 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT135_CLR + Target Register + 0xC388 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT135_TOG + Target Register + 0xC38C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC135 + Miscellaneous Register + 0xC390 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT135_SET + Miscellaneous Register + 0xC394 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT135_CLR + Miscellaneous Register + 0xC398 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT135_TOG + Miscellaneous Register + 0xC39C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST135 + Post Divider Register + 0xC3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT135_SET + Post Divider Register + 0xC3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT135_CLR + Post Divider Register + 0xC3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT135_TOG + Post Divider Register + 0xC3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE135 + Pre Divider Register + 0xC3B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT135_SET + Pre Divider Register + 0xC3B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT135_CLR + Pre Divider Register + 0xC3B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT135_TOG + Pre Divider Register + 0xC3BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL135 + Access Control Register + 0xC3F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT135_SET + Access Control Register + 0xC3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT135_CLR + Access Control Register + 0xC3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT135_TOG + Access Control Register + 0xC3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT136 + Target Register + 0xC400 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT136_SET + Target Register + 0xC404 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT136_CLR + Target Register + 0xC408 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT136_TOG + Target Register + 0xC40C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC136 + Miscellaneous Register + 0xC410 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT136_SET + Miscellaneous Register + 0xC414 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT136_CLR + Miscellaneous Register + 0xC418 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT136_TOG + Miscellaneous Register + 0xC41C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST136 + Post Divider Register + 0xC420 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT136_SET + Post Divider Register + 0xC424 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT136_CLR + Post Divider Register + 0xC428 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT136_TOG + Post Divider Register + 0xC42C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE136 + Pre Divider Register + 0xC430 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT136_SET + Pre Divider Register + 0xC434 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT136_CLR + Pre Divider Register + 0xC438 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT136_TOG + Pre Divider Register + 0xC43C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL136 + Access Control Register + 0xC470 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT136_SET + Access Control Register + 0xC474 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT136_CLR + Access Control Register + 0xC478 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT136_TOG + Access Control Register + 0xC47C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT137 + Target Register + 0xC480 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT137_SET + Target Register + 0xC484 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT137_CLR + Target Register + 0xC488 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT137_TOG + Target Register + 0xC48C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC137 + Miscellaneous Register + 0xC490 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT137_SET + Miscellaneous Register + 0xC494 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT137_CLR + Miscellaneous Register + 0xC498 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT137_TOG + Miscellaneous Register + 0xC49C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST137 + Post Divider Register + 0xC4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT137_SET + Post Divider Register + 0xC4A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT137_CLR + Post Divider Register + 0xC4A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT137_TOG + Post Divider Register + 0xC4AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE137 + Pre Divider Register + 0xC4B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT137_SET + Pre Divider Register + 0xC4B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT137_CLR + Pre Divider Register + 0xC4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT137_TOG + Pre Divider Register + 0xC4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL137 + Access Control Register + 0xC4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT137_SET + Access Control Register + 0xC4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT137_CLR + Access Control Register + 0xC4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT137_TOG + Access Control Register + 0xC4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT138 + Target Register + 0xC500 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT138_SET + Target Register + 0xC504 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT138_CLR + Target Register + 0xC508 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT138_TOG + Target Register + 0xC50C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC138 + Miscellaneous Register + 0xC510 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT138_SET + Miscellaneous Register + 0xC514 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT138_CLR + Miscellaneous Register + 0xC518 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT138_TOG + Miscellaneous Register + 0xC51C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST138 + Post Divider Register + 0xC520 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT138_SET + Post Divider Register + 0xC524 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT138_CLR + Post Divider Register + 0xC528 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT138_TOG + Post Divider Register + 0xC52C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE138 + Pre Divider Register + 0xC530 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT138_SET + Pre Divider Register + 0xC534 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT138_CLR + Pre Divider Register + 0xC538 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT138_TOG + Pre Divider Register + 0xC53C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL138 + Access Control Register + 0xC570 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT138_SET + Access Control Register + 0xC574 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT138_CLR + Access Control Register + 0xC578 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT138_TOG + Access Control Register + 0xC57C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT139 + Target Register + 0xC580 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT139_SET + Target Register + 0xC584 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT139_CLR + Target Register + 0xC588 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT139_TOG + Target Register + 0xC58C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC139 + Miscellaneous Register + 0xC590 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT139_SET + Miscellaneous Register + 0xC594 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT139_CLR + Miscellaneous Register + 0xC598 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT139_TOG + Miscellaneous Register + 0xC59C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST139 + Post Divider Register + 0xC5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT139_SET + Post Divider Register + 0xC5A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT139_CLR + Post Divider Register + 0xC5A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT139_TOG + Post Divider Register + 0xC5AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE139 + Pre Divider Register + 0xC5B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT139_SET + Pre Divider Register + 0xC5B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT139_CLR + Pre Divider Register + 0xC5B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT139_TOG + Pre Divider Register + 0xC5BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL139 + Access Control Register + 0xC5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT139_SET + Access Control Register + 0xC5F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT139_CLR + Access Control Register + 0xC5F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT139_TOG + Access Control Register + 0xC5FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT140 + Target Register + 0xC600 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT140_SET + Target Register + 0xC604 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT140_CLR + Target Register + 0xC608 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT140_TOG + Target Register + 0xC60C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC140 + Miscellaneous Register + 0xC610 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT140_SET + Miscellaneous Register + 0xC614 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT140_CLR + Miscellaneous Register + 0xC618 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT140_TOG + Miscellaneous Register + 0xC61C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST140 + Post Divider Register + 0xC620 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT140_SET + Post Divider Register + 0xC624 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT140_CLR + Post Divider Register + 0xC628 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT140_TOG + Post Divider Register + 0xC62C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE140 + Pre Divider Register + 0xC630 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT140_SET + Pre Divider Register + 0xC634 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT140_CLR + Pre Divider Register + 0xC638 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT140_TOG + Pre Divider Register + 0xC63C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL140 + Access Control Register + 0xC670 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT140_SET + Access Control Register + 0xC674 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT140_CLR + Access Control Register + 0xC678 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT140_TOG + Access Control Register + 0xC67C + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + TARGET_ROOT141 + Target Register + 0xC680 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT141_SET + Target Register + 0xC684 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT141_CLR + Target Register + 0xC688 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + TARGET_ROOT141_TOG + Target Register + 0xC68C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + PRE_PODF + Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM + 16 + 3 + read-write + + + PRE_PODF_0 + Divide by 1 + 0 + + + PRE_PODF_1 + Divide by 2 + 0x1 + + + PRE_PODF_2 + Divide by 3 + 0x2 + + + PRE_PODF_3 + Divide by 4 + 0x3 + + + PRE_PODF_4 + Divide by 5 + 0x4 + + + PRE_PODF_5 + Divide by 6 + 0x5 + + + PRE_PODF_6 + Divide by 7 + 0x6 + + + PRE_PODF_7 + Divide by 8 + 0x7 + + + + + MUX + Selection of clock sources This field is 1 bit long for DRAM and CORE + 24 + 3 + read-write + + + ENABLE + Enable this clock + 28 + 1 + read-write + + + ENABLE_0 + clock root is OFF + 0 + + + ENABLE_1 + clock root is ON + 0x1 + + + + + + + MISC141 + Miscellaneous Register + 0xC690 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT141_SET + Miscellaneous Register + 0xC694 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT141_CLR + Miscellaneous Register + 0xC698 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + MISC_ROOT141_TOG + Miscellaneous Register + 0xC69C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTHEN_FAIL + This sticky bit reflects access restricted by access control of this clock + 0 + 1 + read-write + + + TIMEOUT + This sticky bit reflects time out happened during accessing this clock + 4 + 1 + read-write + + + VIOLATE + This sticky bit reflects access violation in normal interface of this clock + 8 + 1 + read-write + + + + + POST141 + Post Divider Register + 0xC6A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT141_SET + Post Divider Register + 0xC6A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT141_CLR + Post Divider Register + 0xC6A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + POST_ROOT141_TOG + Post Divider Register + 0xC6AC + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_PODF + Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long + 0 + 6 + read-write + + + POST_PODF_0 + Divide by 1 + 0 + + + POST_PODF_1 + Divide by 2 + 0x1 + + + POST_PODF_2 + Divide by 3 + 0x2 + + + POST_PODF_3 + Divide by 4 + 0x3 + + + POST_PODF_4 + Divide by 5 + 0x4 + + + POST_PODF_5 + Divide by 6 + 0x5 + + + POST_PODF_63 + Divide by 64 + 0x3F + + + + + BUSY1 + Post divider is applying new set value + 7 + 1 + read-only + + + SELECT + Selection of pre clock branches This field is not applied in IP + 28 + 1 + read-write + + + SELECT_0 + select branch A + 0 + + + SELECT_1 + select branch B + 0x1 + + + + + BUSY2 + Clock switching multiplexer is applying new setting + 31 + 1 + read-only + + + + + PRE141 + Pre Divider Register + 0xC6B0 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT141_SET + Pre Divider Register + 0xC6B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT141_CLR + Pre Divider Register + 0xC6B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + PRE_ROOT141_TOG + Pre Divider Register + 0xC6BC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_PODF_B + Pre divider divide number for branch B Divider value is n + 1 + 0 + 3 + read-write + + + PRE_PODF_B_0 + Divide by 1 + 0 + + + PRE_PODF_B_1 + Divide by 2 + 0x1 + + + PRE_PODF_B_2 + Divide by 3 + 0x2 + + + PRE_PODF_B_3 + Divide by 4 + 0x3 + + + PRE_PODF_B_4 + Divide by 5 + 0x4 + + + PRE_PODF_B_5 + Divide by 6 + 0x5 + + + PRE_PODF_B_6 + Divide by 7 + 0x6 + + + PRE_PODF_B_7 + Divide by 8 + 0x7 + + + + + BUSY0 + Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM + 3 + 1 + read-only + + + MUX_B + Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 8 + 3 + read-write + + + EN_B + Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 12 + 1 + read-write + + + EN_B_0 + Clock shutdown + 0 + + + EN_B_1 + Clock ON + 0x1 + + + + + BUSY1 + EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM + 15 + 1 + read-only + + + PRE_PODF_A + Pre divider divide number for branch A Divider value is n + 1 + 16 + 3 + read-write + + + PRE_PODF_A_0 + Divide by 1 + 0 + + + PRE_PODF_A_1 + Divide by 2 + 0x1 + + + PRE_PODF_A_2 + Divide by 3 + 0x2 + + + PRE_PODF_A_3 + Divide by 4 + 0x3 + + + PRE_PODF_A_4 + Divide by 5 + 0x4 + + + PRE_PODF_A_5 + Divide by 6 + 0x5 + + + PRE_PODF_A_6 + Divide by 7 + 0x6 + + + PRE_PODF_A_7 + Divide by 8 + 0x7 + + + + + BUSY3 + Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM + 19 + 1 + read-only + + + MUX_A + Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM + 24 + 3 + read-write + + + EN_A + Branch A clock gate control This field applies to DRAM and DRAM_PHYM + 28 + 1 + read-write + + + EN_A_0 + Clock shutdown + 0 + + + EN_A_1 + clock ON + 0x1 + + + + + BUSY4 + EN_A field is applied to field This field applies to DRAM and DRAM_PHYM + 31 + 1 + read-only + + + + + ACCESS_CTRL141 + Access Control Register + 0xC6F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT141_SET + Access Control Register + 0xC6F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT141_CLR + Access Control Register + 0xC6F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + ACCESS_CTRL_ROOT141_TOG + Access Control Register + 0xC6FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DOMAIN0_INFO + Information from domain 0 to pass to others This field can only be changed by domain 0 + 0 + 4 + read-write + + + DOMAIN1_INFO + Information from domain 1 to pass to others This field can only be changed by domain 1 + 4 + 4 + read-write + + + DOMAIN2_INFO + Information from domain 2 to pass to others This field can only be changed by domain 2 + 8 + 4 + read-write + + + DOMAIN3_INFO + Information from domain 3 to pass to others This field can only be changed by domain 3 + 12 + 4 + read-write + + + OWNER_ID + Current domain that owns semaphore This field is meaningless when MUTEX is 0 + 16 + 2 + read-only + + + OWNER_ID_0 + domaino + 0 + + + OWNER_ID_1 + domain1 + 0x1 + + + OWNER_ID_2 + domain2 + 0x2 + + + OWNER_ID_3 + domain3 + 0x3 + + + + + MUTEX + Semaphore to control access + 20 + 1 + read-write + + + MUTEX_0 + Semaphore is free to take + 0 + + + MUTEX_1 + Semaphore is taken + 0x1 + + + + + DOMAIN0_WHITELIST + White list of domains that can change setting of this clock root + 24 + 1 + read-write + + + DOMAIN0_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN0_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN1_WHITELIST + White list of domains that can change setting of this clock root + 25 + 1 + read-write + + + DOMAIN1_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN1_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN2_WHITELIST + White list of domains that can change setting of this clock root + 26 + 1 + read-write + + + DOMAIN2_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN2_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + DOMAIN3_WHITELIST + White list of domains that can change setting of this clock root + 27 + 1 + read-write + + + DOMAIN3_WHITELIST_0 + Domain cannot change the setting + 0 + + + DOMAIN3_WHITELIST_1 + Domain can change the setting + 0x1 + + + + + SEMA_EN + Enable internal semaphore This field cannot be changed when lock bit is 1 + 28 + 1 + read-write + + + SEMA_EN_0 + Disable + 0 + + + SEMA_EN_1 + Enable + 0x1 + + + + + LOCK + Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset + 31 + 1 + read-write + + + LOCK_0 + Access control inactive + 0 + + + LOCK_1 + Access control active + 0x1 + + + + + + + + + SRC + SRC + SRC + SRC_ + 0x30390000 + + 0 + 0x1008 + registers + + + SRC + 89 + + + SRC_Combined + 94 + + + + SCR + SRC Reset Control Register + 0 + 32 + read-write + 0xA0 + 0xFFFFFFFF + + + MASK_TEMPSENSE_RESET + Mask tempsense_reset source + 4 + 4 + read-write + + + MASK_TEMPSENSE_RESET_5 + tempsense_reset is masked + 0x5 + + + MASK_TEMPSENSE_RESET_10 + tempsense_reset is not masked + 0xA + + + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + A53RCR0 + A53 Reset Control Register + 0x4 + 32 + read-write + 0xA0000 + 0xFFFFFFFF + + + A53_CORE_POR_RESET0 + POR reset for A53 core0 only + 0 + 1 + read-write + + + A53_CORE_POR_RESET0_0 + do not assert core0 reset + 0 + + + A53_CORE_POR_RESET0_1 + assert core0 reset + 0x1 + + + + + A53_CORE_POR_RESET1 + POR reset for A53 core1 only + 1 + 1 + read-write + + + A53_CORE_POR_RESET1_0 + do not assert core1 reset + 0 + + + A53_CORE_POR_RESET1_1 + assert core1 reset + 0x1 + + + + + A53_CORE_POR_RESET2 + POR reset for A53 core2 only + 2 + 1 + read-write + + + A53_CORE_POR_RESET2_0 + do not assert core2 reset + 0 + + + A53_CORE_POR_RESET2_1 + assert core2 reset + 0x1 + + + + + A53_CORE_POR_RESET3 + POR reset for A53 core3 only + 3 + 1 + read-write + + + A53_CORE_POR_RESET3_0 + do not assert core3 reset + 0 + + + A53_CORE_POR_RESET3_1 + assert core3 reset + 0x1 + + + + + A53_CORE_RESET0 + Software reset for core0 only + 4 + 1 + read-write + + + A53_CORE_RESET0_0 + do not assert core0 reset + 0 + + + A53_CORE_RESET0_1 + assert core0 reset + 0x1 + + + + + A53_CORE_RESET1 + Software reset for core1 only + 5 + 1 + read-write + + + A53_CORE_RESET1_0 + do not assert core1 reset + 0 + + + A53_CORE_RESET1_1 + assert core1 reset + 0x1 + + + + + A53_CORE_RESET2 + Software reset for core2 only + 6 + 1 + read-write + + + A53_CORE_RESET2_0 + do not assert core2 reset + 0 + + + A53_CORE_RESET2_1 + assert core2 reset + 0x1 + + + + + A53_CORE_RESET3 + Software reset for core3 only + 7 + 1 + read-write + + + A53_CORE_RESET3_0 + do not assert core3 reset + 0 + + + A53_CORE_RESET3_1 + assert core3 reset + 0x1 + + + + + A53_DBG_RESET0 + Software reset for core0 debug only + 8 + 1 + read-write + + + A53_DBG_RESET0_0 + do not assert core0 debug reset + 0 + + + A53_DBG_RESET0_1 + assert core0 debug reset + 0x1 + + + + + A53_DBG_RESET1 + Software reset for core1 debug only + 9 + 1 + read-write + + + A53_DBG_RESET1_0 + do not assert core1 debug reset + 0 + + + A53_DBG_RESET1_1 + assert core1 debug reset + 0x1 + + + + + A53_DBG_RESET2 + Software reset for core2 debug only + 10 + 1 + read-write + + + A53_DBG_RESET2_0 + do not assert core2 debug reset + 0 + + + A53_DBG_RESET2_1 + assert core2 debug reset + 0x1 + + + + + A53_DBG_RESET3 + Software reset for core3 debug only + 11 + 1 + read-write + + + A53_DBG_RESET3_0 + do not assert core3 debug reset + 0 + + + A53_DBG_RESET3_1 + assert core3 debug reset + 0x1 + + + + + A53_ETM_RESET0 + Software reset for core0 ETM only + 12 + 1 + read-write + + + A53_ETM_RESET0_0 + do not assert core0 ETM reset + 0 + + + A53_ETM_RESET0_1 + assert core0 ETM reset + 0x1 + + + + + A53_ETM_RESET1 + Software reset for core1 ETM only + 13 + 1 + read-write + + + A53_ETM_RESET1_0 + do not assert core1 ETM reset + 0 + + + A53_ETM_RESET1_1 + assert core1 ETM reset + 0x1 + + + + + A53_ETM_RESET2 + Software reset for core2 ETM only + 14 + 1 + read-write + + + A53_ETM_RESET2_0 + do not assert core2 ETM reset + 0 + + + A53_ETM_RESET2_1 + assert core2 ETM reset + 0x1 + + + + + A53_ETM_RESET3 + Software reset for core3 ETM only + 15 + 1 + read-write + + + A53_ETM_RESET3_0 + do not assert core3 ETM reset + 0 + + + A53_ETM_RESET3_1 + assert core3 ETM reset + 0x1 + + + + + MASK_WDOG1_RST + Mask wdog1_rst_b source + 16 + 4 + read-write + + + MASK_WDOG1_RST_5 + wdog1_rst_b is masked + 0x5 + + + MASK_WDOG1_RST_10 + wdog1_rst_b is not masked + 0xA + + + + + A53_SOC_DBG_RESET + Software reset for system level debug reset + 20 + 1 + read-write + + + A53_SOC_DBG_RESET_0 + do not assert system level debug reset + 0 + + + A53_SOC_DBG_RESET_1 + assert system level debug reset + 0x1 + + + + + A53_L2RESET + Software reset for A53 Snoop Control Unit (SCU) + 21 + 1 + read-write + + + A53_L2RESET_0 + do not assert SCU reset + 0 + + + A53_L2RESET_1 + assert SCU reset + 0x1 + + + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + A53RCR1 + A53 Reset Control Register + 0x8 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + A53_CORE0_ENABLE + Always 1, can't be changed. + 0 + 1 + read-only + + + A53_CORE1_ENABLE + core 1 enable + 1 + 1 + read-write + + + A53_CORE1_ENABLE_0 + core1 is disabled + 0 + + + A53_CORE1_ENABLE_1 + core1 is enabled + 0x1 + + + + + A53_CORE2_ENABLE + core 2 enable + 2 + 1 + read-write + + + A53_CORE2_ENABLE_0 + core2 is disabled + 0 + + + A53_CORE2_ENABLE_1 + core2 is enabled + 0x1 + + + + + A53_CORE3_ENABLE + core 3 enable + 3 + 1 + read-write + + + A53_CORE3_ENABLE_0 + core3 is disabled + 0 + + + A53_CORE3_ENABLE_1 + core3 is enabled + 0x1 + + + + + A53_RST_SLOW + no description available + 4 + 3 + read-write + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + M4RCR + M4 Reset Control Register + 0xC + 32 + read-write + 0xA8 + 0xFFFFFFFF + + + SW_M4C_NON_SCLR_RST + Non-self-clearing SW reset for M4 core + 0 + 1 + read-write + + + SW_M4C_NON_SCLR_RST_0 + do not assert M4 core reset + 0 + + + SW_M4C_NON_SCLR_RST_1 + assert M4 core reset + 0x1 + + + + + SW_M4C_RST + Self-clearing SW reset for M4 core This is a self clearing bit + 1 + 1 + read-write + + + SW_M4C_RST_0 + do not assert M4 core reset + 0 + + + SW_M4C_RST_1 + assert M4 core reset + 0x1 + + + + + SW_M4P_RST + Self-clearing SW reset for M4 platform This is a self clearing bit + 2 + 1 + read-write + + + SW_M4P_RST_0 + do not assert M4 platform reset + 0 + + + SW_M4P_RST_1 + assert M4 platform reset + 0x1 + + + + + ENABLE_M4 + Enable M4 + 3 + 1 + read-write + + + ENABLE_M4_0 + M4 is disabled + 0 + + + ENABLE_M4_1 + M4 is enabled + 0x1 + + + + + MASK_WDOG3_RST + Mask wdog3_rst_b source + 4 + 4 + read-write + + + MASK_WDOG3_RST_5 + wdog3_rst_b is masked + 0x5 + + + MASK_WDOG3_RST_10 + wdog3_rst_b is not masked + 0xA + + + + + WDOG3_RST_OPTION_M4 + Wdog3_rst_b option for M4. This bit is only effective when wdog3_rst_option is set to 1. + 8 + 1 + read-write + + + WDOG3_RST_OPTION_M4_0 + wdgo3_rst_b Reset M4 core only + 0 + + + WDOG3_RST_OPTION_M4_1 + Reset both M4 core and platform + 0x1 + + + + + WDOG3_RST_OPTION + Wdog3_rst_b option + 9 + 1 + read-write + + + WDOG3_RST_OPTION_0 + Wdog3_rst_b asserts M4 reset + 0 + + + WDOG3_RST_OPTION_1 + Wdog3_rst_b asserts global reset + 0x1 + + + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + USBOPHY1_RCR + USB OTG PHY1 Reset Control Register + 0x20 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + OTG1_PHY_RESET + no description available + 0 + 1 + read-write + + + OTG1_PHY_RESET_0 + Don't reset USB OTG1 PHY + 0 + + + OTG1_PHY_RESET_1 + Reset USB OTG1 PHY + 0x1 + + + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + USBOPHY2_RCR + USB OTG PHY2 Reset Control Register + 0x24 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + OTG2_PHY_RESET + no description available + 0 + 1 + read-write + + + OTG2_PHY_RESET_0 + Don't reset USB OTG2 PHY + 0 + + + OTG2_PHY_RESET_1 + Reset USB OTG2 PHY + 0x1 + + + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + MIPIPHY_RCR + MIPI PHY Reset Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + MIPI_DSI_RESET_BYTE_N + no description available + 1 + 1 + read-write + + + MIPI_DSI_RESET_BYTE_N_0 + Reset + 0 + + + MIPI_DSI_RESET_BYTE_N_1 + Don't reset + 0x1 + + + + + MIPI_DSI_RESET_N + no description available + 2 + 1 + read-write + + + MIPI_DSI_RESET_N_0 + Reset + 0 + + + MIPI_DSI_RESET_N_1 + Don't reset + 0x1 + + + + + MIPI_DIS_DPI_RESET_N + no description available + 3 + 1 + read-write + + + MIPI_DIS_DPI_RESET_N_0 + Reset + 0 + + + MIPI_DIS_DPI_RESET_N_1 + Don't reset + 0x1 + + + + + MIPI_DIS_ESC_RESET_N + no description available + 4 + 1 + read-write + + + MIPI_DIS_ESC_RESET_N_0 + Reset + 0 + + + MIPI_DIS_ESC_RESET_N_1 + Don't reset + 0x1 + + + + + MIPI_DIS_PCLK_RESET_N + no description available + 5 + 1 + read-write + + + MIPI_DIS_PCLK_RESET_N_0 + Reset + 0 + + + MIPI_DIS_PCLK_RESET_N_1 + Don't reset + 0x1 + + + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + PCIEPHY_RCR + PCIE PHY Reset Control Register + 0x2C + 32 + read-write + 0xA + 0xFFFFFFFF + + + PCIE_PHY_POWER_ON_RESET_N + PCIE_PHY_POWER_ON_RESET_N + 0 + 1 + read-write + + + PCIEPHY_G_RST + PCIE PHY Global Reset + 1 + 1 + read-write + + + PCIEPHY_BTN + PCIE PHY button + 2 + 1 + read-write + + + PCIEPHY_PERST + Pciephy_perst + 3 + 1 + read-write + + + PCIE_CTRL_APPS_CLK_REQ + Pcie_ctrl_app_clk_req_n + 4 + 1 + read-write + + + PCIE_CTRL_APPS_RST + Pcie_ctrl_app_init_rst + 5 + 1 + read-write + + + PCIE_CTRL_APPS_EN + Pcie_ctrl_app_ltssm_enable + 6 + 1 + read-write + + + PCIE_CTRL_APPS_READY + Pcie_ctrl_app_ready_entr_l23 + 7 + 1 + read-write + + + PCIE_CTRL_APPS_ENTER + Pcie_ctrl_app_req_entr_l1 + 8 + 1 + read-write + + + PCIE_CTRL_APPS_EXIT + Pcie_ctrl_app_req_exit_l1 + 9 + 1 + read-write + + + PCIE_CTRL_APPS_PME + Pcie_ctrl_apps_pm_xmt_pme + 10 + 1 + read-write + + + PCIE_CTRL_APPS_TURNOFF + Pcie_ctrl_apps_pm_xmt_turnoff + 11 + 1 + read-write + + + PCIE_CTRL_CFG_L1_AUX + Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en + 12 + 1 + read-write + + + PCIE_CTRL_SYS_INT + PCIE_CTRL_SYS_INT + 14 + 1 + read-write + + + PCIE_CTRL_APP_UNLOCK_MSG + PCIE_CTRL_APP_UNLOCK_MSG + 15 + 1 + read-write + + + PCIE_CTRL_APP_XFER_PENDING + PCIE_CTRL_APP_XFER_PENDING + 16 + 1 + read-write + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + HDMI_RCR + HDMI Reset Control Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HDMI_PHY_APB_RESET + Active 1 + 0 + 1 + read-write + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + DISP_RCR + DISP Reset Control Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + DISP_RESET + no description available + 0 + 1 + read-write + + + DISP_RESET_0 + Don't reset dispmix + 0 + + + DISP_RESET_1 + Reset dispmix + 0x1 + + + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + GPU_RCR + GPU Reset Control Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPU_RESET + GPU_RESET + 0 + 1 + read-write + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + VPU_RCR + VPU Reset Control Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + VPU_RESET + VPU_RESET + 0 + 1 + read-write + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + PCIE2_RCR + PCIE2 Reset Control Register + 0x48 + 32 + read-write + 0xA + 0xFFFFFFFF + + + PCIE_PHY_POWER_ON_RESET_N + PCIE_PHY_POWER_ON_RESET_N + 0 + 1 + read-write + + + PCIE_G_RST + PCIE Global Reset + 1 + 1 + read-write + + + PCIE_BTN + PCIE2 button + 2 + 1 + read-write + + + PCIE_PERST + Pcie_perst + 3 + 1 + read-write + + + PCIE_CTRL_APPS_CLK_REQ + Pcie_ctrl_app_clk_req_n + 4 + 1 + read-write + + + PCIE_CTRL_APPS_RST + Pcie_ctrl_app_init_rst + 5 + 1 + read-write + + + PCIE_CTRL_APPS_EN + Pcie_ctrl_app_ltssm_enable + 6 + 1 + read-write + + + PCIE_CTRL_APPS_READY + Pcie_ctrl_app_ready_entr_l23 + 7 + 1 + read-write + + + PCIE_CTRL_APPS_ENTER + Pcie_ctrl_app_req_entr_l1 + 8 + 1 + read-write + + + PCIE_CTRL_APPS_EXIT + Pcie_ctrl_app_req_exit_l1 + 9 + 1 + read-write + + + PCIE_CTRL_APPS_PME + Pcie_ctrl_apps_pm_xmt_pme + 10 + 1 + read-write + + + PCIE_CTRL_APPS_TURNOFF + Pcie_ctrl_apps_pm_xmt_turnoff + 11 + 1 + read-write + + + PCIE_CTRL_CFG_L1_AUX + Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en + 12 + 1 + read-write + + + PCIE_CTRL_SYS_INT + PCIE_CTRL_SYS_INT + 14 + 1 + read-write + + + PCIE_CTRL_APP_UNLOCK_MSG + PCIE_CTRL_APP_UNLOCK_MSG + 15 + 1 + read-write + + + PCIE_CTRL_APP_XFER_PENDING + PCIE_CTRL_APP_XFER_PENDING + 16 + 1 + read-write + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + MIPIPHY1_RCR + MIPI CSI1 PHY Reset Control Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + MIPI_CSI1_CORE_RESET + MIPI_CSI1_CORE_RESET + 0 + 1 + read-write + + + MIPI_CSI1_PHY_REF_RESET + MIPI_CSI1_PHY_REF_RESET + 1 + 1 + read-write + + + MIPI_CSI1_ESC_RESET + MIPI_CSI1_ESC_RESET + 2 + 1 + read-write + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + MIPIPHY2_RCR + MIPI CSI2 PHY Reset Control Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + MIPI_CSI2_CORE_RESET + MIPI_CSI2_CORE_RESET + 0 + 1 + read-write + + + MIPI_CSI2_PHY_REF_RESET + MIPI_CSI2_PHY_REF_RESET + 1 + 1 + read-write + + + MIPI_CSI2_ESC_RESET + MIPI_CSI2_ESC_RESET + 2 + 1 + read-write + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + SBMR1 + SRC Boot Mode Register 1 + 0x58 + 32 + read-only + 0 + 0xFFFFFFFF + + + BOOT_CFG + Refer to fusemap. + 0 + 32 + read-only + + + + + SRSR + SRC Reset Status Register + 0x5C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + csu_reset_b + Indicates whether the reset was the result of the csu_reset_b input + 2 + 1 + read-write + oneToClear + + + csu_reset_b_0 + Reset is not a result of the csu_reset_b event. + 0 + + + csu_reset_b_1 + Reset is a result of the csu_reset_b event. + 0x1 + + + + + ipp_user_reset_b + Indicates whether the reset was the result of the ipp_user_reset_b qualified reset. + 3 + 1 + read-write + oneToClear + + + ipp_user_reset_b_0 + Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + 0 + + + ipp_user_reset_b_1 + Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + 0x1 + + + + + wdog1_rst_b + IC Watchdog1 Time-out reset + 4 + 1 + read-write + oneToClear + + + wdog1_rst_b_0 + Reset is not a result of the watchdog1 time-out event. + 0 + + + wdog1_rst_b_1 + Reset is a result of the watchdog1 time-out event. + 0x1 + + + + + jtag_rst_b + HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG. + 5 + 1 + read-write + oneToClear + + + jtag_rst_b_0 + Reset is not a result of HIGH-Z reset from JTAG. + 0 + + + jtag_rst_b_1 + Reset is a result of HIGH-Z reset from JTAG. + 0x1 + + + + + jtag_sw_rst + JTAG software reset. Indicates whether the reset was the result of software reset from JTAG. + 6 + 1 + read-write + oneToClear + + + jtag_sw_rst_0 + Reset is not a result of software reset from JTAG. + 0 + + + jtag_sw_rst_1 + Reset is a result of software reset from JTAG. + 0x1 + + + + + wdog3_rst_b + IC Watchdog3 Time-out reset + 7 + 1 + read-write + oneToClear + + + wdog3_rst_b_0 + Reset is not a result of the watchdog3 time-out event. + 0 + + + wdog3_rst_b_1 + Reset is a result of the watchdog3 time-out event. + 0x1 + + + + + wdog4_rst_b + IC Watchdog4 Time-out reset + 8 + 1 + read-write + oneToClear + + + wdog4_rst_b_0 + Reset is not a result of the watchdog4 time-out event. + 0 + + + wdog4_rst_b_1 + Reset is a result of the watchdog4 time-out event. + 0x1 + + + + + tempsense_rst_b + Temper Sensor software reset + 9 + 1 + read-write + + + tempsense_rst_b_0 + Reset is not a result of software reset from Temperature Sensor. + 0 + + + tempsense_rst_b_1 + Reset is a result of software reset from Temperature Sensor. + 0x1 + + + + + + + SISR + SRC Interrupt Status Register + 0x68 + 32 + read-only + 0 + 0xFFFFFFFF + + + HSICPHY_PASSED_RESET + Interrupt generated to indicate that HSIC PHY passed software reset and is ready to be used + 1 + 1 + read-only + + + HSICPHY_PASSED_RESET_0 + Interrupt generated not due to HSIC PHY passed reset + 0 + + + HSICPHY_PASSED_RESET_1 + Interrupt generated due to HSIC PHY passed reset + 0x1 + + + + + OTGPHY1_PASSED_RESET + Interrupt generated to indicate that OTG PHY1 passed software reset and is ready to be used + 2 + 1 + read-only + + + OTGPHY1_PASSED_RESET_0 + Interrupt generated not due to OTG PHY1 passed reset + 0 + + + OTGPHY1_PASSED_RESET_1 + Interrupt generated due to OTG PHY1 passed reset + 0x1 + + + + + OTGPHY2_PASSED_RESET + Interrupt generated to indicate that OTG PHY2 passed software reset and is ready to be used + 3 + 1 + read-only + + + OTGPHY2_PASSED_RESET_0 + Interrupt generated not due to OTG PHY2 passed reset + 0 + + + OTGPHY2_PASSED_RESET_1 + Interrupt generated due to OTG PHY2 passed reset + 0x1 + + + + + MIPIPHY_PASSED_RESET + Interrupt generated to indicate that MIPI PHY passed software reset and is ready to be used + 4 + 1 + read-only + + + MIPIPHY_PASSED_RESET_0 + Interrupt generated not due to MIPI PHY passed reset + 0 + + + MIPIPHY_PASSED_RESET_1 + Interrupt generated due to MIPI PHY passed reset + 0x1 + + + + + PCIE1_PHY_PASSED_RESET + Interrupt generated to indicate that PCIE1 PHY passed software reset and is ready to be used + 5 + 1 + read-only + + + PCIE1_PHY_PASSED_RESET_0 + Interrupt generated not due to PCIE1 PHY passed reset + 0 + + + PCIE1_PHY_PASSED_RESET_1 + Interrupt generated due to PCIE1 PHY passed reset + 0x1 + + + + + HDMI_PASSED_RESET + Interrupt generated to indicate that HDMI passed software reset and is ready to be used + 6 + 1 + read-only + + + HDMI_PASSED_RESET_0 + Interrupt generated not due to HDMI passed reset + 0 + + + HDMI_PASSED_RESET_1 + Interrupt generated due to HDMI passed reset + 0x1 + + + + + DISPLAY_PASSED_RESET + Interrupt generated to indicate that DISPLAY passed software reset and is ready to be used + 7 + 1 + read-only + + + DISPLAY_PASSED_RESET_0 + Interrupt generated not due to DISPLAY passed reset + 0 + + + DISPLAY_PASSED_RESET_1 + Interrupt generated due to DISPLAY passed reset + 0x1 + + + + + M4C_PASSED_RESET + Interrupt generated to indicate that m4 core passed software reset and is ready to be used + 8 + 1 + read-only + + + M4C_PASSED_RESET_0 + interrupt generated not due to m4 core reset + 0 + + + M4C_PASSED_RESET_1 + interrupt generated due to m4 core reset + 0x1 + + + + + M4P_PASSED_RESET + Interrupt generated to indicate that m4 platform passed software reset and is ready to be used + 9 + 1 + read-only + + + M4P_PASSED_RESET_0 + interrupt generated not due to m4 platform reset + 0 + + + M4P_PASSED_RESET_1 + interrupt generated due to m4 platform reset + 0x1 + + + + + GPU_PASSED_RESET + Interrupt generated to indicate that GPU passed software reset and is ready to be used + 10 + 1 + read-only + + + GPU_PASSED_RESET_0 + interrupt generated not due to GPU reset + 0 + + + GPU_PASSED_RESET_1 + interrupt generated due to GPU reset + 0x1 + + + + + VPU_PASSED_RESET + Interrupt generated to indicate that VPU passed software reset and is ready to be used + 11 + 1 + read-only + + + VPU_PASSED_RESET_0 + interrupt generated not due to VPU reset + 0 + + + VPU_PASSED_RESET_1 + interrupt generated due to VPU reset + 0x1 + + + + + PCIE2_PHY_PASSED_RESET + Interrupt generated to indicate that PCIE2 PHY passed software reset and is ready to be used + 12 + 1 + read-only + + + PCIE2_PHY_PASSED_RESET_0 + interrupt generated not due to PCIE2 PHY reset + 0 + + + PCIE2_PHY_PASSED_RESET_1 + interrupt generated due to PCIE2 PHY reset + 0x1 + + + + + MIPI_CSI1_PHY_PASSED_RESET + Interrupt generated to indicate that MIPI CSI1 PHY passed software reset and is ready to be used + 13 + 1 + read-only + + + MIPI_CSI1_PHY_PASSED_RESET_0 + interrupt generated not due to MIPI CSI1 PHY reset + 0 + + + MIPI_CSI1_PHY_PASSED_RESET_1 + interrupt generated due to MIPI CSI1 PHY reset + 0x1 + + + + + MIPI_CSI2_PHY_PASSED_RESET + Interrupt generated to indicate that MIPI CSI2 PHY passed software reset and is ready to be used + 14 + 1 + read-only + + + MIPI_CSI2_PHY_PASSED_RESET_0 + interrupt generated not due to MIPI CSI2 PHY reset + 0 + + + MIPI_CSI2_PHY_PASSED_RESET_1 + interrupt generated due to MIPI CSI2 PHY reset + 0x1 + + + + + + + SIMR + SRC Interrupt Mask Register + 0x6C + 32 + read-write + 0x3FF + 0xFFFFFFFF + + + MASK_HSICPHY_PASSED_RESET + mask interrupt generation due to HSIC PHY passed reset + 1 + 1 + read-write + + + MASK_HSICPHY_PASSED_RESET_0 + do not mask interrupt due to HSIC PHY passed reset - interrupt will be created + 0 + + + MASK_HSICPHY_PASSED_RESET_1 + mask interrupt due to HSIC PHY passed reset + 0x1 + + + + + MASK_OTGPHY1_PASSED_RESET + mask interrupt generation due to OTG PHY1 passed reset + 2 + 1 + read-write + + + MASK_OTGPHY1_PASSED_RESET_0 + do not mask interrupt due to OTG PHY1 passed reset - interrupt will be created + 0 + + + MASK_OTGPHY1_PASSED_RESET_1 + mask interrupt due to OTG PHY1 passed reset + 0x1 + + + + + MASK_OTGPHY2_PASSED_RESET + mask interrupt generation due to OTG PHY2 passed reset + 3 + 1 + read-write + + + MASK_OTGPHY2_PASSED_RESET_0 + do not mask interrupt due to OTG PHY2 passed reset - interrupt will be created + 0 + + + MASK_OTGPHY2_PASSED_RESET_1 + mask interrupt due to OTG PHY2 passed reset + 0x1 + + + + + MASK_MIPIPHY_PASSED_RESET + mask interrupt generation due to MIPI PHY passed reset + 4 + 1 + read-write + + + MASK_MIPIPHY_PASSED_RESET_0 + do not mask interrupt due to MIPI PHY passed reset - interrupt will be created + 0 + + + MASK_MIPIPHY_PASSED_RESET_1 + mask interrupt due to MIPI PHY passed reset + 0x1 + + + + + MASK_PCIE1_PHY_PASSED_RESET + Mask interrupt generation due to PCIE1 PHY passed reset + 5 + 1 + read-write + + + MASK_PCIE1_PHY_PASSED_RESET_0 + do not mask interrupt due to PCIE1 PHY passed reset - interrupt will be created + 0 + + + MASK_PCIE1_PHY_PASSED_RESET_1 + mask interrupt due to PCIE1 PHY passed reset + 0x1 + + + + + MASK_HDMI_PASSED_RESET + Mask interrupt generation due to HDMI passed reset + 6 + 1 + read-write + + + MASK_HDMI_PASSED_RESET_0 + do not mask interrupt due to HDMI passed reset - interrupt will be created + 0 + + + MASK_HDMI_PASSED_RESET_1 + mask interrupt due to HDMI passed reset + 0x1 + + + + + MASK_DISPLAY_PASSED_RESET + Mask interrupt generation due to HDMI passed reset + 7 + 1 + read-write + + + MASK_DISPLAY_PASSED_RESET_0 + do not mask interrupt due to HDMI passed reset - interrupt will be created + 0 + + + MASK_DISPLAY_PASSED_RESET_1 + mask interrupt due to HDMI passed reset + 0x1 + + + + + MASK_M4C_PASSED_RESET + mask interrupt generation due to m4 core passed reset + 8 + 1 + read-write + + + MASK_M4C_PASSED_RESET_0 + do not mask interrupt due to m4 core passed reset - interrupt will be created + 0 + + + MASK_M4C_PASSED_RESET_1 + mask interrupt due to m4 core passed reset + 0x1 + + + + + MASK_M4P_PASSED_RESET + mask interrupt generation due to m4 platform passed reset + 9 + 1 + read-write + + + MASK_M4P_PASSED_RESET_0 + do not mask interrupt due to m4 platform passed reset - interrupt will be created + 0 + + + MASK_M4P_PASSED_RESET_1 + mask interrupt due to m4platform passed reset + 0x1 + + + + + MASK_GPU_PASSED_RESET + Mask interrupt generation due to GPU passed reset + 10 + 1 + read-write + + + MASK_GPU_PASSED_RESET_0 + do not mask interrupt due to GPU passed reset - interrupt will be created + 0 + + + MASK_GPU_PASSED_RESET_1 + mask interrupt due to GPU passed reset + 0x1 + + + + + MASK_VPU_PASSED_RESET + Mask interrupt generation due to VPU passed reset + 11 + 1 + read-write + + + MASK_VPU_PASSED_RESET_0 + do not mask interrupt due to VPU passed reset - interrupt will be created + 0 + + + MASK_VPU_PASSED_RESET_1 + mask interrupt due to VPU passed reset + 0x1 + + + + + MASK_PCIE2_PHY_PASSED_RESET + Mask interrupt generation due to PCIE2 PHY passed reset + 12 + 1 + read-write + + + MASK_PCIE2_PHY_PASSED_RESET_0 + do not mask interrupt due to PCIE2 PHY passed reset - interrupt will be created + 0 + + + MASK_PCIE2_PHY_PASSED_RESET_1 + mask interrupt due to PCIE2 PHY passed reset + 0x1 + + + + + MASK_MIPI_CSI1_PHY_PASSED_RESET + Mask interrupt generation due to MIPI CSI1 PHY passed reset + 13 + 1 + read-write + + + MASK_MIPI_CSI1_PHY_PASSED_RESET_0 + do not mask interrupt due to MIPI CSI1 PHY passed reset - interrupt will be created + 0 + + + MASK_MIPI_CSI1_PHY_PASSED_RESET_1 + mask interrupt due to MIPI CSI1 PHY passed reset + 0x1 + + + + + MASK_MIPI_CSI2_PHY_PASSED_RESET + Mask interrupt generation due to MIPI CSI2 PHY passed reset + 14 + 1 + read-write + + + MASK_MIPI_CSI2_PHY_PASSED_RESET_0 + do not mask interrupt due to MIPI CSI2 PHY passed reset - interrupt will be created + 0 + + + MASK_MIPI_CSI2_PHY_PASSED_RESET_1 + mask interrupt due to MIPI CSI2 PHY passed reset + 0x1 + + + + + + + SBMR2 + SRC Boot Mode Register 2 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEC_CONFIG + SECONFIG[1] shows the state of the SECONFIG[1] fuse + 0 + 2 + read-only + + + DIR_BT_DIS + DIR_BT_DIS shows the state of the DIR_BT_DIS fuse + 3 + 1 + read-only + + + BT_FUSE_SEL + BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse + 4 + 1 + read-only + + + FUSE_FORCE_COLD_BOOT + See Fusemap for additional informtation. + 5 + 1 + read-write + + + BMOD + BMOD shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B + 24 + 2 + read-only + + + + + GPR1 + SRC General Purpose Register 1 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ENTRY0 + Holds entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR2 + SRC General Purpose Register 2 + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ARG0 + Holds argument of entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR3 + SRC General Purpose Register 3 + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ENTRY1 + Holds entry function for core1 + 0 + 32 + read-write + + + + + GPR4 + SRC General Purpose Register 4 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ARG1 + Holds argument of entry function for core1 + 0 + 32 + read-write + + + + + GPR5 + SRC General Purpose Register 5 + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ENTRY2 + Holds entry function for core2 + 0 + 32 + read-write + + + + + GPR6 + SRC General Purpose Register 6 + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ARG2 + Holds argument of entry function for core2 + 0 + 32 + read-write + + + + + GPR7 + SRC General Purpose Register 7 + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ENTRY3 + Holds entry function for core3 + 0 + 32 + read-write + + + + + GPR8 + SRC General Purpose Register 8 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ARG3 + Holds argument of entry function for core3 + 0 + 32 + read-write + + + + + GPR9 + SRC General Purpose Register 9 + 0x94 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR10 + SRC General Purpose Register 10 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DDRC_RCR + SRC DDR Controller Reset Control Register + 0x1000 + 32 + read-write + 0xF + 0xFFFFFFFF + + + DDRC1_PRST + DDR Controller preset and DDR PHY reset + 0 + 1 + read-write + + + DDRC1_PRST_0 + De-ssert DDR Controller preset and DDR PHY reset reset + 0 + + + DDRC1_PRST_1 + Assert DDR Controller preset and DDR PHY reset + 0x1 + + + + + DDRC1_CORE_RST + DDR Controller core_ddrc_rstn and aresetn + 1 + 1 + read-write + + + DDRC1_CORE_RST_0 + De-ssert DDR controller aresetn and core_ddrc_rstn + 0 + + + DDRC1_CORE_RST_1 + Assert DDR Controller preset and DDR PHY reset + 0x1 + + + + + DDRC1_PHY_RESET + no description available + 2 + 1 + read-write + + + DDRC1_PHY_RESET_0 + De-ssert DDR controller + 0 + + + DDRC1_PHY_RESET_1 + Assert DDR Controller + 0x1 + + + + + DDRC1_PHY_PWROKIN + no description available + 3 + 1 + read-write + + + DDRC1_PHY_PWROKIN_0 + De-ssert DDR controller + 0 + + + DDRC1_PHY_PWROKIN_1 + Assert DDR Controller + 0x1 + + + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + DDRC2_RCR + SRC DDRC2 Controller Reset Control Register + 0x1004 + 32 + read-write + 0xF + 0xFFFFFFFF + + + DDRC2_PRST + DDRC2 Controller preset and DDR PHY reset + 0 + 1 + read-write + + + DDRC2_PRST_0 + De-ssert DDRC2 Controller preset and DDR PHY reset reset + 0 + + + DDRC2_PRST_1 + Assert DDRC2 Controller preset and DDR PHY reset + 0x1 + + + + + DDRC2_CORE_RST + DDRC2 Controller core_ddrc_rstn and aresetn + 1 + 1 + read-write + + + DDRC2_CORE_RST_0 + De-ssert DDR controller aresetn and core_ddrc_rstn + 0 + + + DDRC2_CORE_RST_1 + Assert DDR Controller preset and DDR PHY reset + 0x1 + + + + + DDRC1_PHY_RESET + no description available + 2 + 1 + read-write + + + DDRC1_PHY_RESET_0 + De-ssert DDR controller + 0 + + + DDRC1_PHY_RESET_1 + Assert DDR Controller + 0x1 + + + + + DDRC1_PHY_PWROKIN + no description available + 3 + 1 + read-write + + + DDRC1_PHY_PWROKIN_0 + De-ssert DDR controller + 0 + + + DDRC1_PHY_PWROKIN_1 + Assert DDR Controller + 0x1 + + + + + DOMAIN0 + Domain0 assignment control. Effective when dom_en is set to 1. + 24 + 1 + read-write + + + DOMAIN0_0 + This register is not assigned to domain0. The master from domain3 cannot write to this register. + 0 + + + DOMAIN0_1 + This register is assigned to domain0. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN1 + Domain1 assignment control. Effective when dom_en is set to 1. + 25 + 1 + read-write + + + DOMAIN1_0 + This register is not assigned to domain1. The master from domain3 cannot write to this register. + 0 + + + DOMAIN1_1 + This register is assigned to domain1. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN2 + Domain2 assignment control. Effective when dom_en is set to 1. + 26 + 1 + read-write + + + DOMAIN2_0 + This register is not assigned to domain2. The master from domain3 cannot write to this register. + 0 + + + DOMAIN2_1 + This register is assigned to domain2. The master from domain3 can write to this register + 0x1 + + + + + DOMAIN3 + Domain3 assignment control. Effective when dom_en is set to 1. + 27 + 1 + read-write + + + DOMAIN3_0 + This register is not assigned to domain3. The master from domain3 cannot write to this register. + 0 + + + DOMAIN3_1 + This register is assigned to domain3. The master from domain3 can write to this register + 0x1 + + + + + LOCK + Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0 + 30 + 1 + read-write + + + LOCK_0 + [31] and [27:24] bits can be modified + 0 + + + LOCK_1 + [31] and [27:24] bits cannot be modified + 0x1 + + + + + DOM_EN + Domain Control enable for this register + 31 + 1 + read-write + + + DOM_EN_0 + Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters + 0 + + + DOM_EN_1 + Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. + 0x1 + + + + + + + + + GPC + GPC + GPC + GPC_ + 0x303A0000 + + 0 + 0x250 + registers + + + GPC + 87 + + + + LPCR_A53_BSC + Basic Low power control register of A53 platform + 0 + 32 + read-write + 0x3FF0 + 0xFFFFFFFF + + + LPM0 + CORE0 Setting the low power mode that system will enter on next assertion of dsm_request signal. + 0 + 2 + read-write + + + LPM0_0 + Remain in RUN mode + 0 + + + LPM0_1 + Transfer to WAIT mode + 0x1 + + + LPM0_2 + Transfer to STOP mode + 0x2 + + + + + LPM1 + CORE1 Setting the low power mode that system will enter on next assertion of dsm_request signal. + 2 + 2 + read-write + + + LPM1_0 + Remain in RUN mode + 0 + + + LPM1_1 + Transfer to WAIT mode + 0x1 + + + LPM1_2 + Transfer to STOP mode + 0x2 + + + + + MST_LPM_HSK_MASK + MASTER0 LPM handshake mask + 6 + 1 + read-write + + + MST_LPM_HSK_MASK_0 + enable MASTER0 LPM handshake, wait ACK from MASTER0 + 0 + + + MST_LPM_HSK_MASK_1 + disable MASKTER0 LPM handshake, mask ACK from MASTER0 + 0x1 + + + + + CPU_CLK_ON_LPM + Define if A53 clocks will be disabled on wait/stop mode. + 14 + 1 + read-write + + + CPU_CLK_ON_LPM_0 + A53 clock disabled on wait/stop mode + 0 + + + CPU_CLK_ON_LPM_1 + A53 clock enabled on wait/stop mode + 0x1 + + + + + MASK_CORE0_WFI + CORE0 Wait For Interrupt Mask + 16 + 1 + read-write + + + MASK_CORE0_WFI_0 + WFI for CORE0 is not masked + 0 + + + MASK_CORE0_WFI_1 + WFI for CORE0 is masked + 0x1 + + + + + MASK_CORE1_WFI + CORE1 Wait For Interrupt Mask + 17 + 1 + read-write + + + MASK_CORE1_WFI_0 + WFI for CORE1 is not masked + 0 + + + MASK_CORE1_WFI_1 + WFI for CORE1 is masked + 0x1 + + + + + MASK_CORE2_WFI + CORE2 Wait For Interrupt Mask + 18 + 1 + read-write + + + MASK_CORE2_WFI_0 + WFI for CORE2 is not masked + 0 + + + MASK_CORE2_WFI_1 + WFI for CORE2 is masked + 0x1 + + + + + MASK_CORE3_WFI + CORE3 Wait For Interrupt Mask + 19 + 1 + read-write + + + MASK_CORE3_WFI_0 + WFI for CORE3 is not masked + 0 + + + MASK_CORE3_WFI_1 + WFI for CORE3 is masked + 0x1 + + + + + IRQ_SRC_C2 + LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2], LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide the wake up source for A53 LPM and core0/core1/core2/core3 power + 22 + 1 + read-write + + + IRQ_SRC_C2_0 + core2 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more specific information. + 0 + + + IRQ_SRC_C2_1 + core2 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during low power mode when this bit is set to 1'b1. + 0x1 + + + + + IRQ_SRC_C3 + LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2], LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide the wake up source for A53 LPM and core0/core1/core2/core3 power + 23 + 1 + read-write + + + IRQ_SRC_C3_0 + core3 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more specific information. + 0 + + + IRQ_SRC_C3_1 + core3 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during low power mode when this bit is set to 1'b1. + 0x1 + + + + + MASK_SCU_WFI + SCU Wait For Interrupt Mask Register + 24 + 1 + read-write + + + MASK_SCU_WFI_0 + WFI for SCU is not masked + 0 + + + MASK_SCU_WFI_1 + WFI for SCU is masked + 0x1 + + + + + MASK_L2CC_WFI + L2 cache controller Wait For Interrupt Mask Register + 26 + 1 + read-write + + + MASK_L2CC_WFI_0 + WFI for L2 cache controller is not masked + 0 + + + MASK_L2CC_WFI_1 + WFI for L2 cache controller is masked + 0x1 + + + + + IRQ_SRC_C0 + LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2], LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide the wake up source for A53 LPM and core0/core1/core2/core3 power + 28 + 1 + read-write + + + IRQ_SRC_C0_0 + core0 wakeup source from external INT[127:0], masked by IMR0 refer to "Power up process for A53 platform" for more specific information + 0 + + + IRQ_SRC_C0_1 + core0 wakeup source from GIC(nFIQ[0]/nIRQ[0] ), SCU should not be power down during low power mode when this bit is set to 1'b1 + 0x1 + + + + + IRQ_SRC_C1 + LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2], LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide the wake up source for A53 LPM and core0/core1/core2/core3 power + 29 + 1 + read-write + + + IRQ_SRC_C1_0 + core1 wakeup source from external INT[127:0], masked by IMR1 refer to "Power up process for A53 platform" for more specific information + 0 + + + IRQ_SRC_C1_1 + core1 wakeup source from GIC(nFIQ[1]/nIRQ[1] ), SCU should not be power down during low power mode when this bit is set to 1'b1 + 0x1 + + + + + IRQ_SRC_A53_WUP + LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2], LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide the wake up source for A53 LPM and core0/core1/core2/core3 power + 30 + 1 + read-write + + + IRQ_SRC_A53_WUP_0 + LPM wakeup source be "OR" result of LPCR_A53_BSC[IRQ_SRC_C0]/LPCR_A53_BSC[IRQ_SRC_C1]/LPCR_A53_BSC[IRQ_SRC_C2]/LPCR_A53_BSC[IRQ_SRC_C3] setting + 0 + + + IRQ_SRC_A53_WUP_1 + LPM wakeup source from external INT[127:0], masked by IMR0 + 0x1 + + + + + MASK_DSM_TRIGGER + DSM Trigger Mask + 31 + 1 + read-write + + + MASK_DSM_TRIGGER_0 + DSM trigger of A53 platform will not be masked + 0 + + + MASK_DSM_TRIGGER_1 + DSM trigger of A53 platform will be masked + 0x1 + + + + + + + LPCR_A53_AD + Advanced Low power control register of A53 platform + 0x4 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + EN_C0_WFI_PDN + no description available + 0 + 1 + read-write + + + EN_C0_WFI_PDN_0 + CORE0 will not be power down with WFI request + 0 + + + EN_C0_WFI_PDN_1 + CORE0 will be power down with WFI request + 0x1 + + + + + EN_C0_PDN + no description available + 1 + 1 + read-write + + + EN_C0_PDN_0 + CORE0 will not be power down with low power mode request + 0 + + + EN_C0_PDN_1 + CORE0 will be power down with low power mode request + 0x1 + + + + + EN_C1_WFI_PDN + no description available + 2 + 1 + read-write + + + EN_C1_WFI_PDN_0 + CORE1 will not be power down with WFI request + 0 + + + EN_C1_WFI_PDN_1 + CORE1 will be power down with WFI request + 0x1 + + + + + EN_C1_PDN + no description available + 3 + 1 + read-write + + + EN_C1_PDN_0 + CORE1 will not be power down with low power mode request + 0 + + + EN_C1_PDN_1 + CORE1 will be power down with low power mode request + 0x1 + + + + + EN_PLAT_PDN + no description available + 4 + 1 + read-write + + + EN_PLAT_PDN_0 + SCU and L2 cache RAM will not be power down with low power mode request + 0 + + + EN_PLAT_PDN_1 + SCU and L2 cache RAM will be power down with low power mode request + 0x1 + + + + + EN_C0_IRQ_PUP + no description available + 8 + 1 + read-write + + + EN_C0_IRQ_PUP_0 + CORE0 will power up with IRQ request + 0 + + + EN_C0_IRQ_PUP_1 + CORE0 will not power up with IRQ request + 0x1 + + + + + EN_C0_PUP + (only used wake up from CPU01_OFF mode) + 9 + 1 + read-write + + + EN_C0_PUP_0 + CORE0 will power up with low power mode request + 0 + + + EN_C0_PUP_1 + CORE0 will not power up with low power mode request + 0x1 + + + + + EN_C1_IRQ_PUP + no description available + 10 + 1 + read-write + + + EN_C1_IRQ_PUP_0 + CORE1 will power up with IRQ request + 0 + + + EN_C1_IRQ_PUP_1 + CORE1 will not power up with IRQ request + 0x1 + + + + + EN_C1_PUP + no description available + 11 + 1 + read-write + + + EN_C1_PUP_0 + CORE1 will not power up with low power mode request (only used wake up from CPU01_OFF mode) + 0 + + + EN_C1_PUP_1 + CORE1 will power up with low power mode request + 0x1 + + + + + EN_C2_WFI_PDN + no description available + 16 + 1 + read-write + + + EN_C2_WFI_PDN_0 + CORE2 will not be power down with WFI request + 0 + + + EN_C2_WFI_PDN_1 + CORE2 will be power down with WFI request + 0x1 + + + + + EN_C2_PDN + no description available + 17 + 1 + read-write + + + EN_C2_PDN_0 + CORE2 will not be power down with low power mode request + 0 + + + EN_C2_PDN_1 + CORE2 will be power down with low power mode request + 0x1 + + + + + EN_C3_WFI_PDN + no description available + 18 + 1 + read-write + + + EN_C3_WFI_PDN_0 + CORE3 will not be power down with WFI request + 0 + + + EN_C3_WFI_PDN_1 + CORE3 will be power down with WFI request + 0x1 + + + + + EN_C3_PDN + no description available + 19 + 1 + read-write + + + EN_C3_PDN_0 + CORE3 will not be power down with low power mode request + 0 + + + EN_C3_PDN_1 + CORE3 will be power down with low power mode request + 0x1 + + + + + EN_C0_WFI_PDN_DIS + no description available + 20 + 1 + read-write + + + EN_C0_WFI_PDN_DIS_0 + Disnable WFI power down core0 + 0 + + + EN_C0_WFI_PDN_DIS_1 + Enable WFI power down core0 + 0x1 + + + + + EN_C1_WFI_PDN_DIS + no description available + 21 + 1 + read-write + + + EN_C1_WFI_PDN_DIS_0 + Disnable WFI power down core1 + 0 + + + EN_C1_WFI_PDN_DIS_1 + Enable WFI power down core1 + 0x1 + + + + + EN_C2_WFI_PDN_DIS + no description available + 22 + 1 + read-write + + + EN_C2_WFI_PDN_DIS_0 + Disnable WFI power down core2 + 0 + + + EN_C2_WFI_PDN_DIS_1 + Enable WFI power down core2 + 0x1 + + + + + EN_C3_WFI_PDN_DIS + no description available + 23 + 1 + read-write + + + EN_C3_WFI_PDN_DIS_0 + Disnable WFI power down core3 + 0 + + + EN_C3_WFI_PDN_DIS_1 + Enable WFI power down core3 + 0x1 + + + + + EN_C2_IRQ_PUP + no description available + 24 + 1 + read-write + + + EN_C2_IRQ_PUP_0 + CORE2 will power up with IRQ request + 0 + + + EN_C2_IRQ_PUP_1 + CORE2 will not power up with IRQ request + 0x1 + + + + + EN_C2_PUP + no description available + 25 + 1 + read-write + + + EN_C2_PUP_0 + CORE2 will power up with lower power mode request + 0 + + + EN_C2_PUP_1 + CORE2 will not power up with low power mode request (only used wake up from CPU_OFF) + 0x1 + + + + + EN_C3_IRQ_PUP + no description available + 26 + 1 + read-write + + + EN_C3_IRQ_PUP_0 + CORE3 will power up with IRQ request + 0 + + + EN_C3_IRQ_PUP_1 + CORE3 will not power up with IRQ request + 0x1 + + + + + EN_C3_PUP + no description available + 27 + 1 + read-write + + + EN_C3_PUP_0 + CORE3 will power up with lower power mode request + 0 + + + EN_C3_PUP_1 + CORE3 will not power up with low power mode request (only used wake up from CPU_OFF) + 0x1 + + + + + L2PGE + no description available + 31 + 1 + read-write + + + L2PGE_0 + L2 cache RAM will power down with SCU power domain in A53 platform (used for ALL_OFF mode) + 0 + + + L2PGE_1 + L2 cache RAM will not power down with SCU power domain in A53 platform (used for ALL_OFF mode) + 0x1 + + + + + + + LPCR_M4 + Low power control register of CPU1 + 0x8 + 32 + read-write + 0x3FF0 + 0xFFFFFFFF + + + LPM0 + Setting the low power mode that system will enter on next assertion of dsm_request signal. + 0 + 2 + read-write + + + LPM0_0 + Remain in RUN mode + 0 + + + LPM0_1 + Transfer to WAIT mode + 0x1 + + + LPM0_2 + Transfer to STOP mode + 0x2 + + + + + EN_M4_PDN + Enable m4 virtual PGC power down with LPM enter + 2 + 1 + read-write + + + EN_M4_PUP + Enable m4 virtual PGC power up with LPM enter + 3 + 1 + read-write + + + CPU_CLK_ON_LPM + Define if M4 clocks will be disabled on wait/stop mode. + 14 + 1 + read-write + + + CPU_CLK_ON_LPM_0 + M4 clock disabled on wait/stop mode. + 0 + + + CPU_CLK_ON_LPM_1 + M4 clock enabled on wait/stop mode. + 0x1 + + + + + MASK_M4_WFI + M4 WFI Mask + 16 + 1 + read-write + + + MASK_M4_WFI_0 + WFI for M4 is not masked + 0 + + + MASK_M4_WFI_1 + WFI for M4 is masked + 0x1 + + + + + MASK_DSM_TRIGGER + M4 WFI Mask + 31 + 1 + read-write + + + MASK_DSM_TRIGGER_0 + DSM trigger of M4 platform will not be masked + 0 + + + MASK_DSM_TRIGGER_1 + DSM trigger of M4 platform will be masked + 0x1 + + + + + + + SLPCR + System low power control register + 0x14 + 32 + read-write + 0xE000FF82 + 0xFFFFFFFF + + + BYPASS_PMIC_READY + By asserting this bit GPC will bypass waiting for PMIC_READY signal when coming out of DSM + 0 + 1 + read-write + + + BYPASS_PMIC_READY_0 + Don't bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby voltage was enabled + 0 + + + BYPASS_PMIC_READY_1 + Bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby voltage was enabled + 0x1 + + + + + SBYOS + Standby clock oscillator bit + 1 + 1 + read-write + + + SBYOS_0 + On chip oscillator will not be powered down, after next entrance to DSM. + 0 + + + SBYOS_1 + On chip oscillator will be powered down, after next entrance to DSM. When returning from DSM, external oscillator will be enabled again, on chip oscillator will return to oscillator mode , and after oscnt count GPC will continue with the exit from DSM process. + 0x1 + + + + + VSTBY + Voltage standby request bit + 2 + 1 + read-write + + + VSTBY_0 + Voltage will not be changed to standby voltage after next entrance to stop mode. (PMIC_STBY_REQ will remain negated - '0') + 0 + + + VSTBY_1 + Voltage will be changed to standby voltage after next entrance to stop mode. + 0x1 + + + + + STBY_COUNT + Standby counter definition + 3 + 3 + read-write + + + STBY_COUNT_0 + GPC will wait 4 ckil clock cycles + 0 + + + STBY_COUNT_1 + GPC will wait 8 ckil clock cycles + 0x1 + + + STBY_COUNT_2 + GPC will wait 16 ckil clock cycles + 0x2 + + + STBY_COUNT_3 + GPC will wait 32 ckil clock cycles + 0x3 + + + STBY_COUNT_4 + GPC will wait 64 ckil clock cycles + 0x4 + + + STBY_COUNT_5 + GPC will wait 128 ckil clock cycles + 0x5 + + + STBY_COUNT_6 + GPC will wait 256 ckil clock cycles + 0x6 + + + STBY_COUNT_7 + GPC will wait 512 ckil clock cycles + 0x7 + + + + + COSC_PWRDOWN + In run mode, software can manually control powering down of on chip oscillator, i + 6 + 1 + read-write + + + COSC_PWRDOWN_0 + On-chip oscillator will not be powered down, i.e. cosc_pwrdown = 0 + 0 + + + COSC_PWRDOWN_1 + On-chip oscillator will be powered down, i.e. cosc_pwrdown = 1 + 0x1 + + + + + COSC_EN + On-chip oscillator enable bit - this bit value is reflected on the output cosc_en + 7 + 1 + read-write + + + COSC_EN_0 + Disable on-chip oscillator + 0 + + + COSC_EN_1 + Enable on-chip oscillator + 0x1 + + + + + OSCCNT + Oscillator ready counter value + 8 + 8 + read-write + + + OSCCNT_0 + count 1 ckil + 0 + + + OSCCNT_255 + count 256 ckils + 0xFF + + + + + EN_A53_FASTWUP_WAIT_MODE + Enable A53 fast wake up wait mode, relevant PLLs will not be closed in this mode. + 16 + 1 + read-write + + + EN_A53_FASTWUP_STOP_MODE + Enable A53 fast wake up stop mode, relevant PLLs will not be closed in this mode. + 17 + 1 + read-write + + + EN_M4_FASTWUP_WAIT_MODE + Enable M4 fast wake up wait mode, relevant PLLs will not be closed in this mode. + 18 + 1 + read-write + + + EN_M4_FASTWUP_STOP_MODE + Enable M4 fast wake up stop mode, relevant PLLs will not be closed in this mode. + 19 + 1 + read-write + + + DISABLE_A53_IS_DSM + no description available + 23 + 1 + read-write + + + DISABLE_A53_IS_DSM_0 + Enable A53 isolation signal in DSM + 0 + + + DISABLE_A53_IS_DSM_1 + Disable A53 isolation signal in DSM + 0x1 + + + + + REG_BYPASS_COUNT + Counter for REG_BYPASS signal assertion after standby voltage request by PMIC_STBY_REQ. + 24 + 6 + read-write + + + REG_BYPASS_COUNT_0 + no delay + 0 + + + REG_BYPASS_COUNT_1 + 1 CKIL clock period delay + 0x1 + + + REG_BYPASS_COUNT_63 + 63 CKIL clock period delay + 0x3F + + + + + RBC_EN + Enable for REG_BYPASS_COUNTER + 30 + 1 + read-write + + + RBC_EN_0 + REG_BYPASS_COUNTER disabled + 0 + + + RBC_EN_1 + REG_BYPASS_COUNTER enabled + 0x1 + + + + + EN_DSM + DSM enable + 31 + 1 + read-write + + + EN_DSM_0 + DSM disabled + 0 + + + EN_DSM_1 + DSM enabled + 0x1 + + + + + + + MST_CPU_MAPPING + MASTER LPM Handshake + 0x18 + 32 + read-write + 0xFF + 0xFFFFFFFF + + + MST0_CPU_MAPPING + MASTER0 CPU Mapping + 0 + 1 + read-write + + + MST0_CPU_MAPPING_0 + GPC will not send out power off requirement + 0 + + + MST0_CPU_MAPPING_1 + GPC will send out power off requirement + 0x1 + + + + + MEMLP_RET_PGEN + Delay counter for "retnx" and "pgen" + 1 + 31 + read-write + + + + + MLPCR + Memory low power control register + 0x20 + 32 + read-write + 0x1010100 + 0xFFFFFFFF + + + MEMLP_CTL_DIS + RAM low-power control + 0 + 1 + read-write + + + MEMLP_CTL_DIS_0 + Enable RAM low power control + 0 + + + MEMLP_CTL_DIS_1 + Disable RAM low power control + 0x1 + + + + + MEMLP_RET_SEL + Retention select + 1 + 1 + read-write + + + MEMLP_RET_SEL_0 + retention mode 2 + 0 + + + MEMLP_RET_SEL_1 + retention mode 1 + 0x1 + + + + + ROMLP_PDN_DIS + ROM shut down control + 2 + 1 + read-write + + + ROMLP_PDN_DIS_0 + Enable ROM shut down control(should also enable RAM low power control); + 0 + + + ROMLP_PDN_DIS_1 + Disable ROM shut down control + 0x1 + + + + + MEMLP_ENT_CNT + Delay counter to make sure all clock off after pll_dis_req is issued by smc + 8 + 8 + read-write + + + MEM_EXT_CNT + Delay counter to start existing from memory low power + 16 + 8 + read-write + + + MEMLP_RET_PGEN + Delay conter for "retnx" and "pgen" + 24 + 8 + read-write + + + + + PGC_ACK_SEL_A53 + PGC acknowledge signal selection of A53 platform + 0x24 + 32 + read-write + 0x80008000 + 0xFFFFFFFF + + + A53_C0_PGC_PDN_ACK + Select power down acknowledge signal of A53 CORE0 PGC as the power down acknowledge for A53 LPM. + 0 + 1 + read-write + + + A53_C1_PGC_PDN_ACK + Select power down acknowledge signal of A53 CORE1 PGC as the power down acknowledge for A53 LPM. + 1 + 1 + read-write + + + A53_PLAT_PGC_PDN_ACK + Select power down acknowledge signal of A53 PLATFORM PGC as the power down acknowledge for A53 LPM. + 2 + 1 + read-write + + + A53_C2_PGC_PDN_ACK + Select power down acknowledge signal of A53 CORE2 PGC as the power down acknowledge for A53 LPM. + 13 + 1 + read-write + + + A53_C3_PGC_PDN_ACK + Select power down acknowledge signal of A53 CORE3 PGC as the power down acknowledge for A53 LPM. + 14 + 1 + read-write + + + A53_PGC_PDN_ACK + Select power down acknowledge signal of A53 (dummy) PGC as the power down acknowledge for A53 LPM. + 15 + 1 + read-write + + + A53_C0_PGC_PUP_ACK + Select power up acknowledge signal of A53 CORE0 PGC as the power up acknowledge for A53 LPM. + 16 + 1 + read-write + + + A53_C1_PGC_PUP_ACK + Select power up acknowledge signal of A53 CORE1 PGC as the power up acknowledge for A53 LPM. + 17 + 1 + read-write + + + A53_PLAT_PGC_PUP_ACK + Select power up acknowledge signal of A53 PLATFORM PGC as the power up acknowledge for A53 LPM. + 18 + 1 + read-write + + + A53_C2_PGC_PUP_ACK + Select power up acknowledge signal of A53 CORE2 PGC as the power up acknowledge for A53 LPM. + 29 + 1 + read-write + + + A53_C3_PGC_PUP_ACK + Select power up acknowledge signal of A53 CORE3 PGC as the power up acknowledge for A53 LPM. + 30 + 1 + read-write + + + A53_PGC_PUP_ACK + Select power up acknowledge signal of A53 (dummy) PGC as the power up acknowledge for A53 LPM. + 31 + 1 + read-write + + + + + PGC_ACK_SEL_M4 + PGC acknowledge signal selection of M4 platform + 0x28 + 32 + read-write + 0x80008000 + 0xFFFFFFFF + + + M4_VIRTUAL_PGC_PDN_ACK + Select power down acknowledge signal of M4 virtual PGC as the power down acknowledge for M4 LPM + 0 + 1 + read-write + + + M4_DUMMY_PGC_PDN_ACK + Select power down acknowledge signal of M4 (dummy) PGC as the power down acknowledge for M4 LPM. + 15 + 1 + read-write + + + M4_VIRTUAL_PGC_PUP_ACK + Select power up acknowledge signal of M4 virtual PGC as the power up acknowledge for M4 LPM + 16 + 1 + read-write + + + M4_DUMMY_PGC_PUP_ACK + Select power up acknowledge signal of M4 (dummy) PGC as the power up acknowledge for M4 LPM. + 31 + 1 + read-write + + + + + MISC + GPC Miscellaneous register + 0x2C + 32 + read-write + 0x21 + 0xFFFFFFFF + + + M4_SLEEP_HOLD_REQ_B + M4 sleep hold + 0 + 1 + read-write + + + M4_SLEEP_HOLD_REQ_B_0 + Hold M4 platform in sleep mode. This bit is a software control bit to M4 platform. + 0 + + + M4_SLEEP_HOLD_REQ_B_1 + Don't hold M4 platform in sleep mode. + 0x1 + + + + + A53_SLEEP_HOLD_REQ_B + A53 sleep hold + 1 + 1 + read-write + + + A53_SLEEP_HOLD_REQ_B_0 + Hold A53 platform in sleep mode. This bit is a software control bit to A53 platform. + 0 + + + A53_SLEEP_HOLD_REQ_B_1 + Don't hold A53 platform in sleep mode. + 0x1 + + + + + GPC_IRQ_MASK + GPC interrupt/event masking + 5 + 1 + read-write + + + GPC_IRQ_MASK_0 + Not masked + 0 + + + GPC_IRQ_MASK_1 + Interrupt / event is masked + 0x1 + + + + + M4_PDN_REQ_MASK + M4 power-down mask + 8 + 1 + read-write + + + M4_PDN_REQ_MASK_0 + M4 power down request to virtual M4 PGC will be masked. + 0 + + + M4_PDN_REQ_MASK_1 + M4 power down request to virtual M4 PGC will not be masked. Set this bit to 1'b1 when M4 virtual PGC is used. + 0x1 + + + + + A53_BYPASS_PUP_MASK + no description available + 24 + 1 + read-write + + + M4_BYPASS_PUP_MASK + no description available + 25 + 1 + read-write + + + + + IMR1_CORE0_A53 + IRQ masking register 1 of A53 core0 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR1_CORE0_A53 + A53 core0 IRQ[31:0] masking bits: + 0 + 32 + read-write + + + IMR1_CORE0_A53_0 + IRQ not masked + 0 + + + IMR1_CORE0_A53_1 + IRQ masked + 0x1 + + + + + + + IMR2_CORE0_A53 + IRQ masking register 2 of A53 core0 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR2_CORE0_A53 + A53 core0 IRQ[63:32] masking bits: + 0 + 32 + read-write + + + IMR2_CORE0_A53_0 + IRQ not masked + 0 + + + IMR2_CORE0_A53_1 + IRQ masked + 0x1 + + + + + + + IMR3_CORE0_A53 + IRQ masking register 3 of A53 core0 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR3_CORE0_A53 + A53 core0 IRQ[95:64] masking bits: + 0 + 32 + read-write + + + IMR3_CORE0_A53_0 + IRQ not masked + 0 + + + IMR3_CORE0_A53_1 + IRQ masked + 0x1 + + + + + + + IMR4_CORE0_A53 + IRQ masking register 4 of A53 core0 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR4_CORE0_A53 + A53 core0 IRQ[127:96] masking bits: + 0 + 32 + read-write + + + IMR4_CORE0_A53_0 + IRQ not masked + 0 + + + IMR4_CORE0_A53_1 + IRQ masked + 0x1 + + + + + + + IMR1_CORE1_A53 + IRQ masking register 1 of A53 core1 + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR1_CORE1_A53 + A53 core1 IRQ[31:0] masking bits: + 0 + 32 + read-write + + + IMR1_CORE1_A53_0 + IRQ not masked + 0 + + + IMR1_CORE1_A53_1 + IRQ masked + 0x1 + + + + + + + IMR2_CORE1_A53 + IRQ masking register 2 of A53 core1 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR2_CORE1_A53 + A53 core1 IRQ[63:32] masking bits: + 0 + 32 + read-write + + + IMR2_CORE1_A53_0 + IRQ not masked + 0 + + + IMR2_CORE1_A53_1 + IRQ masked + 0x1 + + + + + + + IMR3_CORE1_A53 + IRQ masking register 3 of A53 core1 + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR3_CORE1_A53 + A53 core1 IRQ[95:64] masking bits: + 0 + 32 + read-write + + + IMR3_CORE1_A53_0 + IRQ not masked + 0 + + + IMR3_CORE1_A53_1 + IRQ masked + 0x1 + + + + + + + IMR4_CORE1_A53 + IRQ masking register 4 of A53 core1 + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR4_CORE1_A53 + A53 core1 IRQ[127:96] masking bits: + 0 + 32 + read-write + + + IMR4_CORE1_A53_0 + IRQ not masked + 0 + + + IMR4_CORE1_A53_1 + IRQ masked + 0x1 + + + + + + + IMR1_M4 + IRQ masking register 1 of M4 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR1_M4 + M4 IRQ[31:0] masking bits: + 0 + 32 + read-write + + + IMR1_M4_0 + IRQ not masked + 0 + + + IMR1_M4_1 + IRQ masked + 0x1 + + + + + + + IMR2_M4 + IRQ masking register 2 of M4 + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR2_M4 + M4 IRQ[63:32] masking bits: + 0 + 32 + read-write + + + IMR2_M4_0 + IRQ not masked + 0 + + + IMR2_M4_1 + IRQ masked + 0x1 + + + + + + + IMR3_M4 + IRQ masking register 3 of M4 + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR3_M4 + M4 IRQ[95:64] masking bits: + 0 + 32 + read-write + + + IMR3_M4_0 + IRQ not masked + 0 + + + IMR3_M4_1 + IRQ masked + 0x1 + + + + + + + IMR4_M4 + IRQ masking register 4 of M4 + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR4_M4 + M4 IRQ[127:96] masking bits: + 0 + 32 + read-write + + + IMR4_M4_0 + IRQ not masked + 0 + + + IMR4_M4_1 + IRQ masked + 0x1 + + + + + + + ISR1_A53 + IRQ status register 1 of A53 + 0x70 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR1_A53 + A53 IRQ[31:0] status + 0 + 32 + read-only + + + + + ISR2_A53 + IRQ status register 2 of A53 + 0x74 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR2_A53 + A53 IRQ[63:32] status + 0 + 32 + read-only + + + + + ISR3_A53 + IRQ status register 3 of A53 + 0x78 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR3_A53 + A53 IRQ[95:64] status + 0 + 32 + read-only + + + + + ISR4_A53 + IRQ status register 4 of A53 + 0x7C + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR4_A53 + A53 IRQ[127:96] status + 0 + 32 + read-only + + + + + ISR1_M4 + IRQ status register 1 of M4 + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR1_M4 + M4 IRQ[31:0] status + 0 + 32 + read-only + + + + + ISR2_M4 + IRQ status register 2 of M4 + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR2_M4 + M4 IRQ[63:32] status + 0 + 32 + read-only + + + + + ISR3_M4 + IRQ status register 3 of M4 + 0x88 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR3_M4 + M4 IRQ[95:64] status + 0 + 32 + read-only + + + + + ISR4_M4 + IRQ status register 4 of M4 + 0x8C + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR4_M4 + M4 IRQ[127:96] status + 0 + 32 + read-only + + + + + SLT0_CFG + Slot configure register for A53 core + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT1_CFG + Slot configure register for A53 core + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT2_CFG + Slot configure register for A53 core + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT3_CFG + Slot configure register for A53 core + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT4_CFG + Slot configure register for A53 core + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT5_CFG + Slot configure register for A53 core + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT6_CFG + Slot configure register for A53 core + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT7_CFG + Slot configure register for A53 core + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT8_CFG + Slot configure register for A53 core + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT9_CFG + Slot configure register for A53 core + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT10_CFG + Slot configure register for A53 core + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT11_CFG + Slot configure register for A53 core + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT12_CFG + Slot configure register for A53 core + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT13_CFG + Slot configure register for A53 core + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT14_CFG + Slot configure register for A53 core + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + PGC_CPU_0_1_MAPPING + PGC CPU mapping + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + MF_A53_DOMAIN + MF_A53_DOMAIN + 0 + 1 + read-write + + + MIPI_A53_DOMAIN + MIPI A53 DOMAIN + 2 + 1 + read-write + + + PCIE_A53_DOMAIN + PCIE_A53_DOMAIN + 3 + 1 + read-write + + + OTG1_A53_DOMAIN + OTG1_A53_DOMAIN + 4 + 1 + read-write + + + OTG2_A53_DOMAIN + OTG2_A53_DOMAIN + 5 + 1 + read-write + + + DDR1_A53_DOMAIN + DDR1_A53_DOMAIN + 7 + 1 + read-write + + + DDR2_A53_DOMAIN + DDR2_A53_DOMAIN + 8 + 1 + read-write + + + GPU_A53_DOMAIN + GPU_A53_DOMAIN + 9 + 1 + read-write + + + VPU_A53_DOMAIN + VPU_A53_DOMAIN + 10 + 1 + read-write + + + HDMI_A53_DOMAIN + HDMI_A53_DOMAIN + 11 + 1 + read-write + + + DISP_A53_DOMAIN + DISP_A53_DOMAIN + 12 + 1 + read-write + + + MIPI_CSI1_A53_DOMAIN + MIPI_CSI1_A53_DOMAIN + 13 + 1 + read-write + + + MIPI_CSI2_A53_DOMAIN + MIPI_CSI2_A53_DOMAIN + 14 + 1 + read-write + + + PCIE2_A53_DOMAIN + PCIE2_A53_DOMAIN + 15 + 1 + read-write + + + MF_M4_DOMAIN + MF_M4_DOMAIN + 16 + 1 + read-write + + + MIPI_M4_DOMAIN + MIPI_M4_DOMAIN + 18 + 1 + read-write + + + PCIE_M4_DOMAIN + PCIE_M4_DOMAIN + 19 + 1 + read-write + + + OTG1_M4_DOMAIN + OTG1_M4_DOMAIN + 20 + 1 + read-write + + + OTG2_M4_DOMAIN + OTG2_M4_DOMAIN + 21 + 1 + read-write + + + DDR1_M4_DOMAIN + DDR1_M4_DOMAIN + 23 + 1 + read-write + + + DDR2_M4_DOMAIN + DDR2_M4_DOMAIN + 24 + 1 + read-write + + + GPU_M4_DOMAIN + GPU_M4_DOMAIN + 25 + 1 + read-write + + + VPU_M4_DOMAIN + VPU_M4_DOMAIN + 26 + 1 + read-write + + + HDMI_M4_DOMAIN + HDMI_M4_DOMAIN + 27 + 1 + read-write + + + DISP_M4_DOMAIN + DISP_M4_DOMAIN + 28 + 1 + read-write + + + MIPI_CSI1_M4_DOMAIN + MIPI_CSI1_M4_DOMAIN + 29 + 1 + read-write + + + MIPI_CSI2_M4_DOMAIN + MIPI_CSI2_M4_DOMAIN + 30 + 1 + read-write + + + PCIE2_M4_DOMAIN + PCIE2_M4_DOMAIN + 31 + 1 + read-write + + + + + CPU_PGC_SW_PUP_REQ + CPU PGC software power up trigger + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_SW_PUP_REQ + Software power up trigger for Core0 A53 PGC + 0 + 1 + read-write + + + CORE1_A53_SW_PUP_REQ + Software power up trigger for Core1 A53 PGC + 1 + 1 + read-write + + + SCU_A53_SW_PUP_REQ + Software power up trigger for SCU A53 + 2 + 1 + read-write + + + CORE2_A53_SW_PUP_REQ + Software power up trigger for Core2 A53 PGC + 3 + 1 + read-write + + + CORE3_A53_SW_PUP_REQ + Software power up trigger for Core3 A53 PGC + 4 + 1 + read-write + + + + + MIX_PGC_SW_PUP_REQ + MIX PGC software power up trigger + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MIX_SW_PUP_REQ + Software power up trigger for MIX PGC + 0 + 1 + read-write + + + + + PU_PGC_SW_PUP_REQ + PU PGC software up trigger + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MIPI_SW_PUP_REQ + Software power up trigger for MIPI + 0 + 1 + read-write + + + PCIE_SW_PUP_REQ + Software power up trigger for PCIE + 1 + 1 + read-write + + + USB_OTG1_SW_PUP_REQ + Software power up trigger for USB_OTG1 + 2 + 1 + read-write + + + USB_OTG2_SW_PUP_REQ + Software power up trigger for USB_OTG2 + 3 + 1 + read-write + + + DDR1_SW_PUP_REQ + Software power up trigger for DDR1 + 5 + 1 + read-write + + + DDR2_SW_PUP_REQ + Software power up trigger for DDR2 + 6 + 1 + read-write + + + GPU_SW_PUP_REQ + Software power up trigger for GPU + 7 + 1 + read-write + + + VPU_SW_PUP_REQ + Software power up trigger for VPU + 8 + 1 + read-write + + + HDMI_SW_PUP_REQ + Software power up trigger for HDMI + 9 + 1 + read-write + + + DISP_SW_PUP_REQ + Software power up trigger for DISP + 10 + 1 + read-write + + + MIPI_CSI1_SW_PUP_REQ + Software power up trigger for MIPI CSI1 + 11 + 1 + read-write + + + MIPI_CSI2_SW_PUP_REQ + Software power up trigger for MIPI CSI2 + 12 + 1 + read-write + + + PCIE2_SW_PUP_REQ + Software power up trigger for PCIE2 + 13 + 1 + read-write + + + + + CPU_PGC_SW_PDN_REQ + CPU PGC software down trigger + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_SW_PDN_REQ + Software power down trigger for Core0 A53 PGC + 0 + 1 + read-write + + + CORE1_A53_SW_PDN_REQ + Software power down trigger for Core1 A53 PGC + 1 + 1 + read-write + + + SCU_A53_SW_PDN_REQ + Software power down trigger for SCU A53 + 2 + 1 + read-write + + + CORE2_A53_SW_PUP_REQ + Software power up trigger for Core2 A53 PGC + 3 + 1 + read-write + + + CORE3_A53_SW_PUP_REQ + Software power up trigger for Core3 A53 PGC + 4 + 1 + read-write + + + + + MIX_PGC_SW_PDN_REQ + MIX PGC software power down trigger + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + MIX_SW_PDN_REQ + Software power down trigger for MIX PGC + 0 + 1 + read-write + + + + + PU_PGC_SW_PDN_REQ + PU PGC software down trigger + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + MIPI_SW_PDN_REQ + Software power down trigger for MIPI + 0 + 1 + read-write + + + PCIE_SW_PDN_REQ + Software power down trigger for PCIE + 1 + 1 + read-write + + + USB_OTG1_SW_PDN_REQ + Software power down trigger for USB_OTG1 + 2 + 1 + read-write + + + USB_OTG2_SW_PDN_REQ + Software power down trigger for USB_OTG2 + 3 + 1 + read-write + + + DDR1_SW_PDN_REQ + Software power down trigger for DDR1 + 5 + 1 + read-write + + + DDR2_SW_PDN_REQ + Software power down trigger for DDR2 + 6 + 1 + read-write + + + GPU_SW_PDN_REQ + Software power down trigger for GPU + 7 + 1 + read-write + + + VPU_SW_PDN_REQ + Software power down trigger for VPU + 8 + 1 + read-write + + + HDMI_SW_PDN_REQ + Software power down trigger for HDMI + 9 + 1 + read-write + + + DISP_SW_PDN_REQ + Software power down trigger for DISP + 10 + 1 + read-write + + + MIPI_CSI1_SW_PDN_REQ + Software power down trigger for MIPI CSI1 + 11 + 1 + read-write + + + MIPI_CSI2_SW_PDN_REQ + Software power down trigger for MIPI CSI2 + 12 + 1 + read-write + + + PCIE2_SW_PDN_REQ + Software power down trigger for PCIE2 + 13 + 1 + read-write + + + + + LPCR_A53_BSC2 + Basic Low power control register of A53 platform + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPM2 + CORE2 Setting the low power mode that system will enter on next assertion of dsm_request signal. + 0 + 2 + read-write + + + LPM2_0 + Remain in RUN mode + 0 + + + LPM2_1 + Transfer to WAIT mode + 0x1 + + + LPM2_2 + Transfer to STOP mode + 0x2 + + + + + LPM3 + CORE3 Setting the low power mode that system will enter on next assertion of dsm_request signal. + 2 + 2 + read-write + + + LPM3_0 + Remain in RUN mode + 0 + + + LPM3_1 + Transfer to WAIT mode + 0x1 + + + LPM3_2 + Transfer to STOP mode + 0x2 + + + + + + + CPU_PGC_PUP_STATUS1 + CPU PGC software up trigger status1 + 0x130 + 32 + read-only + 0 + 0xFFFFFFFF + + + CORE0_A53_PUP_STATUS + no description available + 0 + 1 + read-only + + + CORE1_A53_PUP_STATUS + no description available + 1 + 1 + read-only + + + SCU_A53_PUP_STATUS + no description available + 2 + 1 + read-only + + + CORE2_A53_PUP_STATUS + no description available + 3 + 1 + read-only + + + CORE3_A53_PUP_REQ + no description available + 4 + 1 + read-only + + + + + 3 + 0x4 + 0,1,2 + A53_MIX_PGC_PUP_STATUS%s + A53 MIX software up trigger status register + 0x134 + 32 + read-only + 0 + 0xFFFFFFFF + + + A53_MIX_PGC_PUP_STATUS + no description available + 0 + 1 + read-only + + + + + 3 + 0x4 + 0,1,2 + M4_MIX_PGC_PUP_STATUS%s + M4 MIX PGC software up trigger status register + 0x140 + 32 + read-only + 0 + 0xFFFFFFFF + + + M4_MIX_PGC_PUP_STATUS + no description available + 0 + 1 + read-only + + + + + 3 + 0x4 + 0,1,2 + A53_PU_PGC_PUP_STATUS%s + A53 PU software up trigger status register + 0x14C + 32 + read-only + 0 + 0xFFFFFFFF + + + A53_MIPI_PUP_STATUS + no description available + 0 + 1 + read-only + + + A53_PCIE_PUP_STATUS + no description available + 1 + 1 + read-only + + + A53_OTG1_PUP_STATUS + no description available + 2 + 1 + read-only + + + A53_OTG2_PUP_STATUS + no description available + 3 + 1 + read-only + + + A53_DDR1_PUP_STATUS + no description available + 5 + 1 + read-only + + + A53_GPU_PUP_STATUS + no description available + 7 + 1 + read-only + + + A53_VPU_PUP_STATUS + no description available + 8 + 1 + read-only + + + A53_HDMI_PUP_STATUS + no description available + 9 + 1 + read-only + + + A53_DISP_PUP_STATUS + no description available + 10 + 1 + read-only + + + A53_MIPI_CSI1_PUP_STATUS + no description available + 11 + 1 + read-only + + + A53_MIPI_CSI2_PUP_STATUS + no description available + 12 + 1 + read-only + + + A53_PCIE2_PUP_STATUS + no description available + 13 + 1 + read-only + + + + + 3 + 0x4 + 0,1,2 + M4_PU_PGC_PUP_STATUS%s + M4 PU PGC software up trigger status register + 0x158 + 32 + read-only + 0 + 0xFFFFFFFF + + + M4_MIPI_PUP_STATUS + no description available + 0 + 1 + read-only + + + M4_PCIE_PUP_STATUS + no description available + 1 + 1 + read-only + + + M4_OTG1_PUP_STATUS + no description available + 2 + 1 + read-only + + + M4_OTG2_PUP_STATUS + no description available + 3 + 1 + read-only + + + M4_DDR1_PUP_STATUS + no description available + 5 + 1 + read-only + + + M4_GPU_PUP_STATUS + no description available + 7 + 1 + read-only + + + M4_VPU_PUP_STATUS + no description available + 8 + 1 + read-only + + + M4_HDMI_PUP_STATUS + no description available + 9 + 1 + read-only + + + M4_DISP_PUP_STATUS + no description available + 10 + 1 + read-only + + + M4_MIPI_CSI1_PUP_STATUS + no description available + 11 + 1 + read-only + + + M4_MIPI_CSI2_PUP_STATUS + no description available + 12 + 1 + read-only + + + M4_PCIE2_PUP_STATUS + no description available + 13 + 1 + read-only + + + + + CPU_PGC_PDN_STATUS1 + CPU PGC software dn trigger status1 + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_STATUS + no description available + 0 + 1 + read-only + + + CORE1_A53_PDN_STATUS + no description available + 1 + 1 + read-only + + + SCU_A53_PDN_STATUS + no description available + 2 + 1 + read-only + + + CORE2_A53_PDN_STATUS + no description available + 3 + 1 + read-write + + + CORE3_A53_PDN_REQ + no description available + 4 + 1 + read-write + + + + + 3 + 0x4 + 0,1,2 + A53_MIX_PGC_PDN_STATUS%s + A53 MIX software down trigger status register + 0x174 + 32 + read-only + 0 + 0xFFFFFFFF + + + A53_MIX_PGC_PDN_STATUS + no description available + 0 + 1 + read-only + + + + + 3 + 0x4 + 0,1,2 + M4_MIX_PGC_PDN_STATUS%s + M4 MIX PGC software power down trigger status register + 0x180 + 32 + read-only + 0 + 0xFFFFFFFF + + + M4_MIX_PGC_PDN_STATUS + no description available + 0 + 1 + read-only + + + + + 3 + 0x4 + 0,1,2 + A53_PU_PGC_PDN_STATUS%s + A53 PU PGC software down trigger status + 0x18C + 32 + read-only + 0 + 0xFFFFFFFF + + + A53_MIPI_PDN_STATUS + no description available + 0 + 1 + read-only + + + A53_PCIE_PDN_STATUS + no description available + 1 + 1 + read-only + + + A53_OTG1_PDN_STATUS + no description available + 2 + 1 + read-only + + + A53_OTG2_PDN_STATUS + no description available + 3 + 1 + read-only + + + A53_DDR1_PDN_STATUS + no description available + 5 + 1 + read-only + + + A53_GPU_PDN_STATUS + no description available + 7 + 1 + read-only + + + A53_VPU_PDN_STATUS + no description available + 8 + 1 + read-only + + + A53_HDMI_PDN_STATUS + no description available + 9 + 1 + read-only + + + A53_DISP_PDN_STATUS + no description available + 10 + 1 + read-only + + + A53_MIPI_CSI1_PDN_STATUS + no description available + 11 + 1 + read-only + + + A53_MIPI_CSI2_PDN_STATUS + no description available + 12 + 1 + read-only + + + A53_PCIE2_PDN_STATUS + no description available + 13 + 1 + read-only + + + + + 3 + 0x4 + 0,1,2 + M4_PU_PGC_PDN_STATUS%s + M4 PU PGC software down trigger status + 0x198 + 32 + read-only + 0 + 0xFFFFFFFF + + + M4_MIPI_PDN_STATUS + no description available + 0 + 1 + read-only + + + M4_PCIE_PDN_STATUS + no description available + 1 + 1 + read-only + + + M4_OTG1_PDN_STATUS + no description available + 2 + 1 + read-only + + + M4_OTG2_PDN_STATUS + no description available + 3 + 1 + read-only + + + M4_DDR1_PDN_STATUS + no description available + 5 + 1 + read-only + + + M4_GPU_PDN_STATUS + no description available + 7 + 1 + read-only + + + M4_VPU_PDN_STATUS + no description available + 8 + 1 + read-only + + + M4_HDMI_PDN_STATUS + no description available + 9 + 1 + read-only + + + M4_DISP_PDN_STATUS + no description available + 10 + 1 + read-only + + + M4_MIPI_CSI1_PDN_STATUS + no description available + 11 + 1 + read-only + + + M4_MIPI_CSI2_PDN_STATUS + no description available + 12 + 1 + read-only + + + M4_PCIE2_PDN_STATUS + no description available + 13 + 1 + read-only + + + + + A53_MIX_PDN_FLG + A53 MIX PDN FLG + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + A53_MIX_PDN_FLAG + A53 MIX power-down flag + 0 + 1 + read-write + + + + + A53_PU_PDN_FLG + A53 PU PDN FLG + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + A53_PU_PDN_FLG + A53 PGC power-down flag + 0 + 14 + read-write + + + + + M4_MIX_PDN_FLG + M4 MIX PDN FLG + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + M4_MIX_PDN_FLAG + M4_MIX power-down flag + 0 + 1 + read-write + + + + + M4_PU_PDN_FLG + M4 PU PDN FLG + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + M4_PU_PDN_FLG + M4 power-down flag + 0 + 14 + read-write + + + + + IMR1_CORE2_A53 + IRQ masking register 1 of A53 core2 + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR1_CORE2_A53 + A53 core2 IRQ[31:0] masking bits: + 0 + 32 + read-write + + + IMR1_CORE2_A53_0 + IRQ not masked + 0 + + + IMR1_CORE2_A53_1 + IRQ masked + 0x1 + + + + + + + IMR2_CORE2_A53 + IRQ masking register 2 of A53 core2 + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR2_CORE2_A53 + A53 core2 IRQ[63:32] masking bits: + 0 + 32 + read-write + + + IMR2_CORE2_A53_0 + IRQ not masked + 0 + + + IMR2_CORE2_A53_1 + IRQ masked + 0x1 + + + + + + + IMR3_CORE2_A53 + IRQ masking register 3 of A53 core2 + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR3_CORE2_A53 + A53 core2 IRQ[95:64] masking bits: + 0 + 32 + read-write + + + IMR3_CORE2_A53_0 + IRQ not masked + 0 + + + IMR3_CORE2_A53_1 + IRQ masked + 0x1 + + + + + + + IMR4_CORE2_A53 + IRQ masking register 4 of A53 core2 + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR4_CORE2_A53 + A53 core2 IRQ[127:96] masking bits: + 0 + 32 + read-write + + + IMR4_CORE2_A53_0 + IRQ not masked + 0 + + + IMR4_CORE2_A53_1 + IRQ masked + 0x1 + + + + + + + IMR1_CORE3_A53 + IRQ masking register 1 of A53 core3 + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR1_CORE3_A53 + A53 core3 IRQ[31:0] masking bits: + 0 + 32 + read-write + + + IMR1_CORE3_A53_0 + IRQ not masked + 0 + + + IMR1_CORE3_A53_1 + IRQ masked + 0x1 + + + + + + + IMR2_CORE3_A53 + IRQ masking register 2 of A53 core3 + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR2_CORE3_A53 + A53 core3 IRQ[63:32] masking bits: + 0 + 32 + read-write + + + IMR2_CORE3_A53_0 + IRQ not masked + 0 + + + IMR2_CORE3_A53_1 + IRQ masked + 0x1 + + + + + + + IMR3_CORE3_A53 + IRQ masking register 3 of A53 core3 + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR3_CORE3_A53 + A53 core3 IRQ[95:64] masking bits: + 0 + 32 + read-write + + + IMR3_CORE3_A53_0 + IRQ not masked + 0 + + + IMR3_CORE3_A53_1 + IRQ masked + 0x1 + + + + + + + IMR4_CORE3_A53 + IRQ masking register 4 of A53 core3 + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR4_CORE3_A53 + A53 core3 IRQ[127:96] masking bits: + 0 + 32 + read-write + + + IMR4_CORE3_A53_0 + IRQ not masked + 0 + + + IMR4_CORE3_A53_1 + IRQ masked + 0x1 + + + + + + + ACK_SEL_A53_PU + PGC acknowledge signal selection of A53 platform for PUs + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MF_PGC_PDN_ACK + Select power down acknowledge signal of MIX PGC as the power down acknowledge for A53 LPM. + 0 + 1 + read-write + + + MIPI_PGC_PDN_ACK + Select power down acknowledge signal of MIPI PGC as the power down acknowledge for A53 LPM. + 2 + 1 + read-write + + + PCIE_PGC_PDN_ACK + Select power down acknowledge signal of PCIE PGC as the power down acknowledge for A53 LPM. + 3 + 1 + read-write + + + USB_OTG1_PGC_PDN_ACK + Select power down acknowledge signal of USB_OTG1 PGC as the power down acknowledge for A53 LPM. + 4 + 1 + read-write + + + USB_OTG2_PGC_PDN_ACK + Select power down acknowledge signal of USB_OTG2 PGC as the power down acknowledge for A53 LPM. + 5 + 1 + read-write + + + DDR1_PGC_PDN_ACK + Select power down acknowledge signal of DDR1 PGC as the power down acknowledge for A53 LPM. + 7 + 1 + read-write + + + DDR2_PGC_PDN_ACK + Select power down acknowledge signal of DDR2 PGC as the power down acknowledge for A53 LPM. + 8 + 1 + read-write + + + GPU_PGC_PDN_ACK + Select power down acknowledge signal of GPU PGC as the power down acknowledge for A53 LPM. + 9 + 1 + read-write + + + VPU_PGC_PDN_ACK + Select power down acknowledge signal of VPU PGC as the power down acknowledge for A53 LPM. + 10 + 1 + read-write + + + HDMI_PGC_PDN_ACK + Select power down acknowledge signal of HDMI PGC as the power down acknowledge for A53 LPM. + 11 + 1 + read-write + + + DISP_PGC_PDN_ACK + Select power down acknowledge signal of DISP PGC as the power down acknowledge for A53 LPM. + 12 + 1 + read-write + + + MIPI_CSI1_PGC_PDN_ACK + Select power down acknowledge signal of MPI_CSI1 PGC as the power down acknowledge for A53 LPM. + 13 + 1 + read-write + + + MIPI_CSI2_PGC_PDN_ACK + Select power down acknowledge signal of MIPI_CSI2 PGC as the power down acknowledge for A53 LPM. + 14 + 1 + read-write + + + PCIE2_PGC_PDN_ACK + Select power down acknowledge signal of PCIE2 PGC as the power down acknowledge for A53 LPM. + 15 + 1 + read-write + + + MF_PGC_PUP_ACK + Select power down acknowledge signal of MIX PGC as the power up acknowledge for A53 LPM. + 16 + 1 + read-write + + + MIPI_PGC_PUP_ACK + Select power down acknowledge signal of MIPI PGC as the power up acknowledge for A53 LPM. + 18 + 1 + read-write + + + PCIE_PGC_PUP_ACK + Select power down acknowledge signal of PCIE PGC as the power up acknowledge for A53 LPM. + 19 + 1 + read-write + + + USB_OTG1_PGC_PUP_ACK + Select power down acknowledge signal of USB_OTG1 PGC as the power up acknowledge for A53 LPM. + 20 + 1 + read-write + + + USB_OTG2_PGC_PUP_ACK + Select power down acknowledge signal of USB_OTG2 PGC as the power up acknowledge for A53 LPM. + 21 + 1 + read-write + + + DDR1_PGC_PUP_ACK + Select power down acknowledge signal of DDR1 PGC as the power up acknowledge for A53 LPM. + 23 + 1 + read-write + + + DDR2_PGC_PUP_ACK + Select power down acknowledge signal of DDR2 PGC as the power up acknowledge for A53 LPM. + 24 + 1 + read-write + + + GPU_PGC_PUP_ACK + Select power down acknowledge signal of GPU PGC as the power up acknowledge for A53 LPM. + 25 + 1 + read-write + + + VPU_PGC_PUP_ACK + Select power down acknowledge signal of VPU PGC as the power up acknowledge for A53 LPM. + 26 + 1 + read-write + + + HDMI_PGC_PUP_ACK + Select power down acknowledge signal of HDMI PGC as the power up acknowledge for A53 LPM. + 27 + 1 + read-write + + + DISP_PGC_PUP_ACK + Select power down acknowledge signal of DISP PGC as the power up acknowledge for A53 LPM. + 28 + 1 + read-write + + + MIPI_CSI1_PGC_PUP_ACK + Select power down acknowledge signal of MIPI_CSI1 PGC as the power up acknowledge for A53 LPM. + 29 + 1 + read-write + + + MIPI_CSI2_PGC_PUP_ACK + Select power down acknowledge signal of MIPI_CSI2 PGC as the power up acknowledge for A53 LPM. + 30 + 1 + read-write + + + PCIE2_PGC_PUP_ACK + Select power down acknowledge signal of PCIE2 PGC as the power up acknowledge for A53 LPM. + 31 + 1 + read-write + + + + + ACK_SEL_M4_PU + PGC acknowledge signal selection of M4 platform for PUs + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MF_PGC_PDN_ACK + Select power down acknowledge signal of MIX PGC as the power down acknowledge for M4 LPM. + 0 + 1 + read-write + + + MIPI_PGC_PDN_ACK + Select power down acknowledge signal of MIPI PGC as the power down acknowledge for M4 LPM. + 2 + 1 + read-write + + + PCIE_PGC_PDN_ACK + Select power down acknowledge signal of PCIE PGC as the power down acknowledge for M4 LPM. + 3 + 1 + read-write + + + USB_OTG1_PGC_PDN_ACK + Select power down acknowledge signal of USB_OTG1 PGC as the power down acknowledge for M4 LPM. + 4 + 1 + read-write + + + USB_OTG2_PGC_PDN_ACK + Select power down acknowledge signal of USB_OTG2 PGC as the power down acknowledge for M4 LPM. + 5 + 1 + read-write + + + DDR1_PGC_PDN_ACK + Select power down acknowledge signal of DDR1 PGC as the power down acknowledge for M4 LPM. + 7 + 1 + read-write + + + DDR2_PGC_PDN_ACK + Select power down acknowledge signal of DDR2 PGC as the power down acknowledge for M4 LPM. + 8 + 1 + read-write + + + GPU_PGC_PDN_ACK + Select power down acknowledge signal of GPU PGC as the power down acknowledge for M4 LPM. + 9 + 1 + read-write + + + VPU_PGC_PDN_ACK + Select power down acknowledge signal of VPU PGC as the power down acknowledge for M4 LPM. + 10 + 1 + read-write + + + HDMI_PGC_PDN_ACK + Select power down acknowledge signal of HDMI PGC as the power down acknowledge for M4 LPM. + 11 + 1 + read-write + + + DISP_PGC_PDN_ACK + Select power down acknowledge signal of DISP PGC as the power down acknowledge for M4 LPM. + 12 + 1 + read-write + + + MIPI_CSI1_PGC_PDN_ACK + Select power down acknowledge signal of MPI_CSI1 PGC as the power down acknowledge for M4 LPM. + 13 + 1 + read-write + + + MIPI_CSI2_PGC_PDN_ACK + Select power down acknowledge signal of MIPI_CSI2 PGC as the power down acknowledge for M4 LPM. + 14 + 1 + read-write + + + PCIE2_PGC_PDN_ACK + Select power down acknowledge signal of PCIE2 PGC as the power down acknowledge for M4 LPM. + 15 + 1 + read-write + + + MF_PGC_PUP_ACK + Select power down acknowledge signal of MIX PGC as the power up acknowledge for M4 LPM. + 16 + 1 + read-write + + + MIPI_PGC_PUP_ACK + Select power down acknowledge signal of MIPI PGC as the power up acknowledge for M4 LPM. + 18 + 1 + read-write + + + PCIE_PGC_PUP_ACK + Select power down acknowledge signal of PCIE PGC as the power up acknowledge for M4 LPM. + 19 + 1 + read-write + + + USB_OTG1_PGC_PUP_ACK + Select power down acknowledge signal of USB_OTG1 PGC as the power up acknowledge for M4 LPM. + 20 + 1 + read-write + + + USB_OTG2_PGC_PUP_ACK + Select power down acknowledge signal of USB_OTG2 PGC as the power up acknowledge for M4 LPM. + 21 + 1 + read-write + + + DDR1_PGC_PUP_ACK + Select power down acknowledge signal of DDR1 PGC as the power up acknowledge for M4 LPM. + 23 + 1 + read-write + + + DDR2_PGC_PUP_ACK + Select power down acknowledge signal of DDR2 PGC as the power up acknowledge for M4 LPM. + 24 + 1 + read-write + + + GPU_PGC_PUP_ACK + Select power down acknowledge signal of GPU PGC as the power up acknowledge for M4 LPM. + 25 + 1 + read-write + + + VPU_PGC_PUP_ACK + Select power down acknowledge signal of VPU PGC as the power up acknowledge for M4 LPM. + 26 + 1 + read-write + + + HDMI_PGC_PUP_ACK + Select power down acknowledge signal of HDMI PGC as the power up acknowledge for M4 LPM. + 27 + 1 + read-write + + + DISP_PGC_PUP_ACK + Select power down acknowledge signal of DISP PGC as the power up acknowledge for M4 LPM. + 28 + 1 + read-write + + + MIPI_CSI1_PGC_PUP_ACK + Select power down acknowledge signal of MIPI_CSI1 PGC as the power up acknowledge for M4 LPM. + 29 + 1 + read-write + + + MIPI_CSI2_PGC_PUP_ACK + Select power down acknowledge signal of MIPI_CSI2 PGC as the power up acknowledge for M4 LPM. + 30 + 1 + read-write + + + PCIE2_PGC_PUP_ACK + Select power down acknowledge signal of PCIE2 PGC as the power up acknowledge for M4 LPM. + 31 + 1 + read-write + + + + + SLT15_CFG + Slot configure register for A53 core + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT16_CFG + Slot configure register for A53 core + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT17_CFG + Slot configure register for A53 core + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT18_CFG + Slot configure register for A53 core + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + SLT19_CFG + Slot configure register for A53 core + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORE0_A53_PDN_SLOT_CONTROL + CORE0 A53 Power-down slot control + 0 + 1 + read-write + + + CORE0_A53_PUP_SLOT_CONTROL + CORE0 A53 Power-up slot control + 1 + 1 + read-write + + + CORE1_A53_PDN_SLOT_CONTROL + CORE1 A53 Power-down slot control + 2 + 1 + read-write + + + CORE1_A53_PUP_SLOT_CONTROL + CORE1 A53 Power-up slot control + 3 + 1 + read-write + + + CORE2_A53_PDN_SLOT_CONTROL + CORE2 A53 Power-down slot control + 4 + 1 + read-write + + + CORE2_A53_PUP_SLOT_CONTROL + CORE2 A53 Power-up slot control + 5 + 1 + read-write + + + CORE3_A53_PDN_SLOT_CONTROL + CORE3 A53 Power-down slot control + 6 + 1 + read-write + + + CORE3_A53_PUP_SLOT_CONTROL + CORE3 A53 Power-up slot control + 7 + 1 + read-write + + + SCU_PDN_SLOT_CONTROL + SCU Power-down slot control + 8 + 1 + read-write + + + SCU_PUP_SLOT_CONTROL + SCU Power-up slot control + 9 + 1 + read-write + + + + + PU_PWRHSK + Power handshake register + 0x1FC + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + GPC_DDR1_CORE_CSYSREQ + DDR1 controller Hardware Low-Power Request + 0 + 1 + read-write + + + GPC_DDR1_AXI_CSYSREQ + DDR1 AXI Low-Power Request + 1 + 1 + read-write + + + GPC_DDR2_CORE_CSYSREQ + DDR2 controller Hardware Low-Power Request + 2 + 1 + read-write + + + GPC_DDR2_AXI_CSYSREQ + DDR2 AXI Low-Power Request + 3 + 1 + read-write + + + GPC_DISPMIX_PWRDNREQN + DISPMIX ADB400 power down request. Active 0 + 4 + 1 + read-write + + + GPC_VPUMIX_PWRDNREQN + VPU ADB400 power down request. Active 0 + 5 + 1 + read-write + + + GPC_GPUMIX_PWRDNREQN + GPU ADB400 power down request. Active 0 + 6 + 1 + read-write + + + GPC_DDR1_CORE_CSYSACK + DDR1 controller Hardware Low_Power ack + 16 + 1 + read-write + + + GPC_DDR1_CORE_CACTIVE + DDR1 controller Hardware Low-Power Clock active + 17 + 1 + read-write + + + GPC_DDR1_AXI_CSYSACK + DDR1 AXI Low-Power Request ack + 18 + 1 + read-write + + + GPC_DDR1_AXI_CACTIVE + DDR1 AXI Clock Active + 19 + 1 + read-write + + + GPC_DDR2_CORE_CSYSACK + DDR2 controller Hardware Low_Power ack + 20 + 1 + read-write + + + GPC_DDR2_CORE_CACTIVE + DDR2 controller Hardware Low-Power Clock active + 21 + 1 + read-write + + + GPC_DDR2_AXI_CSYSACK + DDR2 AXI Low-Power Request ack + 22 + 1 + read-write + + + GPC_DDR2_AXI_CACTIVE + DDR2 AXI Clock Active + 23 + 1 + read-write + + + GPC_DISPMIX_PWRDNACKN + DISPMIX ADB400 power down ack. Active 0 + 24 + 1 + read-write + + + GPC_VPUMIX_PWRDNACKN + VPU ADB400 power down ack. Active 0 + 25 + 1 + read-write + + + GPC_GPUMIX_PWRDNACKN + GPU ADB400 power down ack. Active 0 + 26 + 1 + read-write + + + + + 20 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19 + SLT%s_CFG_PU + Slot configure register for PUs + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + MF_PDN_SLOT_CONTROL + MF Power-down slot control + 0 + 1 + read-write + + + MF_PUP_SLOT_CONTROL + MF Power-up slot control + 1 + 1 + read-write + + + MIPI_PDN_SLOT_CONTROL + MIPI Power-down slot control + 2 + 1 + read-write + + + MIPI_PUP_SLOT_CONTROL + MIPI Power-up slot control + 3 + 1 + read-write + + + PCIE_PDN_SLOT_CONTROL + SCU Power-down slot control + 4 + 1 + read-write + + + PCIE_PUP_SLOT_CONTROL + PCIE Power-up slot control + 5 + 1 + read-write + + + OTG1_PDN_SLOT_CONTROL + OTG1 Power-down slot control + 6 + 1 + read-write + + + OTG1_PUP_SLOT_CONTROL + OTG1 Power-up slot control + 7 + 1 + read-write + + + OTG2_PDN_SLOT_CONTROL + OTG2 Power-down slot control + 8 + 1 + read-write + + + OTG2_PUP_SLOT_CONTROL + OTG2 Power-up slot control + 9 + 1 + read-write + + + M4_PDN_SLOT_CONTROL + M4 Power-down slot control + 12 + 1 + read-write + + + M4_PUP_SLOT_CONTROL + M4 Power-up slot control + 13 + 1 + read-write + + + DDR1_PDN_SLOT_CONTROL + DDR1 Power-down slot control + 14 + 1 + read-write + + + DDR1_PUP_SLOT_CONTROL + DDR1 Power-up slot control + 15 + 1 + read-write + + + DDR2_PDN_SLOT_CONTROL + DDR2 Power-down slot control + 16 + 1 + read-write + + + DDR2_PUP_SLOT_CONTROL + DDR2 Power-up slot control + 17 + 1 + read-write + + + GPU_PDN_SLOT_CONTROL + GPU Power-down slot control + 18 + 1 + read-write + + + GPU_PUP_SLOT_CONTROL + GPU Power-up slot control + 19 + 1 + read-write + + + VPU_PDN_SLOT_CONTROL + VPU Power-down slot control + 20 + 1 + read-write + + + VPU_PUP_SLOT_CONTROL + VPU Power-up slot control + 21 + 1 + read-write + + + HDMI_PDN_SLOT_CONTROL + HDMI Power-down slot control + 22 + 1 + read-write + + + HDMI_PUP_SLOT_CONTROL + HDMI Power-up slot control + 23 + 1 + read-write + + + DISP_PDN_SLOT_CONTROL + DISP Power-down slot control + 24 + 1 + read-write + + + DISP_PUP_SLOT_CONTROL + DISP Power-up slot control + 25 + 1 + read-write + + + MIPI_CSI1_PDN_SLOT_CONTROL + MIPI_CSI1 Power-down slot control + 26 + 1 + read-write + + + MIPI_CSI1_PUP_SLOT_CONTROL + MIPI_CSI1 Power-up slot control + 27 + 1 + read-write + + + MIPI_CSI2_PDN_SLOT_CONTROL + MIPI_CSI2 Power-down slot control + 28 + 1 + read-write + + + MIPI_CSI2_PUP_SLOT_CONTROL + MIPI_CSI2 Power-up slot control + 29 + 1 + read-write + + + PCIE2_PDN_SLOT_CONTROL + PCIE2 Power-down slot control + 30 + 1 + read-write + + + PCIE2_PUP_SLOT_CONTROL + PCIE2 Power-up slot control + 31 + 1 + read-write + + + + + + + GPC_PGC + GPC_PGC + GPC_PGC + GPC_PGC_ + 0x303A0800 + + 0 + 0x754 + registers + + + + A53CORE0_CTRL + GPC PGC Control Register + 0 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + A53CORE0_PUPSCR + GPC PGC Up Sequence Control Register + 0x4 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + A53CORE0_PDNSCR + GPC PGC Down Sequence Control Register + 0x8 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + A53CORE0_SR + GPC PGC Status Register + 0xC + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + A53CORE0_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x10 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + A53CORE1_CTRL + GPC PGC Control Register + 0x40 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + A53CORE1_PUPSCR + GPC PGC Up Sequence Control Register + 0x44 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + A53CORE1_PDNSCR + GPC PGC Down Sequence Control Register + 0x48 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + A53CORE1_SR + GPC PGC Status Register + 0x4C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + A53CORE1_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x50 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + A53CORE2_CTRL + GPC PGC Control Register + 0x80 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + A53CORE2_PUPSCR + GPC PGC Up Sequence Control Register + 0x84 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + A53CORE2_PDNSCR + GPC PGC Down Sequence Control Register + 0x88 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + A53CORE2_SR + GPC PGC Status Register + 0x8C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + A53CORE2_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x90 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + A53CORE3_CTRL + GPC PGC Control Register + 0xC0 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + A53CORE3_PUPSCR + GPC PGC Up Sequence Control Register + 0xC4 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + A53CORE3_PDNSCR + GPC PGC Down Sequence Control Register + 0xC8 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + A53CORE3_SR + GPC PGC Status Register + 0xCC + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + A53CORE3_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0xD0 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + A53SCU_CTRL + GPC PGC Control Register + 0x100 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + A53SCU_PUPSCR + GPC PGC Up Sequence Control Register + 0x104 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + A53SCU_PDNSCR + GPC PGC Down Sequence Control Register + 0x108 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + A53SCU_SR + GPC PGC Status Register + 0x10C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + A53SCU_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x110 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + MIX_CTRL + GPC PGC Control Register + 0x200 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + MIX_PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + MIX_PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + MIX_PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + MIX_PUPSCR + GPC PGC Up Sequence Control Register + 0x204 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + MIX_PDNSCR + GPC PGC Down Sequence Control Register + 0x208 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + MIX_SR + GPC PGC Status Register + 0x20C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + MIX_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x210 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU0_CTRL + GPC PGC Control Register + 0x400 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU0_PUPSCR + GPC PGC Up Sequence Control Register + 0x404 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU0_PDNSCR + GPC PGC Down Sequence Control Register + 0x408 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU0_SR + GPC PGC Status Register + 0x40C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU0_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x410 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU1_CTRL + GPC PGC Control Register + 0x440 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU1_PUPSCR + GPC PGC Up Sequence Control Register + 0x444 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU1_PDNSCR + GPC PGC Down Sequence Control Register + 0x448 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU1_SR + GPC PGC Status Register + 0x44C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU1_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x450 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU2_CTRL + GPC PGC Control Register + 0x480 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU2_PUPSCR + GPC PGC Up Sequence Control Register + 0x484 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU2_PDNSCR + GPC PGC Down Sequence Control Register + 0x488 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU2_SR + GPC PGC Status Register + 0x48C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU2_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x490 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU3_CTRL + GPC PGC Control Register + 0x4C0 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU3_PUPSCR + GPC PGC Up Sequence Control Register + 0x4C4 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU3_PDNSCR + GPC PGC Down Sequence Control Register + 0x4C8 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU3_SR + GPC PGC Status Register + 0x4CC + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU3_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x4D0 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU4_CTRL + GPC PGC Control Register + 0x500 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU4_PUPSCR + GPC PGC Up Sequence Control Register + 0x504 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU4_PDNSCR + GPC PGC Down Sequence Control Register + 0x508 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU4_SR + GPC PGC Status Register + 0x50C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU4_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x510 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU5_CTRL + GPC PGC Control Register + 0x540 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU5_PUPSCR + GPC PGC Up Sequence Control Register + 0x544 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU5_PDNSCR + GPC PGC Down Sequence Control Register + 0x548 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU5_SR + GPC PGC Status Register + 0x54C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU5_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x550 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU6_CTRL + GPC PGC Control Register + 0x580 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU6_PUPSCR + GPC PGC Up Sequence Control Register + 0x584 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU6_PDNSCR + GPC PGC Down Sequence Control Register + 0x588 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU6_SR + GPC PGC Status Register + 0x58C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU6_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x590 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU7_CTRL + GPC PGC Control Register + 0x5C0 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU7_PUPSCR + GPC PGC Up Sequence Control Register + 0x5C4 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU7_PDNSCR + GPC PGC Down Sequence Control Register + 0x5C8 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU7_SR + GPC PGC Status Register + 0x5CC + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU7_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x5D0 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU8_CTRL + GPC PGC Control Register + 0x600 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU8_PUPSCR + GPC PGC Up Sequence Control Register + 0x604 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU8_PDNSCR + GPC PGC Down Sequence Control Register + 0x608 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU8_SR + GPC PGC Status Register + 0x60C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU8_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x610 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU9_CTRL + GPC PGC Control Register + 0x640 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU9_PUPSCR + GPC PGC Up Sequence Control Register + 0x644 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU9_PDNSCR + GPC PGC Down Sequence Control Register + 0x648 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU9_SR + GPC PGC Status Register + 0x64C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU9_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x650 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU10_CTRL + GPC PGC Control Register + 0x680 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU10_PUPSCR + GPC PGC Up Sequence Control Register + 0x684 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU10_PDNSCR + GPC PGC Down Sequence Control Register + 0x688 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU10_SR + GPC PGC Status Register + 0x68C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU10_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x690 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU11_CTRL + GPC PGC Control Register + 0x6C0 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU11_PUPSCR + GPC PGC Up Sequence Control Register + 0x6C4 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU11_PDNSCR + GPC PGC Down Sequence Control Register + 0x6C8 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU11_SR + GPC PGC Status Register + 0x6CC + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU11_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x6D0 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU12_CTRL + GPC PGC Control Register + 0x700 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU12_PUPSCR + GPC PGC Up Sequence Control Register + 0x704 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU12_PDNSCR + GPC PGC Down Sequence Control Register + 0x708 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU12_SR + GPC PGC Status Register + 0x70C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU12_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x710 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + PU13_CTRL + GPC PGC Control Register + 0x740 + 32 + read-write + 0x6040202 + 0xFFFFFFFF + + + PCR + Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + L2RSTDIS + After scu pdn_req, count this value to assert A53 l2rstdis to 1'b1, it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC) + 1 + 6 + read-write + + + DFTRAM_TCD1 + After scu pdn_req, count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 6 + read-write + + + L2RETN_TCD1_TDR + After scu pdn_req, count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC) + 16 + 6 + read-write + + + MEMPWR_TCD1_TDR_TRM + After scu pdn_req, count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC) + 24 + 6 + read-write + + + + + PU13_PUPSCR + GPC PGC Up Sequence Control Register + 0x744 + 32 + read-write + 0x997C1 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero + 0 + 6 + read-write + + + PUP_WAIT_SCALL_OUT + After SCALL asserting to 1'b0, wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC) + 6 + 1 + read-write + + + SW2ISO + After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation + 7 + 16 + read-write + + + PUP_SCALL_SCALLOUT_CNT + After SCALL asserting to 1'b0, count this value to complete switch power up Only valid when pup_wait_scall_out is set to 1'b0 + 23 + 9 + read-write + + + + + PU13_PDNSCR + GPC PGC Down Sequence Control Register + 0x748 + 32 + read-write + 0x21000801 + 0xFFFFFFFF + + + ISO + Aafte a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero + 0 + 6 + read-write + + + PDN_WAIT_SCALL_OUT + Default 1'b0 + 7 + 1 + read-write + + + ISO2SW + After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero + 8 + 6 + read-write + + + PDN_SCALL_SCALLOUT_CNT + Default 8'h0 + 16 + 8 + read-write + + + PUP_SCPRE_SCALL_CNT + After SCPRE asserting to 1'b0, count this value to assert SCALL to 1'b0 (This register control only for MIX Type PGC) + 24 + 8 + read-write + + + + + PU13_SR + GPC PGC Status Register + 0x74C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-only + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + L2RETN_FLAG + L2 Retention Flag Software should write "1" to clear this flag after A53 is wakeup from L2 retention mode, otherwise it will always keep to 1 (This register control only for SCU Type PGC) + 1 + 1 + read-only + + + L2RETN_FLAG_0 + A53 is not wakeup from L2 retention mode. + 0 + + + L2RETN_FLAG_1 + A53 is wakeup from L2 retention mode. + 0x1 + + + + + ALLOFF_FLAG + All-off flag + 2 + 1 + read-only + + + ALLOFF_FLAG_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ALLOFF_FLAG_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PUP_CLK_DIV_SEL + Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC, ipg_clk(66MHz) for MIX/PU Type PGC) + 3 + 4 + read-write + + + PUP_CLK_DIV_SEL_0 + 1 + 0 + + + PUP_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PUP_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PUP_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PUP_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PUP_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PUP_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PUP_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PUP_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PUP_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PUP_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PUP_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PUP_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PUP_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PUP_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PUP_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + L2RSTDIS_DEASSERT_CNT + Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC) + 8 + 10 + read-write + + + + + PU13_AUXSW + GPC PGC Auxiliary Power Switch Control Register + 0x750 + 32 + read-write + 0x131 + 0xFFFFFFFF + + + SW2 + After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW2 before asserting switch2_b(1P8 Power) SW2 must not be programmed to zero + 0 + 6 + read-write + + + ISO2SW2 + after asserting isolation by power-down request(pdn_req assertion), the PGC waits a number of clocks equal to the value of ISO2SW2 before negating switch2_b(1P8 Power) ISO2SW2 must not be programmed to zero + 8 + 6 + read-only + + + ISO2SW2_0 + A53 is not wakeup from ALL_OFF mode. + 0 + + + ISO2SW2_1 + A53 is wakeup from ALL_OFF mode. + 0x1 + + + + + PDN_CLK_DIV_SEL + Clock divider select for the clock of power down counter + 16 + 4 + read-write + + + PDN_CLK_DIV_SEL_0 + 1 + 0 + + + PDN_CLK_DIV_SEL_1 + 1/2 count_clk + 0x1 + + + PDN_CLK_DIV_SEL_2 + 1/4 count_clk + 0x2 + + + PDN_CLK_DIV_SEL_3 + 1/8 count_clk + 0x3 + + + PDN_CLK_DIV_SEL_4 + 1/16 count_clk + 0x4 + + + PDN_CLK_DIV_SEL_5 + 1/32 count_clk + 0x5 + + + PDN_CLK_DIV_SEL_6 + 1/64 count_clk + 0x6 + + + PDN_CLK_DIV_SEL_7 + 1/128 count_clk + 0x7 + + + PDN_CLK_DIV_SEL_8 + 1/256 count_clk + 0x8 + + + PDN_CLK_DIV_SEL_9 + 1/512 count_clk + 0x9 + + + PDN_CLK_DIV_SEL_10 + 1/1024 count_clk + 0xA + + + PDN_CLK_DIV_SEL_11 + 1/2056 count_clk + 0xB + + + PDN_CLK_DIV_SEL_12 + 1/4096 count_clk + 0xC + + + PDN_CLK_DIV_SEL_13 + 1/8192 count_clk + 0xD + + + PDN_CLK_DIV_SEL_14 + 1/16384 count_clk + 0xE + + + PDN_CLK_DIV_SEL_15 + 1/32768 count_clk + 0xF + + + + + + + + + RDC_SEMAPHORE1 + SEMA42 + RDC_SEMAPHORE + RDC_SEMAPHORE1_ + RDC_SEMAPHORE + 0x303B0000 + + 0 + 0x42 + registers + + + + 64 + 0x1 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 + GATE%s + Gate Register + 0 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 4 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor with master_index = 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor with master_index = 1. + 0x2 + + + GTFSM_3 + The gate has been locked by processor with master_index = 2. + 0x3 + + + GTFSM_4 + The gate has been locked by processor with master_index = 3. + 0x4 + + + GTFSM_5 + The gate has been locked by processor with master_index = 4. + 0x5 + + + GTFSM_6 + The gate has been locked by processor with master_index = 5. + 0x6 + + + GTFSM_7 + The gate has been locked by processor with master_index = 6. + 0x7 + + + GTFSM_8 + The gate has been locked by processor with master_index = 7. + 0x8 + + + GTFSM_9 + The gate has been locked by processor with master_index = 8. + 0x9 + + + GTFSM_10 + The gate has been locked by processor with master_index = 9. + 0xA + + + GTFSM_11 + The gate has been locked by processor with master_index = 10. + 0xB + + + GTFSM_12 + The gate has been locked by processor with master_index = 11. + 0xC + + + GTFSM_13 + The gate has been locked by processor with master_index = 12. + 0xD + + + GTFSM_14 + The gate has been locked by processor with master_index = 13. + 0xE + + + GTFSM_15 + The gate has been locked by processor with master_index = 14. + 0xF + + + + + LDOM + Read-only bits. They indicate which domain had currently locked the gate. + 4 + 2 + read-only + + + LDOM_0 + The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + 0 + + + LDOM_1 + The gate has been locked by domain 1. + 0x1 + + + LDOM_2 + The gate has been locked by domain 2. + 0x2 + + + LDOM_3 + The gate has been locked by domain 3. + 0x3 + + + + + + + RSTGT_R + Reset Gate Read + RSTGT_R_RSTGT_W + 0x40 + 16 + read-write + 0 + 0xFFFF + + + RSTGMS + Reset Gate Bus Master + 0 + 4 + read-only + + + RSTGSM + Reset Gate Finite State Machine + 4 + 2 + read-only + + + RSTGSM_0 + Idle, waiting for the first data pattern write. + 0 + + + RSTGSM_1 + Waiting for the second data pattern write. + 0x1 + + + RSTGSM_2 + The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists for only one clock cycle. Software will never be able to observe this state. + 0x2 + + + RSTGSM_3 + This state encoding is never used and therefore reserved. + 0x3 + + + + + RSTGTN + Reset Gate Number + 8 + 8 + read-write + + + + + RSTGT_W + Reset Gate Write + RSTGT_R_RSTGT_W + 0x40 + 16 + read-write + 0 + 0xFFFF + + + RSTGDP + Reset Gate Data Pattern + 0 + 8 + write-only + + + RSTGTN + Reset Gate Number + 8 + 8 + read-write + + + + + + + RDC_SEMAPHORE2 + SEMA42 + RDC_SEMAPHORE + RDC_SEMAPHORE2_ + 0x303C0000 + + 0 + 0x42 + registers + + + + RDC + RDC + RDC + RDC_ + 0x303D0000 + + 0 + 0xB40 + registers + + + RDC + 39 + + + + VIR + Version Information + 0 + 32 + read-only + 0x376E204 + 0xFFFFFFFF + + + NDID + Number of Domains + 0 + 4 + read-only + + + NMSTR + Number of Masters + 4 + 8 + read-only + + + NPER + Number of Peripherals + 12 + 8 + read-only + + + NRGN + Number of Memory Regions + 20 + 8 + read-only + + + + + STAT + Status + 0x24 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + DID + Domain ID + 0 + 4 + read-write + + + PDS + Power Domain Status + 8 + 1 + read-write + + + PDS_0 + Power Down Domain is OFF + 0 + + + PDS_1 + Power Down Domain is ON + 0x1 + + + + + + + INTCTRL + Interrupt and Control + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + RCI_EN + Restoration Complete Interrupt + 0 + 1 + read-write + + + RCI_EN_0 + Interrupt Disabled + 0 + + + RCI_EN_1 + Interrupt Enabled + 0x1 + + + + + + + INTSTAT + Interrupt Status + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + INT + Interrupt Status + 0 + 1 + read-write + oneToClear + + + INT_0 + No Interrupt Pending + 0 + + + INT_1 + Interrupt Pending + 0x1 + + + + + + + 27 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26 + MDA%s + Master Domain Assignment + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + DID + Domain ID + 0 + 2 + read-write + + + DID_0 + Master assigned to Processing Domain 0 + 0 + + + DID_1 + Master assigned to Processing Domain 1 + 0x1 + + + DID_2 + Master assigned to Processing Domain 2 + 0x2 + + + DID_3 + Master assigned to Processing Domain 3 + 0x3 + + + + + LCK + no description available + 31 + 1 + read-write + + + LCK_0 + Not Locked + 0 + + + LCK_1 + Locked + 0x1 + + + + + + + 118 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117 + PDAP%s + Peripheral Domain Access Permissions + 0x400 + 32 + read-write + 0xFF + 0xFFFFFFFF + + + D0W + Domain 0 Write Access + 0 + 1 + read-write + + + D0W_0 + No Write Access + 0 + + + D0W_1 + Write Access Allowed + 0x1 + + + + + D0R + Domain 0 Read Access + 1 + 1 + read-write + + + D0R_0 + No Read Access + 0 + + + D0R_1 + Read Access Allowed + 0x1 + + + + + D1W + Domain 1 Write Access + 2 + 1 + read-write + + + D1W_0 + No Write Access + 0 + + + D1W_1 + Write Access Allowed + 0x1 + + + + + D1R + Domain 1 Read Access + 3 + 1 + read-write + + + D1R_0 + No Read Access + 0 + + + D1R_1 + Read Access Allowed + 0x1 + + + + + D2W + Domain 2 Write Access + 4 + 1 + read-write + + + D2W_0 + No Write Access + 0 + + + D2W_1 + Write Access Allowed + 0x1 + + + + + D2R + Domain 2 Read Access + 5 + 1 + read-write + + + D2R_0 + No Read Access + 0 + + + D2R_1 + Read Access Allowed + 0x1 + + + + + D3W + Domain 3 Write Access + 6 + 1 + read-write + + + D3W_0 + No Write Access + 0 + + + D3W_1 + Write Access Allowed + 0x1 + + + + + D3R + Domain 3 Read Access + 7 + 1 + read-write + + + D3R_0 + No Read Access + 0 + + + D3R_1 + Read Access Allowed + 0x1 + + + + + SREQ + Semaphore Required + 30 + 1 + read-write + + + SREQ_0 + Semaphores have no effect + 0 + + + SREQ_1 + Semaphores are enforced + 0x1 + + + + + LCK + Peripheral Permissions Lock + 31 + 1 + read-write + + + LCK_0 + Not Locked + 0 + + + LCK_1 + Locked + 0x1 + + + + + + + 52 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51 + MRSA%s + Memory Region Start Address + 0x800 + 32 + read-write + 0 + 0 + + + SADR + Start address for memory region + 7 + 25 + read-write + + + + + 52 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51 + MREA%s + Memory Region End Address + 0x804 + 32 + read-write + 0 + 0 + + + EADR + Upper bound for memory region + 7 + 25 + read-write + + + + + 52 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51 + MRC%s + Memory Region Control + 0x808 + 32 + read-write + 0xFF + 0xFFFFFFFF + + + D0W + Domain 0 Write Access to Region + 0 + 1 + read-write + + + D0W_0 + Processing Domain 0 does not have Write access to the memory region + 0 + + + D0W_1 + Processing Domain 0 has Write access to the memory region + 0x1 + + + + + D0R + Domain 0 Read Access to Region + 1 + 1 + read-write + + + D0R_0 + Processing Domain 0 does not have Read access to the memory region + 0 + + + D0R_1 + Processing Domain 0 has Read access to the memory region + 0x1 + + + + + D1W + Domain 1 Write Access to Region + 2 + 1 + read-write + + + D1W_0 + Processing Domain 1 does not have Write access to the memory region + 0 + + + D1W_1 + Processing Domain 1 has Write access to the memory region + 0x1 + + + + + D1R + Domain 1 Read Access to Region + 3 + 1 + read-write + + + D1R_0 + Processing Domain 1 does not have Read access to the memory region + 0 + + + D1R_1 + Processing Domain 1 has Read access to the memory region + 0x1 + + + + + D2W + Domain 2 Write Access to Region + 4 + 1 + read-write + + + D2W_0 + Processing Domain 2 does not have Write access to the memory region + 0 + + + D2W_1 + Processing Domain 2 has Write access to the memory region + 0x1 + + + + + D2R + Domain 2 Read Access to Region + 5 + 1 + read-write + + + D2R_0 + Processing Domain 2 does not have Read access to the memory region + 0 + + + D2R_1 + Processing Domain 2 has Read access to the memory region + 0x1 + + + + + D3W + Domain 3 Write Access to Region + 6 + 1 + read-write + + + D3W_0 + Processing Domain 3 does not have Write access to the memory region + 0 + + + D3W_1 + Processing Domain 3 has Read access to the memory region + 0x1 + + + + + D3R + Domain 3 Read Access to Region + 7 + 1 + read-write + + + D3R_0 + Processing Domain 3 does not have Read access to the memory region + 0 + + + D3R_1 + Processing Domain 3 has Read access to the memory region + 0x1 + + + + + ENA + Region Enable + 30 + 1 + read-write + + + ENA_0 + Memory region is not defined or restricted. + 0 + + + ENA_1 + Memory boundaries, domain permissions and controls are in effect. + 0x1 + + + + + LCK + Region Lock + 31 + 1 + read-write + + + LCK_0 + No Lock. All fields in this register may be modified. + 0 + + + LCK_1 + Locked. No fields in this register may be modified except ENA, which may be set but not cleared. + 0x1 + + + + + + + 52 + 0x10 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51 + MRVS%s + Memory Region Violation Status + 0x80C + 32 + read-write + 0 + 0xFFFFFFFF + + + VDID + Violating Domain ID + 0 + 2 + read-only + + + VDID_0 + Processing Domain 0 + 0 + + + VDID_1 + Processing Domain 1 + 0x1 + + + VDID_2 + Processing Domain 2 + 0x2 + + + VDID_3 + Processing Domain 3 + 0x3 + + + + + AD + Access Denied + 4 + 1 + read-write + oneToClear + + + VADR + Violating Address + 5 + 27 + read-only + + + + + + + PWM1 + PWM + PWM + PWM1_ + PWM + 0x30660000 + + 0 + 0x18 + registers + + + PWM1 + 81 + + + + PWMCR + PWM Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + PWM Enable + 0 + 1 + read-write + + + EN_0 + PWM disabled + 0 + + + EN_1 + PWM enabled + 0x1 + + + + + REPEAT + Sample Repeat + 1 + 2 + read-write + + + REPEAT_0 + Use each sample once + 0 + + + REPEAT_1 + Use each sample twice + 0x1 + + + REPEAT_2 + Use each sample four times + 0x2 + + + REPEAT_3 + Use each sample eight times + 0x3 + + + + + SWR + Software Reset + 3 + 1 + read-write + + + SWR_0 + PWM is out of reset + 0 + + + SWR_1 + PWM is undergoing reset + 0x1 + + + + + PRESCALER + Counter Clock Prescaler Value + 4 + 12 + read-write + + + PRESCALER_0 + Divide by 1 + 0 + + + PRESCALER_1 + Divide by 2 + 0x1 + + + PRESCALER_4095 + Divide by 4096 + 0xFFF + + + + + CLKSRC + Select Clock Source + 16 + 2 + read-write + + + CLKSRC_0 + Clock is off + 0 + + + CLKSRC_1 + ipg_clk + 0x1 + + + CLKSRC_2 + ipg_clk_highfreq + 0x2 + + + CLKSRC_3 + ipg_clk_32k + 0x3 + + + + + POUTC + PWM Output Configuration. This bit field determines the mode of PWM output on the output pin. + 18 + 2 + read-write + + + POUTC_0 + Output pin is set at rollover and cleared at comparison + 0 + + + POUTC_1 + Output pin is cleared at rollover and set at comparison + 0x1 + + + POUTC_2 + PWM output is disconnected + 0x2 + + + POUTC_3 + PWM output is disconnected + 0x3 + + + + + HCTR + Half-word Data Swap Control + 20 + 1 + read-write + + + HCTR_0 + Half word swapping does not take place + 0 + + + HCTR_1 + Half words from write data bus are swapped + 0x1 + + + + + BCTR + Byte Data Swap Control + 21 + 1 + read-write + + + BCTR_0 + byte ordering remains the same + 0 + + + BCTR_1 + byte ordering is reversed + 0x1 + + + + + DBGEN + Debug Mode Enable + 22 + 1 + read-write + + + DBGEN_0 + Inactive in debug mode + 0 + + + DBGEN_1 + Active in debug mode + 0x1 + + + + + WAITEN + Wait Mode Enable + 23 + 1 + read-write + + + WAITEN_0 + Inactive in wait mode + 0 + + + WAITEN_1 + Active in wait mode + 0x1 + + + + + DOZEN + Doze Mode Enable + 24 + 1 + read-write + + + DOZEN_0 + Inactive in doze mode + 0 + + + DOZEN_1 + Active in doze mode + 0x1 + + + + + STOPEN + Stop Mode Enable + 25 + 1 + read-write + + + STOPEN_0 + Inactive in stop mode + 0 + + + STOPEN_1 + Active in stop mode + 0x1 + + + + + FWM + FIFO Water Mark + 26 + 2 + read-write + + + FWM_0 + FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO + 0 + + + FWM_1 + FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO + 0x1 + + + FWM_2 + FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO + 0x2 + + + FWM_3 + FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO + 0x3 + + + + + + + PWMSR + PWM Status Register + 0x4 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOAV + FIFO Available + 0 + 3 + read-only + + + FIFOAV_0 + No data available + 0 + + + FIFOAV_1 + 1 word of data in FIFO + 0x1 + + + FIFOAV_2 + 2 words of data in FIFO + 0x2 + + + FIFOAV_3 + 3 words of data in FIFO + 0x3 + + + FIFOAV_4 + 4 words of data in FIFO + 0x4 + + + FIFOAV_5 + unused + 0x5 + + + FIFOAV_6 + unused + 0x6 + + + FIFOAV_7 + unused + 0x7 + + + + + FE + FIFO Empty Status Bit + 3 + 1 + read-write + oneToClear + + + FE_0 + Data level is above water mark + 0 + + + FE_1 + When the data level falls below the mark set by FWM field + 0x1 + + + + + ROV + Roll-over Status. This bit shows that a roll-over event has occurred. + 4 + 1 + read-write + oneToClear + + + ROV_0 + Roll-over event not occurred + 0 + + + ROV_1 + Roll-over event occurred + 0x1 + + + + + CMP + Compare Status. This bit shows that a compare event has occurred. + 5 + 1 + read-write + oneToClear + + + CMP_0 + Compare event not occurred + 0 + + + CMP_1 + Compare event occurred + 0x1 + + + + + FWE + FIFO Write Error Status + 6 + 1 + read-write + oneToClear + + + FWE_0 + FIFO write error not occurred + 0 + + + FWE_1 + FIFO write error occurred + 0x1 + + + + + + + PWMIR + PWM Interrupt Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIE + FIFO Empty Interrupt Enable. This bit controls the generation of the FIFO Empty interrupt. + 0 + 1 + read-write + + + FIE_0 + FIFO Empty interrupt disabled + 0 + + + FIE_1 + FIFO Empty interrupt enabled + 0x1 + + + + + RIE + Roll-over Interrupt Enable. This bit controls the generation of the Rollover interrupt. + 1 + 1 + read-write + + + RIE_0 + Roll-over interrupt not enabled + 0 + + + RIE_1 + Roll-over Interrupt enabled + 0x1 + + + + + CIE + Compare Interrupt Enable. This bit controls the generation of the Compare interrupt. + 2 + 1 + read-write + + + CIE_0 + Compare Interrupt not enabled + 0 + + + CIE_1 + Compare Interrupt enabled + 0x1 + + + + + + + PWMSAR + PWM Sample Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE + Sample Value + 0 + 16 + read-write + + + + + PWMPR + PWM Period Register + 0x10 + 32 + read-write + 0xFFFE + 0xFFFFFFFF + + + PERIOD + Period Value + 0 + 16 + read-write + + + + + PWMCNR + PWM Counter Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Counter Value + 0 + 16 + read-only + + + + + + + PWM2 + PWM + PWM + PWM2_ + 0x30670000 + + 0 + 0x18 + registers + + + PWM2 + 82 + + + + PWM3 + PWM + PWM + PWM3_ + 0x30680000 + + 0 + 0x18 + registers + + + PWM3 + 83 + + + + PWM4 + PWM + PWM + PWM4_ + 0x30690000 + + 0 + 0x18 + registers + + + PWM4 + 84 + + + + SPDIF1 + SPDIF + SPDIF + SPDIF1_ + SPDIF + 0x30810000 + + 0 + 0x54 + registers + + + SPDIF1 + 6 + + + + SCR + SPDIF Configuration Register + 0 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + USrc_Sel + no description available + 0 + 2 + read-write + + + USrc_Sel_0 + No embedded U channel + 0 + + + USrc_Sel_1 + U channel from SPDIF receive block (CD mode) + 0x1 + + + USrc_Sel_3 + U channel from on chip transmitter + 0x3 + + + + + TxSel + no description available + 2 + 3 + read-write + + + TxSel_0 + Off and output 0 + 0 + + + TxSel_1 + Feed-through SPDIFIN + 0x1 + + + TxSel_5 + Tx Normal operation + 0x5 + + + + + ValCtrl + no description available + 5 + 1 + read-write + + + ValCtrl_0 + Outgoing Validity always set + 0 + + + ValCtrl_1 + Outgoing Validity always clear + 0x1 + + + + + DMA_TX_En + DMA Transmit Request Enable (Tx FIFO empty) + 8 + 1 + read-write + + + DMA_Rx_En + DMA Receive Request Enable (RX FIFO full) + 9 + 1 + read-write + + + TxFIFO_Ctrl + no description available + 10 + 2 + read-write + + + TxFIFO_Ctrl_0 + Send out digital zero on SPDIF Tx + 0 + + + TxFIFO_Ctrl_1 + Tx Normal operation + 0x1 + + + TxFIFO_Ctrl_2 + Reset to 1 sample remaining + 0x2 + + + + + soft_reset + When write 1 to this bit, it will cause SPDIF software reset + 12 + 1 + read-write + + + LOW_POWER + When write 1 to this bit, it will cause SPDIF enter low-power mode + 13 + 1 + read-write + + + TxFIFOEmpty_Sel + no description available + 15 + 2 + read-write + + + TxFIFOEmpty_Sel_0 + Empty interrupt if 0 sample in Tx left and right FIFOs + 0 + + + TxFIFOEmpty_Sel_1 + Empty interrupt if at most 4 sample in Tx left and right FIFOs + 0x1 + + + TxFIFOEmpty_Sel_2 + Empty interrupt if at most 8 sample in Tx left and right FIFOs + 0x2 + + + TxFIFOEmpty_Sel_3 + Empty interrupt if at most 12 sample in Tx left and right FIFOs + 0x3 + + + + + TxAutoSync + no description available + 17 + 1 + read-write + + + TxAutoSync_0 + Tx FIFO auto sync off + 0 + + + TxAutoSync_1 + Tx FIFO auto sync on + 0x1 + + + + + RxAutoSync + no description available + 18 + 1 + read-write + + + RxAutoSync_0 + Rx FIFO auto sync off + 0 + + + RxAutoSync_1 + RxFIFO auto sync on + 0x1 + + + + + RxFIFOFull_Sel + no description available + 19 + 2 + read-write + + + RxFIFOFull_Sel_0 + Full interrupt if at least 1 sample in Rx left and right FIFOs + 0 + + + RxFIFOFull_Sel_1 + Full interrupt if at least 4 sample in Rx left and right FIFOs + 0x1 + + + RxFIFOFull_Sel_2 + Full interrupt if at least 8 sample in Rx left and right FIFOs + 0x2 + + + RxFIFOFull_Sel_3 + Full interrupt if at least 16 sample in Rx left and right FIFO + 0x3 + + + + + RxFIFO_Rst + no description available + 21 + 1 + read-write + + + RxFIFO_Rst_0 + Normal operation + 0 + + + RxFIFO_Rst_1 + Reset register to 1 sample remaining + 0x1 + + + + + RxFIFO_Off_On + no description available + 22 + 1 + read-write + + + RxFIFO_Off_On_0 + SPDIF Rx FIFO is on + 0 + + + RxFIFO_Off_On_1 + SPDIF Rx FIFO is off. Does not accept data from interface + 0x1 + + + + + RxFIFO_Ctrl + no description available + 23 + 1 + read-write + + + RxFIFO_Ctrl_0 + Normal operation + 0 + + + RxFIFO_Ctrl_1 + Always read zero from Rx data register + 0x1 + + + + + + + SRCD + CDText Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + USyncMode + no description available + 1 + 1 + read-write + + + USyncMode_0 + Non-CD data + 0 + + + USyncMode_1 + CD user channel subcode + 0x1 + + + + + + + SRPC + PhaseConfig Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + GainSel + Gain selection: + 3 + 3 + read-write + + + GainSel_0 + 24*(2**10) + 0 + + + GainSel_1 + 16*(2**10) + 0x1 + + + GainSel_2 + 12*(2**10) + 0x2 + + + GainSel_3 + 8*(2**10) + 0x3 + + + GainSel_4 + 6*(2**10) + 0x4 + + + GainSel_5 + 4*(2**10) + 0x5 + + + GainSel_6 + 3*(2**10) + 0x6 + + + + + LOCK + LOCK bit to show that the internal DPLL is locked, read only + 6 + 1 + read-only + + + ClkSrc_Sel + Clock source selection, all other settings not shown are reserved: + 7 + 4 + read-write + + + ClkSrc_Sel_0 + if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + 0 + + + ClkSrc_Sel_1 + if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + 0x1 + + + ClkSrc_Sel_3 + if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + 0x3 + + + ClkSrc_Sel_5 + REF_CLK_32K (XTALOSC) + 0x5 + + + ClkSrc_Sel_6 + tx_clk (SPDIF0_CLK_ROOT) + 0x6 + + + ClkSrc_Sel_8 + SPDIF_EXT_CLK + 0x8 + + + + + + + SIE + InterruptEn Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-write + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 1 + 1 + read-write + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + read-write + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + read-write + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + read-write + + + UQErr + U/Q Channel framing error + 5 + 1 + read-write + + + UQSync + U/Q Channel sync found + 6 + 1 + read-write + + + QRxOv + Q Channel receive register overrun + 7 + 1 + read-write + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 8 + 1 + read-write + + + URxOv + U Channel receive register overrun + 9 + 1 + read-write + + + URxFul + U Channel receive register full, can't be cleared with reg + 10 + 1 + read-write + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + read-write + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + read-write + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + read-write + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + read-write + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + read-write + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + read-write + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + read-write + + + + + SIC + InterruptClear Register + SIC_SIS + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + write-only + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + write-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + write-only + + + UQErr + U/Q Channel framing error + 5 + 1 + write-only + + + UQSync + U/Q Channel sync found + 6 + 1 + write-only + + + QRxOv + Q Channel receive register overrun + 7 + 1 + write-only + + + URxOv + U Channel receive register overrun + 9 + 1 + write-only + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + write-only + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + write-only + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + write-only + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + write-only + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + write-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + write-only + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + write-only + + + + + SIS + InterruptStat Register + SIC_SIS + 0x10 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-only + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 1 + 1 + read-only + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + read-only + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + read-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + read-only + + + UQErr + U/Q Channel framing error + 5 + 1 + read-only + + + UQSync + U/Q Channel sync found + 6 + 1 + read-only + + + QRxOv + Q Channel receive register overrun + 7 + 1 + read-only + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 8 + 1 + read-only + + + URxOv + U Channel receive register overrun + 9 + 1 + read-only + + + URxFul + U Channel receive register full, can't be cleared with reg + 10 + 1 + read-only + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + read-only + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + read-only + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + read-only + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + read-only + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + read-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + read-only + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + read-only + + + + + SRL + SPDIFRxLeft Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataLeft + Processor receive SPDIF data left + 0 + 24 + read-only + + + + + SRR + SPDIFRxRight Register + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataRight + Processor receive SPDIF data right + 0 + 24 + read-only + + + + + SRCSH + SPDIFRxCChannel_h Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_h + SPDIF receive C channel register, contains first 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRCSL + SPDIFRxCChannel_l Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_l + SPDIF receive C channel register, contains next 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRU + UchannelRx Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxUChannel + SPDIF receive U channel register, contains next 3 U channel bytes + 0 + 24 + read-only + + + + + SRQ + QchannelRx Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxQChannel + SPDIF receive Q channel register, contains next 3 Q channel bytes + 0 + 24 + read-only + + + + + STL + SPDIFTxLeft Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataLeft + SPDIF transmit left channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STR + SPDIFTxRight Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataRight + SPDIF transmit right channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STCSCH + SPDIFTxCChannelCons_h Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_h + SPDIF transmit Cons + 0 + 24 + read-write + + + + + STCSCL + SPDIFTxCChannelCons_l Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_l + SPDIF transmit Cons + 0 + 24 + read-write + + + + + SRFM + FreqMeas Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + FreqMeas + Frequency measurement data + 0 + 24 + read-only + + + + + STC + SPDIFTxClk Register + 0x50 + 32 + read-write + 0x20F00 + 0xFFFFFFFF + + + TxClk_DF + Divider factor (1-128) + 0 + 7 + read-write + + + TxClk_DF_0 + divider factor is 1 + 0 + + + TxClk_DF_1 + divider factor is 2 + 0x1 + + + TxClk_DF_127 + divider factor is 128 + 0x7F + + + + + tx_all_clk_en + Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1. + 7 + 1 + read-write + + + tx_all_clk_en_0 + disable transfer clock. + 0 + + + tx_all_clk_en_1 + enable transfer clock. + 0x1 + + + + + TxClk_Source + no description available + 8 + 3 + read-write + + + TxClk_Source_0 + REF_CLK_32K input (XTALOSC 32 kHz clock) + 0 + + + TxClk_Source_1 + tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + 0x1 + + + TxClk_Source_3 + SPDIF_EXT_CLK, from pads + 0x3 + + + TxClk_Source_5 + ipg_clk input (frequency divided) + 0x5 + + + + + SYSCLK_DF + system clock divider factor, 2~512. + 11 + 9 + read-write + + + SYSCLK_DF_0 + no clock signal + 0 + + + SYSCLK_DF_1 + divider factor is 2 + 0x1 + + + SYSCLK_DF_511 + divider factor is 512 + 0x1FF + + + + + + + + + SPDIF2 + SPDIF + SPDIF + SPDIF2_ + 0x308A0000 + + 0 + 0x54 + registers + + + SPDIF2 + 13 + + + + ECSPI1 + ECSPI + ECSPI + ECSPI1_ + ECSPI + 0x30820000 + + 0 + 0x44 + registers + + + ECSPI1 + 31 + + + + RXDATA + Receive Data Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ECSPI_RXDATA + Receive Data + 0 + 32 + read-only + + + + + TXDATA + Transmit Data Register + 0x4 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_TXDATA + Transmit Data + 0 + 32 + write-only + + + + + CONREG + Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + SPI Block Enable Control + 0 + 1 + read-write + + + EN_0 + Disable the block. + 0 + + + EN_1 + Enable the block. + 0x1 + + + + + HT + Hardware Trigger Enable + 1 + 1 + read-write + + + HT_0 + Disable HT mode. + 0 + + + HT_1 + Enable HT mode. + 0x1 + + + + + XCH + SPI Exchange Bit + 2 + 1 + read-write + + + XCH_0 + Idle. + 0 + + + XCH_1 + Initiates exchange (write) or busy (read). + 0x1 + + + + + SMC + Start Mode Control + 3 + 1 + read-write + + + SMC_0 + SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL descriptions. + 0 + + + SMC_1 + Immediately starts a SPI burst when data is written in TXFIFO. + 0x1 + + + + + CHANNEL_MODE + SPI CHANNEL MODE selects the mode for each SPI channel + 4 + 4 + read-write + + + CHANNEL_MODE_0 + Slave mode. + 0 + + + CHANNEL_MODE_1 + Master mode. + 0x1 + + + + + POST_DIVIDER + SPI Post Divider + 8 + 4 + read-write + + + POST_DIVIDER_0 + Divide by 1. + 0 + + + POST_DIVIDER_1 + Divide by 2. + 0x1 + + + POST_DIVIDER_2 + Divide by 4. + 0x2 + + + POST_DIVIDER_14 + Divide by 2 14 . + 0xE + + + POST_DIVIDER_15 + Divide by 2 15 . + 0xF + + + + + PRE_DIVIDER + SPI Pre Divider + 12 + 4 + read-write + + + PRE_DIVIDER_0 + Divide by 1. + 0 + + + PRE_DIVIDER_1 + Divide by 2. + 0x1 + + + PRE_DIVIDER_2 + Divide by 3. + 0x2 + + + PRE_DIVIDER_13 + Divide by 14. + 0xD + + + PRE_DIVIDER_14 + Divide by 15. + 0xE + + + PRE_DIVIDER_15 + Divide by 16. + 0xF + + + + + DRCTL + SPI Data Ready Control + 16 + 2 + read-write + + + DRCTL_0 + The SPI_RDY signal is a don't care. + 0 + + + DRCTL_1 + Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered). + 0x1 + + + DRCTL_2 + Burst will be triggered by a low level of the SPI_RDY signal (level-triggered). + 0x2 + + + + + CHANNEL_SELECT + SPI CHANNEL SELECT bits + 18 + 2 + read-write + + + CHANNEL_SELECT_0 + Channel 0 is selected. Chip Select 0 (SS0) will be asserted. + 0 + + + CHANNEL_SELECT_1 + Channel 1 is selected. Chip Select 1 (SS1) will be asserted. + 0x1 + + + CHANNEL_SELECT_2 + Channel 2 is selected. Chip Select 2 (SS2) will be asserted. + 0x2 + + + CHANNEL_SELECT_3 + Channel 3 is selected. Chip Select 3 (SS3) will be asserted. + 0x3 + + + + + BURST_LENGTH + Burst Length + 20 + 12 + read-write + + + BURST_LENGTH_0 + A SPI burst contains the 1 LSB in a word. + 0 + + + BURST_LENGTH_1 + A SPI burst contains the 2 LSB in a word. + 0x1 + + + BURST_LENGTH_2 + A SPI burst contains the 3 LSB in a word. + 0x2 + + + BURST_LENGTH_31 + A SPI burst contains all 32 bits in a word. + 0x1F + + + BURST_LENGTH_32 + A SPI burst contains the 1 LSB in first word and all 32 bits in second word. + 0x20 + + + BURST_LENGTH_33 + A SPI burst contains the 2 LSB in first word and all 32 bits in second word. + 0x21 + + + BURST_LENGTH_4094 + A SPI burst contains the 31 LSB in first word and 2^7 -1 words. + 0xFFE + + + BURST_LENGTH_4095 + A SPI burst contains 2^7 words. + 0xFFF + + + + + + + CONFIGREG + Config Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SCLK_PHA + SPI Clock/Data Phase Control + 0 + 4 + read-write + + + SCLK_PHA_0 + Phase 0 operation. + 0 + + + SCLK_PHA_1 + Phase 1 operation. + 0x1 + + + + + SCLK_POL + SPI Clock Polarity Control + 4 + 4 + read-write + + + SCLK_POL_0 + Active high polarity (0 = Idle). + 0 + + + SCLK_POL_1 + Active low polarity (1 = Idle). + 0x1 + + + + + SS_CTL + SPI SS Wave Form Select + 8 + 4 + read-write + + + SS_CTL_0 + In master mode - only one SPI burst will be transmitted. + 0 + + + SS_CTL_1 + In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be transmitted. The SPI transfer will automatically stop when the TXFIFO is empty. + 0x1 + + + + + SS_POL + SPI SS Polarity Select + 12 + 4 + read-write + + + SS_POL_0 + Active low. + 0 + + + SS_POL_1 + Active high. + 0x1 + + + + + DATA_CTL + DATA CTL + 16 + 4 + read-write + + + DATA_CTL_0 + Stay high. + 0 + + + DATA_CTL_1 + Stay low. + 0x1 + + + + + SCLK_CTL + SCLK CTL + 20 + 4 + read-write + + + SCLK_CTL_0 + Stay low. + 0 + + + SCLK_CTL_1 + Stay high. + 0x1 + + + + + HT_LENGTH + HT LENGTH + 24 + 5 + read-write + + + + + INTREG + Interrupt Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEEN + TXFIFO Empty Interrupt enable. This bit enables the TXFIFO Empty Interrupt. + 0 + 1 + read-write + + + TEEN_0 + Disable + 0 + + + TEEN_1 + Enable + 0x1 + + + + + TDREN + TXFIFO Data Request Interrupt enable + 1 + 1 + read-write + + + TDREN_0 + Disable + 0 + + + TDREN_1 + Enable + 0x1 + + + + + TFEN + TXFIFO Full Interrupt enable. This bit enables the TXFIFO Full Interrupt. + 2 + 1 + read-write + + + TFEN_0 + Disable + 0 + + + TFEN_1 + Enable + 0x1 + + + + + RREN + RXFIFO Ready Interrupt enable. This bit enables the RXFIFO Ready Interrupt. + 3 + 1 + read-write + + + RREN_0 + Disable + 0 + + + RREN_1 + Enable + 0x1 + + + + + RDREN + RXFIFO Data Request Interrupt enable + 4 + 1 + read-write + + + RDREN_0 + Disable + 0 + + + RDREN_1 + Enable + 0x1 + + + + + RFEN + RXFIFO Full Interrupt enable. This bit enables the RXFIFO Full Interrupt. + 5 + 1 + read-write + + + RFEN_0 + Disable + 0 + + + RFEN_1 + Enable + 0x1 + + + + + ROEN + RXFIFO Overflow Interrupt enable. This bit enables the RXFIFO Overflow Interrupt. + 6 + 1 + read-write + + + ROEN_0 + Disable + 0 + + + ROEN_1 + Enable + 0x1 + + + + + TCEN + Transfer Completed Interrupt enable. This bit enables the Transfer Completed Interrupt. + 7 + 1 + read-write + + + TCEN_0 + Disable + 0 + + + TCEN_1 + Enable + 0x1 + + + + + + + DMAREG + DMA Control Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_THRESHOLD + TX THRESHOLD + 0 + 6 + read-write + + + TEDEN + TXFIFO Empty DMA Request Enable. This bit enables/disables the TXFIFO Empty DMA Request. + 7 + 1 + read-write + + + TEDEN_0 + Disable + 0 + + + TEDEN_1 + Enable + 0x1 + + + + + RX_THRESHOLD + RX THRESHOLD + 16 + 6 + read-write + + + RXDEN + RXFIFO DMA Request Enable. This bit enables/disables the RXFIFO DMA Request. + 23 + 1 + read-write + + + RXDEN_0 + Disable + 0 + + + RXDEN_1 + Enable + 0x1 + + + + + RX_DMA_LENGTH + RX DMA LENGTH + 24 + 6 + read-write + + + RXTDEN + RXFIFO TAIL DMA Request/Interrupt Enable + 31 + 1 + read-write + + + RXTDEN_0 + Disable + 0 + + + RXTDEN_1 + Enable + 0x1 + + + + + + + STATREG + Status Register + 0x18 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + TE + TXFIFO Empty. This bit is set if the TXFIFO is empty. + 0 + 1 + read-only + + + TE_0 + TXFIFO contains one or more words. + 0 + + + TE_1 + TXFIFO is empty. + 0x1 + + + + + TDR + TXFIFO Data Request. + 1 + 1 + read-only + + + TDR_0 + Number of valid data slots in TXFIFO is greater than TX_THRESHOLD. + 0 + + + TDR_1 + Number of valid data slots in TXFIFO is not greater than TX_THRESHOLD. + 0x1 + + + + + TF + TXFIFO Full. This bit is set when if the TXFIFO is full. + 2 + 1 + read-only + + + TF_0 + TXFIFO is not Full. + 0 + + + TF_1 + TXFIFO is Full. + 0x1 + + + + + RR + RXFIFO Ready. This bit is set when one or more words are stored in the RXFIFO. + 3 + 1 + read-only + + + RR_0 + No valid data in RXFIFO. + 0 + + + RR_1 + More than 1 word in RXFIFO. + 0x1 + + + + + RDR + RXFIFO Data Request. + 4 + 1 + read-only + + + RDR_0 + When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + 0 + + + RDR_1 + When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists. + 0x1 + + + + + RF + RXFIFO Full. This bit is set when the RXFIFO is full. + 5 + 1 + read-only + + + RF_0 + Not Full. + 0 + + + RF_1 + Full. + 0x1 + + + + + RO + RXFIFO Overflow + 6 + 1 + read-write + oneToClear + + + RO_0 + RXFIFO has no overflow. + 0 + + + RO_1 + RXFIFO has overflowed. + 0x1 + + + + + TC + Transfer Completed Status bit + 7 + 1 + read-write + oneToClear + + + TC_0 + Transfer in progress. + 0 + + + TC_1 + Transfer completed. + 0x1 + + + + + + + PERIODREG + Sample Period Control Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE_PERIOD + Sample Period Control + 0 + 15 + read-write + + + SAMPLE_PERIOD_0 + 0 wait states inserted + 0 + + + SAMPLE_PERIOD_1 + 1 wait state inserted + 0x1 + + + SAMPLE_PERIOD_32766 + 32766 wait states inserted + 0x7FFE + + + SAMPLE_PERIOD_32767 + 32767 wait states inserted + 0x7FFF + + + + + CSRC + Clock Source Control. This bit selects the clock source for the sample period counter. + 15 + 1 + read-write + + + CSRC_0 + SPI Clock (SCLK) + 0 + + + CSRC_1 + Low-Frequency Reference Clock (32.768 KHz) + 0x1 + + + + + CSD_CTL + Chip Select Delay Control bits + 16 + 6 + read-write + + + + + TESTREG + Test Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCNT + TXFIFO Counter. This field indicates the number of words in the TXFIFO. + 0 + 7 + read-write + + + RXCNT + RXFIFO Counter. This field indicates the number of words in the RXFIFO. + 8 + 7 + read-write + + + LBC + Loop Back Control + 31 + 1 + read-write + + + LBC_0 + Not connected. + 0 + + + LBC_1 + Transmitter and receiver sections internally connected for Loopback. + 0x1 + + + + + + + MSGDATA + Message Data Register + 0x40 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_MSGDATA + ECSPI_MSGDATA holds the top word of MSG Data FIFO + 0 + 32 + write-only + + + + + + + ECSPI2 + ECSPI + ECSPI + ECSPI2_ + 0x30830000 + + 0 + 0x44 + registers + + + ECSPI2 + 32 + + + + ECSPI3 + ECSPI + ECSPI + ECSPI3_ + 0x30840000 + + 0 + 0x44 + registers + + + ECSPI3 + 33 + + + + UART1 + UARTv2 + UART + UART1_ + UART + 0x30860000 + + 0 + 0xBC + registers + + + UART1 + 26 + + + + URXD + UART Receiver Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RX_DATA + Received Data + 0 + 8 + read-only + + + PRERR + In RS-485 mode, it holds the ninth data bit (bit [8]) of received 9-bit RS-485 data In RS232/IrDA mode, it is the Parity Error flag + 10 + 1 + read-only + + + PRERR_0 + = No parity error was detected for data in the RX_DATA field + 0 + + + PRERR_1 + = A parity error was detected for data in the RX_DATA field + 0x1 + + + + + BRK + BREAK Detect + 11 + 1 + read-only + + + BRK_0 + The current character is not a BREAK character + 0 + + + BRK_1 + The current character is a BREAK character + 0x1 + + + + + FRMERR + Frame Error + 12 + 1 + read-only + + + FRMERR_0 + The current character has no framing error + 0 + + + FRMERR_1 + The current character has a framing error + 0x1 + + + + + OVRRUN + Receiver Overrun + 13 + 1 + read-only + + + OVRRUN_0 + No RxFIFO overrun was detected + 0 + + + OVRRUN_1 + A RxFIFO overrun was detected + 0x1 + + + + + ERR + Error Detect + 14 + 1 + read-only + + + ERR_0 + No error status was detected + 0 + + + ERR_1 + An error status was detected + 0x1 + + + + + CHARRDY + Character Ready + 15 + 1 + read-only + + + CHARRDY_0 + Character in RX_DATA field and associated flags are invalid. + 0 + + + CHARRDY_1 + Character in RX_DATA field and associated flags valid and ready for reading. + 0x1 + + + + + + + UTXD + UART Transmitter Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_DATA + Transmit Data + 0 + 8 + write-only + + + + + UCR1 + UART Control Register 1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + UARTEN + UART Enable + 0 + 1 + read-write + + + UARTEN_0 + Disable the UART + 0 + + + UARTEN_1 + Enable the UART + 0x1 + + + + + DOZE + DOZE + 1 + 1 + read-write + + + DOZE_0 + The UART is enabled when in DOZE state + 0 + + + DOZE_1 + The UART is disabled when in DOZE state + 0x1 + + + + + ATDMAEN + Aging DMA Timer Enable + 2 + 1 + read-write + + + ATDMAEN_0 + Disable AGTIM DMA request + 0 + + + ATDMAEN_1 + Enable AGTIM DMA request + 0x1 + + + + + TXDMAEN + Transmitter Ready DMA Enable + 3 + 1 + read-write + + + TXDMAEN_0 + Disable transmit DMA request + 0 + + + TXDMAEN_1 + Enable transmit DMA request + 0x1 + + + + + SNDBRK + Send BREAK + 4 + 1 + read-write + + + SNDBRK_0 + Do not send a BREAK character + 0 + + + SNDBRK_1 + Send a BREAK character (continuous 0s) + 0x1 + + + + + RTSDEN + RTS Delta Interrupt Enable + 5 + 1 + read-write + + + RTSDEN_0 + Disable RTSD interrupt + 0 + + + RTSDEN_1 + Enable RTSD interrupt + 0x1 + + + + + TXMPTYEN + Transmitter Empty Interrupt Enable + 6 + 1 + read-write + + + TXMPTYEN_0 + Disable the transmitter FIFO empty interrupt + 0 + + + TXMPTYEN_1 + Enable the transmitter FIFO empty interrupt + 0x1 + + + + + IREN + Infrared Interface Enable + 7 + 1 + read-write + + + IREN_0 + Disable the IR interface + 0 + + + IREN_1 + Enable the IR interface + 0x1 + + + + + RXDMAEN + Receive Ready DMA Enable + 8 + 1 + read-write + + + RXDMAEN_0 + Disable DMA request + 0 + + + RXDMAEN_1 + Enable DMA request + 0x1 + + + + + RRDYEN + Receiver Ready Interrupt Enable + 9 + 1 + read-write + + + RRDYEN_0 + Disables the RRDY interrupt + 0 + + + RRDYEN_1 + Enables the RRDY interrupt + 0x1 + + + + + ICD + Idle Condition Detect + 10 + 2 + read-write + + + ICD_0 + Idle for more than 4 frames + 0 + + + ICD_1 + Idle for more than 8 frames + 0x1 + + + ICD_2 + Idle for more than 16 frames + 0x2 + + + ICD_3 + Idle for more than 32 frames + 0x3 + + + + + IDEN + Idle Condition Detected Interrupt Enable + 12 + 1 + read-write + + + IDEN_0 + Disable the IDLE interrupt + 0 + + + IDEN_1 + Enable the IDLE interrupt + 0x1 + + + + + TRDYEN + Transmitter Ready Interrupt Enable + 13 + 1 + read-write + + + TRDYEN_0 + Disable the transmitter ready interrupt + 0 + + + TRDYEN_1 + Enable the transmitter ready interrupt + 0x1 + + + + + ADBR + Automatic Detection of Baud Rate + 14 + 1 + read-write + + + ADBR_0 + Disable automatic detection of baud rate + 0 + + + ADBR_1 + Enable automatic detection of baud rate + 0x1 + + + + + ADEN + Automatic Baud Rate Detection Interrupt Enable + 15 + 1 + read-write + + + ADEN_0 + Disable the automatic baud rate detection interrupt + 0 + + + ADEN_1 + Enable the automatic baud rate detection interrupt + 0x1 + + + + + + + UCR2 + UART Control Register 2 + 0x84 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + SRST + Software Reset + 0 + 1 + read-write + + + SRST_0 + Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3]. + 0 + + + SRST_1 + No reset + 0x1 + + + + + RXEN + Receiver Enable + 1 + 1 + read-write + + + RXEN_0 + Disable the receiver + 0 + + + RXEN_1 + Enable the receiver + 0x1 + + + + + TXEN + Transmitter Enable + 2 + 1 + read-write + + + TXEN_0 + Disable the transmitter + 0 + + + TXEN_1 + Enable the transmitter + 0x1 + + + + + ATEN + Aging Timer Enable. This bit is used to enable the aging timer interrupt (triggered with AGTIM) + 3 + 1 + read-write + + + ATEN_0 + AGTIM interrupt disabled + 0 + + + ATEN_1 + AGTIM interrupt enabled + 0x1 + + + + + RTSEN + Request to Send Interrupt Enable + 4 + 1 + read-write + + + RTSEN_0 + Disable request to send interrupt + 0 + + + RTSEN_1 + Enable request to send interrupt + 0x1 + + + + + WS + Word Size + 5 + 1 + read-write + + + WS_0 + 7-bit transmit and receive character length (not including START, STOP or PARITY bits) + 0 + + + WS_1 + 8-bit transmit and receive character length (not including START, STOP or PARITY bits) + 0x1 + + + + + STPB + Stop + 6 + 1 + read-write + + + STPB_0 + The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits. + 0 + + + STPB_1 + The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits. + 0x1 + + + + + PROE + Parity Odd/Even + 7 + 1 + read-write + + + PROE_0 + Even parity + 0 + + + PROE_1 + Odd parity + 0x1 + + + + + PREN + Parity Enable + 8 + 1 + read-write + + + PREN_0 + Disable parity generator and checker + 0 + + + PREN_1 + Enable parity generator and checker + 0x1 + + + + + RTEC + Request to Send Edge Control + 9 + 2 + read-write + + + RTEC_0 + Trigger interrupt on a rising edge + 0 + + + RTEC_1 + Trigger interrupt on a falling edge + 0x1 + + + RTEC_2 + Trigger interrupt on any edge + #1x + + + + + ESCEN + Escape Enable. Enables/Disables the escape sequence detection logic. + 11 + 1 + read-write + + + ESCEN_0 + Disable escape sequence detection + 0 + + + ESCEN_1 + Enable escape sequence detection + 0x1 + + + + + CTS + Clear to Send + 12 + 1 + read-write + + + CTS_0 + The CTS_B pin is high (inactive) + 0 + + + CTS_1 + The CTS_B pin is low (active) + 0x1 + + + + + CTSC + CTS Pin Control + 13 + 1 + read-write + + + CTSC_0 + The CTS_B pin is controlled by the CTS bit + 0 + + + CTSC_1 + The CTS_B pin is controlled by the receiver + 0x1 + + + + + IRTS + Ignore RTS Pin + 14 + 1 + read-write + + + IRTS_0 + Transmit only when the RTS pin is asserted + 0 + + + IRTS_1 + Ignore the RTS pin + 0x1 + + + + + ESCI + Escape Sequence Interrupt Enable. Enables/Disables the ESCF bit to generate an interrupt. + 15 + 1 + read-write + + + ESCI_0 + Disable the escape sequence interrupt + 0 + + + ESCI_1 + Enable the escape sequence interrupt + 0x1 + + + + + + + UCR3 + UART Control Register 3 + 0x88 + 32 + read-write + 0x700 + 0xFFFFFFFF + + + ACIEN + Autobaud Counter Interrupt Enable + 0 + 1 + read-write + + + ACIEN_0 + ACST interrupt disabled + 0 + + + ACIEN_1 + ACST interrupt enabled + 0x1 + + + + + INVT + Invert TXD output in RS-232/RS-485 mode, set TXD active level in IrDA mode + 1 + 1 + read-write + + + INVT_0 + TXD is not inverted + 0 + + + INVT_1 + TXD is inverted + 0x1 + + + + + RXDMUXSEL + RXD Muxed Input Selected + 2 + 1 + read-write + + + DTRDEN + This bit is not used in this chip. + 3 + 1 + read-write + + + AWAKEN + Asynchronous WAKE Interrupt Enable + 4 + 1 + read-write + + + AWAKEN_0 + Disable the AWAKE interrupt + 0 + + + AWAKEN_1 + Enable the AWAKE interrupt + 0x1 + + + + + AIRINTEN + Asynchronous IR WAKE Interrupt Enable + 5 + 1 + read-write + + + AIRINTEN_0 + Disable the AIRINT interrupt + 0 + + + AIRINTEN_1 + Enable the AIRINT interrupt + 0x1 + + + + + RXDSEN + Receive Status Interrupt Enable + 6 + 1 + read-write + + + RXDSEN_0 + Disable the RXDS interrupt + 0 + + + RXDSEN_1 + Enable the RXDS interrupt + 0x1 + + + + + ADNIMP + Autobaud Detection Not Improved- + 7 + 1 + read-write + + + ADNIMP_0 + Autobaud detection new features selected + 0 + + + ADNIMP_1 + Keep old autobaud detection mechanism + 0x1 + + + + + RI + This bit is not used in this chip. + 8 + 1 + read-write + + + DCD + This bit is not used in this chip. + 9 + 1 + read-write + + + DSR + This bit is not used in this chip. + 10 + 1 + read-write + + + FRAERREN + Frame Error Interrupt Enable + 11 + 1 + read-write + + + FRAERREN_0 + Disable the frame error interrupt + 0 + + + FRAERREN_1 + Enable the frame error interrupt + 0x1 + + + + + PARERREN + Parity Error Interrupt Enable + 12 + 1 + read-write + + + PARERREN_0 + Disable the parity error interrupt + 0 + + + PARERREN_1 + Enable the parity error interrupt + 0x1 + + + + + DTREN + This bit is not used in this chip. + 13 + 1 + read-write + + + DPEC + This bit is not used in this chip. + 14 + 2 + read-write + + + + + UCR4 + UART Control Register 4 + 0x8C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DREN + Receive Data Ready Interrupt Enable. Enables/Disables the RDR bit to generate an interrupt. + 0 + 1 + read-write + + + DREN_0 + Disable RDR interrupt + 0 + + + DREN_1 + Enable RDR interrupt + 0x1 + + + + + OREN + Receiver Overrun Interrupt Enable. Enables/Disables the ORE bit to generate an interrupt. + 1 + 1 + read-write + + + OREN_0 + Disable ORE interrupt + 0 + + + OREN_1 + Enable ORE interrupt + 0x1 + + + + + BKEN + BREAK Condition Detected Interrupt Enable. Enables/Disables the BRCD bit to generate an interrupt. + 2 + 1 + read-write + + + BKEN_0 + Disable the BRCD interrupt + 0 + + + BKEN_1 + Enable the BRCD interrupt + 0x1 + + + + + TCEN + Transmit Complete Interrupt Enable + 3 + 1 + read-write + + + TCEN_0 + Disable TXDC interrupt + 0 + + + TCEN_1 + Enable TXDC interrupt + 0x1 + + + + + LPBYP + Low Power Bypass. Allows to bypass the low power new features in UART. To use during debug phase. + 4 + 1 + read-write + + + LPBYP_0 + Low power features enabled + 0 + + + LPBYP_1 + Low power features disabled + 0x1 + + + + + IRSC + IR Special Case + 5 + 1 + read-write + + + IRSC_0 + The vote logic uses the sampling clock (16x baud rate) for normal operation + 0 + + + IRSC_1 + The vote logic uses the UART reference clock + 0x1 + + + + + IDDMAEN + DMA IDLE Condition Detected Interrupt Enable Enables/Disables the receive DMA request dma_req_rx for the IDLE interrupt (triggered with IDLE flag in USR2[12]) + 6 + 1 + read-write + + + IDDMAEN_0 + DMA IDLE interrupt disabled + 0 + + + IDDMAEN_1 + DMA IDLE interrupt enabled + 0x1 + + + + + WKEN + WAKE Interrupt Enable + 7 + 1 + read-write + + + WKEN_0 + Disable the WAKE interrupt + 0 + + + WKEN_1 + Enable the WAKE interrupt + 0x1 + + + + + ENIRI + Serial Infrared Interrupt Enable. Enables/Disables the serial infrared interrupt. + 8 + 1 + read-write + + + ENIRI_0 + Serial infrared Interrupt disabled + 0 + + + ENIRI_1 + Serial infrared Interrupt enabled + 0x1 + + + + + INVR + Invert RXD input in RS-232/RS-485 Mode, determine RXD input logic level being sampled in In IrDA mode + 9 + 1 + read-write + + + INVR_0 + RXD input is not inverted + 0 + + + INVR_1 + RXD input is inverted + 0x1 + + + + + CTSTL + CTS Trigger Level + 10 + 6 + read-write + + + CTSTL_0 + 0 characters received + 0 + + + CTSTL_1 + 1 characters in the RxFIFO + 0x1 + + + CTSTL_32 + 32 characters in the RxFIFO (maximum) + 0x20 + + + + + + + UFCR + UART FIFO Control Register + 0x90 + 32 + read-write + 0x801 + 0xFFFFFFFF + + + RXTL + Receiver Trigger Level + 0 + 6 + read-write + + + RXTL_0 + 0 characters received + 0 + + + RXTL_1 + RxFIFO has 1 character + 0x1 + + + RXTL_31 + RxFIFO has 31 characters + 0x1F + + + RXTL_32 + RxFIFO has 32 characters (maximum) + 0x20 + + + + + DCEDTE + DCE/DTE mode select + 6 + 1 + read-write + + + DCEDTE_0 + DCE mode selected + 0 + + + DCEDTE_1 + DTE mode selected + 0x1 + + + + + RFDIV + Reference Frequency Divider + 7 + 3 + read-write + + + RFDIV_0 + Divide input clock by 6 + 0 + + + RFDIV_1 + Divide input clock by 5 + 0x1 + + + RFDIV_2 + Divide input clock by 4 + 0x2 + + + RFDIV_3 + Divide input clock by 3 + 0x3 + + + RFDIV_4 + Divide input clock by 2 + 0x4 + + + RFDIV_5 + Divide input clock by 1 + 0x5 + + + RFDIV_6 + Divide input clock by 7 + 0x6 + + + + + TXTL + Transmitter Trigger Level + 10 + 6 + read-write + + + TXTL_2 + TxFIFO has 2 or fewer characters + 0x2 + + + TXTL_31 + TxFIFO has 31 or fewer characters + 0x1F + + + TXTL_32 + TxFIFO has 32 characters (maximum) + 0x20 + + + + + + + USR1 + UART Status Register 1 + 0x94 + 32 + read-write + 0x2040 + 0xFFFFFFFF + + + SAD + RS-485 Slave Address Detected Interrupt Flag + 3 + 1 + read-write + oneToClear + + + SAD_0 + No slave address detected + 0 + + + SAD_1 + Slave address detected + 0x1 + + + + + AWAKE + Asynchronous WAKE Interrupt Flag + 4 + 1 + read-write + oneToClear + + + AWAKE_0 + No falling edge was detected on the RXD Serial pin + 0 + + + AWAKE_1 + A falling edge was detected on the RXD Serial pin + 0x1 + + + + + AIRINT + Asynchronous IR WAKE Interrupt Flag + 5 + 1 + read-write + oneToClear + + + AIRINT_0 + No pulse was detected on the RXD IrDA pin + 0 + + + AIRINT_1 + A pulse was detected on the RXD IrDA pin + 0x1 + + + + + RXDS + Receiver IDLE Interrupt Flag + 6 + 1 + read-only + + + RXDS_0 + Receive in progress + 0 + + + RXDS_1 + Receiver is IDLE + 0x1 + + + + + DTRD + This bit is not used in this chip. + 7 + 1 + read-write + oneToClear + + + AGTIM + Ageing Timer Interrupt Flag + 8 + 1 + read-write + oneToClear + + + AGTIM_0 + AGTIM is not active + 0 + + + AGTIM_1 + AGTIM is active (write 1 to clear) + 0x1 + + + + + RRDY + Receiver Ready Interrupt / DMA Flag + 9 + 1 + read-only + + + RRDY_0 + No character ready + 0 + + + RRDY_1 + Character(s) ready (interrupt posted) + 0x1 + + + + + FRAMERR + Frame Error Interrupt Flag + 10 + 1 + read-write + oneToClear + + + FRAMERR_0 + No frame error detected + 0 + + + FRAMERR_1 + Frame error detected (write 1 to clear) + 0x1 + + + + + ESCF + Escape Sequence Interrupt Flag + 11 + 1 + read-write + oneToClear + + + ESCF_0 + No escape sequence detected + 0 + + + ESCF_1 + Escape sequence detected (write 1 to clear). + 0x1 + + + + + RTSD + RTS Delta + 12 + 1 + read-write + oneToClear + + + RTSD_0 + RTS_B pin did not change state since last cleared + 0 + + + RTSD_1 + RTS_B pin changed state (write 1 to clear) + 0x1 + + + + + TRDY + Transmitter Ready Interrupt / DMA Flag + 13 + 1 + read-only + + + TRDY_0 + The transmitter does not require data + 0 + + + TRDY_1 + The transmitter requires data (interrupt posted) + 0x1 + + + + + RTSS + RTS_B Pin Status + 14 + 1 + read-only + + + RTSS_0 + The RTS_B module input is high (inactive) + 0 + + + RTSS_1 + The RTS_B module input is low (active) + 0x1 + + + + + PARITYERR + Parity Error Interrupt Flag + 15 + 1 + read-write + oneToClear + + + PARITYERR_0 + No parity error detected + 0 + + + PARITYERR_1 + Parity error detected (write 1 to clear) + 0x1 + + + + + + + USR2 + UART Status Register 2 + 0x98 + 32 + read-write + 0x4028 + 0xFFFFFFFF + + + RDR + Receive Data Ready-Indicates that at least 1 character is received and written to the RxFIFO + 0 + 1 + read-only + + + RDR_0 + No receive data ready + 0 + + + RDR_1 + Receive data ready + 0x1 + + + + + ORE + Overrun Error + 1 + 1 + read-write + oneToClear + + + ORE_0 + No overrun error + 0 + + + ORE_1 + Overrun error (write 1 to clear) + 0x1 + + + + + BRCD + BREAK Condition Detected + 2 + 1 + read-write + oneToClear + + + BRCD_0 + No BREAK condition was detected + 0 + + + BRCD_1 + A BREAK condition was detected (write 1 to clear) + 0x1 + + + + + TXDC + Transmitter Complete + 3 + 1 + read-only + + + TXDC_0 + Transmit is incomplete + 0 + + + TXDC_1 + Transmit is complete + 0x1 + + + + + RTSF + RTS Edge Triggered Interrupt Flag + 4 + 1 + read-write + oneToClear + + + RTSF_0 + Programmed edge not detected on RTS_B + 0 + + + RTSF_1 + Programmed edge detected on RTS_B (write 1 to clear) + 0x1 + + + + + DCDIN + This bit is not used in this chip. + 5 + 1 + read-only + + + DCDDELT + This bit is not used in this chip. + 6 + 1 + read-write + oneToClear + + + WAKE + Wake + 7 + 1 + read-write + oneToClear + + + WAKE_0 + start bit not detected + 0 + + + WAKE_1 + start bit detected (write 1 to clear) + 0x1 + + + + + IRINT + Serial Infrared Interrupt Flag + 8 + 1 + read-write + oneToClear + + + IRINT_0 + no edge detected + 0 + + + IRINT_1 + valid edge detected (write 1 to clear) + 0x1 + + + + + RIIN + This bit is not used in this chip. + 9 + 1 + read-only + + + RIDELT + This bit is not used in this chip. + 10 + 1 + read-write + oneToClear + + + ACST + Autobaud Counter Stopped + 11 + 1 + read-write + oneToClear + + + ACST_0 + Measurement of bit length not finished (in autobaud) + 0 + + + ACST_1 + Measurement of bit length finished (in autobaud). (write 1 to clear) + 0x1 + + + + + IDLE + Idle Condition + 12 + 1 + read-write + oneToClear + + + IDLE_0 + No idle condition detected + 0 + + + IDLE_1 + Idle condition detected (write 1 to clear) + 0x1 + + + + + DTRF + This bit is not used in this chip. + 13 + 1 + read-write + oneToClear + + + TXFE + Transmit Buffer FIFO Empty + 14 + 1 + read-only + + + TXFE_0 + The transmit buffer (TxFIFO) is not empty + 0 + + + TXFE_1 + The transmit buffer (TxFIFO) is empty + 0x1 + + + + + ADET + Automatic Baud Rate Detect Complete + 15 + 1 + read-write + oneToClear + + + ADET_0 + ASCII "A" or "a" was not received + 0 + + + ADET_1 + ASCII "A" or "a" was received (write 1 to clear) + 0x1 + + + + + + + UESC + UART Escape Character Register + 0x9C + 32 + read-write + 0x2B + 0xFFFFFFFF + + + ESC_CHAR + UART Escape Character + 0 + 8 + read-write + + + + + UTIM + UART Escape Timer Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIM + UART Escape Timer + 0 + 12 + read-write + + + + + UBIR + UART BRM Incremental Register + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + Incremental Numerator + 0 + 16 + read-write + + + + + UBMR + UART BRM Modulator Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MOD + Modulator Denominator + 0 + 16 + read-write + + + + + UBRC + UART Baud Rate Count Register + 0xAC + 32 + read-only + 0x4 + 0xFFFFFFFF + + + BCNT + Baud Rate Count Register + 0 + 16 + read-only + + + + + ONEMS + UART One Millisecond Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ONEMS + One Millisecond Register + 0 + 24 + read-write + + + + + UTS + UART Test Register + 0xB4 + 32 + read-write + 0x60 + 0xFFFFFFFF + + + SOFTRST + Software Reset. Indicates the status of the software reset (SRST_B bit of UCR2). + 0 + 1 + read-write + + + SOFTRST_0 + Software reset inactive + 0 + + + SOFTRST_1 + Software reset active + 0x1 + + + + + RXFULL + RxFIFO FULL. Indicates the RxFIFO is full. + 3 + 1 + read-write + + + RXFULL_0 + The RxFIFO is not full + 0 + + + RXFULL_1 + The RxFIFO is full + 0x1 + + + + + TXFULL + TxFIFO FULL. Indicates the TxFIFO is full. + 4 + 1 + read-write + + + TXFULL_0 + The TxFIFO is not full + 0 + + + TXFULL_1 + The TxFIFO is full + 0x1 + + + + + RXEMPTY + RxFIFO Empty. Indicates the RxFIFO is empty. + 5 + 1 + read-write + + + RXEMPTY_0 + The RxFIFO is not empty + 0 + + + RXEMPTY_1 + The RxFIFO is empty + 0x1 + + + + + TXEMPTY + TxFIFO Empty. Indicates that the TxFIFO is empty. + 6 + 1 + read-write + + + TXEMPTY_0 + The TxFIFO is not empty + 0 + + + TXEMPTY_1 + The TxFIFO is empty + 0x1 + + + + + RXDBG + This bit is not used in this chip + 9 + 1 + read-write + + + RXDBG_0 + rx fifo read pointer does not increment + 0 + + + RXDBG_1 + rx_fifo read pointer increments as normal + 0x1 + + + + + LOOPIR + Loop TX and RX for IR Test (LOOPIR) + 10 + 1 + read-write + + + LOOPIR_0 + No IR loop + 0 + + + LOOPIR_1 + Connect IR transmitter to IR receiver + 0x1 + + + + + DBGEN + This bit is not used in this chip + 11 + 1 + read-write + + + DBGEN_0 + UART will go into debug mode when debug_req is HIGH + 0 + + + DBGEN_1 + UART will not go into debug mode even if debug_req is HIGH + 0x1 + + + + + LOOP + Loop TX and RX for Test + 12 + 1 + read-write + + + LOOP_0 + Normal receiver operation + 0 + + + LOOP_1 + Internally connect the transmitter output to the receiver input + 0x1 + + + + + FRCPERR + Force Parity Error + 13 + 1 + read-write + + + FRCPERR_0 + Generate normal parity + 0 + + + FRCPERR_1 + Generate inverted parity (error) + 0x1 + + + + + + + UMCR + UART RS-485 Mode Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MDEN + 9-bit data or Multidrop Mode (RS-485) Enable. + 0 + 1 + read-write + + + MDEN_0 + Normal RS-232 or IrDA mode, see for detail. + 0 + + + MDEN_1 + Enable RS-485 mode, see for detail + 0x1 + + + + + SLAM + RS-485 Slave Address Detect Mode Selection. + 1 + 1 + read-write + + + SLAM_0 + Select Normal Address Detect mode + 0 + + + SLAM_1 + Select Automatic Address Detect mode + 0x1 + + + + + TXB8 + Transmit RS-485 bit 8 (the ninth bit or 9th bit) + 2 + 1 + read-write + + + TXB8_0 + 0 will be transmitted as the RS485 9th data bit + 0 + + + TXB8_1 + 1 will be transmitted as the RS485 9th data bit + 0x1 + + + + + SADEN + RS-485 Slave Address Detected Interrupt Enable. + 3 + 1 + read-write + + + SADEN_0 + Disable RS-485 Slave Address Detected Interrupt + 0 + + + SADEN_1 + Enable RS-485 Slave Address Detected Interrupt + 0x1 + + + + + SLADDR + RS-485 Slave Address Character + 8 + 8 + read-write + + + + + + + UART3 + UARTv2 + UART + UART3_ + 0x30880000 + + 0 + 0xBC + registers + + + UART3 + 28 + + + + UART2 + UARTv2 + UART + UART2_ + 0x30890000 + + 0 + 0xBC + registers + + + UART2 + 27 + + + + UART4 + UARTv2 + UART + UART4_ + 0x30A60000 + + 0 + 0xBC + registers + + + UART4 + 29 + + + + SPBA1 + Temperature Monitor + SPBA + SPBA1_ + SPBA + 0x308F0000 + + 0 + 0x80 + registers + + + + 32 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 + PRR%s + Peripheral Rights Register + 0 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + RARA + Resource Access Right + 0 + 1 + read-write + + + PROHIBITED + Access to peripheral is not allowed. + 0 + + + ALLOWED + Access to peripheral is granted. + 0x1 + + + + + RARB + Resource Access Right + 1 + 1 + read-write + + + PROHIBITED + Access to peripheral is not allowed. + 0 + + + ALLOWED + Access to peripheral is granted. + 0x1 + + + + + RARC + Resource Access Right + 2 + 1 + read-write + + + PROHIBITED + Access to peripheral is not allowed. + 0 + + + ALLOWED + Access to peripheral is granted. + 0x1 + + + + + ROI + Resource Owner ID + 16 + 2 + read-only + + + UNOWNED + Unowned resource. + 0 + + + MASTER_A + The resource is owned by master A port. + 0x1 + + + MASTER_B + The resource is owned by master B port. + 0x2 + + + MASTER_C + The resource is owned by master C port. + 0x3 + + + + + RMO + Requesting Master Owner + 30 + 2 + read-only + + + UNOWNED + The resource is unowned. + 0 + + + ANOTHER_MASTER + The resource is owned by another master. + 0x2 + + + REQUESTING_MASTER + The resource is owned by the requesting master. + 0x3 + + + + + + + + + SPBA2 + Temperature Monitor + SPBA + SPBA2_ + 0x300F0000 + + 0 + 0x80 + registers + + + + MIPI_DSI_HOST + MIPI DSI HOST + MIPI_DSI_HOST + MIPI_DSI_HOST_ + 0x30A10000 + + 0 + 0x34 + registers + + + MIPI_DSI + 34 + + + + DSI_HOST_CFG_NUM_LANES + no description available + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_num_lanes + Sets the number of active lanes that are to be used for transmitting data. 2'b00 - 1 Lane 2'b01 - 2 Lanes 2'b10 - 3 Lanes 2'b11 - 4 Lanes + 0 + 2 + read-write + + + + + DSI_HOST_CFG_NONCONTINUOUS_CLK + no description available + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_noncontinuous_clk + Sets the Host Controller into non-continuous MIPI clock mode. When in non-continuous clock mode, the high speed clock will transistion into low power mode between transmissions. 1'b0 - Continuous high speed clock 1'b1 - Non-Continuous high speed clock + 0 + 1 + read-write + + + + + DSI_HOST_CFG_T_PRE + no description available + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_t_pre + Sets the number of byte clock periods ('clk_byte' input) that the controller will wait after enabling the clock lane for HS operation before enabling the data lanes for HS operation. This setting represents the TCLK-PRE parameter. The minimum value for this port is 1. + 0 + 7 + read-write + + + + + DSI_HOST_CFG_T_POST + no description available + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_t_post + Sets the number of byte clock periods ('clk_byte' input) to wait before putting the clock lane into LP mode after the data lanes have been detected to be in Stop State. This setting represents the DPHY timing parameters TLPX (TxClkEsc) + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE requirement for the clock lane before the data lane is allowed to change from LP11 to start a high speed transmission. The minimum value for this port is 1. + 0 + 7 + read-write + + + + + DSI_HOST_CFG_TX_GAP + no description available + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_tx_gap + Sets the number of byte clock periods ('clk_byte' input) that the controller will wait after the clock lane has been put into LP mode before enabling the clock lane for HS mode again. This setting represents the THS-EXIT parameter. The minimum value for this port is 1. + 0 + 7 + read-write + + + + + DSI_HOST_CFG_AUTOINSERT_EOTP + no description available + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_autoinsert_eotp + Enables the Host Controller to automatically insert an EoTp short packet when switching from HS to LP mode. 1'b0 - EoTp is not automatically inserted 1'b1 - EoTp is automatically inserted + 0 + 1 + read-write + + + + + DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP + no description available + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_extra_cmds_after_eotp + Configures the DSI Host Controller to send extra End Of Transmission Packets after the end of a packet. The value is the number of extra EOTP packets sent. + 0 + 8 + read-write + + + + + DSI_HOST_CFG_HTX_TO_COUNT + no description available + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_htx_to_count + Sets the value of the DSI Host High Speed TX timeout count in clk_byte clock periods that once reached will initiate a timeout error and follow the recovery procedure documented in the DSI specification. This timeout parameter should be configured to represent the time taken to transmit the biggest HS data payload. If this timeout is reached the DSI byte count is cleared and the HS transmission is aborted. This timer can be also disabled, when set to 0. + 0 + 24 + read-write + + + + + DSI_HOST_CFG_LRX_H_TO_COUNT + no description available + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_lrx_h_to_count + Sets the value of the DSI Host low power RX timeout count in clk_byte clock periods that once reached will initiate a timeout error and follow the recovery procedure documented in the DSI specification. This timeout parameter should be configured to represent the time taken to receive the biggest LP (Escape mode) data payload. If this timeout is reached, the DSI byte count is cleared and the LP reception is aborted. This timer can be also disabled, when set to 0 + 0 + 24 + read-write + + + + + DSI_HOST_CFG_BTA_H_TO_COUNT + no description available + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_bta_h_to_count + Sets the value of the DSI Host Bus Turn Around (BTA) timeout in clk_byte clock periods that once reached will initiate a timeout error. + 0 + 24 + read-write + + + + + DSI_HOST_CFG_TWAKEUP + no description available + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_twakeup + DPHY Twakeup timing parameter. Sets the number of clk_esc clock periods to keep a clock or data lane in Mark-1 state after exiting ULPS. The MIPI DPHY spec requires a minimum of 1ms in Mark-1 state after leaving ULPS. + 0 + 19 + read-write + + + + + DSI_HOST_CFG_STATUS_OUT + no description available + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + SOT_ERROR + SoT Error - Start of Transmission (SoT) Error from peripheral error report, cleared upon read. + 0 + 1 + read-only + + + SOT_SYNC_ERROR + SoT Sync Error - Start of Transmission (SoT) Sync Error from peripheral error report, cleared upon read + 1 + 1 + read-only + + + EOT_SYNC_ERROR + EoT Sync Error - End of Transmission (EoT) Sync Error from peripheral error report, cleared upon read + 2 + 1 + read-only + + + ESCAPE_MODE_ENTRY_CMD_ERROR + Escape Mode Entry Command Error - Escape Mode Entry Command Error from peripheral error report, cleared upon read + 3 + 1 + read-only + + + LP_TX_SYNC_ERROR + Low-Power Transmit Sync Error - Low Power Transmit Sync error from peripheral error report, cleared upon read + 4 + 1 + read-only + + + PERIPH_TIMEOUT_ERROR + Peripheral Timeout Error - Peripheral Timeout error from peripheral error report, cleared upon read + 5 + 1 + read-only + + + FALSE_CONTROL_ERROR + False Control Error - False Control Error from peripheral error report, cleared upon read + 6 + 1 + read-only + + + CONTENTION_DETECT + Contention Detected - Contention Detection from peripheral error report, cleared upon read + 7 + 1 + read-only + + + ECC_ERROR_SINGLE_BIT + ECC single bit error from peripheral error report, cleared upon read. + 8 + 1 + read-only + + + ECC_ERROR_MULTI_BIT + ECC Error, multi-bit (detected, not corrected) - ECC multi-bit error from peripheral error report, cleared upon read + 9 + 1 + read-only + + + CHECKSUM_ERROR + Checksum Error (long packet only) - Checksum error from peripheral error report, cleared upon read + 10 + 1 + read-only + + + + + DSI_HOST_RX_ERROR_STATUS + no description available + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + dsi_host_rx_error_status + Status Register for Host receive error detection, ECC errors, CRC errors and for timeout indicators [0] ECC single bit error detected [1] ECC multi bit error detected [6:2] Errored bit position for single bit ECC error [7] CRC error detected [8] High Speed forward TX timeout detected [9] Reverse Low power data receive timeout detected [10] BTA timeout detected + 0 + 11 + read-only + + + + + + + MIPI_DSI_HOST_DPI_INTFC + MIPI DSI HOST DPI INTFC + MIPI_DSI_HOST_DPI_INTFC + MIPI_DSI_HOST_DPI_INTFC_ + 0x30A10200 + + 0 + 0x44 + registers + + + + DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE + no description available + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_pixel_payload_size + Maximum number of pixels that should be sent as one DSI packet. Recommended that the line size (in pixels) is evenly divisible by this parameter (packet payload size in pixels). + 0 + 16 + read-write + + + + + DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL + no description available + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_pixel_fifo_send_level + In order to optimize DSI utility, the DPI bridge buffers a cerntain number of DPI pixels before initiating a DSI packet. This configuration port controls the level at which the DPI Host bridge begins sending pixels. + 0 + 16 + read-write + + + + + DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING + no description available + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_interface_color_coding + Sets the distribution of RGB bits within the 24-bit d bus, as specified by the DPI specification. 0= 16-bit Configuration 1 1= 16-bit Configuration 2 2= 16-bit Configuration 3 3= 18-bit Configuration 1 4= 18-bit Configuration 2 5= 24-bit + 0 + 3 + read-write + + + + + DSI_HOST_CFG_DPI_PIXEL_FORMAT + no description available + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_pixel_format + Sets the DSI packet type of the pixels. 0 - 16 bit 1 - 18 bit 2 - 18 bit loosely packed 3 - 24 bit + 0 + 2 + read-write + + + + + DSI_HOST_CFG_DPI_VSYNC_POLARITY + no description available + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_vsync_polarity + Sets polarity of dpi_vsync_input 0 - active low 1 - active high + 0 + 1 + read-write + + + + + DSI_HOST_CFG_DPI_HSYNC_POLARITY + no description available + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_hsync_polarity + Sets polarity of dpi_hsync_input 0 - active low 1 - active high + 0 + 1 + read-write + + + + + DSI_HOST_CFG_DPI_VIDEO_MODE + no description available + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_video_mode + Select DSI video mode that the host DPI module should generate packets for. 2'b00 - Non-Burst mode with Sync Pulses 2'b01 - Non-Burst mode with Sync Events 2'b10 - Burst mode 2'b11 - Reserved, not valid + 0 + 2 + read-write + + + + + DSI_HOST_CFG_DPI_HFP + no description available + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_hfp + Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet. + 0 + 16 + read-write + + + + + DSI_HOST_CFG_DPI_HBP + no description available + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_hbp + Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet. + 0 + 16 + read-write + + + + + DSI_HOST_CFG_DPI_HSA + no description available + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_hsa + Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet. + 0 + 16 + read-write + + + + + DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS + no description available + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_enable_mult_pkts + Enable Multiple packets per video line. When enabled, cfg_dpi_pixel_payload_size must be set to exactly half the size of the video line. 0 - Video Line is sent in a single packet 1 - Video Line is sent in two packets + 0 + 1 + read-write + + + + + DSI_HOST_CFG_DPI_VBP + no description available + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_vbp + Sets the number of lines in the vertical back porch. + 0 + 8 + read-write + + + + + DSI_HOST_CFG_DPI_VFP + no description available + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_vfp + Sets the number of lines in the vertical front porch. + 0 + 8 + read-write + + + + + DSI_HOST_CFG_DPI_BLLP_MODE + no description available + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_bllp_mode + Optimize bllp periods to Low Power mode when possible 0 - blanking packets are sent during BLLP periods 1 - LP mode is used for BLLP periods + 0 + 1 + read-write + + + + + DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP + no description available + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_use_null_pkt_bllp + Selects type of blanking packet to be sent during bllp region 0 - Blanking packet used in bllp region 1 - Null packet used in bllp region + 0 + 1 + read-write + + + + + DSI_HOST_CFG_DPI_VACTIVE + no description available + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_vactive + Sets the number of lines in the vertical active area. This field is equivalent to (real vertical size) - 1. For example, for an image of size 640x480, the bit field should be set as 479. + 0 + 14 + read-write + + + + + DSI_HOST_CFG_DPI_VC + no description available + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_cfg_dpi_vc + Sets the Virtual Channel (VC) of packets that will be sent to the receive packet interface. Packets with VC not equal to this value are discarded and the "DSI VC ID Invalid" bit (bit 12) in the DSI error report is set. + 0 + 2 + read-write + + + + + + + MIPI_DSI_HOST_APB_PKT_IF + MIPI DSI HOST APB PKT IF + MIPI_DSI_HOST_APB_PKT_IF + MIPI_DSI_HOST_APB_PKT_IF_ + 0x30A10280 + + 0 + 0x30 + registers + + + + DSI_HOST_TX_PAYLOAD + no description available + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_tx_payload + Tx Payload data write register. Writes to this registers load the payload fifo with 32 bit values. + 0 + 32 + read-write + + + + + DSI_HOST_PKT_CONTROL + no description available + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_pkt_control + Tx packet control register. [15:0] - Packet word count [17:16] - Packet Virtual Channel [23:18] - Packet Header DSI Data Type [24] - Lp or HS select. 0 - LP mode, 1 - HS mode [25] - perform BTA after packet is sent [26] - perform BTA only, no packet tx + 0 + 27 + read-write + + + + + DSI_HOST_SEND_PACKET + no description available + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_send_packet + Tx send packet. Writing to this register causes the packet described in dsi_host_pkt_control to be sent. + 0 + 1 + read-write + + + + + DSI_HOST_PKT_STATUS + no description available + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + dsi_host_pkt_status + Status of APB to packet interface [0] - state machine not idle [1] - Tx packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header has been received [8] - all rx packet payload data has been receive d + 0 + 9 + read-only + + + + + DSI_HOST_PKT_FIFO_WR_LEVEL + no description available + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + dsi_host_pkt_fifo_wr_level + Write level of APB to pkt interface fifo + 0 + 16 + read-only + + + + + DSI_HOST_PKT_FIFO_RD_LEVEL + no description available + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + dsi_host_pkt_fifo_rd_level + Read level of APB to pkt interface fifo + 0 + 16 + read-only + + + + + DSI_HOST_PKT_RX_PAYLOAD + no description available + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + dsi_host_pkt_rx_payload + APB to pkt interface rx payload read + 0 + 32 + read-only + + + + + DSI_HOST_PKT_RX_PKT_HEADER + no description available + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + dsi_host_pkt_rx_pkt_header + APB to pkt interface rx packet header [15:0] word count [21:16] data type [23:22] Virtual Channel + 0 + 24 + read-only + + + + + DSI_HOST_IRQ_STATUS + no description available + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + dsi_host_irq_status + Status of APB to packet interface [0] - state machine not idle [1] - Tx packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header has been received [8] - all rx packet payload data has been received [28:9] - map directory to dsi host controller status_out port bit descriptions [29] - host bta timeout, host controller host_bta_timeout port [30] - low power rx timeout, host controller lp_rx_timeout port [31] - high speed tx timeout, host controller hs_tx_timeout port + 0 + 32 + read-only + + + + + DSI_HOST_IRQ_STATUS2 + no description available + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + dsi_host_irq_status2 + Status of APB to packet interface part 2. Read part 2 first then dsi_host_irq_status. Reading dsi_host_irq_status will clear both status and status 2. [0] - single bit ecc error [1] - multi bit ecc error [2] - crc error + 0 + 3 + read-only + + + + + DSI_HOST_IRQ_MASK + no description available + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_irq_mask + irq mask [0] - state machine not idle [1] - Tx packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header has been received [8] - all rx packet payload data has been received [28:9] - map directory to dsi host controller status_out port bit descriptions [29] - host bta timeout, host controller host_bta_timeout port [30] - low power rx timeout, host controller lp_rx_timeout port [31] - high speed tx timeout, host controller hs_tx_timeout port + 0 + 32 + read-write + + + + + DSI_HOST_IRQ_MASK2 + no description available + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + dsi_host_irq_mask2 + irq mask 2 [0] - single bit ecc error [1] - multi bit ecc error [2] - crc error + 0 + 3 + read-write + + + + + + + MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC + MIPI DSI HOST FSL IP1 DPHY INTFC + MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC + MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_ + 0x30A10300 + + 0 + 0x48 + registers + + + + DPHY_PD_DPHY + no description available + 0 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + dphy_pd_dphy + DPHY PD_DPHY input control. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 1 + read-write + + + + + DPHY_M_PRG_HS_PREPARE + no description available + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + dphy_m_prg_hs_prepare + DPHY m_PRG_HS_PREPARE input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 2 + read-write + + + dphy_m_prg_hs_prepare_0 + 1 + 0 + + + dphy_m_prg_hs_prepare_1 + 1.5 + 0x1 + + + dphy_m_prg_hs_prepare_2 + 2 + 0x2 + + + dphy_m_prg_hs_prepare_3 + 2.5 + 0x3 + + + + + + + DPHY_MC_PRG_HS_PREPARE + no description available + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + dphy_mc_prg_hs_prepare + DPHY mc_PRG_HS_PREPARE input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 1 + read-write + + + dphy_mc_prg_hs_prepare_0 + 1 + 0 + + + dphy_mc_prg_hs_prepare_1 + 1.5 + 0x1 + + + + + + + DPHY_M_PRG_HS_ZERO + no description available + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + dphy_m_prg_hs_zero + DPHY m_PRG_HS_ZERO input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 5 + read-write + + + dphy_m_prg_hs_zero_0 + 0 + 0 + + + dphy_m_prg_hs_zero_1 + 1 + 0x1 + + + dphy_m_prg_hs_zero_2 + 2 + 0x2 + + + dphy_m_prg_hs_zero_3 + 3 + 0x3 + + + dphy_m_prg_hs_zero_4 + 4 + 0x4 + + + dphy_m_prg_hs_zero_5 + 5 + 0x5 + + + dphy_m_prg_hs_zero_6 + 6 + 0x6 + + + dphy_m_prg_hs_zero_7 + 7 + 0x7 + + + dphy_m_prg_hs_zero_8 + 8 + 0x8 + + + dphy_m_prg_hs_zero_9 + 9 + 0x9 + + + dphy_m_prg_hs_zero_10 + 10 + 0xA + + + dphy_m_prg_hs_zero_11 + 11 + 0xB + + + dphy_m_prg_hs_zero_12 + 12 + 0xC + + + dphy_m_prg_hs_zero_13 + 13 + 0xD + + + dphy_m_prg_hs_zero_14 + 14 + 0xE + + + dphy_m_prg_hs_zero_15 + 15 + 0xF + + + dphy_m_prg_hs_zero_16 + 16 + 0x10 + + + dphy_m_prg_hs_zero_17 + 17 + 0x11 + + + dphy_m_prg_hs_zero_18 + 18 + 0x12 + + + dphy_m_prg_hs_zero_19 + 19 + 0x13 + + + dphy_m_prg_hs_zero_20 + 20 + 0x14 + + + dphy_m_prg_hs_zero_21 + 21 + 0x15 + + + dphy_m_prg_hs_zero_22 + 22 + 0x16 + + + dphy_m_prg_hs_zero_23 + 23 + 0x17 + + + dphy_m_prg_hs_zero_24 + 24 + 0x18 + + + dphy_m_prg_hs_zero_25 + 25 + 0x19 + + + dphy_m_prg_hs_zero_26 + 26 + 0x1A + + + dphy_m_prg_hs_zero_27 + 27 + 0x1B + + + dphy_m_prg_hs_zero_28 + 28 + 0x1C + + + dphy_m_prg_hs_zero_29 + 29 + 0x1D + + + dphy_m_prg_hs_zero_30 + 30 + 0x1E + + + dphy_m_prg_hs_zero_31 + 31 + 0x1F + + + + + + + DPHY_MC_PRG_HS_ZERO + no description available + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + dphy_mc_prg_hs_zero + DPHY mc_PRG_HS_ZERO input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 6 + read-write + + + dphy_mc_prg_hs_zero_32 + 32 + 0x20 + + + dphy_mc_prg_hs_zero_33 + 33 + 0x21 + + + dphy_mc_prg_hs_zero_34 + 34 + 0x22 + + + dphy_mc_prg_hs_zero_35 + 35 + 0x23 + + + dphy_mc_prg_hs_zero_36 + 36 + 0x24 + + + dphy_mc_prg_hs_zero_37 + 37 + 0x25 + + + dphy_mc_prg_hs_zero_38 + 38 + 0x26 + + + dphy_mc_prg_hs_zero_39 + 39 + 0x27 + + + dphy_mc_prg_hs_zero_40 + 40 + 0x28 + + + dphy_mc_prg_hs_zero_41 + 41 + 0x29 + + + dphy_mc_prg_hs_zero_42 + 42 + 0x2A + + + dphy_mc_prg_hs_zero_43 + 43 + 0x2B + + + dphy_mc_prg_hs_zero_44 + 44 + 0x2C + + + dphy_mc_prg_hs_zero_45 + 45 + 0x2D + + + dphy_mc_prg_hs_zero_46 + 46 + 0x2E + + + dphy_mc_prg_hs_zero_47 + 47 + 0x2F + + + dphy_mc_prg_hs_zero_48 + 48 + 0x30 + + + dphy_mc_prg_hs_zero_49 + 49 + 0x31 + + + dphy_mc_prg_hs_zero_50 + 50 + 0x32 + + + dphy_mc_prg_hs_zero_51 + 51 + 0x33 + + + dphy_mc_prg_hs_zero_52 + 52 + 0x34 + + + dphy_mc_prg_hs_zero_53 + 53 + 0x35 + + + dphy_mc_prg_hs_zero_54 + 54 + 0x36 + + + dphy_mc_prg_hs_zero_55 + 55 + 0x37 + + + dphy_mc_prg_hs_zero_56 + 56 + 0x38 + + + dphy_mc_prg_hs_zero_57 + 57 + 0x39 + + + dphy_mc_prg_hs_zero_58 + 58 + 0x3A + + + dphy_mc_prg_hs_zero_59 + 59 + 0x3B + + + dphy_mc_prg_hs_zero_60 + 60 + 0x3C + + + dphy_mc_prg_hs_zero_61 + 61 + 0x3D + + + dphy_mc_prg_hs_zero_62 + 62 + 0x3E + + + dphy_mc_prg_hs_zero_63 + 63 + 0x3F + + + + + + + DPHY_M_PRG_HS_TRAIL + no description available + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + dphy_m_prg_hs_trail + DPHY m_PRG_HS_TRAIL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 4 + read-write + + + dphy_m_prg_hs_trail_0 + 0 + 0 + + + dphy_m_prg_hs_trail_1 + 1 + 0x1 + + + dphy_m_prg_hs_trail_2 + 2 + 0x2 + + + dphy_m_prg_hs_trail_3 + 3 + 0x3 + + + dphy_m_prg_hs_trail_4 + 4 + 0x4 + + + dphy_m_prg_hs_trail_5 + 5 + 0x5 + + + dphy_m_prg_hs_trail_6 + 6 + 0x6 + + + dphy_m_prg_hs_trail_7 + 7 + 0x7 + + + dphy_m_prg_hs_trail_8 + 8 + 0x8 + + + dphy_m_prg_hs_trail_9 + 9 + 0x9 + + + dphy_m_prg_hs_trail_10 + 10 + 0xA + + + dphy_m_prg_hs_trail_11 + 11 + 0xB + + + dphy_m_prg_hs_trail_12 + 12 + 0xC + + + dphy_m_prg_hs_trail_13 + 13 + 0xD + + + dphy_m_prg_hs_trail_14 + 14 + 0xE + + + dphy_m_prg_hs_trail_15 + 15 + 0xF + + + + + + + DPHY_MC_PRG_HS_TRAIL + no description available + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + dphy_mc_prg_hs_trail + DPHY mc_PRG_HS_TRAIL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 4 + read-write + + + dphy_mc_prg_hs_trail_0 + 0 + 0 + + + dphy_mc_prg_hs_trail_1 + 1 + 0x1 + + + dphy_mc_prg_hs_trail_2 + 2 + 0x2 + + + dphy_mc_prg_hs_trail_3 + 3 + 0x3 + + + dphy_mc_prg_hs_trail_4 + 4 + 0x4 + + + dphy_mc_prg_hs_trail_5 + 5 + 0x5 + + + dphy_mc_prg_hs_trail_6 + 6 + 0x6 + + + dphy_mc_prg_hs_trail_7 + 7 + 0x7 + + + dphy_mc_prg_hs_trail_8 + 8 + 0x8 + + + dphy_mc_prg_hs_trail_9 + 9 + 0x9 + + + dphy_mc_prg_hs_trail_10 + 10 + 0xA + + + dphy_mc_prg_hs_trail_11 + 11 + 0xB + + + dphy_mc_prg_hs_trail_12 + 12 + 0xC + + + dphy_mc_prg_hs_trail_13 + 13 + 0xD + + + dphy_mc_prg_hs_trail_14 + 14 + 0xE + + + dphy_mc_prg_hs_trail_15 + 15 + 0xF + + + + + + + DPHY_PD_PLL + no description available + 0x1C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + PD + DPHY PD_PLL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 1 + read-write + + + + + DPHY_TST + no description available + 0x20 + 32 + read-write + 0x25 + 0xFFFFFFFF + + + TST + DPHY TST input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 6 + read-write + + + + + DPHY_CN + no description available + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + CN + DPHY PLL Input Divider + 0 + 5 + read-write + + + CN_0 + Divide by 2 + 0 + + + CN_1 + Divide by 32 + 0x1 + + + CN_2 + Divide by 11 + 0x2 + + + CN_3 + Divide by 31 + 0x3 + + + CN_4 + Divide by 10 + 0x4 + + + CN_5 + Divide by 26 + 0x5 + + + CN_6 + Divide by 30 + 0x6 + + + CN_7 + Divide by 7 + 0x7 + + + CN_8 + Divide by 13 + 0x8 + + + CN_9 + Divide by 9 + 0x9 + + + CN_10 + Divide by 15 + 0xA + + + CN_11 + Divide by 25 + 0xB + + + CN_12 + Divide by 29 + 0xC + + + CN_13 + Divide by 23 + 0xD + + + CN_14 + Divide by 6 + 0xE + + + CN_15 + Divide by 20 + 0xF + + + CN_16 + Divide by 3 + 0x10 + + + CN_17 + Divide by 12 + 0x11 + + + CN_18 + Divide by 27 + 0x12 + + + CN_19 + Divide by 8 + 0x13 + + + CN_20 + Divide by 14 + 0x14 + + + CN_21 + Divide by 16 + 0x15 + + + CN_22 + Divide by 24 + 0x16 + + + CN_23 + Divide by 21 + 0x17 + + + CN_24 + Divide by 4 + 0x18 + + + CN_25 + Divide by 28 + 0x19 + + + CN_26 + Divide by 17 + 0x1A + + + CN_27 + Divide by 22 + 0x1B + + + CN_28 + Divide by 5 + 0x1C + + + CN_29 + Divide by 18 + 0x1D + + + CN_30 + Divide by 19 + 0x1E + + + CN_31 + Divide by 1 + 0x1F + + + + + + + DPHY_CM + no description available + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + CM + DPHY PLL Feedback Divider + 0 + 8 + read-write + + + CM_0 + Divide by 128 + 0 + + + CM_127 + Divide by 255 + 0x7F + + + CM_128 + Divide by 64 + 0x80 + + + CM_191 + Divide by 127 + 0xBF + + + CM_192 + Divide by 32 + 0xC0 + + + CM_223 + Divide by 63 + 0xDF + + + CM_224 + Divide by 16 + #111x0000 + + + CM_239 + Divide by 31 + #111x1111 + + + + + + + DPHY_CO + no description available + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + CO + DPHY PLL Output Divider + 0 + 2 + read-write + + + CO_0 + Divide by 1 + 0 + + + CO_1 + Divide by 2 + 0x1 + + + CO_2 + Divide by 4 + 0x2 + + + CO_3 + Divide by 8 + 0x3 + + + + + + + DPHY_LOCK + no description available + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOCK + DPHY PLL LOCK output. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 1 + read-only + + + + + DPHY_LOCK_BYP + no description available + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + dphy_lock_byp + DPHY LOCK_BYP input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 1 + read-write + + + + + DPHY_RTERM_SEL + no description available + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + dphy_rterm_sel + DPHY RTERM_SEL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 1 + read-write + + + + + DPHY_AUTO_PD_EN + no description available + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + dphy_auto_pd_en + DPHY AUTO_PD_EN input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 1 + read-write + + + + + DPHY_RXLPRP + no description available + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + dphy_rxlprp + DPHY RXLPRP input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 2 + read-write + + + + + DPHY_RXCDRP + no description available + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + dphy_rxcdrp + DPHY RXCDRP input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. + 0 + 2 + read-write + + + + + + + I2C1 + I2C + I2C + I2C1_ + I2C + 0x30A20000 + + 0 + 0x12 + registers + + + I2C1 + 35 + + + + IADR + I2C Address Register + 0 + 16 + read-write + 0 + 0xFFFF + + + ADR + Slave address + 1 + 7 + read-write + + + + + IFDR + I2C Frequency Divider Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + IC + I2C clock rate + 0 + 6 + read-write + + + + + I2CR + I2C Control Register + 0x8 + 16 + read-write + 0 + 0xFFFF + + + RSTA + Repeat start + 2 + 1 + write-only + + + RSTA_0 + No repeat start + 0 + + + RSTA_1 + Generates a Repeated Start condition + 0x1 + + + + + TXAK + Transmit acknowledge enable + 3 + 1 + read-write + + + TXAK_0 + An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. + 0 + + + TXAK_1 + No acknowledge signal response is sent (that is, the acknowledge bit = 1). + 0x1 + + + + + MTX + Transmit/Receive mode select bit. Selects the direction of master and slave transfers. + 4 + 1 + read-write + + + MTX_0 + Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in the I2C status register (I2C_I2SR[SRW]). + 0 + + + MTX_1 + Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1. + 0x1 + + + + + MSTA + Master/Slave mode select bit + 5 + 1 + read-write + + + MSTA_0 + Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode. + 0 + + + MSTA_1 + Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode. + 0x1 + + + + + IIEN + I2C interrupt enable + 6 + 1 + read-write + + + IIEN_0 + I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition occurs. + 0 + + + IIEN_1 + I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set. + 0x1 + + + + + IEN + I2C enable + 7 + 1 + read-write + + + IEN_0 + The block is disabled, but registers can still be accessed. + 0 + + + IEN_1 + The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect. + 0x1 + + + + + + + I2SR + I2C Status Register + 0xC + 16 + read-write + 0x81 + 0xFFFF + + + RXAK + Received acknowledge + 0 + 1 + read-only + + + RXAK_0 + An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus. + 0 + + + RXAK_1 + A "No acknowledge" signal was detected at the ninth clock. + 0x1 + + + + + IIF + I2C interrupt + 1 + 1 + read-write + + + IIF_0 + No I2C interrupt pending. + 0 + + + IIF_1 + An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific address in Slave Receive mode. Arbitration is lost. + 0x1 + + + + + SRW + Slave read/write + 2 + 1 + read-only + + + SRW_0 + Slave receive, master writing to slave + 0 + + + SRW_1 + Slave transmit, master reading from slave + 0x1 + + + + + IAL + Arbitration lost + 4 + 1 + read-write + + + IAL_0 + No arbitration lost. + 0 + + + IAL_1 + Arbitration is lost. + 0x1 + + + + + IBB + I2C bus busy bit + 5 + 1 + read-only + + + IBB_0 + Bus is idle. If a Stop signal is detected, IBB is cleared. + 0 + + + IBB_1 + Bus is busy. When Start is detected, IBB is set. + 0x1 + + + + + IAAS + I2C addressed as a slave bit + 6 + 1 + read-only + + + IAAS_0 + Not addressed + 0 + + + IAAS_1 + Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address. + 0x1 + + + + + ICF + Data transferring bit. While one byte of data is transferred, ICF is cleared. + 7 + 1 + read-only + + + ICF_0 + Transfer is in progress. + 0 + + + ICF_1 + Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer. + 0x1 + + + + + + + I2DR + I2C Data I/O Register + 0x10 + 16 + read-write + 0 + 0xFFFF + + + DATA + Data Byte + 0 + 8 + read-write + + + + + + + I2C2 + I2C + I2C + I2C2_ + 0x30A30000 + + 0 + 0x12 + registers + + + I2C2 + 36 + + + + I2C3 + I2C + I2C + I2C3_ + 0x30A40000 + + 0 + 0x12 + registers + + + I2C3 + 37 + + + + I2C4 + I2C + I2C + I2C4_ + 0x30A50000 + + 0 + 0x12 + registers + + + I2C4 + 38 + + + + MIPI_CSI2RX1 + no description available + MIPI_CSI2RX + MIPI_CSI2RX + 0x30A70000 + + 0 + 0x34 + registers + + + + CSI2RX_CFG_NUM_LANES + no description available + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + csi2rx_cfg_num_lanes + Sets the number of active lanes that are to be used for receiving data. + 0 + 2 + read-write + + + csi2rx_cfg_num_lanes_0 + 1 Lane + 0 + + + csi2rx_cfg_num_lanes_1 + 2 Lane + 0x1 + + + csi2rx_cfg_num_lanes_2 + 3 Lane + 0x2 + + + csi2rx_cfg_num_lanes_3 + 4 Lane + 0x3 + + + + + + + CSI2RX_CFG_DISABLE_DATA_LANES + no description available + 0x4 + 32 + read-write + 0xF + 0xFFFFFFFF + + + csi2rx_cfg_disable_data_lanes + Setting bits to a '1' value causes the DPHY Enable signal to deassert. + 0 + 4 + read-write + + + csi2rx_cfg_disable_data_lanes_1 + Data Lane 0 + 0x1 + + + csi2rx_cfg_disable_data_lanes_2 + Data Lane 1 + 0x2 + + + csi2rx_cfg_disable_data_lanes_4 + Data Lane 2 + 0x4 + + + csi2rx_cfg_disable_data_lanes_8 + Data Lane 3 + 0x8 + + + + + + + CSI2RX_BIT_ERR + no description available + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + csi2rx_bit_err + BIT_ERR: CSI-2 RX Controller ECC and CRC error status. + 0 + 10 + read-only + + + + + CSI2RX_IRQ_STATUS + no description available + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + csi2rx_irq_status + CSI2 RX IRQ status + 0 + 9 + read-only + + + + + CSI2RX_IRQ_MASK + no description available + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + csi2rx_irq_mask + CSI2 RX IRQ Mask setting + 0 + 9 + read-write + + + + + CSI2RX_ULPS_STATUS + no description available + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + csi2rx_ulps_status + Status of RX DPHY ULPS state + 0 + 10 + read-only + + + + + CSI2RX_PPI_ERRSOT_HS + no description available + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + csi2rx_ppi_errsot_hs + CSI2 RX DPHY PPI ErrSotHS captured status from the DPHY. + 0 + 4 + read-only + + + + + CSI2RX_PPI_ERRSOTSYNC_HS + no description available + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + csi2rx_ppi_errsotsync_hs + CSI2 RX DPHY PPI ErrSotSync_HS captured status from the DPHY. + 0 + 4 + read-only + + + + + CSI2RX_PPI_ERRESC + no description available + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + csi2rx_ppi_erresc + CSI2 RX DPHY PPI ErrEsc captured status from the DPHY. + 0 + 4 + read-only + + + + + CSI2RX_PPI_ERRSYNCESC + no description available + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + csi2rx_ppi_errsyncesc + CSI2 RX DPHY PPI ErrSyncEsc captured status from the DPHY. + 0 + 4 + read-only + + + + + CSI2RX_PPI_ERRCONTROL + no description available + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + csi2rx_ppi_errcontrol + CSI2 RX DPHY PPI ErrControl captured status from the DPHY. + 0 + 4 + read-only + + + + + CSI2RX_CFG_DISABLE_PAYLOAD_0 + no description available + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + csi2rx_cfg_disable_payload_null + Null + 0 + 1 + read-write + + + csi2rx_cfg_disable_payload_blank + Blank + 1 + 1 + read-write + + + csi2rx_cfg_disable_payload_embedded + Embedded + 2 + 1 + read-write + + + csi2rx_cfg_disable_payload_legacy_yuv_8 + Legacy YUV 420 8 bit + 10 + 1 + read-write + + + csi2rx_cfg_disable_payload_yuv_8 + YUV422 8 bit + 14 + 1 + read-write + + + csi2rx_cfg_disable_payload_yuv_10 + YUV422 10 bit + 15 + 1 + read-write + + + csi2rx_cfg_disable_payload_rgb444 + RGB444 + 16 + 1 + read-write + + + csi2rx_cfg_disable_payload_rgb555 + RGB555 + 17 + 1 + read-write + + + csi2rx_cfg_disable_payload_rgb565 + RGB565 + 18 + 1 + read-write + + + csi2rx_cfg_disable_payload_rgb666 + RGB666 + 19 + 1 + read-write + + + csi2rx_cfg_disable_payload_rgb888 + RGB888 + 20 + 1 + read-write + + + csi2rx_cfg_disable_payload_raw6 + RAW6 + 24 + 1 + read-write + + + csi2rx_cfg_disable_payload_raw7 + RAW7 + 25 + 1 + read-write + + + csi2rx_cfg_disable_payload_raw8 + RAW8 + 26 + 1 + read-write + + + csi2rx_cfg_disable_payload_raw10 + RAW10 + 27 + 1 + read-write + + + csi2rx_cfg_disable_payload_raw12 + RAW12 + 28 + 1 + read-write + + + csi2rx_cfg_disable_payload_raw14 + RAW14 + 29 + 1 + read-write + + + + + CSI2RX_CFG_DISABLE_PAYLOAD_1 + no description available + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + csi2rx_cfg_disable_payload_udef_30 + User defined type 0x31 + 0 + 1 + read-write + + + csi2rx_cfg_disable_payload_udef_31 + User defined type 0x32 + 1 + 1 + read-write + + + csi2rx_cfg_disable_payload_udef_32 + User defined type 0x33 + 2 + 1 + read-write + + + csi2rx_cfg_disable_payload_udef_33 + User defined type 0x34 + 3 + 1 + read-write + + + csi2rx_cfg_disable_payload_udef_34 + User defined type 0x35 + 4 + 1 + read-write + + + csi2rx_cfg_disable_payload_udef_35 + User defined type 0x35 + 5 + 1 + read-write + + + csi2rx_cfg_disable_payload_udef_36 + User defined type 0x36 + 6 + 1 + read-write + + + csi2rx_cfg_disable_payload_udef_37 + User defined type 0x37 + 7 + 1 + read-write + + + csi2rx_cfg_disable_payload_unsupported + Unsupported Data Types + 16 + 1 + read-write + + + + + + + MIPI_CSI2RX2 + no description available + MIPI_CSI2RX + 0x30B60000 + + 0 + 0x34 + registers + + + + MUB + MU + MUB + MUB_ + 0x30AB0000 + + 0 + 0x28 + registers + + + MU_M4 + 97 + + + + BTR0 + Processor B Transmit Register 0 + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BTR0 + Processor B Transmit Register 0 + 0 + 32 + read-write + + + + + BTR1 + Processor B Transmit Register 1 + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + BTR1 + Processor B Transmit Register 1 + 0 + 32 + read-write + + + + + BTR2 + Processor B Transmit Register 2 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + BTR2 + Processor B Transmit Register 2 + 0 + 32 + read-write + + + + + BTR3 + Processor B Transmit Register 3 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + BTR3 + Processor B Transmit Register 3 + 0 + 32 + read-write + + + + + BRR0 + Processor B Receive Register 0 + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + BRR0 + Processor B Receive Register 0 + 0 + 32 + read-only + + + + + BRR1 + Processor B Receive Register 1 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + BRR1 + Processor B Receive Register 1 + 0 + 32 + read-only + + + + + BRR2 + Processor B Receive Register 2 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + BRR2 + Processor B Receive Register 2 + 0 + 32 + read-only + + + + + BRR3 + Processor B Receive Register 3 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + BRR3 + Processor B Receive Register 3 + 0 + 32 + read-only + + + + + BSR + Processor B Status Register + 0x20 + 32 + read-write + 0xF00080 + 0xFFFFFFFF + + + Fn + For n = {0, 1, 2} Processor B-Side Flag n + 0 + 3 + read-write + + + Fn_0 + ABFn bit in ACR register is written 0 (default). + 0 + + + Fn_1 + ABFn bit in ACR register is written 1. + 0x1 + + + + + EP + Processor B-Side Event Pending + 4 + 1 + read-write + + + EP_0 + The Processor B-side event is not pending (default). + 0 + + + EP_1 + The Processor B-side event is pending. + 0x1 + + + + + APM + Processor A Power Mode. (Read-only) APM[1:0] bits indicate the Processor A power mode. + 5 + 2 + read-write + + + APM_0 + The System is in Run Mode. + 0 + + + APM_1 + The System is in WAIT Mode. + 0x1 + + + APM_3 + The System is in STOP Mode. + 0x3 + + + + + ARS + Processor A Reset State + 7 + 1 + read-write + + + ARS_0 + The Processor A or the Processor A-side of the MU is not in reset. + 0 + + + ARS_1 + The Processor A or the Processor A-side of the MU is in reset. + 0x1 + + + + + FUP + Processor B Flags Update Pending + 8 + 1 + read-write + + + FUP_0 + No flags updated, initiated by the Processor B, in progress (default) + 0 + + + FUP_1 + Processor B initiated flags update, processing + 0x1 + + + + + TEn + For n = {0, 1, 2, 3} Processor B Transmit Register n Empty + 20 + 4 + read-write + + + TEn_0 + BTRn register is not empty. + 0 + + + TEn_1 + BTRn register is empty (default). + 0x1 + + + + + RFn + For n = {0, 1, 2, 3} Processor B Receive Register n Full + 24 + 4 + read-write + + + RFn_0 + BRRn register is not full (default). + 0 + + + RFn_1 + BRRn register has received data from ATRn register and is ready to be read by the Processor B. + 0x1 + + + + + GIPn + For n = {0, 1, 2, 3} Processor B General Interrupt Request n Pending + 28 + 4 + read-write + + + GIPn_0 + Processor B general purpose interrupt n is not pending. (default) + 0 + + + GIPn_1 + Processor B general purpose interrupt n is pending. + 0x1 + + + + + + + BCR + Processor B Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + BAFn + For n = {0, 1, 2} Processor B to Processor A Flag n + 0 + 3 + read-write + + + BAFn_0 + Clears the Fn bit in the ASR register. + 0 + + + BAFn_1 + Sets the Fn bit in the ASR register. + 0x1 + + + + + HRM + Processor B Hardware Reset Mask + 4 + 1 + read-write + + + HRM_0 + BHR bit in ACR is not masked, enables the hardware reset to the Processor B (default after hardware reset). + 0 + + + HRM_1 + BHR bit in ACR is masked, disables the hardware reset request to the Processor B. + 0x1 + + + + + GIRn + For n = {0, 1, 2, 3} Processor B General Purpose Interrupt Request n + 16 + 4 + read-write + + + GIRn_0 + Processor B General Interrupt n is not requested to the Processor A (default). + 0 + + + GIRn_1 + Processor B General Interrupt n is requested to the Processor A. + 0x1 + + + + + TIEn + For n = {0, 1, 2, 3} Processor B Transmit Interrupt Enable n + 20 + 4 + read-write + + + TIEn_0 + Disables Processor B Transmit Interrupt n. (default) + 0 + + + TIEn_1 + Enables Processor B Transmit Interrupt n. + 0x1 + + + + + RIEn + For n = {0, 1, 2, 3} Processor B Receive Interrupt Enable n + 24 + 4 + read-write + + + RIEn_0 + Disables Processor B Receive Interrupt n. (default) + 0 + + + RIEn_1 + Enables Processor B Receive Interrupt n. + 0x1 + + + + + GIEn + For n = {0, 1, 2, 3} Processor B General Purpose Interrupt Enable n + 28 + 4 + read-write + + + GIEn_0 + Disables Processor B General Interrupt n. (default) + 0 + + + GIEn_1 + Enables Processor B General Interrupt n. + 0x1 + + + + + + + + + SEMA4 + IPS_Semaphores + SEMA4 + SEMA4_ + 0x30AC0000 + + 0 + 0x106 + registers + + + + Gate00 + Semaphores Gate 0 Register + 0 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate01 + Semaphores Gate 1 Register + 0x1 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate02 + Semaphores Gate 2 Register + 0x2 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate03 + Semaphores Gate 3 Register + 0x3 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate04 + Semaphores Gate 4 Register + 0x4 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate05 + Semaphores Gate 5 Register + 0x5 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate06 + Semaphores Gate 6 Register + 0x6 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate07 + Semaphores Gate 7 Register + 0x7 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate08 + Semaphores Gate 8 Register + 0x8 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate09 + Semaphores Gate 9 Register + 0x9 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate10 + Semaphores Gate 10 Register + 0xA + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate11 + Semaphores Gate 11 Register + 0xB + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate12 + Semaphores Gate 12 Register + 0xC + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate13 + Semaphores Gate 13 Register + 0xD + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate14 + Semaphores Gate 14 Register + 0xE + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + Gate15 + Semaphores Gate 15 Register + 0xF + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine. + 0 + 2 + read-write + + + GTFSM_0 + The gate is unlocked (free). + 0 + + + GTFSM_1 + The gate has been locked by processor 0. + 0x1 + + + GTFSM_2 + The gate has been locked by processor 1. + 0x2 + + + GTFSM_3 + This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. + 0x3 + + + + + + + 2 + 0x8 + 0,1 + CP%sINE + Semaphores Processor n IRQ Notification Enable + 0x40 + 16 + read-write + 0 + 0xFFFF + + + INE7 + Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 7. + 0 + 1 + read-write + + + INE7_0 + The generation of the notification interrupt is disabled. + 0 + + + INE7_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE6 + Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 6. + 1 + 1 + read-write + + + INE6_0 + The generation of the notification interrupt is disabled. + 0 + + + INE6_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE5 + Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 5. + 2 + 1 + read-write + + + INE5_0 + The generation of the notification interrupt is disabled. + 0 + + + INE5_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE4 + Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 4. + 3 + 1 + read-write + + + INE4_0 + The generation of the notification interrupt is disabled. + 0 + + + INE4_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE3 + Interrupt Request Notification Enable 3 + 4 + 1 + read-write + + + INE3_0 + The generation of the notification interrupt is disabled. + 0 + + + INE3_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE2 + Interrupt Request Notification Enable 2 + 5 + 1 + read-write + + + INE2_0 + The generation of the notification interrupt is disabled. + 0 + + + INE2_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE1 + Interrupt Request Notification Enable 1 + 6 + 1 + read-write + + + INE1_0 + The generation of the notification interrupt is disabled. + 0 + + + INE1_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE0 + Interrupt Request Notification Enable 0 + 7 + 1 + read-write + + + INE0_0 + The generation of the notification interrupt is disabled. + 0 + + + INE0_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE15 + Interrupt Request Notification Enable 15. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 15. + 8 + 1 + read-write + + + INE15_0 + The generation of the notification interrupt is disabled. + 0 + + + INE15_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE14 + Interrupt Request Notification Enable 14. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 14. + 9 + 1 + read-write + + + INE14_0 + The generation of the notification interrupt is disabled. + 0 + + + INE14_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE13 + Interrupt Request Notification Enable 13. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 13. + 10 + 1 + read-write + + + INE13_0 + The generation of the notification interrupt is disabled. + 0 + + + INE13_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE12 + Interrupt Request Notification Enable 12. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 12. + 11 + 1 + read-write + + + INE12_0 + The generation of the notification interrupt is disabled. + 0 + + + INE12_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE11 + Interrupt Request Notification Enable 11. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 11. + 12 + 1 + read-write + + + INE11_0 + The generation of the notification interrupt is disabled. + 0 + + + INE11_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE10 + Interrupt Request Notification Enable 10. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 10. + 13 + 1 + read-write + + + INE10_0 + The generation of the notification interrupt is disabled. + 0 + + + INE10_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE9 + Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 9. + 14 + 1 + read-write + + + INE9_0 + The generation of the notification interrupt is disabled. + 0 + + + INE9_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + INE8 + Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 8. + 15 + 1 + read-write + + + INE8_0 + The generation of the notification interrupt is disabled. + 0 + + + INE8_1 + The generation of the notification interrupt is enabled. + 0x1 + + + + + + + 2 + 0x8 + 0,1 + CP%sNTF + Semaphores Processor n IRQ Notification + 0x80 + 16 + read-only + 0 + 0xFFFF + + + GN7 + Gate 7 Notification + 0 + 1 + read-only + + + GN6 + Gate 6 Notification + 1 + 1 + read-only + + + GN5 + Gate 5 Notification + 2 + 1 + read-only + + + GN4 + Gate 4 Notification + 3 + 1 + read-only + + + GN3 + Gate 3 Notification + 4 + 1 + read-only + + + GN2 + Gate 2 Notification + 5 + 1 + read-only + + + GN1 + Gate 1 Notification + 6 + 1 + read-only + + + GN0 + Gate 0 Notification + 7 + 1 + read-only + + + GN15 + Gate 15 Notification + 8 + 1 + read-only + + + GN14 + Gate 14 Notification + 9 + 1 + read-only + + + GN13 + Gate 13 Notification + 10 + 1 + read-only + + + GN12 + Gate 12 Notification + 11 + 1 + read-only + + + GN11 + Gate 11 Notification + 12 + 1 + read-only + + + GN10 + Gate 10 Notification + 13 + 1 + read-only + + + GN9 + Gate 9 Notification + 14 + 1 + read-only + + + GN8 + Gate 8 Notification + 15 + 1 + read-only + + + + + RSTGT + Semaphores (Secure) Reset Gate n + 0x100 + 16 + read-write + 0 + 0xFFFF + + + RSTGSM_RSTGMS_RSTGDP + This field contains subfields that vary depending on whether it is being read or written + 0 + 8 + read-write + + + RSTGTN + Reset Gate Number + 8 + 8 + read-write + + + + + RSTNTF + Semaphores (Secure) Reset IRQ Notification + 0x104 + 16 + read-write + 0 + 0xFFFF + + + RSTNSM_RSTNMS_RSTNDP + This field contains subfields that vary depending on whether it is being read or written + 0 + 8 + read-write + + + RSTNTN + Reset Notification Number + 8 + 8 + read-write + + + + + + + uSDHC1 + uSDHC + USDHC + uSDHC1_ + USDHC + 0x30B40000 + + 0 + 0xD0 + registers + + + USDHC1 + 22 + + + + DS_ADDR + DMA System Address + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DS_ADDR + DMA System Address: This register contains the 32-bit system memory address for a DMA transfer + 2 + 30 + read-write + + + + + BLK_ATT + Block Attributes + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLKSIZE + Transfer Block Size: This register specifies the block size for block data transfers + 0 + 13 + read-write + + + BLKSIZE_0 + No data transfer + 0 + + + BLKSIZE_1 + 1 Byte + 0x1 + + + BLKSIZE_2 + 2 Bytes + 0x2 + + + BLKSIZE_3 + 3 Bytes + 0x3 + + + BLKSIZE_4 + 4 Bytes + 0x4 + + + BLKSIZE_8 + 4096 Bytes + 0x8 + + + BLKSIZE_200 + 512 Bytes + 0xC8 + + + BLKSIZE_800 + 2048 Bytes + 0x320 + + + + + BLKCNT + Blocks Count For Current Transfer: This register is enabled when the Block Count Enable bit in the Transfer Mode register is set to 1 and is valid only for multiple block transfers + 16 + 16 + read-write + + + BLKCNT_0 + Stop Count + 0 + + + BLKCNT_1 + 1 block + 0x1 + + + BLKCNT_2 + 2 blocks + 0x2 + + + + + + + CMD_ARG + Command Argument + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMDARG + Command Argument + 0 + 32 + read-write + + + + + CMD_XFR_TYP + Command Transfer Type + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RSPTYP + Response Type Select + 16 + 2 + read-write + + + RSPTYP_0 + No Response + 0 + + + RSPTYP_1 + Response Length 136 + 0x1 + + + RSPTYP_2 + Response Length 48 + 0x2 + + + RSPTYP_3 + Response Length 48, check Busy after response + 0x3 + + + + + CCCEN + Command CRC Check Enable + 19 + 1 + read-write + + + CCCEN_0 + Disable + 0 + + + CCCEN_1 + Enable + 0x1 + + + + + CICEN + Command Index Check Enable + 20 + 1 + read-write + + + CICEN_0 + Disable + 0 + + + CICEN_1 + Enable + 0x1 + + + + + DPSEL + Data Present Select + 21 + 1 + read-write + + + DPSEL_0 + No Data Present + 0 + + + DPSEL_1 + Data Present + 0x1 + + + + + CMDTYP + Command Type + 22 + 2 + read-write + + + CMDTYP_0 + Normal Other commands + 0 + + + CMDTYP_1 + Suspend CMD52 for writing Bus Suspend in CCCR + 0x1 + + + CMDTYP_2 + Resume CMD52 for writing Function Select in CCCR + 0x2 + + + CMDTYP_3 + Abort CMD12, CMD52 for writing I/O Abort in CCCR + 0x3 + + + + + CMDINX + Command Index + 24 + 6 + read-write + + + + + CMD_RSP0 + Command Response0 + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP0 + Command Response 0 + 0 + 32 + read-only + + + + + CMD_RSP1 + Command Response1 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP1 + Command Response 1 + 0 + 32 + read-only + + + + + CMD_RSP2 + Command Response2 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP2 + Command Response 2 + 0 + 32 + read-only + + + + + CMD_RSP3 + Command Response3 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP3 + Command Response 3 + 0 + 32 + read-only + + + + + DATA_BUFF_ACC_PORT + Data Buffer Access Port + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATCONT + Data Content + 0 + 32 + read-write + + + + + PRES_STATE + Present State + 0x24 + 32 + read-only + 0x8080 + 0xFFFFFFFF + + + CIHB + Command Inhibit (CMD) + 0 + 1 + read-only + + + CIHB_0 + Can issue command using only CMD line + 0 + + + CIHB_1 + Cannot issue command + 0x1 + + + + + CDIHB + Command Inhibit (DATA) + 1 + 1 + read-only + + + CDIHB_0 + Can issue command which uses the DATA line + 0 + + + CDIHB_1 + Cannot issue command which uses the DATA line + 0x1 + + + + + DLA + Data Line Active + 2 + 1 + read-only + + + DLA_0 + DATA Line Inactive + 0 + + + DLA_1 + DATA Line Active + 0x1 + + + + + SDSTB + SD Clock Stable + 3 + 1 + read-only + + + SDSTB_0 + Clock is changing frequency and not stable. + 0 + + + SDSTB_1 + Clock is stable. + 0x1 + + + + + IPGOFF + IPG_CLK Gated Off Internally + 4 + 1 + read-only + + + IPGOFF_0 + IPG_CLK is active. + 0 + + + IPGOFF_1 + IPG_CLK is gated off. + 0x1 + + + + + HCKOFF + HCLK Gated Off Internally + 5 + 1 + read-only + + + HCKOFF_0 + HCLK is active. + 0 + + + HCKOFF_1 + HCLK is gated off. + 0x1 + + + + + PEROFF + IPG_PERCLK Gated Off Internally + 6 + 1 + read-only + + + PEROFF_0 + IPG_PERCLK is active. + 0 + + + PEROFF_1 + IPG_PERCLK is gated off. + 0x1 + + + + + SDOFF + SD Clock Gated Off Internally + 7 + 1 + read-only + + + SDOFF_0 + SD Clock is active. + 0 + + + SDOFF_1 + SD Clock is gated off. + 0x1 + + + + + WTA + Write Transfer Active + 8 + 1 + read-only + + + WTA_0 + No valid data + 0 + + + WTA_1 + Transferring data + 0x1 + + + + + RTA + Read Transfer Active + 9 + 1 + read-only + + + RTA_0 + No valid data + 0 + + + RTA_1 + Transferring data + 0x1 + + + + + BWEN + Buffer Write Enable + 10 + 1 + read-only + + + BWEN_0 + Write disable + 0 + + + BWEN_1 + Write enable + 0x1 + + + + + BREN + Buffer Read Enable + 11 + 1 + read-only + + + BREN_0 + Read disable + 0 + + + BREN_1 + Read enable + 0x1 + + + + + RTR + Re-Tuning Request (only for SD3.0 SDR104 mode) + 12 + 1 + read-only + + + RTR_0 + Fixed or well tuned sampling clock + 0 + + + RTR_1 + Sampling clock needs re-tuning + 0x1 + + + + + TSCD + Tape Select Change Done + 15 + 1 + read-only + + + TSCD_0 + Delay cell select change is not finished. + 0 + + + TSCD_1 + Delay cell select change is finished. + 0x1 + + + + + CINST + Card Inserted + 16 + 1 + read-only + + + CINST_0 + Power on Reset or No Card + 0 + + + CINST_1 + Card Inserted + 0x1 + + + + + CDPL + Card Detect Pin Level + 18 + 1 + read-only + + + CDPL_0 + No card present (CD_B = 1) + 0 + + + CDPL_1 + Card present (CD_B = 0) + 0x1 + + + + + WPSPL + Write Protect Switch Pin Level + 19 + 1 + read-only + + + WPSPL_0 + Write protected (WP = 1) + 0 + + + WPSPL_1 + Write enabled (WP = 0) + 0x1 + + + + + CLSL + CMD Line Signal Level + 23 + 1 + read-only + + + DLSL + DATA[7:0] Line Signal Level + 24 + 8 + read-only + + + + + PROT_CTRL + Protocol Control + 0x28 + 32 + read-write + 0x8800020 + 0xFFFFFFFF + + + LCTL + LED Control + 0 + 1 + read-write + + + LCTL_0 + LED off + 0 + + + LCTL_1 + LED on + 0x1 + + + + + DTW + Data Transfer Width + 1 + 2 + read-write + + + DTW_0 + 1-bit mode + 0 + + + DTW_1 + 4-bit mode + 0x1 + + + DTW_2 + 8-bit mode + 0x2 + + + + + D3CD + DATA3 as Card Detection Pin + 3 + 1 + read-write + + + D3CD_0 + DATA3 does not monitor Card Insertion + 0 + + + D3CD_1 + DATA3 as Card Detection Pin + 0x1 + + + + + EMODE + Endian Mode + 4 + 2 + read-write + + + EMODE_0 + Big Endian Mode + 0 + + + EMODE_1 + Half Word Big Endian Mode + 0x1 + + + EMODE_2 + Little Endian Mode + 0x2 + + + + + CDTL + Card Detect Test Level + 6 + 1 + read-write + + + CDTL_0 + Card Detect Test Level is 0, no card inserted + 0 + + + CDTL_1 + Card Detect Test Level is 1, card inserted + 0x1 + + + + + CDSS + Card Detect Signal Selection + 7 + 1 + read-write + + + CDSS_0 + Card Detection Level is selected (for normal purpose). + 0 + + + CDSS_1 + Card Detection Test Level is selected (for test purpose). + 0x1 + + + + + DMASEL + DMA Select + 8 + 2 + read-write + + + DMASEL_0 + No DMA or Simple DMA is selected + 0 + + + DMASEL_1 + ADMA1 is selected + 0x1 + + + DMASEL_2 + ADMA2 is selected + 0x2 + + + + + SABGREQ + Stop At Block Gap Request + 16 + 1 + read-write + + + SABGREQ_0 + Transfer + 0 + + + SABGREQ_1 + Stop + 0x1 + + + + + CREQ + Continue Request + 17 + 1 + read-write + + + CREQ_0 + No effect + 0 + + + CREQ_1 + Restart + 0x1 + + + + + RWCTL + Read Wait Control + 18 + 1 + read-write + + + RWCTL_0 + Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + 0 + + + RWCTL_1 + Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + 0x1 + + + + + IABG + Interrupt At Block Gap + 19 + 1 + read-write + + + IABG_0 + Disabled + 0 + + + IABG_1 + Enabled + 0x1 + + + + + RD_DONE_NO_8CLK + Read done no 8 clock: According to the SD/MMC spec, for read data transaction, 8 clocks are needed after the end bit of the last data block + 20 + 1 + read-write + + + WECINT + Wakeup Event Enable On Card Interrupt + 24 + 1 + read-write + + + WECINT_0 + Disable + 0 + + + WECINT_1 + Enable + 0x1 + + + + + WECINS + Wakeup Event Enable On SD Card Insertion + 25 + 1 + read-write + + + WECINS_0 + Disable + 0 + + + WECINS_1 + Enable + 0x1 + + + + + WECRM + Wakeup Event Enable On SD Card Removal + 26 + 1 + read-write + + + WECRM_0 + Disable + 0 + + + WECRM_1 + Enable + 0x1 + + + + + BURST_LEN_EN + BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + 27 + 3 + read-write + + + BURST_LEN_EN_1 + Burst length is enabled for INCR + #xx1 + + + + + NON_EXACT_BLK_RD + Current block read is non-exact block read. It is only used for SDIO. + 30 + 1 + read-write + + + NON_EXACT_BLK_RD_0 + The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + 0 + + + NON_EXACT_BLK_RD_1 + The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + 0x1 + + + + + + + SYS_CTRL + System Control + 0x2C + 32 + read-write + 0x8080800F + 0xFFFFFFFF + + + DVS + Divisor + 4 + 4 + read-write + + + DVS_0 + Divide-by-1 + 0 + + + DVS_1 + Divide-by-2 + 0x1 + + + DVS_14 + Divide-by-15 + 0xE + + + DVS_15 + Divide-by-16 + 0xF + + + + + SDCLKFS + SDCLK Frequency Select + 8 + 8 + read-write + + + DTOCV + Data Timeout Counter Value + 16 + 4 + read-write + + + DTOCV_0 + SDCLK x 2 14 + 0 + + + DTOCV_1 + SDCLK x 2 15 + 0x1 + + + DTOCV_14 + SDCLK x 2 28 + 0xE + + + DTOCV_15 + SDCLK x 2 29 + 0xF + + + + + IPP_RST_N + This register's value will be output to CARD from pad directly for hardware reset of the card if the card supports this feature + 23 + 1 + read-write + + + RSTA + Software Reset For ALL + 24 + 1 + read-write + + + RSTA_0 + No Reset + 0 + + + RSTA_1 + Reset + 0x1 + + + + + RSTC + Software Reset For CMD Line + 25 + 1 + read-write + + + RSTC_0 + No Reset + 0 + + + RSTC_1 + Reset + 0x1 + + + + + RSTD + Software Reset For DATA Line + 26 + 1 + read-write + + + RSTD_0 + No Reset + 0 + + + RSTD_1 + Reset + 0x1 + + + + + INITA + Initialization Active + 27 + 1 + read-write + + + RSTT + Reset Tuning + 28 + 1 + read-write + + + + + INT_STATUS + Interrupt Status + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + CC + Command Complete + 0 + 1 + read-write + oneToClear + + + CC_0 + Command not complete + 0 + + + CC_1 + Command complete + 0x1 + + + + + TC + Transfer Complete + 1 + 1 + read-write + oneToClear + + + TC_0 + Transfer not complete + 0 + + + TC_1 + Transfer complete + 0x1 + + + + + BGE + Block Gap Event + 2 + 1 + read-write + oneToClear + + + BGE_0 + No block gap event + 0 + + + BGE_1 + Transaction stopped at block gap + 0x1 + + + + + DINT + DMA Interrupt + 3 + 1 + read-write + oneToClear + + + DINT_0 + No DMA Interrupt + 0 + + + DINT_1 + DMA Interrupt is generated + 0x1 + + + + + BWR + Buffer Write Ready + 4 + 1 + read-write + oneToClear + + + BWR_0 + Not ready to write buffer + 0 + + + BWR_1 + Ready to write buffer: + 0x1 + + + + + BRR + Buffer Read Ready + 5 + 1 + read-write + oneToClear + + + BRR_0 + Not ready to read buffer + 0 + + + BRR_1 + Ready to read buffer + 0x1 + + + + + CINS + Card Insertion + 6 + 1 + read-write + oneToClear + + + CINS_0 + Card state unstable or removed + 0 + + + CINS_1 + Card inserted + 0x1 + + + + + CRM + Card Removal + 7 + 1 + read-write + oneToClear + + + CRM_0 + Card state unstable or inserted + 0 + + + CRM_1 + Card removed + 0x1 + + + + + CINT + Card Interrupt + 8 + 1 + read-write + oneToClear + + + CINT_0 + No Card Interrupt + 0 + + + CINT_1 + Generate Card Interrupt + 0x1 + + + + + RTE + Re-Tuning Event: (only for SD3.0 SDR104 mode) + 12 + 1 + read-write + oneToClear + + + RTE_0 + Re-Tuning is not required + 0 + + + RTE_1 + Re-Tuning should be performed + 0x1 + + + + + TP + Tuning Pass:(only for SD3.0 SDR104 mode) + 14 + 1 + read-write + oneToClear + + + CTOE + Command Timeout Error + 16 + 1 + read-write + oneToClear + + + CTOE_0 + No Error + 0 + + + CTOE_1 + Time out + 0x1 + + + + + CCE + Command CRC Error + 17 + 1 + read-write + oneToClear + + + CCE_0 + No Error + 0 + + + CCE_1 + CRC Error Generated. + 0x1 + + + + + CEBE + Command End Bit Error + 18 + 1 + read-write + oneToClear + + + CEBE_0 + No Error + 0 + + + CEBE_1 + End Bit Error Generated + 0x1 + + + + + CIE + Command Index Error + 19 + 1 + read-write + oneToClear + + + CIE_0 + No Error + 0 + + + CIE_1 + Error + 0x1 + + + + + DTOE + Data Timeout Error + 20 + 1 + read-write + oneToClear + + + DTOE_0 + No Error + 0 + + + DTOE_1 + Time out + 0x1 + + + + + DCE + Data CRC Error + 21 + 1 + read-write + oneToClear + + + DCE_0 + No Error + 0 + + + DCE_1 + Error + 0x1 + + + + + DEBE + Data End Bit Error + 22 + 1 + read-write + oneToClear + + + DEBE_0 + No Error + 0 + + + DEBE_1 + Error + 0x1 + + + + + AC12E + Auto CMD12 Error + 24 + 1 + read-write + oneToClear + + + AC12E_0 + No Error + 0 + + + AC12E_1 + Error + 0x1 + + + + + TNE + Tuning Error: (only for SD3.0 SDR104 mode) + 26 + 1 + read-write + oneToClear + + + DMAE + DMA Error + 28 + 1 + read-write + oneToClear + + + DMAE_0 + No Error + 0 + + + DMAE_1 + Error + 0x1 + + + + + + + INT_STATUS_EN + Interrupt Status Enable + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCSEN + Command Complete Status Enable + 0 + 1 + read-write + + + CCSEN_0 + Masked + 0 + + + CCSEN_1 + Enabled + 0x1 + + + + + TCSEN + Transfer Complete Status Enable + 1 + 1 + read-write + + + TCSEN_0 + Masked + 0 + + + TCSEN_1 + Enabled + 0x1 + + + + + BGESEN + Block Gap Event Status Enable + 2 + 1 + read-write + + + BGESEN_0 + Masked + 0 + + + BGESEN_1 + Enabled + 0x1 + + + + + DINTSEN + DMA Interrupt Status Enable + 3 + 1 + read-write + + + DINTSEN_0 + Masked + 0 + + + DINTSEN_1 + Enabled + 0x1 + + + + + BWRSEN + Buffer Write Ready Status Enable + 4 + 1 + read-write + + + BWRSEN_0 + Masked + 0 + + + BWRSEN_1 + Enabled + 0x1 + + + + + BRRSEN + Buffer Read Ready Status Enable + 5 + 1 + read-write + + + BRRSEN_0 + Masked + 0 + + + BRRSEN_1 + Enabled + 0x1 + + + + + CINSSEN + Card Insertion Status Enable + 6 + 1 + read-write + + + CINSSEN_0 + Masked + 0 + + + CINSSEN_1 + Enabled + 0x1 + + + + + CRMSEN + Card Removal Status Enable + 7 + 1 + read-write + + + CRMSEN_0 + Masked + 0 + + + CRMSEN_1 + Enabled + 0x1 + + + + + CINTSEN + Card Interrupt Status Enable + 8 + 1 + read-write + + + CINTSEN_0 + Masked + 0 + + + CINTSEN_1 + Enabled + 0x1 + + + + + RTESEN + Re-Tuning Event Status Enable + 12 + 1 + read-write + + + RTESEN_0 + Masked + 0 + + + RTESEN_1 + Enabled + 0x1 + + + + + TPSEN + Tuning Pass Status Enable + 14 + 1 + read-write + + + TPSEN_0 + Masked + 0 + + + TPSEN_1 + Enabled + 0x1 + + + + + CTOESEN + Command Timeout Error Status Enable + 16 + 1 + read-write + + + CTOESEN_0 + Masked + 0 + + + CTOESEN_1 + Enabled + 0x1 + + + + + CCESEN + Command CRC Error Status Enable + 17 + 1 + read-write + + + CCESEN_0 + Masked + 0 + + + CCESEN_1 + Enabled + 0x1 + + + + + CEBESEN + Command End Bit Error Status Enable + 18 + 1 + read-write + + + CEBESEN_0 + Masked + 0 + + + CEBESEN_1 + Enabled + 0x1 + + + + + CIESEN + Command Index Error Status Enable + 19 + 1 + read-write + + + CIESEN_0 + Masked + 0 + + + CIESEN_1 + Enabled + 0x1 + + + + + DTOESEN + Data Timeout Error Status Enable + 20 + 1 + read-write + + + DTOESEN_0 + Masked + 0 + + + DTOESEN_1 + Enabled + 0x1 + + + + + DCESEN + Data CRC Error Status Enable + 21 + 1 + read-write + + + DCESEN_0 + Masked + 0 + + + DCESEN_1 + Enabled + 0x1 + + + + + DEBESEN + Data End Bit Error Status Enable + 22 + 1 + read-write + + + DEBESEN_0 + Masked + 0 + + + DEBESEN_1 + Enabled + 0x1 + + + + + AC12ESEN + Auto CMD12 Error Status Enable + 24 + 1 + read-write + + + AC12ESEN_0 + Masked + 0 + + + AC12ESEN_1 + Enabled + 0x1 + + + + + TNESEN + Tuning Error Status Enable + 26 + 1 + read-write + + + TNESEN_0 + Masked + 0 + + + TNESEN_1 + Enabled + 0x1 + + + + + DMAESEN + DMA Error Status Enable + 28 + 1 + read-write + + + DMAESEN_0 + Masked + 0 + + + DMAESEN_1 + Enabled + 0x1 + + + + + + + INT_SIGNAL_EN + Interrupt Signal Enable + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCIEN + Command Complete Interrupt Enable + 0 + 1 + read-write + + + CCIEN_0 + Masked + 0 + + + CCIEN_1 + Enabled + 0x1 + + + + + TCIEN + Transfer Complete Interrupt Enable + 1 + 1 + read-write + + + TCIEN_0 + Masked + 0 + + + TCIEN_1 + Enabled + 0x1 + + + + + BGEIEN + Block Gap Event Interrupt Enable + 2 + 1 + read-write + + + BGEIEN_0 + Masked + 0 + + + BGEIEN_1 + Enabled + 0x1 + + + + + DINTIEN + DMA Interrupt Enable + 3 + 1 + read-write + + + DINTIEN_0 + Masked + 0 + + + DINTIEN_1 + Enabled + 0x1 + + + + + BWRIEN + Buffer Write Ready Interrupt Enable + 4 + 1 + read-write + + + BWRIEN_0 + Masked + 0 + + + BWRIEN_1 + Enabled + 0x1 + + + + + BRRIEN + Buffer Read Ready Interrupt Enable + 5 + 1 + read-write + + + BRRIEN_0 + Masked + 0 + + + BRRIEN_1 + Enabled + 0x1 + + + + + CINSIEN + Card Insertion Interrupt Enable + 6 + 1 + read-write + + + CINSIEN_0 + Masked + 0 + + + CINSIEN_1 + Enabled + 0x1 + + + + + CRMIEN + Card Removal Interrupt Enable + 7 + 1 + read-write + + + CRMIEN_0 + Masked + 0 + + + CRMIEN_1 + Enabled + 0x1 + + + + + CINTIEN + Card Interrupt Interrupt Enable + 8 + 1 + read-write + + + CINTIEN_0 + Masked + 0 + + + CINTIEN_1 + Enabled + 0x1 + + + + + RTEIEN + Re-Tuning Event Interrupt Enable + 12 + 1 + read-write + + + RTEIEN_0 + Masked + 0 + + + RTEIEN_1 + Enabled + 0x1 + + + + + TPIEN + Tuning Pass Interrupt Enable + 14 + 1 + read-write + + + TPIEN_0 + Masked + 0 + + + TPIEN_1 + Enabled + 0x1 + + + + + CTOEIEN + Command Timeout Error Interrupt Enable + 16 + 1 + read-write + + + CTOEIEN_0 + Masked + 0 + + + CTOEIEN_1 + Enabled + 0x1 + + + + + CCEIEN + Command CRC Error Interrupt Enable + 17 + 1 + read-write + + + CCEIEN_0 + Masked + 0 + + + CCEIEN_1 + Enabled + 0x1 + + + + + CEBEIEN + Command End Bit Error Interrupt Enable + 18 + 1 + read-write + + + CEBEIEN_0 + Masked + 0 + + + CEBEIEN_1 + Enabled + 0x1 + + + + + CIEIEN + Command Index Error Interrupt Enable + 19 + 1 + read-write + + + CIEIEN_0 + Masked + 0 + + + CIEIEN_1 + Enabled + 0x1 + + + + + DTOEIEN + Data Timeout Error Interrupt Enable + 20 + 1 + read-write + + + DTOEIEN_0 + Masked + 0 + + + DTOEIEN_1 + Enabled + 0x1 + + + + + DCEIEN + Data CRC Error Interrupt Enable + 21 + 1 + read-write + + + DCEIEN_0 + Masked + 0 + + + DCEIEN_1 + Enabled + 0x1 + + + + + DEBEIEN + Data End Bit Error Interrupt Enable + 22 + 1 + read-write + + + DEBEIEN_0 + Masked + 0 + + + DEBEIEN_1 + Enabled + 0x1 + + + + + AC12EIEN + Auto CMD12 Error Interrupt Enable + 24 + 1 + read-write + + + AC12EIEN_0 + Masked + 0 + + + AC12EIEN_1 + Enabled + 0x1 + + + + + TNEIEN + Tuning Error Interrupt Enable + 26 + 1 + read-write + + + TNEIEN_0 + Masked + 0 + + + TNEIEN_1 + Enabled + 0x1 + + + + + DMAEIEN + DMA Error Interrupt Enable + 28 + 1 + read-write + + + DMAEIEN_0 + Masked + 0 + + + DMAEIEN_1 + Enable + 0x1 + + + + + + + AUTOCMD12_ERR_STATUS + Auto CMD12 Error Status + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + AC12NE + Auto CMD12 Not Executed + 0 + 1 + read-only + + + AC12NE_0 + Executed + 0 + + + AC12NE_1 + Not executed + 0x1 + + + + + AC12TOE + Auto CMD12 / 23 Timeout Error + 1 + 1 + read-only + + + AC12TOE_0 + No error + 0 + + + AC12TOE_1 + Time out + 0x1 + + + + + AC12EBE + Auto CMD12 / 23 End Bit Error + 2 + 1 + read-only + + + AC12EBE_0 + No error + 0 + + + AC12EBE_1 + End Bit Error Generated + 0x1 + + + + + AC12CE + Auto CMD12 / 23 CRC Error + 3 + 1 + read-only + + + AC12CE_0 + No CRC error + 0 + + + AC12CE_1 + CRC Error Met in Auto CMD12/23 Response + 0x1 + + + + + AC12IE + Auto CMD12 / 23 Index Error + 4 + 1 + read-only + + + AC12IE_0 + No error + 0 + + + AC12IE_1 + Error, the CMD index in response is not CMD12/23 + 0x1 + + + + + CNIBAC12E + Command Not Issued By Auto CMD12 Error + 7 + 1 + read-only + + + CNIBAC12E_0 + No error + 0 + + + CNIBAC12E_1 + Not Issued + 0x1 + + + + + EXECUTE_TUNING + Execute Tuning + 22 + 1 + read-write + + + SMP_CLK_SEL + Sample Clock Select + 23 + 1 + read-write + + + SMP_CLK_SEL_0 + Fixed clock is used to sample data + 0 + + + SMP_CLK_SEL_1 + Tuned clock is used to sample data + 0x1 + + + + + + + HOST_CTRL_CAP + Host Controller Capabilities + 0x40 + 32 + read-write + 0x7F3B407 + 0xFFFFFFFF + + + SDR50_SUPPORT + SDR50 support + 0 + 1 + read-only + + + SDR104_SUPPORT + SDR104 support + 1 + 1 + read-only + + + DDR50_SUPPORT + DDR50 support + 2 + 1 + read-only + + + TIME_COUNT_RETUNING + Time Counter for Retuning + 8 + 4 + read-write + + + USE_TUNING_SDR50 + Use Tuning for SDR50 + 13 + 1 + read-write + + + USE_TUNING_SDR50_0 + SDR does not require tuning + 0 + + + USE_TUNING_SDR50_1 + SDR50 requires tuning + 0x1 + + + + + RETUNING_MODE + Retuning Mode + 14 + 2 + read-only + + + RETUNING_MODE_0 + Mode 1 + 0 + + + RETUNING_MODE_1 + Mode 2 + 0x1 + + + RETUNING_MODE_2 + Mode 3 + 0x2 + + + + + MBL + Max Block Length + 16 + 3 + read-only + + + MBL_0 + 512 bytes + 0 + + + MBL_1 + 1024 bytes + 0x1 + + + MBL_2 + 2048 bytes + 0x2 + + + MBL_3 + 4096 bytes + 0x3 + + + + + ADMAS + ADMA Support + 20 + 1 + read-only + + + ADMAS_0 + Advanced DMA Not supported + 0 + + + ADMAS_1 + Advanced DMA Supported + 0x1 + + + + + HSS + High Speed Support + 21 + 1 + read-only + + + HSS_0 + High Speed Not Supported + 0 + + + HSS_1 + High Speed Supported + 0x1 + + + + + DMAS + DMA Support + 22 + 1 + read-only + + + DMAS_0 + DMA not supported + 0 + + + DMAS_1 + DMA Supported + 0x1 + + + + + SRS + Suspend / Resume Support + 23 + 1 + read-only + + + SRS_0 + Not supported + 0 + + + SRS_1 + Supported + 0x1 + + + + + VS33 + Voltage Support 3.3V + 24 + 1 + read-only + + + VS33_0 + 3.3V not supported + 0 + + + VS33_1 + 3.3V supported + 0x1 + + + + + VS30 + Voltage Support 3.0 V + 25 + 1 + read-only + + + VS30_0 + 3.0V not supported + 0 + + + VS30_1 + 3.0V supported + 0x1 + + + + + VS18 + Voltage Support 1.8 V + 26 + 1 + read-only + + + VS18_0 + 1.8V not supported + 0 + + + VS18_1 + 1.8V supported + 0x1 + + + + + + + WTMK_LVL + Watermark Level + 0x44 + 32 + read-write + 0x8100810 + 0xFFFFFFFF + + + RD_WML + Read Watermark Level + 0 + 8 + read-write + + + RD_BRST_LEN + Read Burst Length Due to system restriction, the actual burst length may not exceed 16. + 8 + 5 + read-write + + + WR_WML + Write Watermark Level + 16 + 8 + read-write + + + WR_BRST_LEN + Write Burst Length Due to system restriction, the actual burst length may not exceed 16. + 24 + 5 + read-write + + + + + MIX_CTRL + Mixer Control + 0x48 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + DMAEN + DMA Enable + 0 + 1 + read-write + + + DMAEN_0 + Disable + 0 + + + DMAEN_1 + Enable + 0x1 + + + + + BCEN + Block Count Enable + 1 + 1 + read-write + + + BCEN_0 + Disable + 0 + + + BCEN_1 + Enable + 0x1 + + + + + AC12EN + Auto CMD12 Enable + 2 + 1 + read-write + + + AC12EN_0 + Disable + 0 + + + AC12EN_1 + Enable + 0x1 + + + + + DDR_EN + Dual Data Rate mode selection + 3 + 1 + read-write + + + DTDSEL + Data Transfer Direction Select + 4 + 1 + read-write + + + DTDSEL_0 + Write (Host to Card) + 0 + + + DTDSEL_1 + Read (Card to Host) + 0x1 + + + + + MSBSEL + Multi / Single Block Select + 5 + 1 + read-write + + + MSBSEL_0 + Single Block + 0 + + + MSBSEL_1 + Multiple Blocks + 0x1 + + + + + NIBBLE_POS + In DDR 4-bit mode nibble position indictation + 6 + 1 + read-write + + + AC23EN + Auto CMD23 Enable + 7 + 1 + read-write + + + EXE_TUNE + Execute Tuning: (Only used for SD3.0, SDR104 mode) + 22 + 1 + read-write + + + EXE_TUNE_0 + Not Tuned or Tuning Completed + 0 + + + EXE_TUNE_1 + Execute Tuning + 0x1 + + + + + SMP_CLK_SEL + When STD_TUNING_EN is 0, this bit is used to select Tuned clock or Fixed clock to sample data / cmd (Only used for SD3 + 23 + 1 + read-write + + + SMP_CLK_SEL_0 + Fixed clock is used to sample data / cmd + 0 + + + SMP_CLK_SEL_1 + Tuned clock is used to sample data / cmd + 0x1 + + + + + AUTO_TUNE_EN + Auto Tuning Enable (Only used for SD3.0, SDR104 mode) + 24 + 1 + read-write + + + AUTO_TUNE_EN_0 + Disable auto tuning + 0 + + + AUTO_TUNE_EN_1 + Enable auto tuning + 0x1 + + + + + FBCLK_SEL + Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode) + 25 + 1 + read-write + + + FBCLK_SEL_0 + Feedback clock comes from the loopback CLK + 0 + + + FBCLK_SEL_1 + Feedback clock comes from the ipp_card_clk_out + 0x1 + + + + + HS400_MODE + Enable HS400 Mode + 26 + 1 + read-write + + + + + FORCE_EVENT + Force Event + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FEVTAC12NE + Force Event Auto Command 12 Not Executed + 0 + 1 + write-only + + + FEVTAC12TOE + Force Event Auto Command 12 Time Out Error + 1 + 1 + write-only + + + FEVTAC12CE + Force Event Auto Command 12 CRC Error + 2 + 1 + write-only + + + FEVTAC12EBE + Force Event Auto Command 12 End Bit Error + 3 + 1 + write-only + + + FEVTAC12IE + Force Event Auto Command 12 Index Error + 4 + 1 + write-only + + + FEVTCNIBAC12E + Force Event Command Not Executed By Auto Command 12 Error + 7 + 1 + write-only + + + FEVTCTOE + Force Event Command Time Out Error + 16 + 1 + write-only + + + FEVTCCE + Force Event Command CRC Error + 17 + 1 + write-only + + + FEVTCEBE + Force Event Command End Bit Error + 18 + 1 + write-only + + + FEVTCIE + Force Event Command Index Error + 19 + 1 + write-only + + + FEVTDTOE + Force Event Data Time Out Error + 20 + 1 + write-only + + + FEVTDCE + Force Event Data CRC Error + 21 + 1 + write-only + + + FEVTDEBE + Force Event Data End Bit Error + 22 + 1 + write-only + + + FEVTAC12E + Force Event Auto Command 12 Error + 24 + 1 + write-only + + + FEVTTNE + Force Tuning Error + 26 + 1 + write-only + + + FEVTDMAE + Force Event DMA Error + 28 + 1 + write-only + + + FEVTCINT + Force Event Card Interrupt + 31 + 1 + write-only + + + + + ADMA_ERR_STATUS + ADMA Error Status Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADMAES + ADMA Error State (when ADMA Error is occurred) + 0 + 2 + read-only + + + ADMALME + ADMA Length Mismatch Error + 2 + 1 + read-only + + + ADMALME_0 + No Error + 0 + + + ADMALME_1 + Error + 0x1 + + + + + ADMADCE + ADMA Descritor Error + 3 + 1 + read-only + + + ADMADCE_0 + No Error + 0 + + + ADMADCE_1 + Error + 0x1 + + + + + + + ADMA_SYS_ADDR + ADMA System Address + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADS_ADDR + ADMA System Address + 2 + 30 + read-write + + + + + DLL_CTRL + DLL (Delay Line) Control + 0x60 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + DLL_CTRL_ENABLE + Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL + 0 + 1 + read-write + + + DLL_CTRL_RESET + Setting this bit to 1 force a reset on DLL + 1 + 1 + read-write + + + DLL_CTRL_SLV_FORCE_UPD + Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately + 2 + 1 + read-write + + + DLL_CTRL_SLV_DLY_TARGET0 + The delay target for the uSDHC loopback read clock can be programmed in 1/16th increments of an ref_clock half-period + 3 + 4 + read-write + + + DLL_CTRL_GATE_UPDATE + Set this bit to 1 to prevent the DLL from updating (since when clock_in exists, glitches may appear during DLL updates) + 7 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE + Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to disable manual override + 8 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE_VAL + When SLV_OVERRIDE = 1 This field is used to select 1 of 128 physical taps manually + 9 + 7 + read-write + + + DLL_CTRL_SLV_DLY_TARGET1 + Refer to DLL_CTRL_SLV_DLY_TARGET0 below. + 16 + 3 + read-write + + + DLL_CTRL_SLV_UPDATE_INT + Slave delay line update interval + 20 + 8 + read-write + + + DLL_CTRL_REF_UPDATE_INT + DLL control loop update interval + 28 + 4 + read-write + + + + + DLL_STATUS + DLL Status + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + DLL_STS_SLV_LOCK + Slave delay-line lock status + 0 + 1 + read-only + + + DLL_STS_REF_LOCK + Reference DLL lock status + 1 + 1 + read-only + + + DLL_STS_SLV_SEL + Slave delay line select status + 2 + 7 + read-only + + + DLL_STS_REF_SEL + Reference delay line select taps. This is encoded by 7 bits for 127 taps. + 9 + 7 + read-only + + + + + CLK_TUNE_CTRL_STATUS + CLK Tuning Control and Status + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLY_CELL_SET_POST + Set the number of delay cells on the feedback clock between CLK_OUT and CLK_POST. + 0 + 4 + read-write + + + DLY_CELL_SET_OUT + Set the number of delay cells on the feedback clock between CLK_PRE and CLK_OUT. + 4 + 4 + read-write + + + DLY_CELL_SET_PRE + Set the number of delay cells on the feedback clock between the feedback clock and CLK_PRE. + 8 + 7 + read-write + + + NXT_ERR + NXT error which means the number of delay cells added on the feedback clock is too large + 15 + 1 + read-only + + + TAP_SEL_POST + Reflect the number of delay cells added on the feedback clock between CLK_OUT and CLK_POST. + 16 + 4 + read-only + + + TAP_SEL_OUT + Reflect the number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT. + 20 + 4 + read-only + + + TAP_SEL_PRE + Reflects the number of delay cells added on the feedback clock between the feedback clock and CLK_PRE + 24 + 7 + read-only + + + PRE_ERR + PRE error which means the number of delay cells added on the feedback clock is too small + 31 + 1 + read-only + + + + + STROBE_DLL_CTRL + Strobe DLL Control + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + STROBE_DLL_CTRL_ENABLE + Strobe DLL Control Enable + 0 + 1 + read-write + + + STROBE_DLL_CTRL_RESET + Strobe DLL Control Reset + 1 + 1 + read-write + + + STROBE_DLL_CTRL_SLV_FORCE_UPD + Strobe DLL Control Slave Force Updated + 2 + 1 + read-write + + + STROBE_DLL_CTRL_SLV_DLY_TARGET + Strobe DLL Control Slave Delay Target + 3 + 3 + read-write + + + STROBE_DLL_CTRL_GATE_UPDATE_0 + Strobe DLL Control Gate Update + 6 + 1 + read-write + + + STROBE_DLL_CTRL_GATE_UPDATE_1 + Strobe DLL Control Gate Update + 7 + 1 + read-write + + + STROBE_DLL_CTRL_SLV_OVERRIDE + Strobe DLL Control Slave Override + 8 + 1 + read-write + + + STROBE_DLL_CTRL_SLV_OVERRIDE_VAL + Strobe DLL Control Slave Override Value + 9 + 7 + read-write + + + STROBE_DLL_CTRL_SLV_UPDATE_INT + Strobe DLL Control Slave Update Interval + 20 + 8 + read-write + + + STROBE_DLL_CTRL_REF_UPDATE_INT + Strobe DLL Control Reference Update Interval + 28 + 4 + read-write + + + + + STROBE_DLL_STATUS + Strobe DLL Status + 0x74 + 32 + read-only + 0 + 0xFFFFFFFF + + + STROBE_DLL_STS_SLV_LOCK + Strobe DLL Status Slave Lock + 0 + 1 + read-only + + + STROBE_DLL_STS_REF_LOCK + Strobe DLL Status Reference Lock + 1 + 1 + read-only + + + STROBE_DLL_STS_SLV_SEL + Strobe DLL Status Slave Select + 2 + 7 + read-only + + + STROBE_DLL_STS_REF_SEL + Strobe DLL Status Reference Select + 9 + 7 + read-only + + + + + VEND_SPEC + Vendor Specific Register + 0xC0 + 32 + read-write + 0x20007809 + 0xFFFFFFFF + + + EXT_DMA_EN + External DMA Request Enable + 0 + 1 + read-write + + + EXT_DMA_EN_0 + In any scenario, uSDHC does not send out external DMA request. + 0 + + + EXT_DMA_EN_1 + When internal DMA is not active, the external DMA request will be sent out. + 0x1 + + + + + VSELECT + Voltage Selection + 1 + 1 + read-write + + + VSELECT_0 + Change the voltage to high voltage range, around 3.0 V + 0 + + + VSELECT_1 + Change the voltage to low voltage range, around 1.8 V + 0x1 + + + + + CONFLICT_CHK_EN + Conflict check enable. + 2 + 1 + read-write + + + CONFLICT_CHK_EN_0 + Conflict check disable + 0 + + + CONFLICT_CHK_EN_1 + Conflict check enable + 0x1 + + + + + AC12_WR_CHKBUSY_EN + Check busy enable after auto CMD12 for write data packet + 3 + 1 + read-write + + + AC12_WR_CHKBUSY_EN_0 + Do not check busy after auto CMD12 for write data packet + 0 + + + AC12_WR_CHKBUSY_EN_1 + Check busy after auto CMD12 for write data packet + 0x1 + + + + + DAT3_CD_POL + Only for debug. Polarity of DATA3 pin when it is used as card detection. + 4 + 1 + read-write + + + DAT3_CD_POL_0 + Card detected when DATA3 is high. + 0 + + + DAT3_CD_POL_1 + Card detected when DATA3 is low. + 0x1 + + + + + CD_POL + Only for debug. Polarity of the CD_B pin: + 5 + 1 + read-write + + + CD_POL_0 + CD_B pin is low active. + 0 + + + CD_POL_1 + CD_B pin is high active. + 0x1 + + + + + WP_POL + Only for debug. Polarity of the WP pin: + 6 + 1 + read-write + + + WP_POL_0 + WP pin is high active. + 0 + + + WP_POL_1 + WP pin is low active. + 0x1 + + + + + CLKONJ_IN_ABORT + Only for debug. Force CLK output active when sending Abort command: + 7 + 1 + read-write + + + CLKONJ_IN_ABORT_0 + The CLK output is active when sending abort command while data is transmitting even if the internal FIFO is full (for read) or empty (for write). + 0 + + + CLKONJ_IN_ABORT_1 + The CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is full (for read) or empty (for write). + 0x1 + + + + + FRC_SDCLK_ON + Force CLK output active + 8 + 1 + read-write + + + FRC_SDCLK_ON_0 + CLK active or inactive is fully controlled by the hardware. + 0 + + + FRC_SDCLK_ON_1 + Force CLK active. + 0x1 + + + + + IPG_CLK_SOFT_EN + IPG_CLK Software Enable + 11 + 1 + read-write + + + IPG_CLK_SOFT_EN_0 + Gate off the IPG_CLK + 0 + + + IPG_CLK_SOFT_EN_1 + Enable the IPG_CLK + 0x1 + + + + + HCLK_SOFT_EN + AHB Clock Software Enable + 12 + 1 + read-write + + + HCLK_SOFT_EN_0 + Gate off the AHB clock. + 0 + + + HCLK_SOFT_EN_1 + Enable the AHB clock. + 0x1 + + + + + IPG_PERCLK_SOFT_EN + IPG_PERCLK Software Enable + 13 + 1 + read-write + + + IPG_PERCLK_SOFT_EN_0 + Gate off the IPG_PERCLK + 0 + + + IPG_PERCLK_SOFT_EN_1 + Enable the IPG_PERCLK + 0x1 + + + + + CARD_CLK_SOFT_EN + Card Clock Software Enable + 14 + 1 + read-write + + + CARD_CLK_SOFT_EN_0 + Gate off the sd_clk + 0 + + + CARD_CLK_SOFT_EN_1 + Enable the sd_clk + 0x1 + + + + + CRC_CHK_DIS + CRC Check Disable + 15 + 1 + read-write + + + CRC_CHK_DIS_0 + Check CRC16 for every read data packet and check CRC bits for every write data packet + 0 + + + CRC_CHK_DIS_1 + Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + 0x1 + + + + + INT_ST_VAL + Internal State Value + 16 + 8 + read-only + + + CMD_BYTE_EN + Byte access + 31 + 1 + read-write + + + CMD_BYTE_EN_0 + Disable + 0 + + + CMD_BYTE_EN_1 + Enable + 0x1 + + + + + + + MMC_BOOT + MMC Boot Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DTOCV_ACK + Boot ACK time out counter value. + 0 + 4 + read-write + + + DTOCV_ACK_0 + SDCLK x 2^13 + 0 + + + DTOCV_ACK_1 + SDCLK x 2^14 + 0x1 + + + DTOCV_ACK_2 + SDCLK x 2^15 + 0x2 + + + DTOCV_ACK_3 + SDCLK x 2^16 + 0x3 + + + DTOCV_ACK_4 + SDCLK x 2^17 + 0x4 + + + DTOCV_ACK_5 + SDCLK x 2^18 + 0x5 + + + DTOCV_ACK_6 + SDCLK x 2^19 + 0x6 + + + DTOCV_ACK_7 + SDCLK x 2^20 + 0x7 + + + DTOCV_ACK_14 + SDCLK x 2^27 + 0xE + + + DTOCV_ACK_15 + SDCLK x 2^28 + 0xF + + + + + BOOT_ACK + Boot ACK mode select + 4 + 1 + read-write + + + BOOT_ACK_0 + No ack + 0 + + + BOOT_ACK_1 + Ack + 0x1 + + + + + BOOT_MODE + Boot mode select + 5 + 1 + read-write + + + BOOT_MODE_0 + Normal boot + 0 + + + BOOT_MODE_1 + Alternative boot + 0x1 + + + + + BOOT_EN + Boot mode enable + 6 + 1 + read-write + + + BOOT_EN_0 + Fast boot disable + 0 + + + BOOT_EN_1 + Fast boot enable + 0x1 + + + + + AUTO_SABG_EN + During boot, enable auto stop at block gap function + 7 + 1 + read-write + + + DISABLE_TIME_OUT + Disable Time Out + 8 + 1 + read-write + + + DISABLE_TIME_OUT_0 + Enable time out + 0 + + + DISABLE_TIME_OUT_1 + Disable time out + 0x1 + + + + + BOOT_BLK_CNT + The value defines the Stop At Block Gap value of automatic mode + 16 + 16 + read-write + + + + + VEND_SPEC2 + Vendor Specific 2 Register + 0xC8 + 32 + read-write + 0x6 + 0xFFFFFFFF + + + SDR104_TIMING_DIS + Timeout counter test. This bit only uses for debugging. + 0 + 1 + read-write + + + SDR104_TIMING_DIS_0 + The timeout counter for Ncr changes to 80, Ncrc changes to 21. + 0 + + + SDR104_TIMING_DIS_1 + The timeout counter for Ncr changes to 72, Ncrc changes to 15. + 0x1 + + + + + SDR104_OE_DIS + CMD_OE / DATA_OE logic generation test. This bit only uses for debugging. + 1 + 1 + read-write + + + SDR104_OE_DIS_0 + Drive the CMD_OE / DATA_OE for one more clock cycle after the end bit. + 0 + + + SDR104_OE_DIS_1 + Stop to drive the CMD_OE / DATA_OE at once after driving the end bit. + 0x1 + + + + + SDR104_NSD_DIS + Interrupt window after abort command is sent. This bit only uses for debugging. + 2 + 1 + read-write + + + SDR104_NSD_DIS_0 + Enable the interrupt window 9 cycles later after the end of the I/O abort command (or CMD12) is sent. + 0 + + + SDR104_NSD_DIS_1 + Enable the interrupt window 5 cycles later after the end of the I/O abort command (or CMD12) is sent. + 0x1 + + + + + CARD_INT_D3_TEST + Card Interrupt Detection Test + 3 + 1 + read-write + + + CARD_INT_D3_TEST_0 + Check the card interrupt only when DATA3 is high. + 0 + + + CARD_INT_D3_TEST_1 + Check the card interrupt by ignoring the status of DATA3. + 0x1 + + + + + TUNING_8bit_EN + Enable the auto tuning circuit to check the DATA[7:0] + 4 + 1 + read-write + + + TUNING_8bit_EN_0 + Tuning circuit only checks the DATA[3:0]. + 0 + + + TUNING_8bit_EN_1 + Tuning circuit only checks the DATA0. + 0x1 + + + + + TUNING_1bit_EN + Enable the auto tuning circuit to check the DATA0 only + 5 + 1 + read-write + + + TUNING_CMD_EN + Enable the auto tuning circuit to check the CMD line. + 6 + 1 + read-write + + + TUNING_CMD_EN_0 + Auto tuning circuit does not check the CMD line. + 0 + + + TUNING_CMD_EN_1 + Auto tuning circuit checks the CMD line. + 0x1 + + + + + CARD_INT_AUTO_CLR_DIS + Disable the feature to clear the Card interrupt status bit when Card Interrupt status enable bit is cleared + 7 + 1 + read-write + + + CARD_INT_AUTO_CLR_DIS_0 + Card interrupt status bit (CINT) can be cleared when Card Interrupt status enable bit is 0. + 0 + + + CARD_INT_AUTO_CLR_DIS_1 + Card interrupt status bit (CINT) can only be cleared by writting a 1 to CINT bit. + 0x1 + + + + + HS400_WR_CLK_STOP_EN + HS400 Write Clock Stop Enable + 10 + 1 + read-write + + + HS400_RD_CLK_STOP_EN + HS400 Read Clock Stop Enable + 11 + 1 + read-write + + + + + TUNING_CTRL + Tuning Control Register + 0xCC + 32 + read-write + 0x212800 + 0xFFFFFFFF + + + TUNING_START_TAP + The start dealy cell point when send first CMD19 in tuning procedure. + 0 + 8 + read-write + + + TUNING_COUNTER + The MAX repeat CMD19 times in tuning procedure. + 8 + 8 + read-write + + + TUNING_STEP + The increasing delay cell steps in tuning procedure. + 16 + 3 + read-write + + + TUNING_WINDOW + Select data window value for auto tuning + 20 + 3 + read-write + + + STD_TUNING_EN + Standard tuning circuit and procedure enable: This bit is used to enable standard tuning circuit and procedure + 24 + 1 + read-write + + + + + + + uSDHC2 + uSDHC + USDHC + uSDHC2_ + 0x30B50000 + + 0 + 0xD0 + registers + + + USDHC2 + 23 + + + + QuadSPI + QuadSPI + QUADSPI + QuadSPI_ + 0x30BB0000 + + 0 + 0x410 + registers + + + QSPI + 107 + + + + MCR + Module Configuration Register + 0 + 32 + read-write + 0xF4000 + 0xFFFFFFFF + + + SWRSTSD + Software reset for Serial Flash domainPlease keep other fields value when write to SWRSTHD and SWRSTSD These software reset don't reset register setting but only reset internal flip-flops in quadspi controller To remove the reset, need to write 0 to SWRSTHD and SWRSTSD + 0 + 1 + read-write + + + SWRSTSD_0 + No action + 0 + + + SWRSTSD_1 + Serial Flash domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. + 0x1 + + + + + SWRSTHD + Software reset for AHB domainPlease keep other fields value when write to SWRSTHD and SWRSTSD These software reset don't reset register setting but only reset internal flip-flops in quadspi controller To remove the reset, need to write 0 to SWRSTHD and SWRSTSD + 1 + 1 + read-write + + + SWRSTHD_0 + No action + 0 + + + SWRSTHD_1 + AHB domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. + 0x1 + + + + + END_CFG + Defines the endianness of the QSPI module.For more details refer to Byte Ordering Endianess + 2 + 2 + read-write + + + DQS_EN + DQS enable: This field is valid for both SDR and DDR mode + 6 + 1 + read-write + + + DQS_EN_0 + DQS disabled. + 0 + + + DQS_EN_1 + DQS enabled- When enabled, the incoming data is sampled on both the edges of DQS input when QSPI_MCR[DDR_EN] is set, else, on only one edge when QSPI_MCR[DDR_EN] is 0. The QSPI_SMPR[DDR_SMP] values are ignored. + 0x1 + + + + + DDR_EN + DDR mode enable: + 7 + 1 + read-write + + + DDR_EN_0 + 2x and 4x clocks are disabled for SDR instructions only + 0 + + + DDR_EN_1 + 2x and 4x clocks are enabled supports both SDR and DDR instruction. + 0x1 + + + + + CLR_RXF + Clear RX FIFO. Invalidate the RX Buffer. + 10 + 1 + read-write + + + CLR_RXF_0 + No action. + 0 + + + CLR_RXF_1 + Read and write pointers of the RX Buffer are reset to 0. QSPI_RBSR[RDBFL] is reset to 0. + 0x1 + + + + + CLR_TXF + Clear TX FIFO/Buffer. Invalidate the TX Buffer content. + 11 + 1 + read-write + + + CLR_TXF_0 + No action. + 0 + + + CLR_TXF_1 + Read and write pointers of the TX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0. + 0x1 + + + + + MDIS + Module Disable + 14 + 1 + read-write + + + MDIS_0 + Enable QuadSPI clocks. + 0 + + + MDIS_1 + Allow external logic to disable QuadSPI clocks. + 0x1 + + + + + DQS_LOOPBACK_FROM_PAD + This bit should always be set to '1' when DQS_LOOPBACK_EN is set to '1' + 24 + 1 + read-write + + + DQS_LOOPBACK_EN + Quadspi will output serial data strobe signal which will be loopback from pad to sample input flash serial data + 25 + 1 + read-write + + + DQS_PHASE_EN + This bit controls internal DQS output phase + 26 + 1 + read-write + + + + + IPCR + IP Configuration Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDATSZ + IP data transfer size: Defines the data transfer size in bytes of the IP command. + 0 + 16 + read-write + + + PAR_EN + When set, a transaction to two serial flash devices is triggered in parallel mode + 16 + 1 + read-write + + + SEQID + Points to a sequence in the Look-up-table + 24 + 4 + read-write + + + + + FLSHCR + Flash Configuration Register + 0xC + 32 + read-write + 0x303 + 0xFFFFFFFF + + + TCSS + Serial flash CS setup time in terms of serial flash clock cycles + 0 + 4 + read-write + + + TCSH + Serial flash CS hold time in terms of serial flash clock cycles + 8 + 4 + read-write + + + TDH + Serial flash Data In hold time: This helps in meeting the Data In Hold time requirement of a Flash + 16 + 2 + read-write + + + TDH_0 + Data aligned with the posedge of Internal reference clock of QuadSPI + 0 + + + TDH_1 + Data aligned with 2x serial flash half clock + 0x1 + + + + + + + BUF0CR + Buffer0 Configuration Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSTRID + Master ID: The ID of the AHB master associated with BUFFER0 + 0 + 4 + read-write + + + ADATSZ + AHB data transfer size: Defines the data transfer size in 8 bytes of an AHB triggered access to serial flash + 8 + 8 + read-write + + + HP_EN + High Priority Enable: When set, the master associated with this buffer is assigned a priority higher than the rest of the masters + 31 + 1 + read-write + + + + + BUF1CR + Buffer1 Configuration Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSTRID + Master ID: The ID of the AHB master associated with BUFFER1 + 0 + 4 + read-write + + + ADATSZ + AHB data transfer size: Defines the data transfer size in 8 bytes of an AHB triggered access to serial flash + 8 + 8 + read-write + + + + + BUF2CR + Buffer2 Configuration Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSTRID + Master ID: The ID of the AHB master associated with BUFFER2 + 0 + 4 + read-write + + + ADATSZ + AHB data transfer size: Defines the data transfer size in 8 Bytes of an AHB triggered access to serial flash + 8 + 8 + read-write + + + + + BUF3CR + Buffer3 Configuration Register + 0x1C + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + MSTRID + Master ID: The ID of the AHB master associated with BUFFER3 + 0 + 4 + read-write + + + ADATSZ + AHB data transfer size: Defines the data transfer size in 8 Bytes of an AHB triggered access to serial flash + 8 + 8 + read-write + + + ALLMST + All master enable: When set, buffer3 acts as an all-master buffer + 31 + 1 + read-write + + + + + BFGENCR + Buffer Generic Configuration Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEQID + Points to a sequence in the Look-up-table + 12 + 4 + read-write + + + PAR_EN + When set, a transaction to two serial flash devices is triggered in parallel mode + 16 + 1 + read-write + + + + + BUF0IND + Buffer0 Top Index Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPINDX0 + Top index of buffer 0. + 3 + 29 + read-write + + + + + BUF1IND + Buffer1 Top Index Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPINDX1 + Top index of buffer 1. + 3 + 29 + read-write + + + + + BUF2IND + Buffer2 Top Index Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPINDX2 + Top index of buffer 2. + 3 + 29 + read-write + + + + + SFAR + Serial Flash Address Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SFADR + Serial Flash Address. The register content is used as byte address for all following IP Commands. + 0 + 32 + read-write + + + + + SMPR + Sampling Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDRSMP + SDR sampling point. + 5 + 2 + read-write + + + DDRSMP + DDR Sampling point + 16 + 3 + read-write + + + + + RBSR + RX Buffer Status Register + 0x10C + 32 + read-only + 0 + 0xFFFFFFFF + + + RDBFL + RX Buffer Fill Level, indicates how many entries of 4 bytes are still available in the RX Buffer + 8 + 6 + read-only + + + RDCTR + Read Counter, indicates how many entries of 4 bytes have been removed from the RX Buffer + 16 + 16 + read-only + + + + + RBCT + RX Buffer Control Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + WMRK + RX Buffer Watermark: This field determines when the readout action of the RX Buffer is triggered + 0 + 5 + read-write + + + RXBRD + RX Buffer Readout: This bit specifies the access scheme for the RX Buffer readout. + 8 + 1 + read-write + + + RXBRD_0 + RX Buffer content is read using the AHB Bus registers QSPI_ARDB0 to QSPI_ARDB31. For details, refer to Exclusive Access to Serial Flash for AHB Commands. + 0 + + + RXBRD_1 + RX Buffer content is read using the IP Bus registers QSPI_RBDR0 to QSPI_RBDR31. + 0x1 + + + + + + + TBSR + TX Buffer Status Register + 0x150 + 32 + read-only + 0 + 0xFFFFFFFF + + + TRBFL + TX Buffer Fill Level + 8 + 5 + read-only + + + TRCTR + Transmit Counter + 16 + 16 + read-only + + + + + TBDR + TX Buffer Data Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXDATA + TX Data On write access the data is written into the next available entry of the TX Buffer and the QPSI_TBSR[TRBFL] field is updated accordingly + 0 + 32 + read-write + + + + + SR + Status Register + 0x15C + 32 + read-only + 0x3800 + 0xFFFFFFFF + + + BUSY + Module Busy: Asserted when module is currently busy handling a transaction to an external flash device + 0 + 1 + read-only + + + IP_ACC + IP Access: Asserted when transaction currently executed was initiated by IP bus. + 1 + 1 + read-only + + + AHB_ACC + AHB Access: Asserted when the transaction currently executed was initiated by AHB bus. + 2 + 1 + read-only + + + AHBGNT + AHB Command priority Granted: Asserted when another module has been granted priority of AHB Commands against IP Commands + 5 + 1 + read-only + + + AHBTRN + AHB Access Transaction pending: Asserted when there is a pending request on the AHB interface + 6 + 1 + read-only + + + AHB0NE + AHB 0 Buffer Not Empty: Asserted when AHB 0 buffer contains data. + 7 + 1 + read-only + + + AHB1NE + AHB 1 Buffer Not Empty: Asserted when AHB 1 buffer contains data. + 8 + 1 + read-only + + + AHB2NE + AHB 2 Buffer Not Empty: Asserted when AHB 2 buffer contains data. + 9 + 1 + read-only + + + AHB3NE + AHB 3 Buffer Not Empty: Asserted when AHB 3 buffer contains data. + 10 + 1 + read-only + + + AHB0FUL + AHB 0 Buffer Full: Asserted when AHB 0 buffer is full. + 11 + 1 + read-only + + + AHB1FUL + AHB 1 Buffer Full: Asserted when AHB 1 buffer is full. + 12 + 1 + read-only + + + AHB2FUL + AHB 2 Buffer Full: Asserted when AHB 2 buffer is full. + 13 + 1 + read-only + + + AHB3FUL + AHB 3 Buffer Full: Asserted when AHB 3 buffer is full. + 14 + 1 + read-only + + + RXWE + RX Buffer Watermark Exceeded: Asserted when the number of valid entries in the RX Buffer exceeds the number given in the QSPI_RBCT[WMRK] field + 16 + 1 + read-only + + + RXFULL + RX Buffer Full: Asserted when the RX Buffer is full, i + 19 + 1 + read-only + + + RXDMA + RX Buffer DMA: Asserted when RX Buffer read out via DMA is active i.e DMA is requested or running. + 23 + 1 + read-only + + + TXEDA + Tx Buffer Enough Data Available + 24 + 1 + read-only + + + TXFULL + TX Buffer Full: Asserted when no more data can be stored. + 27 + 1 + read-only + + + DLPSMP + Data learning is not implemented on this chip + 29 + 3 + read-only + + + + + FR + Flag Register + 0x160 + 32 + read-write + 0x8000000 + 0xFFFFFFFF + + + TFF + IP Command Transaction Finished Flag: Set when the QuadSPI module has finished a running IP Command + 0 + 1 + read-write + oneToClear + + + IPGEF + IP Command Trigger during AHB Grant Error Flag: Set when the following condition occurs: A write access occurs to the QSPI_IPCR[SEQID] field and the QSPI_SR[AHBGNT] bit is set + 4 + 1 + read-write + oneToClear + + + IPIEF + IP Command Trigger could not be executed Error Flag + 6 + 1 + read-write + oneToClear + + + IPAEF + IP Command Trigger during AHB Access Error Flag + 7 + 1 + read-write + oneToClear + + + IUEF + IP Command Usage Error Flag: Set when in parallel flash mode the execution of an IP Command is started and the sequence pointed to by the sequence ID contains a WRITE or a WRITE_DDR command + 11 + 1 + read-write + oneToClear + + + ABOF + AHB Buffer Overflow Flag: Set when the size of the AHB access exceeds the size of the AHB buffer + 12 + 1 + read-write + oneToClear + + + ABSEF + AHB Sequence Error Flag: Set when the execution of an AHB Command is started with an WRITE or WRITE_DDR Command in the sequence pointed to by the QSPI_BUFxCR QSPI_BUFxCR implies anyone of QSPI_BUF0CR/QSPI_BUF1CR/QSPI_BUF2CR/QSPI_BUF3CR register Communication with the serial flash device is terminated before the execution of WRITE/WRITE_DDR command by the QuadSPI module + 15 + 1 + read-write + oneToClear + + + RBDF + RX Buffer Drain Flag: Will be set if the QuadSPI_SR[RXWE] status bit is asserted + 16 + 1 + read-write + oneToClear + + + RBOF + RX Buffer Overflow Flag: Set when not all the data read from the serial flash device could be pushed into the RX Buffer + 17 + 1 + read-write + oneToClear + + + ILLINE + Illegal Instruction Error Flag: Set when an illegal instruction is encountered by the controller in any of the sequences + 23 + 1 + read-write + oneToClear + + + TBUF + TX Buffer Underrun Flag: Set when the module tried to pull data although TX Buffer was emptyor the buffer contains less than 128bits of data + 26 + 1 + read-write + oneToClear + + + TBFF + TX Buffer Fill Flag: Before writing to the TX buffer, this bit should be cleared + 27 + 1 + read-write + oneToClear + + + DLPFF + Data learning is not implemented on this chip + 31 + 1 + read-write + oneToClear + + + + + RSER + Interrupt and DMA Request Select and Enable Register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFIE + Transaction Finished Interrupt Enable + 0 + 1 + read-write + + + TFIE_0 + No TFF interrupt will be generated + 0 + + + TFIE_1 + TFF interrupt will be generated + 0x1 + + + + + IPGEIE + IP Command Trigger during AHB Grant Error Interrupt Enable + 4 + 1 + read-write + + + IPGEIE_0 + No IPGEF interrupt will be generated + 0 + + + IPGEIE_1 + IPGEF interrupt will be generated + 0x1 + + + + + IPIEIE + IP Command Trigger during IP Access Error Interrupt Enable + 6 + 1 + read-write + + + IPIEIE_0 + No IPIEF interrupt will be generated + 0 + + + + + IPAEIE + IP Command Trigger during AHB Access Error Interrupt Enable + 7 + 1 + read-write + + + IPAEIE_0 + No IPAEF interrupt will be generated + 0 + + + IPAEIE_1 + IPAEF interrupt will be generated + 0x1 + + + + + IUEIE + IP Command Usage Error Interrupt Enable + 11 + 1 + read-write + + + IUEIE_0 + No IUEF interrupt will be generated + 0 + + + IUEIE_1 + IUEF interrupt will be generated + 0x1 + + + + + ABOIE + AHB Buffer Overflow Interrupt Enable + 12 + 1 + read-write + + + ABOIE_0 + No ABOF interrupt will be generated + 0 + + + ABOIE_1 + ABOF interrupt will be generated + 0x1 + + + + + ABSEIE + AHB Sequence Error Interrupt Enable: Triggered by ABSEF flags of QSPI_FR + 15 + 1 + read-write + + + ABSEIE_0 + No ABSEF interrupt will be generated + 0 + + + ABSEIE_1 + ABSEF interrupt will be generated + 0x1 + + + + + RBDIE + RX Buffer Drain Interrupt Enable: Enables generation of IRQ requests for RX Buffer Drain + 16 + 1 + read-write + + + RBDIE_0 + No RBDF interrupt will be generated + 0 + + + RBDIE_1 + RBDF Interrupt will be generated + 0x1 + + + + + RBOIE + RX Buffer Overflow Interrupt Enable + 17 + 1 + read-write + + + RBOIE_0 + No RBOF interrupt will be generated + 0 + + + RBOIE_1 + RBOF interrupt will be generated + 0x1 + + + + + RBDDE + RX Buffer Drain DMA Enable: Enables generation of DMA requests for RX Buffer Drain + 21 + 1 + read-write + + + RBDDE_0 + No DMA request will be generated + 0 + + + RBDDE_1 + DMA request will be generated + 0x1 + + + + + ILLINIE + Illegal Instruction Error Interrupt Enable. Triggered by ILLINE flag in QSPI_FR + 23 + 1 + read-write + + + ILLINIE_0 + No ILLINE interrupt will be generated + 0 + + + ILLINIE_1 + ILLINE interrupt will be generated + 0x1 + + + + + TBUIE + TX Buffer Underrun Interrupt Enable + 26 + 1 + read-write + + + TBUIE_0 + No TBUF interrupt will be generated + 0 + + + TBUIE_1 + TBUF interrupt will be generated + 0x1 + + + + + TBFIE + TX Buffer Fill Interrupt Enable + 27 + 1 + read-write + + + TBFIE_0 + No TBFF interrupt will be generated + 0 + + + TBFIE_1 + TBFF interrupt will be generated + 0x1 + + + + + DLPFIE + Data learning is not implemented on this chip + 31 + 1 + read-write + + + DLPFIE_0 + No DLPFF interrupt will be generated + 0 + + + DLPFIE_1 + DLPFF interrupt will be generated + 0x1 + + + + + + + SPNDST + Sequence Suspend Status Register + 0x168 + 32 + read-only + 0 + 0xFFFFFFFF + + + SUSPND + When set, it signifies that a sequence is in suspended state + 0 + 1 + read-only + + + SPDBUF + Suspended Buffer: Provides the suspended buffer number. Valid only when SUSPND is set to 1'b1 + 6 + 2 + read-only + + + DATLFT + Data left: Provides information about the amount of data left to be read in the suspended sequence + 9 + 7 + read-only + + + + + SPTRCLR + Sequence Pointer Clear Register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + BFPTRC + Buffer Pointer Clear: 1: Clears the sequence pointer for AHB accesses as defined in QuadSPI_BFGENCR + 0 + 1 + read-write + + + IPPTRC + IP Pointer Clear: 1: Clears the sequence pointer for IP accesses as defined in QuadSPI_IPCR + 8 + 1 + read-write + + + + + SFA1AD + Serial Flash A1 Top Address + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPADA1 + Top address for Serial Flash A1. In effect, TPADxx is the first location of the next memory. + 10 + 22 + read-write + + + + + SFA2AD + Serial Flash A2 Top Address + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPADA2 + Top address for Serial Flash A2. In effect, TPxxAD is the first location of the next memory. + 10 + 22 + read-write + + + + + SFB1AD + Serial Flash B1Top Address + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPADB1 + Top address for Serial Flash B1.In effect, TPxxAD is the first location of the next memory. + 10 + 22 + read-write + + + + + SFB2AD + Serial Flash B2Top Address + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + TPADB2 + Top address for Serial Flash B2. In effect, TPxxAD is the first location of the next memory. + 10 + 22 + read-write + + + + + 32 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 + RBDR%s + RX Buffer Data Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXDATA + RX Data + 0 + 32 + read-write + + + + + LUTKEY + LUT Key Register + 0x300 + 32 + read-write + 0x5AF05AF0 + 0xFFFFFFFF + + + KEY + The key to lock or unlock the LUT. The KEY is 0x5AF05AF0. The read value is always 0x5AF05AF0 + 0 + 32 + read-write + + + + + LCKCR + LUT Lock Configuration Register + 0x304 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + LOCK + Locks the LUT when the following condition is met: This register is written just after the LUTKEYLUT Key Register The LUT key register was written with 0x5AF05AF0 key + 0 + 1 + read-write + + + UNLOCK + Unlocks the LUT when the following two conditions are met: 1 + 1 + 1 + read-write + + + + + LUT0 + Look-up Table register + 0x310 + 32 + read-write + 0x8180403 + 0xFFFFFFFF + + + OPRND0 + Operand for INSTR0. + 0 + 8 + read-write + + + PAD0 + Pad information for INSTR0. + 8 + 2 + read-write + + + PAD0_0 + 1 Pad + 0 + + + PAD0_1 + 2 Pads + 0x1 + + + PAD0_2 + 4 Pads + 0x2 + + + PAD0_3 + NA + 0x3 + + + + + INSTR0 + Instruction 0 + 10 + 6 + read-write + + + OPRND1 + Operand for INSTR1. + 16 + 8 + read-write + + + PAD1 + Pad information for INSTR1. + 24 + 2 + read-write + + + PAD1_0 + 1 Pad + 0 + + + PAD1_1 + 2 Pads + 0x1 + + + PAD1_2 + 4 Pads + 0x2 + + + PAD1_3 + NA + 0x3 + + + + + INSTR1 + Instruction 1 + 26 + 6 + read-write + + + + + LUT1 + Look-up Table register + 0x314 + 32 + read-write + 0x24001C08 + 0xFFFFFFFF + + + OPRND0 + Operand for INSTR0. + 0 + 8 + read-write + + + PAD0 + Pad information for INSTR0. + 8 + 2 + read-write + + + PAD0_0 + 1 Pad + 0 + + + PAD0_1 + 2 Pads + 0x1 + + + PAD0_2 + 4 Pads + 0x2 + + + PAD0_3 + NA + 0x3 + + + + + INSTR0 + Instruction 0 + 10 + 6 + read-write + + + OPRND1 + Operand for INSTR1. + 16 + 8 + read-write + + + PAD1 + Pad information for INSTR1. + 24 + 2 + read-write + + + PAD1_0 + 1 Pad + 0 + + + PAD1_1 + 2 Pads + 0x1 + + + PAD1_2 + 4 Pads + 0x2 + + + PAD1_3 + NA + 0x3 + + + + + INSTR1 + Instruction 1 + 26 + 6 + read-write + + + + + 62 + 0x4 + 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 + LUT%s + Look-up Table register + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + OPRND0 + Operand for INSTR0. + 0 + 8 + read-write + + + PAD0 + Pad information for INSTR0. + 8 + 2 + read-write + + + PAD0_0 + 1 Pad + 0 + + + PAD0_1 + 2 Pads + 0x1 + + + PAD0_2 + 4 Pads + 0x2 + + + PAD0_3 + NA + 0x3 + + + + + INSTR0 + Instruction 0 + 10 + 6 + read-write + + + OPRND1 + Operand for INSTR1. + 16 + 8 + read-write + + + PAD1 + Pad information for INSTR1. + 24 + 2 + read-write + + + PAD1_0 + 1 Pad + 0 + + + PAD1_1 + 2 Pads + 0x1 + + + PAD1_2 + 4 Pads + 0x2 + + + PAD1_3 + NA + 0x3 + + + + + INSTR1 + Instruction 1 + 26 + 6 + read-write + + + + + + + SDMAARM1 + SDMA + SDMAARM + SDMAARM1_ + SDMAARM + 0x30BD0000 + + 0 + 0x2C0 + registers + + + SDMA1 + 2 + + + + MC0PTR + Arm platform Channel 0 Pointer + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MC0PTR + Channel 0 Pointer contains the 32-bit address, in Arm platform memory, of channel 0 control block (the boot channel) + 0 + 32 + read-write + + + + + INTR + Channel Interrupts + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + HI + The Arm platform Interrupts register contains the 32 HI[i] bits + 0 + 32 + read-write + oneToClear + + + + + STOP_STAT + Channel Stop/Channel Status + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HE + This 32-bit register gives access to the Arm platform Enable bits + 0 + 32 + read-write + oneToClear + + + + + HSTART + Channel Start + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + HSTART_HE + The HSTART_HE registers are 32 bits wide with one bit for every channel + 0 + 32 + read-write + oneToClear + + + + + EVTOVR + Channel Event Override + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + EO + The Channel Event Override register contains the 32 EO[i] bits + 0 + 32 + read-write + + + + + DSPOVR + Channel BP Override + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DO + This register is reserved + 0 + 32 + read-write + + + DO_0 + - Reserved + 0 + + + DO_1 + - Reset value. + 0x1 + + + + + + + HOSTOVR + Channel Arm platform Override + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + HO + The Channel Arm platform Override register contains the 32 HO[i] bits + 0 + 32 + read-write + + + + + EVTPEND + Channel Event Pending + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + EP + The Channel Event Pending register contains the 32 EP[i] bits + 0 + 32 + read-write + oneToClear + + + + + RESET + Reset Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESET + When set, this bit causes the SDMA to be held in a software reset + 0 + 1 + read-only + + + RESCHED + When set, this bit forces the SDMA to reschedule as if a script had executed a done instruction + 1 + 1 + read-only + + + + + EVTERR + DMA Request Error Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + CHNERR + This register is used by the SDMA to warn the Arm platform when an incoming DMA request was detected and it triggers a channel that is already pending or being serviced + 0 + 32 + read-only + + + + + INTRMASK + Channel Arm platform Interrupt Mask + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + HIMASK + The Interrupt Mask Register contains 32 interrupt generation mask bits + 0 + 32 + read-write + + + + + PSW + Schedule Status + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + CCR + The Current Channel Register indicates the number of the channel that is being executed by the SDMA + 0 + 4 + read-only + + + CCP + The Current Channel Priority indicates the priority of the current active channel + 4 + 4 + read-only + + + CCP_0 + No running channel + 0 + + + CCP_1 + Active channel priority + 0x1 + + + + + NCR + The Next Channel Register indicates the number of the next scheduled pending channel with the highest priority + 8 + 5 + read-only + + + NCP + The Next Channel Priority gives the next pending channel priority + 13 + 3 + read-only + + + NCP_0 + No running channel + 0 + + + NCP_1 + Active channel priority + 0x1 + + + + + + + EVTERRDBG + DMA Request Error Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + CHNERR + This register is the same as EVTERR, except reading it does not clear its contents + 0 + 32 + read-only + + + + + CONFIG + Configuration Register + 0x38 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + CSM + Selects the Context Switch Mode + 0 + 2 + read-write + + + CSM_0 + static + 0 + + + CSM_1 + dynamic low power + 0x1 + + + CSM_2 + dynamic with no loop + 0x2 + + + CSM_3 + dynamic + 0x3 + + + + + ACR + Arm platform DMA / SDMA Core Clock Ratio + 4 + 1 + read-write + + + ACR_0 + Arm platform DMA interface frequency equals twice core frequency + 0 + + + ACR_1 + Arm platform DMA interface frequency equals core frequency + 0x1 + + + + + RTDOBS + Indicates if Real-Time Debug pins are used: They do not toggle by default in order to reduce power consumption + 11 + 1 + read-write + + + RTDOBS_0 + RTD pins disabled + 0 + + + RTDOBS_1 + RTD pins enabled + 0x1 + + + + + DSPDMA + This bit's function is reserved and should be configured as zero. + 12 + 1 + read-write + + + DSPDMA_0 + - Reset Value + 0 + + + DSPDMA_1 + - Reserved + 0x1 + + + + + + + SDMA_LOCK + SDMA LOCK + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK + The LOCK bit is used to restrict access to update SDMA script memory through ROM channel zero scripts and through the OnCE interface under Arm platform control + 0 + 1 + read-write + + + LOCK_0 + LOCK disengaged. + 0 + + + LOCK_1 + LOCK enabled. + 0x1 + + + + + SRESET_LOCK_CLR + The SRESET_LOCK_CLR bit determine if the LOCK bit is cleared on a software reset triggered by writing to the RESET register + 1 + 1 + read-write + + + SRESET_LOCK_CLR_0 + Software Reset does not clear the LOCK bit. + 0 + + + SRESET_LOCK_CLR_1 + Software Reset clears the LOCK bit. + 0x1 + + + + + + + ONCE_ENB + OnCE Enable + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENB + The OnCE Enable register selects the OnCE control source: When cleared (0), the OnCE registers are accessed through the JTAG interface; when set (1), the OnCE registers may be accessed by the Arm platform through the addresses described, as follows + 0 + 1 + read-write + + + + + ONCE_DATA + OnCE Data Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data register of the OnCE JTAG controller + 0 + 32 + read-write + + + + + ONCE_INSTR + OnCE Instruction Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + INSTR + Instruction register of the OnCE JTAG controller + 0 + 16 + read-write + + + + + ONCE_STAT + OnCE Status Register + 0x4C + 32 + read-only + 0xE000 + 0xFFFFFFFF + + + ECDR + Event Cell Debug Request + 0 + 3 + read-only + + + ECDR_0 + 1 matched addra_cond + 0 + + + ECDR_1 + 1 matched addrb_cond + 0x1 + + + ECDR_2 + 1 matched data_cond + 0x2 + + + + + MST + This flag is raised when the OnCE is controlled from the Arm platform peripheral interface. + 7 + 1 + read-only + + + MST_0 + The JTAG interface controls the OnCE. + 0 + + + MST_1 + The Arm platform peripheral interface controls the OnCE. + 0x1 + + + + + SWB + This flag is raised when the SDMA has entered debug mode after a software breakpoint. + 8 + 1 + read-only + + + ODR + This flag is raised when the SDMA has entered debug mode after a OnCE debug request. + 9 + 1 + read-only + + + EDR + This flag is raised when the SDMA has entered debug mode after an external debug request. + 10 + 1 + read-only + + + RCV + After each write access to the real time buffer (RTB), the RCV bit is set + 11 + 1 + read-only + + + PST + The Processor Status bits reflect the state of the SDMA RISC engine + 12 + 4 + read-only + + + PST_0 + Program + 0 + + + PST_1 + Data + 0x1 + + + PST_2 + Change of Flow + 0x2 + + + PST_3 + Change of Flow in Loop + 0x3 + + + PST_4 + Debug + 0x4 + + + PST_5 + Functional Unit + 0x5 + + + PST_6 + Sleep + 0x6 + + + PST_7 + Save + 0x7 + + + PST_8 + Program in Sleep + 0x8 + + + PST_9 + Data in Sleep + 0x9 + + + PST_12 + Debug in Sleep + 0xC + + + PST_13 + Functional Unit in Sleep + 0xD + + + PST_14 + Sleep after Reset + 0xE + + + PST_15 + Restore + 0xF + + + + + + + ONCE_CMD + OnCE Command Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD + Writing to this register will cause the OnCE to execute the command that is written + 0 + 4 + read-write + + + CMD_0 + rstatus + 0 + + + CMD_1 + dmov + 0x1 + + + CMD_2 + exec_once + 0x2 + + + CMD_3 + run_core + 0x3 + + + CMD_4 + exec_core + 0x4 + + + CMD_5 + debug_rqst + 0x5 + + + CMD_6 + rbuffer + 0x6 + + + + + + + ILLINSTADDR + Illegal Instruction Trap Address + 0x58 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ILLINSTADDR + The Illegal Instruction Trap Address is the address where the SDMA jumps when an illegal instruction is executed + 0 + 14 + read-write + + + + + CHN0ADDR + Channel 0 Boot Address + 0x5C + 32 + read-write + 0x50 + 0xFFFFFFFF + + + CHN0ADDR + This 14-bit register is used by the boot code of the SDMA + 0 + 14 + read-write + + + SMSZ + The bit 14 (Scratch Memory Size) determines if scratch memory must be available after every channel context + 14 + 1 + read-write + + + SMSZ_0 + 24 words per context + 0 + + + SMSZ_1 + 32 words per context + 0x1 + + + + + + + EVT_MIRROR + DMA Requests + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + EVENTS + This register reflects the DMA requests received by the SDMA for events 31-0 + 0 + 32 + read-only + + + EVENTS_0 + DMA request event not pending + 0 + + + EVENTS_1 + DMA request event pending + 0x1 + + + + + + + EVT_MIRROR2 + DMA Requests 2 + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + EVENTS + This register reflects the DMA requests received by the SDMA for events 47-32 + 0 + 16 + read-only + + + EVENTS_0 + - DMA request event not pending + 0 + + + + + + + XTRIG_CONF1 + Cross-Trigger Events Configuration Register 1 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM0 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0 + 6 + read-write + + + CNF0 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 6 + 1 + read-write + + + CNF0_0 + channel + 0 + + + CNF0_1 + DMA request + 0x1 + + + + + NUM1 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 8 + 6 + read-write + + + CNF1 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 14 + 1 + read-write + + + CNF1_0 + channel + 0 + + + CNF1_1 + DMA request + 0x1 + + + + + NUM2 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 16 + 6 + read-write + + + CNF2 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 22 + 1 + read-write + + + CNF2_0 + channel + 0 + + + CNF2_1 + DMA request + 0x1 + + + + + NUM3 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 24 + 6 + read-write + + + CNF3 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 30 + 1 + read-write + + + CNF3_0 + channel + 0 + + + CNF3_1 + DMA request + 0x1 + + + + + + + XTRIG_CONF2 + Cross-Trigger Events Configuration Register 2 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM4 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0 + 6 + read-write + + + CNF4 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 6 + 1 + read-write + + + CNF4_0 + channel + 0 + + + CNF4_1 + DMA request + 0x1 + + + + + NUM5 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 8 + 6 + read-write + + + CNF5 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 14 + 1 + read-write + + + CNF5_0 + channel + 0 + + + CNF5_1 + DMA request + 0x1 + + + + + NUM6 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 16 + 6 + read-write + + + CNF6 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 22 + 1 + read-write + + + CNF6_0 + channel + 0 + + + CNF6_1 + DMA request + 0x1 + + + + + NUM7 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 24 + 6 + read-write + + + CNF7 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 30 + 1 + read-write + + + CNF7_0 + channel + 0 + + + CNF7_1 + DMA request + 0x1 + + + + + + + 32 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 + SDMA_CHNPRI%s + Channel Priority Registers + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHNPRIn + This contains the priority of channel number n + 0 + 3 + read-write + + + + + 48 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47 + CHNENBL%s + Channel Enable RAM + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENBLn + This 32-bit value selects the channels that are triggered by the DMA request number n + 0 + 32 + read-write + + + + + + + SDMAARM2 + SDMA + SDMAARM + SDMAARM2_ + 0x302C0000 + + 0 + 0x2C0 + registers + + + SDMA2 + 103 + + + + ENET + Ethernet MAC-NET Core + ENET + ENET_ + 0x30BE0000 + + 0 + 0x628 + registers + + + ENET + 120 + + + + EIR + Interrupt Event Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXB1 + Receive buffer interrupt, class 1 + 0 + 1 + read-write + oneToClear + + + RXF1 + Receive frame interrupt, class 1 + 1 + 1 + read-write + oneToClear + + + TXB1 + Transmit buffer interrupt, class 1 + 2 + 1 + read-write + oneToClear + + + TXF1 + Transmit frame interrupt, class 1 + 3 + 1 + read-write + oneToClear + + + RXB2 + Receive buffer interrupt, class 2 + 4 + 1 + read-write + oneToClear + + + RXF2 + Receive frame interrupt, class 2 + 5 + 1 + read-write + oneToClear + + + TXB2 + Transmit buffer interrupt, class 2 + 6 + 1 + read-write + oneToClear + + + TXF2 + Transmit frame interrupt, class 2 + 7 + 1 + read-write + oneToClear + + + RXFLUSH_0 + RX DMA Ring 0 flush indication + 12 + 1 + read-write + oneToClear + + + RXFLUSH_1 + RX DMA Ring 1 flush indication + 13 + 1 + read-write + oneToClear + + + RXFLUSH_2 + RX DMA Ring 2 flush indication + 14 + 1 + read-write + oneToClear + + + TS_TIMER + Timestamp Timer + 15 + 1 + read-write + oneToClear + + + TS_AVAIL + Transmit Timestamp Available + 16 + 1 + read-write + oneToClear + + + WAKEUP + Node Wakeup Request Indication + 17 + 1 + read-write + oneToClear + + + PLR + Payload Receive Error + 18 + 1 + read-write + oneToClear + + + UN + Transmit FIFO Underrun + 19 + 1 + read-write + oneToClear + + + RL + Collision Retry Limit + 20 + 1 + read-write + oneToClear + + + LC + Late Collision + 21 + 1 + read-write + oneToClear + + + EBERR + Ethernet Bus Error + 22 + 1 + read-write + oneToClear + + + MII + MII Interrupt. + 23 + 1 + read-write + oneToClear + + + RXB + Receive Buffer Interrupt + 24 + 1 + read-write + oneToClear + + + RXF + Receive Frame Interrupt + 25 + 1 + read-write + oneToClear + + + TXB + Transmit Buffer Interrupt + 26 + 1 + read-write + oneToClear + + + TXF + Transmit Frame Interrupt + 27 + 1 + read-write + oneToClear + + + GRA + Graceful Stop Complete + 28 + 1 + read-write + oneToClear + + + BABT + Babbling Transmit Error + 29 + 1 + read-write + oneToClear + + + BABR + Babbling Receive Error + 30 + 1 + read-write + oneToClear + + + + + EIMR + Interrupt Mask Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXB1 + Receive buffer interrupt, class 1 + 0 + 1 + read-write + + + RXF1 + Receive frame interrupt, class 1 + 1 + 1 + read-write + + + TXB1 + Transmit buffer interrupt, class 1 + 2 + 1 + read-write + + + TXF1 + Transmit frame interrupt, class 1 + 3 + 1 + read-write + + + RXB2 + Receive buffer interrupt, class 2 + 4 + 1 + read-write + + + RXF2 + Receive frame interrupt, class 2 + 5 + 1 + read-write + + + TXB2 + Transmit buffer interrupt, class 2 + 6 + 1 + read-write + + + TXF2 + Transmit frame interrupt, class 2 + 7 + 1 + read-write + + + RXFLUSH_0 + Corresponds to interrupt source EIR[RXFLUSH_0] and determines whether an interrupt condition can generate an interrupt + 12 + 1 + read-write + + + RXFLUSH_1 + Corresponds to interrupt source EIR[RXFLUSH_1] and determines whether an interrupt condition can generate an interrupt + 13 + 1 + read-write + + + RXFLUSH_2 + Corresponds to interrupt source EIR[RXFLUSH_2] and determines whether an interrupt condition can generate an interrupt + 14 + 1 + read-write + + + TS_TIMER + TS_TIMER Interrupt Mask + 15 + 1 + read-write + + + TS_AVAIL + TS_AVAIL Interrupt Mask + 16 + 1 + read-write + + + WAKEUP + WAKEUP Interrupt Mask + 17 + 1 + read-write + + + PLR + PLR Interrupt Mask + 18 + 1 + read-write + + + UN + UN Interrupt Mask + 19 + 1 + read-write + + + RL + RL Interrupt Mask + 20 + 1 + read-write + + + LC + LC Interrupt Mask + 21 + 1 + read-write + + + EBERR + EBERR Interrupt Mask + 22 + 1 + read-write + + + MII + MII Interrupt Mask + 23 + 1 + read-write + + + RXB + RXB Interrupt Mask + 24 + 1 + read-write + + + RXF + RXF Interrupt Mask + 25 + 1 + read-write + + + TXB + TXB Interrupt Mask + 26 + 1 + read-write + + + TXB_0 + The corresponding interrupt source is masked. + 0 + + + TXB_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + TXF + TXF Interrupt Mask + 27 + 1 + read-write + + + TXF_0 + The corresponding interrupt source is masked. + 0 + + + TXF_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + GRA + GRA Interrupt Mask + 28 + 1 + read-write + + + GRA_0 + The corresponding interrupt source is masked. + 0 + + + GRA_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + BABT + BABT Interrupt Mask + 29 + 1 + read-write + + + BABT_0 + The corresponding interrupt source is masked. + 0 + + + BABT_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + BABR + BABR Interrupt Mask + 30 + 1 + read-write + + + BABR_0 + The corresponding interrupt source is masked. + 0 + + + BABR_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + + + RDAR + Receive Descriptor Active Register - Ring 0 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDAR + Receive Descriptor Active + 24 + 1 + read-write + + + + + TDAR + Transmit Descriptor Active Register - Ring 0 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDAR + Transmit Descriptor Active + 24 + 1 + read-write + + + + + ECR + Ethernet Control Register + 0x24 + 32 + read-write + 0x70000000 + 0xFFFFFFFF + + + RESET + Ethernet MAC Reset + 0 + 1 + read-write + + + ETHEREN + Ethernet Enable + 1 + 1 + read-write + + + ETHEREN_0 + Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + 0 + + + ETHEREN_1 + MAC is enabled, and reception and transmission are possible. + 0x1 + + + + + MAGICEN + Magic Packet Detection Enable + 2 + 1 + read-write + + + MAGICEN_0 + Magic detection logic disabled. + 0 + + + MAGICEN_1 + The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + 0x1 + + + + + SLEEP + Sleep Mode Enable + 3 + 1 + read-write + + + SLEEP_0 + Normal operating mode. + 0 + + + SLEEP_1 + Sleep mode. + 0x1 + + + + + EN1588 + EN1588 Enable + 4 + 1 + read-write + + + EN1588_0 + Legacy FEC buffer descriptors and functions enabled. + 0 + + + EN1588_1 + Enhanced frame time-stamping functions enabled. + 0x1 + + + + + SPEED + Selects between 10/100-Mbit/s and 1000-Mbit/s modes of operation. + 5 + 1 + read-write + + + SPEED_0 + 10/100-Mbit/s mode + 0 + + + SPEED_1 + 1000-Mbit/s mode + 0x1 + + + + + DBGEN + Debug Enable + 6 + 1 + read-write + + + DBGEN_0 + MAC continues operation in debug mode. + 0 + + + DBGEN_1 + MAC enters hardware freeze mode when the processor is in debug mode. + 0x1 + + + + + DBSWP + Descriptor Byte Swapping Enable + 8 + 1 + read-write + + + DBSWP_0 + The buffer descriptor bytes are not swapped to support big-endian devices. + 0 + + + DBSWP_1 + The buffer descriptor bytes are swapped to support little-endian devices. + 0x1 + + + + + SVLANEN + S-VLAN enable + 9 + 1 + read-write + + + SVLANEN_0 + Only the EtherType 0x8100 will be considered for VLAN detection. + 0 + + + SVLANEN_1 + The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the classification match comparators, RCMRn. + 0x1 + + + + + VLANUSE2ND + VLAN use second tag + 10 + 1 + read-write + + + VLANUSE2ND_0 + Always extract data from the first VLAN tag if it exists. + 0 + + + VLANUSE2ND_1 + When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The second tag must be a C-VLAN + 0x1 + + + + + SVLANDBL + S-VLAN double tag + 11 + 1 + read-write + + + + + MMFR + MII Management Frame Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Management Frame Data + 0 + 16 + read-write + + + TA + Turn Around + 16 + 2 + read-write + + + RA + Register Address + 18 + 5 + read-write + + + PA + PHY Address + 23 + 5 + read-write + + + OP + Operation Code + 28 + 2 + read-write + + + ST + Start Of Frame Delimiter + 30 + 2 + read-write + + + + + MSCR + MII Speed Control Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + MII_SPEED + MII Speed + 1 + 6 + read-write + + + DIS_PRE + Disable Preamble + 7 + 1 + read-write + + + DIS_PRE_0 + Preamble enabled. + 0 + + + DIS_PRE_1 + Preamble (32 ones) is not prepended to the MII management frame. + 0x1 + + + + + HOLDTIME + Hold time On MDIO Output + 8 + 3 + read-write + + + HOLDTIME_0 + 1 internal module clock cycle + 0 + + + HOLDTIME_1 + 2 internal module clock cycles + 0x1 + + + HOLDTIME_2 + 3 internal module clock cycles + 0x2 + + + HOLDTIME_7 + 8 internal module clock cycles + 0x7 + + + + + + + MIBC + MIB Control Register + 0x64 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + MIB_CLEAR + MIB Clear + 29 + 1 + read-write + + + MIB_CLEAR_0 + See note above. + 0 + + + MIB_CLEAR_1 + All statistics counters are reset to 0. + 0x1 + + + + + MIB_IDLE + MIB Idle + 30 + 1 + read-only + + + MIB_IDLE_0 + The MIB block is updating MIB counters. + 0 + + + MIB_IDLE_1 + The MIB block is not currently updating any MIB counters. + 0x1 + + + + + MIB_DIS + Disable MIB Logic + 31 + 1 + read-write + + + MIB_DIS_0 + MIB logic is enabled. + 0 + + + MIB_DIS_1 + MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + 0x1 + + + + + + + RCR + Receive Control Register + 0x84 + 32 + read-write + 0x5EE0001 + 0xFFFFFFFF + + + LOOP + Internal Loopback + 0 + 1 + read-write + + + LOOP_0 + Loopback disabled. + 0 + + + LOOP_1 + Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + 0x1 + + + + + DRT + Disable Receive On Transmit + 1 + 1 + read-write + + + DRT_0 + Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + 0 + + + DRT_1 + Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + 0x1 + + + + + MII_MODE + Media Independent Interface Mode + 2 + 1 + read-write + + + MII_MODE_1 + MII or RMII mode, as indicated by the RMII_MODE field. + 0x1 + + + + + PROM + Promiscuous Mode + 3 + 1 + read-write + + + PROM_0 + Disabled. + 0 + + + PROM_1 + Enabled. + 0x1 + + + + + BC_REJ + Broadcast Frame Reject + 4 + 1 + read-write + + + FCE + Flow Control Enable + 5 + 1 + read-write + + + RGMII_EN + RGMII Mode Enable + 6 + 1 + read-write + + + RGMII_EN_0 + MAC configured for non-RGMII operation + 0 + + + RGMII_EN_1 + MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode. + 0x1 + + + + + RMII_MODE + RMII Mode Enable + 8 + 1 + read-write + + + RMII_MODE_0 + MAC configured for MII mode. + 0 + + + RMII_MODE_1 + MAC configured for RMII operation. + 0x1 + + + + + RMII_10T + Enables 10-Mbit/s mode of the RMII or RGMII . + 9 + 1 + read-write + + + RMII_10T_0 + 100-Mbit/s operation. + 0 + + + RMII_10T_1 + 10-Mbit/s operation. + 0x1 + + + + + PADEN + Enable Frame Padding Remove On Receive + 12 + 1 + read-write + + + PADEN_0 + No padding is removed on receive by the MAC. + 0 + + + PADEN_1 + Padding is removed from received frames. + 0x1 + + + + + PAUFWD + Terminate/Forward Pause Frames + 13 + 1 + read-write + + + PAUFWD_0 + Pause frames are terminated and discarded in the MAC. + 0 + + + PAUFWD_1 + Pause frames are forwarded to the user application. + 0x1 + + + + + CRCFWD + Terminate/Forward Received CRC + 14 + 1 + read-write + + + CRCFWD_0 + The CRC field of received frames is transmitted to the user application. + 0 + + + CRCFWD_1 + The CRC field is stripped from the frame. + 0x1 + + + + + CFEN + MAC Control Frame Enable + 15 + 1 + read-write + + + CFEN_0 + MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + 0 + + + CFEN_1 + MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + 0x1 + + + + + MAX_FL + Maximum Frame Length + 16 + 14 + read-write + + + NLC + Payload Length Check Disable + 30 + 1 + read-write + + + NLC_0 + The payload length check is disabled. + 0 + + + NLC_1 + The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. + 0x1 + + + + + GRS + Graceful Receive Stopped + 31 + 1 + read-only + + + + + TCR + Transmit Control Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GTS + Graceful Transmit Stop + 0 + 1 + read-write + + + FDEN + Full-Duplex Enable + 2 + 1 + read-write + + + TFC_PAUSE + Transmit Frame Control Pause + 3 + 1 + read-write + + + TFC_PAUSE_0 + No PAUSE frame transmitted. + 0 + + + TFC_PAUSE_1 + The MAC stops transmission of data frames after the current transmission is complete. + 0x1 + + + + + RFC_PAUSE + Receive Frame Control Pause + 4 + 1 + read-only + + + ADDSEL + Source MAC Address Select On Transmit + 5 + 3 + read-write + + + ADDSEL_0 + Node MAC address programmed on PADDR1/2 registers. + 0 + + + + + ADDINS + Set MAC Address On Transmit + 8 + 1 + read-write + + + ADDINS_0 + The source MAC address is not modified by the MAC. + 0 + + + ADDINS_1 + The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + 0x1 + + + + + CRCFWD + Forward Frame From Application With CRC + 9 + 1 + read-write + + + CRCFWD_0 + TxBD[TC] controls whether the frame has a CRC from the application. + 0 + + + CRCFWD_1 + The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + 0x1 + + + + + + + PALR + Physical Address Lower Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADDR1 + Pause Address + 0 + 32 + read-write + + + + + PAUR + Physical Address Upper Register + 0xE8 + 32 + read-write + 0x8808 + 0xFFFFFFFF + + + TYPE + Type Field In PAUSE Frames + 0 + 16 + read-only + + + PADDR2 + Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames + 16 + 16 + read-write + + + + + OPD + Opcode/Pause Duration Register + 0xEC + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + PAUSE_DUR + Pause Duration + 0 + 16 + read-write + + + OPCODE + Opcode Field In PAUSE Frames + 16 + 16 + read-only + + + + + 3 + 0x4 + 0,1,2 + TXIC%s + Transmit Interrupt Coalescing Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICTT + Interrupt coalescing timer threshold + 0 + 16 + read-write + + + ICFT + Interrupt coalescing frame count threshold + 20 + 8 + read-write + + + ICCS + Interrupt Coalescing Timer Clock Source Select + 30 + 1 + read-write + + + ICCS_0 + Use MII/GMII TX clocks. + 0 + + + ICCS_1 + Use ENET system clock. + 0x1 + + + + + ICEN + Interrupt Coalescing Enable + 31 + 1 + read-write + + + ICEN_0 + Disable Interrupt coalescing. + 0 + + + ICEN_1 + Enable Interrupt coalescing. + 0x1 + + + + + + + 3 + 0x4 + 0,1,2 + RXIC%s + Receive Interrupt Coalescing Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICTT + Interrupt coalescing timer threshold + 0 + 16 + read-write + + + ICFT + Interrupt coalescing frame count threshold + 20 + 8 + read-write + + + ICCS + Interrupt Coalescing Timer Clock Source Select + 30 + 1 + read-write + + + ICCS_0 + Use MII/GMII TX clocks. + 0 + + + ICCS_1 + Use ENET system clock. + 0x1 + + + + + ICEN + Interrupt Coalescing Enable + 31 + 1 + read-write + + + ICEN_0 + Disable Interrupt coalescing. + 0 + + + ICEN_1 + Enable Interrupt coalescing. + 0x1 + + + + + + + IAUR + Descriptor Individual Upper Address Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR1 + Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address + 0 + 32 + read-write + + + + + IALR + Descriptor Individual Lower Address Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR2 + Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address + 0 + 32 + read-write + + + + + GAUR + Descriptor Group Upper Address Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR1 + Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address + 0 + 32 + read-write + + + + + GALR + Descriptor Group Lower Address Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR2 + Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address + 0 + 32 + read-write + + + + + TFWR + Transmit FIFO Watermark Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFWR + Transmit FIFO Write + 0 + 6 + read-write + + + TFWR_0 + 64 bytes written. + 0 + + + TFWR_1 + 64 bytes written. + 0x1 + + + TFWR_2 + 128 bytes written. + 0x2 + + + TFWR_3 + 192 bytes written. + 0x3 + + + TFWR_63 + 4032 bytes written. + 0x3F + + + + + STRFWD + Store And Forward Enable + 8 + 1 + read-write + + + STRFWD_0 + Reset. The transmission start threshold is programmed in TFWR[TFWR]. + 0 + + + STRFWD_1 + Enabled. + 0x1 + + + + + + + RDSR1 + Receive Descriptor Ring 1 Start Register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_DES_START + Pointer to the beginning of the receive buffer descriptor queue 1. + 3 + 29 + read-write + + + + + TDSR1 + Transmit Buffer Descriptor Ring 1 Start Register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + X_DES_START + Pointer to the beginning of transmit buffer descriptor queue 1. + 3 + 29 + read-write + + + + + MRBR1 + Maximum Receive Buffer Size Register - Ring 1 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_BUF_SIZE + Receive buffer size in bytes + 4 + 7 + read-write + + + + + RDSR2 + Receive Descriptor Ring 2 Start Register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + R_DES_START + Pointer to the beginning of receive buffer descriptor queue 2. + 3 + 29 + read-write + + + + + TDSR2 + Transmit Buffer Descriptor Ring 2 Start Register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + X_DES_START + Pointer to the beginning of transmit buffer descriptor queue 2. + 3 + 29 + read-write + + + + + MRBR2 + Maximum Receive Buffer Size Register - Ring 2 + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_BUF_SIZE + Receive buffer size in bytes + 4 + 7 + read-write + + + + + RDSR + Receive Descriptor Ring 0 Start Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_DES_START + Pointer to the beginning of the receive buffer descriptor queue. 0 + 3 + 29 + read-write + + + + + TDSR + Transmit Buffer Descriptor Ring 0 Start Register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + X_DES_START + Pointer to the beginning of the transmit buffer descriptor queue. + 3 + 29 + read-write + + + + + MRBR + Maximum Receive Buffer Size Register - Ring 0 + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_BUF_SIZE + Receive buffer size in bytes + 4 + 7 + read-write + + + + + RSFL + Receive FIFO Section Full Threshold + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_FULL + Value Of Receive FIFO Section Full Threshold + 0 + 10 + read-write + + + + + RSEM + Receive FIFO Section Empty Threshold + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_EMPTY + Value Of The Receive FIFO Section Empty Threshold + 0 + 10 + read-write + + + STAT_SECTION_EMPTY + RX Status FIFO Section Empty Threshold + 16 + 5 + read-write + + + + + RAEM + Receive FIFO Almost Empty Threshold + 0x198 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_EMPTY + Value Of The Receive FIFO Almost Empty Threshold + 0 + 10 + read-write + + + + + RAFL + Receive FIFO Almost Full Threshold + 0x19C + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_FULL + Value Of The Receive FIFO Almost Full Threshold + 0 + 10 + read-write + + + + + TSEM + Transmit FIFO Section Empty Threshold + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_SECTION_EMPTY + Value Of The Transmit FIFO Section Empty Threshold + 0 + 10 + read-write + + + + + TAEM + Transmit FIFO Almost Empty Threshold + 0x1A4 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + TX_ALMOST_EMPTY + Value of Transmit FIFO Almost Empty Threshold + 0 + 10 + read-write + + + + + TAFL + Transmit FIFO Almost Full Threshold + 0x1A8 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + TX_ALMOST_FULL + Value Of The Transmit FIFO Almost Full Threshold + 0 + 10 + read-write + + + + + TIPG + Transmit Inter-Packet Gap + 0x1AC + 32 + read-write + 0xC + 0xFFFFFFFF + + + IPG + Transmit Inter-Packet Gap + 0 + 5 + read-write + + + + + FTRL + Frame Truncation Length + 0x1B0 + 32 + read-write + 0x7FF + 0xFFFFFFFF + + + TRUNC_FL + Frame Truncation Length + 0 + 14 + read-write + + + + + TACC + Transmit Accelerator Function Configuration + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFT16 + TX FIFO Shift-16 + 0 + 1 + read-write + + + SHIFT16_0 + Disabled. + 0 + + + SHIFT16_1 + Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. + 0x1 + + + + + IPCHK + Enables insertion of IP header checksum. + 3 + 1 + read-write + + + IPCHK_0 + Checksum is not inserted. + 0 + + + IPCHK_1 + If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. + 0x1 + + + + + PROCHK + Enables insertion of protocol checksum. + 4 + 1 + read-write + + + PROCHK_0 + Checksum not inserted. + 0 + + + PROCHK_1 + If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. + 0x1 + + + + + + + RACC + Receive Accelerator Function Configuration + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADREM + Enable Padding Removal For Short IP Frames + 0 + 1 + read-write + + + PADREM_0 + Padding not removed. + 0 + + + PADREM_1 + Any bytes following the IP payload section of the frame are removed from the frame. + 0x1 + + + + + IPDIS + Enable Discard Of Frames With Wrong IPv4 Header Checksum + 1 + 1 + read-write + + + IPDIS_0 + Frames with wrong IPv4 header checksum are not discarded. + 0 + + + IPDIS_1 + If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + 0x1 + + + + + PRODIS + Enable Discard Of Frames With Wrong Protocol Checksum + 2 + 1 + read-write + + + PRODIS_0 + Frames with wrong checksum are not discarded. + 0 + + + PRODIS_1 + If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + 0x1 + + + + + LINEDIS + Enable Discard Of Frames With MAC Layer Errors + 6 + 1 + read-write + + + LINEDIS_0 + Frames with errors are not discarded. + 0 + + + LINEDIS_1 + Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + 0x1 + + + + + SHIFT16 + RX FIFO Shift-16 + 7 + 1 + read-write + + + SHIFT16_0 + Disabled. + 0 + + + SHIFT16_1 + Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + 0x1 + + + + + + + 2 + 0x4 + 1,2 + RCMR%s + Receive Classification Match Register for Class n + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMP0 + Compare 0 + 0 + 3 + read-write + + + CMP1 + Compare 1 + 4 + 3 + read-write + + + CMP2 + Compare 2 + 8 + 3 + read-write + + + CMP3 + Compare 3 + 12 + 3 + read-write + + + MATCHEN + Match Enable + 16 + 1 + read-write + + + MATCHEN_0 + Disabled (default): no compares will occur and the classification indicator for this class will never assert. + 0 + + + MATCHEN_1 + The register contents are valid and a comparison with all compare values is done when a VLAN frame is received. + 0x1 + + + + + + + 2 + 0x4 + 1,2 + DMA%sCFG + DMA Class Based Configuration + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDLE_SLOPE + Idle slope + 0 + 16 + read-write + + + DMA_CLASS_EN + DMA class enable + 16 + 1 + read-write + + + DMA_CLASS_EN_0 + The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2 queues are disabled then their frames will be placed in queue 0. + 0 + + + DMA_CLASS_EN_1 + Enable the DMA controller to support the corresponding descriptor ring for this class of traffic. + 0x1 + + + + + CALC_NOIPG + Calculate no IPG + 17 + 1 + read-write + + + CALC_NOIPG_0 + The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations. This is the default. + 0 + + + CALC_NOIPG_1 + Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping, when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames will become more bandwidth than large frames due to the relation of data to IPG overhead). + 0x1 + + + + + + + RDAR1 + Receive Descriptor Active Register - Ring 1 + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDAR + Receive Descriptor Active + 24 + 1 + read-write + + + + + TDAR1 + Transmit Descriptor Active Register - Ring 1 + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDAR + Transmit Descriptor Active + 24 + 1 + read-write + + + + + RDAR2 + Receive Descriptor Active Register - Ring 2 + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDAR + Receive Descriptor Active + 24 + 1 + read-write + + + + + TDAR2 + Transmit Descriptor Active Register - Ring 2 + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + TDAR + Transmit Descriptor Active + 24 + 1 + read-write + + + + + QOS + QOS Scheme + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_SCHEME + TX scheme configuration + 0 + 3 + read-write + + + TX_SCHEME_0 + Credit-based scheme + 0 + + + TX_SCHEME_1 + Round-robin scheme + 0x1 + + + + + RX_FLUSH0 + RX Flush Ring 0 + 3 + 1 + read-write + + + RX_FLUSH0_0 + Disable + 0 + + + RX_FLUSH0_1 + Enable + 0x1 + + + + + RX_FLUSH1 + RX Flush Ring 1 + 4 + 1 + read-write + + + RX_FLUSH1_0 + Disable + 0 + + + RX_FLUSH1_1 + Enable + 0x1 + + + + + RX_FLUSH2 + RX Flush Ring 2 + 5 + 1 + read-write + + + RX_FLUSH2_0 + Disable + 0 + + + RX_FLUSH2_1 + Enable + 0x1 + + + + + + + RMON_T_DROP + Reserved Statistic Register + 0x200 + 32 + read-only + 0 + 0xFFFFFFFF + + + RMON_T_PACKETS + Tx Packet Count Statistic Register + 0x204 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Packet count + 0 + 16 + read-only + + + + + RMON_T_BC_PKT + Tx Broadcast Packets Statistic Register + 0x208 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Broadcast packets + 0 + 16 + read-only + + + + + RMON_T_MC_PKT + Tx Multicast Packets Statistic Register + 0x20C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Multicast packets + 0 + 16 + read-only + + + + + RMON_T_CRC_ALIGN + Tx Packets with CRC/Align Error Statistic Register + 0x210 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Packets with CRC/align error + 0 + 16 + read-only + + + + + RMON_T_UNDERSIZE + Tx Packets Less Than Bytes and Good CRC Statistic Register + 0x214 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets less than 64 bytes with good CRC + 0 + 16 + read-only + + + + + RMON_T_OVERSIZE + Tx Packets GT MAX_FL bytes and Good CRC Statistic Register + 0x218 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than MAX_FL bytes with good CRC + 0 + 16 + read-only + + + + + RMON_T_FRAG + Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register + 0x21C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of packets less than 64 bytes with bad CRC + 0 + 16 + read-only + + + + + RMON_T_JAB + Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register + 0x220 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than MAX_FL bytes and bad CRC + 0 + 16 + read-only + + + + + RMON_T_COL + Tx Collision Count Statistic Register + 0x224 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit collisions + 0 + 16 + read-only + + + + + RMON_T_P64 + Tx 64-Byte Packets Statistic Register + 0x228 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 64-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P65TO127 + Tx 65- to 127-byte Packets Statistic Register + 0x22C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 65- to 127-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P128TO255 + Tx 128- to 255-byte Packets Statistic Register + 0x230 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 128- to 255-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P256TO511 + Tx 256- to 511-byte Packets Statistic Register + 0x234 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 256- to 511-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P512TO1023 + Tx 512- to 1023-byte Packets Statistic Register + 0x238 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 512- to 1023-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P1024TO2047 + Tx 1024- to 2047-byte Packets Statistic Register + 0x23C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 1024- to 2047-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P_GTE2048 + Tx Packets Greater Than 2048 Bytes Statistic Register + 0x240 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than 2048 bytes + 0 + 16 + read-only + + + + + RMON_T_OCTETS + Tx Octets Statistic Register + 0x244 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXOCTS + Number of transmit octets + 0 + 32 + read-only + + + + + IEEE_T_DROP + Reserved Statistic Register + 0x248 + 32 + read-only + 0 + 0xFFFFFFFF + + + IEEE_T_FRAME_OK + Frames Transmitted OK Statistic Register + 0x24C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted OK + 0 + 16 + read-only + + + + + IEEE_T_1COL + Frames Transmitted with Single Collision Statistic Register + 0x250 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with one collision + 0 + 16 + read-only + + + + + IEEE_T_MCOL + Frames Transmitted with Multiple Collisions Statistic Register + 0x254 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with multiple collisions + 0 + 16 + read-only + + + + + IEEE_T_DEF + Frames Transmitted after Deferral Delay Statistic Register + 0x258 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with deferral delay + 0 + 16 + read-only + + + + + IEEE_T_LCOL + Frames Transmitted with Late Collision Statistic Register + 0x25C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with late collision + 0 + 16 + read-only + + + + + IEEE_T_EXCOL + Frames Transmitted with Excessive Collisions Statistic Register + 0x260 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with excessive collisions + 0 + 16 + read-only + + + + + IEEE_T_MACERR + Frames Transmitted with Tx FIFO Underrun Statistic Register + 0x264 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with transmit FIFO underrun + 0 + 16 + read-only + + + + + IEEE_T_CSERR + Frames Transmitted with Carrier Sense Error Statistic Register + 0x268 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with carrier sense error + 0 + 16 + read-only + + + + + IEEE_T_SQE + Reserved Statistic Register + 0x26C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + This read-only field is reserved and always has the value 0 + 0 + 16 + read-only + + + + + IEEE_T_FDXFC + Flow Control Pause Frames Transmitted Statistic Register + 0x270 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of flow-control pause frames transmitted + 0 + 16 + read-only + + + + + IEEE_T_OCTETS_OK + Octet Count for Frames Transmitted w/o Error Statistic Register + 0x274 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). + 0 + 32 + read-only + + + + + RMON_R_PACKETS + Rx Packet Count Statistic Register + 0x284 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of packets received + 0 + 16 + read-only + + + + + RMON_R_BC_PKT + Rx Broadcast Packets Statistic Register + 0x288 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive broadcast packets + 0 + 16 + read-only + + + + + RMON_R_MC_PKT + Rx Multicast Packets Statistic Register + 0x28C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive multicast packets + 0 + 16 + read-only + + + + + RMON_R_CRC_ALIGN + Rx Packets with CRC/Align Error Statistic Register + 0x290 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with CRC or align error + 0 + 16 + read-only + + + + + RMON_R_UNDERSIZE + Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register + 0x294 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with less than 64 bytes and good CRC + 0 + 16 + read-only + + + + + RMON_R_OVERSIZE + Rx Packets Greater Than MAX_FL and Good CRC Statistic Register + 0x298 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets greater than MAX_FL and good CRC + 0 + 16 + read-only + + + + + RMON_R_FRAG + Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register + 0x29C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with less than 64 bytes and bad CRC + 0 + 16 + read-only + + + + + RMON_R_JAB + Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register + 0x2A0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets greater than MAX_FL and bad CRC + 0 + 16 + read-only + + + + + RMON_R_RESVD_0 + Reserved Statistic Register + 0x2A4 + 32 + read-only + 0 + 0xFFFFFFFF + + + RMON_R_P64 + Rx 64-Byte Packets Statistic Register + 0x2A8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 64-byte receive packets + 0 + 16 + read-only + + + + + RMON_R_P65TO127 + Rx 65- to 127-Byte Packets Statistic Register + 0x2AC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 65- to 127-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P128TO255 + Rx 128- to 255-Byte Packets Statistic Register + 0x2B0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 128- to 255-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P256TO511 + Rx 256- to 511-Byte Packets Statistic Register + 0x2B4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 256- to 511-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P512TO1023 + Rx 512- to 1023-Byte Packets Statistic Register + 0x2B8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 512- to 1023-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P1024TO2047 + Rx 1024- to 2047-Byte Packets Statistic Register + 0x2BC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 1024- to 2047-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P_GTE2048 + Rx Packets Greater than 2048 Bytes Statistic Register + 0x2C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of greater-than-2048-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_OCTETS + Rx Octets Statistic Register + 0x2C4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive octets + 0 + 32 + read-only + + + + + IEEE_R_DROP + Frames not Counted Correctly Statistic Register + 0x2C8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Frame count + 0 + 16 + read-only + + + + + IEEE_R_FRAME_OK + Frames Received OK Statistic Register + 0x2CC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received OK + 0 + 16 + read-only + + + + + IEEE_R_CRC + Frames Received with CRC Error Statistic Register + 0x2D0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received with CRC error + 0 + 16 + read-only + + + + + IEEE_R_ALIGN + Frames Received with Alignment Error Statistic Register + 0x2D4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received with alignment error + 0 + 16 + read-only + + + + + IEEE_R_MACERR + Receive FIFO Overflow Count Statistic Register + 0x2D8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Receive FIFO overflow count + 0 + 16 + read-only + + + + + IEEE_R_FDXFC + Flow Control Pause Frames Received Statistic Register + 0x2DC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of flow-control pause frames received + 0 + 16 + read-only + + + + + IEEE_R_OCTETS_OK + Octet Count for Frames Received without Error Statistic Register + 0x2E0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of octets for frames received without error + 0 + 32 + read-only + + + + + ATCR + Adjustable Timer Control Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable Timer + 0 + 1 + read-write + + + EN_0 + The timer stops at the current value. + 0 + + + EN_1 + The timer starts incrementing. + 0x1 + + + + + OFFEN + Enable One-Shot Offset Event + 2 + 1 + read-write + + + OFFEN_0 + Disable. + 0 + + + OFFEN_1 + The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. + 0x1 + + + + + OFFRST + Reset Timer On Offset Event + 3 + 1 + read-write + + + OFFRST_0 + The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + 0 + + + OFFRST_1 + If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + 0x1 + + + + + PEREN + Enable Periodical Event + 4 + 1 + read-write + + + PEREN_0 + Disable. + 0 + + + PEREN_1 + A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. + 0x1 + + + + + PINPER + Enables event signal output assertion on period event + 7 + 1 + read-write + + + PINPER_0 + Disable. + 0 + + + PINPER_1 + Enable. + 0x1 + + + + + RESTART + Reset Timer + 9 + 1 + read-write + + + CAPTURE + Capture Timer Value + 11 + 1 + read-write + + + CAPTURE_0 + No effect. + 0 + + + CAPTURE_1 + The current time is captured and can be read from the ATVR register. + 0x1 + + + + + SLAVE + Enable Timer Slave Mode + 13 + 1 + read-write + + + SLAVE_0 + The timer is active and all configuration fields in this register are relevant. + 0 + + + SLAVE_1 + The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + 0x1 + + + + + + + ATVR + Timer Value Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATIME + A write sets the timer + 0 + 32 + read-write + + + + + ATOFF + Timer Offset Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET + Offset value for one-shot event generation + 0 + 32 + read-write + + + + + ATPER + Timer Period Register + 0x40C + 32 + read-write + 0x3B9ACA00 + 0xFFFFFFFF + + + PERIOD + Value for generating periodic events + 0 + 32 + read-write + + + + + ATCOR + Timer Correction Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + COR + Correction Counter Wrap-Around Value + 0 + 31 + read-write + + + + + ATINC + Time-Stamping Clock Period Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds + 0 + 7 + read-write + + + INC_CORR + Correction Increment Value + 8 + 7 + read-write + + + + + ATSTMP + Timestamp of Last Transmitted Frame + 0x418 + 32 + read-only + 0 + 0xFFFFFFFF + + + TIMESTAMP + Timestamp of the last frame transmitted by the core that had TxBD[TS] set + 0 + 32 + read-only + + + + + TGSR + Timer Global Status Register + 0x604 + 32 + read-write + 0 + 0xFFFFFFFF + + + TF0 + Copy Of Timer Flag For Channel 0 + 0 + 1 + read-write + oneToClear + + + TF0_0 + Timer Flag for Channel 0 is clear + 0 + + + TF0_1 + Timer Flag for Channel 0 is set + 0x1 + + + + + TF1 + Copy Of Timer Flag For Channel 1 + 1 + 1 + read-write + oneToClear + + + TF1_0 + Timer Flag for Channel 1 is clear + 0 + + + TF1_1 + Timer Flag for Channel 1 is set + 0x1 + + + + + TF2 + Copy Of Timer Flag For Channel 2 + 2 + 1 + read-write + oneToClear + + + TF2_0 + Timer Flag for Channel 2 is clear + 0 + + + TF2_1 + Timer Flag for Channel 2 is set + 0x1 + + + + + TF3 + Copy Of Timer Flag For Channel 3 + 3 + 1 + read-write + oneToClear + + + TF3_0 + Timer Flag for Channel 3 is clear + 0 + + + TF3_1 + Timer Flag for Channel 3 is set + 0x1 + + + + + + + 4 + 0x8 + 0,1,2,3 + TCSR%s + Timer Control Status Register + 0x608 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDRE + Timer DMA Request Enable + 0 + 1 + read-write + + + TDRE_0 + DMA request is disabled + 0 + + + TDRE_1 + DMA request is enabled + 0x1 + + + + + TMODE + Timer Mode + 2 + 4 + read-write + + + TMODE_0 + Timer Channel is disabled. + 0 + + + TMODE_1 + Timer Channel is configured for Input Capture on rising edge. + 0x1 + + + TMODE_2 + Timer Channel is configured for Input Capture on falling edge. + 0x2 + + + TMODE_3 + Timer Channel is configured for Input Capture on both edges. + 0x3 + + + TMODE_4 + Timer Channel is configured for Output Compare - software only. + 0x4 + + + TMODE_5 + Timer Channel is configured for Output Compare - toggle output on compare. + 0x5 + + + TMODE_6 + Timer Channel is configured for Output Compare - clear output on compare. + 0x6 + + + TMODE_7 + Timer Channel is configured for Output Compare - set output on compare. + 0x7 + + + TMODE_9 + Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + #10x1 + + + TMODE_10 + Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + 0xA + + + TMODE_14 + Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. + 0xE + + + TMODE_15 + Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle. + 0xF + + + + + TIE + Timer Interrupt Enable + 6 + 1 + read-write + + + TIE_0 + Interrupt is disabled + 0 + + + TIE_1 + Interrupt is enabled + 0x1 + + + + + TF + Timer Flag + 7 + 1 + read-write + oneToClear + + + TF_0 + Input Capture or Output Compare has not occurred. + 0 + + + TF_1 + Input Capture or Output Compare has occurred. + 0x1 + + + + + + + 4 + 0x8 + 0,1,2,3 + TCCR%s + Timer Compare Capture Register + 0x60C + 32 + read-write + 0 + 0xFFFFFFFF + + + TCC + Timer Capture Compare + 0 + 32 + read-write + + + + + + + HDMI_TX + hdmi_tx + HDMI_TX + 0x32C00000 + + 0 + 0x30838 + registers + + + + APB_CTRL + no description available + 0 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + apb_xt_reset + APB Control on the CPU reset active High + 0 + 1 + read-write + + + apb_dram_path + When 1 enable APB to R/W the DRAM + 1 + 1 + read-write + + + apb_iram_path + When 1 enable APB to R/W the IRAM + 2 + 1 + read-write + + + reserved_0 + reserved_0 + 3 + 29 + read-only + + + + + xt_int_ctrl + no description available + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + xt_int_polarity + xt_int_polarity + 0 + 2 + read-write + + + reserved_0 + reserved_0 + 2 + 30 + read-only + + + + + MAILBOX_FULL_ADDR + no description available + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + mailbox_full + Mailboxes full indication + 0 + 1 + read-only + + + reserved_0 + reserved_0 + 1 + 31 + read-only + + + + + MAILBOX_EMPTY_ADDR + no description available + 0xC + 32 + read-only + 0x1 + 0xFFFFFFFF + + + mailbox_empty + Mailboxes Empty indication + 0 + 1 + read-only + + + reserved_0 + reserved_0 + 1 + 31 + read-only + + + + + mailbox0_wr_data + no description available + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + mailbox0_wr_data + Write Data to Mailbox + 0 + 8 + read-write + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + mailbox0_rd_data + no description available + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + mailbox0_rd_data + Mailbox Read data + 0 + 8 + read-only + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + KEEP_ALIVE + no description available + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + keep_alive_cnt + Software keep alive counter + 0 + 8 + read-only + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + VER_L + no description available + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + ver_lsb + Software Version LSB + 0 + 8 + read-only + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + VER_H + no description available + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + ver_msb + Software Version MSB + 0 + 8 + read-only + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + VER_LIB_L_ADDR + no description available + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + sw_lib_ver_l + Software Lib version written by CPU + 0 + 8 + read-only + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + VER_LIB_H_ADDR + no description available + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + sw_lib_ver_h + Software Lib version written by CPU + 0 + 8 + read-only + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + SW_DEBUG_L + no description available + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + sw_debug_7_0 + sw_debug_7_0 + 0 + 8 + read-only + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + SW_DEBUG_H + no description available + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + sw_debug_15_8 + sw_debug_15_8 + 0 + 8 + read-only + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + MAILBOX_INT_MASK + no description available + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + mailbox_int_mask + Mailbox Interupt mask Bit[0] - Empty Bit[1] - Full + 0 + 2 + read-write + + + reserved_0 + reserved_0 + 2 + 30 + read-only + + + + + MAILBOX_INT_STATUS + no description available + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + mailbox_int_status + Mailbox Interupt Status Bit[0] - Empty Bit[1] - Full + 0 + 2 + read-only + + + reserved_0 + reserved_0 + 2 + 30 + read-only + + + + + SW_CLK_L + no description available + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + sw_clock_val_l + Fractial of the clock decimal value + 0 + 8 + read-write + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + SW_CLK_H + no description available + 0x40 + 32 + read-write + 0x64 + 0xFFFFFFFF + + + sw_clock_val_h + Clock frequency in decimal values + 0 + 8 + read-write + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + SW_EVENTS0 + no description available + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + sw_events7_0 + When SW writes it updted just the extra event bits When Host read it is cleared + 0 + 8 + read-only + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + SW_EVENTS1 + no description available + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + sw_events15_8 + When SW writes it updted just the extra event bits When Host read it is cleared + 0 + 8 + read-only + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + SW_EVENTS2 + no description available + 0x4C + 32 + read-only + 0 + 0xFFFFFFFF + + + sw_events23_16 + When SW writes it updted just the extra event bits When Host read it is cleared + 0 + 8 + read-only + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + SW_EVENTS3 + no description available + 0x50 + 32 + read-only + 0 + 0xFFFFFFFF + + + sw_events31_24 + When SW writes it updted just the extra event bits When Host read it is cleared + 0 + 8 + read-only + + + reserved_0 + reserved_0 + 8 + 24 + read-only + + + + + XT_OCD_CTRL + no description available + 0x60 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + xt_dreset + Xtensa Dreset control register + 0 + 1 + read-write + + + xt_ocdhaltonreset + Xtensa Halt On Reget configuration register + 1 + 1 + read-write + + + reserved_0 + reserved_0 + 2 + 30 + read-only + + + + + XT_OCD_CTRL_RO + no description available + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + xt_xocdmode + Xtensa OCD mode configuration + 0 + 1 + read-only + + + reserved_0 + reserved_0 + 1 + 31 + read-only + + + + + APB_INT_MASK + no description available + 0x6C + 32 + read-write + 0x7 + 0xFFFFFFFF + + + apb_intr_mask + Mask the APB interupt Bit0 - Mailbox Interupt Bit1 - PIF Interupt Bit2 - CEC Interupt + 0 + 3 + read-write + + + reserved_0 + reserved_0 + 3 + 29 + read-only + + + + + APB_STATUS_MASK + no description available + 0x70 + 32 + read-only + 0 + 0xFFFFFFFF + + + apb_intr_status + APB interupt STATUS Bit0 - Mailbox Interupt Bit1 - PIF Interupt Bit2 - CEC Interupt + 0 + 3 + read-only + + + reserved_0 + reserved_0 + 3 + 29 + read-only + + + + + AUDIO_SRC_CNTL + no description available + 0x30000 + 32 + read-write + 0 + 0xFFFFFFFF + + + sw_rst + Software reset. Active high. + 0 + 1 + read-write + + + i2s_dec_start + When high Source Decoder starts. + 1 + 1 + read-write + + + i2s_block_start_force + Force a "Block Start" in the audio stream. + 2 + 1 + read-write + + + spdif_ts_en + Enble SPDIF Time Stamp when decoders are disabled + 3 + 1 + read-write + + + i2s_ts_en + Enble I2S Time Stamp when decoders are disabled + 4 + 1 + read-write + + + valid_bits_force + Force valid bits of the channels + 5 + 1 + read-write + + + valid_all + valid bit for all samples + 6 + 1 + read-write + + + reserved_0 + reserved_0 + 7 + 25 + read-only + + + + + AUDIO_SRC_CNFG + no description available + 0x30004 + 32 + read-write + 0 + 0xFFFFFFFF + + + low_index_msb + When low MSB is transmitted first. When high LSB is transmitted first. + 0 + 1 + read-write + + + ws_polarity + Word Select Polarity. 0: No change, 1: Inverted. + 1 + 1 + read-write + + + audio_ch_num + Number of channels to decode + 2 + 5 + read-write + + + audio_sample_just + Data justification setting:00 left-justified, 01 right-justified + 7 + 2 + read-write + + + audio_sample_width + Decoder sample width:00-16 bit, 01-24 bit, 10-32 bit + 9 + 2 + read-write + + + trans_smpl_width + Decoder Word Select width: 00-16 bit, 01-24 bit, 10-32 bit + 11 + 2 + read-write + + + audio_channel_type + Set the transmission type. + 13 + 4 + read-write + + + i2s_dec_port_en + Enables the I2S Decoder ports. Allowed values are:0001 - I2S port 0 is enabled.0011 - I2S ports 0,1 are enabled.1111 - I2S ports 0,1,2,3 are enabled. No other values are allowed. + 17 + 4 + read-write + + + reserved_0 + reserved_0 + 21 + 11 + read-only + + + + + COM_CH_STTS_BITS + no description available + 0x30008 + 32 + read-write + 0 + 0xFFFFFFFF + + + Byte0 + Byte 0 of transmitted channel. Same for all channels. + 0 + 8 + read-write + + + Category_Code + Category Code of transmitted channel. Same for all channels. + 8 + 8 + read-write + + + Sampling_Freq + Sampling Frequency of transmitted channel. Same for all channels. + 16 + 4 + read-write + + + Clock_accuracy + Clock Accuracy of transmitted channel. Same for all channels. + 20 + 4 + read-write + + + Original_samp_freq + Original Sampling Freq. of transmitted channel. Same for all channels. + 24 + 4 + read-write + + + reserved_0 + reserved_0 + 28 + 4 + read-only + + + + + STTS_BIT_CH01 + no description available + 0x3000C + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch0 + Channel 0 Source number. + 0 + 4 + read-write + + + channel_num_ch0 + Channel 0 channel number. + 4 + 4 + read-write + + + word_length_ch0 + Channel 0 word length. + 8 + 4 + read-write + + + source_num_ch1 + Channel 1 Source number. + 12 + 4 + read-write + + + channel_num_ch1 + Channel 1 channel number. + 16 + 4 + read-write + + + word_length_ch1 + Channel 1 word length. + 20 + 4 + read-write + + + valid_bits1_0 + Valid Bits for channel 1 and 0 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH23 + no description available + 0x30010 + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch2 + Channel 2 Source number. + 0 + 4 + read-write + + + channel_num_ch2 + Channel 2 channel number. + 4 + 4 + read-write + + + word_length_ch2 + Channel 2 word length. + 8 + 4 + read-write + + + source_num_ch3 + Channel 3 Source number. + 12 + 4 + read-write + + + channel_num_ch3 + Channel 3 channel number. + 16 + 4 + read-write + + + word_length_ch3 + Channel 3 word length. + 20 + 4 + read-write + + + valid_bits3_2 + Valid Bits for channel 3 and 2 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH45 + no description available + 0x30014 + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch4 + Channel 4 Source number. + 0 + 4 + read-write + + + channel_num_ch4 + Channel 4 channel number. + 4 + 4 + read-write + + + word_length_ch4 + Channel 4 word length. + 8 + 4 + read-write + + + source_num_ch5 + Channel 5 Source number. + 12 + 4 + read-write + + + channel_num_ch5 + Channel 5 channel number. + 16 + 4 + read-write + + + word_length_ch5 + Channel 5 word length. + 20 + 4 + read-write + + + valid_bits5_4 + Valid Bits for channel 5 and 4 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH67 + no description available + 0x30018 + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch6 + Channel 6 Source number. + 0 + 4 + read-write + + + channel_num_ch6 + Channel 6 channel number. + 4 + 4 + read-write + + + word_length_ch6 + Channel 6 word length. + 8 + 4 + read-write + + + source_num_ch7 + Channel 7 Source number. + 12 + 4 + read-write + + + channel_num_ch7 + Channel 7 channel number. + 16 + 4 + read-write + + + word_length_ch7 + Channel 7 word length. + 20 + 4 + read-write + + + valid_bits7_6 + Valid Bits for channel 7 and 6 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH89 + no description available + 0x3001C + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch8 + Channel 8 Source number. + 0 + 4 + read-write + + + channel_num_ch8 + Channel 8 channel number. + 4 + 4 + read-write + + + word_length_ch8 + Channel 8 word length. + 8 + 4 + read-write + + + source_num_ch9 + Channel 9 Source number. + 12 + 4 + read-write + + + channel_num_ch9 + Channel 9 channel number. + 16 + 4 + read-write + + + word_length_ch9 + Channel 9 word length. + 20 + 4 + read-write + + + valid_bits9_8 + Valid Bits for channel 9 and 8 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH1011 + no description available + 0x30020 + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch10 + Channel 10 Source number. + 0 + 4 + read-write + + + channel_num_ch10 + Channel 10 channel number. + 4 + 4 + read-write + + + word_length_ch10 + Channel 10 word length. + 8 + 4 + read-write + + + source_num_ch11 + Channel 11 Source number. + 12 + 4 + read-write + + + channel_num_ch11 + Channel 11 channel number. + 16 + 4 + read-write + + + word_length_ch11 + Channel 11 word length. + 20 + 4 + read-write + + + valid_bits11_10 + Valid Bits for channel 11 and 10 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH1213 + no description available + 0x30024 + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch12 + Channel 12 Source number. + 0 + 4 + read-write + + + channel_num_ch12 + Channel 12 channel number. + 4 + 4 + read-write + + + word_length_ch12 + Channel 12 word length. + 8 + 4 + read-write + + + source_num_ch13 + Channel 13 Source number. + 12 + 4 + read-write + + + channel_num_ch13 + Channel 13 channel number. + 16 + 4 + read-write + + + word_length_ch13 + Channel 13 word length. + 20 + 4 + read-write + + + valid_bits13_12 + Valid Bits for channel 13 and 12 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH1415 + no description available + 0x30028 + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch14 + Channel 14 Source number. + 0 + 4 + read-write + + + channel_num_ch14 + Channel 14 channel number. + 4 + 4 + read-write + + + word_length_ch14 + Channel 14 word length. + 8 + 4 + read-write + + + source_num_ch15 + Channel 15 Source number. + 12 + 4 + read-write + + + channel_num_ch15 + Channel 15 channel number. + 16 + 4 + read-write + + + word_length_ch15 + Channel 15 word length. + 20 + 4 + read-write + + + valid_bits15_14 + Valid Bits for channel 15 and 14 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH1617 + no description available + 0x3002C + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch16 + Channel 16 Source number. + 0 + 4 + read-write + + + channel_num_ch16 + Channel 16 channel number. + 4 + 4 + read-write + + + word_length_ch16 + Channel 16 word length. + 8 + 4 + read-write + + + source_num_ch17 + Channel 17 Source number. + 12 + 4 + read-write + + + channel_num_ch17 + Channel 17 channel number. + 16 + 4 + read-write + + + word_length_ch17 + Channel 17 word length. + 20 + 4 + read-write + + + valid_bits17_16 + Valid Bits for channel 17 and 16 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH1819 + no description available + 0x30030 + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch18 + Channel 18 Source number. + 0 + 4 + read-write + + + channel_num_ch18 + Channel 18 channel number. + 4 + 4 + read-write + + + word_length_ch18 + Channel 18 word length. + 8 + 4 + read-write + + + source_num_ch19 + Channel 19 Source number. + 12 + 4 + read-write + + + channel_num_ch19 + Channel 19 channel number. + 16 + 4 + read-write + + + word_length_ch19 + Channel 19 word length. + 20 + 4 + read-write + + + valid_bits19_18 + Valid Bits for channel 19 and 18 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH2021 + no description available + 0x30034 + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch20 + Channel 20 Source number. + 0 + 4 + read-write + + + channel_num_ch20 + Channel 20 channel number. + 4 + 4 + read-write + + + word_length_ch20 + Channel 20 word length. + 8 + 4 + read-write + + + source_num_ch21 + Channel 21 Source number. + 12 + 4 + read-write + + + channel_num_ch21 + Channel 21 channel number. + 16 + 4 + read-write + + + word_length_ch21 + Channel 21 word length. + 20 + 4 + read-write + + + valid_bits21_20 + Valid Bits for channel 21 and 20 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH2223 + no description available + 0x30038 + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch22 + Channel 22 Source number. + 0 + 4 + read-write + + + channel_num_ch22 + Channel 22 channel number. + 4 + 4 + read-write + + + word_length_ch22 + Channel 22 word length. + 8 + 4 + read-write + + + source_num_ch23 + Channel 23 Source number. + 12 + 4 + read-write + + + channel_num_ch23 + Channel 23 channel number. + 16 + 4 + read-write + + + word_length_ch23 + Channel 23 word length. + 20 + 4 + read-write + + + valid_bits23_22 + Valid Bits for channel 23 and 22 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH2425 + no description available + 0x3003C + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch24 + Channel 24 Source number. + 0 + 4 + read-write + + + channel_num_ch24 + Channel 24 channel number. + 4 + 4 + read-write + + + word_length_ch24 + Channel 24 word length. + 8 + 4 + read-write + + + source_num_ch25 + Channel 25 Source number. + 12 + 4 + read-write + + + channel_num_ch25 + Channel 25 channel number. + 16 + 4 + read-write + + + word_length_ch25 + Channel 25 word length. + 20 + 4 + read-write + + + valid_bits25_24 + Valid Bits for channel 25 and 24 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH2627 + no description available + 0x30040 + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch26 + Channel 26 Source number. + 0 + 4 + read-write + + + channel_num_ch26 + Channel 26 channel number. + 4 + 4 + read-write + + + word_length_ch26 + Channel 26 word length. + 8 + 4 + read-write + + + source_num_ch27 + Channel 27 Source number. + 12 + 4 + read-write + + + channel_num_ch27 + Channel 27 channel number. + 16 + 4 + read-write + + + word_length_ch27 + Channel 27 word length. + 20 + 4 + read-write + + + valid_bits27_26 + Valid Bits for channel 27 and 26 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH2829 + no description available + 0x30044 + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch28 + Channel 28 Source number. + 0 + 4 + read-write + + + channel_num_ch28 + Channel 28 channel number. + 4 + 4 + read-write + + + word_length_ch28 + Channel 28 word length. + 8 + 4 + read-write + + + source_num_ch29 + Channel 29 Source number. + 12 + 4 + read-write + + + channel_num_ch29 + Channel 29 channel number. + 16 + 4 + read-write + + + word_length_ch29 + Channel 29 word length. + 20 + 4 + read-write + + + valid_bits29_28 + Valid Bits for channel 29 and 28 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + STTS_BIT_CH3031 + no description available + 0x30048 + 32 + read-write + 0 + 0xFFFFFFFF + + + source_num_ch30 + Channel 30 Source number. + 0 + 4 + read-write + + + channel_num_ch30 + Channel 30 channel number. + 4 + 4 + read-write + + + word_length_ch30 + Channel 30 word length. + 8 + 4 + read-write + + + source_num_ch31 + Channel 31 Source number. + 12 + 4 + read-write + + + channel_num_ch31 + Channel 31 channel number. + 16 + 4 + read-write + + + word_length_ch31 + Channel 31 word length. + 20 + 4 + read-write + + + valid_bits31_30 + Valid Bits for channel 31 and 30 if force is enabled + 24 + 2 + read-write + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + SPDIF_CTRL_ADDR + no description available + 0x3004C + 32 + read-write + 0 + 0xFFFFFFFF + + + spdif_jitter_avg_win + Spdif Jitter AVG Window + 0 + 3 + read-write + + + spdif_jitter_thrsh + SPDIF Jitter threshold + 3 + 8 + read-write + + + spdif_fifo_mid_range + SPDIF fifo mid range + 11 + 8 + read-write + + + spdif_jitter_bypass + SPDIF Jitter Bypass + 19 + 1 + read-write + + + spdif_avg_sel + SPDIF average Select + 20 + 1 + read-write + + + spdif_enable + SPDIF Enable + 21 + 1 + read-write + + + spdif_jitter_status + SPDIF Jitter Status + 22 + 4 + read-only + + + reserved_0 + reserved_0 + 26 + 6 + read-only + + + + + SPDIF_CH1_CS_3100_ADDR + no description available + 0x30050 + 32 + read-only + 0 + 0xFFFFFFFF + + + spdif_ch1_st_stts_bits3100 + SPDIF Channel 1 Status bits[31:0] + 0 + 32 + read-only + + + + + SPDIF_CH1_CS_6332_ADDR + no description available + 0x30054 + 32 + read-only + 0 + 0xFFFFFFFF + + + spdif_ch1_st_stts_bits6332 + SPDIF Channel 1 Status bits[63:32] + 0 + 32 + read-only + + + + + SPDIF_CH1_CS_9564_ADDR + no description available + 0x30058 + 32 + read-only + 0 + 0xFFFFFFFF + + + spdif_ch1_st_stts_bits9564 + SPDIF Channel 1 Status bits[95:64] + 0 + 32 + read-only + + + + + SPDIF_CH1_CS_12796_ADDR + no description available + 0x3005C + 32 + read-only + 0 + 0xFFFFFFFF + + + spdif_ch1_st_stts_bits12796 + SPDIF Channel 1 Status bits[127:96] + 0 + 32 + read-only + + + + + SPDIF_CH1_CS_159128_ADDR + no description available + 0x30060 + 32 + read-only + 0 + 0xFFFFFFFF + + + spdif_ch1_st_stts_bits159128 + SPDIF Channel 1 Status bits[159:128] + 0 + 32 + read-only + + + + + SPDIF_CH1_CS_191160_ADDR + no description available + 0x30064 + 32 + read-only + 0 + 0xFFFFFFFF + + + spdif_ch1_st_stts_bits191160 + SPDIF Channel 1 Status bits[191160] + 0 + 32 + read-only + + + + + SPDIF_CH2_CS_3100_ADDR + no description available + 0x30068 + 32 + read-only + 0 + 0xFFFFFFFF + + + spdif_ch2_st_stts_bits3100 + SPDIF Channel 2 Status bits[31:0] + 0 + 32 + read-only + + + + + SPDIF_CH2_CS_6332_ADDR + no description available + 0x3006C + 32 + read-only + 0 + 0xFFFFFFFF + + + spdif_ch2_st_stts_bits6332 + SPDIF Channel 2 Status bits[63:32] + 0 + 32 + read-only + + + + + SPDIF_CH2_CS_9564_ADDR + no description available + 0x30070 + 32 + read-only + 0 + 0xFFFFFFFF + + + spdif_ch2_st_stts_bits9564 + SPDIF Channel 2 Status bits[95:64] + 0 + 32 + read-only + + + + + SPDIF_CH2_CS_12796_ADDR + no description available + 0x30074 + 32 + read-only + 0 + 0xFFFFFFFF + + + spdif_ch2_st_stts_bits12796 + SPDIF Channel 2 Status bits[127:96] + 0 + 32 + read-only + + + + + SPDIF_CH2_CS_159128_ADDR + no description available + 0x30078 + 32 + read-only + 0 + 0xFFFFFFFF + + + spdif_ch2_st_stts_bits159128 + SPDIF Channel 2 Status bits[159:128] + 0 + 32 + read-only + + + + + SPDIF_CH2_CS_191160_ADDR + no description available + 0x3007C + 32 + read-only + 0 + 0xFFFFFFFF + + + spdif_ch2_st_stts_bits191160 + SPDIF Channel 2 Status bits[191160] + 0 + 32 + read-only + + + + + SMPL2PKT_CNTL + no description available + 0x30080 + 32 + read-write + 0 + 0xFFFFFFFF + + + sw_rst + Software reset. Active high. + 0 + 1 + read-write + + + smpl2pkt_en + When high Sample to Packets Block starts. + 1 + 1 + read-write + + + reserved_0 + reserved_0 + 2 + 30 + read-only + + + + + SMPL2PKT_CNFG + no description available + 0x30084 + 32 + read-write + 0x800 + 0xFFFFFFFF + + + max_num_ch + Number of channels to decode. 0: 1 channel, 31: 32 channels + 0 + 5 + read-write + + + num_of_i2s_ports + Number ofactive I2S ports. 00- 1 port, 01-2 ports, 11- 4 ports, 11 -NA. + 5 + 2 + read-write + + + audio_type + Audio Type setting. Packet is structured according to audio type. + 7 + 4 + read-write + + + cfg_sub_pckt_num + Number of sub-packets in HDMI audio 2-ch packet. 00: 1-SP, 01: 2-SP, 10: 3-SP, 11: 4-SP.100-111: NA. + 11 + 3 + read-write + + + cfg_block_lpcm_first_pkt + 0 - All packets behave the same. 1- First lpcm audio packet is sent with 1 - SP. + 14 + 1 + read-write + + + cfg_en_auto_sub_pckt_num + Enable automatics sub packet number. When enabled number of sub-packts will be set according to MEM FIFO number of samples. + 15 + 1 + read-write + + + cfg_sample_present + Sample present bits if force them is active + 16 + 4 + read-write + + + cfg_sample_present_force + Force sample present bits + 20 + 1 + read-write + + + reserved_0 + reserved_0 + 21 + 11 + read-only + + + + + FIFO_CNTL + no description available + 0x30088 + 32 + read-write + 0 + 0xFFFFFFFF + + + fifo_sw_rst + Resets Fifo's write and read pointers. When FIFO configuration bits change this signal should be high (due to synchronization issues). + 0 + 1 + read-write + + + sync_wr_to_ch_zero + When high the last channel index synchronizes the write addresses (to the next channel group) + 1 + 1 + read-write + + + fifo_dir + 0 - smpl2pkt (inc_step=number of I2S ports), 1 - pkt2smpl (inc_step=num_ch_per_port) + 2 + 1 + read-write + + + fifo_empty_calc + 0- Empty is a function of read address. 1 - Empty is a function of BASE read address. + 3 + 1 + read-write + + + cfg_dis_port3 + 0 - Normal Operation. 1 - I2S port 3 is disabled (user should ignore its outputs). This allows for 24-ch, 12-ch, 6-ch transfer. + 4 + 1 + read-write + + + reserved_0 + reserved_0 + 5 + 27 + read-only + + + + + FIFO_STTS + no description available + 0x3008C + 32 + read-only + 0 + 0xFFFFFFFF + + + wfull + Indicates FIFO Full - indication comes with delay caused by Synchronization. + 0 + 1 + read-only + + + rempty + Indicates FIFO Empty - indication comes with delay caused by Synchronization. + 1 + 1 + read-only + + + overrun + Indicates a FIFO overrun error has occurred - FIFO written to when it was full. + 2 + 1 + read-only + + + underrun + Indicates a FIFO underrun error has occurred - FIFO read when it was empty. + 3 + 1 + read-only + + + reserved_0 + reserved_0 + 4 + 28 + read-only + + + + + SUB_PCKT_THRSH + no description available + 0x30090 + 32 + read-write + 0x302010 + 0xFFFFFFFF + + + cfg_mem_fifo_thrsh1 + If number of samples in MEM FIFO is below Threshold 1: Each Packet will contain only 1 subpacket. + 0 + 8 + read-write + + + cfg_mem_fifo_thrsh2 + If number of samples in MEM FIFO is below Threshold2: Each Packet will contain only 2 subpacket. + 8 + 8 + read-write + + + cfg_mem_fifo_thrsh3 + If number of samples in MEM FIFO is below Threshold 3: Each Packet will contain only 3 subpacket. + 16 + 8 + read-write + + + reserved_0 + reserved_0 + 24 + 8 + read-only + + + + + SOURCE_PIF_WR_ADDR + no description available + 0x30800 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_addr + 4 MSB of the packet memory address in which the data is written. + 0 + 4 + read-write + + + reserved_0 + reserved_0 + 4 + 28 + read-only + + + + + SOURCE_PIF_WR_REQ + no description available + 0x30804 + 32 + read-write + 0 + 0xFFFFFFFF + + + host_wr + Write request bit for the host write transaction. + 0 + 1 + read-write + + + reserved_0 + reserved_0 + 1 + 31 + read-only + + + + + SOURCE_PIF_RD_ADDR + no description available + 0x30808 + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_addr + 4 MSB of the packet memory address from which the data is read. + 0 + 4 + read-write + + + reserved_0 + reserved_0 + 4 + 28 + read-only + + + + + SOURCE_PIF_RD_REQ + no description available + 0x3080C + 32 + read-write + 0 + 0xFFFFFFFF + + + host_rd + Read request bit for the host read transaction + 0 + 1 + read-write + + + reserved_0 + reserved_0 + 1 + 31 + read-only + + + + + SOURCE_PIF_DATA_WR + no description available + 0x30810 + 32 + read-write + 0 + 0xFFFFFFFF + + + data_wr + The 32 bits of the data to be written to the packet memory. When written to this register fifo1_wr_enable will be asserted. + 0 + 32 + read-write + + + + + SOURCE_PIF_DATA_RD + no description available + 0x30814 + 32 + read-only + 0 + 0xFFFFFFFF + + + fifo2_data_out + The 32 bits of the data to be read from the packet memory. When read from this register fifo2_rd_enable will be asserted. + 0 + 32 + read-only + + + + + SOURCE_PIF_FIFO1_FLUSH + no description available + 0x30818 + 32 + read-write + 0 + 0xFFFFFFFF + + + fifo1_flush + Fifo1 flush bit + 0 + 1 + read-write + + + reserved_0 + reserved_0 + 1 + 31 + read-only + + + + + SOURCE_PIF_FIFO2_FLUSH + no description available + 0x3081C + 32 + read-write + 0 + 0xFFFFFFFF + + + fifo2_flush + Fifo2 flush bit + 0 + 1 + read-write + + + reserved_0 + reserved_0 + 1 + 31 + read-only + + + + + SOURCE_PIF_STATUS + no description available + 0x30820 + 32 + read-only + 0x8 + 0xFFFFFFFF + + + source_pkt_mem_ctrl_fsm_state + State of the FSM that controls packet memory transactions. + 0 + 2 + read-only + + + fifo1_full + Fifo1 full indication + 2 + 1 + read-only + + + fifo2_empty + Fifo2 empty indication + 3 + 1 + read-only + + + reserved_0 + reserved_0 + 4 + 28 + read-only + + + + + SOURCE_PIF_INTERRUPT_SOURCE + no description available + 0x30824 + 32 + read-only + 0 + 0xFFFFFFFF + + + host_wr_done_int + Indication that the host write transaction finished. + 0 + 1 + read-only + + + host_rd_done_int + Indication that the host read transaction finished. + 1 + 1 + read-only + + + nonvalid_type_requested_int + Indication that nonvalid type of packet is requested by the packet interface. + 2 + 1 + read-only + + + pslverr + APB slave error interrupt + 3 + 1 + read-only + + + alloc_wr_done + Successful write to the allocation table. + 4 + 1 + read-only + + + alloc_wr_error + Error happened, invalid write to the allocation table. + 5 + 1 + read-only + + + fifo1_overflow + Fifo1 overflow indication + 6 + 1 + read-only + + + fifo1_underflow + Fifo1 underflow indication + 7 + 1 + read-only + + + fifo2_overflow + Fifo2 overflow indication + 8 + 1 + read-only + + + fifo2_underflow + Fifo2 underflow indication + 9 + 1 + read-only + + + reserved_0 + reserved_0 + 10 + 22 + read-only + + + + + SOURCE_PIF_INTERRUPT_MASK + no description available + 0x30828 + 32 + read-write + 0 + 0xFFFFFFFF + + + host_wr_done_int_mask + Masks the host_wr_done_int interrupt + 0 + 1 + read-write + + + host_rd_done_int_mask + Masks the host_rd_done_int interrupt + 1 + 1 + read-write + + + nonvalid_type_requested_int_mask + Masks the nonvalid_type_requested_int interrupt + 2 + 1 + read-write + + + pslverr_mask + Masks the pslverr interrupt + 3 + 1 + read-write + + + alloc_wr_done_mask + Masks the alloc_wr_done interrupt + 4 + 1 + read-write + + + alloc_wr_error_mask + Masks the alloc_wr_error interrupt + 5 + 1 + read-write + + + fifo1_overflow_mask + Masks the fifo1_overflow interrupt + 6 + 1 + read-write + + + fifo1_underflow_mask + Masks the fifo1_underflow interrupt + 7 + 1 + read-write + + + fifo2_overflow_mask + Masks the fifo2_overflow interrupt + 8 + 1 + read-write + + + fifo2_underflow_mask + Masks the fifo2_underflow interrupt + 9 + 1 + read-write + + + reserved_0 + reserved_0 + 10 + 22 + read-only + + + + + SOURCE_PIF_PKT_ALLOC_REG + no description available + 0x3082C + 32 + read-write + 0 + 0xFFFFFFFF + + + pkt_alloc_address + Address of the register in the source allocation table + 0 + 4 + read-write + + + reserved_0 + reserved_0 + 4 + 4 + read-only + + + packet_type + Type of packet + 8 + 8 + read-write + + + type_valid + 1 for valid, 0 for nonvalid + 16 + 1 + read-write + + + active_idle_type + active_idle_type + 17 + 1 + read-write + + + reserved_1 + reserved_1 + 18 + 14 + read-only + + + + + SOURCE_PIF_PKT_ALLOC_WR_EN + no description available + 0x30830 + 32 + read-write + 0 + 0xFFFFFFFF + + + pkt_alloc_wr_en + Enable bit for writing to the allocation table + 0 + 1 + read-write + + + reserved_0 + reserved_0 + 1 + 31 + read-only + + + + + SOURCE_PIF_SW_RESET + no description available + 0x30834 + 32 + read-write + 0 + 0xFFFFFFFF + + + sw_rst + Software reset + 0 + 1 + read-write + + + reserved_0 + reserved_0 + 1 + 31 + read-only + + + + + + + DCSS__MED_HDR10 + no description available + MED_HDR10 + 0x32E0C000 + + 0 + 0xFFFF + registers + + + + PIPE1_A0_LUT + A0 component Look-Up-Table. (LUT) + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIPE1_A0_LUT + The LUT entries are 14 bits wide. They my be unsigned integers OR 14-bit floating point numbers + 0 + 14 + read-write + + + + + PIPE1_A1_LUT + A1 component Look-Up-Table. (LUT) + 0x1000 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIPE1_A1_LUT + The LUT entries are 14 bits wide. They my be unsigned integers OR 14-bit floating point numbers + 0 + 14 + read-write + + + + + PIPE1_A2_LUT + A2 component Look-Up-Table. (LUT) + 0x2000 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIPE1_A2_LUT + The LUT entries are 14 bits wide. They my be unsigned integers OR 14-bit floating point numbers + 0 + 14 + read-write + + + + + HDR_PIPE1_CSCA_CONTROL_REG + Pipe1 Colorspace Converter A control. + 0x3000 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + 0: Don't enable this CSC: Pixels pass thru the CSC unmodiifed 1: This CSC is enabled for current picture + 0 + 1 + read-write + + + ENABLE_FOR_ALL_PELS + 0: This CSC is enabled only for blened pixels 1: This CSC is enabled all pixels + 1 + 1 + read-write + + + BYPASS + 0: Don't bypass this CSC 1: Pixels pass thru this CSC unmodiifed + 15 + 1 + read-write + + + + + HDR_PIPE1_CSCA_H00 + Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient + 0x3004 + 32 + read-write + 0 + 0xFFFFFFFF + + + H00 + h(0,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCA_H10 + Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient + 0x3008 + 32 + read-write + 0 + 0xFFFFFFFF + + + H10 + h(1,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCA_H20 + Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient + 0x300C + 32 + read-write + 0 + 0xFFFFFFFF + + + H20 + h(2,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCA_H01 + Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient + 0x3010 + 32 + read-write + 0 + 0xFFFFFFFF + + + H01 + h(0,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCA_H11 + Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient + 0x3014 + 32 + read-write + 0 + 0xFFFFFFFF + + + H11 + h(1,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCA_H21 + Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient + 0x3018 + 32 + read-write + 0 + 0xFFFFFFFF + + + H21 + h(2,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCA_H02 + Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient + 0x301C + 32 + read-write + 0 + 0xFFFFFFFF + + + H02 + h(0,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCA_H12 + Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient + 0x3020 + 32 + read-write + 0 + 0xFFFFFFFF + + + H12 + h(1,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCA_H22 + Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient + 0x3024 + 32 + read-write + 0 + 0xFFFFFFFF + + + H22 + h(2,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCA_IO_0 + Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset + 0x3028 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPO_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 0 of the pixel + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_IO_1 + Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset + 0x302C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 1 of the pixel + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_IO_2 + Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset + 0x3030 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 2 of the pixel + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_IO_MIN_0 + Pipe1 Colorspace Converter A (CSCA) component 0 clip min. + 0x3034 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_IO_MIN_1 + Pipe1 Colorspace Converter A (CSCA) component 1 clip min. + 0x3038 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_IO_MIN_2 + Pipe1 Colorspace Converter A (CSCA) component 2 clip min. + 0x303C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_IO_MAX_0 + Pipe1 Colorspace Converter A (CSCA) component 0 clip max value. + 0x3040 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MAX + This 10-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_IO_MAX_1 + Pipe1 Colorspace Converter A (CSCA) component 1 clip max value. + 0x3044 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MAX + This 10-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_IO_MAX_2 + Pipe1 Colorspace Converter A (CSCA) component 2 clip max value. + 0x3048 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MAX + This 10-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_NORM + Pipe1 Colorspace Converter A (CSCA) normalization factor + 0x304C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCA_NORM + This 5-bit unsigned value is size if arithmetic shift after matrix multiply. + 0 + 5 + read-write + + + + + HDR_PIPE1_CSCA_OO_0 + Pipe1 Colorspace Converter A (CSCA): Post offset component 0 + 0x3050 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCA_OO_0 + Ouput Offset (OO) This is a signed 28-bit number. Per component + 0 + 28 + read-write + + + + + HDR_PIPE1_CSCA_OO_1 + Pipe1 Colorspace Converter A (CSCA): Post offset component 1 + 0x3054 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCA_OO_1 + Ouput Offset (OO) This is a signed 28-bit number. Per component + 0 + 28 + read-write + + + + + HDR_PIPE1_CSCA_OO_2 + Pipe1 Colorspace Converter A (CSCA): Post offset component 2 + 0x3058 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCA_OO_2 + Ouput Offset (OO) This is a signed 28-bit number. Per component + 0 + 28 + read-write + + + + + HDR_PIPE1_CSCA_OMIN_0 + Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0 + 0x305C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_OMIN_1 + Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1 + 0x3060 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_OMIN_2 + Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2 + 0x3064 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_OMAX_0 + Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0 + 0x3068 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_OMAX_1 + Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1 + 0x306C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCA_OMAX_2 + Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2 + 0x3070 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE1_ENTRY_29 + PIPE1: NOT USED + 0x3074 + 32 + read-only + 0 + 0xFFFFFFFF + + + HDR_PIPE1_LUT_CONTROL_REG + Pipe1 LUT control register + 0x3080 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + 0: Don't enable this LUT: Pixels pass thru the LUT unmodiifed 1: This LUT is enabled for current picture + 0 + 1 + read-write + + + ENABLE_FOR_ALL_PELS + 0: This LUT is enabled only for blened pixels 1: This LUT is enabled all pixels + 1 + 1 + read-write + + + BYPASS + 0: Don't bypass this LUT 1: Pixels pass thru this LUT unmodiifed + 15 + 1 + read-write + + + + + HDR_PIPE1_CSCB_CONTROL_REG + Pipe1 Colorspace Converter B control. + 0x3800 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + 0: Don't enable this CSC: Pixels pass thru the CSC unmodiifed 1: This CSC is enabled for current picture + 0 + 1 + read-write + + + ENABLE_FOR_ALL_PELS + 0: This CSC is enabled only for blened pixels 1: This CSC is enabled all pixels + 1 + 1 + read-write + + + BYPASS + 0: Don't bypass this CSC 1: Pixels pass thru this CSC unmodiifed + 15 + 1 + read-write + + + + + HDR_PIPE1_CSCB_H00 + Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient + 0x3804 + 32 + read-write + 0 + 0xFFFFFFFF + + + H00 + h(0,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCB_H10 + Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient + 0x3808 + 32 + read-write + 0 + 0xFFFFFFFF + + + H10 + h(1,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCB_H20 + Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient + 0x380C + 32 + read-write + 0 + 0xFFFFFFFF + + + H20 + h(2,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCB_H01 + Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient + 0x3810 + 32 + read-write + 0 + 0xFFFFFFFF + + + H01 + h(0,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCB_H11 + Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient + 0x3814 + 32 + read-write + 0 + 0xFFFFFFFF + + + H11 + h(1,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCB_H21 + Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient + 0x3818 + 32 + read-write + 0 + 0xFFFFFFFF + + + H21 + h(2,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCB_H02 + Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient + 0x381C + 32 + read-write + 0 + 0xFFFFFFFF + + + H02 + h(0,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCB_H12 + Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient + 0x3820 + 32 + read-write + 0 + 0xFFFFFFFF + + + H12 + h(1,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCB_H22 + Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient + 0x3824 + 32 + read-write + 0 + 0xFFFFFFFF + + + H22 + h(2,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE1_CSCB_IO_0 + Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset + 0x3828 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPO_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 0 of the pixel + 0 + 14 + read-write + + + + + HDR_PIPE1_CSCB_IO_1 + Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset + 0x382C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 1 of the pixel + 0 + 14 + read-write + + + + + HDR_PIPE1_CSCB_IO_2 + Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset + 0x3830 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 2 of the pixel + 0 + 14 + read-write + + + + + HDR_PIPE1_CSCB_IO_MIN_0 + Pipe1 Colorspace Converter B (CSCB) component 0 clip min. + 0x3834 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MIN + This 14-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE1_CSCB_IO_MIN_1 + Pipe1 Colorspace Converter B (CSCB) component 1 clip min. + 0x3838 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MIN + This 14-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE1_CSCB_IO_MIN_2 + Pipe1 Colorspace Converter B (CSCB) component 2 clip min. + 0x383C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE1_CSCB_IO_MAX_0 + Pipe1 Colorspace Converter B (CSCB) component 0 clip max value. + 0x3840 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MAX + This 14-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE1_CSCB_IO_MAX_1 + Pipe1 Colorspace Converter B (CSCB) component 1 clip max value. + 0x3844 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MAX + This 14-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE1_CSCB_IO_MAX_2 + Pipe1 Colorspace Converter B (CSCB) component 2 clip max value. + 0x3848 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MAX + This 14-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE1_CSCB_NORM + Pipe1 Colorspace Converter B (CSCB) normalization factor + 0x384C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCB_NORM + This 5-bit unsigned value is size if arithmetic shift after matrix multiply. + 0 + 5 + read-write + + + + + HDR_PIPE1_CSCB_OO_0 + Pipe1 Colorspace Converter B (CSCB): Post offset component 0 + 0x3850 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCB_OO_0 + Ouput Offset (OO) This is a signed 29-bit number. Per component + 0 + 29 + read-write + + + + + HDR_PIPE1_CSCB_OO_1 + Pipe1 Colorspace Converter B (CSCB): Post offset component 1 + 0x3854 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCB_OO_1 + Ouput Offset (OO) This is a signed 29-bit number. Per component + 0 + 29 + read-write + + + + + HDR_PIPE1_CSCB_OO_2 + Pipe1 Colorspace Converter B (CSCB): Post offset component 2 + 0x3858 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCB_OO_2 + Ouput Offset (OO) This is a signed 29-bit number. Per component + 0 + 29 + read-write + + + + + HDR_PIPE1_CSCB_OMIN_0 + Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0 + 0x385C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE1_CSCB_OMIN_1 + Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1 + 0x3860 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE1_CSCB_OMIN_2 + Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2 + 0x3864 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minimum clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE1_CSCB_OMAX_0 + Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0 + 0x3868 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE1_CSCB_OMAX_1 + Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1 + 0x386C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximun clipped pixel component. + 0 + 10 + read-write + + + + + HDR_PIPE1_CSCB_OMAX_2 + Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2 + 0x3870 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximun clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE1_FL2FX + Pipe1 floating point to fixed point control + 0x3874 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + 0: Don't enable this Float-to-Fixed converter: Pixels pass thru the Float-to-Fixed unmodiifed 1: This Float-to-Fixed converter is enabled for current picture + 0 + 1 + read-write + + + ENABLE_FOR_ALL_PELS + 0: This Float to Fixed operation is enabled only for blended pixels 1: This Float to Fixed operation is enabled all pixels + 1 + 1 + read-write + + + + + HDR_PIPE1_ENTRY_30 + PIPE1: NOT USED + 0x3878 + 32 + read-only + 0 + 0xFFFFFFFF + + + PIPE2_A0_LUT + A0 component Look-Up-Table. (LUT) + 0x4000 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIPE2_A0_LUT + The LUT entries are 14 bits wide. They my be unsigned integers OR 14-bit floating point numbers + 0 + 14 + read-write + + + + + PIPE2_A1_LUT + A1 component Look-Up-Table. (LUT) + 0x5000 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIPE2_A1_LUT + The LUT entries are 14 bits wide. They my be unsigned integers OR 14-bit floating point numbers + 0 + 14 + read-write + + + + + PIPE2_A2_LUT + A2 component Look-Up-Table. (LUT) + 0x6000 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIPE2_A2_LUT + The LUT entries are 14 bits wide. They my be unsigned integers OR 14-bit floating point numbers + 0 + 14 + read-write + + + + + HDR_PIPE2_CSCA_CONTROL_REG + Pipe1 Colorspace Converter A control. + 0x7000 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + 0: Don't enable this CSC: Pixels pass thru the CSC unmodiifed 1: This CSC is enabled for current picture + 0 + 1 + read-write + + + ENABLE_FOR_ALL_PELS + 0: This CSC is enabled only for blened pixels 1: This CSC is enabled all pixels + 1 + 1 + read-write + + + BYPASS + 0: Don't bypass this CSC 1: Pixels pass thru this CSC unmodiifed + 15 + 1 + read-write + + + + + HDR_PIPE2_CSCA_H00 + Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient + 0x7004 + 32 + read-write + 0 + 0xFFFFFFFF + + + H00 + h(0,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCA_H10 + Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient + 0x7008 + 32 + read-write + 0 + 0xFFFFFFFF + + + H10 + h(1,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCA_H20 + Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient + 0x700C + 32 + read-write + 0 + 0xFFFFFFFF + + + H20 + h(2,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCA_H01 + Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient + 0x7010 + 32 + read-write + 0 + 0xFFFFFFFF + + + H01 + h(0,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCA_H11 + Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient + 0x7014 + 32 + read-write + 0 + 0xFFFFFFFF + + + H11 + h(1,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCA_H21 + Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient + 0x7018 + 32 + read-write + 0 + 0xFFFFFFFF + + + H21 + h(2,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCA_H02 + Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient + 0x701C + 32 + read-write + 0 + 0xFFFFFFFF + + + H02 + h(0,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCA_H12 + Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient + 0x7020 + 32 + read-write + 0 + 0xFFFFFFFF + + + H12 + h(1,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCA_H22 + Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient + 0x7024 + 32 + read-write + 0 + 0xFFFFFFFF + + + H22 + h(2,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCA_IO_0 + Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset + 0x7028 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPO_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 0 of the pixel + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_IO_1 + Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset + 0x702C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 1 of the pixel + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_IO_2 + Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset + 0x7030 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 2 of the pixel + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_IO_MIN_0 + Pipe1 Colorspace Converter A (CSCA) component 0 clip min. + 0x7034 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_IO_MIN_1 + Pipe1 Colorspace Converter A (CSCA) component 1 clip min. + 0x7038 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_IO_MIN_2 + Pipe1 Colorspace Converter A (CSCA) component 2 clip min. + 0x703C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_IO_MAX_0 + Pipe1 Colorspace Converter A (CSCA) component 0 clip max value. + 0x7040 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MAX + This 10-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_IO_MAX_1 + Pipe1 Colorspace Converter A (CSCA) component 1 clip max value. + 0x7044 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MAX + This 10-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_IO_MAX_2 + Pipe1 Colorspace Converter A (CSCA) component 2 clip max value. + 0x7048 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MAX + This 10-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_NORM + Pipe1 Colorspace Converter A (CSCA) normalization factor + 0x704C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCA_NORM + This 5-bit unsigned value is size if arithmetic shift after matrix multiply. + 0 + 5 + read-write + + + + + HDR_PIPE2_CSCA_OO_0 + Pipe1 Colorspace Converter A (CSCA): Post offset component 0 + 0x7050 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCA_OO_0 + Ouput Offset (OO) This is a signed 28-bit number. Per component + 0 + 28 + read-write + + + + + HDR_PIPE2_CSCA_OO_1 + Pipe1 Colorspace Converter A (CSCA): Post offset component 1 + 0x7054 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCA_OO_1 + Ouput Offset (OO) This is a signed 28-bit number. Per component + 0 + 28 + read-write + + + + + HDR_PIPE2_CSCA_OO_2 + Pipe1 Colorspace Converter A (CSCA): Post offset component 2 + 0x7058 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCA_OO_2 + Ouput Offset (OO) This is a signed 28-bit number. Per component + 0 + 28 + read-write + + + + + HDR_PIPE2_CSCA_OMIN_0 + Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0 + 0x705C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_OMIN_1 + Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1 + 0x7060 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_OMIN_2 + Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2 + 0x7064 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_OMAX_0 + Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0 + 0x7068 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_OMAX_1 + Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1 + 0x706C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCA_OMAX_2 + Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2 + 0x7070 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE2_ENTRY_29 + PIPE2: NOT USED + 0x7074 + 32 + read-only + 0 + 0xFFFFFFFF + + + HDR_PIPE2_LUT_CONTROL_REG + Pipe1 LUT control register + 0x7080 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + 0: Don't enable this LUT: Pixels pass thru the LUT unmodiifed 1: This LUT is enabled for current picture + 0 + 1 + read-write + + + ENABLE_FOR_ALL_PELS + 0: This LUT is enabled only for blened pixels 1: This LUT is enabled all pixels + 1 + 1 + read-write + + + BYPASS + 0: Don't bypass this LUT 1: Pixels pass thru this LUT unmodiifed + 15 + 1 + read-write + + + + + HDR_PIPE2_CSCB_CONTROL_REG + Pipe1 Colorspace Converter B control. + 0x7800 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + 0: Don't enable this CSC: Pixels pass thru the CSC unmodiifed 1: This CSC is enabled for current picture + 0 + 1 + read-write + + + ENABLE_FOR_ALL_PELS + 0: This CSC is enabled only for blened pixels 1: This CSC is enabled all pixels + 1 + 1 + read-write + + + BYPASS + 0: Don't bypass this CSC 1: Pixels pass thru this CSC unmodiifed + 15 + 1 + read-write + + + + + HDR_PIPE2_CSCB_H00 + Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient + 0x7804 + 32 + read-write + 0 + 0xFFFFFFFF + + + H00 + h(0,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCB_H10 + Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient + 0x7808 + 32 + read-write + 0 + 0xFFFFFFFF + + + H10 + h(1,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCB_H20 + Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient + 0x780C + 32 + read-write + 0 + 0xFFFFFFFF + + + H20 + h(2,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCB_H01 + Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient + 0x7810 + 32 + read-write + 0 + 0xFFFFFFFF + + + H01 + h(0,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCB_H11 + Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient + 0x7814 + 32 + read-write + 0 + 0xFFFFFFFF + + + H11 + h(1,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCB_H21 + Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient + 0x7818 + 32 + read-write + 0 + 0xFFFFFFFF + + + H21 + h(2,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCB_H02 + Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient + 0x781C + 32 + read-write + 0 + 0xFFFFFFFF + + + H02 + h(0,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCB_H12 + Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient + 0x7820 + 32 + read-write + 0 + 0xFFFFFFFF + + + H12 + h(1,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCB_H22 + Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient + 0x7824 + 32 + read-write + 0 + 0xFFFFFFFF + + + H22 + h(2,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE2_CSCB_IO_0 + Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset + 0x7828 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPO_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 0 of the pixel + 0 + 14 + read-write + + + + + HDR_PIPE2_CSCB_IO_1 + Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset + 0x782C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 1 of the pixel + 0 + 14 + read-write + + + + + HDR_PIPE2_CSCB_IO_2 + Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset + 0x7830 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 2 of the pixel + 0 + 14 + read-write + + + + + HDR_PIPE2_CSCB_IO_MIN_0 + Pipe1 Colorspace Converter B (CSCB) component 0 clip min. + 0x7834 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MIN + This 14-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE2_CSCB_IO_MIN_1 + Pipe1 Colorspace Converter B (CSCB) component 1 clip min. + 0x7838 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MIN + This 14-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE2_CSCB_IO_MIN_2 + Pipe1 Colorspace Converter B (CSCB) component 2 clip min. + 0x783C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE2_CSCB_IO_MAX_0 + Pipe1 Colorspace Converter B (CSCB) component 0 clip max value. + 0x7840 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MAX + This 14-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE2_CSCB_IO_MAX_1 + Pipe1 Colorspace Converter B (CSCB) component 1 clip max value. + 0x7844 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MAX + This 14-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE2_CSCB_IO_MAX_2 + Pipe1 Colorspace Converter B (CSCB) component 2 clip max value. + 0x7848 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MAX + This 14-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE2_CSCB_NORM + Pipe1 Colorspace Converter B (CSCB) normalization factor + 0x784C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCB_NORM + This 5-bit unsigned value is size if arithmetic shift after matrix multiply. + 0 + 5 + read-write + + + + + HDR_PIPE2_CSCB_OO_0 + Pipe1 Colorspace Converter B (CSCB): Post offset component 0 + 0x7850 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCB_OO_0 + Ouput Offset (OO) This is a signed 29-bit number. Per component + 0 + 29 + read-write + + + + + HDR_PIPE2_CSCB_OO_1 + Pipe1 Colorspace Converter B (CSCB): Post offset component 1 + 0x7854 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCB_OO_1 + Ouput Offset (OO) This is a signed 29-bit number. Per component + 0 + 29 + read-write + + + + + HDR_PIPE2_CSCB_OO_2 + Pipe1 Colorspace Converter B (CSCB): Post offset component 2 + 0x7858 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCB_OO_2 + Ouput Offset (OO) This is a signed 29-bit number. Per component + 0 + 29 + read-write + + + + + HDR_PIPE2_CSCB_OMIN_0 + Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0 + 0x785C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE2_CSCB_OMIN_1 + Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1 + 0x7860 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE2_CSCB_OMIN_2 + Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2 + 0x7864 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minimum clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE2_CSCB_OMAX_0 + Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0 + 0x7868 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE2_CSCB_OMAX_1 + Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1 + 0x786C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximun clipped pixel component. + 0 + 10 + read-write + + + + + HDR_PIPE2_CSCB_OMAX_2 + Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2 + 0x7870 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximun clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE2_FL2FX + Pipe1 floating point to fixed point control + 0x7874 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + 0: Don't enable this Float-to-Fixed converter: Pixels pass thru the Float-to-Fixed unmodiifed 1: This Float-to-Fixed converter is enabled for current picture + 0 + 1 + read-write + + + ENABLE_FOR_ALL_PELS + 0: This Float to Fixed operation is enabled only for blended pixels 1: This Float to Fixed operation is enabled all pixels + 1 + 1 + read-write + + + + + HDR_PIPE2_ENTRY_30 + PIPE2: NOT USED + 0x7878 + 32 + read-only + 0 + 0xFFFFFFFF + + + PIPE3_A0_LUT + A0 component Look-Up-Table. (LUT) + 0x8000 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIPE3_A0_LUT + The LUT entries are 14 bits wide. They my be unsigned integers OR 14-bit floating point numbers + 0 + 14 + read-write + + + + + PIPE3_A1_LUT + A1 component Look-Up-Table. (LUT) + 0x9000 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIPE3_A1_LUT + The LUT entries are 14 bits wide. They my be unsigned integers OR 14-bit floating point numbers + 0 + 14 + read-write + + + + + PIPE3_A2_LUT + A2 component Look-Up-Table. (LUT) + 0xA000 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIPE3_A2_LUT + The LUT entries are 14 bits wide. They my be unsigned integers OR 14-bit floating point numbers + 0 + 14 + read-write + + + + + HDR_PIPE3_CSCA_CONTROL_REG + Pipe1 Colorspace Converter A control. + 0xB000 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + 0: Don't enable this CSC: Pixels pass thru the CSC unmodiifed 1: This CSC is enabled for current picture + 0 + 1 + read-write + + + ENABLE_FOR_ALL_PELS + 0: This CSC is enabled only for blened pixels 1: This CSC is enabled all pixels + 1 + 1 + read-write + + + BYPASS + 0: Don't bypass this CSC 1: Pixels pass thru this CSC unmodiifed + 15 + 1 + read-write + + + + + HDR_PIPE3_CSCA_H00 + Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient + 0xB004 + 32 + read-write + 0 + 0xFFFFFFFF + + + H00 + h(0,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCA_H10 + Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient + 0xB008 + 32 + read-write + 0 + 0xFFFFFFFF + + + H10 + h(1,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCA_H20 + Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient + 0xB00C + 32 + read-write + 0 + 0xFFFFFFFF + + + H20 + h(2,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCA_H01 + Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient + 0xB010 + 32 + read-write + 0 + 0xFFFFFFFF + + + H01 + h(0,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCA_H11 + Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient + 0xB014 + 32 + read-write + 0 + 0xFFFFFFFF + + + H11 + h(1,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCA_H21 + Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient + 0xB018 + 32 + read-write + 0 + 0xFFFFFFFF + + + H21 + h(2,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCA_H02 + Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient + 0xB01C + 32 + read-write + 0 + 0xFFFFFFFF + + + H02 + h(0,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCA_H12 + Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient + 0xB020 + 32 + read-write + 0 + 0xFFFFFFFF + + + H12 + h(1,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCA_H22 + Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient + 0xB024 + 32 + read-write + 0 + 0xFFFFFFFF + + + H22 + h(2,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCA_IO_0 + Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset + 0xB028 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPO_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 0 of the pixel + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_IO_1 + Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset + 0xB02C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 1 of the pixel + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_IO_2 + Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset + 0xB030 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 2 of the pixel + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_IO_MIN_0 + Pipe1 Colorspace Converter A (CSCA) component 0 clip min. + 0xB034 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_IO_MIN_1 + Pipe1 Colorspace Converter A (CSCA) component 1 clip min. + 0xB038 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_IO_MIN_2 + Pipe1 Colorspace Converter A (CSCA) component 2 clip min. + 0xB03C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_IO_MAX_0 + Pipe1 Colorspace Converter A (CSCA) component 0 clip max value. + 0xB040 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MAX + This 10-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_IO_MAX_1 + Pipe1 Colorspace Converter A (CSCA) component 1 clip max value. + 0xB044 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MAX + This 10-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_IO_MAX_2 + Pipe1 Colorspace Converter A (CSCA) component 2 clip max value. + 0xB048 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MAX + This 10-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_NORM + Pipe1 Colorspace Converter A (CSCA) normalization factor + 0xB04C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCA_NORM + This 5-bit unsigned value is size if arithmetic shift after matrix multiply. + 0 + 5 + read-write + + + + + HDR_PIPE3_CSCA_OO_0 + Pipe1 Colorspace Converter A (CSCA): Post offset component 0 + 0xB050 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCA_OO_0 + Ouput Offset (OO) This is a signed 28-bit number. Per component + 0 + 28 + read-write + + + + + HDR_PIPE3_CSCA_OO_1 + Pipe1 Colorspace Converter A (CSCA): Post offset component 1 + 0xB054 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCA_OO_1 + Ouput Offset (OO) This is a signed 28-bit number. Per component + 0 + 28 + read-write + + + + + HDR_PIPE3_CSCA_OO_2 + Pipe1 Colorspace Converter A (CSCA): Post offset component 2 + 0xB058 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCA_OO_2 + Ouput Offset (OO) This is a signed 28-bit number. Per component + 0 + 28 + read-write + + + + + HDR_PIPE3_CSCA_OMIN_0 + Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0 + 0xB05C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_OMIN_1 + Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1 + 0xB060 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_OMIN_2 + Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2 + 0xB064 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_OMAX_0 + Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0 + 0xB068 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_OMAX_1 + Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1 + 0xB06C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCA_OMAX_2 + Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2 + 0xB070 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_PIPE3_ENTRY_29 + PIPE3: NOT USED + 0xB074 + 32 + read-only + 0 + 0xFFFFFFFF + + + HDR_PIPE3_LUT_CONTROL_REG + Pipe1 LUT control register + 0xB080 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + 0: Don't enable this LUT: Pixels pass thru the LUT unmodiifed 1: This LUT is enabled for current picture + 0 + 1 + read-write + + + ENABLE_FOR_ALL_PELS + 0: This LUT is enabled only for blened pixels 1: This LUT is enabled all pixels + 1 + 1 + read-write + + + BYPASS + 0: Don't bypass this LUT 1: Pixels pass thru this LUT unmodiifed + 15 + 1 + read-write + + + + + HDR_PIPE3_CSCB_CONTROL_REG + Pipe1 Colorspace Converter B control. + 0xB800 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + 0: Don't enable this CSC: Pixels pass thru the CSC unmodiifed 1: This CSC is enabled for current picture + 0 + 1 + read-write + + + ENABLE_FOR_ALL_PELS + 0: This CSC is enabled only for blened pixels 1: This CSC is enabled all pixels + 1 + 1 + read-write + + + BYPASS + 0: Don't bypass this CSC 1: Pixels pass thru this CSC unmodiifed + 15 + 1 + read-write + + + + + HDR_PIPE3_CSCB_H00 + Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient + 0xB804 + 32 + read-write + 0 + 0xFFFFFFFF + + + H00 + h(0,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCB_H10 + Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient + 0xB808 + 32 + read-write + 0 + 0xFFFFFFFF + + + H10 + h(1,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCB_H20 + Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient + 0xB80C + 32 + read-write + 0 + 0xFFFFFFFF + + + H20 + h(2,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCB_H01 + Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient + 0xB810 + 32 + read-write + 0 + 0xFFFFFFFF + + + H01 + h(0,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCB_H11 + Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient + 0xB814 + 32 + read-write + 0 + 0xFFFFFFFF + + + H11 + h(1,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCB_H21 + Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient + 0xB818 + 32 + read-write + 0 + 0xFFFFFFFF + + + H21 + h(2,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCB_H02 + Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient + 0xB81C + 32 + read-write + 0 + 0xFFFFFFFF + + + H02 + h(0,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCB_H12 + Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient + 0xB820 + 32 + read-write + 0 + 0xFFFFFFFF + + + H12 + h(1,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCB_H22 + Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient + 0xB824 + 32 + read-write + 0 + 0xFFFFFFFF + + + H22 + h(2,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_PIPE3_CSCB_IO_0 + Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset + 0xB828 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPO_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 0 of the pixel + 0 + 14 + read-write + + + + + HDR_PIPE3_CSCB_IO_1 + Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset + 0xB82C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 1 of the pixel + 0 + 14 + read-write + + + + + HDR_PIPE3_CSCB_IO_2 + Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset + 0xB830 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 2 of the pixel + 0 + 14 + read-write + + + + + HDR_PIPE3_CSCB_IO_MIN_0 + Pipe1 Colorspace Converter B (CSCB) component 0 clip min. + 0xB834 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MIN + This 14-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE3_CSCB_IO_MIN_1 + Pipe1 Colorspace Converter B (CSCB) component 1 clip min. + 0xB838 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MIN + This 14-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE3_CSCB_IO_MIN_2 + Pipe1 Colorspace Converter B (CSCB) component 2 clip min. + 0xB83C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE3_CSCB_IO_MAX_0 + Pipe1 Colorspace Converter B (CSCB) component 0 clip max value. + 0xB840 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MAX + This 14-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE3_CSCB_IO_MAX_1 + Pipe1 Colorspace Converter B (CSCB) component 1 clip max value. + 0xB844 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MAX + This 14-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE3_CSCB_IO_MAX_2 + Pipe1 Colorspace Converter B (CSCB) component 2 clip max value. + 0xB848 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MAX + This 14-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 14 + read-write + + + + + HDR_PIPE3_CSCB_NORM + Pipe1 Colorspace Converter B (CSCB) normalization factor + 0xB84C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCB_NORM + This 5-bit unsigned value is size if arithmetic shift after matrix multiply. + 0 + 5 + read-write + + + + + HDR_PIPE3_CSCB_OO_0 + Pipe1 Colorspace Converter B (CSCB): Post offset component 0 + 0xB850 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCB_OO_0 + Ouput Offset (OO) This is a signed 29-bit number. Per component + 0 + 29 + read-write + + + + + HDR_PIPE3_CSCB_OO_1 + Pipe1 Colorspace Converter B (CSCB): Post offset component 1 + 0xB854 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCB_OO_1 + Ouput Offset (OO) This is a signed 29-bit number. Per component + 0 + 29 + read-write + + + + + HDR_PIPE3_CSCB_OO_2 + Pipe1 Colorspace Converter B (CSCB): Post offset component 2 + 0xB858 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSCB_OO_2 + Ouput Offset (OO) This is a signed 29-bit number. Per component + 0 + 29 + read-write + + + + + HDR_PIPE3_CSCB_OMIN_0 + Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0 + 0xB85C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE3_CSCB_OMIN_1 + Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1 + 0xB860 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE3_CSCB_OMIN_2 + Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2 + 0xB864 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minimum clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE3_CSCB_OMAX_0 + Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0 + 0xB868 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE3_CSCB_OMAX_1 + Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1 + 0xB86C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximun clipped pixel component. + 0 + 10 + read-write + + + + + HDR_PIPE3_CSCB_OMAX_2 + Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2 + 0xB870 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximun clipped pixel component. + 0 + 28 + read-write + + + + + HDR_PIPE3_FL2FX + Pipe1 floating point to fixed point control + 0xB874 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + 0: Don't enable this Float-to-Fixed converter: Pixels pass thru the Float-to-Fixed unmodiifed 1: This Float-to-Fixed converter is enabled for current picture + 0 + 1 + read-write + + + ENABLE_FOR_ALL_PELS + 0: This Float to Fixed operation is enabled only for blended pixels 1: This Float to Fixed operation is enabled all pixels + 1 + 1 + read-write + + + + + HDR_PIPE3_ENTRY_30 + PIPE3: NOT USED + 0xB878 + 32 + read-only + 0 + 0xFFFFFFFF + + + OPIPE_A0_TABLE + A0 component Linear-to-Non-linear conversion table + 0xC000 + 32 + read-write + 0 + 0xFFFFFFFF + + + OPIPE_A0_TABLE + The TABLE Nodes are 14 bits wide. They my be unsigned integers OR 14-bit floating point numbers + 0 + 14 + read-write + + + + + OPIPE_A1_TABLE + A1 component Linear-to-Non-linear conversion table + 0xD000 + 32 + read-write + 0 + 0xFFFFFFFF + + + OPIPE_A1_TABLE + The TABLE Nodes are 14 bits wide. They my be unsigned integers OR 14-bit floating point numbers + 0 + 14 + read-write + + + + + OPIPE_A2_TABLE + A2 component Linear-to-Non-linear conversion table + 0xE000 + 32 + read-write + 0 + 0xFFFFFFFF + + + OPIPE_A2_TABLE + The TABLE Nodes are 14 bits wide. They my be unsigned integers OR 14-bit floating point numbers + 0 + 14 + read-write + + + + + HDR_OPIPE_CSC_CONTROL_REG + HDR output stage Colorspace Converter (CSCO) control. + 0xF000 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + 0: Don't enable this CSC: Pixels pass thru the CSC unmodiifed 1: This CSC is enabled for current picture + 0 + 1 + read-write + + + ENABLE_FOR_ALL_PELS + 0: This CSC is enabled only for blened pixels 1: This CSC is enabled all pixels + 1 + 1 + read-write + + + BYPASS + 0: Don't bypass this CSC 1: Pixels pass thru this CSC unmodiifed + 15 + 1 + read-write + + + + + HDR_OPIPE_CSC_H00 + Pipe1 Colorspace Converter (CSC) h(0,0) matrix coefficient + 0xF004 + 32 + read-write + 0 + 0xFFFFFFFF + + + H00 + h(0,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_OPIPE_CSC_H10 + Pipe1 Colorspace Converter (CSC) h(1,0) matrix coefficient + 0xF008 + 32 + read-write + 0 + 0xFFFFFFFF + + + H10 + h(1,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_OPIPE_CSC_H20 + HDR OUTPUT Colorspace Converter (CSCO) h(2,0) matrix coefficient + 0xF00C + 32 + read-write + 0 + 0xFFFFFFFF + + + H20 + h(2,0) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_OPIPE_CSC_H01 + HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,1) matrix coefficient + 0xF010 + 32 + read-write + 0 + 0xFFFFFFFF + + + H01 + h(0,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_OPIPE_CSC_H11 + HDR OUTPUT pipe Colorspace Converter (CSCO) h(1,1) matrix coefficient + 0xF014 + 32 + read-write + 0 + 0xFFFFFFFF + + + H11 + h(1,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_OPIPE_CSC_H21 + HDR_output pipe Colorspace Converter (CSCO) h(2,1) matrix coefficient + 0xF018 + 32 + read-write + 0 + 0xFFFFFFFF + + + H21 + h(2,1) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_OPIPE_CSC_H02 + HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,2) matrix coefficient + 0xF01C + 32 + read-write + 0 + 0xFFFFFFFF + + + H02 + h(0,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_OPIPE_CSC_H12 + HDR OUPUT pipe Colorspace Converter (CSCO) h(1,2) matrix coefficient + 0xF020 + 32 + read-write + 0 + 0xFFFFFFFF + + + H12 + h(1,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_ + HDR OUPUT pipe Colorspace Converter (CSCO) h(2,2) matrix coefficient + 0xF024 + 32 + read-write + 0 + 0xFFFFFFFF + + + H22 + h(2,2) 16 bit signed coefficient + 0 + 16 + read-write + + + + + HDR_OPIPE_CSC_IO_0 + HDR OUTPUT pipe Colorspace Converter (CSCO) component 0 pre-offset + 0xF028 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPO_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 0 of the pixel + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_IO_1 + HDR OUPTUT pipe Colorspace Converter (CSCO) component 1 pre-offset + 0xF02C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 1 of the pixel + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_IO_2 + HDR OUPUT pipe: Colorspace Converter (CSCO) component 2 pre-offset + 0xF030 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_PRE_OFFSET + Before the color space conversion matrix multiply, This offset is added to component 2 of the pixel + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_MIN_0 + HDR OUPTU pipe Colorspace Converter (CSCO) component 0 clip min. + 0xF034 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_MIN_1 + HDR OUPUT pipe Colorspace Converter (CSCO) component 1 clip min. + 0xF038 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_MIN_2 + HDR OUPTU pipe Colorspace Converter (CSCO) component 2 clip min. + 0xF03C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MIN + This 10-bit signed value is the minimum value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_MAX_0 + HDR OUPTUT pipe Colorspace Converter O (CSC) component 0 clip max value. + 0xF040 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP0_CLIP_MAX + This 10-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_MAX_1 + HDR OUTPUT pipe Colorspace Converter (CSCO) component 1 clip max value. + 0xF044 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP1_CLIP_MAX + This 10-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_MAX_2 + HDR OUTPUT pipe Colorspace Converter (CSCO) component 2 clip max value. + 0xF048 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP2_CLIP_MAX + This 10-bit unsigned value is the maximun value of pixel component after the pre-increment. + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_NORM + HDR OUPUT pipe Colorspace Converter (CSCO) normalization factor + 0xF04C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSC_NORM + This 5-bit unsigned value is size if arithmetic shift after matrix multiply. + 0 + 5 + read-write + + + + + HDR_OPIPE_CSC_OO_0 + HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 0 + 0xF050 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSC_OO_0 + Ouput Offset (OO) This is a signed 28-bit number. Per component + 0 + 28 + read-write + + + + + HDR_OPIPE_CSC_OO_1 + HDR OUTPUT pipe Colorspace Converter (CSC): Post offset component 1 + 0xF054 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSC_OO_1 + Ouput Offset (OO) This is a signed 28-bit number. Per component + 0 + 28 + read-write + + + + + HDR_OPIPE_CSC_OO_2 + HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 2 + 0xF058 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSC_OO_2 + Ouput Offset (OO) This is a signed 28-bit number. Per component + 0 + 28 + read-write + + + + + HDR_OPIPE_CSC_OMIN_0 + HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 0 + 0xF05C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_OMIN_1 + HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 1 + 0xF060 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_OMIN_2 + HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 2 + 0xF064 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MIN + Minum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_OMAX_0 + HDR OUPTUT pipe Colorspace Converter (CSC): Post offset max clip value for component 0 + 0xF068 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_OMAX_1 + HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 1 + 0xF06C + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_OPIPE_CSC_OMAX_2 + HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 2 + 0xF070 + 32 + read-write + 0 + 0xFFFFFFFF + + + POST_OFF_MAX + Maximum clipped pixel component. [0-1023] + 0 + 10 + read-write + + + + + HDR_OPIPE_2NL_CONTROL_REG + HDR OUTPUT -TO NON LINEAR pipeline control + 0xF874 + 32 + read-write + 0 + 0xFFFFFFFF + + + PASS_THRU + 0: Process the pixels with linear to non-linear pipeline 1: Pass the data through the linear to non-linear pipeline unmodified + 0 + 1 + read-write + + + DISABLE_FIXED_TO_FLOAT + 0: The 28 bit input component is converted to floating point format to be processed by the linear to non-linear converter 1: The 28 bit fixed point number is truncated to 14 bits and passed the passed to the linear to non linear pipe + 1 + 1 + read-write + + + LTNL_ENABLE_FOR_ALL_PELS + 0: When 0 linear_to_non linear conversion is enabled for blended pels 1: When 1 linear_to_non linear conversion is enabled for all pels + 2 + 1 + read-write + + + FIX2FLT_ENABLE_FOR_ALL_PELS + 0: fixed-to_float is enabled for blended pels 1: fixed-to_float is enabled for all pels + 3 + 1 + read-write + + + + + + + DCSS__DEC400D + DEC400D + DEC400D + 0x32E15000 + + 0 + 0xE80 + registers + + + + GCCHIPREV + Revision ID + 0x24 + 32 + read-only + 0 + 0 + + + GCCHIPREV + Revision ID + 0 + 32 + read-only + + + + + GCCHIPDATE + Release Date + 0x28 + 32 + read-only + 0 + 0 + + + GCCHIPDATE + Date + 0 + 32 + read-only + + + + + GCREGHICHIPPATCHREV + Patch Revision + 0x98 + 32 + read-only + 0 + 0 + + + GCREGHICHIPPATCHREV + Product ID + 0 + 32 + read-only + + + + + GCPRODUCTID + Product ID + 0xA8 + 32 + read-only + 0 + 0 + + + GCPRODUCTID + Product ID + 0 + 32 + read-only + + + + + 32 + 0x4 + GCREGAHBDECREADCONFIG[%s] + Decode Read Configuration + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPRESSION_ENABLE + Compression Enable + 0 + 1 + read-write + + + COMPRESSION_ENABLE_0 + Disable + 0 + + + COMPRESSION_ENABLE_1 + Enable + 0x1 + + + + + COMPRESSION_FORMAT + Compression Format + 3 + 5 + read-write + + + COMPRESSION_FORMAT_0 + ARGB8 + 0 + + + + + COMPRESSION_ALIGN_MODE + Compression Align Mode + 16 + 2 + read-write + + + COMPRESSION_ALIGN_MODE_0 + ALIGN1_BYTE + 0 + + + COMPRESSION_ALIGN_MODE_1 + ALIGN16_BYTE + 0x1 + + + COMPRESSION_ALIGN_MODE_2 + ALIGN32_BYTE + 0x2 + + + COMPRESSION_ALIGN_MODE_3 + ALIGN64_BYTE + 0x3 + + + + + TILE_ALIGN_MODE + Tile Align Mode + 22 + 3 + read-write + + + TILE_ALIGN_MODE_0 + TILE1_ALIGN + 0 + + + TILE_ALIGN_MODE_1 + TILE2_ALIGN + 0x1 + + + TILE_ALIGN_MODE_2 + TILE4_ALIGN + 0x2 + + + TILE_ALIGN_MODE_3 + CBSR_ALIGN + 0x3 + + + + + TILE_MODE + Tile Mode + 25 + 5 + read-write + + + TILE_MODE_0 + TILE8X8_XMAJOR + 0 + + + TILE_MODE_1 + TILE8X8_YMAJOR + 0x1 + + + TILE_MODE_2 + TILE16X4 + 0x2 + + + TILE_MODE_3 + TILE8X4 + 0x3 + + + TILE_MODE_4 + TILE4X8 + 0x4 + + + TILE_MODE_5 + TILE4X4 + 0x5 + + + TILE_MODE_6 + RASTER16X4 + 0x6 + + + TILE_MODE_7 + TILE64X4 + 0x7 + + + TILE_MODE_8 + TILE32X4 + 0x8 + + + TILE_MODE_9 + RASTER256X1 + 0x9 + + + TILE_MODE_10 + RASTER128X1 + 0xA + + + TILE_MODE_11 + RASTER64X4 + 0xB + + + TILE_MODE_12 + RASTER256X2 + 0xC + + + TILE_MODE_13 + RASTER128X2 + 0xD + + + TILE_MODE_14 + RASTER128X4 + 0xE + + + TILE_MODE_15 + RASTER64X1 + 0xF + + + + + + + 32 + 0x4 + GCREGAHBDECREADBUFFERBASE[%s] + Decode Read Buffer Base + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_ADDRESS + Base address for pixel buffer for read ID. + 0 + 32 + read-write + + + + + 32 + 0x4 + GCREGAHBDECREADCACHEBASE[%s] + Decode Read Cache Base + 0x980 + 32 + read-write + 0 + 0xFFFFFFFF + + + CACHE_ADDRESS + Base address for tile status buffer for read ID. + 0 + 32 + read-write + + + + + GCREGAHBDECCONTROL + Dec400D Control + 0xB00 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLUSH + Flush tile status cache. + 0 + 1 + read-write + + + FLUSH_0 + Disable + 0 + + + FLUSH_1 + Enable + 0x1 + + + + + DISABLE_COMPRESSION + Bypass compression for all streams. + 1 + 1 + read-write + + + DISABLE_COMPRESSION_0 + Disable + 0 + + + DISABLE_COMPRESSION_1 + Enable + 0x1 + + + + + DISABLE_RAM_CLOCK_GATING + Disable clock gating for RAMs. + 2 + 1 + read-write + + + DISABLE_RAM_CLOCK_GATING_0 + Disable + 0 + + + DISABLE_RAM_CLOCK_GATING_1 + Enable + 0x1 + + + + + DISABLE_DEBUG_REGISTERS + Disable debug registers. + 3 + 1 + read-write + + + DISABLE_DEBUG_REGISTERS_0 + Disable + 0 + + + DISABLE_DEBUG_REGISTERS_1 + Enable + 0x1 + + + + + SOFT_RESET + Soft reset the Dec400D. + 4 + 1 + read-write + + + SOFT_RESET_0 + Disable + 0 + + + SOFT_RESET_1 + Enable + 0x1 + + + + + TILE_STATUS_READ_ID + Tile status cache's AXI read ID. + 6 + 5 + read-write + + + DISABLE_HW_FLUSH + Tile status cache flush through frame end pin is disabled. + 16 + 1 + read-write + + + DISABLE_HW_FLUSH_0 + Disable + 0 + + + DISABLE_HW_FLUSH_1 + Enable + 0x1 + + + + + CLK_DIS + Disable clock. + 17 + 1 + read-write + + + CLK_DIS_0 + Disable + 0 + + + CLK_DIS_1 + Enable + 0x1 + + + + + SW_FLUSH_ID + ID of tile status flush. + 18 + 6 + read-write + + + DISABLE_MODULE_CLOCK_GATING + Disable clock gating for sub modules + 30 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_0 + Disable + 0 + + + DISABLE_MODULE_CLOCK_GATING_1 + Enable + 0x1 + + + + + + + GCREGAHBDECINTRACKNOWLEDGE + Interrupt Acknowledge + 0xB04 + 32 + read-only + 0 + 0xFFFFFFFF + + + INTR_VEC + Interrupt vector + 0 + 32 + read-only + + + + + GCREGAHBDECINTRENBL + Interrupt Enable + 0xB08 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTR_ENBL_VEC + Interrupt enable vector + 0 + 32 + read-write + + + + + GCREGAHBDECTILESTATUSDEBUG + Tile Status Module Debug + 0xB0C + 32 + read-only + 0 + 0xFFFFFFFF + + + TILE_DEBUG + Debug + 0 + 32 + read-only + + + + + GCREGAHBDECDECODERDEBUG + Decompression Module Debug + 0xB14 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEC_DEBUG + Debug + 0 + 32 + read-only + + + + + GCREGAHBDECTOTALREADSIN + Total Reads In + 0xB18 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDIN_COUNT + Count + 0 + 32 + read-only + + + + + GCREGAHBDECTOTALREADBURSTSIN + Total Read Data Count + 0xB20 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDIN_BURST_COUNT + Count + 0 + 32 + read-only + + + + + GCREGAHBDECTOTALREADREQIN + Total Read Request In + 0xB28 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDIN_REQ_COUNT + Count + 0 + 32 + read-only + + + + + GCREGAHBDECTOTALREADLASTSIN + Total Input Read Last Number + 0xB30 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDIN_LAST_COUNT + Count + 0 + 32 + read-only + + + + + GCREGAHBDECTOTALREADSOUT + Total Reads Out + 0xB38 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDOUT_COUNT + Count + 0 + 32 + read-only + + + + + GCREGAHBDECTOTALREADBURSTSOUT + Total Read Bursts Out + 0xB40 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDOUT_BURST_COUNT + Count + 0 + 32 + read-only + + + + + GCREGAHBDECTOTALREADREQOUT + Total Read Request Out + 0xB48 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDOUT_REQ_COUNT + Count + 0 + 32 + read-only + + + + + GCREGAHBDECTOTALREADLASTSOUT + Total Read Last Out + 0xB50 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDOUT_LAST_COUNT + Count + 0 + 32 + read-only + + + + + GCREGAHBDECDEBUG0 + Debug Register 0 + 0xB58 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEBUG0 + Debug register 0 + 0 + 32 + read-only + + + + + GCREGAHBDECDEBUG1 + Debug Register 1 + 0xB5C + 32 + read-only + 0 + 0xFFFFFFFF + + + DEBUG1 + Debug 1 + 0 + 32 + read-only + + + + + GCREGAHBDECDEBUG2 + Debug register 2 + 0xB60 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEBUG2 + Debug 2 + 0 + 32 + read-only + + + + + GCREGAHBDECDEBUG3 + Debug Register 3 + 0xB64 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEBUG3 + Debug 3 + 0 + 32 + read-only + + + + + GCREGAHBDECCONTROLEX + GCREGAHBDECCONTROLEX + 0xB68 + 32 + read-write + 0 + 0xFFFFFFFF + + + GCREGAHBDECCONTROLEX + GCREGAHBDECCONTROLEX + 0 + 32 + read-write + + + + + GCREGAHBDECSTATECOMMIT + GCREGAHBDECSTATECOMMIT + 0xB6C + 32 + read-write + 0 + 0xFFFFFFFF + + + GCREGAHBDECSTATECOMMIT + GCREGAHBDECSTATECOMMIT + 0 + 32 + read-write + + + + + GCREGAHBDECSTATELOCK + GCREGAHBDECSTATELOCK + 0xB70 + 32 + read-only + 0 + 0xFFFFFFFF + + + GCREGAHBDECSTATELOCK + GCREGAHBDECSTATELOCK + 0 + 32 + read-only + + + + + 32 + 0x4 + GCREGAHBDECREADEXCONFIG[%s] + Decode Read Extra Configuration + 0xC00 + 32 + read-write + 0 + 0xFFFFFFFF + + + CBSR_WIDTH + CBSR width + 3 + 13 + read-write + + + BIT_DEPTH + Bit depth + 16 + 3 + read-write + + + BIT_DEPTH_0 + 8 bit + 0 + + + BIT_DEPTH_1 + 10 bit + 0x1 + + + BIT_DEPTH_2 + 12 bit + 0x2 + + + BIT_DEPTH_3 + 16 bit + 0x3 + + + + + TILE_Y + Tile Y + 19 + 1 + read-write + + + TILE_Y_0 + Disable + 0 + + + TILE_Y_1 + Enable + 0x1 + + + + + STREAM_MODE + Stream mode + 20 + 5 + read-write + + + STREAM_MODE_0 + Default + 0 + + + STREAM_MODE_1 + ISA_STREAM0 + 0x1 + + + STREAM_MODE_2 + ISA_STREAM1 + 0x2 + + + STREAM_MODE_3 + ISA_STREAM2 + 0x3 + + + STREAM_MODE_4 + ISA_STREAM3 + 0x4 + + + STREAM_MODE_5 + TNR_STREAM_Y + 0x5 + + + STREAM_MODE_6 + TNR_STREAM_UV + 0x6 + + + STREAM_MODE_7 + GDC_STREAM_Y + 0x7 + + + STREAM_MODE_8 + GDC_STREAM_U + 0x8 + + + STREAM_MODE_9 + GDC_STREAM_V + 0x9 + + + STREAM_MODE_10 + VPU_SRC_Y + 0xA + + + STREAM_MODE_11 + VPR_SRC_UV + 0xB + + + STREAM_MODE_12 + VPU_REF_Y + 0xC + + + STREAM_MODE_13 + VPU_REF_UV + 0xD + + + STREAM_MODE_14 + XYZ_STREAM_AY + 0xE + + + STREAM_MODE_15 + XYZ_STREAM_AU + 0xF + + + STREAM_MODE_16 + XYZ_STREAM_AV + 0x10 + + + STREAM_MODE_17 + XYZ_STREAM_BY + 0x11 + + + STREAM_MODE_18 + XYZ_STREAM_BU + 0x12 + + + STREAM_MODE_19 + XYZ_STREAM_BV + 0x13 + + + + + TS_CACHE_READ_MODE + TS cache read mode + 26 + 1 + read-write + + + TS_CACHE_READ_MODE_0 + Disable + 0 + + + TS_CACHE_READ_MODE_1 + Enable + 0x1 + + + + + PIXEL_CACHE_REPLACEMENT + Pixel cache replacement + 27 + 1 + read-write + + + PIXEL_CACHE_REPLACEMENT_0 + LRU + 0 + + + PIXEL_CACHE_REPLACEMENT_1 + FIFO + 0x1 + + + + + INTEL_P010 + Intel's P010 format + 28 + 1 + read-write + + + INTEL_P010_0 + Disable + 0 + + + INTEL_P010_1 + Enable + 0x1 + + + + + TS_CACHE_REPLACEMENT + TS cache replacement + 29 + 1 + read-write + + + TS_CACHE_REPLACEMENT_0 + LRU + 0 + + + TS_CACHE_REPLACEMENT_1 + FIFO + 0x1 + + + + + + + 32 + 0x4 + GCREGAHBDECREADSTRIDE[%s] + Decoder Read Stride + 0xC80 + 32 + read-write + 0 + 0xFFFFFFFF + + + STRIDE + Surface stride + 0 + 18 + read-write + + + + + 32 + 0x4 + GCREGAHBDECREADBUFFEREND[%s] + Decoder Read Buffer End + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + RD_BUFF_END + Address + 0 + 32 + read-write + + + + + + + DCSS__DTRC1 + DTRC + DTRC + DTRC + 0x32E16000 + + 0 + 0xFC + registers + + + + 2 + 0x60 + FRAME_REGISTERS[%s] + no description available + 0 + + FDYDSADDR + Luma video data start address + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + F0DYDSADDR + Luma video data start address + 0 + 32 + read-write + + + + + FDCDSADDR + Chroma video data start address + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + F0DCDSADDR + Chroma video data start address + 0 + 32 + read-write + + + + + FDYTSADDR + Luma table data start address + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + F0DYTSADDR + Luma table data start address + 0 + 32 + read-write + + + + + FDCTSADDR + Chroma table data start address + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + F0DCTSADDR + Chroma table data start address + 0 + 32 + read-write + + + + + FSIZE + Frame size + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + F0WIDTH + Frame width + 0 + 10 + read-write + + + F0HEIGHT + Frame height + 16 + 10 + read-write + + + + + FSYSSA + Luma data slave start address + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + F0YSTRBYPASS + Luma Start Tile to Raster scan Bypass + 0 + 1 + read-write + + + F0YSTRBYPASS_0 + All ARADDR does NOT bypass the tile-to-rasterscan logic. + 0 + + + F0YSTRBYPASS_1 + All ARADDR bypasses the tile-to-rasterscan logic. + 0x1 + + + + + F0SYSSA + Luma data slave start address + 4 + 28 + read-write + + + + + FSYSEA + Luma data slave end address + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + F0YETRBYPASS + End Tile to Raster scan Bypass + 0 + 1 + read-write + + + F0YETRBYPASS_0 + All ARADDR does NOT bypass the tile-to-rasterscan logic. + 0 + + + F0YETRBYPASS_1 + All ARADDR bypasses the tile-to-rasterscan logic. + 0x1 + + + + + F0SYSEA + Luma data slave end address + 4 + 28 + read-write + + + + + FSUVSSA + Chroma data slave start address + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + F0CSTRBYPASS + Chroma Start Tile to Raster scan Bypass + 0 + 1 + read-write + + + F0CSTRBYPASS_0 + All ARADDR does NOT bypass the tile-to-rasterscan logic. + 0 + + + F0CSTRBYPASS_1 + All ARADDR bypasses the tile-to-rasterscan logic. + 0x1 + + + + + F0SUVSSA + Chroma data slave start address + 4 + 28 + read-write + + + + + FSUVSEA + Chroma data slave end address + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + F0CETRBYPASS + End Tile to Raster scan Bypass + 0 + 1 + read-write + + + F0CETRBYPASS_0 + All ARADDR does NOT bypass the tile-to-rasterscan logic. + 0 + + + F0CETRBYPASS_1 + All ARADDR bypasses the tile-to-rasterscan logic. + 0x1 + + + + + F0SUVSEA + Chroma data slave end address + 4 + 28 + read-write + + + + + FCROPORIG + Cropped picture origin + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + F0CROPORIGX + Cropped picture x origin + 0 + 13 + read-write + + + F0CROPORIGY + Cropped picture y origin + 16 + 13 + read-write + + + + + FCROPSIZE + Cropped picture size + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + F0CROPWIDTH + Cropped picture width + 0 + 13 + read-write + + + F0CROPHEIGHT + Cropped picture height + 16 + 13 + read-write + + + + + FDCTL + Frame data control + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + F0FRAMECFG + Frame configuration ready + 0 + 1 + read-write + + + F0FRAMECFG_0 + Frame 0 configuration is not ready. + 0 + + + F0FRAMECFG_1 + Frame 0 configuration is ready and decompress can start for the frame. All other configuration, such as main8/main10 are updated before setting this bit to 1. If there is no G1/G2 video transaction, set this bit to 0. + 0x1 + + + + + F0PIXELBITDEPTH + Pixel bit depth + 1 + 1 + read-write + + + F0PIXELBITDEPTH_0 + 10-bit pixel depth + 0 + + + F0PIXELBITDEPTH_1 + 8-bit pixel depth + 0x1 + + + + + F0DECOMPRESS + Decompress bypass + 17 + 1 + read-write + + + F0DECOMPRESS_0 + G2 reference frame is compressed. + 0 + + + F0DECOMPRESS_1 + G2/G1 reference frame is not compressed. + 0x1 + + + + + F0CROPENABLE + Cropped enable + 18 + 1 + read-write + + + + + + DTRCINTEN + DTRC Interrupt enables + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAMEFETCHDONE_EN + Frame fetch done interrupt enable + 0 + 1 + read-write + + + FRAMEFETCHDONE_EN_0 + Frame fetch done interrupt disabled. + 0 + + + FRAMEFETCHDONE_EN_1 + Frame fetch done interrupt enabled. + 0x1 + + + + + BUSERROR_EN + Bus error interrupt enable + 1 + 1 + read-write + + + BUSERROR_EN_0 + Bus error interrupt disabled. + 0 + + + BUSERROR_EN_1 + Bus error interrupt enabled. + 0x1 + + + + + TIMEOUT_EN + Time out enable + 2 + 1 + read-write + + + TIMEOUT_EN_0 + Time out disabled. + 0 + + + TIMEOUT_EN_1 + Time out enabled. + 0x1 + + + + + SLFRAMEFETCHDONE_EN + Slave frame fetch done + 3 + 1 + read-write + + + SLFRAMEFETCHDONE_EN_0 + Slave frame fetch done disabled. + 0 + + + SLFRAMEFETCHDONE_EN_1 + Slave frame fetch done enabled. + 0x1 + + + + + HOTRESETFINISH_EN + Hot reset finish + 4 + 1 + read-write + + + HOTRESETFINISH_EN_0 + Hot reset finish disabled. + 0 + + + HOTRESETFINISH_EN_1 + Hot reset finish enabled. + 0x1 + + + + + + + FDINTR + DTRC Interrupt Requests + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAMEFETCHDONE + Frame fetch done interrupt + 0 + 1 + read-only + + + BUSERROR + Bus error interrupt + 1 + 1 + read-only + + + TIMEOUT + Time out interrupt + 2 + 1 + read-write + + + SLFRAMEFETCHDONE + Slave frame fetch done interrupt + 3 + 1 + read-write + + + HOTRESETFINISH + Hot reset finish interrupt + 4 + 1 + read-write + + + + + DTCTRL + DTRC Control + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARIDRCFG + ARIDR configuration + 0 + 2 + read-write + + + ARIDRCFG_0 + All ARID is de-tiled. + 0 + + + ARIDRCFG_1 + ARID in ARIDR is de-tiled, and others are bypass. NOTE: ARID[0] specify decode luma or chroma, so 4 ARIDs in ARIDR should include both of ARID[0] ==1 and ARID[0] ==0. + 0x1 + + + ARIDRCFG_2 + ARID in ARIDR is bypass_de-tile, and others are de-tiled. + 0x2 + + + ARIDRCFG_3 + Same as 2'b01. + 0x3 + + + + + HOTRESETTRIG + Hot reset trigger + 2 + 1 + read-write + + + G1G2DATA + G2 or G1 source data + 3 + 1 + read-write + + + G1G2DATA_0 + The source data is G2 data. + 0 + + + G1G2DATA_1 + The source data is G1 tile data + 0x1 + + + + + AXIMAXBURSTL + Maximum burst length of AXI master port + 4 + 8 + read-write + + + BYTESWAP_SLRAST + Byte swap mode for slave interface raster scan data + 12 + 4 + read-write + + + BYTESWAP_MCOMPTILE + Byte swap mode for master interface compressed data and tiled data + 16 + 4 + read-write + + + BYTESWAP_MTABLE + Byte swap mode for master interface table data + 20 + 4 + read-write + + + BYTESWAP_M_NONG1G2 + Byte swap mode for master interface non-G1/G2 data + 24 + 4 + read-write + + + MERGEG1G2_ARIDEN + Merge G2/G1 ARID enable + 28 + 1 + read-write + + + MERGEG1G2_ARIDEN_0 + G2/G1 transactions at AXI master interface use different id for table/chroma and data/luma according to DTID2DDR definition. + 0 + + + MERGEG1G2_ARIDEN_1 + All G2/G1 transactions at AXI master interface use the same id configured in DTID2DDR[15:8] Please note that DTID2DDR[15:8] and DTID2DDR[7:0] still need to be set the same way as when DTCTRL[28] is 0. + 0x1 + + + + + RAST_ENDIAN + Raster endian mode + 29 + 1 + read-write + + + RAST_ENDIAN_0 + 10-bit output format is little-endian. Byte swap setting of DTCTRL[15:12] is used. + 0 + + + RAST_ENDIAN_1 + 10-bit output format is big-endian. Byte swap setting of DTCTRL[15:12] is ignored. + 0x1 + + + + + ADDR_ARID + ADDR_ARID + 30 + 1 + read-write + + + ADDR_ARID_0 + By ARID (See bit[1:0] of this register). + 0 + + + ADDR_ARID_1 + By ARADDR + 0x1 + + + + + FRBUFF_PTR + FRBUFF_PTR + 31 + 1 + read-only + + + FRBUFF_PTR_0 + Configure frame 0 registers. + 0 + + + FRBUFF_PTR_1 + Configure frame 1 registers. + 0x1 + + + + + + + ARIDR + ARIDR + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + ARIDR + ARIDR + 0 + 32 + read-write + + + + + DTID2DDR + DTID2DDR + 0xD0 + 32 + read-write + 0xF0E + 0xFFFFFFFF + + + ARID_COMPR + ARID_COMPR + 0 + 8 + read-write + + + ARID_TABLE + ARID_TABLE + 8 + 8 + read-write + + + + + DTRCCONFIG + DTRCCONFIG + 0xD4 + 32 + read-only + 0 + 0 + + + G1G2_KEEPORDER + G1G2_KEEPORDER + 1 + 1 + read-only + + + G1G2_KEEPORDER_0 + Not supported. DTRC sends out data transactions as soon as they are ready regardless of the address transactions order, The master connected to AXI slave interface must recognize the data transactions by the RID. + 0 + + + G1G2_KEEPORDER_1 + Supported, DTRC ensure return read data from a sequence of read transactions in the same order in which it received the address. + 0x1 + + + + + AXI_MAXBURSTL + AXI_MAXBURSTL + 2 + 1 + read-only + + + AXI_MAXBURSTL_0 + Not supported. + 0 + + + AXI_MAXBURSTL_1 + Supported. DTRC sends the G1/G2 relating requests with ARLEN <= (the maximum burst length - 1). The maximum burst length is set by DTCTRL[16:8]. + 0x1 + + + + + G1TILE_INPUT + G1TILE_INPUT + 3 + 1 + read-only + + + G1TILE_INPUT_0 + Not supported. + 0 + + + G1TILE_INPUT_1 + Supported. + 0x1 + + + + + MAX_PIC_WIDTH + MAX_PIC_WIDTH + 4 + 2 + read-only + + + MAX_PIC_WIDTH_0 + 4096 + 0 + + + MAX_PIC_WIDTH_1 + 1920 + 0x1 + + + + + + + DTRCVERSION + DTRC Version + 0xD8 + 32 + read-only + 0 + 0 + + + CUST_VERSION + CUST_VERSION + 0 + 4 + read-only + + + MINOR + MINOR + 4 + 6 + read-only + + + MAJOR + MAJOR + 10 + 6 + read-only + + + + + PFCTRL + Performance counter control + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PFC_EN + PFC_EN + 0 + 1 + read-write + + + PFC_EN_0 + Performance Counter disabled. + 0 + + + PFC_EN_1 + Performance Counter enabled. + 0x1 + + + + + + + PFCR + Performance counter + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PFCR + Performance Counter + 0 + 32 + read-write + + + + + TOCR + Time Out Cycles + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TOCR + Time Out Cycles + 0 + 32 + read-write + + + + + + + DCSS__DTRC2 + DTRC + DTRC + 0x32E17000 + + 0 + 0xFC + registers + + + + DCSS__DPR1 + no description available + DPR + DPR + 0x32E18000 + + 0 + 0x210 + registers + + + + SYSTEM_CTRL0 + System Control 0 + 0 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + RUN_EN + Run Enable + 0 + 1 + read-write + + + SOFT_RESET + Soft Reset + 1 + 1 + read-write + + + REPEAT_EN + Repeat Enable + 2 + 1 + read-write + + + SHADOW_LOAD_EN + Shadow Load Enable + 3 + 1 + read-write + + + SW_SHADOW_LOAD_SEL + Software Shadow Load Select + 4 + 1 + read-write + + + BCMD2AXI_MSTR_ID_CTRL + Buscmd To AXI Master ID Control + 16 + 1 + read-write + + + + + SYSTEM_CTRL0_SET + System Control 0 + 0x4 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + RUN_EN + Run Enable + 0 + 1 + read-write + oneToSet + + + SOFT_RESET + Soft Reset + 1 + 1 + read-write + oneToSet + + + REPEAT_EN + Repeat Enable + 2 + 1 + read-write + oneToSet + + + SHADOW_LOAD_EN + Shadow Load Enable + 3 + 1 + read-write + oneToSet + + + SW_SHADOW_LOAD_SEL + Software Shadow Load Select + 4 + 1 + read-write + oneToSet + + + BCMD2AXI_MSTR_ID_CTRL + Buscmd To AXI Master ID Control + 16 + 1 + read-write + oneToSet + + + + + SYSTEM_CTRL0_CLR + System Control 0 + 0x8 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + RUN_EN + Run Enable + 0 + 1 + read-write + oneToClear + + + SOFT_RESET + Soft Reset + 1 + 1 + read-write + oneToClear + + + REPEAT_EN + Repeat Enable + 2 + 1 + read-write + oneToClear + + + SHADOW_LOAD_EN + Shadow Load Enable + 3 + 1 + read-write + oneToClear + + + SW_SHADOW_LOAD_SEL + Software Shadow Load Select + 4 + 1 + read-write + oneToClear + + + BCMD2AXI_MSTR_ID_CTRL + Buscmd To AXI Master ID Control + 16 + 1 + read-write + oneToClear + + + + + SYSTEM_CTRL0_TOG + System Control 0 + 0xC + 32 + read-write + 0x10 + 0xFFFFFFFF + + + RUN_EN + Run Enable + 0 + 1 + read-write + oneToToggle + + + SOFT_RESET + Soft Reset + 1 + 1 + read-write + oneToToggle + + + REPEAT_EN + Repeat Enable + 2 + 1 + read-write + oneToToggle + + + SHADOW_LOAD_EN + Shadow Load Enable + 3 + 1 + read-write + oneToToggle + + + SW_SHADOW_LOAD_SEL + Software Shadow Load Select + 4 + 1 + read-write + oneToToggle + + + BCMD2AXI_MSTR_ID_CTRL + Buscmd To AXI Master ID Control + 16 + 1 + read-write + oneToToggle + + + + + IRQ_MASK + Interrupt Mask + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ_DPR_CTRL_DONE + DPR Control Done IRQ Mask + 0 + 1 + read-write + + + IRQ_DPR_RUN + DPR Run IRQ Mask + 1 + 1 + read-write + + + IRQ_DPR_SHADOW_LOADED_MASK + DPR Shadow Loaded IRQ Mask + 2 + 1 + read-write + + + IRQ_AXI_READ_ERROR + AXI Read Error IRQ Mask + 3 + 1 + read-write + + + DPR2RTR_YRGB_FIFO_OVFL + DPR to RTRAM YRGB Fifo Overflow IRQ Mask + 4 + 1 + read-write + + + DPR2RTR_UV_FIFO_OVFL + DPR to RTRAM UV Fifo Overflow IRQ Mask + 5 + 1 + read-write + + + DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR + DPR to RTRAM Fifo load YRGB buffer ready IRQ error Mask + 6 + 1 + read-write + + + DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR + DPR to RTRAM Fifo load UV buffer ready IRQ error Mask + 7 + 1 + read-write + + + + + IRQ_MASK_SET + Interrupt Mask + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ_DPR_CTRL_DONE + DPR Control Done IRQ Mask + 0 + 1 + read-write + oneToSet + + + IRQ_DPR_RUN + DPR Run IRQ Mask + 1 + 1 + read-write + oneToSet + + + IRQ_DPR_SHADOW_LOADED_MASK + DPR Shadow Loaded IRQ Mask + 2 + 1 + read-write + oneToSet + + + IRQ_AXI_READ_ERROR + AXI Read Error IRQ Mask + 3 + 1 + read-write + oneToSet + + + DPR2RTR_YRGB_FIFO_OVFL + DPR to RTRAM YRGB Fifo Overflow IRQ Mask + 4 + 1 + read-write + oneToSet + + + DPR2RTR_UV_FIFO_OVFL + DPR to RTRAM UV Fifo Overflow IRQ Mask + 5 + 1 + read-write + oneToSet + + + DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR + DPR to RTRAM Fifo load YRGB buffer ready IRQ error Mask + 6 + 1 + read-write + oneToSet + + + DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR + DPR to RTRAM Fifo load UV buffer ready IRQ error Mask + 7 + 1 + read-write + oneToSet + + + + + IRQ_MASK_CLR + Interrupt Mask + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ_DPR_CTRL_DONE + DPR Control Done IRQ Mask + 0 + 1 + read-write + oneToClear + + + IRQ_DPR_RUN + DPR Run IRQ Mask + 1 + 1 + read-write + oneToClear + + + IRQ_DPR_SHADOW_LOADED_MASK + DPR Shadow Loaded IRQ Mask + 2 + 1 + read-write + oneToClear + + + IRQ_AXI_READ_ERROR + AXI Read Error IRQ Mask + 3 + 1 + read-write + oneToClear + + + DPR2RTR_YRGB_FIFO_OVFL + DPR to RTRAM YRGB Fifo Overflow IRQ Mask + 4 + 1 + read-write + oneToClear + + + DPR2RTR_UV_FIFO_OVFL + DPR to RTRAM UV Fifo Overflow IRQ Mask + 5 + 1 + read-write + oneToClear + + + DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR + DPR to RTRAM Fifo load YRGB buffer ready IRQ error Mask + 6 + 1 + read-write + oneToClear + + + DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR + DPR to RTRAM Fifo load UV buffer ready IRQ error Mask + 7 + 1 + read-write + oneToClear + + + + + IRQ_MASK_TOG + Interrupt Mask + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ_DPR_CTRL_DONE + DPR Control Done IRQ Mask + 0 + 1 + read-write + oneToToggle + + + IRQ_DPR_RUN + DPR Run IRQ Mask + 1 + 1 + read-write + oneToToggle + + + IRQ_DPR_SHADOW_LOADED_MASK + DPR Shadow Loaded IRQ Mask + 2 + 1 + read-write + oneToToggle + + + IRQ_AXI_READ_ERROR + AXI Read Error IRQ Mask + 3 + 1 + read-write + oneToToggle + + + DPR2RTR_YRGB_FIFO_OVFL + DPR to RTRAM YRGB Fifo Overflow IRQ Mask + 4 + 1 + read-write + oneToToggle + + + DPR2RTR_UV_FIFO_OVFL + DPR to RTRAM UV Fifo Overflow IRQ Mask + 5 + 1 + read-write + oneToToggle + + + DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR + DPR to RTRAM Fifo load YRGB buffer ready IRQ error Mask + 6 + 1 + read-write + oneToToggle + + + DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR + DPR to RTRAM Fifo load UV buffer ready IRQ error Mask + 7 + 1 + read-write + oneToToggle + + + + + IRQ_MASK_STATUS + Status Register of Masked IRQ + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + IRQ_DPR_CTRL_DONE + DPR Control Done Masked IRQ + 0 + 1 + read-only + + + IRQ_DPR_RUN + DPR Run Masked IRQ + 1 + 1 + read-only + + + IRQ_DPR_SHADOW_LOADED + DPR Shadow Loaded Masked IRQ + 2 + 1 + read-only + + + IRQ_AXI_READ_ERROR + AXI Read Error Masked IRQ + 3 + 1 + read-only + + + DPR2RTR_YRGB_FIFO_OVFL + DPR to RTRAM YRGB Fifo Overflow Masked IRQ + 4 + 1 + read-only + + + DPR2RTR_UV_FIFO_OVFL + DPR to RTRAM UV Fifo Overflow Masked IRQ + 5 + 1 + read-only + + + DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR + DPR to RTRAM Fifo load YRGB buffer error Masked IRQ + 6 + 1 + read-only + + + DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR + DPR to RTRAM Fifo load UV buffer error Masked IRQ + 7 + 1 + read-only + + + + + IRQ_MASK_STATUS_SET + Status Register of Masked IRQ + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + IRQ_DPR_CTRL_DONE + DPR Control Done Masked IRQ + 0 + 1 + read-only + oneToSet + + + IRQ_DPR_RUN + DPR Run Masked IRQ + 1 + 1 + read-only + oneToSet + + + IRQ_DPR_SHADOW_LOADED + DPR Shadow Loaded Masked IRQ + 2 + 1 + read-only + oneToSet + + + IRQ_AXI_READ_ERROR + AXI Read Error Masked IRQ + 3 + 1 + read-only + oneToSet + + + DPR2RTR_YRGB_FIFO_OVFL + DPR to RTRAM YRGB Fifo Overflow Masked IRQ + 4 + 1 + read-only + oneToSet + + + DPR2RTR_UV_FIFO_OVFL + DPR to RTRAM UV Fifo Overflow Masked IRQ + 5 + 1 + read-only + oneToSet + + + DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR + DPR to RTRAM Fifo load YRGB buffer error Masked IRQ + 6 + 1 + read-only + oneToSet + + + DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR + DPR to RTRAM Fifo load UV buffer error Masked IRQ + 7 + 1 + read-only + oneToSet + + + + + IRQ_MASK_STATUS_CLR + Status Register of Masked IRQ + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + IRQ_DPR_CTRL_DONE + DPR Control Done Masked IRQ + 0 + 1 + read-only + oneToClear + + + IRQ_DPR_RUN + DPR Run Masked IRQ + 1 + 1 + read-only + oneToClear + + + IRQ_DPR_SHADOW_LOADED + DPR Shadow Loaded Masked IRQ + 2 + 1 + read-only + oneToClear + + + IRQ_AXI_READ_ERROR + AXI Read Error Masked IRQ + 3 + 1 + read-only + oneToClear + + + DPR2RTR_YRGB_FIFO_OVFL + DPR to RTRAM YRGB Fifo Overflow Masked IRQ + 4 + 1 + read-only + oneToClear + + + DPR2RTR_UV_FIFO_OVFL + DPR to RTRAM UV Fifo Overflow Masked IRQ + 5 + 1 + read-only + oneToClear + + + DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR + DPR to RTRAM Fifo load YRGB buffer error Masked IRQ + 6 + 1 + read-only + oneToClear + + + DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR + DPR to RTRAM Fifo load UV buffer error Masked IRQ + 7 + 1 + read-only + oneToClear + + + + + IRQ_MASK_STATUS_TOG + Status Register of Masked IRQ + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + IRQ_DPR_CTRL_DONE + DPR Control Done Masked IRQ + 0 + 1 + read-only + oneToToggle + + + IRQ_DPR_RUN + DPR Run Masked IRQ + 1 + 1 + read-only + oneToToggle + + + IRQ_DPR_SHADOW_LOADED + DPR Shadow Loaded Masked IRQ + 2 + 1 + read-only + oneToToggle + + + IRQ_AXI_READ_ERROR + AXI Read Error Masked IRQ + 3 + 1 + read-only + oneToToggle + + + DPR2RTR_YRGB_FIFO_OVFL + DPR to RTRAM YRGB Fifo Overflow Masked IRQ + 4 + 1 + read-only + oneToToggle + + + DPR2RTR_UV_FIFO_OVFL + DPR to RTRAM UV Fifo Overflow Masked IRQ + 5 + 1 + read-only + oneToToggle + + + DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR + DPR to RTRAM Fifo load YRGB buffer error Masked IRQ + 6 + 1 + read-only + oneToToggle + + + DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR + DPR to RTRAM Fifo load UV buffer error Masked IRQ + 7 + 1 + read-only + oneToToggle + + + + + IRQ_NONMASK_STATUS + Status of Non-Masked IRQ + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ_DPR_CTRL_DONE + DPR Control Done Non-Masked IRQ + 0 + 1 + read-write + oneToClear + + + IRQ_DPR_RUN + DPR Run Non-Masked IRQ + 1 + 1 + read-write + oneToClear + + + IRQ_DPR_SHADOW_LOADED_NMSTAT + DPR Shadow Loaded Non-Masked IRQ + 2 + 1 + read-write + oneToClear + + + IRQ_AXI_READ_ERROR + AXI Read Error Non-Masked IRQ + 3 + 1 + read-write + oneToClear + + + DPR2RTR_YRGB_FIFO_OVFL + DPR to RTRAM YRGB Fifo Overflow Non-Masked IRQ + 4 + 1 + read-write + oneToClear + + + DPR2RTR_UV_FIFO_OVFL + DPR to RTRAM UV Fifo Overflow Non-Masked IRQ + 5 + 1 + read-write + oneToClear + + + DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR + DPR to RTRAM Fifo load YRGB buffer ready error Non-Masked IRQ + 6 + 1 + read-write + oneToClear + + + DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR + DPR to RTRAM Fifo load UV buffer ready error Non-Masked IRQ + 7 + 1 + read-write + oneToClear + + + + + IRQ_NONMASK_STATUS_SET + Status of Non-Masked IRQ + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ_DPR_CTRL_DONE + DPR Control Done Non-Masked IRQ + 0 + 1 + read-write + oneToSet + + + IRQ_DPR_RUN + DPR Run Non-Masked IRQ + 1 + 1 + read-write + oneToSet + + + IRQ_DPR_SHADOW_LOADED_NMSTAT + DPR Shadow Loaded Non-Masked IRQ + 2 + 1 + read-write + oneToSet + + + IRQ_AXI_READ_ERROR + AXI Read Error Non-Masked IRQ + 3 + 1 + read-write + oneToSet + + + DPR2RTR_YRGB_FIFO_OVFL + DPR to RTRAM YRGB Fifo Overflow Non-Masked IRQ + 4 + 1 + read-write + oneToSet + + + DPR2RTR_UV_FIFO_OVFL + DPR to RTRAM UV Fifo Overflow Non-Masked IRQ + 5 + 1 + read-write + oneToSet + + + DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR + DPR to RTRAM Fifo load YRGB buffer ready error Non-Masked IRQ + 6 + 1 + read-write + oneToSet + + + DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR + DPR to RTRAM Fifo load UV buffer ready error Non-Masked IRQ + 7 + 1 + read-write + oneToSet + + + + + IRQ_NONMASK_STATUS_CLR + Status of Non-Masked IRQ + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ_DPR_CTRL_DONE + DPR Control Done Non-Masked IRQ + 0 + 1 + read-write + oneToClear + + + IRQ_DPR_RUN + DPR Run Non-Masked IRQ + 1 + 1 + read-write + oneToClear + + + IRQ_DPR_SHADOW_LOADED_NMSTAT + DPR Shadow Loaded Non-Masked IRQ + 2 + 1 + read-write + oneToClear + + + IRQ_AXI_READ_ERROR + AXI Read Error Non-Masked IRQ + 3 + 1 + read-write + oneToClear + + + DPR2RTR_YRGB_FIFO_OVFL + DPR to RTRAM YRGB Fifo Overflow Non-Masked IRQ + 4 + 1 + read-write + oneToClear + + + DPR2RTR_UV_FIFO_OVFL + DPR to RTRAM UV Fifo Overflow Non-Masked IRQ + 5 + 1 + read-write + oneToClear + + + DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR + DPR to RTRAM Fifo load YRGB buffer ready error Non-Masked IRQ + 6 + 1 + read-write + oneToClear + + + DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR + DPR to RTRAM Fifo load UV buffer ready error Non-Masked IRQ + 7 + 1 + read-write + oneToClear + + + + + IRQ_NONMASK_STATUS_TOG + Status of Non-Masked IRQ + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ_DPR_CTRL_DONE + DPR Control Done Non-Masked IRQ + 0 + 1 + read-write + oneToToggle + + + IRQ_DPR_RUN + DPR Run Non-Masked IRQ + 1 + 1 + read-write + oneToToggle + + + IRQ_DPR_SHADOW_LOADED_NMSTAT + DPR Shadow Loaded Non-Masked IRQ + 2 + 1 + read-write + oneToToggle + + + IRQ_AXI_READ_ERROR + AXI Read Error Non-Masked IRQ + 3 + 1 + read-write + oneToToggle + + + DPR2RTR_YRGB_FIFO_OVFL + DPR to RTRAM YRGB Fifo Overflow Non-Masked IRQ + 4 + 1 + read-write + oneToToggle + + + DPR2RTR_UV_FIFO_OVFL + DPR to RTRAM UV Fifo Overflow Non-Masked IRQ + 5 + 1 + read-write + oneToToggle + + + DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR + DPR to RTRAM Fifo load YRGB buffer ready error Non-Masked IRQ + 6 + 1 + read-write + oneToToggle + + + DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR + DPR to RTRAM Fifo load UV buffer ready error Non-Masked IRQ + 7 + 1 + read-write + oneToToggle + + + + + MODE_CTRL0 + Mode Control 0 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTR_3BUF_EN + RTRAM Buffer Implementation + 0 + 1 + read-write + + + RTR_4LINE_BUF_EN + RTRAM Lines Per Buffer + 1 + 1 + read-write + + + TILE_TYPE + Tile Type + 2 + 3 + read-write + + + YUV_EN + YUV Enable + 6 + 1 + read-write + + + COMP_2PLANE_EN + Component 2-Plane Enable + 7 + 1 + read-write + + + PIX_SIZE + Pixel Size + 8 + 2 + read-write + + + PIX_LUMA_UV_SWAP + Pixel luma/UV position Swap + 10 + 1 + read-write + + + PIX_UV_SWAP + Pixel UV Swap + 11 + 1 + read-write + + + B_COMP_SEL + B Component Select + 12 + 2 + read-write + + + G_COMP_SEL + G Component Select + 14 + 2 + read-write + + + R_COMP_SEL + R Component Select + 16 + 2 + read-write + + + A_COMP_SEL + A Component Select + 18 + 2 + read-write + + + + + MODE_CTRL0_SET + Mode Control 0 + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTR_3BUF_EN + RTRAM Buffer Implementation + 0 + 1 + read-write + oneToSet + + + RTR_4LINE_BUF_EN + RTRAM Lines Per Buffer + 1 + 1 + read-write + oneToSet + + + TILE_TYPE + Tile Type + 2 + 3 + read-write + oneToSet + + + YUV_EN + YUV Enable + 6 + 1 + read-write + oneToSet + + + COMP_2PLANE_EN + Component 2-Plane Enable + 7 + 1 + read-write + oneToSet + + + PIX_SIZE + Pixel Size + 8 + 2 + read-write + oneToSet + + + PIX_LUMA_UV_SWAP + Pixel luma/UV position Swap + 10 + 1 + read-write + oneToSet + + + PIX_UV_SWAP + Pixel UV Swap + 11 + 1 + read-write + oneToSet + + + B_COMP_SEL + B Component Select + 12 + 2 + read-write + oneToSet + + + G_COMP_SEL + G Component Select + 14 + 2 + read-write + oneToSet + + + R_COMP_SEL + R Component Select + 16 + 2 + read-write + oneToSet + + + A_COMP_SEL + A Component Select + 18 + 2 + read-write + oneToSet + + + + + MODE_CTRL0_CLR + Mode Control 0 + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTR_3BUF_EN + RTRAM Buffer Implementation + 0 + 1 + read-write + oneToClear + + + RTR_4LINE_BUF_EN + RTRAM Lines Per Buffer + 1 + 1 + read-write + oneToClear + + + TILE_TYPE + Tile Type + 2 + 3 + read-write + oneToClear + + + YUV_EN + YUV Enable + 6 + 1 + read-write + oneToClear + + + COMP_2PLANE_EN + Component 2-Plane Enable + 7 + 1 + read-write + oneToClear + + + PIX_SIZE + Pixel Size + 8 + 2 + read-write + oneToClear + + + PIX_LUMA_UV_SWAP + Pixel luma/UV position Swap + 10 + 1 + read-write + oneToClear + + + PIX_UV_SWAP + Pixel UV Swap + 11 + 1 + read-write + oneToClear + + + B_COMP_SEL + B Component Select + 12 + 2 + read-write + oneToClear + + + G_COMP_SEL + G Component Select + 14 + 2 + read-write + oneToClear + + + R_COMP_SEL + R Component Select + 16 + 2 + read-write + oneToClear + + + A_COMP_SEL + A Component Select + 18 + 2 + read-write + oneToClear + + + + + MODE_CTRL0_TOG + Mode Control 0 + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + RTR_3BUF_EN + RTRAM Buffer Implementation + 0 + 1 + read-write + oneToToggle + + + RTR_4LINE_BUF_EN + RTRAM Lines Per Buffer + 1 + 1 + read-write + oneToToggle + + + TILE_TYPE + Tile Type + 2 + 3 + read-write + oneToToggle + + + YUV_EN + YUV Enable + 6 + 1 + read-write + oneToToggle + + + COMP_2PLANE_EN + Component 2-Plane Enable + 7 + 1 + read-write + oneToToggle + + + PIX_SIZE + Pixel Size + 8 + 2 + read-write + oneToToggle + + + PIX_LUMA_UV_SWAP + Pixel luma/UV position Swap + 10 + 1 + read-write + oneToToggle + + + PIX_UV_SWAP + Pixel UV Swap + 11 + 1 + read-write + oneToToggle + + + B_COMP_SEL + B Component Select + 12 + 2 + read-write + oneToToggle + + + G_COMP_SEL + G Component Select + 14 + 2 + read-write + oneToToggle + + + R_COMP_SEL + R Component Select + 16 + 2 + read-write + oneToToggle + + + A_COMP_SEL + A Component Select + 18 + 2 + read-write + oneToToggle + + + + + FRAME_CTRL0 + Frame Control 0 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + HFLIP_EN + Horizontal Flip Enable + 0 + 1 + read-write + + + VFLIP_EN + Vertical Flip Enable + 1 + 1 + read-write + + + ROT_ENC + Encoded Rotation + 2 + 2 + read-write + + + ROT_FLIP_ORDER_EN + Rotation Flip Order + 4 + 1 + read-write + + + PITCH + Image Pitch + 16 + 16 + read-write + + + + + FRAME_CTRL0_SET + Frame Control 0 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + HFLIP_EN + Horizontal Flip Enable + 0 + 1 + read-write + oneToSet + + + VFLIP_EN + Vertical Flip Enable + 1 + 1 + read-write + oneToSet + + + ROT_ENC + Encoded Rotation + 2 + 2 + read-write + oneToSet + + + ROT_FLIP_ORDER_EN + Rotation Flip Order + 4 + 1 + read-write + oneToSet + + + PITCH + Image Pitch + 16 + 16 + read-write + oneToSet + + + + + FRAME_CTRL0_CLR + Frame Control 0 + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + HFLIP_EN + Horizontal Flip Enable + 0 + 1 + read-write + oneToClear + + + VFLIP_EN + Vertical Flip Enable + 1 + 1 + read-write + oneToClear + + + ROT_ENC + Encoded Rotation + 2 + 2 + read-write + oneToClear + + + ROT_FLIP_ORDER_EN + Rotation Flip Order + 4 + 1 + read-write + oneToClear + + + PITCH + Image Pitch + 16 + 16 + read-write + oneToClear + + + + + FRAME_CTRL0_TOG + Frame Control 0 + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + HFLIP_EN + Horizontal Flip Enable + 0 + 1 + read-write + oneToToggle + + + VFLIP_EN + Vertical Flip Enable + 1 + 1 + read-write + oneToToggle + + + ROT_ENC + Encoded Rotation + 2 + 2 + read-write + oneToToggle + + + ROT_FLIP_ORDER_EN + Rotation Flip Order + 4 + 1 + read-write + oneToToggle + + + PITCH + Image Pitch + 16 + 16 + read-write + oneToToggle + + + + + FRAME_1P_CTRL0 + Frame 1-Plane Control 0 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAX_BYTES_PREQ + Max Bytes Per Request + 0 + 3 + read-write + + + + + FRAME_1P_CTRL0_SET + Frame 1-Plane Control 0 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAX_BYTES_PREQ + Max Bytes Per Request + 0 + 3 + read-write + oneToSet + + + + + FRAME_1P_CTRL0_CLR + Frame 1-Plane Control 0 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAX_BYTES_PREQ + Max Bytes Per Request + 0 + 3 + read-write + oneToClear + + + + + FRAME_1P_CTRL0_TOG + Frame 1-Plane Control 0 + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + MAX_BYTES_PREQ + Max Bytes Per Request + 0 + 3 + read-write + oneToToggle + + + + + FRAME_1P_PIX_X_CTRL + Frame 1-Plane Pix X Control + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_X_PIX_WIDE + Number of Pixels Wide in X-direction + 0 + 16 + read-write + + + CROP_ULC_X + Starting Coordinate of Cropped Image X (1-Plane or 2-Plane Luma) + 16 + 16 + read-write + + + + + FRAME_1P_PIX_X_CTRL_SET + Frame 1-Plane Pix X Control + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_X_PIX_WIDE + Number of Pixels Wide in X-direction + 0 + 16 + read-write + oneToSet + + + CROP_ULC_X + Starting Coordinate of Cropped Image X (1-Plane or 2-Plane Luma) + 16 + 16 + read-write + oneToSet + + + + + FRAME_1P_PIX_X_CTRL_CLR + Frame 1-Plane Pix X Control + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_X_PIX_WIDE + Number of Pixels Wide in X-direction + 0 + 16 + read-write + oneToClear + + + CROP_ULC_X + Starting Coordinate of Cropped Image X (1-Plane or 2-Plane Luma) + 16 + 16 + read-write + oneToClear + + + + + FRAME_1P_PIX_X_CTRL_TOG + Frame 1-Plane Pix X Control + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_X_PIX_WIDE + Number of Pixels Wide in X-direction + 0 + 16 + read-write + oneToToggle + + + CROP_ULC_X + Starting Coordinate of Cropped Image X (1-Plane or 2-Plane Luma) + 16 + 16 + read-write + oneToToggle + + + + + FRAME_1P_PIX_Y_CTRL + Frame 1-Plane Pix Y Control + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_Y_PIX_HIGH + Number of Pixels High in Y-direction + 0 + 16 + read-write + + + CROP_ULC_Y + Starting Coordinate of Cropped Image Y (1-Plane or 2-Plane Luma) + 16 + 16 + read-write + + + + + FRAME_1P_PIX_Y_CTRL_SET + Frame 1-Plane Pix Y Control + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_Y_PIX_HIGH + Number of Pixels High in Y-direction + 0 + 16 + read-write + oneToSet + + + CROP_ULC_Y + Starting Coordinate of Cropped Image Y (1-Plane or 2-Plane Luma) + 16 + 16 + read-write + oneToSet + + + + + FRAME_1P_PIX_Y_CTRL_CLR + Frame 1-Plane Pix Y Control + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_Y_PIX_HIGH + Number of Pixels High in Y-direction + 0 + 16 + read-write + oneToClear + + + CROP_ULC_Y + Starting Coordinate of Cropped Image Y (1-Plane or 2-Plane Luma) + 16 + 16 + read-write + oneToClear + + + + + FRAME_1P_PIX_Y_CTRL_TOG + Frame 1-Plane Pix Y Control + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_Y_PIX_HIGH + Number of Pixels High in Y-direction + 0 + 16 + read-write + oneToToggle + + + CROP_ULC_Y + Starting Coordinate of Cropped Image Y (1-Plane or 2-Plane Luma) + 16 + 16 + read-write + oneToToggle + + + + + FRAME_1P_BASE_ADDR_CTRL0 + Frame 1-Plane Base Address Control 0 + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE_ADDR + Base Address + 0 + 32 + read-write + + + + + FRAME_1P_BASE_ADDR_CTRL0_SET + Frame 1-Plane Base Address Control 0 + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE_ADDR + Base Address + 0 + 32 + read-write + oneToSet + + + + + FRAME_1P_BASE_ADDR_CTRL0_CLR + Frame 1-Plane Base Address Control 0 + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE_ADDR + Base Address + 0 + 32 + read-write + oneToClear + + + + + FRAME_1P_BASE_ADDR_CTRL0_TOG + Frame 1-Plane Base Address Control 0 + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE_ADDR + Base Address + 0 + 32 + read-write + oneToToggle + + + + + FRAME_2P_CTRL0 + Frame 2-Plane Control 0 + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAX_BYTES_PREQ + Max Bytes Per Request + 0 + 3 + read-write + + + + + FRAME_2P_CTRL0_SET + Frame 2-Plane Control 0 + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAX_BYTES_PREQ + Max Bytes Per Request + 0 + 3 + read-write + oneToSet + + + + + FRAME_2P_CTRL0_CLR + Frame 2-Plane Control 0 + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAX_BYTES_PREQ + Max Bytes Per Request + 0 + 3 + read-write + oneToClear + + + + + FRAME_2P_CTRL0_TOG + Frame 2-Plane Control 0 + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + MAX_BYTES_PREQ + Max Bytes Per Request + 0 + 3 + read-write + oneToToggle + + + + + FRAME_2P_PIX_X_CTRL + Frame 2-Plane Pix X Control + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_X_PIX_WIDE + Number of Pixels Wide in X-direction + 0 + 16 + read-write + + + CROP_ULC_X + Starting Coordinate of Cropped Image X (2-Plane UV) + 16 + 16 + read-write + + + + + FRAME_2P_PIX_X_CTRL_SET + Frame 2-Plane Pix X Control + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_X_PIX_WIDE + Number of Pixels Wide in X-direction + 0 + 16 + read-write + oneToSet + + + CROP_ULC_X + Starting Coordinate of Cropped Image X (2-Plane UV) + 16 + 16 + read-write + oneToSet + + + + + FRAME_2P_PIX_X_CTRL_CLR + Frame 2-Plane Pix X Control + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_X_PIX_WIDE + Number of Pixels Wide in X-direction + 0 + 16 + read-write + oneToClear + + + CROP_ULC_X + Starting Coordinate of Cropped Image X (2-Plane UV) + 16 + 16 + read-write + oneToClear + + + + + FRAME_2P_PIX_X_CTRL_TOG + Frame 2-Plane Pix X Control + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_X_PIX_WIDE + Number of Pixels Wide in X-direction + 0 + 16 + read-write + oneToToggle + + + CROP_ULC_X + Starting Coordinate of Cropped Image X (2-Plane UV) + 16 + 16 + read-write + oneToToggle + + + + + FRAME_2P_PIX_Y_CTRL + Frame 2-Plane Pix Y Control + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_Y_PIX_HIGH + Number of Pixels High in Y-direction + 0 + 16 + read-write + + + CROP_ULC_Y + Starting Coordinate of Cropped Image Y (2-Plane UV) + 16 + 16 + read-write + + + + + FRAME_2P_PIX_Y_CTRL_SET + Frame 2-Plane Pix Y Control + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_Y_PIX_HIGH + Number of Pixels High in Y-direction + 0 + 16 + read-write + oneToSet + + + CROP_ULC_Y + Starting Coordinate of Cropped Image Y (2-Plane UV) + 16 + 16 + read-write + oneToSet + + + + + FRAME_2P_PIX_Y_CTRL_CLR + Frame 2-Plane Pix Y Control + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_Y_PIX_HIGH + Number of Pixels High in Y-direction + 0 + 16 + read-write + oneToClear + + + CROP_ULC_Y + Starting Coordinate of Cropped Image Y (2-Plane UV) + 16 + 16 + read-write + oneToClear + + + + + FRAME_2P_PIX_Y_CTRL_TOG + Frame 2-Plane Pix Y Control + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_Y_PIX_HIGH + Number of Pixels High in Y-direction + 0 + 16 + read-write + oneToToggle + + + CROP_ULC_Y + Starting Coordinate of Cropped Image Y (2-Plane UV) + 16 + 16 + read-write + oneToToggle + + + + + FRAME_2P_BASE_ADDR_CTRL0 + Frame 2-Plane Base Address Control 0 + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE_ADDR + Base Address + 0 + 32 + read-write + + + + + FRAME_2P_BASE_ADDR_CTRL0_SET + Frame 2-Plane Base Address Control 0 + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE_ADDR + Base Address + 0 + 32 + read-write + oneToSet + + + + + FRAME_2P_BASE_ADDR_CTRL0_CLR + Frame 2-Plane Base Address Control 0 + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE_ADDR + Base Address + 0 + 32 + read-write + oneToClear + + + + + FRAME_2P_BASE_ADDR_CTRL0_TOG + Frame 2-Plane Base Address Control 0 + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE_ADDR + Base Address + 0 + 32 + read-write + oneToToggle + + + + + RTRAM_CTRL0 + RTRAM Control 0 + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_ROWS_ACTIVE + Number of Rows Active + 0 + 1 + read-write + + + THRES_HIGH + Threshold High + 1 + 3 + read-write + + + THRES_LOW + Threshold Low + 4 + 3 + read-write + + + ABORT_SEL + Abort Select + 7 + 1 + read-write + + + + + RTRAM_CTRL0_SET + RTRAM Control 0 + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_ROWS_ACTIVE + Number of Rows Active + 0 + 1 + read-write + oneToSet + + + THRES_HIGH + Threshold High + 1 + 3 + read-write + oneToSet + + + THRES_LOW + Threshold Low + 4 + 3 + read-write + oneToSet + + + ABORT_SEL + Abort Select + 7 + 1 + read-write + oneToSet + + + + + RTRAM_CTRL0_CLR + RTRAM Control 0 + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_ROWS_ACTIVE + Number of Rows Active + 0 + 1 + read-write + oneToClear + + + THRES_HIGH + Threshold High + 1 + 3 + read-write + oneToClear + + + THRES_LOW + Threshold Low + 4 + 3 + read-write + oneToClear + + + ABORT_SEL + Abort Select + 7 + 1 + read-write + oneToClear + + + + + RTRAM_CTRL0_TOG + RTRAM Control 0 + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_ROWS_ACTIVE + Number of Rows Active + 0 + 1 + read-write + oneToToggle + + + THRES_HIGH + Threshold High + 1 + 3 + read-write + oneToToggle + + + THRES_LOW + Threshold Low + 4 + 3 + read-write + oneToToggle + + + ABORT_SEL + Abort Select + 7 + 1 + read-write + oneToToggle + + + + + + + DCSS__DPR2 + no description available + DPR + 0x32E19000 + + 0 + 0x210 + registers + + + + DCSS__DPR3 + no description available + DPR + 0x32E1A000 + + 0 + 0x210 + registers + + + + DCSS__SUBSAM + no description available + SUBSAM + 0x32E1B000 + + 0 + 0xC4 + registers + + + + SS_SYS_CTRL + no description available + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RUN_EN + Software sets this bit to indicate when the subsam module is ready to be enabled + 0 + 1 + read-write + + + + + SS_SYS_CTRL_SET + no description available + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RUN_EN + Software sets this bit to indicate when the subsam module is ready to be enabled + 0 + 1 + read-write + oneToSet + + + + + SS_SYS_CTRL_CLR + no description available + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RUN_EN + Software sets this bit to indicate when the subsam module is ready to be enabled + 0 + 1 + read-write + oneToClear + + + + + SS_SYS_CTRL_TOG + no description available + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RUN_EN + Software sets this bit to indicate when the subsam module is ready to be enabled + 0 + 1 + read-write + oneToToggle + + + + + SS_DISPLAY + no description available + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + LRC_X + Holds the lower right corner x coordinate + 0 + 13 + read-write + + + LRC_Y + Holds the lower right corner y coordinate + 16 + 13 + read-write + + + + + SS_DISPLAY_SET + no description available + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + LRC_X + Holds the lower right corner x coordinate + 0 + 13 + read-write + oneToSet + + + LRC_Y + Holds the lower right corner y coordinate + 16 + 13 + read-write + oneToSet + + + + + SS_DISPLAY_CLR + no description available + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + LRC_X + Holds the lower right corner x coordinate + 0 + 13 + read-write + oneToClear + + + LRC_Y + Holds the lower right corner y coordinate + 16 + 13 + read-write + oneToClear + + + + + SS_DISPLAY_TOG + no description available + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + LRC_X + Holds the lower right corner x coordinate + 0 + 13 + read-write + oneToToggle + + + LRC_Y + Holds the lower right corner y coordinate + 16 + 13 + read-write + oneToToggle + + + + + SS_HSYNC + no description available + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + START + horizontal sync is asserted when horizontal count == START + 0 + 13 + read-write + + + END + horizontal sync is de-asserted when horizontal count == END + 16 + 13 + read-write + + + POL + Polarity of sync signal. 0 == active low ; 1 == active_high + 31 + 1 + read-write + + + + + SS_HSYNC_SET + no description available + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + START + horizontal sync is asserted when horizontal count == START + 0 + 13 + read-write + oneToSet + + + END + horizontal sync is de-asserted when horizontal count == END + 16 + 13 + read-write + oneToSet + + + POL + Polarity of sync signal. 0 == active low ; 1 == active_high + 31 + 1 + read-write + oneToSet + + + + + SS_HSYNC_CLR + no description available + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + START + horizontal sync is asserted when horizontal count == START + 0 + 13 + read-write + oneToClear + + + END + horizontal sync is de-asserted when horizontal count == END + 16 + 13 + read-write + oneToClear + + + POL + Polarity of sync signal. 0 == active low ; 1 == active_high + 31 + 1 + read-write + oneToClear + + + + + SS_HSYNC_TOG + no description available + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + START + horizontal sync is asserted when horizontal count == START + 0 + 13 + read-write + oneToToggle + + + END + horizontal sync is de-asserted when horizontal count == END + 16 + 13 + read-write + oneToToggle + + + POL + Polarity of sync signal. 0 == active low ; 1 == active_high + 31 + 1 + read-write + oneToToggle + + + + + SS_VSYNC + no description available + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + START + When v_count = START and h_count = CSR_SS_LRC_X then vsync goes active + 0 + 13 + read-write + + + END + When v_count = END h_count = CSR_SS_LRC_X vsync goes inactive + 16 + 13 + read-write + + + POL + Polarity of sync signal. 0 == active low ; 1 == active_high + 31 + 1 + read-write + + + + + SS_VSYNC_SET + no description available + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + START + When v_count = START and h_count = CSR_SS_LRC_X then vsync goes active + 0 + 13 + read-write + oneToSet + + + END + When v_count = END h_count = CSR_SS_LRC_X vsync goes inactive + 16 + 13 + read-write + oneToSet + + + POL + Polarity of sync signal. 0 == active low ; 1 == active_high + 31 + 1 + read-write + oneToSet + + + + + SS_VSYNC_CLR + no description available + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + START + When v_count = START and h_count = CSR_SS_LRC_X then vsync goes active + 0 + 13 + read-write + oneToClear + + + END + When v_count = END h_count = CSR_SS_LRC_X vsync goes inactive + 16 + 13 + read-write + oneToClear + + + POL + Polarity of sync signal. 0 == active low ; 1 == active_high + 31 + 1 + read-write + oneToClear + + + + + SS_VSYNC_TOG + no description available + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + START + When v_count = START and h_count = CSR_SS_LRC_X then vsync goes active + 0 + 13 + read-write + oneToToggle + + + END + When v_count = END h_count = CSR_SS_LRC_X vsync goes inactive + 16 + 13 + read-write + oneToToggle + + + POL + Polarity of sync signal. 0 == active low ; 1 == active_high + 31 + 1 + read-write + oneToToggle + + + + + SS_DE_ULC + no description available + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ULC_X + Horizontal position in the scan line that determines when DE goes active. + 0 + 13 + read-write + + + ULC_Y + Vertical position in the display that determines when the DE goes active. + 16 + 13 + read-write + + + POL + Polarity of DE signal. 0 == active low ; 1 == active_high + 31 + 1 + read-write + + + + + SS_DE_ULC_SET + no description available + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + ULC_X + Horizontal position in the scan line that determines when DE goes active. + 0 + 13 + read-write + oneToSet + + + ULC_Y + Vertical position in the display that determines when the DE goes active. + 16 + 13 + read-write + oneToSet + + + POL + Polarity of DE signal. 0 == active low ; 1 == active_high + 31 + 1 + read-write + oneToSet + + + + + SS_DE_ULC_CLR + no description available + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + ULC_X + Horizontal position in the scan line that determines when DE goes active. + 0 + 13 + read-write + oneToClear + + + ULC_Y + Vertical position in the display that determines when the DE goes active. + 16 + 13 + read-write + oneToClear + + + POL + Polarity of DE signal. 0 == active low ; 1 == active_high + 31 + 1 + read-write + oneToClear + + + + + SS_DE_ULC_TOG + no description available + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + ULC_X + Horizontal position in the scan line that determines when DE goes active. + 0 + 13 + read-write + oneToToggle + + + ULC_Y + Vertical position in the display that determines when the DE goes active. + 16 + 13 + read-write + oneToToggle + + + POL + Polarity of DE signal. 0 == active low ; 1 == active_high + 31 + 1 + read-write + oneToToggle + + + + + SS_DE_LRC + no description available + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + LRC_X + Horizontal position in the scan line that determines when DE goes inactive. + 0 + 13 + read-write + + + LRC_Y + Vertical position in the display that determines when the DE goes inactive. + 16 + 13 + read-write + + + + + SS_DE_LRC_SET + no description available + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + LRC_X + Horizontal position in the scan line that determines when DE goes inactive. + 0 + 13 + read-write + oneToSet + + + LRC_Y + Vertical position in the display that determines when the DE goes inactive. + 16 + 13 + read-write + oneToSet + + + + + SS_DE_LRC_CLR + no description available + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LRC_X + Horizontal position in the scan line that determines when DE goes inactive. + 0 + 13 + read-write + oneToClear + + + LRC_Y + Vertical position in the display that determines when the DE goes inactive. + 16 + 13 + read-write + oneToClear + + + + + SS_DE_LRC_TOG + no description available + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + LRC_X + Horizontal position in the scan line that determines when DE goes inactive. + 0 + 13 + read-write + oneToToggle + + + LRC_Y + Vertical position in the display that determines when the DE goes inactive. + 16 + 13 + read-write + oneToToggle + + + + + SS_MODE + no description available + 0x60 + 32 + read-write + 0x242400 + 0xFFFFFFFF + + + PIPE_MODE + Sets the sub-sampler mode. 00: bypass 01: 422 subsample 10: 420 subsample 11: bypass + 0 + 2 + read-write + + + COMP_SEL0_OUT + This register field is used to select which 12-bit pixel lane is MUXed to the lowest 12-bit position (hdmi_pdata[11:0]) on the output 36-bit pixel bus: 00: Cr 01: Cb 10: Y 11: N/A + 8 + 2 + read-write + + + COMP_SEL1_OUT + This register field is used to select which 12-bit pixel lane is MUXed to the middle 12-bit position (hdmi_pdata[23:12]) on the output 36-bit pixel bus: 00: Cr 01: Cb 10: Y 11: N/A + 10 + 2 + read-write + + + COMP_SEL2_OUT + This register field is used to select which 12-bit pixel lane is MUXed to the highest 12-bit position (hdmi_pdata[35:24]) on the output 36-bit pixel bus: 00: Cr 01: Cb 10: Y 11: N/A + 12 + 2 + read-write + + + COMP_SEL0_IN + This register field is used to select which 12-bit pixel lane contains the Cb component on the input 36-bit pixel bus (pixdp_data[35:0]): 00: Bits [11:0] 01: Bits [23:12] 10: Bits [35:24] 11: N/A + 16 + 2 + read-write + + + COMP_SEL1_IN + This register field is used to select which 12-bit pixel lane contains the Cr component on the input 36-bit pixel bus (pixdp_data[35:0]): 00: Bits [11:0] 01: Bits [23:12] 10: Bits [35:24] 11: N/A + 18 + 2 + read-write + + + COMP_SEL2_IN + This register field is used to select which 12-bit pixel lane contains the Y component on the input 36-bit pixel bus (pixdp_data[35:0]): 00: Bits [11:0] 01: Bits [23:12] 10: Bits [35:24] 11: N/A + 20 + 2 + read-write + + + + + SS_MODE_SET + no description available + 0x64 + 32 + read-write + 0x242400 + 0xFFFFFFFF + + + PIPE_MODE + Sets the sub-sampler mode. 00: bypass 01: 422 subsample 10: 420 subsample 11: bypass + 0 + 2 + read-write + oneToSet + + + COMP_SEL0_OUT + This register field is used to select which 12-bit pixel lane is MUXed to the lowest 12-bit position (hdmi_pdata[11:0]) on the output 36-bit pixel bus: 00: Cr 01: Cb 10: Y 11: N/A + 8 + 2 + read-write + oneToSet + + + COMP_SEL1_OUT + This register field is used to select which 12-bit pixel lane is MUXed to the middle 12-bit position (hdmi_pdata[23:12]) on the output 36-bit pixel bus: 00: Cr 01: Cb 10: Y 11: N/A + 10 + 2 + read-write + oneToSet + + + COMP_SEL2_OUT + This register field is used to select which 12-bit pixel lane is MUXed to the highest 12-bit position (hdmi_pdata[35:24]) on the output 36-bit pixel bus: 00: Cr 01: Cb 10: Y 11: N/A + 12 + 2 + read-write + oneToSet + + + COMP_SEL0_IN + This register field is used to select which 12-bit pixel lane contains the Cb component on the input 36-bit pixel bus (pixdp_data[35:0]): 00: Bits [11:0] 01: Bits [23:12] 10: Bits [35:24] 11: N/A + 16 + 2 + read-write + oneToSet + + + COMP_SEL1_IN + This register field is used to select which 12-bit pixel lane contains the Cr component on the input 36-bit pixel bus (pixdp_data[35:0]): 00: Bits [11:0] 01: Bits [23:12] 10: Bits [35:24] 11: N/A + 18 + 2 + read-write + oneToSet + + + COMP_SEL2_IN + This register field is used to select which 12-bit pixel lane contains the Y component on the input 36-bit pixel bus (pixdp_data[35:0]): 00: Bits [11:0] 01: Bits [23:12] 10: Bits [35:24] 11: N/A + 20 + 2 + read-write + oneToSet + + + + + SS_MODE_CLR + no description available + 0x68 + 32 + read-write + 0x242400 + 0xFFFFFFFF + + + PIPE_MODE + Sets the sub-sampler mode. 00: bypass 01: 422 subsample 10: 420 subsample 11: bypass + 0 + 2 + read-write + oneToClear + + + COMP_SEL0_OUT + This register field is used to select which 12-bit pixel lane is MUXed to the lowest 12-bit position (hdmi_pdata[11:0]) on the output 36-bit pixel bus: 00: Cr 01: Cb 10: Y 11: N/A + 8 + 2 + read-write + oneToClear + + + COMP_SEL1_OUT + This register field is used to select which 12-bit pixel lane is MUXed to the middle 12-bit position (hdmi_pdata[23:12]) on the output 36-bit pixel bus: 00: Cr 01: Cb 10: Y 11: N/A + 10 + 2 + read-write + oneToClear + + + COMP_SEL2_OUT + This register field is used to select which 12-bit pixel lane is MUXed to the highest 12-bit position (hdmi_pdata[35:24]) on the output 36-bit pixel bus: 00: Cr 01: Cb 10: Y 11: N/A + 12 + 2 + read-write + oneToClear + + + COMP_SEL0_IN + This register field is used to select which 12-bit pixel lane contains the Cb component on the input 36-bit pixel bus (pixdp_data[35:0]): 00: Bits [11:0] 01: Bits [23:12] 10: Bits [35:24] 11: N/A + 16 + 2 + read-write + oneToClear + + + COMP_SEL1_IN + This register field is used to select which 12-bit pixel lane contains the Cr component on the input 36-bit pixel bus (pixdp_data[35:0]): 00: Bits [11:0] 01: Bits [23:12] 10: Bits [35:24] 11: N/A + 18 + 2 + read-write + oneToClear + + + COMP_SEL2_IN + This register field is used to select which 12-bit pixel lane contains the Y component on the input 36-bit pixel bus (pixdp_data[35:0]): 00: Bits [11:0] 01: Bits [23:12] 10: Bits [35:24] 11: N/A + 20 + 2 + read-write + oneToClear + + + + + SS_MODE_TOG + no description available + 0x6C + 32 + read-write + 0x242400 + 0xFFFFFFFF + + + PIPE_MODE + Sets the sub-sampler mode. 00: bypass 01: 422 subsample 10: 420 subsample 11: bypass + 0 + 2 + read-write + oneToToggle + + + COMP_SEL0_OUT + This register field is used to select which 12-bit pixel lane is MUXed to the lowest 12-bit position (hdmi_pdata[11:0]) on the output 36-bit pixel bus: 00: Cr 01: Cb 10: Y 11: N/A + 8 + 2 + read-write + oneToToggle + + + COMP_SEL1_OUT + This register field is used to select which 12-bit pixel lane is MUXed to the middle 12-bit position (hdmi_pdata[23:12]) on the output 36-bit pixel bus: 00: Cr 01: Cb 10: Y 11: N/A + 10 + 2 + read-write + oneToToggle + + + COMP_SEL2_OUT + This register field is used to select which 12-bit pixel lane is MUXed to the highest 12-bit position (hdmi_pdata[35:24]) on the output 36-bit pixel bus: 00: Cr 01: Cb 10: Y 11: N/A + 12 + 2 + read-write + oneToToggle + + + COMP_SEL0_IN + This register field is used to select which 12-bit pixel lane contains the Cb component on the input 36-bit pixel bus (pixdp_data[35:0]): 00: Bits [11:0] 01: Bits [23:12] 10: Bits [35:24] 11: N/A + 16 + 2 + read-write + oneToToggle + + + COMP_SEL1_IN + This register field is used to select which 12-bit pixel lane contains the Cr component on the input 36-bit pixel bus (pixdp_data[35:0]): 00: Bits [11:0] 01: Bits [23:12] 10: Bits [35:24] 11: N/A + 18 + 2 + read-write + oneToToggle + + + COMP_SEL2_IN + This register field is used to select which 12-bit pixel lane contains the Y component on the input 36-bit pixel bus (pixdp_data[35:0]): 00: Bits [11:0] 01: Bits [23:12] 10: Bits [35:24] 11: N/A + 20 + 2 + read-write + oneToToggle + + + + + SS_COEFF + no description available + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + HORIZ_A + Sets the 4 bit horizontal A coefficient. + 0 + 4 + read-write + + + HORIZ_B + Sets the 4 bit horizontal B coefficient. + 4 + 4 + read-write + + + HORIZ_C + Sets the 4 bit horizontal C coefficient. + 8 + 4 + read-write + + + HORIZ_NORM + Sets the 3 bit horizontal filter normalization factor. + 12 + 3 + read-write + + + VERT_A + Sets the 4 bit vertical A coefficient. + 16 + 4 + read-write + + + VERT_B + Sets the 4 bit vertical B coefficient. + 20 + 4 + read-write + + + VERT_C + Sets the 4 bit vertical C coefficient. + 24 + 4 + read-write + + + VERT_NORM + Sets the 3 bit vertical filter normalization factor. + 28 + 3 + read-write + + + + + SS_COEFF_SET + no description available + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + HORIZ_A + Sets the 4 bit horizontal A coefficient. + 0 + 4 + read-write + oneToSet + + + HORIZ_B + Sets the 4 bit horizontal B coefficient. + 4 + 4 + read-write + oneToSet + + + HORIZ_C + Sets the 4 bit horizontal C coefficient. + 8 + 4 + read-write + oneToSet + + + HORIZ_NORM + Sets the 3 bit horizontal filter normalization factor. + 12 + 3 + read-write + oneToSet + + + VERT_A + Sets the 4 bit vertical A coefficient. + 16 + 4 + read-write + oneToSet + + + VERT_B + Sets the 4 bit vertical B coefficient. + 20 + 4 + read-write + oneToSet + + + VERT_C + Sets the 4 bit vertical C coefficient. + 24 + 4 + read-write + oneToSet + + + VERT_NORM + Sets the 3 bit vertical filter normalization factor. + 28 + 3 + read-write + oneToSet + + + + + SS_COEFF_CLR + no description available + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + HORIZ_A + Sets the 4 bit horizontal A coefficient. + 0 + 4 + read-write + oneToClear + + + HORIZ_B + Sets the 4 bit horizontal B coefficient. + 4 + 4 + read-write + oneToClear + + + HORIZ_C + Sets the 4 bit horizontal C coefficient. + 8 + 4 + read-write + oneToClear + + + HORIZ_NORM + Sets the 3 bit horizontal filter normalization factor. + 12 + 3 + read-write + oneToClear + + + VERT_A + Sets the 4 bit vertical A coefficient. + 16 + 4 + read-write + oneToClear + + + VERT_B + Sets the 4 bit vertical B coefficient. + 20 + 4 + read-write + oneToClear + + + VERT_C + Sets the 4 bit vertical C coefficient. + 24 + 4 + read-write + oneToClear + + + VERT_NORM + Sets the 3 bit vertical filter normalization factor. + 28 + 3 + read-write + oneToClear + + + + + SS_COEFF_TOG + no description available + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + HORIZ_A + Sets the 4 bit horizontal A coefficient. + 0 + 4 + read-write + oneToToggle + + + HORIZ_B + Sets the 4 bit horizontal B coefficient. + 4 + 4 + read-write + oneToToggle + + + HORIZ_C + Sets the 4 bit horizontal C coefficient. + 8 + 4 + read-write + oneToToggle + + + HORIZ_NORM + Sets the 3 bit horizontal filter normalization factor. + 12 + 3 + read-write + oneToToggle + + + VERT_A + Sets the 4 bit vertical A coefficient. + 16 + 4 + read-write + oneToToggle + + + VERT_B + Sets the 4 bit vertical B coefficient. + 20 + 4 + read-write + oneToToggle + + + VERT_C + Sets the 4 bit vertical C coefficient. + 24 + 4 + read-write + oneToToggle + + + VERT_NORM + Sets the 3 bit vertical filter normalization factor. + 28 + 3 + read-write + oneToToggle + + + + + SS_CLIP_CB + no description available + 0x80 + 32 + read-write + 0xFFF0000 + 0xFFFFFFFF + + + MIN + Set minimum value for Cb clipping function + 0 + 12 + read-write + + + MAX + Set maximum value for Cb clipping function + 16 + 12 + read-write + + + + + SS_CLIP_CB_SET + no description available + 0x84 + 32 + read-write + 0xFFF0000 + 0xFFFFFFFF + + + MIN + Set minimum value for Cb clipping function + 0 + 12 + read-write + oneToSet + + + MAX + Set maximum value for Cb clipping function + 16 + 12 + read-write + oneToSet + + + + + SS_CLIP_CB_CLR + no description available + 0x88 + 32 + read-write + 0xFFF0000 + 0xFFFFFFFF + + + MIN + Set minimum value for Cb clipping function + 0 + 12 + read-write + oneToClear + + + MAX + Set maximum value for Cb clipping function + 16 + 12 + read-write + oneToClear + + + + + SS_CLIP_CB_TOG + no description available + 0x8C + 32 + read-write + 0xFFF0000 + 0xFFFFFFFF + + + MIN + Set minimum value for Cb clipping function + 0 + 12 + read-write + oneToToggle + + + MAX + Set maximum value for Cb clipping function + 16 + 12 + read-write + oneToToggle + + + + + SS_CLIP_CR + no description available + 0x90 + 32 + read-write + 0xFFF0000 + 0xFFFFFFFF + + + MIN + Set minimum value for Cr clipping function + 0 + 12 + read-write + + + MAX + Set maximum value for Cr clipping function + 16 + 12 + read-write + + + + + SS_CLIP_CR_SET + no description available + 0x94 + 32 + read-write + 0xFFF0000 + 0xFFFFFFFF + + + MIN + Set minimum value for Cr clipping function + 0 + 12 + read-write + oneToSet + + + MAX + Set maximum value for Cr clipping function + 16 + 12 + read-write + oneToSet + + + + + SS_CLIP_CR_CLR + no description available + 0x98 + 32 + read-write + 0xFFF0000 + 0xFFFFFFFF + + + MIN + Set minimum value for Cr clipping function + 0 + 12 + read-write + oneToClear + + + MAX + Set maximum value for Cr clipping function + 16 + 12 + read-write + oneToClear + + + + + SS_CLIP_CR_TOG + no description available + 0x9C + 32 + read-write + 0xFFF0000 + 0xFFFFFFFF + + + MIN + Set minimum value for Cr clipping function + 0 + 12 + read-write + oneToToggle + + + MAX + Set maximum value for Cr clipping function + 16 + 12 + read-write + oneToToggle + + + + + SS_INTER_MODE + no description available + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT_EN + Set this bit to 1 to enable interlaced HDMI timing. + 0 + 1 + read-write + + + VSYNC_SHIFT + Set 0 to run in general interlaced mode + 1 + 1 + read-write + + + + + SS_INTER_MODE_SET + no description available + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT_EN + Set this bit to 1 to enable interlaced HDMI timing. + 0 + 1 + read-write + oneToSet + + + VSYNC_SHIFT + Set 0 to run in general interlaced mode + 1 + 1 + read-write + oneToSet + + + + + SS_INTER_MODE_CLR + no description available + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT_EN + Set this bit to 1 to enable interlaced HDMI timing. + 0 + 1 + read-write + oneToClear + + + VSYNC_SHIFT + Set 0 to run in general interlaced mode + 1 + 1 + read-write + oneToClear + + + + + SS_INTER_MODE_TOG + no description available + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + INT_EN + Set this bit to 1 to enable interlaced HDMI timing. + 0 + 1 + read-write + oneToToggle + + + VSYNC_SHIFT + Set 0 to run in general interlaced mode + 1 + 1 + read-write + oneToToggle + + + + + SS_CHKSUM_CTRL + no description available + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHKSUM_EN + This register field is used to enable or disable the checksum hardware from running + 0 + 1 + read-write + + + CHKSUM_EN_0 + Checksum is disabled. + 0 + + + CHKSUM_EN_1 + Checksum is enabled. + 0x1 + + + + + NUM_FRAMES + This register field is used to select the duration of a checksum measurement + 4 + 4 + read-write + + + NUM_FRAMES_0 + Continuous mode. Output a checksum after each start trigger to end trigger process. + 0 + + + NUM_FRAMES_1 + Accumulate the cheksum over one complete frame. + 0x1 + + + NUM_FRAMES_2 + Accumulate the cheksum over two complete frames. + 0x2 + + + NUM_FRAMES_3 + Accumulate the cheksum over NUM_FRAMES complete frames. + 0x3 + + + NUM_FRAMES_4 + Accumulate the cheksum over NUM_FRAMES complete frames. + 0x4 + + + NUM_FRAMES_5 + Accumulate the cheksum over NUM_FRAMES complete frames. + 0x5 + + + NUM_FRAMES_6 + Accumulate the cheksum over NUM_FRAMES complete frames. + 0x6 + + + NUM_FRAMES_7 + Accumulate the cheksum over NUM_FRAMES complete frames. + 0x7 + + + NUM_FRAMES_8 + Accumulate the cheksum over NUM_FRAMES complete frames. + 0x8 + + + NUM_FRAMES_9 + Accumulate the cheksum over NUM_FRAMES complete frames. + 0x9 + + + + + + + SS_CHKSUM_START + no description available + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + VCOUNT_START + This register field selects the starting vertical coordinate within a frame to begin running the checksum generator + 0 + 13 + read-write + + + HCOUNT_START + This register field selects the starting horizontal coordinate within a frame to begin running the checksum generator + 16 + 13 + read-write + + + + + SS_CHKSUM_END + no description available + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + VCOUNT_END + This register field selects the vertical coordinate within a frame to stop running the checksum generator + 0 + 13 + read-write + + + HCOUNT_END + This register field selects the horizontal coordinate within a frame to stop running the checksum generator + 16 + 13 + read-write + + + + + SS_CHKSUM_DATA_LOW + no description available + 0xBC + 32 + read-only + 0 + 0xFFFFFFFF + + + CHKSUM_RESULT + This register holds the lowest 32-bits of the 42-bit checksum result + 0 + 32 + read-only + + + + + SS_CHKSUM_DATA_HIGH + no description available + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHKSUM_RESULT + This register holds the lowest 32-bits of the 42-bit checksum result + 0 + 10 + read-only + + + CHKSUM_VLD + This register field is used to indicate then the CHKSUM_RESULT is valid + 31 + 1 + read-write + oneToClear + + + + + + + DCSS__MED_DC_SCALER + no description available + MED_DC_SCALER + 0x32E1C000 + + 0 + 0xF3 + registers + + + + SCALE_CTRL + Scale Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE_SCALER + This bit, when set to logic 1, causes the scaler to begin processing a frame buffer based on all current programmable settings + 0 + 1 + read-write + + + ENABLE_REPEAT + This bit enables the scaler to restart processing a frame buffer without receiving a SW "kick" event using the ENABLE_SCALER control bit + 4 + 1 + read-write + + + ENABLE_SCALE2MEM + This bit enables the path from the scaler output back to the system memory + 8 + 1 + read-write + + + ENABLE_MEM2OFIFO + This bit enables the path from external memory to drive the data into the scale output FIFO + 12 + 1 + read-write + + + + + SCALE_OFIFO_CTRL + Scale Output FIFO Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFIFO_LOW_THRESH + This value is used to detect when the output FIFO has a number of pixels that are valid that first exceeds this value, and then decrements to a value equal to the value programmed in this register + 0 + 10 + read-write + + + OFIFO_HIGH_THRESH + This value is used to detect when the output FIFO has a number of pixels that are valid that first exceeds this value, and then decrements to a value equal to the value programmed in this register + 16 + 10 + read-write + + + CLEAR_UNDERRUN_DETECT + This bit clears the underrun detected interrupt + 26 + 1 + read-write + + + CLEAR_LOW_THRESH_DETECT + This bit clears the low threshold detect interrupt 0: disabled, no action + 27 + 1 + read-write + + + CLEAR_HIGH_THRESH_DETECT + This bit clears the high threshold detect interrupt + 28 + 1 + read-write + + + ENABLE_UNDERRUN_DETECT + This bit controls if the underrun on the output FIFO can generate an interrupt + 29 + 1 + read-write + + + ENABLE_LOW_THRESH_DETECT + This bit controls if the low threshold detection of the output FIFO can generate an interrupt + 30 + 1 + read-write + + + ENABLE_HIGH_THRESH_DETECT + This bit controls if the high threshold detection of the output FIFO can generate an interrupt + 31 + 1 + read-write + + + + + SCALE_SRC_DATA_CTRL + Scale Source Data Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRC_SELECT + This bit controls whether the source is Video format(YUV) or Graphics(RGB) + 0 + 1 + read-write + + + RTRAM_LINES_PER_BANK + This field determines the number of lines that are used in each bank of the RTRAM_CTRL module + 1 + 1 + read-write + + + Y_UV_BYTE_SWAP + This bit controls the swapping of alternate bytes in the incoming data word + 4 + 1 + read-write + + + A2R10G10B10_FORMAT + This field represents the data arrangement in the memory in case 10 RGB mode + 8 + 4 + read-write + + + + + SCALE_BIT_DEPTH + Scale Bit Depth Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + LUMA_BIT_DEPTH + These bits determine the bit depth of the primary component (Y, RGB) processing + 0 + 2 + read-write + + + CHROMA_BIT_DEPTH + These bits determine the bit depth of the alternate component (UV 2-plane) processing + 4 + 2 + read-write + + + + + SCALE_SRC_FORMAT + Scale Source Format Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRC_FORMAT + These bits define the input buffer format + 0 + 2 + read-write + + + + + SCALE_DST_FORMAT + Scale Destination Format Control Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + DST_FORMAT + These bits define the scaler output format. 1: YUV422. 2: RGB888/YUV444. Other: Reserved. + 0 + 2 + read-write + + + + + SCALE_SRC_LUMA_RES + Scale Source Luma Resolution Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + WIDTH + This field defines the width of the source image in pixels minus 1 + 0 + 12 + read-write + + + HEIGHT + This field defines the height of the source image in pixels minus 1 + 16 + 12 + read-write + + + + + SCALE_SRC_CHROMA_RES + Scale Source Chroma Resolution Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + WIDTH + This field defines the width of the source image in pixels minus 1 + 0 + 12 + read-write + + + HEIGHT + This field defines the height of the source image in pixels minus 1 + 16 + 12 + read-write + + + + + SCALE_DST_LUMA_RES + Scale Destination Luma Resolution Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + WIDTH + This field defines the width of the destination image in pixels minus 1. + 0 + 12 + read-write + + + HEIGHT + This field defines the height of the destination image in pixels minus 1. + 16 + 12 + read-write + + + + + SCALE_DST_CHROMA_RES + Scale Destination Chroma Resolution Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + WIDTH + This field defines the width of the destination image in pixels minus 1. + 0 + 12 + read-write + + + + + SCALE_V_LUMA_START + Scale Vertical Luma Start Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + V_START + This register contains 13 integer and 13 fractional bits to define the vertical offset into the start of the prefetched image + 0 + 26 + read-write + + + + + SCALE_V_LUMA_INC + Scale Vertical Luma Increment Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + V_INC + Vertical increment value used for scaling the image + 0 + 20 + read-write + + + + + SCALE_H_LUMA_START + Scale Horizontal Luma Start Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + H_START + This register contains 13 integer and 13 fractional bits to define the horizontal offset into the start of the prefetched image + 0 + 26 + read-write + + + + + SCALE_H_LUMA_INC + Scale Horizontal Luma Increment Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + H_INC + Horizontal increment value used for scaling the image + 0 + 20 + read-write + + + + + SCALE_V_CHROMA_START + Scale Vertical Chroma Start Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + V_START + This register contains 13 integer and 13 fractional bits to define the vertical offset into the start of the prefetched image + 0 + 26 + read-write + + + + + SCALE_V_CHROMA_INC + Scale Vertical Chroma Increment Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + V_INC + Vertical increment value used for scaling the image + 0 + 20 + read-write + + + + + SCALE_H_CHROMA_START + Scale Horizontal Chroma Start Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + H_START + This register contains 13 integer and 13 fractional bits to define the horizontal offset into the start of the prefetched image + 0 + 26 + read-write + + + + + SCALE_H_CHROMA_INC + Scale Horizontal Chroma Increment Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + H_INC + Horizontal increment value used for scaling the image + 0 + 20 + read-write + + + + + SCALE_COEF_ARRAY + Scale Coefficient Memory Array + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + COEF + The coefficients have 1-bit sign, 1-bit integer, and 10-bits fraction + 0 + 12 + read-write + + + + + + + DCSS__DTG + no description available + DTG + 0x32E20000 + + 0 + 0x80 + registers + + + + TC_CONTROL_STATUS + Timing Controller Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_VIDEO_BASE_PATH_ENABLE + Enable channel3 (Dolby_mode:Base Layer channel ) processing + 0 + 1 + read-write + + + TC_VIDEO_ENH_PATH_ENABLE + Enable channel_2 (Dolby_mode:Enhancement channel ) processing + 1 + 1 + read-write + + + TC_OVERLAY_PATH_ENABLE + Enable channel_1 (Dolby_mode:Overlay /HDR10: (GFX)) processing + 2 + 1 + read-write + + + TC_OVERLAY_FIFO_DATA_MODE + Overlay fifo output data in yuv or RGB mode 0: YUV 1: RGB + 3 + 1 + read-write + + + TC_BLENDER_VIDEO_ALPHA_SELECT + alpha_valid 0: No alpha in the ch1 pixel so use default foreground alpha TC_DEFAULT_OVERLAY_ALPHA 1: there is an alpha in ch1 pixel + 7 + 1 + read-write + + + TC_GO + Used to start and stop timing controller 0: timing controller inactive + 8 + 1 + read-write + + + TC_DOLBY_MODE + Enables Dolby mode + 9 + 1 + read-write + + + TC_CH1_PER_PEL_ALPHA_SEL + Enables per pixel alpha for channel1 (Overlay or Graphics) 0: use alpha from TC_DEFAULT_OVERLAY_ALPHA or foreground alpha 1: use alpha from channel1 Data stream and apply blending per pixel + 10 + 1 + read-write + + + TC_CSS_PIX_COMP_SWAP + Permutes the pixel conponent ordering into the chroma subsampler (CSS) block + 12 + 3 + read-write + + + TC_DEFAULT_OVERLAY_ALPHA + Default alpha foreground used for the active regions where graphics channel does not provide an alpha value This is used when Graphics channel is ONLY RGB + 24 + 8 + read-write + + + + + TC_DTG_REG1 + DTG lower right corner locations + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_DTG_LOWER_RIGHT_X + lower right corner X (horizontal) coordinate of the raster table + 0 + 13 + read-write + + + TC_DTG_LOWER_RIGHT_Y + lower right corner Y (vertical) coordinate of the raster table + 16 + 13 + read-write + + + + + TC_DISPLAY_REG2 + Display Register: TOP Window Coordinates for Active display area + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_DISPLAY_UPPER_LEFT_X + upper left corner X (horizontal) coordinate of the active dispplay region + 0 + 13 + read-write + + + TC_DISPLAY_UPPER_LEFT_Y + upper left corner Y (vertical) coordinate of the active display region + 16 + 13 + read-write + + + + + TC_DISPLAY_REG3 + Display Register: BOTTOM Window Coordinates for Active display area + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_DISPLAY_LOWER_RIGHT_X + lower rignt corner X (horizontal) coordinate of the active dispplay region + 0 + 13 + read-write + + + TC_DISPLAY_LOWER_RIGHT_Y + lower right corner Y (vertical) coordinate of the active display region + 16 + 13 + read-write + + + + + TC_CH1_REG4 + Channel 1 window Register: TOP Window Coordinates for channel1 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_CHANNEL_1_UPPER_LEFT_X + upper left corner X (horizontal) coordinate of the channel_1 window + 0 + 13 + read-write + + + TC_CHANNEL_1_UPPER_LEFT_Y + upper left corner Y (vertical) coordinate of the channel_1 window + 16 + 13 + read-write + + + + + TC_CH1_REG5 + Channel_1 window Register: BOTTOM Window Coordinates for channel_1 window + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_CHANNEL_1_LOWER_RIGHT_X + lower rignt corner X (horizontal) coordinate of the channel_1 window + 0 + 13 + read-write + + + TC_CHANNEL_1_LOWER_RIGHT_Y + lower right corner Y (vertical) coordinate of the channel_1 window + 16 + 13 + read-write + + + + + TC_CH2_REG6 + Channel 2 window Register: TOP Window Coordinates for channel_2 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_CHANNEL_2_UPPER_LEFT_X + upper left corner X (horizontal) coordinate of the channel_2 window + 0 + 13 + read-write + + + TC_CHANNEL_2_UPPER_LEFT_Y + upper left corner Y (vertical) coordinate of the channel_2 window + 16 + 13 + read-write + + + + + TC_CH2_REG7 + Channel_2 window Register: BOTTOM Window Coordinates for channel_2 pixel window + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_CHANNEL_2_LOWER_RIGHT_X + lower rignt corner X (horizontal) coordinate of the channel_2 window + 0 + 13 + read-write + + + TC_CHANNEL_2_LOWER_RIGHT_Y + lower right corner Y (vertical) coordinate of the channel_2 window + 16 + 13 + read-write + + + + + TC_CH3_REG8 + Channel 3 window Register: TOP Window Coordinates for channel_3 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_CHANNEL_3_UPPER_LEFT_X + upper left corner X (horizontal) coordinate of the channel_3 window + 0 + 13 + read-write + + + TC_CHANNEL_3_UPPER_LEFT_Y + upper left corner Y (vertical) coordinate of the channel_3 window + 16 + 13 + read-write + + + + + TC_CH3_REG9 + Channel_3 window Register: BOTTOM Window Coordinates for channel_3 pixel window + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_CHANNEL_3_LOWER_RIGHT_X + lower rignt corner X (horizontal) coordinate of the channel_3 window + 0 + 13 + read-write + + + TC_CHANNEL_3_LOWER_RIGHT_Y + lower right corner Y (vertical) coordinate of the channel_3 window + 16 + 13 + read-write + + + + + TC_CTX_LD_REG10 + Context Loader Register: Coordinates in the raster table where the context loader is started. + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_CNTXT_DB_LINE_COUNT + Line Count for Double Buffered (DB) Context Loading + 0 + 13 + read-write + + + TC_CNTXT_SB_LINE_COUNT + Line Count for Sngle Bufferend (SB) Context Loading + 16 + 13 + read-write + + + + + TC_CH1_BKRND_REG11 + Channel_1 background pixel color. + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_CH1_BKRND_PEL_COMP_3 + 10-bit component ( B or Cr ) + 0 + 10 + read-write + + + TC_CH1_BKRND_PEL_COMP_2 + 10-bit component ( G or Cb ) + 10 + 10 + read-write + + + TC_CH1_BKRND_PEL_COMP_1 + 10-bit component ( R or Y ) + 20 + 10 + read-write + + + + + TC_CH2_BKRND_REG12 + Channel_2 background pixel color. + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_CH2_BKRND_PEL_COMP_3 + 10-bit component ( B or Cr ) + 0 + 10 + read-write + + + TC_CH2_BKRND_PEL_COMP_2 + 10-bit component ( G or Cb ) + 10 + 10 + read-write + + + TC_CH2_BKRND_PEL_COMP_1 + 10-bit component ( R or Y ) + 20 + 10 + read-write + + + + + BLENDER_DBY_EOTF_RANGEINV + DBY MODE Blender control. + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLENDER_EOTF_RANGEINV + eotf_rangeInv parameter for DBY blender + 0 + 17 + read-write + + + + + BLENDER_DBY_EOTF_RANGEMIN + DBY MODE Blender control. + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + BLENDER_EOTF_RANGEMIN + eotf_rangeMin parameter for DBY blender + 0 + 17 + read-write + + + + + BLENDER_DBY_BDP + DBY MODE blender control. + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLENDER_BDP + bitDepth parameter in DBY blender + 0 + 5 + read-write + + + + + BLENDER_BKRND_I_GRAPHICS + Backgound pixel color component sent to blender. Used when no valid pixels + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLENDER_BCKRND_I_COMP + 28-bit component I component in DBY mode R/Y component in HDR10 MODE + 0 + 28 + read-write + + + + + BLENDER_BKRND_P_GRAPHICS + Backgound pixel color component sent to blender. Used when no valid pixels + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLENDER_BCKRND_P_COMP + 28-bit component P component in DBY mode G/Cb component in HDR10 MODE + 0 + 28 + read-write + + + + + BLENDER_BKRND_T_GRAPHICS + Backgound pixel color component sent to blender. Used when no valid pixels + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + BLENDER_BCKRND_T_COMP + 28-bit component T component in DBY mode B/Cr component in HDR10 MODE + 0 + 28 + read-write + + + + + TC_LINE1_INT_REG13 + LINE1 interrupt control: Coordinate where line1 interrupt is asserted + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_LINE1_INT_X + X (horizontal) coordinate for line1 interrupt + 0 + 13 + read-write + + + TC_LINE1_INT_Y + Y (vertical) coordinate for line1 interrupt + 16 + 13 + read-write + + + + + TC_LINE2_INT_REG14 + LINE2 interrupt control: Coordinate where line2 interrupt is asserted + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_LINE2_INT_X + X (horizontal) coordinate for line2 interrupt + 0 + 13 + read-write + + + TC_LINE2_INT_Y + Y (vertical) coordinate for line2 interrupt + 16 + 13 + read-write + + + + + TC_ALPHA_DEFAULT_REG15 + default alpha + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_ALPHA_DEF + default background alpha value + 0 + 8 + read-write + + + + + TC_INTERRUPT_STATUS + Timing Controller interrupt status + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + TC_LINE0_INTERRUPT + LINE0 interrupt status + 0 + 1 + read-only + + + TC_LINE1_INTERRUPT + LINE1 interrupt status + 1 + 1 + read-only + + + TC_LINE2_INTERRUPT + LINE2 interrupt status + 2 + 1 + read-only + + + TC_LINE3_INTERRUPT + LINE3 interrupt status + 3 + 1 + read-only + + + TC_RTRAM_CH1_PANIC_INTERRUPT + Panic interrupt is asserted by the scaler for channel1 + 4 + 1 + read-only + + + TC_RTRAM_CH2_PANIC_INTERRUPT + Panic interrupt is asserted by the scaler for channel2 + 5 + 1 + read-only + + + TC_RTRAM_CH3_PANIC_INTERRUPT + Panic interrupt is asserted by the scaler for channel3 + 6 + 1 + read-only + + + + + TC_INTRERRUPT_CONTROL_REG17 + Timing Controller interrupt control. + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_LINE0_INTERRUPT_CLR + Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register. + 0 + 1 + read-write + + + TC_LINE1_INTERRUPT_CLR + Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register. + 1 + 1 + read-write + + + TC_LINE2_INTERRUPT_CLR + Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register. + 2 + 1 + read-write + + + TC_LINE3_INTERRUPT_CLR + Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register. + 3 + 1 + read-write + + + TC_RTRAM_CH1_PANIC_INTERRUPT_CLR + Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register + 4 + 1 + read-write + + + TC_RTRAM_CH2_PANIC_INTERRUPT_CLR + Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register + 5 + 1 + read-write + + + TC_RTRAM_CH3_PANIC_INTERRUPT_CLR + Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register + 6 + 1 + read-write + + + + + TC_CH3_BKRND_REG18 + Channel_3 background pixel color. + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_CH3_BKRND_PEL_COMP_3 + 10-bit component ( B or Cr ) + 0 + 10 + read-write + + + TC_CH3_BKRND_PEL_COMP_2 + 10-bit component ( G or Cb ) + 10 + 10 + read-write + + + TC_CH3_BKRND_PEL_COMP_1 + 10-bit component ( R or Y ) + 20 + 10 + read-write + + + + + TC_INTRERRUPT_MASK + Timing Controller interrupt masks + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_LINE0_INT_MASK + LINE0 interrupt status + 0 + 1 + read-write + + + TC_LINE1_INT_MASK + LINE1 interrupt status + 1 + 1 + read-write + + + TC_LINE2_INT_MASK + LINE2 interrupt status + 2 + 1 + read-write + + + TC_LINE3_INT_MASK + LINE3 interrupt status + 3 + 1 + read-write + + + TC_RTRAM_CH1_PANIC_INT_MASK + Mask bit for Channel 1 Panic interrupt asserted by the scaler 0: interrupt is disabled (masked) 1: panic interrupt is enabled + 4 + 1 + read-write + + + TC_RTRAM_CH2_PANIC_INT_MASK + Mask bit for Channel 2 Panic interrupt asserted by the scaler 0: interrupt is disabled (masked) 1: panic interrupt is enabled + 5 + 1 + read-write + + + TC_RTRAM_CH3_PANIC_INT_MASK + Mask bit for Channel 3 Panic interrupt asserted by the scaler 0: interrupt is disabled (masked) 1: panic interrupt is enabled + 6 + 1 + read-write + + + + + TC_LINE3_INT_REG + LINE3 interrupt control: Coordinate where line3 interrupt is asserted + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_LINE3_INT_X + X (horizontal) coordinate for line3 interrupt + 0 + 13 + read-write + + + TC_LINE3_INT_Y + Y (vertical) coordinate for line3 interrupt + 16 + 13 + read-write + + + + + TC_LINE4_INT_REG + LINE4 interrupt control: Coordinate where line4 interrupt is asserted + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_LINE4_INT_X + X (horizontal) coordinate for line4 interrupt + 0 + 13 + read-write + + + TC_LINE4_INT_Y + Y (vertical) coordinate for line4 interrupt + 16 + 13 + read-write + + + + + TC_OL_DE_CONTROL_REG + For DBY Mode: Controls the assertion and de-assertion DE signal (Overlay channel). + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_DE_SET_LOW_X + X (horizontal) coordinate Where DE control signal is set to 0 in a line. + 0 + 13 + read-write + + + TC_DE_SET_HIGH_X + X (horizontal) coordinate Where DE control signal is set to 1 in a line. + 16 + 13 + read-write + + + TC_INVERT_DE_X + 0: DE signal is not inverted 1: DE signal is INVERTED + 31 + 1 + read-write + + + + + TC_BL_DE_CONTROL_REG + For DBY Mode: Controls the assertion and de-assertion DE signal (Base layer (BL) channel). + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_DE_SET_LOW_X + X (horizontal) coordinate Where DE control signal is set to 0 in a line. + 0 + 13 + read-write + + + TC_DE_SET_HIGH_X + X (horizontal) coordinate Where DE control signal is set to 1 in a line. + 16 + 13 + read-write + + + TC_INVERT_DE_X + 0: DE signal is not inverted 1: DE signal is INVERTED + 31 + 1 + read-write + + + + + TC_EL_DE_CONTROL_REG + For DBY Mode: Controls the assertion and de-assertion DE signal (Enhancement layer (EL) channel). + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_DE_SET_LOW_X + X (horizontal) coordinate Where DE control signal is set to 0 in a line. + 0 + 13 + read-write + + + TC_DE_SET_HIGH_X + X (horizontal) coordinate Where DE control signal is set to 1 in a line. + 16 + 13 + read-write + + + TC_INVERT_DE_X + 0: DE signal is not inverted 1: DE signal is INVERTED + 31 + 1 + read-write + + + + + + + DCSS__WR_SCL + no description available + WR_SCL + 0x32E21000 + + 0 + 0x18 + registers + + + + CTRL_STATUS + Control register for Context Loader. + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable / Busy + 0 + 1 + read-write + + + REPEAT + Repeat feature + 1 + 1 + read-write + + + BPP + Bits per pixel + 2 + 3 + read-write + + + T_SIZE + Transaction Size + 5 + 2 + read-write + + + P_SIZE + Payload Size + 7 + 3 + read-write + + + P_FREQ + Payload frequency + 10 + 8 + read-write + + + FIFO_SIZE + Size of FIFO in design + 18 + 7 + read-only + + + FRAME_COMP_EN + Write error IRQ enable + 28 + 1 + read-write + + + FRAME_COMP + Indicates the current frame being processed has finished. + 29 + 1 + read-write + oneToClear + + + WR_ERR_EN + Write error IRQ enable + 30 + 1 + read-write + + + WR_ERR + Indicates a write error on the axi interface. + 31 + 1 + read-write + oneToClear + + + + + CTRL_STATUS_SET + Control register for Context Loader. + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable / Busy + 0 + 1 + read-write + oneToSet + + + REPEAT + Repeat feature + 1 + 1 + read-write + oneToSet + + + BPP + Bits per pixel + 2 + 3 + read-write + oneToSet + + + T_SIZE + Transaction Size + 5 + 2 + read-write + oneToSet + + + P_SIZE + Payload Size + 7 + 3 + read-write + oneToSet + + + P_FREQ + Payload frequency + 10 + 8 + read-write + oneToSet + + + FIFO_SIZE + Size of FIFO in design + 18 + 7 + read-only + oneToSet + + + FRAME_COMP_EN + Write error IRQ enable + 28 + 1 + read-write + oneToSet + + + FRAME_COMP + Indicates the current frame being processed has finished. + 29 + 1 + read-write + oneToSet + + + WR_ERR_EN + Write error IRQ enable + 30 + 1 + read-write + oneToSet + + + WR_ERR + Indicates a write error on the axi interface. + 31 + 1 + read-write + oneToSet + + + + + CTRL_STATUS_CLR + Control register for Context Loader. + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable / Busy + 0 + 1 + read-write + oneToClear + + + REPEAT + Repeat feature + 1 + 1 + read-write + oneToClear + + + BPP + Bits per pixel + 2 + 3 + read-write + oneToClear + + + T_SIZE + Transaction Size + 5 + 2 + read-write + oneToClear + + + P_SIZE + Payload Size + 7 + 3 + read-write + oneToClear + + + P_FREQ + Payload frequency + 10 + 8 + read-write + oneToClear + + + FIFO_SIZE + Size of FIFO in design + 18 + 7 + read-only + oneToClear + + + FRAME_COMP_EN + Write error IRQ enable + 28 + 1 + read-write + oneToClear + + + FRAME_COMP + Indicates the current frame being processed has finished. + 29 + 1 + read-write + oneToClear + + + WR_ERR_EN + Write error IRQ enable + 30 + 1 + read-write + oneToClear + + + WR_ERR + Indicates a write error on the axi interface. + 31 + 1 + read-write + oneToClear + + + + + CTRL_STATUS_TOG + Control register for Context Loader. + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable / Busy + 0 + 1 + read-write + oneToToggle + + + REPEAT + Repeat feature + 1 + 1 + read-write + oneToToggle + + + BPP + Bits per pixel + 2 + 3 + read-write + oneToToggle + + + T_SIZE + Transaction Size + 5 + 2 + read-write + oneToToggle + + + P_SIZE + Payload Size + 7 + 3 + read-write + oneToToggle + + + P_FREQ + Payload frequency + 10 + 8 + read-write + oneToToggle + + + FIFO_SIZE + Size of FIFO in design + 18 + 7 + read-only + oneToToggle + + + FRAME_COMP_EN + Write error IRQ enable + 28 + 1 + read-write + oneToToggle + + + FRAME_COMP + Indicates the current frame being processed has finished. + 29 + 1 + read-write + oneToToggle + + + WR_ERR_EN + Write error IRQ enable + 30 + 1 + read-write + oneToToggle + + + WR_ERR + Indicates a write error on the axi interface. + 31 + 1 + read-write + oneToToggle + + + + + BASE_ADDR + Holds the base address + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE_ADDR + Base address + 0 + 32 + read-write + + + + + PITCH + Pitch + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Vertical pitch for memory address calculation. + 0 + 16 + read-write + + + + + + + DCSS__RD_SRC + no description available + RD_SRC + 0x32E22000 + + 0 + 0x20 + registers + + + + CTRL_STATUS + Control register for Read surface. + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Read surface enable. + 0 + 1 + read-write + + + BPP + Bits per pixel + 2 + 3 + read-write + + + T_SIZE + Transaction Size (T_SIZE) + 5 + 2 + read-write + + + P_SIZE + Payload size (P_SIZE) + 7 + 3 + read-write + + + FRAME_COMP_EN + Frame complete IRQ enable + 14 + 1 + read-write + + + RD_ERR_EN + AXI Read Error IRQ enable + 15 + 1 + read-write + + + FIFO_SIZE + FIFO size + 16 + 7 + read-only + + + FRAME_COMP + Frame processing complete + 30 + 1 + read-write + oneToClear + + + RD_ERR + AXI Read Error + 31 + 1 + read-write + oneToClear + + + + + CTRL_STATUS_SET + Control register for Read surface. + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Read surface enable. + 0 + 1 + read-write + oneToSet + + + BPP + Bits per pixel + 2 + 3 + read-write + oneToSet + + + T_SIZE + Transaction Size (T_SIZE) + 5 + 2 + read-write + oneToSet + + + P_SIZE + Payload size (P_SIZE) + 7 + 3 + read-write + oneToSet + + + FRAME_COMP_EN + Frame complete IRQ enable + 14 + 1 + read-write + oneToSet + + + RD_ERR_EN + AXI Read Error IRQ enable + 15 + 1 + read-write + oneToSet + + + FIFO_SIZE + FIFO size + 16 + 7 + read-only + oneToSet + + + FRAME_COMP + Frame processing complete + 30 + 1 + read-write + oneToSet + + + RD_ERR + AXI Read Error + 31 + 1 + read-write + oneToSet + + + + + CTRL_STATUS_CLR + Control register for Read surface. + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Read surface enable. + 0 + 1 + read-write + oneToClear + + + BPP + Bits per pixel + 2 + 3 + read-write + oneToClear + + + T_SIZE + Transaction Size (T_SIZE) + 5 + 2 + read-write + oneToClear + + + P_SIZE + Payload size (P_SIZE) + 7 + 3 + read-write + oneToClear + + + FRAME_COMP_EN + Frame complete IRQ enable + 14 + 1 + read-write + oneToClear + + + RD_ERR_EN + AXI Read Error IRQ enable + 15 + 1 + read-write + oneToClear + + + FIFO_SIZE + FIFO size + 16 + 7 + read-only + oneToClear + + + FRAME_COMP + Frame processing complete + 30 + 1 + read-write + oneToClear + + + RD_ERR + AXI Read Error + 31 + 1 + read-write + oneToClear + + + + + CTRL_STATUS_TOG + Control register for Read surface. + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Read surface enable. + 0 + 1 + read-write + oneToToggle + + + BPP + Bits per pixel + 2 + 3 + read-write + oneToToggle + + + T_SIZE + Transaction Size (T_SIZE) + 5 + 2 + read-write + oneToToggle + + + P_SIZE + Payload size (P_SIZE) + 7 + 3 + read-write + oneToToggle + + + FRAME_COMP_EN + Frame complete IRQ enable + 14 + 1 + read-write + oneToToggle + + + RD_ERR_EN + AXI Read Error IRQ enable + 15 + 1 + read-write + oneToToggle + + + FIFO_SIZE + FIFO size + 16 + 7 + read-only + oneToToggle + + + FRAME_COMP + Frame processing complete + 30 + 1 + read-write + oneToToggle + + + RD_ERR + AXI Read Error + 31 + 1 + read-write + oneToToggle + + + + + BASE_ADDR + Read Surface Base address + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE_ADDR + Base address + 0 + 32 + read-write + + + + + PITCH + Read surface vertical pitch + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Pitch + 0 + 16 + read-write + + + + + WIDTH + Source frame buffer width + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + WIDTH + Width + 0 + 16 + read-write + + + + + HEIGHT + Height of frame to be read + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + HEIGHT + Height + 0 + 16 + read-write + + + + + + + DCSS__CTX_LD + no description available + CTX_LD + 0x32E23000 + + 0 + 0x24 + registers + + + + CTRL_STATUS + Control status register for Context Loader. + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable/Busy + 0 + 1 + read-write + + + ARB_SEL + Arbitration select + 1 + 1 + read-write + + + RD_ERR_EN + AXI read error IRQ enable + 2 + 1 + read-write + + + DB_COMP_EN + Double buffer region loading complete IRQ enable + 3 + 1 + read-write + + + SB_HP_COMP_EN + Single buffer high priority region loading complete IRQ enable + 4 + 1 + read-write + + + SB_LP_COMP_EN + Single buffer low priority region loading complete IRQ enable + 5 + 1 + read-write + + + DB_PEND_SB_REC_EN + Double/single region overlap interrupt enable + 6 + 1 + read-write + + + SB_PEND_DISP_ACTIVE_EN + Single/active region overlap interrupt enable. + 7 + 1 + read-write + + + AHB_ERR_EN + AHB error IRQ enable + 8 + 1 + read-write + + + RD_ERR + AXI read error + 16 + 1 + read-write + oneToClear + + + DB_COMP + Double buffer region loading complete + 17 + 1 + read-write + oneToClear + + + SB_HP_COMP + Single buffer high priority region loading complete + 18 + 1 + read-write + oneToClear + + + SB_LP_COMP + Single buffer low priority region loading complete IRQ enable + 19 + 1 + read-write + oneToClear + + + DB_PEND_SB_REC + Double/single region overlap + 20 + 1 + read-write + oneToClear + + + SB_PEND_DISP_ACTIVE + Single/active region overlap + 21 + 1 + read-write + oneToClear + + + AHB_ERR + AHB error + 22 + 1 + read-write + oneToClear + + + + + CTRL_STATUS_SET + Control status register for Context Loader. + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable/Busy + 0 + 1 + read-write + oneToSet + + + ARB_SEL + Arbitration select + 1 + 1 + read-write + oneToSet + + + RD_ERR_EN + AXI read error IRQ enable + 2 + 1 + read-write + oneToSet + + + DB_COMP_EN + Double buffer region loading complete IRQ enable + 3 + 1 + read-write + oneToSet + + + SB_HP_COMP_EN + Single buffer high priority region loading complete IRQ enable + 4 + 1 + read-write + oneToSet + + + SB_LP_COMP_EN + Single buffer low priority region loading complete IRQ enable + 5 + 1 + read-write + oneToSet + + + DB_PEND_SB_REC_EN + Double/single region overlap interrupt enable + 6 + 1 + read-write + oneToSet + + + SB_PEND_DISP_ACTIVE_EN + Single/active region overlap interrupt enable. + 7 + 1 + read-write + oneToSet + + + AHB_ERR_EN + AHB error IRQ enable + 8 + 1 + read-write + oneToSet + + + RD_ERR + AXI read error + 16 + 1 + read-write + oneToSet + + + DB_COMP + Double buffer region loading complete + 17 + 1 + read-write + oneToSet + + + SB_HP_COMP + Single buffer high priority region loading complete + 18 + 1 + read-write + oneToSet + + + SB_LP_COMP + Single buffer low priority region loading complete IRQ enable + 19 + 1 + read-write + oneToSet + + + DB_PEND_SB_REC + Double/single region overlap + 20 + 1 + read-write + oneToSet + + + SB_PEND_DISP_ACTIVE + Single/active region overlap + 21 + 1 + read-write + oneToSet + + + AHB_ERR + AHB error + 22 + 1 + read-write + oneToSet + + + + + CTRL_STATUS_CLR + Control status register for Context Loader. + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable/Busy + 0 + 1 + read-write + oneToClear + + + ARB_SEL + Arbitration select + 1 + 1 + read-write + oneToClear + + + RD_ERR_EN + AXI read error IRQ enable + 2 + 1 + read-write + oneToClear + + + DB_COMP_EN + Double buffer region loading complete IRQ enable + 3 + 1 + read-write + oneToClear + + + SB_HP_COMP_EN + Single buffer high priority region loading complete IRQ enable + 4 + 1 + read-write + oneToClear + + + SB_LP_COMP_EN + Single buffer low priority region loading complete IRQ enable + 5 + 1 + read-write + oneToClear + + + DB_PEND_SB_REC_EN + Double/single region overlap interrupt enable + 6 + 1 + read-write + oneToClear + + + SB_PEND_DISP_ACTIVE_EN + Single/active region overlap interrupt enable. + 7 + 1 + read-write + oneToClear + + + AHB_ERR_EN + AHB error IRQ enable + 8 + 1 + read-write + oneToClear + + + RD_ERR + AXI read error + 16 + 1 + read-write + oneToClear + + + DB_COMP + Double buffer region loading complete + 17 + 1 + read-write + oneToClear + + + SB_HP_COMP + Single buffer high priority region loading complete + 18 + 1 + read-write + oneToClear + + + SB_LP_COMP + Single buffer low priority region loading complete IRQ enable + 19 + 1 + read-write + oneToClear + + + DB_PEND_SB_REC + Double/single region overlap + 20 + 1 + read-write + oneToClear + + + SB_PEND_DISP_ACTIVE + Single/active region overlap + 21 + 1 + read-write + oneToClear + + + AHB_ERR + AHB error + 22 + 1 + read-write + oneToClear + + + + + CTRL_STATUS_TOG + Control status register for Context Loader. + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable/Busy + 0 + 1 + read-write + oneToToggle + + + ARB_SEL + Arbitration select + 1 + 1 + read-write + oneToToggle + + + RD_ERR_EN + AXI read error IRQ enable + 2 + 1 + read-write + oneToToggle + + + DB_COMP_EN + Double buffer region loading complete IRQ enable + 3 + 1 + read-write + oneToToggle + + + SB_HP_COMP_EN + Single buffer high priority region loading complete IRQ enable + 4 + 1 + read-write + oneToToggle + + + SB_LP_COMP_EN + Single buffer low priority region loading complete IRQ enable + 5 + 1 + read-write + oneToToggle + + + DB_PEND_SB_REC_EN + Double/single region overlap interrupt enable + 6 + 1 + read-write + oneToToggle + + + SB_PEND_DISP_ACTIVE_EN + Single/active region overlap interrupt enable. + 7 + 1 + read-write + oneToToggle + + + AHB_ERR_EN + AHB error IRQ enable + 8 + 1 + read-write + oneToToggle + + + RD_ERR + AXI read error + 16 + 1 + read-write + oneToToggle + + + DB_COMP + Double buffer region loading complete + 17 + 1 + read-write + oneToToggle + + + SB_HP_COMP + Single buffer high priority region loading complete + 18 + 1 + read-write + oneToToggle + + + SB_LP_COMP + Single buffer low priority region loading complete IRQ enable + 19 + 1 + read-write + oneToToggle + + + DB_PEND_SB_REC + Double/single region overlap + 20 + 1 + read-write + oneToToggle + + + SB_PEND_DISP_ACTIVE + Single/active region overlap + 21 + 1 + read-write + oneToToggle + + + AHB_ERR + AHB error + 22 + 1 + read-write + oneToToggle + + + + + DB_BASE_ADDR + DRAM addr for double buffered register fetch. + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DB_BASE_ADDR + Double buffered registers base address. + 0 + 32 + read-write + + + + + DB_COUNT + Double buffer register count + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + DB_COUNT + Double buffered region fetch count + 0 + 16 + read-write + + + + + SB_BASE_ADDR + DRAM addr for single buffered registers. + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + SB_BASE_ADDR + Single buffered register base address. + 0 + 32 + read-write + + + + + SB_COUNT + Single buffer register count + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + HP_COUNT + Single buffered high priority region fetch count + 0 + 16 + read-write + + + LP_COUNT + Single buffered low priority region fetch count + 16 + 16 + read-write + + + + + AHB_ERR_ADDR + AHB address with error response. + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + AHB_ERR_ADDR + AHB error address. + 0 + 32 + read-only + + + + + + + DCSS__LUT_LD + no description available + LUT_LD + 0x32E24000 + + 0 + 0x14 + registers + + + + CTRL_STATUS + Control/Status register for LUT Loader. + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable LUT_LD + 0 + 1 + read-write + + + BYTES_PER_REQ + bytes per request control + 1 + 1 + read-write + + + RD_ERR_EN + AXI Read Error IRQ enable. + 8 + 1 + read-write + + + RD_ERR + AXI Read Error. + 16 + 1 + read-write + oneToClear + + + + + CTRL_STATUS_SET + Control/Status register for LUT Loader. + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable LUT_LD + 0 + 1 + read-write + oneToSet + + + BYTES_PER_REQ + bytes per request control + 1 + 1 + read-write + oneToSet + + + RD_ERR_EN + AXI Read Error IRQ enable. + 8 + 1 + read-write + oneToSet + + + RD_ERR + AXI Read Error. + 16 + 1 + read-write + oneToSet + + + + + CTRL_STATUS_CLR + Control/Status register for LUT Loader. + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable LUT_LD + 0 + 1 + read-write + oneToClear + + + BYTES_PER_REQ + bytes per request control + 1 + 1 + read-write + oneToClear + + + RD_ERR_EN + AXI Read Error IRQ enable. + 8 + 1 + read-write + oneToClear + + + RD_ERR + AXI Read Error. + 16 + 1 + read-write + oneToClear + + + + + CTRL_STATUS_TOG + Control/Status register for LUT Loader. + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable LUT_LD + 0 + 1 + read-write + oneToToggle + + + BYTES_PER_REQ + bytes per request control + 1 + 1 + read-write + oneToToggle + + + RD_ERR_EN + AXI Read Error IRQ enable. + 8 + 1 + read-write + oneToToggle + + + RD_ERR + AXI Read Error. + 16 + 1 + read-write + oneToToggle + + + + + BASE_ADDR + Address for data fetch. + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE_ADDR + Base Address + 0 + 32 + read-write + + + + + + + IRQ_STEER + IRQSTEER + IRQ_STEER + 0x32E2D000 + + 0 + 0xCC + registers + + + + CHANnCTL + Channel n Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0 + Channel 0 control + 0 + 1 + read-write + + + CH0_0 + Disable channel 0 + 0 + + + CH0_1 + Enable channel 0 + 0x1 + + + + + CH1 + Channel 1 control + 1 + 1 + read-write + + + CH1_0 + Disable channel 1 + 0 + + + CH1_1 + Enable channel 1 + 0x1 + + + + + CH2 + Channel 2 control + 2 + 1 + read-write + + + CH2_0 + Disable channel 2 + 0 + + + CH2_1 + Enable channel 2 + 0x1 + + + + + CH3 + Channel 3 control + 3 + 1 + read-write + + + CH3_0 + Disable channel 3 + 0 + + + CH3_1 + Enable channel 3 + 0x1 + + + + + CH4 + Channel 4 control + 4 + 1 + read-write + + + CH4_0 + Disable channel 4 + 0 + + + CH4_1 + Enable channel 4 + 0x1 + + + + + + + 16 + 0x4 + CHn_MASK[%s] + Channel n Interrupt Mask Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASKFLD + Mask bits + 0 + 32 + read-write + + + MASKFLD_0 + Mask interrupt + 0 + + + MASKFLD_1 + Do not mask interrupt + 0x1 + + + + + + + 16 + 0x4 + CHn_SET[%s] + Channel n Interrupt Set Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORCEFLD + Brief bitfield description. + 0 + 32 + read-write + + + FORCEFLD_0 + Normal operation + 0 + + + FORCEFLD_1 + Force interrupt + 0x1 + + + + + + + 16 + 0x4 + CHn_STATUS[%s] + Channel n Interrupt Status Register + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + STATUS + Status of an interrupt + 0 + 32 + read-only + + + STATUS_0 + Interrupt is not set. + 0 + + + STATUS_1 + Interrupt is set. + 0x1 + + + + + + + CHn_MINTDIS + Channel n Master Interrupt Disable Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DISABLE + Each bit of this field disables the corresponding interrupts in table above. + 0 + 8 + read-write + + + DISABLE_0 + Enable interrupts + 0 + + + DISABLE_1 + Disable interrupts + 0x1 + + + + + + + CHn_MSTRSTAT + Channel n Master Status Register + 0xC8 + 32 + read-only + 0 + 0xFFFFFFFF + + + STATUS + Status of all interrupts + 0 + 1 + read-only + + + STATUS_0 + No interrupts are asserted. + 0 + + + STATUS_1 + At least one interrupt is asserted. + 0x1 + + + + + + + + + DCSS__BLK_CTL + no description available + BLK_CTL + 0x32E2F000 + + 0 + 0x50 + registers + + + + RESET_CTRL + Reset Control + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + B_CLK_RESETN + b_clk domain modules resetn + 0 + 1 + read-write + + + APB_CLK_RESETN + apb_clk domain modules resetn + 1 + 1 + read-write + + + P_CLK_RESETN + p_clk domain modules resetn + 2 + 1 + read-write + + + RTR_CLK_RESETN + rtr_clk domain modules resetn + 3 + 1 + read-write + + + SPARE_CLK_RESETN + spare clk domain resetn + 16 + 8 + read-write + + + + + RESET_CTRL_SET + Reset Control + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + B_CLK_RESETN + b_clk domain modules resetn + 0 + 1 + read-write + oneToSet + + + APB_CLK_RESETN + apb_clk domain modules resetn + 1 + 1 + read-write + oneToSet + + + P_CLK_RESETN + p_clk domain modules resetn + 2 + 1 + read-write + oneToSet + + + RTR_CLK_RESETN + rtr_clk domain modules resetn + 3 + 1 + read-write + oneToSet + + + SPARE_CLK_RESETN + spare clk domain resetn + 16 + 8 + read-write + oneToSet + + + + + RESET_CTRL_CLR + Reset Control + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + B_CLK_RESETN + b_clk domain modules resetn + 0 + 1 + read-write + oneToClear + + + APB_CLK_RESETN + apb_clk domain modules resetn + 1 + 1 + read-write + oneToClear + + + P_CLK_RESETN + p_clk domain modules resetn + 2 + 1 + read-write + oneToClear + + + RTR_CLK_RESETN + rtr_clk domain modules resetn + 3 + 1 + read-write + oneToClear + + + SPARE_CLK_RESETN + spare clk domain resetn + 16 + 8 + read-write + oneToClear + + + + + RESET_CTRL_TOG + Reset Control + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + B_CLK_RESETN + b_clk domain modules resetn + 0 + 1 + read-write + oneToToggle + + + APB_CLK_RESETN + apb_clk domain modules resetn + 1 + 1 + read-write + oneToToggle + + + P_CLK_RESETN + p_clk domain modules resetn + 2 + 1 + read-write + oneToToggle + + + RTR_CLK_RESETN + rtr_clk domain modules resetn + 3 + 1 + read-write + oneToToggle + + + SPARE_CLK_RESETN + spare clk domain resetn + 16 + 8 + read-write + oneToToggle + + + + + CONTROL0 + Control + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DISPMIX_REFCLK_SEL + Display Subsystem Reference Clock Select + 4 + 2 + read-write + + + DISPMIX_PIXCLK_SEL + Display Subsystem Pixel Clock Select + 8 + 1 + read-write + + + + + CONTROL0_SET + Control + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + DISPMIX_REFCLK_SEL + Display Subsystem Reference Clock Select + 4 + 2 + read-write + oneToSet + + + DISPMIX_PIXCLK_SEL + Display Subsystem Pixel Clock Select + 8 + 1 + read-write + oneToSet + + + + + CONTROL0_CLR + Control + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + DISPMIX_REFCLK_SEL + Display Subsystem Reference Clock Select + 4 + 2 + read-write + oneToClear + + + DISPMIX_PIXCLK_SEL + Display Subsystem Pixel Clock Select + 8 + 1 + read-write + oneToClear + + + + + CONTROL0_TOG + Control + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + DISPMIX_REFCLK_SEL + Display Subsystem Reference Clock Select + 4 + 2 + read-write + oneToToggle + + + DISPMIX_PIXCLK_SEL + Display Subsystem Pixel Clock Select + 8 + 1 + read-write + oneToToggle + + + + + SPARE_CTRL0 + Spare Control0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SPARE_CTRL + SPARE Control + 0 + 32 + read-write + + + + + SPARE_CTRL0_SET + Spare Control0 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + SPARE_CTRL + SPARE Control + 0 + 32 + read-write + oneToSet + + + + + SPARE_CTRL0_CLR + Spare Control0 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + SPARE_CTRL + SPARE Control + 0 + 32 + read-write + oneToClear + + + + + SPARE_CTRL0_TOG + Spare Control0 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + SPARE_CTRL + SPARE Control + 0 + 32 + read-write + oneToToggle + + + + + SPARE_CTRL1 + Spare Control1 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + SPARE_CTRL + SPARE Control + 0 + 32 + read-write + + + + + SPARE_CTRL1_SET + Spare Control1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + SPARE_CTRL + SPARE Control + 0 + 32 + read-write + oneToSet + + + + + SPARE_CTRL1_CLR + Spare Control1 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + SPARE_CTRL + SPARE Control + 0 + 32 + read-write + oneToClear + + + + + SPARE_CTRL1_TOG + Spare Control1 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + SPARE_CTRL + SPARE Control + 0 + 32 + read-write + oneToToggle + + + + + SPARE_STATUS0 + Spare Status0 + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + SPARE_STATUS + SPARE Control + 0 + 32 + read-only + + + + + SPARE_STATUS0_SET + Spare Status0 + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + SPARE_STATUS + SPARE Control + 0 + 32 + read-only + oneToSet + + + + + SPARE_STATUS0_CLR + Spare Status0 + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + SPARE_STATUS + SPARE Control + 0 + 32 + read-only + oneToClear + + + + + SPARE_STATUS0_TOG + Spare Status0 + 0x4C + 32 + read-only + 0 + 0xFFFFFFFF + + + SPARE_STATUS + SPARE Control + 0 + 32 + read-only + oneToToggle + + + + + + + APBH + APBH Register Reference Index + APBH + APBH_ + 0x33000000 + + 0 + 0x804 + registers + + + APBHDMA + 12 + + + + CTRL0 + AHB to APBH Bridge Control and Status Register 0 + 0 + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + These bits must be set to zero for normal operation of each channel + 0 + 16 + read-write + + + NAND0 + NAND0 + 0x1 + + + NAND1 + NAND1 + 0x2 + + + NAND2 + NAND2 + 0x4 + + + NAND3 + NAND3 + 0x8 + + + NAND4 + NAND4 + 0x10 + + + NAND5 + NAND5 + 0x20 + + + NAND6 + NAND6 + 0x40 + + + NAND7 + NAND7 + 0x80 + + + SSP + SSP + 0x100 + + + + + APB_BURST_EN + Set this bit to one to enable apb master do a continous transfers when a device request a burst dma + 28 + 1 + read-write + + + AHB_BURST8_EN + Set this bit to one (default) to enable AHB 8-beat burst + 29 + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal APBH DMA operation + 31 + 1 + read-write + + + + + CTRL0_SET + AHB to APBH Bridge Control and Status Register 0 + 0x4 + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + These bits must be set to zero for normal operation of each channel + 0 + 16 + read-write + + + NAND0 + NAND0 + 0x1 + + + NAND1 + NAND1 + 0x2 + + + NAND2 + NAND2 + 0x4 + + + NAND3 + NAND3 + 0x8 + + + NAND4 + NAND4 + 0x10 + + + NAND5 + NAND5 + 0x20 + + + NAND6 + NAND6 + 0x40 + + + NAND7 + NAND7 + 0x80 + + + SSP + SSP + 0x100 + + + + + APB_BURST_EN + Set this bit to one to enable apb master do a continous transfers when a device request a burst dma + 28 + 1 + read-write + + + AHB_BURST8_EN + Set this bit to one (default) to enable AHB 8-beat burst + 29 + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal APBH DMA operation + 31 + 1 + read-write + + + + + CTRL0_CLR + AHB to APBH Bridge Control and Status Register 0 + 0x8 + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + These bits must be set to zero for normal operation of each channel + 0 + 16 + read-write + + + NAND0 + NAND0 + 0x1 + + + NAND1 + NAND1 + 0x2 + + + NAND2 + NAND2 + 0x4 + + + NAND3 + NAND3 + 0x8 + + + NAND4 + NAND4 + 0x10 + + + NAND5 + NAND5 + 0x20 + + + NAND6 + NAND6 + 0x40 + + + NAND7 + NAND7 + 0x80 + + + SSP + SSP + 0x100 + + + + + APB_BURST_EN + Set this bit to one to enable apb master do a continous transfers when a device request a burst dma + 28 + 1 + read-write + + + AHB_BURST8_EN + Set this bit to one (default) to enable AHB 8-beat burst + 29 + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal APBH DMA operation + 31 + 1 + read-write + + + + + CTRL0_TOG + AHB to APBH Bridge Control and Status Register 0 + 0xC + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + These bits must be set to zero for normal operation of each channel + 0 + 16 + read-write + + + NAND0 + NAND0 + 0x1 + + + NAND1 + NAND1 + 0x2 + + + NAND2 + NAND2 + 0x4 + + + NAND3 + NAND3 + 0x8 + + + NAND4 + NAND4 + 0x10 + + + NAND5 + NAND5 + 0x20 + + + NAND6 + NAND6 + 0x40 + + + NAND7 + NAND7 + 0x80 + + + SSP + SSP + 0x100 + + + + + APB_BURST_EN + Set this bit to one to enable apb master do a continous transfers when a device request a burst dma + 28 + 1 + read-write + + + AHB_BURST8_EN + Set this bit to one (default) to enable AHB 8-beat burst + 29 + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal APBH DMA operation + 31 + 1 + read-write + + + + + CTRL1 + AHB to APBH Bridge Control and Status Register 1 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 0 + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 1 + 1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 2 + 2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 3 + 3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 4 + 4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 5 + 5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 6 + 6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 7 + 7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 8 + 8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 9 + 9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 10 + 10 + 1 + read-write + + + CH11_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 11 + 11 + 1 + read-write + + + CH12_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 12 + 12 + 1 + read-write + + + CH13_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 13 + 13 + 1 + read-write + + + CH14_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 14 + 14 + 1 + read-write + + + CH15_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 15 + 15 + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. + 16 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. + 17 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. + 18 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. + 19 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. + 20 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. + 21 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. + 22 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. + 23 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 8. + 24 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 9. + 25 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 10. + 26 + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 11. + 27 + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 12. + 28 + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 13. + 29 + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 14. + 30 + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 15. + 31 + 1 + read-write + + + + + CTRL1_SET + AHB to APBH Bridge Control and Status Register 1 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 0 + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 1 + 1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 2 + 2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 3 + 3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 4 + 4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 5 + 5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 6 + 6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 7 + 7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 8 + 8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 9 + 9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 10 + 10 + 1 + read-write + + + CH11_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 11 + 11 + 1 + read-write + + + CH12_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 12 + 12 + 1 + read-write + + + CH13_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 13 + 13 + 1 + read-write + + + CH14_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 14 + 14 + 1 + read-write + + + CH15_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 15 + 15 + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. + 16 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. + 17 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. + 18 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. + 19 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. + 20 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. + 21 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. + 22 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. + 23 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 8. + 24 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 9. + 25 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 10. + 26 + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 11. + 27 + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 12. + 28 + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 13. + 29 + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 14. + 30 + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 15. + 31 + 1 + read-write + + + + + CTRL1_CLR + AHB to APBH Bridge Control and Status Register 1 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 0 + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 1 + 1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 2 + 2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 3 + 3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 4 + 4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 5 + 5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 6 + 6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 7 + 7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 8 + 8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 9 + 9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 10 + 10 + 1 + read-write + + + CH11_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 11 + 11 + 1 + read-write + + + CH12_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 12 + 12 + 1 + read-write + + + CH13_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 13 + 13 + 1 + read-write + + + CH14_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 14 + 14 + 1 + read-write + + + CH15_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 15 + 15 + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. + 16 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. + 17 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. + 18 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. + 19 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. + 20 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. + 21 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. + 22 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. + 23 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 8. + 24 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 9. + 25 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 10. + 26 + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 11. + 27 + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 12. + 28 + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 13. + 29 + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 14. + 30 + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 15. + 31 + 1 + read-write + + + + + CTRL1_TOG + AHB to APBH Bridge Control and Status Register 1 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 0 + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 1 + 1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 2 + 2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 3 + 3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 4 + 4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 5 + 5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 6 + 6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 7 + 7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 8 + 8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 9 + 9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 10 + 10 + 1 + read-write + + + CH11_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 11 + 11 + 1 + read-write + + + CH12_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 12 + 12 + 1 + read-write + + + CH13_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 13 + 13 + 1 + read-write + + + CH14_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 14 + 14 + 1 + read-write + + + CH15_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 15 + 15 + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. + 16 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. + 17 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. + 18 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. + 19 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. + 20 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. + 21 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. + 22 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. + 23 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 8. + 24 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 9. + 25 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 10. + 26 + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 11. + 27 + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 12. + 28 + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 13. + 29 + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 14. + 30 + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 15. + 31 + 1 + read-write + + + + + CTRL2 + AHB to APBH Bridge Control and Status Register 2 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 0 + 0 + 1 + read-write + + + CH1_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 1 + 1 + 1 + read-write + + + CH2_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 2 + 2 + 1 + read-write + + + CH3_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 3 + 3 + 1 + read-write + + + CH4_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 4 + 4 + 1 + read-write + + + CH5_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 5 + 5 + 1 + read-write + + + CH6_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 6 + 6 + 1 + read-write + + + CH7_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 7 + 7 + 1 + read-write + + + CH8_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 8 + 8 + 1 + read-write + + + CH9_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 9 + 9 + 1 + read-write + + + CH10_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 10 + 10 + 1 + read-write + + + CH11_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 11 + 11 + 1 + read-write + + + CH12_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 12 + 12 + 1 + read-write + + + CH13_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 13 + 13 + 1 + read-write + + + CH14_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 14 + 14 + 1 + read-write + + + CH15_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 15 + 15 + 1 + read-write + + + CH0_ERROR_STATUS + Error status bit for APBX DMA Channel 0 + 16 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH1_ERROR_STATUS + Error status bit for APBX DMA Channel 1 + 17 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH2_ERROR_STATUS + Error status bit for APBX DMA Channel 2 + 18 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH3_ERROR_STATUS + Error status bit for APBX DMA Channel 3 + 19 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH4_ERROR_STATUS + Error status bit for APBX DMA Channel 4 + 20 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH5_ERROR_STATUS + Error status bit for APBX DMA Channel 5 + 21 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH6_ERROR_STATUS + Error status bit for APBX DMA Channel 6 + 22 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH7_ERROR_STATUS + Error status bit for APBX DMA Channel 7 + 23 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH8_ERROR_STATUS + Error status bit for APBH DMA Channel 8 + 24 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH9_ERROR_STATUS + Error status bit for APBH DMA Channel 9 + 25 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH10_ERROR_STATUS + Error status bit for APBH DMA Channel 10 + 26 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH11_ERROR_STATUS + Error status bit for APBH DMA Channel 11 + 27 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH12_ERROR_STATUS + Error status bit for APBH DMA Channel 12 + 28 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH13_ERROR_STATUS + Error status bit for APBH DMA Channel 13 + 29 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH14_ERROR_STATUS + Error status bit for APBH DMA Channel 14 + 30 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH15_ERROR_STATUS + Error status bit for APBH DMA Channel 15 + 31 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + + + CTRL2_SET + AHB to APBH Bridge Control and Status Register 2 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 0 + 0 + 1 + read-write + + + CH1_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 1 + 1 + 1 + read-write + + + CH2_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 2 + 2 + 1 + read-write + + + CH3_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 3 + 3 + 1 + read-write + + + CH4_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 4 + 4 + 1 + read-write + + + CH5_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 5 + 5 + 1 + read-write + + + CH6_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 6 + 6 + 1 + read-write + + + CH7_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 7 + 7 + 1 + read-write + + + CH8_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 8 + 8 + 1 + read-write + + + CH9_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 9 + 9 + 1 + read-write + + + CH10_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 10 + 10 + 1 + read-write + + + CH11_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 11 + 11 + 1 + read-write + + + CH12_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 12 + 12 + 1 + read-write + + + CH13_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 13 + 13 + 1 + read-write + + + CH14_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 14 + 14 + 1 + read-write + + + CH15_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 15 + 15 + 1 + read-write + + + CH0_ERROR_STATUS + Error status bit for APBX DMA Channel 0 + 16 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH1_ERROR_STATUS + Error status bit for APBX DMA Channel 1 + 17 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH2_ERROR_STATUS + Error status bit for APBX DMA Channel 2 + 18 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH3_ERROR_STATUS + Error status bit for APBX DMA Channel 3 + 19 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH4_ERROR_STATUS + Error status bit for APBX DMA Channel 4 + 20 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH5_ERROR_STATUS + Error status bit for APBX DMA Channel 5 + 21 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH6_ERROR_STATUS + Error status bit for APBX DMA Channel 6 + 22 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH7_ERROR_STATUS + Error status bit for APBX DMA Channel 7 + 23 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH8_ERROR_STATUS + Error status bit for APBH DMA Channel 8 + 24 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH9_ERROR_STATUS + Error status bit for APBH DMA Channel 9 + 25 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH10_ERROR_STATUS + Error status bit for APBH DMA Channel 10 + 26 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH11_ERROR_STATUS + Error status bit for APBH DMA Channel 11 + 27 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH12_ERROR_STATUS + Error status bit for APBH DMA Channel 12 + 28 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH13_ERROR_STATUS + Error status bit for APBH DMA Channel 13 + 29 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH14_ERROR_STATUS + Error status bit for APBH DMA Channel 14 + 30 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH15_ERROR_STATUS + Error status bit for APBH DMA Channel 15 + 31 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + + + CTRL2_CLR + AHB to APBH Bridge Control and Status Register 2 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 0 + 0 + 1 + read-write + + + CH1_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 1 + 1 + 1 + read-write + + + CH2_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 2 + 2 + 1 + read-write + + + CH3_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 3 + 3 + 1 + read-write + + + CH4_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 4 + 4 + 1 + read-write + + + CH5_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 5 + 5 + 1 + read-write + + + CH6_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 6 + 6 + 1 + read-write + + + CH7_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 7 + 7 + 1 + read-write + + + CH8_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 8 + 8 + 1 + read-write + + + CH9_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 9 + 9 + 1 + read-write + + + CH10_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 10 + 10 + 1 + read-write + + + CH11_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 11 + 11 + 1 + read-write + + + CH12_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 12 + 12 + 1 + read-write + + + CH13_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 13 + 13 + 1 + read-write + + + CH14_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 14 + 14 + 1 + read-write + + + CH15_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 15 + 15 + 1 + read-write + + + CH0_ERROR_STATUS + Error status bit for APBX DMA Channel 0 + 16 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH1_ERROR_STATUS + Error status bit for APBX DMA Channel 1 + 17 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH2_ERROR_STATUS + Error status bit for APBX DMA Channel 2 + 18 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH3_ERROR_STATUS + Error status bit for APBX DMA Channel 3 + 19 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH4_ERROR_STATUS + Error status bit for APBX DMA Channel 4 + 20 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH5_ERROR_STATUS + Error status bit for APBX DMA Channel 5 + 21 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH6_ERROR_STATUS + Error status bit for APBX DMA Channel 6 + 22 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH7_ERROR_STATUS + Error status bit for APBX DMA Channel 7 + 23 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH8_ERROR_STATUS + Error status bit for APBH DMA Channel 8 + 24 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH9_ERROR_STATUS + Error status bit for APBH DMA Channel 9 + 25 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH10_ERROR_STATUS + Error status bit for APBH DMA Channel 10 + 26 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH11_ERROR_STATUS + Error status bit for APBH DMA Channel 11 + 27 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH12_ERROR_STATUS + Error status bit for APBH DMA Channel 12 + 28 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH13_ERROR_STATUS + Error status bit for APBH DMA Channel 13 + 29 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH14_ERROR_STATUS + Error status bit for APBH DMA Channel 14 + 30 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH15_ERROR_STATUS + Error status bit for APBH DMA Channel 15 + 31 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + + + CTRL2_TOG + AHB to APBH Bridge Control and Status Register 2 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 0 + 0 + 1 + read-write + + + CH1_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 1 + 1 + 1 + read-write + + + CH2_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 2 + 2 + 1 + read-write + + + CH3_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 3 + 3 + 1 + read-write + + + CH4_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 4 + 4 + 1 + read-write + + + CH5_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 5 + 5 + 1 + read-write + + + CH6_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 6 + 6 + 1 + read-write + + + CH7_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 7 + 7 + 1 + read-write + + + CH8_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 8 + 8 + 1 + read-write + + + CH9_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 9 + 9 + 1 + read-write + + + CH10_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 10 + 10 + 1 + read-write + + + CH11_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 11 + 11 + 1 + read-write + + + CH12_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 12 + 12 + 1 + read-write + + + CH13_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 13 + 13 + 1 + read-write + + + CH14_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 14 + 14 + 1 + read-write + + + CH15_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 15 + 15 + 1 + read-write + + + CH0_ERROR_STATUS + Error status bit for APBX DMA Channel 0 + 16 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH1_ERROR_STATUS + Error status bit for APBX DMA Channel 1 + 17 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH2_ERROR_STATUS + Error status bit for APBX DMA Channel 2 + 18 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH3_ERROR_STATUS + Error status bit for APBX DMA Channel 3 + 19 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH4_ERROR_STATUS + Error status bit for APBX DMA Channel 4 + 20 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH5_ERROR_STATUS + Error status bit for APBX DMA Channel 5 + 21 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH6_ERROR_STATUS + Error status bit for APBX DMA Channel 6 + 22 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH7_ERROR_STATUS + Error status bit for APBX DMA Channel 7 + 23 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH8_ERROR_STATUS + Error status bit for APBH DMA Channel 8 + 24 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH9_ERROR_STATUS + Error status bit for APBH DMA Channel 9 + 25 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH10_ERROR_STATUS + Error status bit for APBH DMA Channel 10 + 26 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH11_ERROR_STATUS + Error status bit for APBH DMA Channel 11 + 27 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH12_ERROR_STATUS + Error status bit for APBH DMA Channel 12 + 28 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH13_ERROR_STATUS + Error status bit for APBH DMA Channel 13 + 29 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH14_ERROR_STATUS + Error status bit for APBH DMA Channel 14 + 30 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH15_ERROR_STATUS + Error status bit for APBH DMA Channel 15 + 31 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + + + CHANNEL_CTRL + AHB to APBH Bridge Channel Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FREEZE_CHANNEL + Setting a bit in this field will freeze the DMA channel associated with it + 0 + 16 + read-write + + + NAND0 + NAND0 + 0x1 + + + NAND1 + NAND1 + 0x2 + + + NAND2 + NAND2 + 0x4 + + + NAND3 + NAND3 + 0x8 + + + NAND4 + NAND4 + 0x10 + + + NAND5 + NAND5 + 0x20 + + + NAND6 + NAND6 + 0x40 + + + NAND7 + NAND7 + 0x80 + + + SSP + SSP + 0x100 + + + + + RESET_CHANNEL + Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state + 16 + 16 + read-write + + + NAND0 + NAND0 + 0x1 + + + NAND1 + NAND1 + 0x2 + + + NAND2 + NAND2 + 0x4 + + + NAND3 + NAND3 + 0x8 + + + NAND4 + NAND4 + 0x10 + + + NAND5 + NAND5 + 0x20 + + + NAND6 + NAND6 + 0x40 + + + NAND7 + NAND7 + 0x80 + + + SSP + SSP + 0x100 + + + + + + + CHANNEL_CTRL_SET + AHB to APBH Bridge Channel Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + FREEZE_CHANNEL + Setting a bit in this field will freeze the DMA channel associated with it + 0 + 16 + read-write + + + NAND0 + NAND0 + 0x1 + + + NAND1 + NAND1 + 0x2 + + + NAND2 + NAND2 + 0x4 + + + NAND3 + NAND3 + 0x8 + + + NAND4 + NAND4 + 0x10 + + + NAND5 + NAND5 + 0x20 + + + NAND6 + NAND6 + 0x40 + + + NAND7 + NAND7 + 0x80 + + + SSP + SSP + 0x100 + + + + + RESET_CHANNEL + Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state + 16 + 16 + read-write + + + NAND0 + NAND0 + 0x1 + + + NAND1 + NAND1 + 0x2 + + + NAND2 + NAND2 + 0x4 + + + NAND3 + NAND3 + 0x8 + + + NAND4 + NAND4 + 0x10 + + + NAND5 + NAND5 + 0x20 + + + NAND6 + NAND6 + 0x40 + + + NAND7 + NAND7 + 0x80 + + + SSP + SSP + 0x100 + + + + + + + CHANNEL_CTRL_CLR + AHB to APBH Bridge Channel Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FREEZE_CHANNEL + Setting a bit in this field will freeze the DMA channel associated with it + 0 + 16 + read-write + + + NAND0 + NAND0 + 0x1 + + + NAND1 + NAND1 + 0x2 + + + NAND2 + NAND2 + 0x4 + + + NAND3 + NAND3 + 0x8 + + + NAND4 + NAND4 + 0x10 + + + NAND5 + NAND5 + 0x20 + + + NAND6 + NAND6 + 0x40 + + + NAND7 + NAND7 + 0x80 + + + SSP + SSP + 0x100 + + + + + RESET_CHANNEL + Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state + 16 + 16 + read-write + + + NAND0 + NAND0 + 0x1 + + + NAND1 + NAND1 + 0x2 + + + NAND2 + NAND2 + 0x4 + + + NAND3 + NAND3 + 0x8 + + + NAND4 + NAND4 + 0x10 + + + NAND5 + NAND5 + 0x20 + + + NAND6 + NAND6 + 0x40 + + + NAND7 + NAND7 + 0x80 + + + SSP + SSP + 0x100 + + + + + + + CHANNEL_CTRL_TOG + AHB to APBH Bridge Channel Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + FREEZE_CHANNEL + Setting a bit in this field will freeze the DMA channel associated with it + 0 + 16 + read-write + + + NAND0 + NAND0 + 0x1 + + + NAND1 + NAND1 + 0x2 + + + NAND2 + NAND2 + 0x4 + + + NAND3 + NAND3 + 0x8 + + + NAND4 + NAND4 + 0x10 + + + NAND5 + NAND5 + 0x20 + + + NAND6 + NAND6 + 0x40 + + + NAND7 + NAND7 + 0x80 + + + SSP + SSP + 0x100 + + + + + RESET_CHANNEL + Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state + 16 + 16 + read-write + + + NAND0 + NAND0 + 0x1 + + + NAND1 + NAND1 + 0x2 + + + NAND2 + NAND2 + 0x4 + + + NAND3 + NAND3 + 0x8 + + + NAND4 + NAND4 + 0x10 + + + NAND5 + NAND5 + 0x20 + + + NAND6 + NAND6 + 0x40 + + + NAND7 + NAND7 + 0x80 + + + SSP + SSP + 0x100 + + + + + + + DEVSEL + AHB to APBH DMA Device Assignment Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + DMA_BURST_SIZE + AHB to APBH DMA burst size + 0x50 + 32 + read-write + 0x555555 + 0xFFFFFFFF + + + CH0 + DMA burst size for GPMI channel 0. Do not change. GPMI only support burst size 4. + 0 + 2 + read-write + + + CH1 + DMA burst size for GPMI channel 1. Do not change. GPMI only support burst size 4. + 2 + 2 + read-write + + + CH2 + DMA burst size for GPMI channel 2. Do not change. GPMI only support burst size 4. + 4 + 2 + read-write + + + CH3 + DMA burst size for GPMI channel 3. Do not change. GPMI only support burst size 4. + 6 + 2 + read-write + + + CH4 + DMA burst size for GPMI channel 4. Do not change. GPMI only support burst size 4. + 8 + 2 + read-write + + + CH5 + DMA burst size for GPMI channel 5. Do not change. GPMI only support burst size 4. + 10 + 2 + read-write + + + CH6 + DMA burst size for GPMI channel 6. Do not change. GPMI only support burst size 4. + 12 + 2 + read-write + + + CH7 + DMA burst size for GPMI channel 7. Do not change. GPMI only support burst size 4. + 14 + 2 + read-write + + + CH8 + DMA burst size for SSP. + 16 + 2 + read-write + + + BURST0 + BURST0 + 0 + + + BURST4 + BURST4 + 0x1 + + + BURST8 + BURST8 + 0x2 + + + + + + + DEBUG + AHB to APBH DMA Debug Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPMI_ONE_FIFO + Set to 0ne and the 8 GPMI channels will share the DMA FIFO, and when set to zero, the 8 GPMI channels will use its own DMA FIFO + 0 + 1 + read-write + + + + + 16 + 0x70 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CH%s_CURCMDAR + APBH DMA Channel n Current Command Address Register + 0x100 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMD_ADDR + Pointer to command structure currently being processed for channel n. + 0 + 32 + read-only + + + + + 16 + 0x70 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CH%s_NXTCMDAR + APBH DMA Channel n Next Command Address Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD_ADDR + Pointer to next command structure for channel n. + 0 + 32 + read-write + + + + + 16 + 0x70 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CH%s_CMD + APBH DMA Channel n Command Register + 0x120 + 32 + read-only + 0 + 0xFFFFFFFF + + + COMMAND + This bitfield indicates the type of current command: + 0 + 2 + read-only + + + NO_DMA_XFER + Perform any requested PIO word transfers but terminate command before any DMA transfer. + 0 + + + DMA_WRITE + Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + 0x1 + + + DMA_READ + Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + 0x2 + + + DMA_SENSE + Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. + 0x3 + + + + + CHAIN + A value of one indicates that another command is chained onto the end of the current command structure + 2 + 1 + read-only + + + IRQONCMPLT + A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i + 3 + 1 + read-only + + + NANDLOCK + A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels + 4 + 1 + read-only + + + NANDWAIT4READY + A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command + 5 + 1 + read-only + + + SEMAPHORE + A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure + 6 + 1 + read-only + + + WAIT4ENDCMD + A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command + 7 + 1 + read-only + + + HALTONTERMINATE + A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set + 8 + 1 + read-only + + + CMDWORDS + This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there + 12 + 4 + read-only + + + XFER_COUNT + This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device + 16 + 16 + read-only + + + + + 16 + 0x70 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CH%s_BAR + APBH DMA Channel n Buffer Address Register + 0x130 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDRESS + Address of system memory buffer to be read or written over the AHB bus. + 0 + 32 + read-only + + + + + 16 + 0x70 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CH%s_SEMA + APBH DMA Channel n Semaphore Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT_SEMA + The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + PHORE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + 16 + 0x70 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CH%s_DEBUG1 + AHB to APBH DMA Channel n Debug Information + 0x150 + 32 + read-only + 0xA00000 + 0xFFFFFFFF + + + STATEMACHINE + PIO Display of the DMA Channel n state machine state. + 0 + 5 + read-only + + + IDLE + This is the idle state of the DMA state machine. + 0 + + + REQ_CMD1 + State in which the DMA is waiting to receive the first word of a command. + 0x1 + + + REQ_CMD3 + State in which the DMA is waiting to receive the third word of a command. + 0x2 + + + REQ_CMD2 + State in which the DMA is waiting to receive the second word of a command. + 0x3 + + + XFER_DECODE + The state machine processes the descriptor command field in this state and branches accordingly. + 0x4 + + + REQ_WAIT + The state machine waits in this state for the PIO APB cycles to complete. + 0x5 + + + REQ_CMD4 + State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. + 0x6 + + + PIO_REQ + This state determines whether another PIO cycle needs to occur before starting DMA transfers. + 0x7 + + + READ_FLUSH + During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + 0x8 + + + READ_WAIT + When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + 0x9 + + + WRITE + During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + 0xC + + + READ_REQ + During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + 0xD + + + CHECK_CHAIN + Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + 0xE + + + XFER_COMPLETE + The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + 0xF + + + TERMINATE + When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + 0x14 + + + WAIT_END + When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + 0x15 + + + WRITE_WAIT + During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + 0x1C + + + HALT_AFTER_TERM + If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state + 0x1D + + + CHECK_WAIT + If the Chain bit is a 0, the state machine enters this state and effectively halts. + 0x1E + + + WAIT_READY + When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. + 0x1F + + + + + WR_FIFO_FULL + This bit reflects the current state of the DMA Channel's Write FIFO Full signal. + 20 + 1 + read-only + + + WR_FIFO_EMPTY + This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. + 21 + 1 + read-only + + + RD_FIFO_FULL + This bit reflects the current state of the DMA Channel's Read FIFO Full signal. + 22 + 1 + read-only + + + RD_FIFO_EMPTY + This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. + 23 + 1 + read-only + + + NEXTCMDADDRVALID + This bit reflects the internal bit which indicates whether the channel's next command address is valid + 24 + 1 + read-only + + + READY + This bit is reserved for this DMA Channel and always reads 0. + 26 + 1 + read-only + + + END + This bit reflects the current state of the DMA End Command Signal sent from the APB Device + 28 + 1 + read-only + + + KICK + This bit reflects the current state of the DMA Kick Signal sent to the APB Device + 29 + 1 + read-only + + + BURST + This bit reflects the current state of the DMA Burst Signal from the APB device + 30 + 1 + read-only + + + REQ + This bit reflects the current state of the DMA Request Signal from the APB device + 31 + 1 + read-only + + + + + 16 + 0x70 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CH%s_DEBUG2 + AHB to APBH DMA Channel n Debug Information + 0x160 + 32 + read-only + 0 + 0xFFFFFFFF + + + AHB_BYTES + This value reflects the current number of AHB bytes remaining to be transfered in the current transfer + 0 + 16 + read-only + + + APB_BYTES + This value reflects the current number of APB bytes remaining to be transfered in the current transfer + 16 + 16 + read-only + + + + + VERSION + APBH Bridge Version Register + 0x800 + 32 + read-only + 0x3010000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 24 + 8 + read-only + + + + + + + GPMI + GPMI + GPMI + GPMI_ + 0x33002000 + + 0 + 0x134 + registers + + + GPMI + 15 + + + + CTRL0 + GPMI Control Register 0 Description + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + Number of bytes to transfer for this command. A value of zero will transfer 64K bytes. + 0 + 16 + read-write + + + ADDRESS_INCREMENT + In ATA mode, the address will increment with each cycle + 16 + 1 + read-write + + + ADDRESS_INCREMENT_0 + Address does not increment. + 0 + + + ADDRESS_INCREMENT_1 + Increment address. + 0x1 + + + + + ADDRESS + Specifies the three address lines for ATA mode + 17 + 3 + read-write + + + CS + Selects which chip select is active for this command + 20 + 3 + read-write + + + WORD_LENGTH + This bit should only be changed when RUN==0 + 23 + 1 + read-write + + + WORD_LENGTH_1 + 8-bit Data Bus mode. + 0x1 + + + + + COMMAND_MODE + WRITE = 0x0 Write mode + 24 + 2 + read-write + + + COMMAND_MODE_0 + Write mode. + 0 + + + COMMAND_MODE_1 + Read Mode. + 0x1 + + + COMMAND_MODE_2 + Read and Compare Mode (setting sense flop). + 0x2 + + + COMMAND_MODE_3 + Wait for Ready. + 0x3 + + + + + UDMA + DISABLED = 0x0 Use ATA-PIO mode on the external bus + 26 + 1 + read-write + + + UDMA_0 + Use ATA-PIO mode on the external bus. + 0 + + + UDMA_1 + Use ATA-Ultra DMA mode on the external bus. + 0x1 + + + + + LOCK_CS + For ATA/NAND mode: 0= Deassert chip select (CS) after RUN is complete + 27 + 1 + read-write + + + DEV_IRQ_EN + When set to '1' and ATA_IRQ pin is asserted, the GPMI_IRQ output will assert. + 28 + 1 + read-write + + + RUN + The GPMI is busy running a command whenever this bit is set to '1' + 29 + 1 + read-write + + + CLKGATE + Set this bit zero for normal operation + 30 + 1 + read-write + + + SFTRST + Set to zero for normal operation + 31 + 1 + read-write + + + + + CTRL0_SET + GPMI Control Register 0 Description + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + Number of bytes to transfer for this command. A value of zero will transfer 64K bytes. + 0 + 16 + read-write + + + ADDRESS_INCREMENT + In ATA mode, the address will increment with each cycle + 16 + 1 + read-write + + + ADDRESS_INCREMENT_0 + Address does not increment. + 0 + + + ADDRESS_INCREMENT_1 + Increment address. + 0x1 + + + + + ADDRESS + Specifies the three address lines for ATA mode + 17 + 3 + read-write + + + CS + Selects which chip select is active for this command + 20 + 3 + read-write + + + WORD_LENGTH + This bit should only be changed when RUN==0 + 23 + 1 + read-write + + + WORD_LENGTH_1 + 8-bit Data Bus mode. + 0x1 + + + + + COMMAND_MODE + WRITE = 0x0 Write mode + 24 + 2 + read-write + + + COMMAND_MODE_0 + Write mode. + 0 + + + COMMAND_MODE_1 + Read Mode. + 0x1 + + + COMMAND_MODE_2 + Read and Compare Mode (setting sense flop). + 0x2 + + + COMMAND_MODE_3 + Wait for Ready. + 0x3 + + + + + UDMA + DISABLED = 0x0 Use ATA-PIO mode on the external bus + 26 + 1 + read-write + + + UDMA_0 + Use ATA-PIO mode on the external bus. + 0 + + + UDMA_1 + Use ATA-Ultra DMA mode on the external bus. + 0x1 + + + + + LOCK_CS + For ATA/NAND mode: 0= Deassert chip select (CS) after RUN is complete + 27 + 1 + read-write + + + DEV_IRQ_EN + When set to '1' and ATA_IRQ pin is asserted, the GPMI_IRQ output will assert. + 28 + 1 + read-write + + + RUN + The GPMI is busy running a command whenever this bit is set to '1' + 29 + 1 + read-write + + + CLKGATE + Set this bit zero for normal operation + 30 + 1 + read-write + + + SFTRST + Set to zero for normal operation + 31 + 1 + read-write + + + + + CTRL0_CLR + GPMI Control Register 0 Description + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + Number of bytes to transfer for this command. A value of zero will transfer 64K bytes. + 0 + 16 + read-write + + + ADDRESS_INCREMENT + In ATA mode, the address will increment with each cycle + 16 + 1 + read-write + + + ADDRESS_INCREMENT_0 + Address does not increment. + 0 + + + ADDRESS_INCREMENT_1 + Increment address. + 0x1 + + + + + ADDRESS + Specifies the three address lines for ATA mode + 17 + 3 + read-write + + + CS + Selects which chip select is active for this command + 20 + 3 + read-write + + + WORD_LENGTH + This bit should only be changed when RUN==0 + 23 + 1 + read-write + + + WORD_LENGTH_1 + 8-bit Data Bus mode. + 0x1 + + + + + COMMAND_MODE + WRITE = 0x0 Write mode + 24 + 2 + read-write + + + COMMAND_MODE_0 + Write mode. + 0 + + + COMMAND_MODE_1 + Read Mode. + 0x1 + + + COMMAND_MODE_2 + Read and Compare Mode (setting sense flop). + 0x2 + + + COMMAND_MODE_3 + Wait for Ready. + 0x3 + + + + + UDMA + DISABLED = 0x0 Use ATA-PIO mode on the external bus + 26 + 1 + read-write + + + UDMA_0 + Use ATA-PIO mode on the external bus. + 0 + + + UDMA_1 + Use ATA-Ultra DMA mode on the external bus. + 0x1 + + + + + LOCK_CS + For ATA/NAND mode: 0= Deassert chip select (CS) after RUN is complete + 27 + 1 + read-write + + + DEV_IRQ_EN + When set to '1' and ATA_IRQ pin is asserted, the GPMI_IRQ output will assert. + 28 + 1 + read-write + + + RUN + The GPMI is busy running a command whenever this bit is set to '1' + 29 + 1 + read-write + + + CLKGATE + Set this bit zero for normal operation + 30 + 1 + read-write + + + SFTRST + Set to zero for normal operation + 31 + 1 + read-write + + + + + CTRL0_TOG + GPMI Control Register 0 Description + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + Number of bytes to transfer for this command. A value of zero will transfer 64K bytes. + 0 + 16 + read-write + + + ADDRESS_INCREMENT + In ATA mode, the address will increment with each cycle + 16 + 1 + read-write + + + ADDRESS_INCREMENT_0 + Address does not increment. + 0 + + + ADDRESS_INCREMENT_1 + Increment address. + 0x1 + + + + + ADDRESS + Specifies the three address lines for ATA mode + 17 + 3 + read-write + + + CS + Selects which chip select is active for this command + 20 + 3 + read-write + + + WORD_LENGTH + This bit should only be changed when RUN==0 + 23 + 1 + read-write + + + WORD_LENGTH_1 + 8-bit Data Bus mode. + 0x1 + + + + + COMMAND_MODE + WRITE = 0x0 Write mode + 24 + 2 + read-write + + + COMMAND_MODE_0 + Write mode. + 0 + + + COMMAND_MODE_1 + Read Mode. + 0x1 + + + COMMAND_MODE_2 + Read and Compare Mode (setting sense flop). + 0x2 + + + COMMAND_MODE_3 + Wait for Ready. + 0x3 + + + + + UDMA + DISABLED = 0x0 Use ATA-PIO mode on the external bus + 26 + 1 + read-write + + + UDMA_0 + Use ATA-PIO mode on the external bus. + 0 + + + UDMA_1 + Use ATA-Ultra DMA mode on the external bus. + 0x1 + + + + + LOCK_CS + For ATA/NAND mode: 0= Deassert chip select (CS) after RUN is complete + 27 + 1 + read-write + + + DEV_IRQ_EN + When set to '1' and ATA_IRQ pin is asserted, the GPMI_IRQ output will assert. + 28 + 1 + read-write + + + RUN + The GPMI is busy running a command whenever this bit is set to '1' + 29 + 1 + read-write + + + CLKGATE + Set this bit zero for normal operation + 30 + 1 + read-write + + + SFTRST + Set to zero for normal operation + 31 + 1 + read-write + + + + + COMPARE + GPMI Compare Register Description + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + REFERENCE + 16-bit value which is XORed with data read from the NAND device. + 0 + 16 + read-write + + + MASK + 16-bit mask which is applied after the read data is XORed with the REFERENCE bit field. + 16 + 16 + read-write + + + + + ECCCTRL + GPMI Integrated ECC Control Register Description + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + ECC buffer information + 0 + 9 + read-write + + + RANDOMIZER_TYPE + Set randomizer type + 9 + 2 + read-write + + + RANDOMIZER_TYPE_0 + Type 0 + 0 + + + RANDOMIZER_TYPE_1 + Type 1 + 0x1 + + + + + RANDOMIZER_ENABLE + Enable randomizer function. If this bit is set to enable, ENABLE_ECC should be also enable. + 11 + 1 + read-write + + + RANDOMIZER_ENABLE_0 + disable + 0 + + + RANDOMIZER_ENABLE_1 + enable + 0x1 + + + + + ENABLE_ECC + Enable ECC processing of GPMI transfers + 12 + 1 + read-write + + + ECC_CMD + ECC Command information + 13 + 2 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 15 + 1 + read-write + + + HANDLE + This is a register available to software to attach an identifier to a transaction in progress + 16 + 16 + read-write + + + + + ECCCTRL_SET + GPMI Integrated ECC Control Register Description + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + ECC buffer information + 0 + 9 + read-write + + + RANDOMIZER_TYPE + Set randomizer type + 9 + 2 + read-write + + + RANDOMIZER_TYPE_0 + Type 0 + 0 + + + RANDOMIZER_TYPE_1 + Type 1 + 0x1 + + + + + RANDOMIZER_ENABLE + Enable randomizer function. If this bit is set to enable, ENABLE_ECC should be also enable. + 11 + 1 + read-write + + + RANDOMIZER_ENABLE_0 + disable + 0 + + + RANDOMIZER_ENABLE_1 + enable + 0x1 + + + + + ENABLE_ECC + Enable ECC processing of GPMI transfers + 12 + 1 + read-write + + + ECC_CMD + ECC Command information + 13 + 2 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 15 + 1 + read-write + + + HANDLE + This is a register available to software to attach an identifier to a transaction in progress + 16 + 16 + read-write + + + + + ECCCTRL_CLR + GPMI Integrated ECC Control Register Description + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + ECC buffer information + 0 + 9 + read-write + + + RANDOMIZER_TYPE + Set randomizer type + 9 + 2 + read-write + + + RANDOMIZER_TYPE_0 + Type 0 + 0 + + + RANDOMIZER_TYPE_1 + Type 1 + 0x1 + + + + + RANDOMIZER_ENABLE + Enable randomizer function. If this bit is set to enable, ENABLE_ECC should be also enable. + 11 + 1 + read-write + + + RANDOMIZER_ENABLE_0 + disable + 0 + + + RANDOMIZER_ENABLE_1 + enable + 0x1 + + + + + ENABLE_ECC + Enable ECC processing of GPMI transfers + 12 + 1 + read-write + + + ECC_CMD + ECC Command information + 13 + 2 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 15 + 1 + read-write + + + HANDLE + This is a register available to software to attach an identifier to a transaction in progress + 16 + 16 + read-write + + + + + ECCCTRL_TOG + GPMI Integrated ECC Control Register Description + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + ECC buffer information + 0 + 9 + read-write + + + RANDOMIZER_TYPE + Set randomizer type + 9 + 2 + read-write + + + RANDOMIZER_TYPE_0 + Type 0 + 0 + + + RANDOMIZER_TYPE_1 + Type 1 + 0x1 + + + + + RANDOMIZER_ENABLE + Enable randomizer function. If this bit is set to enable, ENABLE_ECC should be also enable. + 11 + 1 + read-write + + + RANDOMIZER_ENABLE_0 + disable + 0 + + + RANDOMIZER_ENABLE_1 + enable + 0x1 + + + + + ENABLE_ECC + Enable ECC processing of GPMI transfers + 12 + 1 + read-write + + + ECC_CMD + ECC Command information + 13 + 2 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 15 + 1 + read-write + + + HANDLE + This is a register available to software to attach an identifier to a transaction in progress + 16 + 16 + read-write + + + + + ECCCOUNT + GPMI Integrated ECC Transfer Count Register Description + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + COUNT + Number of bytes to pass through ECC + 0 + 16 + read-write + + + RANDOMIZER_PAGE + Set NAND page number needed to be randomized. The value is between 0-255 + 16 + 8 + read-write + + + + + PAYLOAD + GPMI Payload Address Register Description + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Always write zeroes to this bit field. + 0 + 2 + read-only + + + ADDRESS + Pointer to an array of one or more 512 byte payload buffers. + 2 + 30 + read-write + + + + + AUXILIARY + GPMI Auxiliary Address Register Description + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Always write zeroes to this bit field. + 0 + 2 + read-only + + + ADDRESS + Pointer to ECC control structure and meta-data storage. + 2 + 30 + read-write + + + + + CTRL1 + GPMI Control Register 1 Description + 0x60 + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + ATA mode is only supported on channel zero + 0 + 1 + read-write + + + GPMI_MODE_0 + NAND mode. + 0 + + + GPMI_MODE_1 + ATA mode. + 0x1 + + + + + CAMERA_MODE + When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface. + 1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit + 2 + 1 + read-write + + + ATA_IRQRDY_POLARITY_0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + 0 + + + ATA_IRQRDY_POLARITY_1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + 0x1 + + + + + DEV_RESET + ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted) + 3 + 1 + read-write + + + DEV_RESET_0 + NANDF_WP_B pin is held low (asserted). + 0 + + + DEV_RESET_1 + NANDF_WP_B pin is held high (de-asserted). + 0x1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + Abort a wait for ready command on selected channel + 4 + 3 + read-write + + + ABORT_WAIT_REQUEST + Request to abort "wait for ready" command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL + 7 + 1 + read-write + + + BURST_EN + When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. + 8 + 1 + read-write + + + TIMEOUT_IRQ + This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. + 9 + 1 + read-write + + + DEV_IRQ + This bit is set when an Interrupt is received from the ATA device. Write 0 to clear. + 10 + 1 + read-write + + + DMA2ECC_MODE + This is mainly for testing HWECC without involving the Nand device + 11 + 1 + read-write + + + RDN_DELAY + This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling + 12 + 4 + read-write + + + HALF_PERIOD + Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation + 16 + 1 + read-write + + + DLL_ENABLE + Set this bit to 1 to enable the GPMI DLL + 17 + 1 + read-write + + + BCH_MODE + This bit selects which error correction unit will access GPMI + 18 + 1 + read-write + + + GANGED_RDYBUSY + Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0 + 19 + 1 + read-write + + + TIMEOUT_IRQ_EN + Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only, and for WAIT_FOR_READY commands in both ATA and Nand mode + 20 + 1 + read-write + + + TEST_TRIGGER + Test Trigger Enable + 21 + 1 + read-write + + + TEST_TRIGGER_0 + Disable + 0 + + + TEST_TRIGGER_1 + Enable + 0x1 + + + + + WRN_DLY_SEL + Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match the load on this pin + 22 + 2 + read-write + + + DECOUPLE_CS + Decouple Chip Select from DMA Channel + 24 + 1 + read-write + + + SSYNCMODE + source synchronouse mode 1 or asynchrous mode 0 + 25 + 1 + read-write + + + UPDATE_CS + force the CS value is be updated to external chip select pin, even GPMI is idle. + 26 + 1 + read-write + + + GPMI_CLK_DIV2_EN + This bit should be reset to 0 in asynchronous mode + 27 + 1 + read-write + + + GPMI_CLK_DIV2_EN_0 + internal factor-2 clock divider is disabled + 0 + + + GPMI_CLK_DIV2_EN_1 + internal factor-2 clock divider is enabled. + 0x1 + + + + + TOGGLE_MODE + enable samsung toggle mode. + 28 + 1 + read-write + + + WRITE_CLK_STOP + In onfi source synchronous mode, host may save power during the data write cycles by holding the CLK signal high (i + 29 + 1 + read-write + + + SSYNC_CLK_STOP + set this bit to 1 will stop the source synchronous mode clk. + 30 + 1 + read-write + + + DEV_CLK_STOP + set this bit to 1 will stop gpmi io working clk. + 31 + 1 + read-write + + + + + CTRL1_SET + GPMI Control Register 1 Description + 0x64 + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + ATA mode is only supported on channel zero + 0 + 1 + read-write + + + GPMI_MODE_0 + NAND mode. + 0 + + + GPMI_MODE_1 + ATA mode. + 0x1 + + + + + CAMERA_MODE + When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface. + 1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit + 2 + 1 + read-write + + + ATA_IRQRDY_POLARITY_0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + 0 + + + ATA_IRQRDY_POLARITY_1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + 0x1 + + + + + DEV_RESET + ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted) + 3 + 1 + read-write + + + DEV_RESET_0 + NANDF_WP_B pin is held low (asserted). + 0 + + + DEV_RESET_1 + NANDF_WP_B pin is held high (de-asserted). + 0x1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + Abort a wait for ready command on selected channel + 4 + 3 + read-write + + + ABORT_WAIT_REQUEST + Request to abort "wait for ready" command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL + 7 + 1 + read-write + + + BURST_EN + When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. + 8 + 1 + read-write + + + TIMEOUT_IRQ + This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. + 9 + 1 + read-write + + + DEV_IRQ + This bit is set when an Interrupt is received from the ATA device. Write 0 to clear. + 10 + 1 + read-write + + + DMA2ECC_MODE + This is mainly for testing HWECC without involving the Nand device + 11 + 1 + read-write + + + RDN_DELAY + This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling + 12 + 4 + read-write + + + HALF_PERIOD + Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation + 16 + 1 + read-write + + + DLL_ENABLE + Set this bit to 1 to enable the GPMI DLL + 17 + 1 + read-write + + + BCH_MODE + This bit selects which error correction unit will access GPMI + 18 + 1 + read-write + + + GANGED_RDYBUSY + Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0 + 19 + 1 + read-write + + + TIMEOUT_IRQ_EN + Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only, and for WAIT_FOR_READY commands in both ATA and Nand mode + 20 + 1 + read-write + + + TEST_TRIGGER + Test Trigger Enable + 21 + 1 + read-write + + + TEST_TRIGGER_0 + Disable + 0 + + + TEST_TRIGGER_1 + Enable + 0x1 + + + + + WRN_DLY_SEL + Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match the load on this pin + 22 + 2 + read-write + + + DECOUPLE_CS + Decouple Chip Select from DMA Channel + 24 + 1 + read-write + + + SSYNCMODE + source synchronouse mode 1 or asynchrous mode 0 + 25 + 1 + read-write + + + UPDATE_CS + force the CS value is be updated to external chip select pin, even GPMI is idle. + 26 + 1 + read-write + + + GPMI_CLK_DIV2_EN + This bit should be reset to 0 in asynchronous mode + 27 + 1 + read-write + + + GPMI_CLK_DIV2_EN_0 + internal factor-2 clock divider is disabled + 0 + + + GPMI_CLK_DIV2_EN_1 + internal factor-2 clock divider is enabled. + 0x1 + + + + + TOGGLE_MODE + enable samsung toggle mode. + 28 + 1 + read-write + + + WRITE_CLK_STOP + In onfi source synchronous mode, host may save power during the data write cycles by holding the CLK signal high (i + 29 + 1 + read-write + + + SSYNC_CLK_STOP + set this bit to 1 will stop the source synchronous mode clk. + 30 + 1 + read-write + + + DEV_CLK_STOP + set this bit to 1 will stop gpmi io working clk. + 31 + 1 + read-write + + + + + CTRL1_CLR + GPMI Control Register 1 Description + 0x68 + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + ATA mode is only supported on channel zero + 0 + 1 + read-write + + + GPMI_MODE_0 + NAND mode. + 0 + + + GPMI_MODE_1 + ATA mode. + 0x1 + + + + + CAMERA_MODE + When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface. + 1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit + 2 + 1 + read-write + + + ATA_IRQRDY_POLARITY_0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + 0 + + + ATA_IRQRDY_POLARITY_1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + 0x1 + + + + + DEV_RESET + ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted) + 3 + 1 + read-write + + + DEV_RESET_0 + NANDF_WP_B pin is held low (asserted). + 0 + + + DEV_RESET_1 + NANDF_WP_B pin is held high (de-asserted). + 0x1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + Abort a wait for ready command on selected channel + 4 + 3 + read-write + + + ABORT_WAIT_REQUEST + Request to abort "wait for ready" command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL + 7 + 1 + read-write + + + BURST_EN + When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. + 8 + 1 + read-write + + + TIMEOUT_IRQ + This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. + 9 + 1 + read-write + + + DEV_IRQ + This bit is set when an Interrupt is received from the ATA device. Write 0 to clear. + 10 + 1 + read-write + + + DMA2ECC_MODE + This is mainly for testing HWECC without involving the Nand device + 11 + 1 + read-write + + + RDN_DELAY + This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling + 12 + 4 + read-write + + + HALF_PERIOD + Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation + 16 + 1 + read-write + + + DLL_ENABLE + Set this bit to 1 to enable the GPMI DLL + 17 + 1 + read-write + + + BCH_MODE + This bit selects which error correction unit will access GPMI + 18 + 1 + read-write + + + GANGED_RDYBUSY + Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0 + 19 + 1 + read-write + + + TIMEOUT_IRQ_EN + Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only, and for WAIT_FOR_READY commands in both ATA and Nand mode + 20 + 1 + read-write + + + TEST_TRIGGER + Test Trigger Enable + 21 + 1 + read-write + + + TEST_TRIGGER_0 + Disable + 0 + + + TEST_TRIGGER_1 + Enable + 0x1 + + + + + WRN_DLY_SEL + Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match the load on this pin + 22 + 2 + read-write + + + DECOUPLE_CS + Decouple Chip Select from DMA Channel + 24 + 1 + read-write + + + SSYNCMODE + source synchronouse mode 1 or asynchrous mode 0 + 25 + 1 + read-write + + + UPDATE_CS + force the CS value is be updated to external chip select pin, even GPMI is idle. + 26 + 1 + read-write + + + GPMI_CLK_DIV2_EN + This bit should be reset to 0 in asynchronous mode + 27 + 1 + read-write + + + GPMI_CLK_DIV2_EN_0 + internal factor-2 clock divider is disabled + 0 + + + GPMI_CLK_DIV2_EN_1 + internal factor-2 clock divider is enabled. + 0x1 + + + + + TOGGLE_MODE + enable samsung toggle mode. + 28 + 1 + read-write + + + WRITE_CLK_STOP + In onfi source synchronous mode, host may save power during the data write cycles by holding the CLK signal high (i + 29 + 1 + read-write + + + SSYNC_CLK_STOP + set this bit to 1 will stop the source synchronous mode clk. + 30 + 1 + read-write + + + DEV_CLK_STOP + set this bit to 1 will stop gpmi io working clk. + 31 + 1 + read-write + + + + + CTRL1_TOG + GPMI Control Register 1 Description + 0x6C + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + ATA mode is only supported on channel zero + 0 + 1 + read-write + + + GPMI_MODE_0 + NAND mode. + 0 + + + GPMI_MODE_1 + ATA mode. + 0x1 + + + + + CAMERA_MODE + When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface. + 1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit + 2 + 1 + read-write + + + ATA_IRQRDY_POLARITY_0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + 0 + + + ATA_IRQRDY_POLARITY_1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + 0x1 + + + + + DEV_RESET + ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted) + 3 + 1 + read-write + + + DEV_RESET_0 + NANDF_WP_B pin is held low (asserted). + 0 + + + DEV_RESET_1 + NANDF_WP_B pin is held high (de-asserted). + 0x1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + Abort a wait for ready command on selected channel + 4 + 3 + read-write + + + ABORT_WAIT_REQUEST + Request to abort "wait for ready" command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL + 7 + 1 + read-write + + + BURST_EN + When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. + 8 + 1 + read-write + + + TIMEOUT_IRQ + This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. + 9 + 1 + read-write + + + DEV_IRQ + This bit is set when an Interrupt is received from the ATA device. Write 0 to clear. + 10 + 1 + read-write + + + DMA2ECC_MODE + This is mainly for testing HWECC without involving the Nand device + 11 + 1 + read-write + + + RDN_DELAY + This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling + 12 + 4 + read-write + + + HALF_PERIOD + Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation + 16 + 1 + read-write + + + DLL_ENABLE + Set this bit to 1 to enable the GPMI DLL + 17 + 1 + read-write + + + BCH_MODE + This bit selects which error correction unit will access GPMI + 18 + 1 + read-write + + + GANGED_RDYBUSY + Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0 + 19 + 1 + read-write + + + TIMEOUT_IRQ_EN + Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only, and for WAIT_FOR_READY commands in both ATA and Nand mode + 20 + 1 + read-write + + + TEST_TRIGGER + Test Trigger Enable + 21 + 1 + read-write + + + TEST_TRIGGER_0 + Disable + 0 + + + TEST_TRIGGER_1 + Enable + 0x1 + + + + + WRN_DLY_SEL + Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match the load on this pin + 22 + 2 + read-write + + + DECOUPLE_CS + Decouple Chip Select from DMA Channel + 24 + 1 + read-write + + + SSYNCMODE + source synchronouse mode 1 or asynchrous mode 0 + 25 + 1 + read-write + + + UPDATE_CS + force the CS value is be updated to external chip select pin, even GPMI is idle. + 26 + 1 + read-write + + + GPMI_CLK_DIV2_EN + This bit should be reset to 0 in asynchronous mode + 27 + 1 + read-write + + + GPMI_CLK_DIV2_EN_0 + internal factor-2 clock divider is disabled + 0 + + + GPMI_CLK_DIV2_EN_1 + internal factor-2 clock divider is enabled. + 0x1 + + + + + TOGGLE_MODE + enable samsung toggle mode. + 28 + 1 + read-write + + + WRITE_CLK_STOP + In onfi source synchronous mode, host may save power during the data write cycles by holding the CLK signal high (i + 29 + 1 + read-write + + + SSYNC_CLK_STOP + set this bit to 1 will stop the source synchronous mode clk. + 30 + 1 + read-write + + + DEV_CLK_STOP + set this bit to 1 will stop gpmi io working clk. + 31 + 1 + read-write + + + + + TIMING0 + GPMI Timing Register 0 Description + 0x70 + 32 + read-write + 0x10203 + 0xFFFFFFFF + + + DATA_SETUP + Data bus setup time in GPMICLK cycles + 0 + 8 + read-write + + + DATA_HOLD + Data bus hold time in GPMICLK cycles + 8 + 8 + read-write + + + ADDRESS_SETUP + Number of GPMICLK cycles that the CE/ADDR signals are active before a strobe is asserted + 16 + 8 + read-write + + + RSVD1 + Always write zeroes to this bit field. + 24 + 8 + write-only + + + + + TIMING1 + GPMI Timing Register 1 Description + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD1 + Always write zeroes to this bit field. + 0 + 16 + read-only + + + DEVICE_BUSY_TIMEOUT + Timeout waiting for NAND Ready/Busy or ATA IRQ + 16 + 16 + read-write + + + + + TIMING2 + GPMI Timing Register 2 Description + 0x90 + 32 + read-write + 0x3023336 + 0xFFFFFFFF + + + DATA_PAUSE + GPMI delay time from data pause to data resume in GPMICLK cycles + 0 + 4 + read-write + + + CMDADD_PAUSE + GPMI delay time from command or addres pause to command or address resume in GPMICLK cycles + 4 + 4 + read-write + + + POSTAMBLE_DELAY + GPMI post-amble delay in GPMICLK cycles. A value of zero is interpreted as 16. + 8 + 4 + read-write + + + PREAMBLE_DELAY + GPMI pre-amble delay in GPMICLK cycles. A value of zero is interpreted as 16. + 12 + 4 + read-write + + + CE_DELAY + GPMI dealy from CEn assert to W/Rn changing edge. value of zero is interpreted as 32. + 16 + 5 + read-write + + + RSVD0 + Always write zeroes to this bit field. + 21 + 3 + read-only + + + READ_LATENCY + This field is for double data rate read latency configuration. others READ LATENCY is 3 + 24 + 3 + read-write + + + READ_LATENCY_0 + READ LATENCY is 0 + 0 + + + READ_LATENCY_1 + READ LATENCY is 1 + 0x1 + + + READ_LATENCY_2 + READ LATENCY is 2 + 0x2 + + + READ_LATENCY_3 + READ LATENCY is 3 + 0x3 + + + READ_LATENCY_4 + READ LATENCY is 4 + 0x4 + + + READ_LATENCY_5 + READ LATENCY is 5 + 0x5 + + + + + TCR + Only for Toggle NAND timing control delay (TCR+1) GPMICLK cycles for CEn_B low to RE_B low, 0 is less than or equal to TCR, which is less than the PREAMBLE_DELAY + 27 + 2 + read-write + + + TRPSTH + Only for Toggle NAND timing control delay TRPSTH GPMICLK cycles for CEn_B high to RE_B high, A value of zero is interpreted as 8 + 29 + 3 + read-write + + + + + DATA + GPMI DMA Data Transfer Register Description + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + In 8-bit mode, one, two, three or four bytes can can be accessed to send the same number of bus cycles + 0 + 32 + read-write + + + + + STAT + GPMI Status Register Description + 0xB0 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + PRESENT + UNAVAILABLE = 0x0 GPMI is not present in this product + 0 + 1 + read-only + + + PRESENT_0 + GPMI is not present in this product. + 0 + + + PRESENT_1 + GPMI is present is in this product. + 0x1 + + + + + FIFO_FULL + NOT_FULL = 0x0 FIFO is not full. FULL = 0x1 FIFO is full. + 1 + 1 + read-only + + + FIFO_FULL_0 + FIFO is not full. + 0 + + + FIFO_FULL_1 + FIFO is full. + 0x1 + + + + + FIFO_EMPTY + NOT_EMPTY = 0x0 FIFO is not empty. EMPTY = 0x1 FIFO is empty. + 2 + 1 + read-only + + + FIFO_EMPTY_0 + FIFO is not empty. + 0 + + + FIFO_EMPTY_1 + FIFO is empty. + 0x1 + + + + + INVALID_BUFFER_MASK + Buffer Mask Validity bit. + 3 + 1 + read-only + + + INVALID_BUFFER_MASK_0 + ECC Buffer Mask is not invalid. + 0 + + + INVALID_BUFFER_MASK_1 + ECC Buffer Mask is invalid. + 0x1 + + + + + ATA_IRQ + Status of the ATA_IRQ input pin. + 4 + 1 + read-only + + + RSVD1 + Always write zeroes to this bit field. + 5 + 3 + read-only + + + DEV0_ERROR + DMA channel 0 (Timeout or compare failure, depending on COMMAND_MODE). + 8 + 1 + read-only + + + DEV0_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 0. + 0 + + + DEV0_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV1_ERROR + DMA channel 1 (Timeout or compare failure, depending on COMMAND_MODE). + 9 + 1 + read-only + + + DEV1_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 1. + 0 + + + DEV1_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV2_ERROR + DMA channel 2 (Timeout or compare failure, depending on COMMAND_MODE). + 10 + 1 + read-only + + + DEV2_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 2. + 0 + + + DEV2_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV3_ERROR + DMA channel 3 (Timeout or compare failure, depending on COMMAND_MODE). + 11 + 1 + read-only + + + DEV3_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 3. + 0 + + + DEV3_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV4_ERROR + DMA channel 4 (Timeout or compare failure, depending on COMMAND_MODE). + 12 + 1 + read-only + + + DEV4_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 4. + 0 + + + DEV4_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV5_ERROR + DMA channel 5 (Timeout or compare failure, depending on COMMAND_MODE). + 13 + 1 + read-only + + + DEV5_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 5. + 0 + + + DEV5_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV6_ERROR + DMA channel 6 (Timeout or compare failure, depending on COMMAND_MODE). + 14 + 1 + read-only + + + DEV6_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 6. + 0 + + + DEV6_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV7_ERROR + DMA channel 7 (Timeout or compare failure, depending on COMMAND_MODE). + 15 + 1 + read-only + + + DEV7_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 7. + 0 + + + DEV7_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + RDY_TIMEOUT + State of the RDY/BUSY Timeout Flags + 16 + 8 + read-only + + + READY_BUSY + Read-only view of NAND Ready_Busy Input pins. + 24 + 8 + read-only + + + + + DEBUG + GPMI Debug Information Register Description + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMD_END + Read Only view of the Command End toggle signals to DMA. One per channel + 0 + 8 + read-only + + + DMAREQ + Read-only view of DMA request line for 8 DMA channels + 8 + 8 + read-only + + + DMA_SENSE + Read-only view of sense state of the 8 DMA channels + 16 + 8 + read-only + + + WAIT_FOR_READY_END + Read Only view of the Wait_For_Ready End toggle signals to DMA. One per channel + 24 + 8 + read-only + + + + + VERSION + GPMI Version Register Description + 0xD0 + 32 + read-only + 0x5020000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 24 + 8 + read-only + + + + + DEBUG2 + GPMI Debug2 Information Register Description + 0xE0 + 32 + read-write + 0xF100 + 0xFFFFFFFF + + + RDN_TAP + This is the DLL tap calculated by the DLL controller + 0 + 6 + read-only + + + UPDATE_WINDOW + A 1 indicates that the DLL is busy generating the required delay. + 6 + 1 + read-only + + + VIEW_DELAYED_RDN + Set to a 1 to select the delayed feedback RE_B to drive the GPMI_ADDR[0] (Nand CLE) pin + 7 + 1 + read-write + + + SYND2GPMI_READY + Data handshake Input from BCH. + 8 + 1 + read-only + + + SYND2GPMI_VALID + Data handshake Input from BCH. + 9 + 1 + read-only + + + GPMI2SYND_READY + Data handshake output to BCH. + 10 + 1 + read-only + + + GPMI2SYND_VALID + Data handshake output to BCH. + 11 + 1 + read-only + + + SYND2GPMI_BE + Data byte enable Input from BCH. + 12 + 4 + read-only + + + MAIN_STATE + parameter MSM_IDLE = 4'h0, MSM_BYTCNT = 4'h1, MSM_WAITFE = 4'h2, MSM_WAITFR = 4'h3, MSM_DMAREQ = 4'h4, MSM_DMAACK = 4'h5, MSM_WAITFF = 4'h6, MSM_LDFIFO = 4'h7, MSM_LDDMAR = 4'h8, MSM_RDCMP = 4'h9, MSM_DONE = 4'hA + 16 + 4 + read-only + + + PIN_STATE + parameter PSM_IDLE = 3'h0, PSM_BYTCNT = 3'h1, PSM_ADDR = 3'h2, PSM_STALL = 3'h3, PSM_STROBE = 3'h4, PSM_ATARDY = 3'h5, PSM_DHOLD = 3'h6, PSM_DONE = 3'h7 + 20 + 3 + read-only + + + BUSY + When asserted the GPMI is busy + 23 + 1 + read-only + + + UDMA_STATE + USM_IDLE = 4'h0, idle USM_DMARQ = 4'h1, DMA req USM_ACK = 4'h2, DMA ACK USM_FIFO_E = 4'h3, Fifo empty USM_WPAUSE = 4'h4, WR DMA Paused by device USM_TSTRB = 4'h5, Toggle HSTROBE USM_CAPTUR = 4'h6, Capture Stage, (data sampled with DSTROBE is valid) USM_DATOUT = 4'h7, Change Burst DATAOUT USM_CRC = 4'h8, Source CRC to Device USM_WAIT_R = 4'h9, Waiting for DDMARDY- USM_END = 4'ha; Negate DMAACK (end of DMA) USM_WAIT_S = 4'hb, Waiting for DSTROBE USM_RPAUSE = 4'hc, Rd DMA Paused by Host USM_RSTOP = 4'hd, Rd DMA Stopped by Host USM_WTERM = 4'he, Wr DMA Termination State USM_RTERM = 4'hf, Rd DMA Termination state + 24 + 4 + read-only + + + RSVD1 + Always write zeroes to this bit field. + 28 + 4 + read-write + + + + + DEBUG3 + GPMI Debug3 Information Register Description + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEV_WORD_CNTR + Reflects the number of bytes remains to be transferred on the ATA/Nand bus. + 0 + 16 + read-only + + + APB_WORD_CNTR + Reflects the number of bytes remains to be transferred on the APB bus. + 16 + 16 + read-only + + + + + READ_DDR_DLL_CTRL + GPMI Double Rate Read DLL Control Register Description + 0x100 + 32 + read-write + 0x38 + 0xFFFFFFFF + + + ENABLE + Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL + 0 + 1 + read-write + + + RESET + Setting this bit to 1 force a reset on DLL + 1 + 1 + read-write + + + SLV_FORCE_UPD + Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately + 2 + 1 + read-write + + + SLV_DLY_TARGET + The delay target for the read clock is can be programmed in 1/16th increments of an GPMICLK half-period + 3 + 4 + read-write + + + GATE_UPDATE + Setting this bit to 1, forces the slave delay line not update + 7 + 1 + read-write + + + REFCLK_ON + set this bit to 1 will turn on the reference clock + 8 + 1 + read-write + + + SLV_OVERRIDE + Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to disable manual override + 9 + 1 + read-write + + + SLV_OVERRIDE_VAL + When SLV_OVERRIDE=1 This field is used to select 1 of 256 physical taps manually + 10 + 8 + read-write + + + RSVD1 + Reserved + 18 + 2 + read-only + + + SLV_UPDATE_INT + Setting a value greater than 0 in this field, shall over-ride the default slave delay-line update interval of 256 GPMICLK cycles + 20 + 8 + read-write + + + REF_UPDATE_INT + This field allows the user to add additional delay cycles to the DLL control loop (reference delay line control) + 28 + 4 + read-write + + + + + WRITE_DDR_DLL_CTRL + GPMI Double Rate Write DLL Control Register Description + 0x110 + 32 + read-write + 0x38 + 0xFFFFFFFF + + + ENABLE + Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL + 0 + 1 + read-write + + + RESET + Setting this bit to 1 force a reset on DLL + 1 + 1 + read-write + + + SLV_FORCE_UPD + Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately + 2 + 1 + read-write + + + SLV_DLY_TARGET + The delay target for the read clock can be programmed in 1/16th increments of an GPMICLK half-period + 3 + 4 + read-write + + + GATE_UPDATE + Setting this bit to 1, forces the slave delay line not update + 7 + 1 + read-write + + + REFCLK_ON + set this bit to 1 will turn on the reference clock + 8 + 1 + read-write + + + SLV_OVERRIDE + Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to disable manual override + 9 + 1 + read-write + + + SLV_OVERRIDE_VAL + When SLV_OVERRIDE=1 This field is used to select 1 of 256 physical taps manually + 10 + 8 + read-write + + + RSVD1 + Reserved + 18 + 2 + read-only + + + SLV_UPDATE_INT + Setting a value greater than 0 in this field, shall over-ride the default slave delay-line update interval of 256 GPMICLK cycles + 20 + 8 + read-write + + + REF_UPDATE_INT + This field allows the user to add additional delay cycles to the DLL control loop (reference delay line control) + 28 + 4 + read-write + + + + + READ_DDR_DLL_STS + GPMI Double Rate Read DLL Status Register Description + 0x120 + 32 + read-only + 0 + 0xFFFFFFFF + + + SLV_LOCK + Slave delay-line lock status + 0 + 1 + read-only + + + SLV_SEL + Slave delay line select status + 1 + 8 + read-only + + + RSVD0 + Reserved + 9 + 7 + read-only + + + REF_LOCK + Reference DLL lock status + 16 + 1 + read-only + + + REF_SEL + Reference delay line select status. + 17 + 8 + read-only + + + RSVD1 + Reserved + 25 + 7 + read-only + + + + + WRITE_DDR_DLL_STS + GPMI Double Rate Write DLL Status Register Description + 0x130 + 32 + read-only + 0 + 0xFFFFFFFF + + + SLV_LOCK + Slave delay-line lock status + 0 + 1 + read-only + + + SLV_SEL + Slave delay line select status + 1 + 8 + read-only + + + RSVD0 + Reserved + 9 + 7 + read-only + + + REF_LOCK + Reference DLL lock status + 16 + 1 + read-only + + + REF_SEL + Reference delay line select status. + 17 + 8 + read-only + + + RSVD1 + Reserved + 25 + 7 + read-only + + + + + + + BCH + BCH Register Reference Index + BCH + BCH_ + 0x33004000 + + 0 + 0x180 + registers + + + BCH + 14 + + + + CTRL + Hardware BCH ECC Accelerator Control Register + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + COMPLETE_IRQ + This bit indicates the state of the external interrupt line + 0 + 1 + read-write + + + RSVD0 + This field is reserved. + 1 + 1 + read-only + + + DEBUG_STALL_IRQ + DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. + 2 + 1 + read-write + + + BM_ERROR_IRQ + AHB Bus interface Error Interrupt Status + 3 + 1 + read-write + + + RSVD1 + This field is reserved. + 4 + 4 + read-only + + + COMPLETE_IRQ_EN + 1 = interrupt on completion of correction is enabled. + 8 + 1 + read-write + + + RSVD2 + This field is reserved. + 9 + 1 + read-only + + + DEBUG_STALL_IRQ_EN + 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block + 10 + 1 + read-write + + + RSVD3 + This field is reserved. + 11 + 5 + read-only + + + M2M_ENABLE + NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION + 16 + 1 + read-write + + + M2M_ENCODE + Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. + 17 + 1 + read-write + + + M2M_LAYOUT + Selects the flash page format for memory-to-memory operations. + 18 + 2 + read-write + + + RSVD4 + This field is reserved. + 20 + 2 + read-only + + + DEBUGSYNDROME + (For debug purposes only) + 22 + 1 + read-write + + + RSVD5 + This field is reserved. + 23 + 7 + read-only + + + CLKGATE + This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block. + 30 + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + NO_CLKS + Do not clock BCH gates in order to minimize power consumption. + 0x1 + + + + + SFTRST + Set this bit to 0 to enable normal BCH operation + 31 + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + RESET + Hold BCH in reset. + 0x1 + + + + + + + CTRL_SET + Hardware BCH ECC Accelerator Control Register + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + COMPLETE_IRQ + This bit indicates the state of the external interrupt line + 0 + 1 + read-write + + + RSVD0 + This field is reserved. + 1 + 1 + read-only + + + DEBUG_STALL_IRQ + DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. + 2 + 1 + read-write + + + BM_ERROR_IRQ + AHB Bus interface Error Interrupt Status + 3 + 1 + read-write + + + RSVD1 + This field is reserved. + 4 + 4 + read-only + + + COMPLETE_IRQ_EN + 1 = interrupt on completion of correction is enabled. + 8 + 1 + read-write + + + RSVD2 + This field is reserved. + 9 + 1 + read-only + + + DEBUG_STALL_IRQ_EN + 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block + 10 + 1 + read-write + + + RSVD3 + This field is reserved. + 11 + 5 + read-only + + + M2M_ENABLE + NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION + 16 + 1 + read-write + + + M2M_ENCODE + Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. + 17 + 1 + read-write + + + M2M_LAYOUT + Selects the flash page format for memory-to-memory operations. + 18 + 2 + read-write + + + RSVD4 + This field is reserved. + 20 + 2 + read-only + + + DEBUGSYNDROME + (For debug purposes only) + 22 + 1 + read-write + + + RSVD5 + This field is reserved. + 23 + 7 + read-only + + + CLKGATE + This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block. + 30 + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + NO_CLKS + Do not clock BCH gates in order to minimize power consumption. + 0x1 + + + + + SFTRST + Set this bit to 0 to enable normal BCH operation + 31 + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + RESET + Hold BCH in reset. + 0x1 + + + + + + + CTRL_CLR + Hardware BCH ECC Accelerator Control Register + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + COMPLETE_IRQ + This bit indicates the state of the external interrupt line + 0 + 1 + read-write + + + RSVD0 + This field is reserved. + 1 + 1 + read-only + + + DEBUG_STALL_IRQ + DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. + 2 + 1 + read-write + + + BM_ERROR_IRQ + AHB Bus interface Error Interrupt Status + 3 + 1 + read-write + + + RSVD1 + This field is reserved. + 4 + 4 + read-only + + + COMPLETE_IRQ_EN + 1 = interrupt on completion of correction is enabled. + 8 + 1 + read-write + + + RSVD2 + This field is reserved. + 9 + 1 + read-only + + + DEBUG_STALL_IRQ_EN + 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block + 10 + 1 + read-write + + + RSVD3 + This field is reserved. + 11 + 5 + read-only + + + M2M_ENABLE + NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION + 16 + 1 + read-write + + + M2M_ENCODE + Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. + 17 + 1 + read-write + + + M2M_LAYOUT + Selects the flash page format for memory-to-memory operations. + 18 + 2 + read-write + + + RSVD4 + This field is reserved. + 20 + 2 + read-only + + + DEBUGSYNDROME + (For debug purposes only) + 22 + 1 + read-write + + + RSVD5 + This field is reserved. + 23 + 7 + read-only + + + CLKGATE + This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block. + 30 + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + NO_CLKS + Do not clock BCH gates in order to minimize power consumption. + 0x1 + + + + + SFTRST + Set this bit to 0 to enable normal BCH operation + 31 + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + RESET + Hold BCH in reset. + 0x1 + + + + + + + CTRL_TOG + Hardware BCH ECC Accelerator Control Register + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + COMPLETE_IRQ + This bit indicates the state of the external interrupt line + 0 + 1 + read-write + + + RSVD0 + This field is reserved. + 1 + 1 + read-only + + + DEBUG_STALL_IRQ + DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. + 2 + 1 + read-write + + + BM_ERROR_IRQ + AHB Bus interface Error Interrupt Status + 3 + 1 + read-write + + + RSVD1 + This field is reserved. + 4 + 4 + read-only + + + COMPLETE_IRQ_EN + 1 = interrupt on completion of correction is enabled. + 8 + 1 + read-write + + + RSVD2 + This field is reserved. + 9 + 1 + read-only + + + DEBUG_STALL_IRQ_EN + 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block + 10 + 1 + read-write + + + RSVD3 + This field is reserved. + 11 + 5 + read-only + + + M2M_ENABLE + NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION + 16 + 1 + read-write + + + M2M_ENCODE + Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. + 17 + 1 + read-write + + + M2M_LAYOUT + Selects the flash page format for memory-to-memory operations. + 18 + 2 + read-write + + + RSVD4 + This field is reserved. + 20 + 2 + read-only + + + DEBUGSYNDROME + (For debug purposes only) + 22 + 1 + read-write + + + RSVD5 + This field is reserved. + 23 + 7 + read-only + + + CLKGATE + This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block. + 30 + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + NO_CLKS + Do not clock BCH gates in order to minimize power consumption. + 0x1 + + + + + SFTRST + Set this bit to 0 to enable normal BCH operation + 31 + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + RESET + Hold BCH in reset. + 0x1 + + + + + + + STATUS0 + Hardware ECC Accelerator Status Register 0 + 0x10 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + RSVD0 + This field is reserved. + 0 + 2 + read-only + + + UNCORRECTABLE + 1 = Uncorrectable error encountered during last processing cycle. + 2 + 1 + read-only + + + CORRECTED + 1 = At least one correctable error encountered during last processing cycle. + 3 + 1 + read-only + + + ALLONES + 1 = All data bits of this transaction are ONE. + 4 + 1 + read-only + + + RSVD1 + This field is reserved. + 5 + 3 + read-only + + + STATUS_BLK0 + Count of symbols in error during processing of first block of flash (metadata block) + 8 + 8 + read-only + + + ZERO + No errors found on block. + 0 + + + ERROR1 + One error found on block. + 0x1 + + + ERROR2 + One errors found on block. + 0x2 + + + ERROR3 + One errors found on block. + 0x3 + + + ERROR4 + One errors found on block. + 0x4 + + + UNCORRECTABLE + Block exhibited uncorrectable errors. + 0xFE + + + ERASED + Page is erased. + 0xFF + + + + + COMPLETED_CE + This is the chip enable number corresponding to the NAND device from which this data came. + 16 + 4 + read-only + + + HANDLE + Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction + 20 + 12 + read-only + + + + + STATUS0_SET + Hardware ECC Accelerator Status Register 0 + 0x14 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + RSVD0 + This field is reserved. + 0 + 2 + read-only + + + UNCORRECTABLE + 1 = Uncorrectable error encountered during last processing cycle. + 2 + 1 + read-only + + + CORRECTED + 1 = At least one correctable error encountered during last processing cycle. + 3 + 1 + read-only + + + ALLONES + 1 = All data bits of this transaction are ONE. + 4 + 1 + read-only + + + RSVD1 + This field is reserved. + 5 + 3 + read-only + + + STATUS_BLK0 + Count of symbols in error during processing of first block of flash (metadata block) + 8 + 8 + read-only + + + ZERO + No errors found on block. + 0 + + + ERROR1 + One error found on block. + 0x1 + + + ERROR2 + One errors found on block. + 0x2 + + + ERROR3 + One errors found on block. + 0x3 + + + ERROR4 + One errors found on block. + 0x4 + + + UNCORRECTABLE + Block exhibited uncorrectable errors. + 0xFE + + + ERASED + Page is erased. + 0xFF + + + + + COMPLETED_CE + This is the chip enable number corresponding to the NAND device from which this data came. + 16 + 4 + read-only + + + HANDLE + Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction + 20 + 12 + read-only + + + + + STATUS0_CLR + Hardware ECC Accelerator Status Register 0 + 0x18 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + RSVD0 + This field is reserved. + 0 + 2 + read-only + + + UNCORRECTABLE + 1 = Uncorrectable error encountered during last processing cycle. + 2 + 1 + read-only + + + CORRECTED + 1 = At least one correctable error encountered during last processing cycle. + 3 + 1 + read-only + + + ALLONES + 1 = All data bits of this transaction are ONE. + 4 + 1 + read-only + + + RSVD1 + This field is reserved. + 5 + 3 + read-only + + + STATUS_BLK0 + Count of symbols in error during processing of first block of flash (metadata block) + 8 + 8 + read-only + + + ZERO + No errors found on block. + 0 + + + ERROR1 + One error found on block. + 0x1 + + + ERROR2 + One errors found on block. + 0x2 + + + ERROR3 + One errors found on block. + 0x3 + + + ERROR4 + One errors found on block. + 0x4 + + + UNCORRECTABLE + Block exhibited uncorrectable errors. + 0xFE + + + ERASED + Page is erased. + 0xFF + + + + + COMPLETED_CE + This is the chip enable number corresponding to the NAND device from which this data came. + 16 + 4 + read-only + + + HANDLE + Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction + 20 + 12 + read-only + + + + + STATUS0_TOG + Hardware ECC Accelerator Status Register 0 + 0x1C + 32 + read-only + 0x10 + 0xFFFFFFFF + + + RSVD0 + This field is reserved. + 0 + 2 + read-only + + + UNCORRECTABLE + 1 = Uncorrectable error encountered during last processing cycle. + 2 + 1 + read-only + + + CORRECTED + 1 = At least one correctable error encountered during last processing cycle. + 3 + 1 + read-only + + + ALLONES + 1 = All data bits of this transaction are ONE. + 4 + 1 + read-only + + + RSVD1 + This field is reserved. + 5 + 3 + read-only + + + STATUS_BLK0 + Count of symbols in error during processing of first block of flash (metadata block) + 8 + 8 + read-only + + + ZERO + No errors found on block. + 0 + + + ERROR1 + One error found on block. + 0x1 + + + ERROR2 + One errors found on block. + 0x2 + + + ERROR3 + One errors found on block. + 0x3 + + + ERROR4 + One errors found on block. + 0x4 + + + UNCORRECTABLE + Block exhibited uncorrectable errors. + 0xFE + + + ERASED + Page is erased. + 0xFF + + + + + COMPLETED_CE + This is the chip enable number corresponding to the NAND device from which this data came. + 16 + 4 + read-only + + + HANDLE + Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction + 20 + 12 + read-only + + + + + MODE + Hardware ECC Accelerator Mode Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASE_THRESHOLD + This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased + 0 + 8 + read-write + + + RSVD + This field is reserved. + 8 + 24 + read-only + + + + + MODE_SET + Hardware ECC Accelerator Mode Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASE_THRESHOLD + This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased + 0 + 8 + read-write + + + RSVD + This field is reserved. + 8 + 24 + read-only + + + + + MODE_CLR + Hardware ECC Accelerator Mode Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASE_THRESHOLD + This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased + 0 + 8 + read-write + + + RSVD + This field is reserved. + 8 + 24 + read-only + + + + + MODE_TOG + Hardware ECC Accelerator Mode Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASE_THRESHOLD + This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased + 0 + 8 + read-write + + + RSVD + This field is reserved. + 8 + 24 + read-only + + + + + ENCODEPTR + Hardware BCH ECC Loopback Encode Buffer Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to encode buffer + 0 + 32 + read-write + + + + + ENCODEPTR_SET + Hardware BCH ECC Loopback Encode Buffer Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to encode buffer + 0 + 32 + read-write + + + + + ENCODEPTR_CLR + Hardware BCH ECC Loopback Encode Buffer Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to encode buffer + 0 + 32 + read-write + + + + + ENCODEPTR_TOG + Hardware BCH ECC Loopback Encode Buffer Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to encode buffer + 0 + 32 + read-write + + + + + DATAPTR + Hardware BCH ECC Loopback Data Buffer Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to data buffer + 0 + 32 + read-write + + + + + DATAPTR_SET + Hardware BCH ECC Loopback Data Buffer Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to data buffer + 0 + 32 + read-write + + + + + DATAPTR_CLR + Hardware BCH ECC Loopback Data Buffer Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to data buffer + 0 + 32 + read-write + + + + + DATAPTR_TOG + Hardware BCH ECC Loopback Data Buffer Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to data buffer + 0 + 32 + read-write + + + + + METAPTR + Hardware BCH ECC Loopback Metadata Buffer Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to metadata buffer + 0 + 32 + read-write + + + + + METAPTR_SET + Hardware BCH ECC Loopback Metadata Buffer Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to metadata buffer + 0 + 32 + read-write + + + + + METAPTR_CLR + Hardware BCH ECC Loopback Metadata Buffer Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to metadata buffer + 0 + 32 + read-write + + + + + METAPTR_TOG + Hardware BCH ECC Loopback Metadata Buffer Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to metadata buffer + 0 + 32 + read-write + + + + + LAYOUTSELECT + Hardware ECC Accelerator Layout Select Register + 0x70 + 32 + read-write + 0xE4E4E4E4 + 0xFFFFFFFF + + + CS0_SELECT + Selects which layout is used for chip select 0. + 0 + 2 + read-write + + + CS1_SELECT + Selects which layout is used for chip select 1. + 2 + 2 + read-write + + + CS2_SELECT + Selects which layout is used for chip select 2. + 4 + 2 + read-write + + + CS3_SELECT + Selects which layout is used for chip select 3. + 6 + 2 + read-write + + + CS4_SELECT + Selects which layout is used for chip select 4. + 8 + 2 + read-write + + + CS5_SELECT + Selects which layout is used for chip select 5. + 10 + 2 + read-write + + + CS6_SELECT + Selects which layout is used for chip select 6. + 12 + 2 + read-write + + + CS7_SELECT + Selects which layout is used for chip select 7. + 14 + 2 + read-write + + + CS8_SELECT + Selects which layout is used for chip select 8. + 16 + 2 + read-write + + + CS9_SELECT + Selects which layout is used for chip select 9. + 18 + 2 + read-write + + + CS10_SELECT + Selects which layout is used for chip select 10. + 20 + 2 + read-write + + + CS11_SELECT + Selects which layout is used for chip select 11. + 22 + 2 + read-write + + + CS12_SELECT + Selects which layout is used for chip select 12. + 24 + 2 + read-write + + + CS13_SELECT + Selects which layout is used for chip select 13. + 26 + 2 + read-write + + + CS14_SELECT + Selects which layout is used for chip select 14. + 28 + 2 + read-write + + + CS15_SELECT + Selects which layout is used for chip select 15. + 30 + 2 + read-write + + + + + LAYOUTSELECT_SET + Hardware ECC Accelerator Layout Select Register + 0x74 + 32 + read-write + 0xE4E4E4E4 + 0xFFFFFFFF + + + CS0_SELECT + Selects which layout is used for chip select 0. + 0 + 2 + read-write + + + CS1_SELECT + Selects which layout is used for chip select 1. + 2 + 2 + read-write + + + CS2_SELECT + Selects which layout is used for chip select 2. + 4 + 2 + read-write + + + CS3_SELECT + Selects which layout is used for chip select 3. + 6 + 2 + read-write + + + CS4_SELECT + Selects which layout is used for chip select 4. + 8 + 2 + read-write + + + CS5_SELECT + Selects which layout is used for chip select 5. + 10 + 2 + read-write + + + CS6_SELECT + Selects which layout is used for chip select 6. + 12 + 2 + read-write + + + CS7_SELECT + Selects which layout is used for chip select 7. + 14 + 2 + read-write + + + CS8_SELECT + Selects which layout is used for chip select 8. + 16 + 2 + read-write + + + CS9_SELECT + Selects which layout is used for chip select 9. + 18 + 2 + read-write + + + CS10_SELECT + Selects which layout is used for chip select 10. + 20 + 2 + read-write + + + CS11_SELECT + Selects which layout is used for chip select 11. + 22 + 2 + read-write + + + CS12_SELECT + Selects which layout is used for chip select 12. + 24 + 2 + read-write + + + CS13_SELECT + Selects which layout is used for chip select 13. + 26 + 2 + read-write + + + CS14_SELECT + Selects which layout is used for chip select 14. + 28 + 2 + read-write + + + CS15_SELECT + Selects which layout is used for chip select 15. + 30 + 2 + read-write + + + + + LAYOUTSELECT_CLR + Hardware ECC Accelerator Layout Select Register + 0x78 + 32 + read-write + 0xE4E4E4E4 + 0xFFFFFFFF + + + CS0_SELECT + Selects which layout is used for chip select 0. + 0 + 2 + read-write + + + CS1_SELECT + Selects which layout is used for chip select 1. + 2 + 2 + read-write + + + CS2_SELECT + Selects which layout is used for chip select 2. + 4 + 2 + read-write + + + CS3_SELECT + Selects which layout is used for chip select 3. + 6 + 2 + read-write + + + CS4_SELECT + Selects which layout is used for chip select 4. + 8 + 2 + read-write + + + CS5_SELECT + Selects which layout is used for chip select 5. + 10 + 2 + read-write + + + CS6_SELECT + Selects which layout is used for chip select 6. + 12 + 2 + read-write + + + CS7_SELECT + Selects which layout is used for chip select 7. + 14 + 2 + read-write + + + CS8_SELECT + Selects which layout is used for chip select 8. + 16 + 2 + read-write + + + CS9_SELECT + Selects which layout is used for chip select 9. + 18 + 2 + read-write + + + CS10_SELECT + Selects which layout is used for chip select 10. + 20 + 2 + read-write + + + CS11_SELECT + Selects which layout is used for chip select 11. + 22 + 2 + read-write + + + CS12_SELECT + Selects which layout is used for chip select 12. + 24 + 2 + read-write + + + CS13_SELECT + Selects which layout is used for chip select 13. + 26 + 2 + read-write + + + CS14_SELECT + Selects which layout is used for chip select 14. + 28 + 2 + read-write + + + CS15_SELECT + Selects which layout is used for chip select 15. + 30 + 2 + read-write + + + + + LAYOUTSELECT_TOG + Hardware ECC Accelerator Layout Select Register + 0x7C + 32 + read-write + 0xE4E4E4E4 + 0xFFFFFFFF + + + CS0_SELECT + Selects which layout is used for chip select 0. + 0 + 2 + read-write + + + CS1_SELECT + Selects which layout is used for chip select 1. + 2 + 2 + read-write + + + CS2_SELECT + Selects which layout is used for chip select 2. + 4 + 2 + read-write + + + CS3_SELECT + Selects which layout is used for chip select 3. + 6 + 2 + read-write + + + CS4_SELECT + Selects which layout is used for chip select 4. + 8 + 2 + read-write + + + CS5_SELECT + Selects which layout is used for chip select 5. + 10 + 2 + read-write + + + CS6_SELECT + Selects which layout is used for chip select 6. + 12 + 2 + read-write + + + CS7_SELECT + Selects which layout is used for chip select 7. + 14 + 2 + read-write + + + CS8_SELECT + Selects which layout is used for chip select 8. + 16 + 2 + read-write + + + CS9_SELECT + Selects which layout is used for chip select 9. + 18 + 2 + read-write + + + CS10_SELECT + Selects which layout is used for chip select 10. + 20 + 2 + read-write + + + CS11_SELECT + Selects which layout is used for chip select 11. + 22 + 2 + read-write + + + CS12_SELECT + Selects which layout is used for chip select 12. + 24 + 2 + read-write + + + CS13_SELECT + Selects which layout is used for chip select 13. + 26 + 2 + read-write + + + CS14_SELECT + Selects which layout is used for chip select 14. + 28 + 2 + read-write + + + CS15_SELECT + Selects which layout is used for chip select 15. + 30 + 2 + read-write + + + + + FLASH0LAYOUT0 + Hardware BCH ECC Flash 0 Layout 0 Register + 0x80 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH0LAYOUT0_SET + Hardware BCH ECC Flash 0 Layout 0 Register + 0x84 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH0LAYOUT0_CLR + Hardware BCH ECC Flash 0 Layout 0 Register + 0x88 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH0LAYOUT0_TOG + Hardware BCH ECC Flash 0 Layout 0 Register + 0x8C + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH0LAYOUT1 + Hardware BCH ECC Flash 0 Layout 1 Register + 0x90 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH0LAYOUT1_SET + Hardware BCH ECC Flash 0 Layout 1 Register + 0x94 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH0LAYOUT1_CLR + Hardware BCH ECC Flash 0 Layout 1 Register + 0x98 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH0LAYOUT1_TOG + Hardware BCH ECC Flash 0 Layout 1 Register + 0x9C + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH1LAYOUT0 + Hardware BCH ECC Flash 1 Layout 0 Register + 0xA0 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH1LAYOUT0_SET + Hardware BCH ECC Flash 1 Layout 0 Register + 0xA4 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH1LAYOUT0_CLR + Hardware BCH ECC Flash 1 Layout 0 Register + 0xA8 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH1LAYOUT0_TOG + Hardware BCH ECC Flash 1 Layout 0 Register + 0xAC + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH1LAYOUT1 + Hardware BCH ECC Flash 1 Layout 1 Register + 0xB0 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH1LAYOUT1_SET + Hardware BCH ECC Flash 1 Layout 1 Register + 0xB4 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH1LAYOUT1_CLR + Hardware BCH ECC Flash 1 Layout 1 Register + 0xB8 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH1LAYOUT1_TOG + Hardware BCH ECC Flash 1 Layout 1 Register + 0xBC + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH2LAYOUT0 + Hardware BCH ECC Flash 2 Layout 0 Register + 0xC0 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH2LAYOUT0_SET + Hardware BCH ECC Flash 2 Layout 0 Register + 0xC4 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH2LAYOUT0_CLR + Hardware BCH ECC Flash 2 Layout 0 Register + 0xC8 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH2LAYOUT0_TOG + Hardware BCH ECC Flash 2 Layout 0 Register + 0xCC + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH2LAYOUT1 + Hardware BCH ECC Flash 2 Layout 1 Register + 0xD0 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH2LAYOUT1_SET + Hardware BCH ECC Flash 2 Layout 1 Register + 0xD4 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH2LAYOUT1_CLR + Hardware BCH ECC Flash 2 Layout 1 Register + 0xD8 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH2LAYOUT1_TOG + Hardware BCH ECC Flash 2 Layout 1 Register + 0xDC + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH3LAYOUT0 + Hardware BCH ECC Flash 3 Layout 0 Register + 0xE0 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH3LAYOUT0_SET + Hardware BCH ECC Flash 3 Layout 0 Register + 0xE4 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH3LAYOUT0_CLR + Hardware BCH ECC Flash 3 Layout 0 Register + 0xE8 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH3LAYOUT0_TOG + Hardware BCH ECC Flash 3 Layout 0 Register + 0xEC + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 16 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 24 + 8 + read-write + + + + + FLASH3LAYOUT1 + Hardware BCH ECC Flash 3 Layout 1 Register + 0xF0 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH3LAYOUT1_SET + Hardware BCH ECC Flash 3 Layout 1 Register + 0xF4 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH3LAYOUT1_CLR + Hardware BCH ECC Flash 3 Layout 1 Register + 0xF8 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + FLASH3LAYOUT1_TOG + Hardware BCH ECC Flash 3 Layout 1 Register + 0xFC + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 10 + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 11 + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC60 + ECC 60 to be performed + 0x1E + + + ECC62 + ECC 62 to be performed + 0x1F + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 16 + 16 + read-write + + + + + DEBUG0 + Hardware BCH ECC Debug Register0 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_REG_SELECT + The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine + 0 + 6 + read-write + + + RSVD0 + This field is reserved. + 6 + 2 + read-only + + + BM_KES_TEST_BYPASS + 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine + 8 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_STALL + Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete + 9 + 1 + read-write + + + NORMAL + KES FSM proceeds to next block supplied by bus master. + 0 + + + WAIT + KES FSM waits after current equations are solved and the search engine is started. + 0x1 + + + + + KES_DEBUG_STEP + Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block + 10 + 1 + read-write + + + KES_STANDALONE + Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine + 11 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_KICK + Toggling causes KES engine FSM to start as if kick by the Bus Master + 12 + 1 + read-write + + + KES_DEBUG_MODE4K + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages) + 13 + 1 + read-write + + + 4k + Mode is set for 4K NAND pages. + 0x1 + + + + + KES_DEBUG_PAYLOAD_FLAG + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag + 14 + 1 + read-write + + + DATA + Payload is set for 512 bytes data block. + 0x1 + + + + + KES_DEBUG_SHIFT_SYND + Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine + 15 + 1 + read-write + + + KES_DEBUG_SYNDROME_SYMBOL + The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled + 16 + 9 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + RSVD1 + This field is reserved. + 25 + 7 + read-only + + + + + DEBUG0_SET + Hardware BCH ECC Debug Register0 + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_REG_SELECT + The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine + 0 + 6 + read-write + + + RSVD0 + This field is reserved. + 6 + 2 + read-only + + + BM_KES_TEST_BYPASS + 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine + 8 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_STALL + Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete + 9 + 1 + read-write + + + NORMAL + KES FSM proceeds to next block supplied by bus master. + 0 + + + WAIT + KES FSM waits after current equations are solved and the search engine is started. + 0x1 + + + + + KES_DEBUG_STEP + Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block + 10 + 1 + read-write + + + KES_STANDALONE + Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine + 11 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_KICK + Toggling causes KES engine FSM to start as if kick by the Bus Master + 12 + 1 + read-write + + + KES_DEBUG_MODE4K + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages) + 13 + 1 + read-write + + + 4k + Mode is set for 4K NAND pages. + 0x1 + + + + + KES_DEBUG_PAYLOAD_FLAG + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag + 14 + 1 + read-write + + + DATA + Payload is set for 512 bytes data block. + 0x1 + + + + + KES_DEBUG_SHIFT_SYND + Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine + 15 + 1 + read-write + + + KES_DEBUG_SYNDROME_SYMBOL + The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled + 16 + 9 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + RSVD1 + This field is reserved. + 25 + 7 + read-only + + + + + DEBUG0_CLR + Hardware BCH ECC Debug Register0 + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_REG_SELECT + The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine + 0 + 6 + read-write + + + RSVD0 + This field is reserved. + 6 + 2 + read-only + + + BM_KES_TEST_BYPASS + 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine + 8 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_STALL + Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete + 9 + 1 + read-write + + + NORMAL + KES FSM proceeds to next block supplied by bus master. + 0 + + + WAIT + KES FSM waits after current equations are solved and the search engine is started. + 0x1 + + + + + KES_DEBUG_STEP + Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block + 10 + 1 + read-write + + + KES_STANDALONE + Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine + 11 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_KICK + Toggling causes KES engine FSM to start as if kick by the Bus Master + 12 + 1 + read-write + + + KES_DEBUG_MODE4K + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages) + 13 + 1 + read-write + + + 4k + Mode is set for 4K NAND pages. + 0x1 + + + + + KES_DEBUG_PAYLOAD_FLAG + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag + 14 + 1 + read-write + + + DATA + Payload is set for 512 bytes data block. + 0x1 + + + + + KES_DEBUG_SHIFT_SYND + Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine + 15 + 1 + read-write + + + KES_DEBUG_SYNDROME_SYMBOL + The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled + 16 + 9 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + RSVD1 + This field is reserved. + 25 + 7 + read-only + + + + + DEBUG0_TOG + Hardware BCH ECC Debug Register0 + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_REG_SELECT + The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine + 0 + 6 + read-write + + + RSVD0 + This field is reserved. + 6 + 2 + read-only + + + BM_KES_TEST_BYPASS + 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine + 8 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_STALL + Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete + 9 + 1 + read-write + + + NORMAL + KES FSM proceeds to next block supplied by bus master. + 0 + + + WAIT + KES FSM waits after current equations are solved and the search engine is started. + 0x1 + + + + + KES_DEBUG_STEP + Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block + 10 + 1 + read-write + + + KES_STANDALONE + Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine + 11 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_KICK + Toggling causes KES engine FSM to start as if kick by the Bus Master + 12 + 1 + read-write + + + KES_DEBUG_MODE4K + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages) + 13 + 1 + read-write + + + 4k + Mode is set for 4K NAND pages. + 0x1 + + + + + KES_DEBUG_PAYLOAD_FLAG + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag + 14 + 1 + read-write + + + DATA + Payload is set for 512 bytes data block. + 0x1 + + + + + KES_DEBUG_SHIFT_SYND + Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine + 15 + 1 + read-write + + + KES_DEBUG_SYNDROME_SYMBOL + The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled + 16 + 9 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + RSVD1 + This field is reserved. + 25 + 7 + read-only + + + + + DBGKESREAD + KES Debug Read Register + 0x110 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + This register returns the ROM BIST CRC value after a BIST test. + 0 + 32 + read-only + + + + + DBGKESREAD_SET + KES Debug Read Register + 0x114 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + This register returns the ROM BIST CRC value after a BIST test. + 0 + 32 + read-only + + + + + DBGKESREAD_CLR + KES Debug Read Register + 0x118 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + This register returns the ROM BIST CRC value after a BIST test. + 0 + 32 + read-only + + + + + DBGKESREAD_TOG + KES Debug Read Register + 0x11C + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + This register returns the ROM BIST CRC value after a BIST test. + 0 + 32 + read-only + + + + + DBGCSFEREAD + Chien Search Debug Read Register + 0x120 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGCSFEREAD_SET + Chien Search Debug Read Register + 0x124 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGCSFEREAD_CLR + Chien Search Debug Read Register + 0x128 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGCSFEREAD_TOG + Chien Search Debug Read Register + 0x12C + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGSYNDGENREAD + Syndrome Generator Debug Read Register + 0x130 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGSYNDGENREAD_SET + Syndrome Generator Debug Read Register + 0x134 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGSYNDGENREAD_CLR + Syndrome Generator Debug Read Register + 0x138 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGSYNDGENREAD_TOG + Syndrome Generator Debug Read Register + 0x13C + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGAHBMREAD + Bus Master and ECC Controller Debug Read Register + 0x140 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGAHBMREAD_SET + Bus Master and ECC Controller Debug Read Register + 0x144 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGAHBMREAD_CLR + Bus Master and ECC Controller Debug Read Register + 0x148 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGAHBMREAD_TOG + Bus Master and ECC Controller Debug Read Register + 0x14C + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + BLOCKNAME + Block Name Register + 0x150 + 32 + read-only + 0x20484342 + 0xFFFFFFFF + + + NAME + The name is in the ASCII characters BCH (0x20, H, C, B). + 0 + 32 + read-only + + + + + BLOCKNAME_SET + Block Name Register + 0x154 + 32 + read-only + 0x20484342 + 0xFFFFFFFF + + + NAME + The name is in the ASCII characters BCH (0x20, H, C, B). + 0 + 32 + read-only + + + + + BLOCKNAME_CLR + Block Name Register + 0x158 + 32 + read-only + 0x20484342 + 0xFFFFFFFF + + + NAME + The name is in the ASCII characters BCH (0x20, H, C, B). + 0 + 32 + read-only + + + + + BLOCKNAME_TOG + Block Name Register + 0x15C + 32 + read-only + 0x20484342 + 0xFFFFFFFF + + + NAME + The name is in the ASCII characters BCH (0x20, H, C, B). + 0 + 32 + read-only + + + + + VERSION + BCH Version Register + 0x160 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value indicates the MINOR field of the RTL version. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value indicates the MAJOR field of the RTL version. + 24 + 8 + read-only + + + + + VERSION_SET + BCH Version Register + 0x164 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value indicates the MINOR field of the RTL version. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value indicates the MAJOR field of the RTL version. + 24 + 8 + read-only + + + + + VERSION_CLR + BCH Version Register + 0x168 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value indicates the MINOR field of the RTL version. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value indicates the MAJOR field of the RTL version. + 24 + 8 + read-only + + + + + VERSION_TOG + BCH Version Register + 0x16C + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value indicates the MINOR field of the RTL version. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value indicates the MAJOR field of the RTL version. + 24 + 8 + read-only + + + + + DEBUG1 + Hardware BCH ECC Debug Register 1 + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASED_ZERO_COUNT + The zero counts on one page. + 0 + 9 + read-only + + + RSVD + This field is reserved. + 9 + 22 + read-only + + + DEBUG1_PREERASECHK + Blank page enables pre-erase check. + 31 + 1 + read-write + + + DEBUG1_PREERASECHK_0 + Turn off pre-erase check + 0 + + + DEBUG1_PREERASECHK_1 + Turn on pre-erase check + 0x1 + + + + + + + DEBUG1_SET + Hardware BCH ECC Debug Register 1 + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASED_ZERO_COUNT + The zero counts on one page. + 0 + 9 + read-only + + + RSVD + This field is reserved. + 9 + 22 + read-only + + + DEBUG1_PREERASECHK + Blank page enables pre-erase check. + 31 + 1 + read-write + + + DEBUG1_PREERASECHK_0 + Turn off pre-erase check + 0 + + + DEBUG1_PREERASECHK_1 + Turn on pre-erase check + 0x1 + + + + + + + DEBUG1_CLR + Hardware BCH ECC Debug Register 1 + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASED_ZERO_COUNT + The zero counts on one page. + 0 + 9 + read-only + + + RSVD + This field is reserved. + 9 + 22 + read-only + + + DEBUG1_PREERASECHK + Blank page enables pre-erase check. + 31 + 1 + read-write + + + DEBUG1_PREERASECHK_0 + Turn off pre-erase check + 0 + + + DEBUG1_PREERASECHK_1 + Turn on pre-erase check + 0x1 + + + + + + + DEBUG1_TOG + Hardware BCH ECC Debug Register 1 + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASED_ZERO_COUNT + The zero counts on one page. + 0 + 9 + read-only + + + RSVD + This field is reserved. + 9 + 22 + read-only + + + DEBUG1_PREERASECHK + Blank page enables pre-erase check. + 31 + 1 + read-write + + + DEBUG1_PREERASECHK_0 + Turn off pre-erase check + 0 + + + DEBUG1_PREERASECHK_1 + Turn on pre-erase check + 0x1 + + + + + + + + + DDRC + DDRC + DDRC_REGS + 0x3D400000 + + 0 + 0x1000000 + registers + + + + MSTR + Master Register0 + 0 + 32 + read-write + 0x3040001 + 0xFFFFFFFF + + + ddr3 + Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3. + 0 + 1 + read-write + + + lpddr2 + Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to support LPDDR2. + 2 + 1 + read-write + + + lpddr3 + Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to support LPDDR3. + 3 + 1 + read-write + + + ddr4 + Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support DDR4. + 4 + 1 + read-write + + + lpddr4 + Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to support LPDDR4. + 5 + 1 + read-write + + + burstchop + When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (DDRC_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. Burst Chop for Writes is exercised only if Partial Writes enabled (DDRC_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'. BC4 (fixed) mode is not supported. + 9 + 1 + read-write + + + en_2t_timing_mode + If 1, then DDRC uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T timing is not supported in DDR4 geardown mode. Note: 2T timing is not supported in Shared-AC dual channel mode and the register value is don't care. + 10 + 1 + read-write + + + geardown_mode + 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed, only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: Geardown mode is not supported if the configuration parameter DDRC_SHARED_AC is set (in Shared-AC mode) and the register value is don't care + 11 + 1 + read-write + + + data_bus_width + Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus width is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width). + 12 + 2 + read-write + + + dll_off_mode + Set to 1 when the DDRC and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put DDRC and DRAM in DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and this bit must be set to '0'. + 15 + 1 + read-write + + + burst_rdwr + SDRAM burst length used + 16 + 4 + read-write + + + burst_rdwr_1 + Burst length of 2 (only supported for mDDR) + 0x1 + + + burst_rdwr_2 + Burst length of 4 + 0x2 + + + burst_rdwr_4 + Burst length of 8 + 0x4 + + + burst_rdwr_8 + Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) + 0x8 + + + + + frequency_ratio + Selects the Frequency Ratio + 22 + 1 + read-write + + + frequency_ratio_0 + 1:2 Mode + 0 + + + frequency_ratio_1 + 1:1 Mode + 0x1 + + + + + active_ranks + Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are present. + 24 + 2 + read-write + + + frequency_mode + Choose which registers are used. + 29 + 1 + read-write + + + frequency_mode_0 + Original Registers + 0 + + + frequency_mode_1 + Shadow Registers + 0x1 + + + + + device_config + Indicates the configuration of the device used in the system. + 30 + 2 + read-write + + + device_config_0 + x4 device + 0 + + + device_config_1 + x8 device + 0x1 + + + device_config_2 + x16 device + 0x2 + + + device_config_3 + x32 device + 0x3 + + + + + + + STAT + Operating Mode Status Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + operating_mode + Operating mode + 0 + 3 + read-only + + + selfref_type + Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. + 4 + 2 + read-only + + + selfref_type_0 + SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is in-progress. + 0 + + + selfref_type_2 + SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity + 0x2 + + + selfref_type_3 + SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error. + 0x3 + + + + + selfref_state + Self refresh state. This indicates self refresh or self refresh power down state for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh. + 8 + 2 + read-only + + + selfref_state_0 + SDRAM is not in Self Refresh. + 0 + + + selfref_state_1 + Self refresh 1 + 0x1 + + + selfref_state_2 + Self refresh power down + 0x2 + + + selfref_state_3 + Self refresh + 0x3 + + + + + + + MRCTRL0 + Mode Register Read/Write Control Register 0. + 0x10 + 32 + read-write + 0x30 + 0xFFFFFFFF + + + mr_type + Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. + 0 + 1 + read-write + + + mr_type_0 + Write + 0 + + + mr_type_1 + Read + 0x1 + + + + + mpr_en + Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4). + 1 + 1 + read-write + + + mpr_en_0 + MRS + 0 + + + mpr_en_1 + WR/RD for MPR + 0x1 + + + + + pda_en + Indicates whether the mode register operation is MRS in PDA mode or not.Note that when pba_mode=1, PBA access is initiated instead of PDA access. + 2 + 1 + read-write + + + pda_en_0 + MRS + 0 + + + pda_en_1 + MRS in Per DRAM Addressability + 0x1 + + + + + sw_init_int + Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4 independent channel mode, note that this must be programmed to both channels beforehand. Note that this must be cleared to 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. + 3 + 1 + read-write + + + sw_init_int_0 + Software intervention is not allowed + 0 + + + sw_init_int_1 + Software intervention is allowed + 0x1 + + + + + mr_rank + Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. Examples (assume DDRC is configured for 4 ranks):0x1 - select rank 0 onlyselect rank 1 onlyselect ranks 0 and 2select ranks 1 and 3select ranks 0, 1, 2 and 3 + 4 + 2 + read-write + + + mr_addr + Address of the mode register that is to be written to. + 12 + 4 + read-write + + + mr_addr_0 + MR0 + 0 + + + mr_addr_1 + MR1 + 0x1 + + + mr_addr_2 + MR2 + 0x2 + + + mr_addr_3 + MR3 + 0x3 + + + mr_addr_4 + MR4 + 0x4 + + + mr_addr_5 + MR5 + 0x5 + + + mr_addr_6 + MR6 + 0x6 + + + mr_addr_7 + MR7 + 0x7 + + + + + pba_mode + Indicates whether PBA access is executed. When setting this bit to 1 along with setting pda_en to 1, DDRC initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability mode - 1 - Per Buffer Addressability mode The completion of PBA access is confirmed by MRSTAT.pda_done in the same way as PDA. + 30 + 1 + read-write + + + mr_wr + Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRC automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. + 31 + 1 + read-write + + + + + MRCTRL1 + Mode Register Read/Write Control Register 1 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + mr_data + Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For LPDDR2/LPDDR3/LPDDR4, MRCTRL1[15:0] are interpreted as [15:8] MR Address [7:0] MR data for writes, don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. + 0 + 18 + read-write + + + + + MRSTAT + Mode Register Read/Write Status Register + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + mr_wr_busy + The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when 'MRSTAT.mr_wr_busy' is high. + 0 + 1 + read-only + + + mr_wr_busy_0 + Indicates that the SoC core can initiate a mode register write operation + 0 + + + mr_wr_busy_1 + Indicates that mode register write operation is in progress + 0x1 + + + + + pda_done + The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to perform PDA operation next time + 8 + 1 + read-only + + + pda_done_0 + Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet. + 0 + + + pda_done_1 + Indicates that mode register write operation related to PDA/PBA has competed. + 0x1 + + + + + + + MRCTRL2 + Mode Register Read/Write Control Register 2 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + mr_device_sel + Indicates the device(s) to be selected during the MRS that happens in PDA mode. Each bit is associated with one device. For example, bit[0] corresponds to Device 0, bit[1] to Device 1 etc. A '1' should be programmed to indicate that the MRS command should be applied to that device. A '0' indicates that the MRS commands should be skipped for that device. + 0 + 32 + read-write + + + + + DERATEEN + Temperature Derate Enable Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + derate_enable + Enables derating. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. + 0 + 1 + read-write + + + derate_enable_0 + Timing parameter derating is disabled + 0 + + + derate_enable_1 + Timing parameter derating is enabled using MR4 read value. + 0x1 + + + + + derate_value + Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it should be set to 0. + 1 + 1 + read-write + + + derate_value_0 + Derating uses +1 + 0 + + + derate_value_1 + Derating uses +2 + 0x1 + + + + + derate_byte + Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. + 4 + 4 + read-write + + + rc_derate_value + Derate value of tRC for LPDDR4. Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer. + 8 + 2 + read-write + + + rc_derate_value_0 + Derating uses +1 + 0 + + + rc_derate_value_1 + Derating uses +2 + 0x1 + + + rc_derate_value_2 + Derating uses +3 + 0x2 + + + rc_derate_value_3 + Derating uses +4 + 0x3 + + + + + + + DERATEINT + Temperature Derate Interval Register + 0x24 + 32 + read-write + 0x800000 + 0xFFFFFFFF + + + mr4_read_interval + Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycle. + 0 + 32 + read-write + + + + + PWRCTL + Low Power Control Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + selfref_en + If true then the DDRC puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. + 0 + 1 + read-write + + + powerdown_en + If true then the DDRC goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. + 1 + 1 + read-write + + + deeppowerdown_en + When this is 1, DDRC puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be reset to '0' to bring DDRC out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down exit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this register should not be set to 1. FOR PERFORMANCE ONLY. + 2 + 1 + read-write + + + en_dfi_dram_clk_disable + Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows:In DDR2/DDR3, can only be asserted in Self Refresh.In DDR4, can be asserted in following:in Self Refreshin Maximum Power Saving ModeIn mDDR/LPDDR2/LPDDR3, can be asserted in following:in Self Refreshin Power Downin Deep Power Downduring Normal operation (Clock Stop)In LPDDR4, can be asserted in following:in Self Refresh Power Down in Power Downduring Normal operation (Clock Stop) + 3 + 1 + read-write + + + mpsm_en + When this is 1, the DDRC puts the SDRAM into maximum power saving mode when the transaction store is empty. This register must be reset to '0' to bring DDRC out of maximum power saving mode. Present only in designs configured to support DDR4. For non-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DDR PHY, if the PHY parameter DDRC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY. + 4 + 1 + read-write + + + selfref_sw + A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. + 5 + 1 + read-write + + + selfref_sw_0 + Software Exit from Self Refresh + 0 + + + selfref_sw_1 + Software Entry to Self Refresh + 0x1 + + + + + stay_in_selfref + Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state for LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow transition from Self refresh state + 6 + 1 + read-write + + + stay_in_selfref_0 + no description available + 0 + + + stay_in_selfref_1 + no description available + 0x1 + + + + + + + PWRTMG + Low Power Timing Register + 0x34 + 32 + read-write + 0x402010 + 0xFFFFFFFF + + + powerdown_to_x32 + After this many clocks of the DDRC command channel being idle the DDRC automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. Unit: Multiples of 32 DFI clocks FOR PERFORMANCE ONLY. + 0 + 5 + read-write + + + t_dpd_x4096 + Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Multiples of 4096 DFI clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY. + 8 + 8 + read-write + + + selfref_to_x32 + After this many clocks of the DDRC command channel being idle the DDRC automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. Unit: Multiples of 32 DFI clocks. FOR PERFORMANCE ONLY. + 16 + 8 + read-write + + + + + HWLPCTL + Hardware Low Power Control Register + 0x38 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + hw_lp_en + Enable for Hardware Low Power Interface. + 0 + 1 + read-write + + + hw_lp_exit_idle_en + When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power Interface and/or Software (PWRCTL.selfref_sw). + 1 + 1 + read-write + + + hw_lp_idle_x32 + Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. Unit: Multiples of 32 DFI clocks. FOR PERFORMANCE ONLY. + 16 + 12 + read-write + + + + + RFSHCTL0 + Refresh Control Register 0 + 0x50 + 32 + read-write + 0x210000 + 0xFFFFFFFF + + + per_bank_refresh + Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 + 2 + 1 + read-write + + + per_bank_refresh_0 + All bank refresh + 0 + + + per_bank_refresh_1 + Per bank refresh + 0x1 + + + + + refresh_burst + The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiated update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY-initiated update is complete. + 4 + 5 + read-write + + + refresh_to_x32 + If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks. + 12 + 5 + read-write + + + refresh_margin + Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks. + 20 + 4 + read-write + + + + + RFSHCTL1 + Refresh Control Register 1 + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + refresh_timer0_start_value_x32 + Refresh timer start for rank 0 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples of 32 DFI clock cycles. FOR PERFORMANCE ONLY. + 0 + 12 + read-write + + + refresh_timer1_start_value_x32 + Refresh timer start for rank 1 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples of 32 DFI clock cycles. FOR PERFORMANCE ONLY. + 16 + 12 + read-write + + + + + RFSHCTL3 + Refresh Control Register 3 + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + dis_auto_refresh + When '1', disable auto-refresh generated by the DDRC. When auto-refresh is disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the DDRC. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. (DDR4 only) If FGR mode is enabled (RFSHCTL3.refresh_mode > 0), disable auto-refresh is not supported, and this bit must be set to '0'. This register field is changeable on the fly. + 0 + 1 + read-write + + + refresh_update_level + Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. refresh_update_level must not be toggled when the DDRC is in reset (core_ddrc_rstn = 0). The refresh register(s) are automatically updated when exiting reset. + 1 + 1 + read-write + + + refresh_mode + Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: Only Fixed 1x mode is supported if RFSHCTL3.dis_auto_refresh = 1. Note: The on-the-fly modes are not supported in this version of the DDRC. Note: This must be set up while the Controller is in reset or while the Controller is in self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in future version of the DDRC. Note: This register field has effect only if a DDR4 SDRAM device is in use (MSTR.ddr4 = 1). + 4 + 3 + read-write + + + + + RFSHTMG + Refresh Timing Register + 0x64 + 32 + read-write + 0x62008C + 0xFFFFFFFF + + + t_rfc_min + tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the appropriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks. + 0 + 10 + read-write + + + lpddr3_trefbw_en + Used only when LPDDR3 memory type is connected. Should only be changed when DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 - tREFBW parameter used + 15 + 1 + read-write + + + t_rfc_nom_x32 + tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed 2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks. + 16 + 12 + read-write + + + + + CRCPARCTL0 + CRC Parity Control Register0 + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + dfi_alert_err_int_en + Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input will result in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. + 0 + 1 + read-write + + + dfi_alert_err_int_clr + Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int will be cleared. When the clear operation is complete, the DDRC automatically clears this bit. + 1 + 1 + read-write + + + dfi_alert_err_cnt_clr + DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit will clear the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRC automatically clears this bit. + 2 + 1 + read-write + + + + + CRCPARCTL1 + CRC Parity Control Register1 + 0xC4 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + parity_enable + C/A Parity enable register. If RCD's parity error detection or SDRAM's parity detection is enabled, this register should be 1. + 0 + 1 + read-write + + + parity_enable_0 + Disable generation of C/A parity and disable detection of C/A parity error + 0 + + + parity_enable_1 + Enable generation of C/A parity and detection of C/A parity error + 0x1 + + + + + crc_enable + CRC enable Register. The setting of this register should match the CRC mode register setting in the DRAM. + 4 + 1 + read-write + + + crc_enable_0 + isable generation of CRC + 0 + + + crc_enable_1 + Enable generation of CRC + 0x1 + + + + + crc_inc_dm + CRC Calculation setting register. Present only in designs configured to support DDR4. + 7 + 1 + read-write + + + crc_inc_dm_0 + CRC not includes DM signal + 0 + + + crc_inc_dm_1 + CRC includes DM signal + 0x1 + + + + + caparity_disable_before_sr + If DDR4-SDRAM's CA parity is enabled by INIT6.mr5[2:0]!=0 and this register is set to 1, CA parity is automatically disabled before Self-Refresh entry and enabled after Self-Refresh exit by issuing MR5. - 1: CA parity is disabled before Self-Refresh entry - 0: CA parity is not disabled before Self-Refresh entry If Geardown is used by MSTR.geardown_mode=1, this register must be set to 1. If this register set to 0, DRAMTMG5.t_ckesr and DRAMTMG5.t_cksre must be increased by PL(Parity latency) + 12 + 1 + read-write + + + caparity_disable_before_sr_0 + CA parity is not disabled before Self-Refresh entry + 0 + + + caparity_disable_before_sr_1 + CA parity is disabled before Self-Refresh entry + 0x1 + + + + + + + CRCPARSTAT + CRC Parity Status Register + 0xCC + 32 + read-only + 0 + 0xFFFFFFFF + + + dfi_alert_err_cnt + DFI alert error count. If a parity/CRC error is detected on dfi_alert_n, this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It will saturate at 0xFFFF, and can be cleared by asserting CRCPARCTL0.dfi_alert_err_cnt_clr. + 0 + 16 + read-only + + + dfi_alert_err_int + DFI alert error interrupt. If a parity/CRC error is detected on dfi_alert_n, and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit will be set. It will remain set until cleared by CRCPARCTL0.dfi_alert_err_int_clr + 16 + 1 + read-only + + + + + INIT0 + SDRAM Initialization Register 0 + 0xD0 + 32 + read-write + 0x2004E + 0xFFFFFFFF + + + pre_cke_x1024 + Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 DFI clock cycles. DDR2 specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. For DDR3/DDR4 RDIMMs, this should include the time needed to satisfy tSTAB + 0 + 12 + read-write + + + post_cke_x1024 + Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 DFI clock cycles. DDR2 typically requires a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be programmed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. + 16 + 10 + read-write + + + skip_dram_init + If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run after power-up. + 30 + 2 + read-write + + + skip_dram_init_0 + SDRAM Initialization routine is run after power-up + 0 + + + skip_dram_init_1 + SDRAM Initialization routine is skipped after power-up + 0x1 + + + skip_dram_init_2 + SDRAM Initialization routine is run after power-up + 0x2 + + + skip_dram_init_3 + SDRAM Initialization routine is skipped after power-up + 0x3 + + + + + + + INIT1 + SDRAM Initialization Register 1 + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + pre_ocd_x32 + Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 DFI clock cycles. There is no known specific requirement for this; it may be set to zero. + 0 + 4 + read-write + + + dram_rstn_x1024 + Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 1024 DFI clock cycles. + 16 + 9 + read-write + + + + + INIT2 + SDRAM Initialization Register 2 + 0xD8 + 32 + read-write + 0xD05 + 0xFFFFFFFF + + + min_stable_clock_x1 + Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: DFI clock cycles. + 0 + 4 + read-write + + + idle_after_reset_x32 + Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 32 DFI clock cycles. + 8 + 8 + read-write + + + + + INIT3 + SDRAM Initialization Register 3 + 0xDC + 32 + read-write + 0x510 + 0xFFFFFFFF + + + emr + DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR2 register + 0 + 16 + read-write + + + mr + DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register + 16 + 16 + read-write + + + + + INIT4 + SDRAM Initialization Register 4 + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + emr3 + DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register + 0 + 16 + read-write + + + emr2 + DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused + 16 + 16 + read-write + + + + + INIT5 + SDRAM Initialization Register 5 + 0xE4 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + max_auto_init_x1024 + Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: 1024 DFI clock cycles. + 0 + 10 + read-write + + + dev_zqinit_x32 + ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires 1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 32 DFI clock cycles. + 16 + 8 + read-write + + + + + INIT6 + SDRAM Initialization Register 6 + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + mr5 + DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. + 0 + 16 + read-write + + + mr4 + DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. + 16 + 16 + read-write + + + + + INIT7 + SDRAM Initialization Register 7 + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + mr6 + DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. + 16 + 16 + read-write + + + + + DIMMCTL + DIMM Control Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + dimm_stagger_cs_en + Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs.Even if this bit is set it does not take care of software driven MR commands (via MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate. + 0 + 1 + read-write + + + dimm_stagger_cs_en_0 + Do not stagger accesses + 0 + + + dimm_stagger_cs_en_1 + (non-DDR4) Send all commands to even and odd ranks separately + 0x1 + + + + + dimm_addr_mirr_en + Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures that, for mode register accesses during the automatic initialization routine, these bits are swapped within the DDRC to compensate for this UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1. + 1 + 1 + read-write + + + dimm_addr_mirr_en_0 + Do not implement address mirroring + 0 + + + dimm_addr_mirr_en_1 + For odd ranks, implement address mirroring for MRS commands to during initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring) + 0x1 + + + + + dimm_output_inv_en + Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4 RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the DDRC during the automatic initialization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. For B-side mode register accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. + 2 + 1 + read-write + + + dimm_output_inv_en_0 + Do not implement output inversion for B-side DRAMs. + 0 + + + dimm_output_inv_en_1 + Implement output inversion for B-side DRAMs. + 0x1 + + + + + mrs_a17_en + Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, this must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. + 3 + 1 + read-write + + + mrs_a17_en_0 + Disabled + 0 + + + mrs_a17_en_1 + Enabled + 0x1 + + + + + mrs_bg1_en + Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output Inversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0 of odd ranks. + 4 + 1 + read-write + + + mrs_bg1_en_0 + Disabled + 0 + + + mrs_bg1_en_1 + Enabled + 0x1 + + + + + dimm_dis_bg_mirroring + Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs with x16 devices. + 5 + 1 + read-write + + + dimm_dis_bg_mirroring_0 + BG0 and BG1 are swapped if address mirroring is enabled. + 0 + + + dimm_dis_bg_mirroring_1 + BG0 and BG1 are NOT swapped. + 0x1 + + + + + lrdimm_bcom_cmd_prot + Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM commands defined in the Data Buffer specification. When using DDR4 LRDIMM, this bit must be set to 1. Otherwise, this bit must be set to 0. + 6 + 1 + read-write + + + + + RANKCTL + Rank Control Register + 0xF4 + 32 + read-write + 0x66F + 0xFFFFFFFF + + + max_rank_rd + Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus contention as well as to give PHY enough time to switch the delay when changing ranks. The DDRC arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_rank_rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutively to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as long as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0xF. FOR PERFORMANCE ONLY. + 0 + 4 + read-write + + + diff_rank_rd_gap + Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should consider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during reads. When the controller is operating in 1:1 mode, program this to the larger of PHY requirement or ODT requirement. When the controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to the next integer. Note that, if using DDR4-LRDIMM, refer to TRDRD timing requirements in JEDEC DDR4 Data Buffer (DDR4DB01) Specification. + 4 + 4 + read-write + + + diff_rank_wr_gap + Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should consider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcsgap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 When the controller is operating in 1:1 mode, program this to the larger of PHY requirement or ODT requirement. When the controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to the next integer. Note that, if using DDR4-LRDIMM, refer to TWRWR timing requirements in JEDEC DDR4 Data Buffer (DDR4DB01) Specification. + 8 + 4 + read-write + + + + + DRAMTMG0 + SDRAM Timing Register 0 + 0x100 + 32 + read-write + 0xF101B0F + 0xFFFFFFFF + + + t_ras_min + tRAS(min): Minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks + 0 + 6 + read-write + + + t_ras_max + tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of 1024 clocks. + 8 + 7 + read-write + + + t_faw + tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency mode. Unit: Clocks + 16 + 6 + read-write + + + wr2pre + Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2 frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM. + 24 + 7 + read-write + + + + + DRAMTMG1 + SDRAM Timing Register 1 + 0x104 + 32 + read-write + 0x80414 + 0xFFFFFFFF + + + t_rc + tRC: Minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit: Clocks. + 0 + 7 + read-write + + + rd2pre + tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously, use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode, divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. Unit: Clocks. + 8 + 6 + read-write + + + t_xp + tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program this to (tXP/2) and round it up to the next integer value. Units: Clocks + 16 + 5 + read-write + + + + + DRAMTMG2 + SDRAM Timing Register 2 + 0x108 + 32 + read-write + 0x305060D + 0xFFFFFFFF + + + wr2rd + DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same bank group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. When the controller is operating in 1:2 mode, divide the value calculated using the above equation by 2, and round it up to next integer. + 0 + 6 + read-write + + + rd2wr + DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: - WL = write latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM. + 8 + 6 + read-write + + + read_latency + Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks + 16 + 6 + read-write + + + write_latency + Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks + 24 + 6 + read-write + + + + + DRAMTMG3 + SDRAM Timing Register 3 + 0x10C + 32 + read-write + 0x50400C + 0xFFFFFFFF + + + t_mod + tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip. Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode. + 0 + 10 + read-write + + + t_mrd + tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. + 12 + 6 + read-write + + + t_mrw + Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. When the controller is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and round it up to the next integer value. For LDPDR3, this register is used for the time from a MRW/MRR to a MRW/MRR. + 20 + 10 + read-write + + + + + DRAMTMG4 + SDRAM Timing Register 4 + 0x110 + 32 + read-write + 0x5040405 + 0xFFFFFFFF + + + t_rp + tRP: Minimum time from precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. + 0 + 5 + read-write + + + t_rrd + DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Unit: Clocks. + 8 + 4 + read-write + + + t_ccd + DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. Unit: clocks. + 16 + 4 + read-write + + + t_rcd + tRCD - tAL: Minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio mode. Unit: Clocks. + 24 + 5 + read-write + + + + + DRAMTMG5 + SDRAM Timing Register 5 + 0x114 + 32 + read-write + 0x5050403 + 0xFFFFFFFF + + + t_cke + Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When the controller is operating in 1:2 frequency ratio mode, program this to (value described above)/2 and round it up to the next integer value. Unit: Clocks. + 0 + 5 + read-write + + + t_ckesr + Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. + 8 + 6 + read-write + + + t_cksre + This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+ PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. + 16 + 4 + read-write + + + t_cksrx + This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. + 24 + 4 + read-write + + + + + DRAMTMG6 + SDRAM Timing Register 6 + 0x118 + 32 + read-write + 0x2020005 + 0xFFFFFFFF + + + t_ckcsx + This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + 0 + 4 + read-write + + + t_ckdpdx + This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2 devices. + 16 + 4 + read-write + + + t_ckdpde + This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. + 24 + 4 + read-write + + + + + DRAMTMG7 + SDRAM Timing Register 7 + 0x11C + 32 + read-write + 0x202 + 0xFFFFFFFF + + + t_ckpdx + This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + 0 + 4 + read-write + + + t_ckpde + This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + 8 + 4 + read-write + + + + + DRAMTMG8 + SDRAM Timing Register 8 + 0x120 + 32 + read-write + 0x3034405 + 0xFFFFFFFF + + + t_xs_x32 + tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + 0 + 7 + read-write + + + t_xs_dll_x32 + tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + 8 + 7 + read-write + + + t_xs_abort_x32 + tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Ensure this is less than or equal to t_xs_x32. + 16 + 7 + read-write + + + t_xs_fast_x32 + tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32. + 24 + 7 + read-write + + + + + DRAMTMG9 + SDRAM Timing Register 9 + 0x124 + 32 + read-write + 0x4040D + 0xFFFFFFFF + + + wr2rd_s + CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. This comes directly from the SDRAM specification. When the controller is operating in 1:2 mode, divide the value calculated using the above equation by 2, and round it up to next integer. + 0 + 6 + read-write + + + t_rrd_s + tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. + 8 + 4 + read-write + + + t_ccd_s + tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks. + 16 + 3 + read-write + + + ddr4_wr_preamble + DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 + 30 + 1 + read-write + + + + + DRAMTMG10 + SDRAM Timing Register 10 + 0x128 + 32 + read-write + 0x1C180A + 0xFFFFFFFF + + + t_gear_hold + Geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer value. Unit: Clocks + 0 + 2 + read-write + + + t_gear_setup + Geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer value. Unit: Clocks + 2 + 2 + read-write + + + t_cmd_gear + Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2) and round it up to the next integer value. Unit: Clocks + 8 + 5 + read-write + + + t_sync_gear + Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28 When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up to the next integer value. Unit: Clocks + 16 + 5 + read-write + + + + + DRAMTMG11 + SDRAM Timing Register 11 + 0x12C + 32 + read-write + 0x440C021C + 0xFFFFFFFF + + + t_ckmpe + tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. + 0 + 5 + read-write + + + t_mpx_s + tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. + 8 + 2 + read-write + + + t_mpx_lh + tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks. + 16 + 5 + read-write + + + post_mpsm_gap_x32 + tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Multiples of 32 clocks. + 24 + 7 + read-write + + + + + DRAMTMG12 + SDRAM Timing Register 12 + 0x130 + 32 + read-write + 0x20610 + 0xFFFFFFFF + + + t_mrd_pda + tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up to the next integer value. + 0 + 5 + read-write + + + t_ckehcmd + tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next integer value. + 8 + 4 + read-write + + + t_cmdcke + tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value. + 16 + 2 + read-write + + + + + DRAMTMG13 + SDRAM Timing Register 13 + 0x134 + 32 + read-write + 0x1C200004 + 0xFFFFFFFF + + + t_ppd + LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to the next integer value. Unit: Clocks. + 0 + 3 + read-write + + + t_ccd_mw + LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks. + 16 + 6 + read-write + + + odtloff + LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round it up to the next integer value. Unit: Clocks. + 24 + 7 + read-write + + + + + DRAMTMG14 + SDRAM Timing Register 14 + 0x138 + 32 + read-write + 0xA0 + 0xFFFFFFFF + + + t_xsr + tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode. + 0 + 12 + read-write + + + + + DRAMTMG15 + SDRAM Timing Register 15 + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + t_stab_x32 + tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the clock must be stable for a time specified by tSTAB - in the case of input clock frequency change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock cycles. + 0 + 8 + read-write + + + en_dfi_lp_t_stab + Enable DFI tSTAB + 31 + 1 + read-write + + + en_dfi_lp_t_stab_0 + Disable using tSTAB when exiting DFI LP + 0 + + + en_dfi_lp_t_stab_1 + Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. + 0x1 + + + + + + + ZQCTL0 + ZQ Control Register 0 + 0x180 + 32 + read-write + 0x2000040 + 0xFFFFFFFF + + + t_zq_short_nop + tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + 0 + 10 + read-write + + + t_zq_long_nop + tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + 16 + 11 + read-write + + + dis_mpsmx_zqcl + Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting MPSM mode. + 28 + 1 + read-write + + + dis_mpsmx_zqcl_0 + Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting DDR4 devices. + 0 + + + dis_mpsmx_zqcl_1 + Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. + 0x1 + + + + + zq_resistor_shared + ZQ resistor sharing + 29 + 1 + read-write + + + zq_resistor_shared_0 + ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + 0 + + + zq_resistor_shared_1 + Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. + 0x1 + + + + + dis_srx_zqcl + Disable ZQCL/MPC + 30 + 1 + read-write + + + dis_srx_zqcl_0 + Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + 0 + + + dis_srx_zqcl_1 + Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. + 0x1 + + + + + dis_auto_zq + Disable Auto ZQCS/MPC + 31 + 1 + read-write + + + dis_auto_zq_0 + Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024. + 0 + + + dis_auto_zq_1 + Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. + 0x1 + + + + + + + ZQCTL1 + ZQ Control Register 1 + 0x184 + 32 + read-write + 0x2000100 + 0xFFFFFFFF + + + t_zq_short_interval_x1024 + Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 DFI clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + 0 + 20 + read-write + + + t_zq_reset_nop + tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode, program this to tZQReset/2 and round it up to the next integer value. This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. + 20 + 10 + read-write + + + + + ZQCTL2 + ZQ Control Register 2 + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + zq_reset + Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRC automatically clears this bit. It is recommended NOT to set this signal if in Init, Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. + 0 + 1 + read-write + + + + + ZQSTAT + ZQ Status Register + 0x18C + 32 + read-only + 0 + 0xFFFFFFFF + + + zq_reset_busy + SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. + 0 + 1 + read-only + + + zq_reset_busy_0 + Indicates that the SoC core can initiate a ZQ Reset operation + 0 + + + zq_reset_busy_1 + Indicates that ZQ Reset operation is in progress + 0x1 + + + + + + + DFITMG0 + DFI Timing Register 0 + 0x190 + 32 + read-write + 0x7020002 + 0xFFFFFFFF + + + dfi_tphy_wrlat + Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr. + 0 + 6 + read-write + + + dfi_tphy_wrdata + Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr. + 8 + 6 + read-write + + + dfi_wrdata_use_sdr + Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct value. + 15 + 1 + read-write + + + dfi_t_rddata_en + Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr. + 16 + 7 + read-write + + + dfi_rddata_use_sdr + Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct value. + 23 + 1 + read-write + + + dfi_t_ctrl_delay + Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms of DFI clock. + 24 + 5 + read-write + + + + + DFITMG1 + DFI Timing Register 1 + 0x194 + 32 + read-write + 0x404 + 0xFFFFFFFF + + + dfi_t_dram_clk_enable + Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. + 0 + 5 + read-write + + + dfi_t_dram_clk_disable + Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. + 8 + 5 + read-write + + + dfi_t_wrdata_delay + Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks + 16 + 5 + read-write + + + dfi_t_parin_lat + Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. + 24 + 2 + read-write + + + dfi_t_cmd_lat + Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 + 28 + 4 + read-write + + + + + DFILPCFG0 + DFI Low Power Configuration Register 0 + 0x198 + 32 + read-write + 0x7000000 + 0xFFFFFFFF + + + dfi_lp_en_pd + Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled + 0 + 1 + read-write + + + dfi_lp_wakeup_pd + Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: + 4 + 4 + read-write + + + dfi_lp_wakeup_pd_0 + 16 cycles + 0 + + + dfi_lp_wakeup_pd_1 + 32 cycles + 0x1 + + + dfi_lp_wakeup_pd_2 + 64 cycles + 0x2 + + + dfi_lp_wakeup_pd_3 + 128 cycles + 0x3 + + + dfi_lp_wakeup_pd_4 + 256 cycles + 0x4 + + + dfi_lp_wakeup_pd_5 + 512 cycles + 0x5 + + + dfi_lp_wakeup_pd_6 + 1024 cycles + 0x6 + + + dfi_lp_wakeup_pd_7 + 2048 cycles + 0x7 + + + dfi_lp_wakeup_pd_8 + 4096 cycles + 0x8 + + + dfi_lp_wakeup_pd_9 + 8192 cycles + 0x9 + + + dfi_lp_wakeup_pd_10 + 16384 cycles + 0xA + + + dfi_lp_wakeup_pd_11 + 32768 cycles + 0xB + + + dfi_lp_wakeup_pd_12 + 65536 cycles + 0xC + + + dfi_lp_wakeup_pd_13 + 131072 cycles + 0xD + + + dfi_lp_wakeup_pd_14 + 262144 cycles + 0xE + + + dfi_lp_wakeup_pd_15 + Unlimited cycles + 0xF + + + + + dfi_lp_en_sr + Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled + 8 + 1 + read-write + + + dfi_lp_en_sr_0 + Disabled + 0 + + + dfi_lp_en_sr_1 + Enabled + 0x1 + + + + + dfi_lp_wakeup_sr + Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: + 12 + 4 + read-write + + + dfi_lp_wakeup_sr_0 + 16 cycles + 0 + + + dfi_lp_wakeup_sr_1 + 32 cycles + 0x1 + + + dfi_lp_wakeup_sr_2 + 64 cycles + 0x2 + + + dfi_lp_wakeup_sr_3 + 128 cycles + 0x3 + + + dfi_lp_wakeup_sr_4 + 256 cycles + 0x4 + + + dfi_lp_wakeup_sr_5 + 512 cycles + 0x5 + + + dfi_lp_wakeup_sr_6 + 1024 cycles + 0x6 + + + dfi_lp_wakeup_sr_7 + 2048 cycles + 0x7 + + + dfi_lp_wakeup_sr_8 + 4096 cycles + 0x8 + + + dfi_lp_wakeup_sr_9 + 8192 cycles + 0x9 + + + dfi_lp_wakeup_sr_10 + 16384 cycles + 0xA + + + dfi_lp_wakeup_sr_11 + 32768 cycles + 0xB + + + dfi_lp_wakeup_sr_12 + 65536 cycles + 0xC + + + dfi_lp_wakeup_sr_13 + 131072 cycles + 0xD + + + dfi_lp_wakeup_sr_14 + 262144 cycles + 0xE + + + dfi_lp_wakeup_sr_15 + Unlimited cycles + 0xF + + + + + dfi_lp_en_dpd + Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. + 16 + 1 + read-write + + + dfi_lp_wakeup_dpd + Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. + 20 + 4 + read-write + + + dfi_lp_wakeup_dpd_0 + 16 cycles + 0 + + + dfi_lp_wakeup_dpd_1 + 32 cycles + 0x1 + + + dfi_lp_wakeup_dpd_2 + 64 cycles + 0x2 + + + dfi_lp_wakeup_dpd_3 + 128 cycles + 0x3 + + + dfi_lp_wakeup_dpd_4 + 256 cycles + 0x4 + + + dfi_lp_wakeup_dpd_5 + 512 cycles + 0x5 + + + dfi_lp_wakeup_dpd_6 + 1024 cycles + 0x6 + + + dfi_lp_wakeup_dpd_7 + 2048 cycles + 0x7 + + + dfi_lp_wakeup_dpd_8 + 4096 cycles + 0x8 + + + dfi_lp_wakeup_dpd_9 + 8192 cycles + 0x9 + + + dfi_lp_wakeup_dpd_10 + 16384 cycles + 0xA + + + dfi_lp_wakeup_dpd_11 + 32768 cycles + 0xB + + + dfi_lp_wakeup_dpd_12 + 65536 cycles + 0xC + + + dfi_lp_wakeup_dpd_13 + 131072 cycles + 0xD + + + dfi_lp_wakeup_dpd_14 + 262144 cycles + 0xE + + + dfi_lp_wakeup_dpd_15 + Unlimited cycles + 0xF + + + + + dfi_tlp_resp + Setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always. + 24 + 5 + read-write + + + + + DFILPCFG1 + DFI Low Power Configuration Register 1 + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + dfi_lp_en_mpsm + Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4 devices. + 0 + 1 + read-write + + + dfi_lp_wakeup_mpsm + Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: + 4 + 4 + read-write + + + dfi_lp_wakeup_mpsm_0 + 16 cycles + 0 + + + dfi_lp_wakeup_mpsm_1 + 32 cycles + 0x1 + + + dfi_lp_wakeup_mpsm_2 + 64 cycles + 0x2 + + + dfi_lp_wakeup_mpsm_3 + 128 cycles + 0x3 + + + dfi_lp_wakeup_mpsm_4 + 256 cycles + 0x4 + + + dfi_lp_wakeup_mpsm_5 + 512 cycles + 0x5 + + + dfi_lp_wakeup_mpsm_6 + 1024 cycles + 0x6 + + + dfi_lp_wakeup_mpsm_7 + 2048 cycles + 0x7 + + + dfi_lp_wakeup_mpsm_8 + 4096 cycles + 0x8 + + + dfi_lp_wakeup_mpsm_9 + 8192 cycles + 0x9 + + + dfi_lp_wakeup_mpsm_10 + 16384 cycles + 0xA + + + dfi_lp_wakeup_mpsm_11 + 32768 cycles + 0xB + + + dfi_lp_wakeup_mpsm_12 + 65536 cycles + 0xC + + + dfi_lp_wakeup_mpsm_13 + 131072 cycles + 0xD + + + dfi_lp_wakeup_mpsm_14 + 262144 cycles + 0xE + + + dfi_lp_wakeup_mpsm_15 + Unlimited cycles + 0xF + + + + + + + DFIUPD0 + DFI Update Register 0 + 0x1A0 + 32 + read-write + 0x400003 + 0xFFFFFFFF + + + dfi_t_ctrlup_min + Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRC expects the PHY to respond within this time. If the PHY does not respond, the DDRC will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. + 0 + 10 + read-write + + + dfi_t_ctrlup_max + Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. + 16 + 10 + read-write + + + ctrlupd_pre_srx + Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1 : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact, because no dfi_ctrlupd_req will be issued when SRX. + 29 + 1 + read-write + + + ctrlupd_pre_srx_0 + send ctrlupd after SRX + 0 + + + ctrlupd_pre_srx_1 + send ctrlupd before SRX + 0x1 + + + + + dis_auto_ctrlupd_srx + Auto ctrlupd request generation + 30 + 1 + read-write + + + dis_auto_ctrlupd_srx_0 + DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx. + 0 + + + dis_auto_ctrlupd_srx_1 + disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit. + 0x1 + + + + + dis_auto_ctrlupd + automatic dfi_ctrlupd_req generation by the DDRC + 31 + 1 + read-write + + + dis_auto_ctrlupd_0 + DDRC issues dfi_ctrlupd_req periodically. + 0 + + + dis_auto_ctrlupd_1 + disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req signal using register reg_ddrc_ctrlupd. + 0x1 + + + + + + + DFIUPD1 + DFI Update Register 1 + 0x1A4 + 32 + read-write + 0x10001 + 0xFFFFFFFF + + + dfi_t_ctrlupd_interval_max_x1024 + This is the maximum amount of time between DDRC initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 DFI clock cycles + 0 + 8 + read-write + + + dfi_t_ctrlupd_interval_min_x1024 + This is the minimum amount of time between DDRC initiated DFI update requests (which is executed whenever the DDRC is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRC is idle. Minimum allowed value for this field is 1. Unit: 1024 DFI clock cycles + 16 + 8 + read-write + + + + + DFIUPD2 + DFI Update Register 2 + 0x1A8 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + dfi_phyupd_en + Enables the support for acknowledging PHY-initiated updates: + 31 + 1 + read-write + + + dfi_phyupd_en_0 + Disabled + 0 + + + dfi_phyupd_en_1 + Enabled + 0x1 + + + + + + + DFIMISC + DFI Miscellaneous Control Register + 0x1B0 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + dfi_init_complete_en + PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation + 0 + 1 + read-write + + + phy_dbi_mode + DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4. + 1 + 1 + read-write + + + phy_dbi_mode_0 + DDRC implements DBI functionality. + 0 + + + phy_dbi_mode_1 + PHY implements DBI functionality. + 0x1 + + + + + dfi_data_cs_polarity + Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. + 2 + 1 + read-write + + + dfi_data_cs_polarity_0 + Signals are active low + 0 + + + dfi_data_cs_polarity_1 + Signals are active high + 0x1 + + + + + ctl_idle_en + Enables support of ctl_idle signal, which is non-DFI related pin specific to certain PHYs. See signal description of ctl_idle signal for further details of ctl_idle functionality. + 4 + 1 + read-write + + + dfi_init_start + PHY init start request signal.When asserted it triggers the PHY init start request + 5 + 1 + read-write + + + dfi_frequency + Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. + 8 + 5 + read-write + + + + + DFITMG2 + DFI Timing Register 2 + 0x1B4 + 32 + read-write + 0x202 + 0xFFFFFFFF + + + dfi_tphy_wrcslat + Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. + 0 + 6 + read-write + + + dfi_tphy_rdcslat + Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. + 8 + 7 + read-write + + + + + DFITMG3 + DFI Timing Register 3 + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + dfi_t_geardown_delay + The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to the next integer value. Unit: Clocks + 0 + 5 + read-write + + + + + DFISTAT + DFI Status Register + 0x1BC + 32 + read-only + 0 + 0xFFFFFFFF + + + dfi_init_complete + The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. + 0 + 1 + read-only + + + dfi_lp_ack + Stores the value of the dfi_lp_ack input to the controller. + 1 + 1 + read-only + + + + + DBICTL + DM/DBI Control Register + 0x1C0 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + dm_en + DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity from this signal + 0 + 1 + read-write + + + dm_en_0 + DM is disabled + 0 + + + dm_en_1 + DM is enabled + 0x1 + + + + + wr_dbi_en + This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7] + 1 + 1 + read-write + + + wr_dbi_en_0 + Write DBI is disabled + 0 + + + wr_dbi_en_1 + Write DBI is enabled. + 0x1 + + + + + rd_dbi_en + Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6] + 2 + 1 + read-write + + + + + ADDRMAP0 + Address Map Register 0 + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + addrmap_cs_bit0 + Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 28, and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0. + 0 + 5 + read-write + + + + + ADDRMAP1 + Address Map Register 1 + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + addrmap_bank_b0 + Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 31 Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. + 0 + 5 + read-write + + + addrmap_bank_b1 + Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 31 Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. + 8 + 5 + read-write + + + addrmap_bank_b2 + Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 30 and 31 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0. + 16 + 5 + read-write + + + + + ADDRMAP2 + Address Map Register 2 + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + addrmap_col_b2 + - Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF address bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this field. Note, if DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=8, it is required to program this to 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and - PCCFG.bl_exp_mode==1 and either - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 or - In LPDDR4 and ADDRMAP1.addrmap_bank_b0==0 If DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and - PCCFG.bl_exp_mode==1 and - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 Otherwise, if MEMC_BURST_LENGTH=8 and Full Bus Width (MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to column address bit 2. If MEMC_BURST_LENGTH=16 and Full Bus Width (MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to column address bit 2. If MEMC_BURST_LENGTH=16 and Half Bus Width (MSTR.data_bus_width==01), it is recommended to program this to 0 so that HIF[2] maps to column address bit 3. + 0 + 4 + read-write + + + addrmap_col_b3 + - Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF address bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this field. Note, if DDRC_INCL_ARB=1, MEMC_BURST_LENGTH=16, Full bus width (MSTR.data_bus_width=00) and BL16 (MSTR.burst_rdwr=1000), it is recommended to program this to 0. + 8 + 4 + read-write + + + addrmap_col_b4 + - Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF address bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. + 16 + 4 + read-write + + + addrmap_col_b5 + - Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF address bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. + 24 + 4 + read-write + + + + + ADDRMAP3 + Address Map Register 3 + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + addrmap_col_b6 + - Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF address bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. + 0 + 4 + read-write + + + addrmap_col_b7 + - Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF address bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. + 8 + 4 + read-write + + + addrmap_col_b8 + - Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF address bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. + 16 + 4 + read-write + + + addrmap_col_b9 + - Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. + 24 + 4 + read-write + + + + + ADDRMAP4 + Address Map Register 4 + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + addrmap_col_b10 + - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. + 0 + 4 + read-write + + + addrmap_col_b11 + - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. + 8 + 4 + read-write + + + + + ADDRMAP5 + Address Map Register 5 + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + addrmap_row_b0 + Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. + 0 + 4 + read-write + + + addrmap_row_b1 + Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. + 8 + 4 + read-write + + + addrmap_row_b2_10 + Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. When value 15 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. + 16 + 4 + read-write + + + addrmap_row_b11 + Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0. + 24 + 4 + read-write + + + + + ADDRMAP6 + Address Map Register 6 + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + addrmap_row_b12 + Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0. + 0 + 4 + read-write + + + addrmap_row_b13 + Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0. + 8 + 4 + read-write + + + addrmap_row_b14 + Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0. + 16 + 4 + read-write + + + addrmap_row_b15 + Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0. + 24 + 4 + read-write + + + lpddr3_6gb_12gb + Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present only in designs configured to support LPDDR3. + 31 + 1 + read-write + + + + + ADDRMAP7 + Address Map Register 7 + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + addrmap_row_b16 + Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0. + 0 + 4 + read-write + + + addrmap_row_b17 + Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0. + 8 + 4 + read-write + + + + + ADDRMAP8 + Address Map Register 8 + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + addrmap_bg_b0 + Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 31 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. + 0 + 5 + read-write + + + addrmap_bg_b1 + Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 31, and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If set to 63, bank group address bit 1 is set to 0. + 8 + 6 + read-write + + + + + ADDRMAP9 + Address Map Register 9 + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + addrmap_row_b2 + Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + 0 + 4 + read-write + + + addrmap_row_b3 + Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + 8 + 4 + read-write + + + addrmap_row_b4 + Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + 16 + 4 + read-write + + + addrmap_row_b5 + Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + 24 + 4 + read-write + + + + + ADDRMAP10 + Address Map Register 10 + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + addrmap_row_b6 + Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + 0 + 4 + read-write + + + addrmap_row_b7 + Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + 8 + 4 + read-write + + + addrmap_row_b8 + Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + 16 + 4 + read-write + + + addrmap_row_b9 + Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + 24 + 4 + read-write + + + + + ADDRMAP11 + Address Map Register 11 + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + addrmap_row_b10 + Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + 0 + 4 + read-write + + + + + ODTCFG + ODT Configuration Register + 0x240 + 32 + read-write + 0x4000400 + 0xFFFFFFFF + + + rd_odt_delay + The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) + 2 + 5 + read-write + + + rd_odt_hold + DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK) + 8 + 4 + read-write + + + wr_odt_delay + The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) + 16 + 5 + read-write + + + wr_odt_hold + DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) + 24 + 4 + read-write + + + + + ODTMAP + ODT/Rank Map Register + 0x244 + 32 + read-write + 0x2211 + 0xFFFFFFFF + + + rank0_wr_odt + Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. + 0 + 2 + read-write + + + rank0_rd_odt + Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. + 4 + 2 + read-write + + + rank1_wr_odt + Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks + 8 + 2 + read-write + + + rank1_rd_odt + Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks + 12 + 2 + read-write + + + + + SCHED + Scheduler Control Register + 0x250 + 32 + read-write + 0x1005 + 0xFFFFFFFF + + + force_low_pri_n + Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY. + 0 + 1 + read-write + + + prefer_write + If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. + 1 + 1 + read-write + + + pageclose + If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a need to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose feature provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY. + 2 + 1 + read-write + + + lpr_num_entries + Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one less than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests arising out of single bit error correction RMW operation. + 8 + 5 + read-write + + + go2critical_hysteresis + UNUSED + 16 + 8 + read-write + + + rdwr_idle_gap + When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this register. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. FOR PERFORMANCE ONLY + 24 + 7 + read-write + + + + + SCHED1 + Scheduler Control Register 1 + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + pageclose_timer + This field works in conjunction with SCHED.pageclose. It only has meaning if SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for details of when this may happen. If SCHED.pageclose==1 and pageclose_timer>0, then an auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit. Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a page hit. Once the timer has reached zero, an explcit precharge will be attempted to be scheduled. + 0 + 8 + read-write + + + + + PERFHPR1 + High Priority Read CAM Register 1 + 0x25C + 32 + read-write + 0xF000001 + 0xFFFFFFFF + + + hpr_max_starve + Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. FOR PERFORMANCE ONLY. + 0 + 16 + read-write + + + hpr_xact_run_length + Number of transactions that are serviced once the HPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. + 24 + 8 + read-write + + + + + PERFLPR1 + Low Priority Read CAM Register 1 + 0x264 + 32 + read-write + 0xF00007F + 0xFFFFFFFF + + + lpr_max_starve + Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. FOR PERFORMANCE ONLY. + 0 + 16 + read-write + + + lpr_xact_run_length + Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. + 24 + 8 + read-write + + + + + PERFWR1 + Write CAM Register 1 + 0x26C + 32 + read-write + 0xF00007F + 0xFFFFFFFF + + + w_max_starve + Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. FOR PERFORMANCE ONLY. + 0 + 16 + read-write + + + w_xact_run_length + Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. + 24 + 8 + read-write + + + + + DBG0 + Debug Register 0 + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + dis_wc + When 1, disable write combine. FOR DEBUG ONLY + 0 + 1 + read-write + + + dis_rd_bypass + Only present in designs supporting read bypass. When 1, disable bypass path for high priority read page hits FOR DEBUG ONLY. + 1 + 1 + read-write + + + dis_act_bypass + Only present in designs supporting activate bypass. When 1, disable bypass path for high priority read activates FOR DEBUG ONLY. + 2 + 1 + read-write + + + dis_collision_page_opt + When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY. + 4 + 1 + read-write + + + + + DBG1 + Debug Register 1 + 0x304 + 32 + read-write + 0 + 0xFFFFFFFF + + + dis_dq + When 1, DDRC will not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. This bit may be used to prevent reads or writes being issued by the DDRC, which makes it safe to modify certain register fields associated with reads and writes (see User Guide for details). After setting this bit, it is strongly recommended to poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. This bit is intended to be switched on-the-fly. + 0 + 1 + read-write + + + dis_hif + When 1, DDRC asserts the HIF command signal hif_cmd_stall. DDRC will ignore the hif_cmd_valid and all other associated request signals. This bit is intended to be switched on-the-fly. + 1 + 1 + read-write + + + + + DBGCAM + CAM Debug Register + 0x308 + 32 + read-only + 0 + 0xFFFFFFFF + + + dbg_hpr_q_depth + High priority read queue depth FOR DEBUG ONLY + 0 + 6 + read-only + + + dbg_lpr_q_depth + Low priority read queue depth The last entry of Lpr queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY + 8 + 6 + read-only + + + dbg_w_q_depth + Write queue depth The last entry of WR queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY + 16 + 6 + read-only + + + dbg_stall + Stall FOR DEBUG ONLY + 24 + 1 + read-only + + + dbg_rd_q_empty + When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. FOR DEBUG ONLY + 25 + 1 + read-only + + + dbg_wr_q_empty + When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. FOR DEBUG ONLY + 26 + 1 + read-only + + + rd_data_pipeline_empty + This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. + 28 + 1 + read-only + + + wr_data_pipeline_empty + This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. + 29 + 1 + read-only + + + dbg_stall_wr + Stall for Write channel FOR DEBUG ONLY + 30 + 1 + read-only + + + dbg_stall_rd + Stall for Read channel FOR DEBUG ONLY + 31 + 1 + read-only + + + + + DBGCMD + Command Debug Register + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + rank0_refresh + Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent to rank index 0. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. + 0 + 1 + read-write + + + rank1_refresh + Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent to rank index 1. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. + 1 + 1 + read-write + + + zq_calib_short + Setting this register bit to 1 indicates to the DDRC to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRC, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mode. + 4 + 1 + read-write + + + ctrlupd + Setting this register bit to 1 indicates to the DDRC to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRC, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. + 5 + 1 + read-write + + + + + DBGSTAT + Status Debug Register + 0x310 + 32 + read-only + 0 + 0xFFFFFFFF + + + rank0_refresh_busy + SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRC. It is recommended not to perform rank0_refresh operations when this signal is high. - 0 - Indicates that the SoC core can initiate a rank0_refresh operation - 1 - Indicates that rank0_refresh operation has not been stored yet in the DDRC + 0 + 1 + read-only + + + rank1_refresh_busy + SoC core may initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored in the DDRC. It is recommended not to perform rank1_refresh operations when this signal is high. - 0 - Indicates that the SoC core can initiate a rank1_refresh operation - 1 - Indicates that rank1_refresh operation has not been stored yet in the DDRC + 1 + 1 + read-only + + + zq_calib_short_busy + SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRC. It is recommended not to perform ZQCS operations when this signal is high. - 0 - Indicates that the SoC core can initiate a ZQCS operation - 1 - Indicates that ZQCS operation has not been initiated yet in the DDRC + 4 + 1 + read-only + + + ctrlupd_busy + SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRC. It is recommended not to perform ctrlupd operations when this signal is high. - 0 - Indicates that the SoC core can initiate a ctrlupd operation - 1 - Indicates that ctrlupd operation has not been initiated yet in the DDRC + 5 + 1 + read-only + + + + + SWCTL + Software Register Programming Control Enable + 0x320 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + sw_done + Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. + 0 + 1 + read-write + + + + + SWSTAT + Software Register Programming Control Status + 0x324 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + sw_done_ack + Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. + 0 + 1 + read-only + + + + + POISONCFG + AXI Poison Configuration Register. + 0x36C + 32 + read-write + 0x110011 + 0xFFFFFFFF + + + wr_poison_slverr_en + If set to 1, enables SLVERR response for write transaction poisoning + 0 + 1 + read-write + + + wr_poison_intr_en + If set to 1, enables interrupts for write transaction poisoning + 4 + 1 + read-write + + + wr_poison_intr_clr + Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. + 8 + 1 + read-write + + + rd_poison_slverr_en + If set to 1, enables SLVERR response for read transaction poisoning + 16 + 1 + read-write + + + rd_poison_intr_en + If set to 1, enables interrupts for read transaction poisoning + 20 + 1 + read-write + + + rd_poison_intr_clr + Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. + 24 + 1 + read-write + + + + + POISONSTAT + AXI Poison Status Register + 0x370 + 32 + read-only + 0 + 0xFFFFFFFF + + + wr_poison_intr_0 + Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. + 0 + 1 + read-only + + + rd_poison_intr_0 + Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. + 16 + 1 + read-only + + + + + PSTAT + Port Status Register + 0x3FC + 32 + read-only + 0 + 0xFFFFFFFF + + + rd_port_busy_0 + Indicates if there are outstanding reads for AXI port 0. + 0 + 1 + read-only + + + wr_port_busy_0 + Indicates if there are outstanding writes for AXI port 0. + 16 + 1 + read-only + + + + + PCCFG + Port Common Configuration Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + go2critical_en + If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0. + 0 + 1 + read-write + + + pagematch_limit + Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. + 4 + 1 + read-write + + + bl_exp_mode + Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to both reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Partial Writes is enabled (DDRC_PARTIAL_WR=1), in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd_mw penalty in LPDDR4. Hence, bl_exp_mode=1 is only recommended if DDR4 or LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - DDRC_PARTIAL_WR=0 - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.burst_rdwr=1000 (LPDDR4 only) - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.burst_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Data Channel Interleave is enabled + 8 + 1 + read-write + + + + + PCFGR_0 + Port n Configuration Read Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_port_priority + Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: The two LSBs of this register field are tied internally to 2'b00. + 0 + 10 + read-write + + + rd_port_aging_en + If set to 1, enables aging function for the read channel of the port. + 12 + 1 + read-write + + + rd_port_urgent_en + If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + 13 + 1 + read-write + + + rd_port_pagematch_en + If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. + 14 + 1 + read-write + + + rdwr_ordered_en + Enable ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the DDRC_RDWR_ORDERED_n parameter. + 16 + 1 + read-write + + + + + PCFGW_0 + Port n Configuration Write Register + 0x408 + 32 + read-write + 0x4000 + 0xFFFFFFFF + + + wr_port_priority + Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. Note: The two LSBs of this register field are tied internally to 2'b00. + 0 + 10 + read-write + + + wr_port_aging_en + If set to 1, enables aging function for the write channel of the port. + 12 + 1 + read-write + + + wr_port_urgent_en + If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + 13 + 1 + read-write + + + wr_port_pagematch_en + If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. + 14 + 1 + read-write + + + + + PCTRL_0 + Port n Control Register + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + port_en + Enables AXI port n. + 0 + 1 + read-write + + + + + PCFGQOS0_0 + Port n Read QoS Configuration Register 0 + 0x494 + 32 + read-write + 0 + 0xFFFFFFFF + + + rqos_map_level1 + Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinct values. + 0 + 4 + read-write + + + rqos_map_region0 + This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support is disabled (DDRC_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + 16 + 2 + read-write + + + rqos_map_region1 + This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled (DDRC_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + 20 + 2 + read-write + + + + + PCFGQOS1_0 + Port n Read QoS Configuration Register 1 + 0x498 + 32 + read-write + 0 + 0xFFFFFFFF + + + rqos_map_timeoutb + Specifies the timeout value for transactions mapped to the blue address queue. + 0 + 11 + read-write + + + rqos_map_timeoutr + Specifies the timeout value for transactions mapped to the red address queue. + 16 + 11 + read-write + + + + + PCFGWQOS0_0 + Port n Write QoS Configuration Register 0 + 0x49C + 32 + read-write + 0 + 0xFFFFFFFF + + + wqos_map_level + Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which corresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. + 0 + 4 + read-write + + + wqos_map_region0 + This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. + 16 + 2 + read-write + + + wqos_map_region1 + This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. + 20 + 2 + read-write + + + + + PCFGWQOS1_0 + Port n Write QoS Configuration Register 1 + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + wqos_map_timeout + Specifies the timeout value for write transactions. + 0 + 11 + read-write + + + + + DERATEEN_SHADOW + [SHADOW] Temperature Derate Enable Register + 0x2020 + 32 + read-write + 0 + 0xFFFFFFFF + + + derate_enable + Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. + 0 + 1 + read-write + + + derate_value + Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it should be set to 0. + 1 + 1 + read-write + + + derate_byte + Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. + 4 + 4 + read-write + + + rc_derate_value + Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer. + 8 + 2 + read-write + + + + + DERATEINT_SHADOW + [SHADOW] Temperature Derate Interval Register + 0x2024 + 32 + read-write + 0x800000 + 0xFFFFFFFF + + + mr4_read_interval + Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycle. + 0 + 32 + read-write + + + + + RFSHCTL0_SHADOW + [SHADOW] Refresh Control Register 0 + 0x2050 + 32 + read-write + 0x210000 + 0xFFFFFFFF + + + per_bank_refresh + - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 + 2 + 1 + read-write + + + refresh_burst + The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiated update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY-initiated update is complete. + 4 + 5 + read-write + + + refresh_to_x32 + If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks. + 12 + 5 + read-write + + + refresh_margin + Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks. + 20 + 4 + read-write + + + + + RFSHTMG_SHADOW + [SHADOW] Refresh Timing Register + 0x2064 + 32 + read-write + 0x62008C + 0xFFFFFFFF + + + t_rfc_min + tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the appropriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks. + 0 + 10 + read-write + + + lpddr3_trefbw_en + Used only when LPDDR3 memory type is connected. Should only be changed when DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 - tREFBW parameter used + 15 + 1 + read-write + + + t_rfc_nom_x32 + tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed 2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks. + 16 + 12 + read-write + + + + + INIT3_SHADOW + [SHADOW] SDRAM Initialization Register 3 + 0x20DC + 32 + read-write + 0x510 + 0xFFFFFFFF + + + emr + DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR2 register + 0 + 16 + read-write + + + mr + DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register + 16 + 16 + read-write + + + + + INIT4_SHADOW + [SHADOW] SDRAM Initialization Register 4 + 0x20E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + emr3 + DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register + 0 + 16 + read-write + + + emr2 + DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused + 16 + 16 + read-write + + + + + INIT6_SHADOW + [SHADOW] SDRAM Initialization Register 6 + 0x20E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + mr5 + DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. + 0 + 16 + read-write + + + mr4 + DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. + 16 + 16 + read-write + + + + + INIT7_SHADOW + [SHADOW] SDRAM Initialization Register 7 + 0x20EC + 32 + read-write + 0 + 0xFFFFFFFF + + + mr6 + DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. + 16 + 16 + read-write + + + + + DRAMTMG0_SHADOW + [SHADOW] SDRAM Timing Register 0 + 0x2100 + 32 + read-write + 0xF101B0F + 0xFFFFFFFF + + + t_ras_min + tRAS(min): Minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks + 0 + 6 + read-write + + + t_ras_max + tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of 1024 clocks. + 8 + 7 + read-write + + + t_faw + tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency mode. Unit: Clocks + 16 + 6 + read-write + + + wr2pre + Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2 frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM. + 24 + 7 + read-write + + + + + DRAMTMG1_SHADOW + [SHADOW] SDRAM Timing Register 1 + 0x2104 + 32 + read-write + 0x80414 + 0xFFFFFFFF + + + t_rc + tRC: Minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit: Clocks. + 0 + 7 + read-write + + + rd2pre + tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously, use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode, divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. Unit: Clocks. + 8 + 6 + read-write + + + t_xp + tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program this to (tXP/2) and round it up to the next integer value. Units: Clocks + 16 + 5 + read-write + + + + + DRAMTMG2_SHADOW + [SHADOW] SDRAM Timing Register 2 + 0x2108 + 32 + read-write + 0x305060D + 0xFFFFFFFF + + + wr2rd + DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same bank group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. When the controller is operating in 1:2 mode, divide the value calculated using the above equation by 2, and round it up to next integer. + 0 + 6 + read-write + + + rd2wr + DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: - WL = write latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM. + 8 + 6 + read-write + + + read_latency + Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks + 16 + 6 + read-write + + + write_latency + Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks + 24 + 6 + read-write + + + + + DRAMTMG3_SHADOW + [SHADOW] SDRAM Timing Register 3 + 0x210C + 32 + read-write + 0x50400C + 0xFFFFFFFF + + + t_mod + tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip. Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode. + 0 + 10 + read-write + + + t_mrd + tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. + 12 + 6 + read-write + + + t_mrw + Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. When the controller is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and round it up to the next integer value. For LDPDR3, this register is used for the time from a MRW/MRR to a MRW/MRR. + 20 + 10 + read-write + + + + + DRAMTMG4_SHADOW + [SHADOW] SDRAM Timing Register 4 + 0x2110 + 32 + read-write + 0x5040405 + 0xFFFFFFFF + + + t_rp + tRP: Minimum time from precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. + 0 + 5 + read-write + + + t_rrd + DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Unit: Clocks. + 8 + 4 + read-write + + + t_ccd + DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. Unit: clocks. + 16 + 4 + read-write + + + t_rcd + tRCD - tAL: Minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio mode. Unit: Clocks. + 24 + 5 + read-write + + + + + DRAMTMG5_SHADOW + [SHADOW] SDRAM Timing Register 5 + 0x2114 + 32 + read-write + 0x5050403 + 0xFFFFFFFF + + + t_cke + Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When the controller is operating in 1:2 frequency ratio mode, program this to (value described above)/2 and round it up to the next integer value. Unit: Clocks. + 0 + 5 + read-write + + + t_ckesr + Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. + 8 + 6 + read-write + + + t_cksre + This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+ PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. + 16 + 4 + read-write + + + t_cksrx + This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. + 24 + 4 + read-write + + + + + DRAMTMG6_SHADOW + [SHADOW] SDRAM Timing Register 6 + 0x2118 + 32 + read-write + 0x2020005 + 0xFFFFFFFF + + + t_ckcsx + This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + 0 + 4 + read-write + + + t_ckdpdx + This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2 devices. + 16 + 4 + read-write + + + t_ckdpde + This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. + 24 + 4 + read-write + + + + + DRAMTMG7_SHADOW + [SHADOW] SDRAM Timing Register 7 + 0x211C + 32 + read-write + 0x202 + 0xFFFFFFFF + + + t_ckpdx + This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + 0 + 4 + read-write + + + t_ckpde + This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + 8 + 4 + read-write + + + + + DRAMTMG8_SHADOW + [SHADOW] SDRAM Timing Register 8 + 0x2120 + 32 + read-write + 0x3034405 + 0xFFFFFFFF + + + t_xs_x32 + tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + 0 + 7 + read-write + + + t_xs_dll_x32 + tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + 8 + 7 + read-write + + + t_xs_abort_x32 + tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Ensure this is less than or equal to t_xs_x32. + 16 + 7 + read-write + + + t_xs_fast_x32 + tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32. + 24 + 7 + read-write + + + + + DRAMTMG9_SHADOW + [SHADOW] SDRAM Timing Register 9 + 0x2124 + 32 + read-write + 0x4040D + 0xFFFFFFFF + + + wr2rd_s + CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. This comes directly from the SDRAM specification. When the controller is operating in 1:2 mode, divide the value calculated using the above equation by 2, and round it up to next integer. + 0 + 6 + read-write + + + t_rrd_s + tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. + 8 + 4 + read-write + + + t_ccd_s + tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks. + 16 + 3 + read-write + + + ddr4_wr_preamble + DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 + 30 + 1 + read-write + + + + + DRAMTMG10_SHADOW + [SHADOW] SDRAM Timing Register 10 + 0x2128 + 32 + read-write + 0x1C180A + 0xFFFFFFFF + + + t_gear_hold + Geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer value. Unit: Clocks + 0 + 2 + read-write + + + t_gear_setup + Geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer value. Unit: Clocks + 2 + 2 + read-write + + + t_cmd_gear + Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2) and round it up to the next integer value. Unit: Clocks + 8 + 5 + read-write + + + t_sync_gear + Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28 When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up to the next integer value. Unit: Clocks + 16 + 5 + read-write + + + + + DRAMTMG11_SHADOW + [SHADOW] SDRAM Timing Register 11 + 0x212C + 32 + read-write + 0x440C021C + 0xFFFFFFFF + + + t_ckmpe + tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. + 0 + 5 + read-write + + + t_mpx_s + tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. + 8 + 2 + read-write + + + t_mpx_lh + tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks. + 16 + 5 + read-write + + + post_mpsm_gap_x32 + tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Multiples of 32 clocks. + 24 + 7 + read-write + + + + + DRAMTMG12_SHADOW + [SHADOW] SDRAM Timing Register 12 + 0x2130 + 32 + read-write + 0x20610 + 0xFFFFFFFF + + + t_mrd_pda + tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up to the next integer value. + 0 + 5 + read-write + + + t_ckehcmd + tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next integer value. + 8 + 4 + read-write + + + t_cmdcke + tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value. + 16 + 2 + read-write + + + + + DRAMTMG13_SHADOW + [SHADOW] SDRAM Timing Register 13 + 0x2134 + 32 + read-write + 0x1C200004 + 0xFFFFFFFF + + + t_ppd + LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to the next integer value. Unit: Clocks. + 0 + 3 + read-write + + + t_ccd_mw + LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks. + 16 + 6 + read-write + + + odtloff + LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round it up to the next integer value. Unit: Clocks. + 24 + 7 + read-write + + + + + DRAMTMG14_SHADOW + [SHADOW] SDRAM Timing Register 14 + 0x2138 + 32 + read-write + 0xA0 + 0xFFFFFFFF + + + t_xsr + tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode. + 0 + 12 + read-write + + + + + DRAMTMG15_SHADOW + [SHADOW] SDRAM Timing Register 15 + 0x213C + 32 + read-write + 0 + 0xFFFFFFFF + + + t_stab_x32 + tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the clock must be stable for a time specified by tSTAB - in the case of input clock frequency change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock cycles. + 0 + 8 + read-write + + + en_dfi_lp_t_stab + - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP + 31 + 1 + read-write + + + + + ZQCTL0_SHADOW + [SHADOW] ZQ Control Register 0 + 0x2180 + 32 + read-write + 0x2000040 + 0xFFFFFFFF + + + t_zq_short_nop + tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + 0 + 10 + read-write + + + t_zq_long_nop + tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + 16 + 11 + read-write + + + dis_mpsmx_zqcl + - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting DDR4 devices. Note: Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting MPSM mode. + 28 + 1 + read-write + + + zq_resistor_shared + - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + 29 + 1 + read-write + + + dis_srx_zqcl + - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + 30 + 1 + read-write + + + dis_auto_zq + - 1 - Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + 31 + 1 + read-write + + + + + DFITMG0_SHADOW + [SHADOW] DFI Timing Register 0 + 0x2190 + 32 + read-write + 0x7020002 + 0xFFFFFFFF + + + dfi_tphy_wrlat + Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr. + 0 + 6 + read-write + + + dfi_tphy_wrdata + Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr. + 8 + 6 + read-write + + + dfi_wrdata_use_sdr + Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct value. + 15 + 1 + read-write + + + dfi_t_rddata_en + Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr. + 16 + 7 + read-write + + + dfi_rddata_use_sdr + Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct value. + 23 + 1 + read-write + + + dfi_t_ctrl_delay + Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms of DFI clock. + 24 + 5 + read-write + + + + + DFITMG1_SHADOW + [SHADOW] DFI Timing Register 1 + 0x2194 + 32 + read-write + 0x404 + 0xFFFFFFFF + + + dfi_t_dram_clk_enable + Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. + 0 + 5 + read-write + + + dfi_t_dram_clk_disable + Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. + 8 + 5 + read-write + + + dfi_t_wrdata_delay + Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks + 16 + 5 + read-write + + + dfi_t_parin_lat + Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. + 24 + 2 + read-write + + + dfi_t_cmd_lat + Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 + 28 + 4 + read-write + + + + + DFITMG2_SHADOW + [SHADOW] DFI Timing Register 2 + 0x21B4 + 32 + read-write + 0x202 + 0xFFFFFFFF + + + dfi_tphy_wrcslat + Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. + 0 + 6 + read-write + + + dfi_tphy_rdcslat + Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. + 8 + 7 + read-write + + + + + DFITMG3_SHADOW + [SHADOW] DFI Timing Register 3 + 0x21B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + dfi_t_geardown_delay + The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to the next integer value. Unit: Clocks + 0 + 5 + read-write + + + + + ODTCFG_SHADOW + [SHADOW] ODT Configuration Register + 0x2240 + 32 + read-write + 0x4000400 + 0xFFFFFFFF + + + rd_odt_delay + The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) + 2 + 5 + read-write + + + rd_odt_hold + DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK) + 8 + 4 + read-write + + + wr_odt_delay + The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) + 16 + 5 + read-write + + + wr_odt_hold + DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) + 24 + 4 + read-write + + + + + + + ITM + Instrumentation Trace Macrocell Registers + ITM + ITM_ + 0xE0000000 + + 0 + 0x1000 + registers + + + + STIM0_READ + Stimulus Port Register 0 (for reading) + STIM0_READ_STIM0_WRITE + 0 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM0_WRITE + Stimulus Port Register 0 (for writing) + STIM0_READ_STIM0_WRITE + 0 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM1_READ + Stimulus Port Register 1 (for reading) + STIM1_READ_STIM1_WRITE + 0x4 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM1_WRITE + Stimulus Port Register 1 (for writing) + STIM1_READ_STIM1_WRITE + 0x4 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM2_READ + Stimulus Port Register 2 (for reading) + STIM2_READ_STIM2_WRITE + 0x8 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM2_WRITE + Stimulus Port Register 2 (for writing) + STIM2_READ_STIM2_WRITE + 0x8 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM3_READ + Stimulus Port Register 3 (for reading) + STIM3_READ_STIM3_WRITE + 0xC + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM3_WRITE + Stimulus Port Register 3 (for writing) + STIM3_READ_STIM3_WRITE + 0xC + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM4_READ + Stimulus Port Register 4 (for reading) + STIM4_READ_STIM4_WRITE + 0x10 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM4_WRITE + Stimulus Port Register 4 (for writing) + STIM4_READ_STIM4_WRITE + 0x10 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM5_READ + Stimulus Port Register 5 (for reading) + STIM5_READ_STIM5_WRITE + 0x14 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM5_WRITE + Stimulus Port Register 5 (for writing) + STIM5_READ_STIM5_WRITE + 0x14 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM6_READ + Stimulus Port Register 6 (for reading) + STIM6_READ_STIM6_WRITE + 0x18 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM6_WRITE + Stimulus Port Register 6 (for writing) + STIM6_READ_STIM6_WRITE + 0x18 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM7_READ + Stimulus Port Register 7 (for reading) + STIM7_READ_STIM7_WRITE + 0x1C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM7_WRITE + Stimulus Port Register 7 (for writing) + STIM7_READ_STIM7_WRITE + 0x1C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM8_READ + Stimulus Port Register 8 (for reading) + STIM8_READ_STIM8_WRITE + 0x20 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM8_WRITE + Stimulus Port Register 8 (for writing) + STIM8_READ_STIM8_WRITE + 0x20 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM9_READ + Stimulus Port Register 9 (for reading) + STIM9_READ_STIM9_WRITE + 0x24 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM9_WRITE + Stimulus Port Register 9 (for writing) + STIM9_READ_STIM9_WRITE + 0x24 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM10_READ + Stimulus Port Register 10 (for reading) + STIM10_READ_STIM10_WRITE + 0x28 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM10_WRITE + Stimulus Port Register 10 (for writing) + STIM10_READ_STIM10_WRITE + 0x28 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM11_READ + Stimulus Port Register 11 (for reading) + STIM11_READ_STIM11_WRITE + 0x2C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM11_WRITE + Stimulus Port Register 11 (for writing) + STIM11_READ_STIM11_WRITE + 0x2C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM12_READ + Stimulus Port Register 12 (for reading) + STIM12_READ_STIM12_WRITE + 0x30 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM12_WRITE + Stimulus Port Register 12 (for writing) + STIM12_READ_STIM12_WRITE + 0x30 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM13_READ + Stimulus Port Register 13 (for reading) + STIM13_READ_STIM13_WRITE + 0x34 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM13_WRITE + Stimulus Port Register 13 (for writing) + STIM13_READ_STIM13_WRITE + 0x34 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM14_READ + Stimulus Port Register 14 (for reading) + STIM14_READ_STIM14_WRITE + 0x38 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM14_WRITE + Stimulus Port Register 14 (for writing) + STIM14_READ_STIM14_WRITE + 0x38 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM15_READ + Stimulus Port Register 15 (for reading) + STIM15_READ_STIM15_WRITE + 0x3C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM15_WRITE + Stimulus Port Register 15 (for writing) + STIM15_READ_STIM15_WRITE + 0x3C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM16_READ + Stimulus Port Register 16 (for reading) + STIM16_READ_STIM16_WRITE + 0x40 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM16_WRITE + Stimulus Port Register 16 (for writing) + STIM16_READ_STIM16_WRITE + 0x40 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM17_READ + Stimulus Port Register 17 (for reading) + STIM17_READ_STIM17_WRITE + 0x44 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM17_WRITE + Stimulus Port Register 17 (for writing) + STIM17_READ_STIM17_WRITE + 0x44 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM18_READ + Stimulus Port Register 18 (for reading) + STIM18_READ_STIM18_WRITE + 0x48 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM18_WRITE + Stimulus Port Register 18 (for writing) + STIM18_READ_STIM18_WRITE + 0x48 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM19_READ + Stimulus Port Register 19 (for reading) + STIM19_READ_STIM19_WRITE + 0x4C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM19_WRITE + Stimulus Port Register 19 (for writing) + STIM19_READ_STIM19_WRITE + 0x4C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM20_READ + Stimulus Port Register 20 (for reading) + STIM20_READ_STIM20_WRITE + 0x50 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM20_WRITE + Stimulus Port Register 20 (for writing) + STIM20_READ_STIM20_WRITE + 0x50 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM21_READ + Stimulus Port Register 21 (for reading) + STIM21_READ_STIM21_WRITE + 0x54 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM21_WRITE + Stimulus Port Register 21 (for writing) + STIM21_READ_STIM21_WRITE + 0x54 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM22_READ + Stimulus Port Register 22 (for reading) + STIM22_READ_STIM22_WRITE + 0x58 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM22_WRITE + Stimulus Port Register 22 (for writing) + STIM22_READ_STIM22_WRITE + 0x58 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM23_READ + Stimulus Port Register 23 (for reading) + STIM23_READ_STIM23_WRITE + 0x5C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM23_WRITE + Stimulus Port Register 23 (for writing) + STIM23_READ_STIM23_WRITE + 0x5C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM24_READ + Stimulus Port Register 24 (for reading) + STIM24_READ_STIM24_WRITE + 0x60 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM24_WRITE + Stimulus Port Register 24 (for writing) + STIM24_READ_STIM24_WRITE + 0x60 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM25_READ + Stimulus Port Register 25 (for reading) + STIM25_READ_STIM25_WRITE + 0x64 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM25_WRITE + Stimulus Port Register 25 (for writing) + STIM25_READ_STIM25_WRITE + 0x64 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM26_READ + Stimulus Port Register 26 (for reading) + STIM26_READ_STIM26_WRITE + 0x68 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM26_WRITE + Stimulus Port Register 26 (for writing) + STIM26_READ_STIM26_WRITE + 0x68 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM27_READ + Stimulus Port Register 27 (for reading) + STIM27_READ_STIM27_WRITE + 0x6C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM27_WRITE + Stimulus Port Register 27 (for writing) + STIM27_READ_STIM27_WRITE + 0x6C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM28_READ + Stimulus Port Register 28 (for reading) + STIM28_READ_STIM28_WRITE + 0x70 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM28_WRITE + Stimulus Port Register 28 (for writing) + STIM28_READ_STIM28_WRITE + 0x70 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM29_READ + Stimulus Port Register 29 (for reading) + STIM29_READ_STIM29_WRITE + 0x74 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM29_WRITE + Stimulus Port Register 29 (for writing) + STIM29_READ_STIM29_WRITE + 0x74 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM30_READ + Stimulus Port Register 30 (for reading) + STIM30_READ_STIM30_WRITE + 0x78 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM30_WRITE + Stimulus Port Register 30 (for writing) + STIM30_READ_STIM30_WRITE + 0x78 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM31_READ + Stimulus Port Register 31 (for reading) + STIM31_READ_STIM31_WRITE + 0x7C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM31_WRITE + Stimulus Port Register 31 (for writing) + STIM31_READ_STIM31_WRITE + 0x7C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + TER + Trace Enable Register + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + STIMENA + For bit STIMENA[n], in register ITM_TERx:0 = Stimulus port (32x + n) disabled1 = Stimulus port (32x + n) enabled + 0 + 32 + read-write + + + + + TPR + Trace Privilege Register + 0xE40 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRIVMASK + Bit mask to enable tracing on ITM stimulus ports:Bit [0] = stimulus port [7:0]Bit [1] = stimulus port [15:8]Bit [2] = stimulus port [23:16]Bit [3] = stimulus port [31:24] + 0 + 4 + read-write + + + + + TCR + Trace Control Register + 0xE80 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITMENA + no description available + 0 + 1 + read-write + + + ITMENA_0 + Disabled. + 0 + + + ITMENA_1 + Enabled. + 0x1 + + + + + TSENA + no description available + 1 + 1 + read-write + + + TSENA_0 + Disabled. + 0 + + + TSENA_1 + Enabled. + 0x1 + + + + + SYNCENA + no description available + 2 + 1 + read-write + + + SYNCENA_0 + Disabled. + 0 + + + SYNCENA_1 + Enabled. + 0x1 + + + + + TXENA + no description available + 3 + 1 + read-write + + + TXENA_0 + Disabled. + 0 + + + TXENA_1 + Enabled. + 0x1 + + + + + SWOENA + no description available + 4 + 1 + read-write + + + SWOENA_0 + Timestamp counter uses the processor system clock. + 0 + + + SWOENA_1 + Timestamp counter uses asynchronous clock from the TPIU interface. + 0x1 + + + + + TSPrescale + Local timestamp prescaler, used with the trace packet reference clock. + 8 + 2 + read-write + + + TSPrescale_0 + No prescaling. + 0 + + + TSPrescale_1 + Divide by 4. + 0x1 + + + TSPrescale_2 + Divide by 16. + 0x2 + + + TSPrescale_3 + Divide by 64. + 0x3 + + + + + GTSFREQ + Global timestamp frequency. Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps. + 10 + 2 + read-write + + + GTSFREQ_0 + Disable generation of global timestamps. + 0 + + + GTSFREQ_1 + Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:7]. This is approximately every 128 cycles. + 0x1 + + + GTSFREQ_2 + Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:13]. This is approximately every 8192 cycles. + 0x2 + + + GTSFREQ_3 + Generate a timestamp after every packet, if the output FIFO is empty. + 0x3 + + + + + TraceBusID + Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a non-zero value to this field. + 16 + 7 + read-write + + + BUSY + Indicates whether the ITM is currently processing events:0: ITM is not processing any events.1: ITM events present and being drained. + 23 + 1 + read-only + + + BUSY_0 + ITM is not processing any events. + 0 + + + BUSY_1 + ITM events present and beeing drained. + 0x1 + + + + + + + LAR + Lock Access Register + 0xFB0 + 32 + read-write + 0 + 0 + + + WriteAccessCode + Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access. + 0 + 32 + read-write + + + + + LSR + Lock Status Register + 0xFB4 + 32 + read-only + 0x1 + 0xFFFFFFFD + + + IMP + Lock mechanism is implemented. This bit always reads 1. + 0 + 1 + read-only + + + STATUS + Lock Status. This bit is HIGH when the device is locked, and LOW when unlocked. + 1 + 1 + read-only + + + s8BIT + Access Lock Register size. This bit reads 0 to indicate a 32-bit register is present. + 2 + 1 + read-only + + + + + PID4 + Peripheral Identification Register 4. + 0xFD0 + 32 + read-only + 0x4 + 0xFFFFFFFF + + + JEP106 + JEP106 continuation code. + 0 + 4 + read-only + + + c4KB + 4KB Count + 4 + 4 + read-only + + + + + PID5 + Peripheral Identification Register 5. + 0xFD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID6 + Peripheral Identification Register 6. + 0xFD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID7 + Peripheral Identification Register 7. + 0xFDC + 32 + read-only + 0 + 0xFFFFFFFF + + + PID0 + Peripheral Identification Register 0. + 0xFE0 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + PartNumber + Part Number [7:0] + 0 + 8 + read-only + + + + + PID1 + Peripheral Identification Register 1. + 0xFE4 + 32 + read-only + 0xB0 + 0xFFFFFFFF + + + PartNumber + Part Number [11:8] + 0 + 4 + read-only + + + JEP106_identity_code + JEP106 identity code [3:0] + 4 + 4 + read-only + + + + + PID2 + Peripheral Identification Register 2. + 0xFE8 + 32 + read-only + 0x3B + 0xFFFFFFFF + + + JEP106_identity_code + JEP106 identity code [6:4] + 0 + 3 + read-only + + + Revision + Revision + 4 + 4 + read-only + + + + + PID3 + Peripheral Identification Register 3. + 0xFEC + 32 + read-only + 0 + 0xFFFFFFFF + + + CustomerModified + Customer Modified. + 0 + 4 + read-only + + + RevAnd + RevAnd + 4 + 4 + read-only + + + + + CID0 + Component Identification Register 0. + 0xFF0 + 32 + read-only + 0xD + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID1 + Component Identification Register 1. + 0xFF4 + 32 + read-only + 0xE0 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 4 + read-only + + + ComponentClass + Component class + 4 + 4 + read-only + + + ComponentClass_1 + ROM table. + 0x1 + + + ComponentClass_9 + CoreSight component. + 0x9 + + + ComponentClass_15 + PrimeCell of system component with no standardized register layout, for backward compatibility. + 0xF + + + + + + + CID2 + Component Identification Register 2. + 0xFF8 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID3 + Component Identification Register 3. + 0xFFC + 32 + read-only + 0xB1 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + + + DWT + Data Watchpoint and Trace Unit Registers + DWT + DWT_ + 0xE0001000 + + 0 + 0x1000 + registers + + + + CTRL + Control Register + 0 + 32 + read-write + 0 + 0xFFF001 + + + CYCCNTENA + CYCCNTENA bit. Enables CYCCNT.This bit is UNK/SBZP if the NOCYCCNT bit is RAO. + 0 + 1 + read-write + + + CYCCNTENA_0 + Disabled. + 0 + + + CYCCNTENA_1 + Enabled. + 0x1 + + + + + POSTPRESET + POSTPRESET bits. Reload value for the POSTCNT counter. This field is UNK/SBZP if the NOCYCCNT bit is RAO. + 1 + 4 + read-write + + + POSTINIT + POSTINIT bits. Initial value for the POSTCNT counter. This field is UNK/SBZP if the NOCYCCNT bit is RAO. + 5 + 4 + read-write + + + CYCTAP + CYCTAP bit. Selects the position of the POSTCNT tap on the CYCCNT counter.This bit is UNK/SBZP if the NOCYCCNT bit is RAO. + 9 + 1 + read-write + + + CYCTAP_0 + POSTCNT tap at CYCCNT[6]. + 0 + + + CYCTAP_1 + POSTCNT tap at CYCCNT[10]. + 0x1 + + + + + SYNCTAP + SYNCTAP bits. Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate. + 10 + 2 + read-write + + + SYNCTAP_0 + Disabled. No Synchronization packets. + 0 + + + SYNCTAP_1 + Synchronization counter tap at CYCCNT[24]. + 0x1 + + + SYNCTAP_2 + Synchronization counter tap at CYCCNT[26]. + 0x2 + + + SYNCTAP_3 + Synchronization counter tap at CYCCNT[28]. + 0x3 + + + + + PCSAMPLENA + PCSAMPLENA bit. Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation.This bit is UNK/SBZP if the NOTRCPKT bit is RAO or the NOCYCCNT bit is RAO. + 12 + 1 + read-write + + + PCSAMPLENA_0 + No Periodic PC sample packets generated. + 0 + + + PCSAMPLENA_1 + Periodic PC sample packets generated. + 0x1 + + + + + EXCTRCENA + EXCTRCENA bit. Enables generation of exception trace.This bit is UNK/SBZP if the NOTRCPKT bit is RAO. + 16 + 1 + read-write + + + EXCTRCENA_0 + Disabled. + 0 + + + EXCTRCENA_1 + Enabled. + 0x1 + + + + + CPIEVTENA + CPIEVTENA bit. Enables generation of the CPI counter overflow event.This bit is UNK/SBZP if the NOPRFCNT bit is RAO. + 17 + 1 + read-write + + + CPIEVTENA_0 + Disabled. + 0 + + + CPIEVTENA_1 + Enabled. + 0x1 + + + + + EXCEVTENA + EXCEVTENA bit. Enables generation of the Exception overhead counter overflow event.This bit is UNK/SBZP if the NOPRFCNT bit is RAO. + 18 + 1 + read-write + + + EXCEVTENA_0 + Disabled. + 0 + + + EXCEVTENA_1 + Enabled. + 0x1 + + + + + SLEEPEVTENA + SLEEPEVTENA bit. Enables generation of the Sleep counter overflow event.This bit is UNK/SBZP if the NOPRFCNT bit is RAO. + 19 + 1 + read-write + + + SLEEPEVTENA_0 + Disabled. + 0 + + + SLEEPEVTENA_1 + Enabled. + 0x1 + + + + + LSUEVTENA + LSUEVTENA bit. Enables generation of the LSU counter overflow event.This bit is UNK/SBZP if the NOPRFCNT bit is RAO. + 20 + 1 + read-write + + + LSUEVTENA_0 + Disabled. + 0 + + + LSUEVTENA_1 + Enabled. + 0x1 + + + + + FOLDEVTENA + FOLDEVTENA bit. Enables generation of the Folded-instruction counter overflow event.This bit is UNK/SBZP if the NOPRFCNT bit is RAO. + 21 + 1 + read-write + + + FOLDEVTENA_0 + Disabled. + 0 + + + FOLDEVTENA_1 + Enabled. + 0x1 + + + + + CYCEVTENA + CYCEVTENA bit. Enables POSTCNT underflow Event counter packets generation.This bit is UNK/SBZP if the NOTRCPKT bit is RAO or the NOCYCCNT bit is RAO. + 22 + 1 + read-write + + + CYCEVTENA_0 + No POSTCNT underflow packets generated. + 0 + + + CYCEVTENA_1 + POSTCNT underflow packets generated, if PCSAMPLENA set to 0. + 0x1 + + + + + NOPFRCNT + NOPFRCNT bit. Shows whether the implementation supports the profiling counters. + 24 + 1 + read-only + + + NOPFRCNT_0 + Supported. + 0 + + + NOPFRCNT_1 + Not supported. + 0x1 + + + + + NOCYCCNT + NOCYCCNT bit. Shows whether the implementation supports a cycle counter. + 25 + 1 + read-only + + + NOCYCCNT_0 + Cycle counter supported. + 0 + + + NOCYCCNT_1 + Cycle counter not supported. + 0x1 + + + + + NOEXTTRIG + NOEXTRRIG bit. Shows whether the implementation includes external match signals, CMPMATCH[N]. + 26 + 1 + read-only + + + NOEXTTRIG_0 + CMPMATCH[N] supported. + 0 + + + NOEXTTRIG_1 + CMPMATCH[N] not supported. + 0x1 + + + + + NOTRCPKT + NOTRCPKT bit. Shows whether the implementation supports trace sampling and exception tracing.If this bit is RAZ, the NOCYCCNT bit must also RAZ. + 27 + 1 + read-only + + + NOTRCPKT_0 + Trace sampling and exception tracing supported. + 0 + + + NOTRCPKT_1 + Trace sampling and exception tracing not supported. + 0x1 + + + + + NUMCOMP + NUMCOMP bits. Number of comparators implemented.A value of zero indicates no comparator support. + 28 + 4 + read-only + + + + + CYCCNT + Cycle Count Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CYCCNT + CYCCNT[31:0]. Incrementing cycle counter value. When enabled, CYCCNT increments on each processor clock cycle. On overflow, CYCCNT wraps to zero. + 0 + 32 + read-write + + + + + CPICNT + CPI Count Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CPICNT + CPICNT[7:0]. The base CPI counter. Counts additional cycles required to execute multi-cycle instructions, except those recorded by DWT_LSUCNT, and counts any instruction fetch stalls. + 0 + 8 + read-write + + + + + EXCCNT + Exception Overhead Count Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXCCNT + EXCCNT[7:0]. The exception overhead counter. Counts the total cycles spent in exception processing. + 0 + 8 + read-write + + + + + SLEEPCNT + Sleep Count Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEPCNT + SLEEPCNT[7:0]. Sleep counter. Counts the total number of cycles that the processor is sleeping. + 0 + 8 + read-write + + + + + LSUCNT + LSU Count Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + LSUCNT + LSUCNT[7:0]. Load-store counter. Increments on any additional cycles required to execute load or store instructions. + 0 + 8 + read-write + + + + + FOLDCNT + Folded-instruction Count Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + FOLDCNT + FOLDCNT[7:0]. Folded-instruction counter. Increments on each instruction that takes 0 cycles. + 0 + 8 + read-write + + + + + PCSR + Program Counter Sample Register + 0x1C + 32 + read-only + 0 + 0 + + + EIASAMPLE + EIASAMPLE[31:0]. Executed Instruction Address sample value. + 0 + 32 + read-only + + + + + COMP0 + Comparator Register 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP + COMP[31:0]. Reference value for comparison. + 0 + 32 + read-write + + + + + MASK0 + Mask Register 0 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + MASK[4:0]. The size of the ignore mask, 0-31 bits, applied to address range matching.The maximum mask size is IMPLEMENTATION DEFINED. A debugger can write 0b11111 to this field and then read the register back to determine the maximum mask size supported. + 0 + 5 + read-write + + + + + FUNCTION0 + Function Register 0 + 0x28 + 32 + read-write + 0 + 0xFFFFFFDF + + + FUNCTION + FUNCTION[3:0]. Selects action taken on comparator match.This field resets to zero. + 0 + 4 + read-write + + + EMITRANGE + EMITRANGE bit. If the implementation supports trace sampling, enables generation of Data trace address offset packets, that hold Daddr[15:0].If DWT_CTRL.NOTRCPKT is RAZ then this bit is UNK/SBZP. + 5 + 1 + read-write + + + EMITRANGE_0 + Data trace address offset packets disabled. + 0 + + + EMITRANGE_1 + Enable Data trace address offset packet generation. + 0x1 + + + + + CYCMATCH + CYCMATCH bit. If the implementation supports cycle counting, enable cycle count comparison for comparator 0.If DWT_CTRL.NOCYCCNT is RAZ then this bit is UNK/SBZP. + 7 + 1 + read-write + + + CYCMATCH_0 + No comparison is performed. + 0 + + + CYCMATCH_1 + Compare DWT_COMP0 with the cycle counter, DWT_CYCCNT. + 0x1 + + + + + DATAVMATCH + DATAVMATCH bit. Enables data value comparison, if supported.For comparator 0, when the CYCMATCH is set to 1, DATAVMATCH must be set to 0 for it to perform cycle count comparison.See LNK1ENA, DATAVSIZE, DATAVADDR0 and DATAVADDR1 for related information.If the implementation does not support data value comparison this bit is RAZ/WI. + 8 + 1 + read-write + + + DATAVMATCH_0 + Perform address comparison. + 0 + + + DATAVMATCH_1 + Perform data value comparison. + 0x1 + + + + + LNK1ENA + LNK1ENA bit. Indicates whether the implementation supports use of a second linked comparator.When LNK1ENA is RAO, the DATAVADDR1 field specifies the comparator to use as the second linked comparator. + 9 + 1 + read-only + + + LNK1ENA_0 + Second linked comparator not supported. + 0 + + + LNK1ENA_1 + Second linked comparator supported. + 0x1 + + + + + DATAVSIZE + DATAVSIZE[1:0]. For data value matching, specifies the size of the required data comparison. + 10 + 2 + read-write + + + DATAVSIZE_0 + Byte. + 0 + + + DATAVSIZE_1 + Halfword. + 0x1 + + + DATAVSIZE_2 + Word. + 0x2 + + + + + DATAVADDR0 + DATAVADDR0[3:0]. When the DATAVMATCH bit is set to 1 this field can hold the comparator number of a comparator to use for linked address comparison. The DWT unit ignores the value of this field if the DATAVMATCH bit is set to 0. + 12 + 4 + read-write + + + DATAVADDR1 + DATAVADDR1[3:0]. When the DATAVMATCH and LNK1ENA bits are both 1, this field can hold the comparator number of a second comparator to use for linked address comparison. The DWT unit ignores the value of this field unless the LNK1ENA bit is RAO and the DATAVMATCH bit is set to 1.If LNK1ENA is RAZ, this field is RAZ/WI. + 16 + 4 + read-write + + + MATCHED + MATCHED bit. Comparator match.A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register.Reading the register clears this bit to 0. + 24 + 1 + read-only + + + MATCHED_0 + No match. + 0 + + + MATCHED_1 + Match. + 0x1 + + + + + + + COMP1 + Comparator Register 1 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP + COMP[31:0]. Reference value for comparison. + 0 + 32 + read-write + + + + + MASK1 + Mask Register 1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + MASK[4:0]. The size of the ignore mask, 0-31 bits, applied to address range matching.The maximum mask size is IMPLEMENTATION DEFINED. A debugger can write 0b11111 to this field and then read the register back to determine the maximum mask size supported. + 0 + 5 + read-write + + + + + FUNCTION1 + Function Register 1 + 0x38 + 32 + read-write + 0 + 0xFFFFFFDF + + + FUNCTION + FUNCTION[3:0]. Selects action taken on comparator match.This field resets to zero. + 0 + 4 + read-write + + + EMITRANGE + EMITRANGE bit. If the implementation supports trace sampling, enables generation of Data trace address offset packets, that hold Daddr[15:0].If DWT_CTRL.NOTRCPKT is RAZ then this bit is UNK/SBZP. + 5 + 1 + read-write + + + EMITRANGE_0 + Data trace address offset packets disabled. + 0 + + + EMITRANGE_1 + Enable Data trace address offset packet generation. + 0x1 + + + + + DATAVMATCH + DATAVMATCH bit. Enables data value comparison, if supported.For comparator 0, when the CYCMATCH is set to 1, DATAVMATCH must be set to 0 for it to perform cycle count comparison.See LNK1ENA, DATAVSIZE, DATAVADDR0 and DATAVADDR1 for related information.If the implementation does not support data value comparison this bit is RAZ/WI. + 8 + 1 + read-write + + + DATAVMATCH_0 + Perform address comparison. + 0 + + + DATAVMATCH_1 + Perform data value comparison. + 0x1 + + + + + LNK1ENA + LNK1ENA bit. Indicates whether the implementation supports use of a second linked comparator.When LNK1ENA is RAO, the DATAVADDR1 field specifies the comparator to use as the second linked comparator. + 9 + 1 + read-only + + + LNK1ENA_0 + Second linked comparator not supported. + 0 + + + LNK1ENA_1 + Second linked comparator supported. + 0x1 + + + + + DATAVSIZE + DATAVSIZE[1:0]. For data value matching, specifies the size of the required data comparison. + 10 + 2 + read-write + + + DATAVSIZE_0 + Byte. + 0 + + + DATAVSIZE_1 + Halfword. + 0x1 + + + DATAVSIZE_2 + Word. + 0x2 + + + + + DATAVADDR0 + DATAVADDR0[3:0]. When the DATAVMATCH bit is set to 1 this field can hold the comparator number of a comparator to use for linked address comparison. The DWT unit ignores the value of this field if the DATAVMATCH bit is set to 0. + 12 + 4 + read-write + + + DATAVADDR1 + DATAVADDR1[3:0]. When the DATAVMATCH and LNK1ENA bits are both 1, this field can hold the comparator number of a second comparator to use for linked address comparison. The DWT unit ignores the value of this field unless the LNK1ENA bit is RAO and the DATAVMATCH bit is set to 1.If LNK1ENA is RAZ, this field is RAZ/WI. + 16 + 4 + read-write + + + MATCHED + MATCHED bit. Comparator match.A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register.Reading the register clears this bit to 0. + 24 + 1 + read-only + + + MATCHED_0 + No match. + 0 + + + MATCHED_1 + Match. + 0x1 + + + + + + + COMP2 + Comparator Register 2 + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP + COMP[31:0]. Reference value for comparison. + 0 + 32 + read-write + + + + + MASK2 + Mask Register 2 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + MASK[4:0]. The size of the ignore mask, 0-31 bits, applied to address range matching.The maximum mask size is IMPLEMENTATION DEFINED. A debugger can write 0b11111 to this field and then read the register back to determine the maximum mask size supported. + 0 + 5 + read-write + + + + + FUNCTION2 + Function Register 2 + 0x48 + 32 + read-write + 0 + 0xFFFFFFDF + + + FUNCTION + FUNCTION[3:0]. Selects action taken on comparator match.This field resets to zero. + 0 + 4 + read-write + + + EMITRANGE + EMITRANGE bit. If the implementation supports trace sampling, enables generation of Data trace address offset packets, that hold Daddr[15:0].If DWT_CTRL.NOTRCPKT is RAZ then this bit is UNK/SBZP. + 5 + 1 + read-write + + + EMITRANGE_0 + Data trace address offset packets disabled. + 0 + + + EMITRANGE_1 + Enable Data trace address offset packet generation. + 0x1 + + + + + DATAVMATCH + DATAVMATCH bit. Enables data value comparison, if supported.For comparator 0, when the CYCMATCH is set to 1, DATAVMATCH must be set to 0 for it to perform cycle count comparison.See LNK1ENA, DATAVSIZE, DATAVADDR0 and DATAVADDR1 for related information.If the implementation does not support data value comparison this bit is RAZ/WI. + 8 + 1 + read-write + + + DATAVMATCH_0 + Perform address comparison. + 0 + + + DATAVMATCH_1 + Perform data value comparison. + 0x1 + + + + + LNK1ENA + LNK1ENA bit. Indicates whether the implementation supports use of a second linked comparator.When LNK1ENA is RAO, the DATAVADDR1 field specifies the comparator to use as the second linked comparator. + 9 + 1 + read-only + + + LNK1ENA_0 + Second linked comparator not supported. + 0 + + + LNK1ENA_1 + Second linked comparator supported. + 0x1 + + + + + DATAVSIZE + DATAVSIZE[1:0]. For data value matching, specifies the size of the required data comparison. + 10 + 2 + read-write + + + DATAVSIZE_0 + Byte. + 0 + + + DATAVSIZE_1 + Halfword. + 0x1 + + + DATAVSIZE_2 + Word. + 0x2 + + + + + DATAVADDR0 + DATAVADDR0[3:0]. When the DATAVMATCH bit is set to 1 this field can hold the comparator number of a comparator to use for linked address comparison. The DWT unit ignores the value of this field if the DATAVMATCH bit is set to 0. + 12 + 4 + read-write + + + DATAVADDR1 + DATAVADDR1[3:0]. When the DATAVMATCH and LNK1ENA bits are both 1, this field can hold the comparator number of a second comparator to use for linked address comparison. The DWT unit ignores the value of this field unless the LNK1ENA bit is RAO and the DATAVMATCH bit is set to 1.If LNK1ENA is RAZ, this field is RAZ/WI. + 16 + 4 + read-write + + + MATCHED + MATCHED bit. Comparator match.A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register.Reading the register clears this bit to 0. + 24 + 1 + read-only + + + MATCHED_0 + No match. + 0 + + + MATCHED_1 + Match. + 0x1 + + + + + + + COMP3 + Comparator Register 3 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP + COMP[31:0]. Reference value for comparison. + 0 + 32 + read-write + + + + + MASK3 + Mask Register 3 + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + MASK[4:0]. The size of the ignore mask, 0-31 bits, applied to address range matching.The maximum mask size is IMPLEMENTATION DEFINED. A debugger can write 0b11111 to this field and then read the register back to determine the maximum mask size supported. + 0 + 5 + read-write + + + + + FUNCTION3 + Function Register 3 + 0x58 + 32 + read-write + 0 + 0xFFFFFFDF + + + FUNCTION + FUNCTION[3:0]. Selects action taken on comparator match.This field resets to zero. + 0 + 4 + read-write + + + EMITRANGE + EMITRANGE bit. If the implementation supports trace sampling, enables generation of Data trace address offset packets, that hold Daddr[15:0].If DWT_CTRL.NOTRCPKT is RAZ then this bit is UNK/SBZP. + 5 + 1 + read-write + + + EMITRANGE_0 + Data trace address offset packets disabled. + 0 + + + EMITRANGE_1 + Enable Data trace address offset packet generation. + 0x1 + + + + + DATAVMATCH + DATAVMATCH bit. Enables data value comparison, if supported.For comparator 0, when the CYCMATCH is set to 1, DATAVMATCH must be set to 0 for it to perform cycle count comparison.See LNK1ENA, DATAVSIZE, DATAVADDR0 and DATAVADDR1 for related information.If the implementation does not support data value comparison this bit is RAZ/WI. + 8 + 1 + read-write + + + DATAVMATCH_0 + Perform address comparison. + 0 + + + DATAVMATCH_1 + Perform data value comparison. + 0x1 + + + + + LNK1ENA + LNK1ENA bit. Indicates whether the implementation supports use of a second linked comparator.When LNK1ENA is RAO, the DATAVADDR1 field specifies the comparator to use as the second linked comparator. + 9 + 1 + read-only + + + LNK1ENA_0 + Second linked comparator not supported. + 0 + + + LNK1ENA_1 + Second linked comparator supported. + 0x1 + + + + + DATAVSIZE + DATAVSIZE[1:0]. For data value matching, specifies the size of the required data comparison. + 10 + 2 + read-write + + + DATAVSIZE_0 + Byte. + 0 + + + DATAVSIZE_1 + Halfword. + 0x1 + + + DATAVSIZE_2 + Word. + 0x2 + + + + + DATAVADDR0 + DATAVADDR0[3:0]. When the DATAVMATCH bit is set to 1 this field can hold the comparator number of a comparator to use for linked address comparison. The DWT unit ignores the value of this field if the DATAVMATCH bit is set to 0. + 12 + 4 + read-write + + + DATAVADDR1 + DATAVADDR1[3:0]. When the DATAVMATCH and LNK1ENA bits are both 1, this field can hold the comparator number of a second comparator to use for linked address comparison. The DWT unit ignores the value of this field unless the LNK1ENA bit is RAO and the DATAVMATCH bit is set to 1.If LNK1ENA is RAZ, this field is RAZ/WI. + 16 + 4 + read-write + + + MATCHED + MATCHED bit. Comparator match.A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register.Reading the register clears this bit to 0. + 24 + 1 + read-only + + + MATCHED_0 + No match. + 0 + + + MATCHED_1 + Match. + 0x1 + + + + + + + PID4 + Peripheral Identification Register 4. + 0xFD0 + 32 + read-only + 0x4 + 0xFFFFFFFF + + + JEP106 + JEP106 continuation code. + 0 + 4 + read-only + + + c4KB + 4KB Count + 4 + 4 + read-only + + + + + PID5 + Peripheral Identification Register 5. + 0xFD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID6 + Peripheral Identification Register 6. + 0xFD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID7 + Peripheral Identification Register 7. + 0xFDC + 32 + read-only + 0 + 0xFFFFFFFF + + + PID0 + Peripheral Identification Register 0. + 0xFE0 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + PartNumber + Part Number [7:0] + 0 + 8 + read-only + + + + + PID1 + Peripheral Identification Register 1. + 0xFE4 + 32 + read-only + 0xB0 + 0xFFFFFFFF + + + PartNumber + Part Number [11:8] + 0 + 4 + read-only + + + JEP106_identity_code + JEP106 identity code [3:0] + 4 + 4 + read-only + + + + + PID2 + Peripheral Identification Register 2. + 0xFE8 + 32 + read-only + 0x3B + 0xFFFFFFFF + + + JEP106_identity_code + JEP106 identity code [6:4] + 0 + 3 + read-only + + + Revision + Revision + 4 + 4 + read-only + + + + + PID3 + Peripheral Identification Register 3. + 0xFEC + 32 + read-only + 0 + 0xFFFFFFFF + + + CustomerModified + Customer Modified. + 0 + 4 + read-only + + + RevAnd + RevAnd + 4 + 4 + read-only + + + + + CID0 + Component Identification Register 0. + 0xFF0 + 32 + read-only + 0xD + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID1 + Component Identification Register 1. + 0xFF4 + 32 + read-only + 0xE0 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 4 + read-only + + + ComponentClass + Component class + 4 + 4 + read-only + + + ComponentClass_1 + ROM table. + 0x1 + + + ComponentClass_9 + CoreSight component. + 0x9 + + + ComponentClass_15 + PrimeCell of system component with no standardized register layout, for backward compatibility. + 0xF + + + + + + + CID2 + Component Identification Register 2. + 0xFF8 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID3 + Component Identification Register 3. + 0xFFC + 32 + read-only + 0xB1 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + + + SystemControl + System Control Block + SCB + SCB_ + 0xE000E000 + + 0 + 0xF40 + registers + + + + ACTLR + Auxiliary Control Register, + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DISMCYCINT + Disables interruption of multi-cycle instructions. + 0 + 1 + read-write + + + DISDEFWBUF + Disables write buffer use during default memory map accesses. + 1 + 1 + read-write + + + DISFOLD + Disables folding of IT instructions. + 2 + 1 + read-write + + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410FC240 + 0xFFFFFFFF + + + REVISION + Indicates patch release: 0x0 = Patch 0 + 0 + 4 + read-only + + + PARTNO + Indicates part number + 4 + 12 + read-only + + + VARIANT + Indicates processor revision: 0x2 = Revision 2 + 20 + 4 + read-only + + + IMPLEMENTER + Implementer code + 24 + 8 + read-only + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTACTIVE + Active exception number + 0 + 9 + read-only + + + RETTOBASE + no description available + 11 + 1 + read-only + + + RETTOBASE_0 + there are preempted active exceptions to execute + 0 + + + RETTOBASE_1 + there are no active exceptions, or the currently-executing exception is the only active exception + 0x1 + + + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 6 + read-only + + + ISRPENDING + no description available + 22 + 1 + read-only + + + ISRPREEMPT + no description available + 23 + 1 + read-only + + + ISRPREEMPT_0 + Will not service + 0 + + + ISRPREEMPT_1 + Will service a pending exception + 0x1 + + + + + PENDSTCLR + no description available + 25 + 1 + write-only + + + PENDSTCLR_0 + no effect + 0 + + + PENDSTCLR_1 + removes the pending state from the SysTick exception + 0x1 + + + + + PENDSTSET + no description available + 26 + 1 + read-write + + + PENDSTSET_0 + write: no effect; read: SysTick exception is not pending + 0 + + + PENDSTSET_1 + write: changes SysTick exception state to pending; read: SysTick exception is pending + 0x1 + + + + + PENDSVCLR + no description available + 27 + 1 + write-only + + + PENDSVCLR_0 + no effect + 0 + + + PENDSVCLR_1 + removes the pending state from the PendSV exception + 0x1 + + + + + PENDSVSET + no description available + 28 + 1 + read-write + + + PENDSVSET_0 + write: no effect; read: PendSV exception is not pending + 0 + + + PENDSVSET_1 + write: changes PendSV exception state to pending; read: PendSV exception is pending + 0x1 + + + + + NMIPENDSET + no description available + 31 + 1 + read-write + + + NMIPENDSET_0 + write: no effect; read: NMI exception is not pending + 0 + + + NMIPENDSET_1 + write: changes NMI exception state to pending; read: NMI exception is pending + 0x1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + read-write + 0 + 0xFFFFFFFF + + + TBLOFF + Vector table base offset + 7 + 25 + read-write + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTRESET + no description available + 0 + 1 + write-only + + + VECTCLRACTIVE + no description available + 1 + 1 + write-only + + + SYSRESETREQ + no description available + 2 + 1 + write-only + + + SYSRESETREQ_0 + no system reset request + 0 + + + SYSRESETREQ_1 + asserts a signal to the outer system that requests a reset + 0x1 + + + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. + 8 + 3 + read-write + + + ENDIANNESS + no description available + 15 + 1 + read-only + + + ENDIANNESS_0 + Little-endian + 0 + + + ENDIANNESS_1 + Big-endian + 0x1 + + + + + VECTKEY + Register key + 16 + 16 + read-write + + + + + SCR + System Control Register + 0xD10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEPONEXIT + no description available + 1 + 1 + read-write + + + SLEEPONEXIT_0 + o not sleep when returning to Thread mode + 0 + + + SLEEPONEXIT_1 + enter sleep, or deep sleep, on return from an ISR + 0x1 + + + + + SLEEPDEEP + no description available + 2 + 1 + read-write + + + SLEEPDEEP_0 + sleep + 0 + + + SLEEPDEEP_1 + deep sleep + 0x1 + + + + + SEVONPEND + no description available + 4 + 1 + read-write + + + SEVONPEND_0 + only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + SEVONPEND_1 + enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 0x1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-write + 0 + 0xFFFFFFFF + + + NONBASETHRDENA + no description available + 0 + 1 + read-write + + + NONBASETHRDENA_0 + processor can enter Thread mode only when no exception is active + 0 + + + NONBASETHRDENA_1 + processor can enter Thread mode from any level under the control of an EXC_RETURN value + 0x1 + + + + + USERSETMPEND + Enables unprivileged software access to the STIR + 1 + 1 + read-write + + + USERSETMPEND_0 + disable + 0 + + + USERSETMPEND_1 + enable + 0x1 + + + + + UNALIGN_TRP + Enables unaligned access traps + 3 + 1 + read-write + + + UNALIGN_TRP_0 + do not trap unaligned halfword and word accesses + 0 + + + UNALIGN_TRP_1 + trap unaligned halfword and word accesses + 0x1 + + + + + DIV_0_TRP + Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 + 4 + 1 + read-write + + + DIV_0_TRP_0 + do not trap divide by 0 + 0 + + + DIV_0_TRP_1 + trap divide by 0 + 0x1 + + + + + BFHFNMIGN + Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. + 8 + 1 + read-write + + + BFHFNMIGN_0 + data bus faults caused by load and store instructions cause a lock-up + 0 + + + BFHFNMIGN_1 + handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions + 0x1 + + + + + STKALIGN + Indicates stack alignment on exception entry + 9 + 1 + read-write + + + STKALIGN_0 + 4-byte aligned + 0 + + + STKALIGN_1 + 8-byte aligned + 0x1 + + + + + + + SHPR1 + System Handler Priority Register 1 + 0xD18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_4 + Priority of system handler 4, MemManage + 0 + 8 + read-write + + + PRI_5 + Priority of system handler 5, BusFault + 8 + 8 + read-write + + + PRI_6 + Priority of system handler 6, UsageFault + 16 + 8 + read-write + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + read-write + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + read-write + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + read-write + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEMFAULTACT + no description available + 0 + 1 + read-write + + + MEMFAULTACT_0 + exception is not active + 0 + + + MEMFAULTACT_1 + exception is active + 0x1 + + + + + BUSFAULTACT + no description available + 1 + 1 + read-write + + + BUSFAULTACT_0 + exception is not active + 0 + + + BUSFAULTACT_1 + exception is active + 0x1 + + + + + USGFAULTACT + no description available + 3 + 1 + read-write + + + USGFAULTACT_0 + exception is not active + 0 + + + USGFAULTACT_1 + exception is active + 0x1 + + + + + SVCALLACT + no description available + 7 + 1 + read-write + + + SVCALLACT_0 + exception is not active + 0 + + + SVCALLACT_1 + exception is active + 0x1 + + + + + MONITORACT + no description available + 8 + 1 + read-write + + + MONITORACT_0 + exception is not active + 0 + + + MONITORACT_1 + exception is active + 0x1 + + + + + PENDSVACT + no description available + 10 + 1 + read-write + + + PENDSVACT_0 + exception is not active + 0 + + + PENDSVACT_1 + exception is active + 0x1 + + + + + SYSTICKACT + no description available + 11 + 1 + read-write + + + SYSTICKACT_0 + exception is not active + 0 + + + SYSTICKACT_1 + exception is active + 0x1 + + + + + USGFAULTPENDED + no description available + 12 + 1 + read-write + + + USGFAULTPENDED_0 + exception is not pending + 0 + + + USGFAULTPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTPENDED + no description available + 13 + 1 + read-write + + + MEMFAULTPENDED_0 + exception is not pending + 0 + + + MEMFAULTPENDED_1 + exception is pending + 0x1 + + + + + BUSFAULTPENDED + no description available + 14 + 1 + read-write + + + BUSFAULTPENDED_0 + exception is not pending + 0 + + + BUSFAULTPENDED_1 + exception is pending + 0x1 + + + + + SVCALLPENDED + no description available + 15 + 1 + read-write + + + SVCALLPENDED_0 + exception is not pending + 0 + + + SVCALLPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTENA + no description available + 16 + 1 + read-write + + + MEMFAULTENA_0 + disable the exception + 0 + + + MEMFAULTENA_1 + enable the exception + 0x1 + + + + + BUSFAULTENA + no description available + 17 + 1 + read-write + + + BUSFAULTENA_0 + disable the exception + 0 + + + BUSFAULTENA_1 + enable the exception + 0x1 + + + + + USGFAULTENA + no description available + 18 + 1 + read-write + + + USGFAULTENA_0 + disable the exception + 0 + + + USGFAULTENA_1 + enable the exception + 0x1 + + + + + + + CFSR + Configurable Fault Status Registers + 0xD28 + 32 + read-write + 0 + 0xFFFFFFFF + + + IACCVIOL + no description available + 0 + 1 + read-write + + + IACCVIOL_0 + no instruction access violation fault + 0 + + + IACCVIOL_1 + the processor attempted an instruction fetch from a location that does not permit execution + 0x1 + + + + + DACCVIOL + no description available + 1 + 1 + read-write + + + DACCVIOL_0 + no data access violation fault + 0 + + + DACCVIOL_1 + the processor attempted a load or store at a location that does not permit the operation + 0x1 + + + + + MUNSTKERR + no description available + 3 + 1 + read-write + + + MUNSTKERR_0 + no unstacking fault + 0 + + + MUNSTKERR_1 + unstack for an exception return has caused one or more access violations + 0x1 + + + + + MSTKERR + no description available + 4 + 1 + read-write + + + MSTKERR_0 + no stacking fault + 0 + + + MSTKERR_1 + stacking for an exception entry has caused one or more access violations + 0x1 + + + + + MLSPERR + no description available + 5 + 1 + read-write + + + MLSPERR_0 + No MemManage fault occurred during floating-point lazy state preservation + 0 + + + MLSPERR_1 + A MemManage fault occurred during floating-point lazy state preservation + 0x1 + + + + + MMARVALID + no description available + 7 + 1 + read-write + + + MMARVALID_0 + value in MMAR is not a valid fault address + 0 + + + MMARVALID_1 + MMAR holds a valid fault address + 0x1 + + + + + IBUSERR + no description available + 8 + 1 + read-write + + + IBUSERR_0 + no instruction bus error + 0 + + + IBUSERR_1 + instruction bus error + 0x1 + + + + + PRECISERR + no description available + 9 + 1 + read-write + + + PRECISERR_0 + no precise data bus error + 0 + + + PRECISERR_1 + a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault + 0x1 + + + + + IMPRECISERR + no description available + 10 + 1 + read-write + + + IMPRECISERR_0 + no imprecise data bus error + 0 + + + IMPRECISERR_1 + a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error + 0x1 + + + + + UNSTKERR + no description available + 11 + 1 + read-write + + + UNSTKERR_0 + no unstacking fault + 0 + + + UNSTKERR_1 + unstack for an exception return has caused one or more BusFaults + 0x1 + + + + + STKERR + no description available + 12 + 1 + read-write + + + STKERR_0 + no stacking fault + 0 + + + STKERR_1 + stacking for an exception entry has caused one or more BusFaults + 0x1 + + + + + LSPERR + no description available + 13 + 1 + read-write + + + LSPERR_0 + No bus fault occurred during floating-point lazy state preservation + 0 + + + LSPERR_1 + A bus fault occurred during floating-point lazy state preservation + 0x1 + + + + + BFARVALID + no description available + 15 + 1 + read-write + + + BFARVALID_0 + value in BFAR is not a valid fault address + 0 + + + BFARVALID_1 + BFAR holds a valid fault address + 0x1 + + + + + UNDEFINSTR + no description available + 16 + 1 + read-write + + + UNDEFINSTR_0 + no undefined instruction UsageFault + 0 + + + UNDEFINSTR_1 + the processor has attempted to execute an undefined instruction + 0x1 + + + + + INVSTATE + no description available + 17 + 1 + read-write + + + INVSTATE_0 + no invalid state UsageFault + 0 + + + INVSTATE_1 + the processor has attempted to execute an instruction that makes illegal use of the EPSR + 0x1 + + + + + INVPC + no description available + 18 + 1 + read-write + + + INVPC_0 + no invalid PC load UsageFault + 0 + + + INVPC_1 + the processor has attempted an illegal load of EXC_RETURN to the PC + 0x1 + + + + + NOCP + no description available + 19 + 1 + read-write + + + NOCP_0 + no UsageFault caused by attempting to access a coprocessor + 0 + + + NOCP_1 + the processor has attempted to access a coprocessor + 0x1 + + + + + UNALIGNED + no description available + 24 + 1 + read-write + + + UNALIGNED_0 + no unaligned access fault, or unaligned access trapping not enabled + 0 + + + UNALIGNED_1 + the processor has made an unaligned memory access + 0x1 + + + + + DIVBYZERO + no description available + 25 + 1 + read-write + + + DIVBYZERO_0 + no divide by zero fault, or divide by zero trapping not enabled + 0 + + + DIVBYZERO_1 + the processor has executed an SDIV or UDIV instruction with a divisor of 0 + 0x1 + + + + + + + HFSR + HardFault Status register + 0xD2C + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTTBL + no description available + 1 + 1 + read-write + + + VECTTBL_0 + no BusFault on vector table read + 0 + + + VECTTBL_1 + BusFault on vector table read + 0x1 + + + + + FORCED + no description available + 30 + 1 + read-write + + + FORCED_0 + no forced HardFault + 0 + + + FORCED_1 + forced HardFault + 0x1 + + + + + DEBUGEVT + no description available + 31 + 1 + read-write + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HALTED + no description available + 0 + 1 + read-write + + + HALTED_0 + No active halt request debug event + 0 + + + HALTED_1 + Halt request debug event active + 0x1 + + + + + BKPT + no description available + 1 + 1 + read-write + + + BKPT_0 + No current breakpoint debug event + 0 + + + BKPT_1 + At least one current breakpoint debug event + 0x1 + + + + + DWTTRAP + no description available + 2 + 1 + read-write + + + DWTTRAP_0 + No current debug events generated by the DWT + 0 + + + DWTTRAP_1 + At least one current debug event generated by the DWT + 0x1 + + + + + VCATCH + no description available + 3 + 1 + read-write + + + VCATCH_0 + No Vector catch triggered + 0 + + + VCATCH_1 + Vector catch triggered + 0x1 + + + + + EXTERNAL + no description available + 4 + 1 + read-write + + + EXTERNAL_0 + No EDBGRQ debug event + 0 + + + EXTERNAL_1 + EDBGRQ debug event + 0x1 + + + + + + + MMFAR + MemManage Address Register + 0xD34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of MemManage fault location + 0 + 32 + read-write + + + + + BFAR + BusFault Address Register + 0xD38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of the BusFault location + 0 + 32 + read-write + + + + + AFSR + Auxiliary Fault Status Register + 0xD3C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUXFAULT + Latched version of the AUXFAULT inputs + 0 + 32 + read-write + + + + + CPACR + Coprocessor Access Control Register + 0xD88 + 32 + read-write + 0 + 0xFFFFFFFF + + + CP10 + Access privileges for coprocessor 10. + 20 + 2 + read-write + + + CP10_0 + Access denied. Any attempted access generates a NOCP UsageFault + 0 + + + CP10_1 + Privileged access only. An unprivileged access generates a NOCP fault. + 0x1 + + + CP10_3 + Full access. + 0x3 + + + + + CP11 + Access privileges for coprocessor 11. + 22 + 2 + read-write + + + CP11_0 + Access denied. Any attempted access generates a NOCP UsageFault + 0 + + + CP11_1 + Privileged access only. An unprivileged access generates a NOCP fault. + 0x1 + + + CP11_3 + Full access. + 0x3 + + + + + + + FPCCR + Floating-point Context Control Register + 0xF34 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + LSPACT + Lazy state preservation. + 0 + 1 + read-write + + + LSPACT_0 + Lazy state preservation is not active. + 0 + + + LSPACT_1 + Lazy state preservation is active. floating-point stack frame has been allocated but saving state to it has been deferred. + 0x1 + + + + + USER + Privilege level when the floating-point stack frame was allocated. + 1 + 1 + read-write + + + USER_0 + Privilege level was not user when the floating-point stack frame was allocated. + 0 + + + USER_1 + Privilege level was user when the floating-point stack frame was allocated. + 0x1 + + + + + THREAD + Mode when the floating-point stack frame was allocated. + 3 + 1 + read-write + + + THREAD_0 + Mode was not Thread Mode when the floating-point stack frame was allocated. + 0 + + + THREAD_1 + Mode was Thread Mode when the floating-point stack frame was allocated. + 0x1 + + + + + HFRDY + Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated. + 4 + 1 + read-write + + + HFRDY_0 + Priority did not permit setting the HardFault handler to the pending state when the floating-point stack frame was allocated. + 0 + + + HFRDY_1 + Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. + 0x1 + + + + + MMRDY + Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated. + 5 + 1 + read-write + + + MMRDY_0 + MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated. + 0 + + + MMRDY_1 + MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated. + 0x1 + + + + + BFRDY + Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated. + 6 + 1 + read-write + + + BFRDY_0 + BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated. + 0 + + + BFRDY_1 + BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated. + 0x1 + + + + + MONRDY + Permission to set the MON_PEND when the floating-point stack frame was allocated. + 8 + 1 + read-write + + + MONRDY_0 + DebugMonitor is disabled or priority did not permit setting MON_PEND when the floating-point stack frame was allocated. + 0 + + + MONRDY_1 + DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated. + 0x1 + + + + + LSPEN + Lazy state preservation for floating-point context. + 30 + 1 + read-write + + + LSPEN_0 + Disable automatic lazy state preservation for floating-point context. + 0 + + + LSPEN_1 + Enable automatic lazy state preservation for floating-point context. + 0x1 + + + + + ASPEN + Enables CONTROL2 setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit. + 31 + 1 + read-write + + + ASPEN_0 + Disable CONTROL2 setting on execution of a floating-point instruction. + 0 + + + ASPEN_1 + Enable CONTROL2 setting on execution of a floating-point instruction. + 0x1 + + + + + + + FPCAR + Floating-point Context Address Register + 0xF38 + 32 + read-write + 0 + 0 + + + ADDRESS + The location of the unpopulated floating-point register space allocated on an exception stack frame. + 3 + 29 + read-write + + + + + FPDSCR + Floating-point Default Status Control Register + 0xF3C + 32 + read-write + 0 + 0xFFFFFFFF + + + RMode + Default value for FPSCR.RMode (Rounding Mode control field). + 22 + 2 + read-write + + + RMode_0 + Round to Nearest (RN) mode + 0 + + + RMode_1 + Round towards Plus Infinity (RP) mode. + 0x1 + + + RMode_2 + Round towards Minus Infinity (RM) mode. + 0x2 + + + RMode_3 + Round towards Zero (RZ) mode. + 0x3 + + + + + FZ + Default value for FPSCR.FZ (Flush-to-zero mode control bit). + 24 + 1 + read-write + + + FZ_0 + Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. + 0 + + + FZ_1 + Flush-to-zero mode enabled. + 0x1 + + + + + DN + Default value for FPSCR.DN (Default NaN mode control bit). + 25 + 1 + read-write + + + DN_0 + NaN operands propagate through to the output of a floating-point operation. + 0 + + + DN_1 + Any operation involving one or more NaNs returns the Default NaN. + 0x1 + + + + + AHP + Default value for FPSCR.AHP (Alternative half-precision control bit). + 26 + 1 + read-write + + + AHP_0 + IEEE half-precision format selected. + 0 + + + AHP_1 + Alternative half-precision format selected. + 0x1 + + + + + + + + + SysTick + System timer + SYSTICK + SYST_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + ENABLE + no description available + 0 + 1 + read-write + + + ENABLE_0 + counter disabled + 0 + + + ENABLE_1 + counter enabled + 0x1 + + + + + TICKINT + no description available + 1 + 1 + read-write + + + TICKINT_0 + counting down to 0 does not assert the SysTick exception request + 0 + + + TICKINT_1 + counting down to 0 asserts the SysTick exception request + 0x1 + + + + + CLKSOURCE + no description available + 2 + 1 + read-write + + + CLKSOURCE_0 + external clock + 0 + + + CLKSOURCE_1 + processor clock + 0x1 + + + + + COUNTFLAG + no description available + 16 + 1 + read-write + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + read-write + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + read-write + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0x80000000 + 0xFFFFFFFF + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + read-only + + + SKEW + no description available + 30 + 1 + read-only + + + SKEW_0 + 10ms calibration value is exact + 0 + + + SKEW_1 + 10ms calibration value is inexact, because of the clock frequency + 0x1 + + + + + NOREF + no description available + 31 + 1 + read-only + + + NOREF_0 + The reference clock is provided + 0 + + + NOREF_1 + The reference clock is not provided + 0x1 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + 0xE000E100 + + 0 + 0xE04 + registers + + + + NVICISER0 + Interrupt Set Enable Register n + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + + + + + NVICISER1 + Interrupt Set Enable Register n + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + + + + + NVICISER2 + Interrupt Set Enable Register n + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + + + + + NVICISER3 + Interrupt Set Enable Register n + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + + + + + NVICICER0 + Interrupt Clear Enable Register n + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + + + + + NVICICER1 + Interrupt Clear Enable Register n + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + + + + + NVICICER2 + Interrupt Clear Enable Register n + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + + + + + NVICICER3 + Interrupt Clear Enable Register n + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + + + + + NVICISPR0 + Interrupt Set Pending Register n + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + + + + + NVICISPR1 + Interrupt Set Pending Register n + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + + + + + NVICISPR2 + Interrupt Set Pending Register n + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + + + + + NVICISPR3 + Interrupt Set Pending Register n + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + + + + + NVICICPR0 + Interrupt Clear Pending Register n + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + + + + + NVICICPR1 + Interrupt Clear Pending Register n + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + + + + + NVICICPR2 + Interrupt Clear Pending Register n + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + + + + + NVICICPR3 + Interrupt Clear Pending Register n + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + + + + + NVICIABR0 + Interrupt Active bit Register n + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR1 + Interrupt Active bit Register n + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR2 + Interrupt Active bit Register n + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR3 + Interrupt Active bit Register n + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIP0 + Interrupt Priority Register n + 0x300 + 8 + read-write + 0 + 0xFF + + + PRI0 + Priority of interrupt 0 + 0 + 8 + read-write + + + + + NVICIP1 + Interrupt Priority Register n + 0x301 + 8 + read-write + 0 + 0xFF + + + PRI1 + Priority of interrupt 1 + 0 + 8 + read-write + + + + + NVICIP2 + Interrupt Priority Register n + 0x302 + 8 + read-write + 0 + 0xFF + + + PRI2 + Priority of interrupt 2 + 0 + 8 + read-write + + + + + NVICIP3 + Interrupt Priority Register n + 0x303 + 8 + read-write + 0 + 0xFF + + + PRI3 + Priority of interrupt 3 + 0 + 8 + read-write + + + + + NVICIP4 + Interrupt Priority Register n + 0x304 + 8 + read-write + 0 + 0xFF + + + PRI4 + Priority of interrupt 4 + 0 + 8 + read-write + + + + + NVICIP5 + Interrupt Priority Register n + 0x305 + 8 + read-write + 0 + 0xFF + + + PRI5 + Priority of interrupt 5 + 0 + 8 + read-write + + + + + NVICIP6 + Interrupt Priority Register n + 0x306 + 8 + read-write + 0 + 0xFF + + + PRI6 + Priority of interrupt 6 + 0 + 8 + read-write + + + + + NVICIP7 + Interrupt Priority Register n + 0x307 + 8 + read-write + 0 + 0xFF + + + PRI7 + Priority of interrupt 7 + 0 + 8 + read-write + + + + + NVICIP8 + Interrupt Priority Register n + 0x308 + 8 + read-write + 0 + 0xFF + + + PRI8 + Priority of interrupt 8 + 0 + 8 + read-write + + + + + NVICIP9 + Interrupt Priority Register n + 0x309 + 8 + read-write + 0 + 0xFF + + + PRI9 + Priority of interrupt 9 + 0 + 8 + read-write + + + + + NVICIP10 + Interrupt Priority Register n + 0x30A + 8 + read-write + 0 + 0xFF + + + PRI10 + Priority of interrupt 10 + 0 + 8 + read-write + + + + + NVICIP11 + Interrupt Priority Register n + 0x30B + 8 + read-write + 0 + 0xFF + + + PRI11 + Priority of interrupt 11 + 0 + 8 + read-write + + + + + NVICIP12 + Interrupt Priority Register n + 0x30C + 8 + read-write + 0 + 0xFF + + + PRI12 + Priority of interrupt 12 + 0 + 8 + read-write + + + + + NVICIP13 + Interrupt Priority Register n + 0x30D + 8 + read-write + 0 + 0xFF + + + PRI13 + Priority of interrupt 13 + 0 + 8 + read-write + + + + + NVICIP14 + Interrupt Priority Register n + 0x30E + 8 + read-write + 0 + 0xFF + + + PRI14 + Priority of interrupt 14 + 0 + 8 + read-write + + + + + NVICIP15 + Interrupt Priority Register n + 0x30F + 8 + read-write + 0 + 0xFF + + + PRI15 + Priority of interrupt 15 + 0 + 8 + read-write + + + + + NVICIP16 + Interrupt Priority Register n + 0x310 + 8 + read-write + 0 + 0xFF + + + PRI16 + Priority of interrupt 16 + 0 + 8 + read-write + + + + + NVICIP17 + Interrupt Priority Register n + 0x311 + 8 + read-write + 0 + 0xFF + + + PRI17 + Priority of interrupt 17 + 0 + 8 + read-write + + + + + NVICIP18 + Interrupt Priority Register n + 0x312 + 8 + read-write + 0 + 0xFF + + + PRI18 + Priority of interrupt 18 + 0 + 8 + read-write + + + + + NVICIP19 + Interrupt Priority Register n + 0x313 + 8 + read-write + 0 + 0xFF + + + PRI19 + Priority of interrupt 19 + 0 + 8 + read-write + + + + + NVICIP20 + Interrupt Priority Register n + 0x314 + 8 + read-write + 0 + 0xFF + + + PRI20 + Priority of interrupt 20 + 0 + 8 + read-write + + + + + NVICIP21 + Interrupt Priority Register n + 0x315 + 8 + read-write + 0 + 0xFF + + + PRI21 + Priority of interrupt 21 + 0 + 8 + read-write + + + + + NVICIP22 + Interrupt Priority Register n + 0x316 + 8 + read-write + 0 + 0xFF + + + PRI22 + Priority of interrupt 22 + 0 + 8 + read-write + + + + + NVICIP23 + Interrupt Priority Register n + 0x317 + 8 + read-write + 0 + 0xFF + + + PRI23 + Priority of interrupt 23 + 0 + 8 + read-write + + + + + NVICIP24 + Interrupt Priority Register n + 0x318 + 8 + read-write + 0 + 0xFF + + + PRI24 + Priority of interrupt 24 + 0 + 8 + read-write + + + + + NVICIP25 + Interrupt Priority Register n + 0x319 + 8 + read-write + 0 + 0xFF + + + PRI25 + Priority of interrupt 25 + 0 + 8 + read-write + + + + + NVICIP26 + Interrupt Priority Register n + 0x31A + 8 + read-write + 0 + 0xFF + + + PRI26 + Priority of interrupt 26 + 0 + 8 + read-write + + + + + NVICIP27 + Interrupt Priority Register n + 0x31B + 8 + read-write + 0 + 0xFF + + + PRI27 + Priority of interrupt 27 + 0 + 8 + read-write + + + + + NVICIP28 + Interrupt Priority Register n + 0x31C + 8 + read-write + 0 + 0xFF + + + PRI28 + Priority of interrupt 28 + 0 + 8 + read-write + + + + + NVICIP29 + Interrupt Priority Register n + 0x31D + 8 + read-write + 0 + 0xFF + + + PRI29 + Priority of interrupt 29 + 0 + 8 + read-write + + + + + NVICIP30 + Interrupt Priority Register n + 0x31E + 8 + read-write + 0 + 0xFF + + + PRI30 + Priority of interrupt 30 + 0 + 8 + read-write + + + + + NVICIP31 + Interrupt Priority Register n + 0x31F + 8 + read-write + 0 + 0xFF + + + PRI31 + Priority of interrupt 31 + 0 + 8 + read-write + + + + + NVICIP32 + Interrupt Priority Register n + 0x320 + 8 + read-write + 0 + 0xFF + + + PRI32 + Priority of interrupt 32 + 0 + 8 + read-write + + + + + NVICIP33 + Interrupt Priority Register n + 0x321 + 8 + read-write + 0 + 0xFF + + + PRI33 + Priority of interrupt 33 + 0 + 8 + read-write + + + + + NVICIP34 + Interrupt Priority Register n + 0x322 + 8 + read-write + 0 + 0xFF + + + PRI34 + Priority of interrupt 34 + 0 + 8 + read-write + + + + + NVICIP35 + Interrupt Priority Register n + 0x323 + 8 + read-write + 0 + 0xFF + + + PRI35 + Priority of interrupt 35 + 0 + 8 + read-write + + + + + NVICIP36 + Interrupt Priority Register n + 0x324 + 8 + read-write + 0 + 0xFF + + + PRI36 + Priority of interrupt 36 + 0 + 8 + read-write + + + + + NVICIP37 + Interrupt Priority Register n + 0x325 + 8 + read-write + 0 + 0xFF + + + PRI37 + Priority of interrupt 37 + 0 + 8 + read-write + + + + + NVICIP38 + Interrupt Priority Register n + 0x326 + 8 + read-write + 0 + 0xFF + + + PRI38 + Priority of interrupt 38 + 0 + 8 + read-write + + + + + NVICIP39 + Interrupt Priority Register n + 0x327 + 8 + read-write + 0 + 0xFF + + + PRI39 + Priority of interrupt 39 + 0 + 8 + read-write + + + + + NVICIP40 + Interrupt Priority Register n + 0x328 + 8 + read-write + 0 + 0xFF + + + PRI40 + Priority of interrupt 40 + 0 + 8 + read-write + + + + + NVICIP41 + Interrupt Priority Register n + 0x329 + 8 + read-write + 0 + 0xFF + + + PRI41 + Priority of interrupt 41 + 0 + 8 + read-write + + + + + NVICIP42 + Interrupt Priority Register n + 0x32A + 8 + read-write + 0 + 0xFF + + + PRI42 + Priority of interrupt 42 + 0 + 8 + read-write + + + + + NVICIP43 + Interrupt Priority Register n + 0x32B + 8 + read-write + 0 + 0xFF + + + PRI43 + Priority of interrupt 43 + 0 + 8 + read-write + + + + + NVICIP44 + Interrupt Priority Register n + 0x32C + 8 + read-write + 0 + 0xFF + + + PRI44 + Priority of interrupt 44 + 0 + 8 + read-write + + + + + NVICIP45 + Interrupt Priority Register n + 0x32D + 8 + read-write + 0 + 0xFF + + + PRI45 + Priority of interrupt 45 + 0 + 8 + read-write + + + + + NVICIP46 + Interrupt Priority Register n + 0x32E + 8 + read-write + 0 + 0xFF + + + PRI46 + Priority of interrupt 46 + 0 + 8 + read-write + + + + + NVICIP47 + Interrupt Priority Register n + 0x32F + 8 + read-write + 0 + 0xFF + + + PRI47 + Priority of interrupt 47 + 0 + 8 + read-write + + + + + NVICIP48 + Interrupt Priority Register n + 0x330 + 8 + read-write + 0 + 0xFF + + + PRI48 + Priority of interrupt 48 + 0 + 8 + read-write + + + + + NVICIP49 + Interrupt Priority Register n + 0x331 + 8 + read-write + 0 + 0xFF + + + PRI49 + Priority of interrupt 49 + 0 + 8 + read-write + + + + + NVICIP50 + Interrupt Priority Register n + 0x332 + 8 + read-write + 0 + 0xFF + + + PRI50 + Priority of interrupt 50 + 0 + 8 + read-write + + + + + NVICIP51 + Interrupt Priority Register n + 0x333 + 8 + read-write + 0 + 0xFF + + + PRI51 + Priority of interrupt 51 + 0 + 8 + read-write + + + + + NVICIP52 + Interrupt Priority Register n + 0x334 + 8 + read-write + 0 + 0xFF + + + PRI52 + Priority of interrupt 52 + 0 + 8 + read-write + + + + + NVICIP53 + Interrupt Priority Register n + 0x335 + 8 + read-write + 0 + 0xFF + + + PRI53 + Priority of interrupt 53 + 0 + 8 + read-write + + + + + NVICIP54 + Interrupt Priority Register n + 0x336 + 8 + read-write + 0 + 0xFF + + + PRI54 + Priority of interrupt 54 + 0 + 8 + read-write + + + + + NVICIP55 + Interrupt Priority Register n + 0x337 + 8 + read-write + 0 + 0xFF + + + PRI55 + Priority of interrupt 55 + 0 + 8 + read-write + + + + + NVICIP56 + Interrupt Priority Register n + 0x338 + 8 + read-write + 0 + 0xFF + + + PRI56 + Priority of interrupt 56 + 0 + 8 + read-write + + + + + NVICIP57 + Interrupt Priority Register n + 0x339 + 8 + read-write + 0 + 0xFF + + + PRI57 + Priority of interrupt 57 + 0 + 8 + read-write + + + + + NVICIP58 + Interrupt Priority Register n + 0x33A + 8 + read-write + 0 + 0xFF + + + PRI58 + Priority of interrupt 58 + 0 + 8 + read-write + + + + + NVICIP59 + Interrupt Priority Register n + 0x33B + 8 + read-write + 0 + 0xFF + + + PRI59 + Priority of interrupt 59 + 0 + 8 + read-write + + + + + NVICIP60 + Interrupt Priority Register n + 0x33C + 8 + read-write + 0 + 0xFF + + + PRI60 + Priority of interrupt 60 + 0 + 8 + read-write + + + + + NVICIP61 + Interrupt Priority Register n + 0x33D + 8 + read-write + 0 + 0xFF + + + PRI61 + Priority of interrupt 61 + 0 + 8 + read-write + + + + + NVICIP62 + Interrupt Priority Register n + 0x33E + 8 + read-write + 0 + 0xFF + + + PRI62 + Priority of interrupt 62 + 0 + 8 + read-write + + + + + NVICIP63 + Interrupt Priority Register n + 0x33F + 8 + read-write + 0 + 0xFF + + + PRI63 + Priority of interrupt 63 + 0 + 8 + read-write + + + + + NVICIP64 + Interrupt Priority Register n + 0x340 + 8 + read-write + 0 + 0xFF + + + PRI64 + Priority of interrupt 64 + 0 + 8 + read-write + + + + + NVICIP65 + Interrupt Priority Register n + 0x341 + 8 + read-write + 0 + 0xFF + + + PRI65 + Priority of interrupt 65 + 0 + 8 + read-write + + + + + NVICIP66 + Interrupt Priority Register n + 0x342 + 8 + read-write + 0 + 0xFF + + + PRI66 + Priority of interrupt 66 + 0 + 8 + read-write + + + + + NVICIP67 + Interrupt Priority Register n + 0x343 + 8 + read-write + 0 + 0xFF + + + PRI67 + Priority of interrupt 67 + 0 + 8 + read-write + + + + + NVICIP68 + Interrupt Priority Register n + 0x344 + 8 + read-write + 0 + 0xFF + + + PRI68 + Priority of interrupt 68 + 0 + 8 + read-write + + + + + NVICIP69 + Interrupt Priority Register n + 0x345 + 8 + read-write + 0 + 0xFF + + + PRI69 + Priority of interrupt 69 + 0 + 8 + read-write + + + + + NVICIP70 + Interrupt Priority Register n + 0x346 + 8 + read-write + 0 + 0xFF + + + PRI70 + Priority of interrupt 70 + 0 + 8 + read-write + + + + + NVICIP71 + Interrupt Priority Register n + 0x347 + 8 + read-write + 0 + 0xFF + + + PRI71 + Priority of interrupt 71 + 0 + 8 + read-write + + + + + NVICIP72 + Interrupt Priority Register n + 0x348 + 8 + read-write + 0 + 0xFF + + + PRI72 + Priority of interrupt 72 + 0 + 8 + read-write + + + + + NVICIP73 + Interrupt Priority Register n + 0x349 + 8 + read-write + 0 + 0xFF + + + PRI73 + Priority of interrupt 73 + 0 + 8 + read-write + + + + + NVICIP74 + Interrupt Priority Register n + 0x34A + 8 + read-write + 0 + 0xFF + + + PRI74 + Priority of interrupt 74 + 0 + 8 + read-write + + + + + NVICIP75 + Interrupt Priority Register n + 0x34B + 8 + read-write + 0 + 0xFF + + + PRI75 + Priority of interrupt 75 + 0 + 8 + read-write + + + + + NVICIP76 + Interrupt Priority Register n + 0x34C + 8 + read-write + 0 + 0xFF + + + PRI76 + Priority of interrupt 76 + 0 + 8 + read-write + + + + + NVICIP77 + Interrupt Priority Register n + 0x34D + 8 + read-write + 0 + 0xFF + + + PRI77 + Priority of interrupt 77 + 0 + 8 + read-write + + + + + NVICIP78 + Interrupt Priority Register n + 0x34E + 8 + read-write + 0 + 0xFF + + + PRI78 + Priority of interrupt 78 + 0 + 8 + read-write + + + + + NVICIP79 + Interrupt Priority Register n + 0x34F + 8 + read-write + 0 + 0xFF + + + PRI79 + Priority of interrupt 79 + 0 + 8 + read-write + + + + + NVICIP80 + Interrupt Priority Register n + 0x350 + 8 + read-write + 0 + 0xFF + + + PRI80 + Priority of interrupt 80 + 0 + 8 + read-write + + + + + NVICIP81 + Interrupt Priority Register n + 0x351 + 8 + read-write + 0 + 0xFF + + + PRI81 + Priority of interrupt 81 + 0 + 8 + read-write + + + + + NVICIP82 + Interrupt Priority Register n + 0x352 + 8 + read-write + 0 + 0xFF + + + PRI82 + Priority of interrupt 82 + 0 + 8 + read-write + + + + + NVICIP83 + Interrupt Priority Register n + 0x353 + 8 + read-write + 0 + 0xFF + + + PRI83 + Priority of interrupt 83 + 0 + 8 + read-write + + + + + NVICIP84 + Interrupt Priority Register n + 0x354 + 8 + read-write + 0 + 0xFF + + + PRI84 + Priority of interrupt 84 + 0 + 8 + read-write + + + + + NVICIP85 + Interrupt Priority Register n + 0x355 + 8 + read-write + 0 + 0xFF + + + PRI85 + Priority of interrupt 85 + 0 + 8 + read-write + + + + + NVICIP86 + Interrupt Priority Register n + 0x356 + 8 + read-write + 0 + 0xFF + + + PRI86 + Priority of interrupt 86 + 0 + 8 + read-write + + + + + NVICIP87 + Interrupt Priority Register n + 0x357 + 8 + read-write + 0 + 0xFF + + + PRI87 + Priority of interrupt 87 + 0 + 8 + read-write + + + + + NVICIP88 + Interrupt Priority Register n + 0x358 + 8 + read-write + 0 + 0xFF + + + PRI88 + Priority of interrupt 88 + 0 + 8 + read-write + + + + + NVICIP89 + Interrupt Priority Register n + 0x359 + 8 + read-write + 0 + 0xFF + + + PRI89 + Priority of interrupt 89 + 0 + 8 + read-write + + + + + NVICIP90 + Interrupt Priority Register n + 0x35A + 8 + read-write + 0 + 0xFF + + + PRI90 + Priority of interrupt 90 + 0 + 8 + read-write + + + + + NVICIP91 + Interrupt Priority Register n + 0x35B + 8 + read-write + 0 + 0xFF + + + PRI91 + Priority of interrupt 91 + 0 + 8 + read-write + + + + + NVICIP92 + Interrupt Priority Register n + 0x35C + 8 + read-write + 0 + 0xFF + + + PRI92 + Priority of interrupt 92 + 0 + 8 + read-write + + + + + NVICIP93 + Interrupt Priority Register n + 0x35D + 8 + read-write + 0 + 0xFF + + + PRI93 + Priority of interrupt 93 + 0 + 8 + read-write + + + + + NVICIP94 + Interrupt Priority Register n + 0x35E + 8 + read-write + 0 + 0xFF + + + PRI94 + Priority of interrupt 94 + 0 + 8 + read-write + + + + + NVICIP95 + Interrupt Priority Register n + 0x35F + 8 + read-write + 0 + 0xFF + + + PRI95 + Priority of interrupt 95 + 0 + 8 + read-write + + + + + NVICIP96 + Interrupt Priority Register n + 0x360 + 8 + read-write + 0 + 0xFF + + + PRI96 + Priority of interrupt 96 + 0 + 8 + read-write + + + + + NVICIP97 + Interrupt Priority Register n + 0x361 + 8 + read-write + 0 + 0xFF + + + PRI97 + Priority of interrupt 97 + 0 + 8 + read-write + + + + + NVICIP98 + Interrupt Priority Register n + 0x362 + 8 + read-write + 0 + 0xFF + + + PRI98 + Priority of interrupt 98 + 0 + 8 + read-write + + + + + NVICIP99 + Interrupt Priority Register n + 0x363 + 8 + read-write + 0 + 0xFF + + + PRI99 + Priority of interrupt 99 + 0 + 8 + read-write + + + + + NVICIP100 + Interrupt Priority Register n + 0x364 + 8 + read-write + 0 + 0xFF + + + PRI100 + Priority of interrupt 100 + 0 + 8 + read-write + + + + + NVICIP101 + Interrupt Priority Register n + 0x365 + 8 + read-write + 0 + 0xFF + + + PRI101 + Priority of interrupt 101 + 0 + 8 + read-write + + + + + NVICIP102 + Interrupt Priority Register n + 0x366 + 8 + read-write + 0 + 0xFF + + + PRI102 + Priority of interrupt 102 + 0 + 8 + read-write + + + + + NVICIP103 + Interrupt Priority Register n + 0x367 + 8 + read-write + 0 + 0xFF + + + PRI103 + Priority of interrupt 103 + 0 + 8 + read-write + + + + + NVICIP104 + Interrupt Priority Register n + 0x368 + 8 + read-write + 0 + 0xFF + + + PRI104 + Priority of interrupt 104 + 0 + 8 + read-write + + + + + NVICIP105 + Interrupt Priority Register n + 0x369 + 8 + read-write + 0 + 0xFF + + + PRI105 + Priority of interrupt 105 + 0 + 8 + read-write + + + + + NVICSTIR + Software Trigger Interrupt Register + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTID + Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. + 0 + 9 + read-write + + + + + + + ETM + Embedded Trace Macrocell Registers + ETM + ETM + 0xE0041000 + + 0 + 0x1000 + registers + + + + CR + Main Control Register + 0 + 32 + read-write + 0x411 + 0xFFFFFFFF + + + ETMPD + ETM power down. This bit can be used by an implementation to control if the ETM is in a low power state. This bit must be cleared by the trace software tools at the beginning of a debug session. When this bit is set to 1, writes to some registers and fields might be ignored. + 0 + 1 + read-write + + + PS + Port size. The ETM-M4 has no influence over the external pins used for trace. These bits are implemented but not used. On an ETM reset these bits reset to 0b001. + 4 + 3 + read-write + + + SP + Stall processor. The FIFOFULL output can be used to stall the processor to prevent overflow. The FIFOFULL output is only enabled when the stall processor bit is set to 1. When the bit is 0 the FIFOFULL output remains LOW at all times and the FIFO overflows if there are too many trace packets. Trace resumes without corruption once the FIFO has drained, if overflow does occur. An ETM reset sets this bit to 0. + 7 + 1 + read-write + + + BO + Branch output. When set to 1 all branch addresses are output, even if the branch was because of a direct branch instruction. Setting this bit enables reconstruction of the program flow without having access to the memory image of the code being executed. When this bit is set to 1, more trace data is generated, and this may affect the performance of the trace system. Information about the execution of a branch is traced regardless of the state of this bit. An ETM reset sets this bit to 0. + 8 + 1 + read-write + + + DRC + Debug request control. When set to 1 and the trigger event occurs, the DBGRQ output is asserted until DBGACK is observed. This enables the ARM processor to be forced into Debug state. An ETM reset sets this bit to 0. + 9 + 1 + read-write + + + ETMP + ETM programming. This bit must be set to 1 at the start of the ETM programming sequence. Tracing is prevented while this bit is set to 1.On an ETM reset this bit is set to b1. + 10 + 1 + read-write + + + ETMPS + ETM port selection. This bit can be used to control other trace components in an implementation.This bit must be set by the trace software tools to ensure that trace output is enabled from this ETM.An ETM reset sets this bit to 0. + 11 + 1 + read-write + + + ETMPS_0 + ETMEN is LOW. + 0 + + + ETMPS_1 + ETMEN is HIGH. + 0x1 + + + + + PM2 + This bit is implemented but has no function.An ETM reset sets this bit to 0. + 13 + 1 + read-write + + + PM + These bits are implemented but have no function.An ETM reset sets these bits to 0. + 16 + 2 + read-write + + + PS3 + This bit is implemented but has no function.An ETM reset sets this bit to 0. + 21 + 1 + read-write + + + TE + When set, this bit enables timestamping. An ETM reset sets this bit to 0. + 28 + 1 + read-write + + + + + CCR + Configuration Code Register + 0x4 + 32 + read-only + 0x8C802000 + 0xFFFFFFFF + + + NumberOfAddressComparatorPairs + Number of address comparator pairs. The value of these bits is b0000, indicating that address comparator pairs are not implemented. + 0 + 4 + read-only + + + NDVC + Number of data value comparators. The value of these bits is b0000, indicating that data value comparators are not implemented. + 4 + 4 + read-only + + + NMMD + Number of memory map decoders. The value of these bits is b00000, indicating that memory map decoder inputs are not implemented. + 8 + 5 + read-only + + + NC + Number of counters. The value of these bits is b001, indicating that one counter is implemented. + 13 + 3 + read-only + + + SP + Sequencer present. The value of this bit is 0, indicating that the sequencer is not implemented. + 16 + 1 + read-only + + + NEI + Number of external inputs. The value of these bits is between b000 and b010, indicating the number of external inputs, from 0 to 2, implemented in the system. + 17 + 3 + read-only + + + NEO + Number of external outputs. The value of these bits is b000, indicating that no external outputs are supported. + 20 + 3 + read-only + + + FFLP + FIFOFULL logic present. The value of this bit is 1, indicating that FIFOFULL logic is present in the ETM. To use FIFOFULL the system must also support the function, as indicated by bit [8] of ETMSCR. + 23 + 1 + read-only + + + NCIDC + Number of Context ID comparators. The value of these bits is b00, indicating that Context ID comparators are notimplemented. + 24 + 2 + read-only + + + TSSBP + Trace start/stop block present. The value of this bit is 1, indicating that the Trace start/stop block is present. + 26 + 1 + read-only + + + CMA + Coprocessor and memory access. The value of this bit is 1, indicating that memory-mapped access to registers is supported. + 27 + 1 + read-only + + + ETMIDRP + The value of this bit is 1, indicating that the ETMIDR, register 0x79, is present and defines the ETM architecture version in use. + 31 + 1 + read-only + + + + + TRIGGER + Trigger Event Register + 0x8 + 32 + read-write + 0 + 0xFFFE0000 + + + TriggerEvent + Trigger event + 0 + 17 + read-write + + + + + SR + ETM Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFF0 + + + UOF + Untraced overflow flag. If set to 1, there is an overflow that has not yet been traced. This bit is cleared to 0 when either:- trace is restarted- the ETM Power Down bit, bit [0] of the ETM Control Register, 0x00, is set to 1.Note: Setting or clearing the ETM programming bit does not cause this bit to be cleared to 0. + 0 + 1 + read-only + + + Progbit + ETM programming bit value (Progbit). The current effective value of the ETM Programming bit (ETM Control Register bit [10]). Tou must wait for this bit to go to 1 before you start to program the ETM. + 1 + 1 + read-only + + + Status + Holds the current status of the trace start/stop resource. If set to 1, it indicates that a trace on address has been matched, without a corresponding trace off address match. + 2 + 1 + read-write + + + Trigger + Trigger bit. Set when the trigger occurs, and prevents the trigger from being output until the ETM is next programmed. + 3 + 1 + read-write + + + + + SCR + System Configuration Register + 0x14 + 32 + read-only + 0x20D09 + 0xFFFFFFFF + + + MaximumPortSize + Maximum ETM port size bits [2:0]. These bits are used in conjunction with bit [9]. The value of these bits is b001. + 0 + 3 + read-only + + + FIFOFULLsupported + FIFOFULL supported. The value of this bit is 1, indicating that FIFOFULL is supported. This bit is used in conjunction with bit [23] of the ETMCCR. + 8 + 1 + read-only + + + MaximumPortSize3 + Maximum ETM port size bit [3]. This bit is used in conjunction with bits [2:0]. Its value is 0.This has no effect on the TPIU trace port. + 9 + 1 + read-only + + + PortSizeSupported + Port size supported. This bit reads as 1 if the currently selected port size is supported. This has no effect on the TPIU trace port. + 10 + 1 + read-only + + + PortModeSupported + Port mode supported. This bit reads as 1 if the currently selected port mode is supported. This has no effect on the TPIU trace port. + 11 + 1 + read-only + + + N + These bits give the number of supported processors minus 1. The value of these bits is b000, indicating that there is only one processor connected. + 12 + 3 + read-only + + + NoFetchComparisons + No Fetch comparisons. The value of this bit is 1, indicating that fetch comparisons are not implemented. + 17 + 1 + read-only + + + + + EEVR + Trace Enable Event Register + 0x20 + 32 + read-write + 0 + 0 + + + TraceEnableEvent + Trace Enable event. + 0 + 17 + read-write + + + + + TECR1 + Trace Enable Control 1 Register + 0x24 + 32 + read-write + 0 + 0xFDFFFFFF + + + TraceControlEnable + Trace start/stop enable.The trace start/stop resource, resource 0x5F, is unaffected by the value of this bit. + 25 + 1 + read-write + + + TraceControlEnable_0 + Tracing is unaffected by the trace start/stop logic. + 0 + + + TraceControlEnable_1 + Tracing is controlled by the trace on and off addresses configured for the trace start/stop logic. + 0x1 + + + + + + + FFLR + FIFOFULL Level Register + 0x28 + 32 + read-write + 0 + 0 + + + FIFOFullLevel + FIFO full level. The number of bytes left in FIFO, below which the FIFOFULL or SupressData signal is asserted. For example, setting this value to 15 causes data trace suppression or processor stalling, if enabled, when there are less than 15 free bytes in the FIFO. + 0 + 8 + read-write + + + + + CNTRLDVR1 + Free-running counter reload value + 0x140 + 32 + read-write + 0 + 0 + + + IntitialCount + Initial count. + 0 + 16 + read-write + + + + + SYNCFR + Synchronization Frequency Register + 0x1E0 + 32 + read-only + 0x400 + 0xFFFFFFFF + + + SyncFrequency + Synchronization frequency. Default value is 1024. + 0 + 12 + read-only + + + + + IDR + ID Register + 0x1E4 + 32 + read-only + 0x4114F250 + 0xFFFFFFFF + + + ImplementationRevision + Implementation revision. The value of these bits is b0000, indicating implementation revision, 0. + 0 + 4 + read-only + + + MinorETMarchitectureVersion + Minor ETM architecture version. The value of these bits is 0b0101, indicating minor architecture version number 5. + 4 + 4 + read-only + + + MajorETMarchitectureVersion + Major ETM architecture version. The value of these bits is 0b0010, indicating major architecture version number 3, ETMv3. + 8 + 4 + read-only + + + ProcessorFamily + Processor family. The value of these bits is 0b1111, indicating that the processor family is not identified in this register. + 12 + 4 + read-only + + + LoadPCfirst + Load PC first. The value of this bit is 0, indicating that data tracing is not supported. + 16 + 1 + read-only + + + ThumbInstructionTracing + 32-bit Thumb instruction tracing. The value of this bit is 1, indicating that a 32-bit Thumb instruction is traced as a single instruction. + 18 + 1 + read-only + + + ThumbInstructionTracing_0 + A 32-bit Thumb instruction is traced as two instructions, and exceptions might occur between these two instructions. + 0 + + + ThumbInstructionTracing_1 + A 32-bit Thimb instruction is traced as a single instruction. + 0x1 + + + + + SecurityExtensionSupport + Security Extensions support. The value of this bit is 0, indicating that the ETM behaves as if the processor is in Secure state at all times. + 19 + 1 + read-only + + + SecurityExtensionSupport_0 + The ETM behaves as if the processor is in Secure state at all times. + 0 + + + SecurityExtensionSupport_1 + The ARM architecture Security Extensions are implemented by the processor. + 0x1 + + + + + BranchPacketEncoding + Branch packet encoding. The value of this bit is 1, indicating that alternative branch packet encoding is implemented. + 20 + 1 + read-only + + + BranchPacketEncoding_0 + The ETM implements the original branch packet encoding. + 0 + + + BranchPacketEncoding_1 + The ETM implements the alternative branch packet encoding. + 0x1 + + + + + ImplementorCode + Implementor code. These bits identify ARM as the implementor of the processor. The value of these bits is 01000001. + 24 + 8 + read-only + + + + + CCER + Configuration Code Extension Register + 0x1E8 + 32 + read-only + 0x18541800 + 0xFFFFFFFF + + + ExtendedExternalInputSelectors + Extended external input selectors. The value of these bits is 0, indicating that extended external input selectors are not implemented. + 0 + 3 + read-only + + + ExtendedExternalInputBus + Extended external input bus. The value of these bits is 0, indicating that the extended external input bus is not implemented. + 3 + 8 + read-only + + + ReadableRegisters + Readable registers. The value of this bit is 1, indicating that all registers are readable. + 11 + 1 + read-only + + + DataAddressComparisons + Data address comparisons. The value of this bit is 1, indicating that data address comparisons are not supported. + 12 + 1 + read-only + + + InstrumentationResources + Instrumentation resources. The value of these bits is 0b000, indicating that no Instrumentation resources are supported. + 13 + 3 + read-only + + + EmbeddedICEwatchpointInputs + EmbeddedICE watchpoint inputs. The value of these bits is 0b0100, indicating that the number of EmbeddedICE watchpoint inputs implemented is four. These inputs come from the DWT. + 16 + 4 + read-only + + + TraceStartStopBlockUsesEmbeddedICEwatchpointInputs + Trace Start/Stop block uses EmbeddedICE watchpoint inputs. The value of this bit is 1, indicating that the Trace Start/Stop block uses the EmbeddedICE watchpoint inputs. + 20 + 1 + read-only + + + EmbeddedICEbehaviorControlImplemented + EmbeddedICE behavior control implemented. The value of this bit is 0, indicating that the ETMEIBCR is not implemented. + 21 + 1 + read-only + + + TimestampingImplemented + Timestamping implemented. This bit is set to 1, indicating that timestamping is implemented. + 22 + 1 + read-only + + + ReducedFunctionCounter + Reduced function counter. Set to 1 to indicate that Counter 1 is a reduced function counter. + 27 + 1 + read-only + + + TimestampEncoding + Timestamp encoding. Set to 1 to indicate that the timestamp is encoded as a natural binary number. + 28 + 1 + read-only + + + TimestampSize + Timestamp size. Set to 0 to indicate a size of 48 bits. + 29 + 1 + read-only + + + + + TESSEICR + TraceEnable Start/Stop EmbeddedICE Control Register + 0x1F0 + 32 + read-write + 0 + 0xFFF0FFF0 + + + StartResourceSelection + Start resource selection. Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable start resource. Bit [0] corresponds to input 1, bit [1] corresponds to input 2, bit [2] corresponds to input 3, and bit [3] corresponds to input 4. + 0 + 4 + read-write + + + StopResourceSelection + Stop resource selection. Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable stop resource. Bit [16] corresponds to input 1, bit [17] corresponds to input 2, bit [18] corresponds to input 3, and bit [19] corresponds to input 4. + 16 + 4 + read-write + + + + + TSEVR + Timestamp Event Register + 0x1F8 + 32 + read-write + 0 + 0 + + + TimestampEvent + Timestamp event. + 0 + 12 + read-write + + + + + TRACEIDR + CoreSight Trace ID Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + TraceID + Trace ID to output onto the trace bus.On an ETM reset this field is cleared to 0x00. + 0 + 7 + read-write + + + + + IDR2 + ETM ID Register 2 + 0x208 + 32 + read-only + 0 + 0xFFFFFFFF + + + PDSR + Device Power-Down Status Register + 0x314 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + ETMpoweredup + The value of this bit indicates whether you can access the ETM Trace Registers. The value of this bit is always 1, indicating that the ETM Trace Registers can be accessed. + 0 + 1 + read-only + + + + + _ITMISCIN + Integration Test Miscelaneous Inputs Register + 0xEE0 + 32 + read-only + 0 + 0xFFFFFFE0 + + + EXTIN + A read of these bits returns the value of the EXTIN[1:0] input pins. + 0 + 2 + read-only + + + COREHALT + A read of this bit returns the value of the COREHALT input pin. + 4 + 1 + read-only + + + + + _ITTRIGOUT + Integration Test Trigger Out Register + 0xEE8 + 32 + read-write + 0 + 0xFFFFFFFE + + + TRIGGER + A write to this bit sets the TRIGGER output. + 0 + 1 + write-only + + + + + _ITATBCTR2 + ETM Integration Test ATB Control 2 Register + 0xEF0 + 32 + read-only + 0 + 0xFFFFFFFE + + + ATREADY + A read of this bit returns the value of the ETM ATREADY input. + 0 + 1 + read-only + + + + + _ITATBCTR0 + ETM Integration Test ATB Control 0 Register + 0xEF8 + 32 + read-write + 0 + 0xFFFFFFFE + + + ATVALID + A write to this bit sets the value of the ETM ATVALID output. + 0 + 1 + write-only + + + + + ITCTRL + Integration Mode Control Register + 0xF00 + 32 + read-write + 0 + 0xFFFFFFFF + + + Mode + Enable integration mode. When this bit is set to 1, the device enters integration mode to enable Topology Detection or Integration Testing to be checked. On an ETM reset this bit is cleared to 0. + 0 + 1 + read-write + + + + + CLAIMSET + Claim Tag Set Register + 0xFA0 + 32 + read-write + 0 + 0 + + + CLAIMSET + A bit programmable register bank which sets the Claim Tag Value.Write 1 to set the bit in the claim tag. A read will return a logic 1 for all implemented locations. + 0 + 4 + read-write + + + + + CLAIMCLR + Claim Tag Clear Register + 0xFA4 + 32 + read-write + 0 + 0 + + + CLAIMCLR + A bit programmable register bank that is zero at reset.Write 1 to clear the bit in the claim tag. On reads, returns the current setting of the claim tag. + 0 + 4 + read-write + + + + + LAR + Lock Access Register + 0xFB0 + 32 + read-write + 0 + 0 + + + WriteAccessCode + Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access. + 0 + 32 + read-write + + + + + LSR + Lock Status Register + 0xFB4 + 32 + read-only + 0x1 + 0x5 + + + IMP + Lock mechanism is implemented. This bit always reads 1. + 0 + 1 + read-only + + + STATUS + Lock Status. This bit is HIGH when the device is locked, and LOW when unlocked. + 1 + 1 + read-only + + + STATUS_0 + Access permitted. + 0 + + + STATUS_1 + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + s8BIT + Access Lock Register size. This bit reads 0 to indicate a 32-bit register is present. + 2 + 1 + read-only + + + + + AUTHSTATUS + Authentication Status Register + 0xFB8 + 32 + read-only + 0 + 0xFFFFFF00 + + + NSID + Reads as b00, Non-secure invasive debug not supported by the ETM. + 0 + 2 + read-only + + + NSNID + Permission for Non-secure non-invasive debug. + 2 + 2 + read-only + + + NSNID_2 + Non-secure non-invasive debug disabled + 0x2 + + + NSNID_3 + Non-secure non-invasive debug enabled + 0x3 + + + + + SID + Reads as b00, Secure invasive debug not supported by the ETM. + 4 + 2 + read-only + + + SNID + Permission for Secure non-invasive debug. + 6 + 2 + read-only + + + + + DEVTYPE + CoreSight Device Type Register + 0xFCC + 32 + read-only + 0x13 + 0xFFFFFFFF + + + MajorType + Major Type and Class + 0 + 4 + read-only + + + MajorType_3 + Trace source + 0x3 + + + + + SubType + Sub Type + 4 + 4 + read-only + + + SubType_1 + Processor trace + 0x1 + + + + + + + PIDR4 + Peripheral Identification Register 4 + 0xFD0 + 32 + read-only + 0x4 + 0xFFFFFFFF + + + JEP106 + JEP106 continuation code. + 0 + 4 + read-only + + + c4KB + 4KB Count + 4 + 4 + read-only + + + + + PIDR5 + Peripheral Identification Register 5 + 0xFD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + PIDR6 + Peripheral Identification Register 6 + 0xFD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PIDR7 + Peripheral Identification Register 7 + 0xFDC + 32 + read-only + 0 + 0xFFFFFFFF + + + PIDR0 + Peripheral Identification Register 0 + 0xFE0 + 32 + read-only + 0x25 + 0xFFFFFFFF + + + PartNumber + Part Number [7:0] + 0 + 8 + read-only + + + + + PIDR1 + Peripheral Identification Register 1 + 0xFE4 + 32 + read-only + 0xB9 + 0xFFFFFFFF + + + PartNumber + Part Number [11:8] + 0 + 4 + read-only + + + JEP106_identity_code + JEP106 identity code [3:0] + 4 + 4 + read-only + + + + + PIDR2 + Peripheral Identification Register 2 + 0xFE8 + 32 + read-only + 0xB + 0xFFFFFFFF + + + JEP106_identity_code + JEP106 identity code [6:4] + 0 + 3 + read-only + + + Revision + Revision + 4 + 4 + read-only + + + + + PIDR3 + Peripheral Identification Register 3 + 0xFEC + 32 + read-only + 0 + 0xFFFFFFFF + + + CustomerModified + Customer Modified. + 0 + 4 + read-only + + + RevAnd + RevAnd + 4 + 4 + read-only + + + + + CIDR0 + Component Identification Register 0 + 0xFF0 + 32 + read-only + 0xD + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CIDR1 + Component Identification Register 1 + 0xFF4 + 32 + read-only + 0x90 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 4 + read-only + + + ComponentClass + Component class + 4 + 4 + read-only + + + ComponentClass_1 + ROM table. + 0x1 + + + ComponentClass_9 + CoreSight component. + 0x9 + + + ComponentClass_15 + PrimeCell of system component with no standardized register layout, for backward compatibility. + 0xF + + + + + + + CIDR2 + Component Identification Register 2 + 0xFF8 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CIDR3 + Component Identification Register 3 + 0xFFC + 32 + read-only + 0xB1 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + + + MCM + Core Platform Miscellaneous Control Module + MCM + MCM_ + 0xE0080000 + + 0 + 0x2C + registers + + + + PLASC + Crossbar Switch (AXBS) Slave Configuration + 0x8 + 16 + read-only + 0x2 + 0xFFFF + + + ASC + Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. + 0 + 8 + read-only + + + ASC_0 + A bus slave connection to AXBS input port n is absent + 0 + + + ASC_1 + A bus slave connection to AXBS input port n is present + 0x1 + + + + + + + PLAMC + Crossbar Switch (AXBS) Master Configuration + 0xA + 16 + read-only + 0x3 + 0xFFFF + + + AMC + Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. + 0 + 8 + read-only + + + AMC_0 + A bus master connection to AXBS input port n is absent + 0 + + + AMC_1 + A bus master connection to AXBS input port n is present + 0x1 + + + + + + + PLACR + Crossbar Switch (AXBS) Control Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + FADR + Fault address register + 0x20 + 32 + read-only + 0 + 0 + + + ADDRESS + Fault address + 0 + 32 + read-only + + + + + FATR + Fault attributes register + 0x24 + 32 + read-only + 0 + 0 + + + BEDA + Bus error access type + 0 + 1 + read-only + + + BEDA_0 + Instruction + 0 + + + BEDA_1 + Data + 0x1 + + + + + BEMD + Bus error privilege level + 1 + 1 + read-only + + + BEMD_0 + User mode + 0 + + + BEMD_1 + Supervisor/privileged mode + 0x1 + + + + + BESZ + Bus error size + 4 + 2 + read-only + + + BESZ_0 + 8-bit access + 0 + + + BESZ_1 + 16-bit access + 0x1 + + + BESZ_2 + 32-bit access + 0x2 + + + + + BEWT + Bus error write + 7 + 1 + read-only + + + BEWT_0 + Read access + 0 + + + BEWT_1 + Write access + 0x1 + + + + + BEMN + Bus error master number + 8 + 4 + read-only + + + BEOVR + Bus error overrun + 31 + 1 + read-only + + + BEOVR_0 + No bus error overrun + 0 + + + BEOVR_1 + Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error. + 0x1 + + + + + + + FDR + Fault data register + 0x28 + 32 + read-only + 0 + 0 + + + DATA + Fault data + 0 + 32 + read-only + + + + + + + LMEM + Local Memory Controller + LMEM + LMEM_ + 0xE0082000 + + 0 + 0x810 + registers + + + + PCCCR + Cache control register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENCACHE + Cache enable + 0 + 1 + read-write + + + ENCACHE_0 + Cache disabled + 0 + + + ENCACHE_1 + Cache enabled + 0x1 + + + + + ENWRBUF + Enable Write Buffer + 1 + 1 + read-write + + + ENWRBUF_0 + Write buffer disabled + 0 + + + ENWRBUF_1 + Write buffer enabled + 0x1 + + + + + PCCR2 + Forces all cacheable spaces to write through + 2 + 1 + read-write + + + PCCR3 + Forces no allocation on cache misses (must also have ACCR2 asserted) + 3 + 1 + read-write + + + INVW0 + Invalidate Way 0 + 24 + 1 + read-write + + + INVW0_0 + No operation + 0 + + + INVW0_1 + When setting the GO bit, invalidate all lines in way 0. + 0x1 + + + + + PUSHW0 + Push Way 0 + 25 + 1 + read-write + + + PUSHW0_0 + No operation + 0 + + + PUSHW0_1 + When setting the GO bit, push all modified lines in way 0 + 0x1 + + + + + INVW1 + Invalidate Way 1 + 26 + 1 + read-write + + + INVW1_0 + No operation + 0 + + + INVW1_1 + When setting the GO bit, invalidate all lines in way 1 + 0x1 + + + + + PUSHW1 + Push Way 1 + 27 + 1 + read-write + + + PUSHW1_0 + No operation + 0 + + + PUSHW1_1 + When setting the GO bit, push all modified lines in way 1 + 0x1 + + + + + GO + Initiate Cache Command + 31 + 1 + read-write + + + GO_0 + Write: no effect. Read: no cache command active. + 0 + + + GO_1 + Write: initiate command indicated by bits 27-24. Read: cache command active. + 0x1 + + + + + + + PCCLCR + Cache line control register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + LGO + Initiate Cache Line Command + 0 + 1 + read-write + + + LGO_0 + Write: no effect. Read: no line command active. + 0 + + + LGO_1 + Write: initiate line command indicated by bits 27-24. Read: line command active. + 0x1 + + + + + CACHEADDR + Cache address + 2 + 11 + read-write + + + WSEL + Way select + 14 + 1 + read-write + + + WSEL_0 + Way 0 + 0 + + + WSEL_1 + Way 1 + 0x1 + + + + + TDSEL + Tag/Data Select + 16 + 1 + read-write + + + TDSEL_0 + Data + 0 + + + TDSEL_1 + Tag + 0x1 + + + + + LCIVB + Line Command Initial Valid Bit + 20 + 1 + read-only + + + LCIMB + Line Command Initial Modified Bit + 21 + 1 + read-only + + + LCWAY + Line Command Way + 22 + 1 + read-only + + + LCMD + Line Command + 24 + 2 + read-write + + + LCMD_0 + Search and read or write + 0 + + + LCMD_1 + Invalidate + 0x1 + + + LCMD_2 + Push + 0x2 + + + LCMD_3 + Clear + 0x3 + + + + + LADSEL + Line Address Select + 26 + 1 + read-write + + + LADSEL_0 + Cache address + 0 + + + LADSEL_1 + Physical address + 0x1 + + + + + LACC + Line access type + 27 + 1 + read-write + + + LACC_0 + Read + 0 + + + LACC_1 + Write + 0x1 + + + + + + + PCCSAR + Cache search address register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + LGO + Initiate Cache Line Command + 0 + 1 + read-write + + + LGO_0 + Write: no effect. Read: no line command active. + 0 + + + LGO_1 + Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. + 0x1 + + + + + PHYADDR + Physical Address + 2 + 30 + read-write + + + + + PCCCVR + Cache read/write value register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Cache read/write Data + 0 + 32 + read-write + + + + + PSCCR + Cache control register + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENCACHE + Cache enable + 0 + 1 + read-write + + + ENCACHE_0 + Cache disabled + 0 + + + ENCACHE_1 + Cache enabled + 0x1 + + + + + ENWRBUF + Enable Write Buffer + 1 + 1 + read-write + + + ENWRBUF_0 + Write buffer disabled + 0 + + + ENWRBUF_1 + Write buffer enabled + 0x1 + + + + + INVW0 + Invalidate Way 0 + 24 + 1 + read-write + + + INVW0_0 + No operation + 0 + + + INVW0_1 + When setting the GO bit, invalidate all lines in way 0. + 0x1 + + + + + PUSHW0 + Push Way 0 + 25 + 1 + read-write + + + PUSHW0_0 + No operation + 0 + + + PUSHW0_1 + When setting the GO bit, push all modified lines in way 0 + 0x1 + + + + + INVW1 + Invalidate Way 1 + 26 + 1 + read-write + + + INVW1_0 + No operation + 0 + + + INVW1_1 + When setting the GO bit, invalidate all lines in way 1 + 0x1 + + + + + PUSHW1 + Push Way 1 + 27 + 1 + read-write + + + PUSHW1_0 + No operation + 0 + + + PUSHW1_1 + When setting the GO bit, push all modified lines in way 1 + 0x1 + + + + + GO + Initiate Cache Command + 31 + 1 + read-write + + + GO_0 + Write: no effect. Read: no cache command active. + 0 + + + GO_1 + Write: initiate command indicated by bits 27-24. Read: cache command active. + 0x1 + + + + + + + PSCLCR + Cache line control register + 0x804 + 32 + read-write + 0 + 0xFFFFFFFF + + + LGO + Initiate Cache Line Command + 0 + 1 + read-write + + + LGO_0 + Write: no effect. Read: no line command active. + 0 + + + LGO_1 + Write: initiate line command indicated by bits 27-24. Read: line command active. + 0x1 + + + + + CACHEADDR + Cache address + 2 + 11 + read-write + + + WSEL + Way select + 14 + 1 + read-write + + + WSEL_0 + Way 0 + 0 + + + WSEL_1 + Way 1 + 0x1 + + + + + TDSEL + Tag/Data Select + 16 + 1 + read-write + + + TDSEL_0 + Data + 0 + + + TDSEL_1 + Tag + 0x1 + + + + + LCIVB + Line Command Initial Valid Bit + 20 + 1 + read-only + + + LCIMB + Line Command Initial Modified Bit + 21 + 1 + read-only + + + LCWAY + Line Command Way + 22 + 1 + read-only + + + LCMD + Line Command + 24 + 2 + read-write + + + LCMD_0 + Search and read or write + 0 + + + LCMD_1 + Invalidate + 0x1 + + + LCMD_2 + Push + 0x2 + + + LCMD_3 + Clear + 0x3 + + + + + LADSEL + Line Address Select + 26 + 1 + read-write + + + LADSEL_0 + Cache address + 0 + + + LADSEL_1 + Physical address + 0x1 + + + + + LACC + Line access type + 27 + 1 + read-write + + + LACC_0 + Read + 0 + + + LACC_1 + Write + 0x1 + + + + + + + PSCSAR + Cache search address register + 0x808 + 32 + read-write + 0 + 0xFFFFFFFF + + + LGO + Initiate Cache Line Command + 0 + 1 + read-write + + + LGO_0 + Write: no effect. Read: no line command active. + 0 + + + LGO_1 + Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. + 0x1 + + + + + PHYADDR + Physical Address + 2 + 30 + read-write + + + + + PSCCVR + Cache read/write value register + 0x80C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Cache read/write Data + 0 + 32 + read-write + + + + + + + \ No newline at end of file diff --git a/devices/MIMX8MQ6/MIMX8MQ6_cm4_features.h b/devices/MIMX8MQ6/MIMX8MQ6_cm4_features.h new file mode 100644 index 000000000..c9d772e50 --- /dev/null +++ b/devices/MIMX8MQ6/MIMX8MQ6_cm4_features.h @@ -0,0 +1,402 @@ +/* +** ################################################################### +** Version: rev. 4.0, 2018-01-26 +** Build: b210601 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-06-02) +** Initial version. +** - rev. 2.0 (2017-04-27) +** Rev.B Header EAR1 +** - rev. 3.0 (2017-07-19) +** Rev.C Header EAR2 +** - rev. 4.0 (2018-01-26) +** Rev.D Header RFP +** +** ################################################################### +*/ + +#ifndef _MIMX8MQ6_cm4_FEATURES_H_ +#define _MIMX8MQ6_cm4_FEATURES_H_ + +/* SOC module features */ + +/* @brief AIPSTZ availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4) +/* @brief APBH availability on the SoC. */ +#define FSL_FEATURE_SOC_APBH_COUNT (1) +/* @brief BCH availability on the SoC. */ +#define FSL_FEATURE_SOC_BCH_COUNT (1) +/* @brief CCM availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_COUNT (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief DDRC availability on the SoC. */ +#define FSL_FEATURE_SOC_DDRC_COUNT (1) +/* @brief ECSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_ECSPI_COUNT (3) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (1) +/* @brief GPC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_COUNT (1) +/* @brief GPC_PGC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_PGC_COUNT (1) +/* @brief GPMI availability on the SoC. */ +#define FSL_FEATURE_SOC_GPMI_COUNT (1) +/* @brief GPT availability on the SoC. */ +#define FSL_FEATURE_SOC_GPT_COUNT (6) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (6) +/* @brief IGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_IGPIO_COUNT (5) +/* @brief II2C availability on the SoC. */ +#define FSL_FEATURE_SOC_II2C_COUNT (4) +/* @brief IOMUXC availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_COUNT (1) +/* @brief IOMUXC_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) +/* @brief IPWM availability on the SoC. */ +#define FSL_FEATURE_SOC_IPWM_COUNT (4) +/* @brief IRQSTEER availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQSTEER_COUNT (1) +/* @brief IUART availability on the SoC. */ +#define FSL_FEATURE_SOC_IUART_COUNT (4) +/* @brief LCDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDIF_COUNT (1) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (1) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (1) +/* @brief MIPI_CSI2RX availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_CSI2RX_COUNT (2) +/* @brief MIPI_DSI_HOST availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (1) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (1) +/* @brief OCOTP availability on the SoC. */ +#define FSL_FEATURE_SOC_OCOTP_COUNT (1) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (1) +/* @brief RDC availability on the SoC. */ +#define FSL_FEATURE_SOC_RDC_COUNT (1) +/* @brief RDC_SEMAPHORE availability on the SoC. */ +#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (2) +/* @brief ROMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ROMC_COUNT (1) +/* @brief SEMA4 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA4_COUNT (1) +/* @brief SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_SNVS_COUNT (1) +/* @brief SPBA availability on the SoC. */ +#define FSL_FEATURE_SOC_SPBA_COUNT (2) +/* @brief SPDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SPDIF_COUNT (2) +/* @brief SRC availability on the SoC. */ +#define FSL_FEATURE_SOC_SRC_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (2) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (3) +/* @brief XTALOSC availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC_COUNT (1) + +/* CCM module features */ + +/* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */ +#define FSL_FEATURE_CCM_HAS_ERRATA_50235 (0) + +/* ECSPI module features */ + +/* @brief ECSPI Tx FIFO Size. */ +#define FSL_FEATURE_ECSPI_TX_FIFO_SIZEn(x) (64) + +/* ENET module features */ + +/* @brief Support Interrupt Coalesce */ +#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) +/* @brief Queue Size. */ +#define FSL_FEATURE_ENET_QUEUE (3) +/* @brief Has AVB Support. */ +#define FSL_FEATURE_ENET_HAS_AVB (1) +/* @brief Has Timer Pulse Width control. */ +#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (0) +/* @brief Has Extend MDIO Support. */ +#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) +/* @brief Has Additional 1588 Timer Channel Interrupt. */ +#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (1) +/* @brief Support Interrupt Coalesce for each instance */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (0) +/* @brief Queue Size for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (3) +/* @brief Has AVB Support for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (1) +/* @brief Has Timer Pulse Width control for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (0) +/* @brief Has Extend MDIO Support for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1) +/* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) +/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ +#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) +/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +#define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) +/* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ +#define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) +/* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ +#define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) + +/* GPC module features */ + +/* @brief Has PGC MF. */ +#define FSL_FEATURE_GPC_HAS_PGC_MF (1) + +/* IGPIO module features */ + +/* @brief Has data register set DR_SET. */ +#define FSL_FEATURE_IGPIO_HAS_DR_SET (0) +/* @brief Has data register clear DR_CLEAR. */ +#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (0) +/* @brief Has data register toggle DR_TOGGLE. */ +#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (0) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (128) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ + (((x) == I2S1) ? (8) : \ + (((x) == I2S2) ? (1) : \ + (((x) == I2S3) ? (1) : \ + (((x) == I2S4) ? (1) : \ + (((x) == I2S5) ? (1) : \ + (((x) == I2S6) ? (1) : (-1))))))) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (0) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) + +/* LMEM module features */ + +/* @brief Has process identifier support. */ +#define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (1) +/* @brief Support instruction cache demote. */ +#define FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE (1) +/* @brief Has no NONCACHEABLE section. */ +#define FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION (0) +/* @brief L1 ICACHE line size in byte. */ +#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) +/* @brief L1 DCACHE line size in byte. */ +#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) + +/* MEMORY module features */ + +/* @brief Memory map has offset between subsystems. */ +#define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (1) + +/* MU module features */ + +/* @brief MU side for current core */ +#define FSL_FEATURE_MU_SIDE_B (1) +/* @brief MU Has register CCR */ +#define FSL_FEATURE_MU_HAS_CCR (0) +/* @brief MU Has register SR[RS], BSR[ARS] */ +#define FSL_FEATURE_MU_HAS_SR_RS (1) +/* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */ +#define FSL_FEATURE_MU_HAS_RESET_INT (0) +/* @brief MU Has register SR[MURIP] */ +#define FSL_FEATURE_MU_HAS_SR_MURIP (0) +/* @brief MU Has register SR[HRIP] */ +#define FSL_FEATURE_MU_HAS_SR_HRIP (0) +/* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */ +#define FSL_FEATURE_MU_NO_CLKE (1) +/* @brief MU does not support NMI, CR[NMI]. */ +#define FSL_FEATURE_MU_NO_NMI (1) +/* @brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */ +#define FSL_FEATURE_MU_NO_RSTH (1) +/* @brief MU does not supports MU reset, CR[MUR]. */ +#define FSL_FEATURE_MU_NO_MUR (1) +/* @brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */ +#define FSL_FEATURE_MU_NO_HR (1) +/* @brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */ +#define FSL_FEATURE_MU_HAS_HRM (1) +/* @brief MU does not support check the other core power mode. SR[PM] or BSR[APM]. */ +#define FSL_FEATURE_MU_NO_PM (0) +/* @brief MU supports reset assert interrupt. CR[RAIE] or BCR[RAIE]. */ +#define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (0) +/* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */ +#define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (0) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) + +/* QSPI module features */ + +/* @brief QSPI lookup table depth. */ +#define FSL_FEATURE_QSPI_LUT_DEPTH (64) +/* @brief QSPI Tx FIFO depth. */ +#define FSL_FEATURE_QSPI_TXFIFO_DEPTH (16) +/* @brief QSPI Rx FIFO depth. */ +#define FSL_FEATURE_QSPI_RXFIFO_DEPTH (16) +/* @brief QSPI AHB buffer count. */ +#define FSL_FEATURE_QSPI_AHB_BUFFER_COUNT (4) +/* @brief QSPI has command usage error flag. */ +#define FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR (1) +/* @brief QSPI support parallel mode. */ +#define FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE (1) +/* @brief QSPI support dual die. */ +#define FSL_FEATURE_QSPI_SUPPORT_DUAL_DIE (1) +/* @brief there is no SCLKCFG bit in MCR register. */ +#define FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL (1) +/* @brief there is no AITEF bit in FR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_AITEF (1) +/* @brief there is no AIBSEF bit in FR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_AIBSEF (1) +/* @brief there is no TXDMA and TXWA bit in SR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_TXDMA (1) +/* @brief there is no SFACR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_SFACR (1) +/* @brief there is no TDH bit in FLSHCR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_TDH (0) +/* @brief QSPI AHB buffer size in byte. */ +#define FSL_FEATURE_QSPI_AHB_BUFFER_SIZE (1024U) +/* @brief QSPI AMBA base address. */ +#define FSL_FEATURE_QSPI_AMBA_BASE (0xC0000000U) +/* @brief QSPI AHB buffer ARDB base address. */ +#define FSL_FEATURE_QSPI_ARDB_BASE (0x34000000U) +/* @brief QSPI has no SOCCR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG (1) + +/* SDMA module features */ + +/* @brief SDMA module channel number. */ +#define FSL_FEATURE_SDMA_MODULE_CHANNEL (32) +/* @brief SDMA module event number. */ +#define FSL_FEATURE_SDMA_EVENT_NUM (48) +/* @brief SDMA ROM memory to memory script start address. */ +#define FSL_FEATURE_SDMA_M2M_ADDR (644) +/* @brief SDMA ROM peripheral to memory script start address. */ +#define FSL_FEATURE_SDMA_P2M_ADDR (685) +/* @brief SDMA ROM memory to peripheral script start address. */ +#define FSL_FEATURE_SDMA_M2P_ADDR (749) +/* @brief SDMA ROM uart to memory script start address. */ +#define FSL_FEATURE_SDMA_UART2M_ADDR (819) +/* @brief SDMA ROM peripheral on SPBA to memory script start address. */ +#define FSL_FEATURE_SDMA_SHP2M_ADDR (893) +/* @brief SDMA ROM memory to peripheral on SPBA script start address. */ +#define FSL_FEATURE_SDMA_M2SHP_ADDR (962) +/* @brief SDMA ROM UART on SPBA to memory script start address. */ +#define FSL_FEATURE_SDMA_UARTSH2M_ADDR (1034) +/* @brief SDMA ROM SPDIF to memory script start address. */ +#define FSL_FEATURE_SDMA_SPDIF2M_ADDR (1102) +/* @brief SDMA ROM memory to SPDIF script start address. */ +#define FSL_FEATURE_SDMA_M2SPDIF_ADDR (1136) + +/* SEMA4 module features */ + +/* @brief Gate counts */ +#define FSL_FEATURE_SEMA4_GATE_COUNT (16) + +/* SNVS module features */ + +/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ +#define FSL_FEATURE_SNVS_HAS_SRTC (1) +/* @brief Has Passive Tamper Filter (regitser LPTGFCR). */ +#define FSL_FEATURE_SNVS_PASSIVE_TAMPER_FILTER (0) +/* @brief Has Active Tampers (regitser LPATCTLR, LPATCLKR, LPATRCnR). */ +#define FSL_FEATURE_SNVS_HAS_ACTIVE_TAMPERS (0) +/* @brief Number of TAMPER. */ +#define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (1) + +/* SPBA module features */ + +/* @brief SPBA module start address. */ +#define FSL_FEATURE_SPBA_STARTn(x) \ + (((x) == SPBA1) ? (0x30800000) : \ + (((x) == SPBA2) ? (0x30000000) : (-1))) +/* @brief SPBA module end address. */ +#define FSL_FEATURE_SPBA_ENDn(x) \ + (((x) == SPBA1) ? (0x308FFFFF) : \ + (((x) == SPBA2) ? (0x300FFFFF) : (-1))) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* IUART module features */ + +/* @brief UART Transmit/Receive FIFO Size */ +#define FSL_FEATURE_IUART_FIFO_SIZEn(x) (32) +/* @brief UART RX MUXed input selected option */ +#define FSL_FEATURE_IUART_RXDMUXSEL (1) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (1) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (0) + +#endif /* _MIMX8MQ6_cm4_FEATURES_H_ */ + diff --git a/devices/MIMX8MQ6/arm/MIMX8MQx_QSPI_8M_SEC.FLM b/devices/MIMX8MQ6/arm/MIMX8MQx_QSPI_8M_SEC.FLM new file mode 100644 index 000000000..e69de29bb diff --git a/devices/MIMX8MQ6/cmsis_drivers/driver_cmsis_ecspi_MIMX8MQ6.cmake b/devices/MIMX8MQ6/cmsis_drivers/driver_cmsis_ecspi_MIMX8MQ6.cmake new file mode 100644 index 000000000..50492531c --- /dev/null +++ b/devices/MIMX8MQ6/cmsis_drivers/driver_cmsis_ecspi_MIMX8MQ6.cmake @@ -0,0 +1,17 @@ +include_guard(GLOBAL) +message("driver_cmsis_ecspi component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_ecspi_cmsis.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_ecspi_MIMX8MQ6) + +include(CMSIS_Driver_Include_SPI_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/cmsis_drivers/driver_cmsis_ii2c_MIMX8MQ6.cmake b/devices/MIMX8MQ6/cmsis_drivers/driver_cmsis_ii2c_MIMX8MQ6.cmake new file mode 100644 index 000000000..6bd489c3b --- /dev/null +++ b/devices/MIMX8MQ6/cmsis_drivers/driver_cmsis_ii2c_MIMX8MQ6.cmake @@ -0,0 +1,17 @@ +include_guard(GLOBAL) +message("driver_cmsis_ii2c component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_i2c_cmsis.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_ii2c_MIMX8MQ6) + +include(CMSIS_Driver_Include_I2C_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/cmsis_drivers/driver_cmsis_iuart_MIMX8MQ6.cmake b/devices/MIMX8MQ6/cmsis_drivers/driver_cmsis_iuart_MIMX8MQ6.cmake new file mode 100644 index 000000000..41b3b8a36 --- /dev/null +++ b/devices/MIMX8MQ6/cmsis_drivers/driver_cmsis_iuart_MIMX8MQ6.cmake @@ -0,0 +1,17 @@ +include_guard(GLOBAL) +message("driver_cmsis_iuart component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_uart_cmsis.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_iuart_MIMX8MQ6) + +include(CMSIS_Driver_Include_USART_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/cmsis_drivers/fsl_ecspi_cmsis.c b/devices/MIMX8MQ6/cmsis_drivers/fsl_ecspi_cmsis.c new file mode 100644 index 000000000..0acc2e433 --- /dev/null +++ b/devices/MIMX8MQ6/cmsis_drivers/fsl_ecspi_cmsis.c @@ -0,0 +1,1628 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2020 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_ecspi_cmsis.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ecspi_cmsis" +#endif + +#if ((defined(RTE_SPI1) && RTE_SPI1) || (defined(RTE_SPI2) && RTE_SPI2) || (defined(RTE_SPI3) && RTE_SPI3)) + +#define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2) /* driver version */ + +/* + * ARMCC does not support split the data section automatically, so the driver + * needs to split the data to separate sections explicitly, to reduce codesize. + */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) +#endif + +typedef const struct _cmsis_ecspi_resource +{ + ECSPI_Type *base; + uint32_t instance; + uint32_t (*GetFreq)(void); +} cmsis_ecspi_resource_t; + +#if ((defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN) || (defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN) || \ + (defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN)) +#if (defined(FSL_FEATURE_SOC_SDMA_COUNT) && FSL_FEATURE_SOC_SDMA_COUNT) +typedef const struct _cmsis_ecspi_sdma_resource +{ + SDMAARM_Type *txSdmaBase; + uint32_t txSdmaChannel; + uint32_t txSdmaRequest; + uint32_t txSdmaPriority; + sdma_context_data_t *txSdmaContext; + + SDMAARM_Type *rxSdmaBase; + uint32_t rxSdmaChannel; + uint32_t rxSdmaRequest; + uint32_t rxSdmaPriority; + sdma_context_data_t *rxSdmaContext; +} cmsis_ecspi_sdma_resource_t; + +typedef struct _cmsis_ecspi_sdma_driver_state +{ + cmsis_ecspi_resource_t *resource; + cmsis_ecspi_sdma_resource_t *sdmaResource; + ecspi_sdma_handle_t *handle; + sdma_handle_t *sdmaRxDataHandle; + sdma_handle_t *sdmaTxDataHandle; + + uint32_t baudRate_Bps; + ARM_SPI_SignalEvent_t cb_event; + uint8_t flags; /*!< Control and state flags. */ +} cmsis_ecspi_sdma_driver_state_t; +#endif +#else /* SDMA unused. */ +typedef struct _cmsis_ecspi_interrupt_driver_state +{ + cmsis_ecspi_resource_t *resource; + ecspi_master_handle_t *handle; + ARM_SPI_SignalEvent_t cb_event; + uint32_t baudRate_Bps; + uint8_t flags; /*!< Control and state flags. */ +} cmsis_ecspi_interrupt_driver_state_t; +#endif + +/* Driver Version */ +static const ARM_DRIVER_VERSION s_ECSPIDriverVersion = {ARM_SPI_API_VERSION, ARM_SPI_DRV_VERSION}; + +/* Driver Capabilities */ +static const ARM_SPI_CAPABILITIES s_ECSPIDriverCapabilities = { + 1, /* Simplex Mode (Master and Slave) */ + 0, /* TI Synchronous Serial Interface */ + 0, /* Microwire Interface */ + 0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void ECSPI_MasterCommonControl(uint32_t control, + cmsis_ecspi_resource_t *resource, + ecspi_master_config_t *masterConfig) +{ + switch (control & (uint32_t)ARM_SPI_SS_MASTER_MODE_Msk) + { + /* + * Note: + * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or + * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured + * by user in extern file. Besides, ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver. + */ + case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */ + break; + case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */ + break; + case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */ + break; + case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */ + break; + default: + /* Avoid MISRA 16.4 violations. */ + break; + } + + /* Configure the channel to be used. Default channel is channel0. */ + switch (resource->instance) + { + case 1: +#if defined(RTE_SPI1_TRANSFER_CHANNEL) + masterConfig->channel = RTE_SPI1_TRANSFER_CHANNEL; +#endif + break; + case 2: +#if defined(RTE_SPI2_TRANSFER_CHANNEL) + masterConfig->channel = RTE_SPI2_TRANSFER_CHANNEL; +#endif + break; + case 3: +#if defined(RTE_SPI3_TRANSFER_CHANNEL) + masterConfig->channel = RTE_SPI3_TRANSFER_CHANNEL; +#endif + break; + default: + /* Avoid MISRA 16.4 violations. */ + break; + } + + switch (control & (uint32_t)ARM_SPI_FRAME_FORMAT_Msk) + { + case ARM_SPI_CPOL0_CPHA0: + masterConfig->channelConfig.polarity = kECSPI_PolarityActiveHigh; + masterConfig->channelConfig.phase = kECSPI_ClockPhaseFirstEdge; + break; + + case ARM_SPI_CPOL0_CPHA1: + masterConfig->channelConfig.polarity = kECSPI_PolarityActiveHigh; + masterConfig->channelConfig.phase = kECSPI_ClockPhaseSecondEdge; + break; + + case ARM_SPI_CPOL1_CPHA0: + masterConfig->channelConfig.polarity = kECSPI_PolarityActiveLow; + masterConfig->channelConfig.phase = kECSPI_ClockPhaseFirstEdge; + break; + + case ARM_SPI_CPOL1_CPHA1: + masterConfig->channelConfig.polarity = kECSPI_PolarityActiveLow; + masterConfig->channelConfig.phase = kECSPI_ClockPhaseSecondEdge; + break; + default: + /* Avoid MISRA 16.4 violations. */ + break; + } + /* setting Number of burst length. */ + if ((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) != 0U) + { + masterConfig->burstLength = (uint8_t)((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos); + } +} + +static void ECSPI_SlaveCommonControl(uint32_t control, + cmsis_ecspi_resource_t *resource, + ecspi_slave_config_t *slaveConfig) +{ + /* The SPI slave select is controlled by hardware, software mode is not supported by current driver. */ + switch (control & (uint32_t)ARM_SPI_SS_SLAVE_MODE_Msk) + { + case ARM_SPI_SS_SLAVE_HW: + break; + case ARM_SPI_SS_SLAVE_SW: + break; + default: + /* Avoid MISRA 16.4 violations. */ + break; + } + + /* Configure the channel to be used. Default channel is channel0. */ + switch (resource->instance) + { + case 1: +#if defined(RTE_SPI1_TRANSFER_CHANNEL) + slaveConfig->channel = RTE_SPI1_TRANSFER_CHANNEL; +#endif + break; + case 2: +#if defined(RTE_SPI2_TRANSFER_CHANNEL) + slaveConfig->channel = RTE_SPI2_TRANSFER_CHANNEL; +#endif + break; + case 3: +#if defined(RTE_SPI3_TRANSFER_CHANNEL) + slaveConfig->channel = RTE_SPI3_TRANSFER_CHANNEL; +#endif + break; + default: + /* Avoid MISRA 16.4 violations. */ + break; + } + + switch (control & (uint32_t)ARM_SPI_FRAME_FORMAT_Msk) + { + case ARM_SPI_CPOL0_CPHA0: + slaveConfig->channelConfig.polarity = kECSPI_PolarityActiveHigh; + slaveConfig->channelConfig.phase = kECSPI_ClockPhaseFirstEdge; + break; + + case ARM_SPI_CPOL0_CPHA1: + slaveConfig->channelConfig.polarity = kECSPI_PolarityActiveHigh; + slaveConfig->channelConfig.phase = kECSPI_ClockPhaseSecondEdge; + break; + + case ARM_SPI_CPOL1_CPHA0: + slaveConfig->channelConfig.polarity = kECSPI_PolarityActiveLow; + slaveConfig->channelConfig.phase = kECSPI_ClockPhaseFirstEdge; + break; + + case ARM_SPI_CPOL1_CPHA1: + slaveConfig->channelConfig.polarity = kECSPI_PolarityActiveLow; + slaveConfig->channelConfig.phase = kECSPI_ClockPhaseSecondEdge; + break; + default: + /* Avoid MISRA 16.4 violations. */ + break; + } + + if ((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) != 0U) /* setting Number of Data bits */ + { + slaveConfig->burstLength = (uint8_t)((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos); + } +} + +static ARM_DRIVER_VERSION ECSPIx_GetVersion(void) +{ + return s_ECSPIDriverVersion; +} + +static ARM_SPI_CAPABILITIES ECSPIx_GetCapabilities(void) +{ + return s_ECSPIDriverCapabilities; +} + +#endif + +#if ((defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN) || (defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN) || \ + (defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN)) + +#if (defined(FSL_FEATURE_SOC_SDMA_COUNT) && FSL_FEATURE_SOC_SDMA_COUNT) + +static void KSDK_ECSPI_MasterSDMACallback(ECSPI_Type *base, + ecspi_sdma_handle_t *handle, + status_t status, + void *userData) +{ + uint32_t event = 0U; + + if (kStatus_Success == status) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + + /* User data is actually CMSIS driver callback. */ + if (userData != NULL) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} +static void KSDK_ECSPI_SlaveSDMACallback(ECSPI_Type *base, ecspi_sdma_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + if (kStatus_Success == status) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + + /* User data is actually CMSIS driver callback. */ + if (userData != NULL) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} + +static int32_t ECSPI_SDMAInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_ecspi_sdma_driver_state_t *ecspi) +{ + if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_INIT)) + { + ecspi->cb_event = cb_event; + ecspi->flags = (uint8_t)SPI_FLAG_INIT; + } + return ARM_DRIVER_OK; +} + +static int32_t ECSPI_SDMAUninitialize(cmsis_ecspi_sdma_driver_state_t *ecspi) +{ + ecspi->flags = (uint8_t)SPI_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t ECSPI_SDMAPowerControl(ARM_POWER_STATE state, cmsis_ecspi_sdma_driver_state_t *ecspi) +{ + switch (state) + { + case ARM_POWER_OFF: + if ((ecspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U) + { + ECSPI_Deinit(ecspi->resource->base); + ecspi->flags &= ~(uint8_t)SPI_FLAG_POWER; + } + break; + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_POWER_FULL: + if (ecspi->flags == (uint8_t)SPI_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + if ((ecspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U) + { + /* Driver already powered */ + break; + } + ecspi->flags |= (uint8_t)SPI_FLAG_POWER; + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +static int32_t ECSPI_SDMASend(const void *data, uint32_t num, cmsis_ecspi_sdma_driver_state_t *ecspi) +{ + int32_t ret; + status_t status; + ecspi_transfer_t xfer = {0}; + uint32_t datawidth = + (ecspi->resource->base->CONREG & (uint32_t)ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT; + + xfer.rxData = NULL; + xfer.txData = (uint32_t *)data; + xfer.dataSize = num * ((datawidth + 8U) / 8U); + xfer.channel = kECSPI_Channel0; + + /* Configure the channel to be used. */ + switch (ecspi->resource->instance) + { + case 1: +#if defined(RTE_SPI1_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI1_TRANSFER_CHANNEL; +#endif + break; + case 2: +#if defined(RTE_SPI2_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI2_TRANSFER_CHANNEL; +#endif + break; + case 3: +#if defined(RTE_SPI3_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI3_TRANSFER_CHANNEL; +#endif + break; + default: + /* Avoid MISRA 16.4 violations. */ + break; + } + + if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + status = ECSPI_MasterTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer); + } + else + { + status = ECSPI_SlaveTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_ECSPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t ECSPI_SDMAReceive(void *data, uint32_t num, cmsis_ecspi_sdma_driver_state_t *ecspi) +{ + int32_t ret; + status_t status; + ecspi_transfer_t xfer = {0}; + uint32_t datawidth = + (ecspi->resource->base->CONREG & (uint32_t)ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT; + + xfer.txData = NULL; + xfer.rxData = (uint32_t *)data; + xfer.dataSize = num * ((datawidth + 8U) / 8U); + xfer.channel = kECSPI_Channel0; + + /* Configure the channel to be used. */ + switch (ecspi->resource->instance) + { + case 1: +#if defined(RTE_SPI1_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI1_TRANSFER_CHANNEL; +#endif + break; + case 2: +#if defined(RTE_SPI2_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI2_TRANSFER_CHANNEL; +#endif + break; + case 3: +#if defined(RTE_SPI3_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI3_TRANSFER_CHANNEL; +#endif + break; + default: + /* Avoid MISRA 16.4 violations. */ + break; + } + + if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + status = ECSPI_MasterTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer); + } + else + { + status = ECSPI_SlaveTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_ECSPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t ECSPI_SDMATransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_ecspi_sdma_driver_state_t *ecspi) +{ + int32_t ret; + status_t status; + ecspi_transfer_t xfer = {0}; + uint32_t datawidth = + (ecspi->resource->base->CONREG & (uint32_t)ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT; + + xfer.txData = (uint32_t *)data_out; + xfer.rxData = (uint32_t *)data_in; + xfer.dataSize = num * ((datawidth + 8U) / 8U); + xfer.channel = kECSPI_Channel0; + + /* Configure the channel to be used. */ + switch (ecspi->resource->instance) + { + case 1: +#if defined(RTE_SPI1_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI1_TRANSFER_CHANNEL; +#endif + break; + case 2: +#if defined(RTE_SPI2_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI2_TRANSFER_CHANNEL; +#endif + break; + case 3: +#if defined(RTE_SPI3_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI3_TRANSFER_CHANNEL; +#endif + break; + default: + /* Avoid MISRA 16.4 violations. */ + break; + } + + if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + status = ECSPI_MasterTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer); + } + else + { + status = ECSPI_SlaveTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_ECSPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} +static uint32_t ECSPI_SDMAGetCount(cmsis_ecspi_sdma_driver_state_t *ecspi) +{ + /* Unsupported by current driver. */ + return 0U; +} + +static int32_t ECSPI_SDMAControl(uint32_t control, uint32_t arg, cmsis_ecspi_sdma_driver_state_t *ecspi) +{ + if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + switch (control & ARM_SPI_CONTROL_Msk) + { + case ARM_SPI_MODE_INACTIVE: + ECSPI_Enable(ecspi->resource->base, false); + return ARM_DRIVER_OK; + + case ARM_SPI_MODE_MASTER: + ecspi->baudRate_Bps = arg; + ecspi->flags |= (uint8_t)SPI_FLAG_MASTER; + break; + + case ARM_SPI_MODE_SLAVE: + ecspi->flags &= ~(uint8_t)SPI_FLAG_MASTER; + break; + + case ARM_SPI_SET_BUS_SPEED: + if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_MASTER)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + ECSPI_SetBaudRate(ecspi->resource->base, arg, ecspi->resource->GetFreq()); + ecspi->baudRate_Bps = arg; + return ARM_DRIVER_OK; + + case ARM_SPI_GET_BUS_SPEED: /* Set Bus Speed in bps; arg = value */ + if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_MASTER)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ecspi->baudRate_Bps; + + case ARM_SPI_CONTROL_SS: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_SPI_ABORT_TRANSFER: + if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + ECSPI_MasterTransferAbortSDMA(ecspi->resource->base, ecspi->handle); + } + else + { + ECSPI_SlaveTransferAbortSDMA(ecspi->resource->base, ecspi->handle); + } + return ARM_DRIVER_OK; + + case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */ + /* Unsupported by current driver. */ + return ARM_DRIVER_OK; + + case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */ + /* Mode is not supported by current driver. */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */ + /* Mode is not supported by current driver. */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + + default: + /* Avoid MISRA 16.4 violation */ + break; + } + + if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + ecspi_master_config_t masterConfig; + ECSPI_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Bps = ecspi->baudRate_Bps; + + ECSPI_MasterCommonControl(control, ecspi->resource, &masterConfig); + + if ((ecspi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U) + { + ECSPI_Deinit(ecspi->resource->base); + } + ECSPI_MasterInit(ecspi->resource->base, &masterConfig, ecspi->resource->GetFreq()); + + SDMA_CreateHandle(ecspi->sdmaTxDataHandle, ecspi->sdmaResource->txSdmaBase, ecspi->sdmaResource->txSdmaChannel, + ecspi->sdmaResource->txSdmaContext); + SDMA_CreateHandle(ecspi->sdmaRxDataHandle, ecspi->sdmaResource->rxSdmaBase, ecspi->sdmaResource->rxSdmaChannel, + ecspi->sdmaResource->rxSdmaContext); + ECSPI_MasterTransferCreateHandleSDMA(ecspi->resource->base, ecspi->handle, KSDK_ECSPI_MasterSDMACallback, + (void *)ecspi->cb_event, ecspi->sdmaTxDataHandle, ecspi->sdmaRxDataHandle, + ecspi->sdmaResource->txSdmaRequest, ecspi->sdmaResource->rxSdmaRequest, + ecspi->sdmaResource->txSdmaChannel, ecspi->sdmaResource->rxSdmaChannel); + + SDMA_SetChannelPriority(ecspi->sdmaResource->txSdmaBase, ecspi->sdmaResource->txSdmaChannel, + ecspi->sdmaResource->txSdmaPriority); + SDMA_SetChannelPriority(ecspi->sdmaResource->rxSdmaBase, ecspi->sdmaResource->rxSdmaChannel, + ecspi->sdmaResource->rxSdmaPriority); + + ecspi->flags |= (uint8_t)SPI_FLAG_CONFIGURED; + } + else + { + ecspi_slave_config_t slaveConfig; + ECSPI_SlaveGetDefaultConfig(&slaveConfig); + ECSPI_SlaveCommonControl(control, ecspi->resource, &slaveConfig); + + if ((ecspi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U) + { + ECSPI_Deinit(ecspi->resource->base); + } + ECSPI_SlaveInit(ecspi->resource->base, &slaveConfig); + + SDMA_CreateHandle(ecspi->sdmaTxDataHandle, ecspi->sdmaResource->txSdmaBase, ecspi->sdmaResource->txSdmaChannel, + ecspi->sdmaResource->txSdmaContext); + SDMA_CreateHandle(ecspi->sdmaRxDataHandle, ecspi->sdmaResource->rxSdmaBase, ecspi->sdmaResource->rxSdmaChannel, + ecspi->sdmaResource->rxSdmaContext); + ECSPI_SlaveTransferCreateHandleSDMA(ecspi->resource->base, ecspi->handle, KSDK_ECSPI_SlaveSDMACallback, + (void *)ecspi->cb_event, ecspi->sdmaTxDataHandle, ecspi->sdmaRxDataHandle, + ecspi->sdmaResource->txSdmaRequest, ecspi->sdmaResource->rxSdmaRequest, + ecspi->sdmaResource->txSdmaChannel, ecspi->sdmaResource->rxSdmaChannel); + + SDMA_SetChannelPriority(ecspi->sdmaResource->txSdmaBase, ecspi->sdmaResource->txSdmaChannel, + ecspi->sdmaResource->txSdmaPriority); + SDMA_SetChannelPriority(ecspi->sdmaResource->rxSdmaBase, ecspi->sdmaResource->rxSdmaChannel, + ecspi->sdmaResource->rxSdmaPriority); + + ecspi->flags |= (uint8_t)SPI_FLAG_CONFIGURED; + } + + return ARM_DRIVER_OK; +} + +static ARM_SPI_STATUS ECSPI_SDMAGetStatus(cmsis_ecspi_sdma_driver_state_t *ecspi) +{ + ARM_SPI_STATUS stat = {0}; + + stat.busy = ((ecspi->handle->txInProgress == true) || (ecspi->handle->rxInProgress == true)) ? (0U) : (1U); + stat.data_lost = 0U; + stat.mode_fault = 0U; + stat.reserved = 0U; + + return stat; +} +#endif /* defined(FSL_FEATURE_SOC_DMA_COUNT) */ + +#endif + +#if ((defined(RTE_SPI1) && RTE_SPI1 && !RTE_SPI1_DMA_EN) || (defined(RTE_SPI2) && RTE_SPI2 && !RTE_SPI2_DMA_EN) || \ + (defined(RTE_SPI3) && RTE_SPI3 && !RTE_SPI3_DMA_EN)) + +static void KSDK_ECSPI_MasterInterruptCallback(ECSPI_Type *base, + ecspi_master_handle_t *handle, + status_t status, + void *userData) +{ + uint32_t event = 0U; + + if (kStatus_Success == status) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + + if (kStatus_ECSPI_HardwareOverFlow == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + + /* User data is actually CMSIS driver callback. */ + if (userData != NULL) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} + +static void KSDK_ECSPI_SlaveInterruptCallback(ECSPI_Type *base, + ecspi_slave_handle_t *handle, + status_t status, + void *userData) +{ + uint32_t event = 0; + + if (kStatus_Success == status) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + + if (kStatus_ECSPI_HardwareOverFlow == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + + /* User data is actually CMSIS driver callback. */ + if (userData != NULL) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} + +static int32_t ECSPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_ecspi_interrupt_driver_state_t *ecspi) +{ + if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_INIT)) + { + ecspi->cb_event = cb_event; + ecspi->flags = (uint8_t)SPI_FLAG_INIT; + } + return ARM_DRIVER_OK; +} + +static int32_t ECSPI_InterruptUninitialize(cmsis_ecspi_interrupt_driver_state_t *ecspi) +{ + ecspi->flags = (uint8_t)SPI_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t ECSPI_InterruptPowerControl(ARM_POWER_STATE state, cmsis_ecspi_interrupt_driver_state_t *ecspi) +{ + int32_t result = ARM_DRIVER_OK; + switch (state) + { + case ARM_POWER_OFF: + if ((ecspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U) + { + ECSPI_Deinit(ecspi->resource->base); + ecspi->flags &= ~(uint8_t)SPI_FLAG_POWER; + } + break; + + case ARM_POWER_LOW: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + case ARM_POWER_FULL: + if (ecspi->flags == (uint8_t)SPI_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + /* Driver already powered */ + if ((ecspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U) + { + break; + } + ecspi->flags |= (uint8_t)SPI_FLAG_POWER; + break; + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + return result; +} + +static int32_t ECSPI_InterruptSend(const void *data, uint32_t num, cmsis_ecspi_interrupt_driver_state_t *ecspi) +{ + int32_t ret; + status_t status; + ecspi_transfer_t xfer = {0}; + uint32_t datawidth = + (ecspi->resource->base->CONREG & (uint32_t)ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT; + + xfer.rxData = NULL; + xfer.txData = (uint32_t *)data; + xfer.dataSize = num * ((datawidth + 8U) / 8U); + xfer.channel = kECSPI_Channel0; + + /* Configure the channel to be used. */ + switch (ecspi->resource->instance) + { + case 1: +#if defined(RTE_SPI1_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI1_TRANSFER_CHANNEL; +#endif + break; + case 2: +#if defined(RTE_SPI2_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI2_TRANSFER_CHANNEL; +#endif + break; + case 3: +#if defined(RTE_SPI3_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI3_TRANSFER_CHANNEL; +#endif + break; + default: + /* Avoid MISRA 16.4 violations. */ + break; + } + + if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + status = ECSPI_MasterTransferNonBlocking(ecspi->resource->base, ecspi->handle, &xfer); + } + else + { + status = ECSPI_SlaveTransferNonBlocking(ecspi->resource->base, ecspi->handle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_ECSPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t ECSPI_InterruptReceive(void *data, uint32_t num, cmsis_ecspi_interrupt_driver_state_t *ecspi) +{ + int32_t ret; + status_t status; + ecspi_transfer_t xfer = {0}; + uint32_t datawidth = + (ecspi->resource->base->CONREG & ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT; + + xfer.txData = NULL; + xfer.rxData = (uint32_t *)data; + xfer.dataSize = num * ((datawidth + 8U) / 8U); + xfer.channel = kECSPI_Channel0; + + /* Configure the channel to be used. */ + switch (ecspi->resource->instance) + { + case 1: +#if defined(RTE_SPI1_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI1_TRANSFER_CHANNEL; +#endif + break; + case 2: +#if defined(RTE_SPI2_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI2_TRANSFER_CHANNEL; +#endif + break; + case 3: +#if defined(RTE_SPI3_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI3_TRANSFER_CHANNEL; +#endif + break; + default: + /* Avoid MISRA 16.4 violations. */ + break; + } + + if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + status = ECSPI_MasterTransferNonBlocking(ecspi->resource->base, ecspi->handle, &xfer); + } + else + { + status = ECSPI_SlaveTransferNonBlocking(ecspi->resource->base, ecspi->handle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_ECSPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t ECSPI_InterruptTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_ecspi_interrupt_driver_state_t *ecspi) +{ + int32_t ret; + status_t status; + ecspi_transfer_t xfer = {0}; + uint32_t datawidth = + (ecspi->resource->base->CONREG & (uint32_t)ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT; + + xfer.txData = (uint32_t *)data_out; + xfer.rxData = (uint32_t *)data_in; + xfer.dataSize = num * ((datawidth + 8U) / 8U); + xfer.channel = kECSPI_Channel0; + + /* Configure the channel to be used. */ + switch (ecspi->resource->instance) + { + case 1: +#if defined(RTE_SPI1_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI1_TRANSFER_CHANNEL; +#endif + break; + case 2: +#if defined(RTE_SPI2_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI2_TRANSFER_CHANNEL; +#endif + break; + case 3: +#if defined(RTE_SPI3_TRANSFER_CHANNEL) + xfer.channel = RTE_SPI3_TRANSFER_CHANNEL; +#endif + break; + default: + /* Avoid MISRA 16.4 violations. */ + break; + } + + if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + status = ECSPI_MasterTransferNonBlocking(ecspi->resource->base, ecspi->handle, &xfer); + } + else + { + status = ECSPI_SlaveTransferNonBlocking(ecspi->resource->base, ecspi->handle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_ECSPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} +static uint32_t ECSPI_InterruptGetCount(cmsis_ecspi_interrupt_driver_state_t *ecspi) +{ + uint32_t datawidth = + (ecspi->resource->base->CONREG & (uint32_t)ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT; + uint32_t cnt = ecspi->handle->transferSize - ecspi->handle->rxRemainingBytes; + cnt /= ((datawidth + 8U) / 8U); + return cnt; +} + +static int32_t ECSPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_ecspi_interrupt_driver_state_t *ecspi) +{ + int32_t result = ARM_DRIVER_OK; + bool isContinue = false; + if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + switch (control & ARM_SPI_CONTROL_Msk) + { + case ARM_SPI_MODE_MASTER: /* SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps */ + ecspi->baudRate_Bps = arg; + ecspi->flags |= (uint8_t)SPI_FLAG_MASTER; + isContinue = true; + break; + + case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on MISO, Input on MOSI) */ + ecspi->flags &= ~(uint8_t)SPI_FLAG_MASTER; + isContinue = true; + break; + + case ARM_SPI_GET_BUS_SPEED: /* Get Bus Speed in bps */ + if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_MASTER)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + result = (int32_t)ecspi->baudRate_Bps; + break; + + case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */ + if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_MASTER)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + ECSPI_SetBaudRate(ecspi->resource->base, arg, ecspi->resource->GetFreq()); + ecspi->baudRate_Bps = arg; + break; + + case ARM_SPI_CONTROL_SS: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */ + if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + ECSPI_MasterTransferAbort(ecspi->resource->base, ecspi->handle); + } + else + { + ECSPI_SlaveTransferAbort(ecspi->resource->base, ecspi->handle); + } + break; + + case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */ + /* Mode is not supported by current driver. */ + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */ + /* Mode is not supported by current driver. */ + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */ + /* Mode is not supported by current driver. */ + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + default: + isContinue = true; + /* Avoid MISRA 16.4 violation */ + break; + } + + if (!isContinue) + { + return result; + } + + if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + ecspi_master_config_t masterConfig; + ECSPI_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Bps = ecspi->baudRate_Bps; + + ECSPI_MasterCommonControl(control, ecspi->resource, &masterConfig); + + if ((ecspi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U) + { + ECSPI_Deinit(ecspi->resource->base); + } + ECSPI_MasterInit(ecspi->resource->base, &masterConfig, ecspi->resource->GetFreq()); + ECSPI_MasterTransferCreateHandle(ecspi->resource->base, ecspi->handle, KSDK_ECSPI_MasterInterruptCallback, + (void *)ecspi->cb_event); + ecspi->flags |= (uint8_t)SPI_FLAG_CONFIGURED; + } + else + { + ecspi_slave_config_t slaveConfig; + ECSPI_SlaveGetDefaultConfig(&slaveConfig); + + ECSPI_SlaveCommonControl(control, ecspi->resource, &slaveConfig); + + if ((ecspi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U) + { + ECSPI_Deinit(ecspi->resource->base); + } + ECSPI_SlaveInit(ecspi->resource->base, &slaveConfig); + ECSPI_SlaveTransferCreateHandle(ecspi->resource->base, ecspi->handle, KSDK_ECSPI_SlaveInterruptCallback, + (void *)ecspi->cb_event); + ecspi->flags |= (uint8_t)SPI_FLAG_CONFIGURED; + } + + return result; +} + +static ARM_SPI_STATUS ECSPI_InterruptGetStatus(cmsis_ecspi_interrupt_driver_state_t *ecspi) +{ + ARM_SPI_STATUS stat = {0}; + + stat.busy = ((ecspi->handle->txRemainingBytes > 0U) || (ecspi->handle->rxRemainingBytes > 0U)) ? (0U) : (1U); + stat.data_lost = 0U; + stat.mode_fault = 0U; + stat.reserved = 0U; + + return stat; +} + +#endif + +#if defined(ECSPI1) && defined(RTE_SPI1) && RTE_SPI1 + +/* User needs to provide the implementation for ECSPI1_GetFreq/InitPins/DeinitPins + * in the application for enabling according instance. + */ +extern uint32_t ECSPI1_GetFreq(void); + +static cmsis_ecspi_resource_t ECSPI1_Resource = {ECSPI1, 1, ECSPI1_GetFreq}; + +#if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN + +AT_NONCACHEABLE_SECTION_ALIGN(ecspi_sdma_handle_t ECSPI1_SdmaHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(sdma_handle_t ECSPI1_TxSdmaHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(sdma_handle_t ECSPI1_RxSdmaHandle, 4); + +AT_NONCACHEABLE_SECTION_ALIGN(sdma_context_data_t ECSPI1_TxSdmaContext, 4); +AT_NONCACHEABLE_SECTION_ALIGN(sdma_context_data_t ECSPI1_RxSdmaContext, 4); + +static cmsis_ecspi_sdma_resource_t ECSPI1_SDMAResource = { + RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH, RTE_SPI1_DMA_TX_CH_REQUEST, RTE_SPI1_DMA_TX_CH_PRIORITY, + &ECSPI1_TxSdmaContext, RTE_SPI1_DMA_RX_DMA_BASE, RTE_SPI1_DMA_RX_CH, RTE_SPI1_DMA_RX_CH_REQUEST, + RTE_SPI1_DMA_RX_CH_PRIORITY, &ECSPI1_RxSdmaContext}; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("ecspi1_sdma_driver_state") +static cmsis_ecspi_sdma_driver_state_t ECSPI1_SDMADriverState = { +#else +static cmsis_ecspi_sdma_driver_state_t ECSPI1_SDMADriverState = { +#endif + &ECSPI1_Resource, &ECSPI1_SDMAResource, &ECSPI1_SdmaHandle, &ECSPI1_RxSdmaHandle, &ECSPI1_TxSdmaHandle}; + +static int32_t ECSPI1_SDMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI1_PIN_INIT + RTE_SPI1_PIN_INIT(); +#endif + return ECSPI_SDMAInitialize(cb_event, &ECSPI1_SDMADriverState); +} + +static int32_t ECSPI1_SDMAUninitialize(void) +{ +#ifdef RTE_SPI1_PIN_DEINIT + RTE_SPI1_PIN_DEINIT(); +#endif + return ECSPI_SDMAUninitialize(&ECSPI1_SDMADriverState); +} + +static int32_t ECSPI1_SDMAPowerControl(ARM_POWER_STATE state) +{ + return ECSPI_SDMAPowerControl(state, &ECSPI1_SDMADriverState); +} + +static int32_t ECSPI1_SDMASend(const void *data, uint32_t num) +{ + return ECSPI_SDMASend(data, num, &ECSPI1_SDMADriverState); +} + +static int32_t ECSPI1_SDMAReceive(void *data, uint32_t num) +{ + return ECSPI_SDMAReceive(data, num, &ECSPI1_SDMADriverState); +} + +static int32_t ECSPI1_SDMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return ECSPI_SDMATransfer(data_out, data_in, num, &ECSPI1_SDMADriverState); +} + +static uint32_t ECSPI1_SDMAGetCount(void) +{ + return ECSPI_SDMAGetCount(&ECSPI1_SDMADriverState); +} + +static int32_t ECSPI1_SDMAControl(uint32_t control, uint32_t arg) +{ + return ECSPI_SDMAControl(control, arg, &ECSPI1_SDMADriverState); +} + +static ARM_SPI_STATUS ECSPI1_SDMAGetStatus(void) +{ + return ECSPI_SDMAGetStatus(&ECSPI1_SDMADriverState); +} + +#else + +static ecspi_master_handle_t ECSPI1_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("ecspi1_interrupt_driver_state") +static cmsis_ecspi_interrupt_driver_state_t ECSPI1_InterruptDriverState = { +#else +static cmsis_ecspi_interrupt_driver_state_t ECSPI1_InterruptDriverState = { +#endif + &ECSPI1_Resource, + &ECSPI1_Handle, +}; + +static int32_t ECSPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI1_PIN_INIT + RTE_SPI1_PIN_INIT(); +#endif + return ECSPI_InterruptInitialize(cb_event, &ECSPI1_InterruptDriverState); +} + +static int32_t ECSPI1_InterruptUninitialize(void) +{ +#ifdef RTE_SPI1_PIN_DEINIT + RTE_SPI1_PIN_DEINIT(); +#endif + return ECSPI_InterruptUninitialize(&ECSPI1_InterruptDriverState); +} + +static int32_t ECSPI1_InterruptPowerControl(ARM_POWER_STATE state) +{ + return ECSPI_InterruptPowerControl(state, &ECSPI1_InterruptDriverState); +} + +static int32_t ECSPI1_InterruptSend(const void *data, uint32_t num) +{ + return ECSPI_InterruptSend(data, num, &ECSPI1_InterruptDriverState); +} + +static int32_t ECSPI1_InterruptReceive(void *data, uint32_t num) +{ + return ECSPI_InterruptReceive(data, num, &ECSPI1_InterruptDriverState); +} + +static int32_t ECSPI1_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return ECSPI_InterruptTransfer(data_out, data_in, num, &ECSPI1_InterruptDriverState); +} + +static uint32_t ECSPI1_InterruptGetCount(void) +{ + return ECSPI_InterruptGetCount(&ECSPI1_InterruptDriverState); +} + +static int32_t ECSPI1_InterruptControl(uint32_t control, uint32_t arg) +{ + return ECSPI_InterruptControl(control, arg, &ECSPI1_InterruptDriverState); +} + +static ARM_SPI_STATUS ECSPI1_InterruptGetStatus(void) +{ + return ECSPI_InterruptGetStatus(&ECSPI1_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI1 = { + ECSPIx_GetVersion, ECSPIx_GetCapabilities, +#if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN + ECSPI1_SDMAInitialize, ECSPI1_SDMAUninitialize, ECSPI1_SDMAPowerControl, ECSPI1_SDMASend, ECSPI1_SDMAReceive, + ECSPI1_SDMATransfer, ECSPI1_SDMAGetCount, ECSPI1_SDMAControl, ECSPI1_SDMAGetStatus +#else + ECSPI1_InterruptInitialize, ECSPI1_InterruptUninitialize, ECSPI1_InterruptPowerControl, ECSPI1_InterruptSend, + ECSPI1_InterruptReceive, ECSPI1_InterruptTransfer, ECSPI1_InterruptGetCount, ECSPI1_InterruptControl, + ECSPI1_InterruptGetStatus +#endif +}; + +#endif /* ECSPI1 */ + +#if defined(ECSPI2) && defined(RTE_SPI2) && RTE_SPI2 + +/* User needs to provide the implementation for ECSPI2_GetFreq/InitPins/DeinitPins + * in the application for enabling according instance. + */ +extern uint32_t ECSPI2_GetFreq(void); + +static cmsis_ecspi_resource_t ECSPI2_Resource = {ECSPI2, 2, ECSPI2_GetFreq}; + +#if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN + +AT_NONCACHEABLE_SECTION_ALIGN(ecspi_sdma_handle_t ECSPI2_SdmaHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(sdma_handle_t ECSPI2_TxSdmaHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(sdma_handle_t ECSPI2_RxSdmaHandle, 4); + +AT_NONCACHEABLE_SECTION_ALIGN(sdma_context_data_t ECSPI2_TxSdmaContext, 4); +AT_NONCACHEABLE_SECTION_ALIGN(sdma_context_data_t ECSPI2_RxSdmaContext, 4); + +static cmsis_ecspi_sdma_resource_t ECSPI2_SDMAResource = { + RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH, RTE_SPI2_DMA_TX_CH_REQUEST, RTE_SPI2_DMA_TX_CH_PRIORITY, + &ECSPI2_TxSdmaContext, RTE_SPI2_DMA_RX_DMA_BASE, RTE_SPI2_DMA_RX_CH, RTE_SPI2_DMA_RX_CH_REQUEST, + RTE_SPI2_DMA_RX_CH_PRIORITY, &ECSPI2_RxSdmaContext}; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("ecspi2_sdma_driver_state") +static cmsis_ecspi_sdma_driver_state_t ECSPI2_SDMADriverState = { +#else +static cmsis_ecspi_sdma_driver_state_t ECSPI2_SDMADriverState = { +#endif + &ECSPI2_Resource, &ECSPI2_SDMAResource, &ECSPI2_SdmaHandle, &ECSPI2_TxSdmaHandle, &ECSPI2_RxSdmaHandle, + +}; + +static int32_t ECSPI2_SDMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI2_PIN_INIT + RTE_SPI2_PIN_INIT(); +#endif + return ECSPI_SDMAInitialize(cb_event, &ECSPI2_SDMADriverState); +} + +static int32_t ECSPI2_SDMAUninitialize(void) +{ +#ifdef RTE_SPI2_PIN_DEINIT + RTE_SPI2_PIN_DEINIT(); +#endif + return ECSPI_SDMAUninitialize(&ECSPI2_SDMADriverState); +} + +static int32_t ECSPI2_SDMAPowerControl(ARM_POWER_STATE state) +{ + return ECSPI_SDMAPowerControl(state, &ECSPI2_SDMADriverState); +} + +static int32_t ECSPI2_SDMASend(const void *data, uint32_t num) +{ + return ECSPI_SDMASend(data, num, &ECSPI2_SDMADriverState); +} + +static int32_t ECSPI2_SDMAReceive(void *data, uint32_t num) +{ + return ECSPI_SDMAReceive(data, num, &ECSPI2_SDMADriverState); +} + +static int32_t ECSPI2_SDMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return ECSPI_SDMATransfer(data_out, data_in, num, &ECSPI2_SDMADriverState); +} + +static uint32_t ECSPI2_SDMAGetCount(void) +{ + return ECSPI_SDMAGetCount(&ECSPI2_SDMADriverState); +} + +static int32_t ECSPI2_SDMAControl(uint32_t control, uint32_t arg) +{ + return ECSPI_SDMAControl(control, arg, &ECSPI2_SDMADriverState); +} + +static ARM_SPI_STATUS ECSPI2_SDMAGetStatus(void) +{ + return ECSPI_SDMAGetStatus(&ECSPI2_SDMADriverState); +} + +#else + +static ecspi_master_handle_t ECSPI2_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("ecspi2_interrupt_driver_state") +static cmsis_ecspi_interrupt_driver_state_t ECSPI2_InterruptDriverState = { +#else +static cmsis_ecspi_interrupt_driver_state_t ECSPI2_InterruptDriverState = { +#endif + &ECSPI2_Resource, + &ECSPI2_Handle, +}; + +static int32_t ECSPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI2_PIN_INIT + RTE_SPI2_PIN_INIT(); +#endif + return ECSPI_InterruptInitialize(cb_event, &ECSPI2_InterruptDriverState); +} + +static int32_t ECSPI2_InterruptUninitialize(void) +{ +#ifdef RTE_SPI2_PIN_DEINIT + RTE_SPI2_PIN_DEINIT(); +#endif + return ECSPI_InterruptUninitialize(&ECSPI2_InterruptDriverState); +} + +static int32_t ECSPI2_InterruptPowerControl(ARM_POWER_STATE state) +{ + return ECSPI_InterruptPowerControl(state, &ECSPI2_InterruptDriverState); +} + +static int32_t ECSPI2_InterruptSend(const void *data, uint32_t num) +{ + return ECSPI_InterruptSend(data, num, &ECSPI2_InterruptDriverState); +} + +static int32_t ECSPI2_InterruptReceive(void *data, uint32_t num) +{ + return ECSPI_InterruptReceive(data, num, &ECSPI2_InterruptDriverState); +} + +static int32_t ECSPI2_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return ECSPI_InterruptTransfer(data_out, data_in, num, &ECSPI2_InterruptDriverState); +} + +static uint32_t ECSPI2_InterruptGetCount(void) +{ + return ECSPI_InterruptGetCount(&ECSPI2_InterruptDriverState); +} + +static int32_t ECSPI2_InterruptControl(uint32_t control, uint32_t arg) +{ + return ECSPI_InterruptControl(control, arg, &ECSPI2_InterruptDriverState); +} + +static ARM_SPI_STATUS ECSPI2_InterruptGetStatus(void) +{ + return ECSPI_InterruptGetStatus(&ECSPI2_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI2 = { + ECSPIx_GetVersion, ECSPIx_GetCapabilities, +#if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN + ECSPI2_SDMAInitialize, ECSPI2_SDMAUninitialize, ECSPI2_SDMAPowerControl, ECSPI2_SDMASend, ECSPI2_SDMAReceive, + ECSPI2_SDMATransfer, ECSPI2_SDMAGetCount, ECSPI2_SDMAControl, ECSPI2_SDMAGetStatus +#else + ECSPI2_InterruptInitialize, ECSPI2_InterruptUninitialize, ECSPI2_InterruptPowerControl, ECSPI2_InterruptSend, + ECSPI2_InterruptReceive, ECSPI2_InterruptTransfer, ECSPI2_InterruptGetCount, ECSPI2_InterruptControl, + ECSPI2_InterruptGetStatus +#endif +}; + +#endif /* ECSPI2 */ + +#if defined(ECSPI3) && defined(RTE_SPI3) && RTE_SPI3 + +/* User needs to provide the implementation for ECSPI3_GetFreq/InitPins/DeinitPins + * in the application for enabling according instance. + */ +extern uint32_t ECSPI3_GetFreq(void); + +static cmsis_ecspi_resource_t ECSPI3_Resource = {ECSPI3, 3, ECSPI3_GetFreq}; + +#if defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN) + +AT_NONCACHEABLE_SECTION_ALIGN(ecspi_sdma_handle_t ECSPI3_SdmaHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(sdma_handle_t ECSPI3_TxSdmaHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(sdma_handle_t ECSPI3_RxSdmaHandle, 4); + +AT_NONCACHEABLE_SECTION_ALIGN(sdma_context_data_t ECSPI3_TxSdmaContext, 4); +AT_NONCACHEABLE_SECTION_ALIGN(sdma_context_data_t ECSPI3_RxSdmaContext, 4); + +static cmsis_ecspi_sdma_resource_t ECSPI3_SDMAResource = { + RTE_SPI3_DMA_TX_DMA_BASE, RTE_SPI3_DMA_TX_CH, RTE_SPI3_DMA_TX_CH_REQUEST, RTE_SPI3_DMA_TX_CH_PRIORITY, + &ECSPI3_TxSdmaContext, RTE_SPI3_DMA_RX_DMA_BASE, RTE_SPI3_DMA_RX_CH, RTE_SPI3_DMA_RX_CH_REQUEST, + RTE_SPI3_DMA_RX_CH_PRIORITY, &ECSPI3_RxSdmaContext}; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("ecspi3_sdma_driver_state") +static cmsis_ecspi_sdma_driver_state_t ECSPI3_SDMADriverState = { +#else +static cmsis_ecspi_sdma_driver_state_t ECSPI3_SDMADriverState = { +#endif + &ECSPI3_Resource, &ECSPI3_SDMAResource, &ECSPI3_SdmaHandle, &ECSPI3_TxSdmaHandle, &ECSPI3_RxSdmaHandle, + +}; + +static int32_t ECSPI3_SDMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI3_PIN_INIT + RTE_SPI3_PIN_INIT(); +#endif + return ECSPI_SDMAInitialize(cb_event, &ECSPI3_SDMADriverState); +} + +static int32_t ECSPI3_SDMAUninitialize(void) +{ +#ifdef RTE_SPI3_PIN_DEINIT + RTE_SPI3_PIN_DEINIT(); +#endif + return ECSPI_SDMAUninitialize(&ECSPI3_SDMADriverState); +} + +static int32_t ECSPI3_SDMAPowerControl(ARM_POWER_STATE state) +{ + return ECSPI_SDMAPowerControl(state, &ECSPI3_SDMADriverState); +} + +static int32_t ECSPI3_SDMASend(const void *data, uint32_t num) +{ + return ECSPI_SDMASend(data, num, &ECSPI3_SDMADriverState); +} + +static int32_t ECSPI3_SDMAReceive(void *data, uint32_t num) +{ + return ECSPI_SDMAReceive(data, num, &ECSPI3_SDMADriverState); +} + +static int32_t ECSPI3_SDMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return ECSPI_SDMATransfer(data_out, data_in, num, &ECSPI3_SDMADriverState); +} + +static uint32_t ECSPI3_SDMAGetCount(void) +{ + return ECSPI_SDMAGetCount(&ECSPI3_SDMADriverState); +} + +static int32_t ECSPI3_SDMAControl(uint32_t control, uint32_t arg) +{ + return ECSPI_SDMAControl(control, arg, &ECSPI3_SDMADriverState); +} + +static ARM_SPI_STATUS ECSPI3_SDMAGetStatus(void) +{ + return ECSPI_SDMAGetStatus(&ECSPI3_SDMADriverState); +} + +#else + +static ecspi_master_handle_t ECSPI3_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("ecspi3_interrupt_driver_state") +static cmsis_ecspi_interrupt_driver_state_t ECSPI3_InterruptDriverState = { +#else +static cmsis_ecspi_interrupt_driver_state_t ECSPI3_InterruptDriverState = { +#endif + &ECSPI3_Resource, + &ECSPI3_Handle, +}; + +static int32_t ECSPI3_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI3_PIN_INIT + RTE_SPI3_PIN_INIT(); +#endif + return ECSPI_InterruptInitialize(cb_event, &ECSPI3_InterruptDriverState); +} + +static int32_t ECSPI3_InterruptUninitialize(void) +{ +#ifdef RTE_SPI3_PIN_DEINIT + RTE_SPI3_PIN_DEINIT(); +#endif + return ECSPI_InterruptUninitialize(&ECSPI3_InterruptDriverState); +} + +static int32_t ECSPI3_InterruptPowerControl(ARM_POWER_STATE state) +{ + return ECSPI_InterruptPowerControl(state, &ECSPI3_InterruptDriverState); +} + +static int32_t ECSPI3_InterruptSend(const void *data, uint32_t num) +{ + return ECSPI_InterruptSend(data, num, &ECSPI3_InterruptDriverState); +} + +static int32_t ECSPI3_InterruptReceive(void *data, uint32_t num) +{ + return ECSPI_InterruptReceive(data, num, &ECSPI3_InterruptDriverState); +} + +static int32_t ECSPI3_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return ECSPI_InterruptTransfer(data_out, data_in, num, &ECSPI3_InterruptDriverState); +} + +static uint32_t ECSPI3_InterruptGetCount(void) +{ + return ECSPI_InterruptGetCount(&ECSPI3_InterruptDriverState); +} + +static int32_t ECSPI3_InterruptControl(uint32_t control, uint32_t arg) +{ + return ECSPI_InterruptControl(control, arg, &ECSPI3_InterruptDriverState); +} + +static ARM_SPI_STATUS ECSPI3_InterruptGetStatus(void) +{ + return ECSPI_InterruptGetStatus(&ECSPI3_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI3 = { + ECSPIx_GetVersion, ECSPIx_GetCapabilities, +#if defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN + ECSPI3_SDMAInitialize, ECSPI3_SDMAUninitialize, ECSPI3_SDMAPowerControl, ECSPI3_SDMASend, ECSPI3_SDMAReceive, + ECSPI3_SDMATransfer, ECSPI3_SDMAGetCount, ECSPI3_SDMAControl, ECSPI3_SDMAGetStatus +#else + ECSPI3_InterruptInitialize, ECSPI3_InterruptUninitialize, ECSPI3_InterruptPowerControl, ECSPI3_InterruptSend, + ECSPI3_InterruptReceive, ECSPI3_InterruptTransfer, ECSPI3_InterruptGetCount, ECSPI3_InterruptControl, + ECSPI3_InterruptGetStatus +#endif +}; + +#endif /* ECSPI3 */ diff --git a/devices/MIMX8MQ6/cmsis_drivers/fsl_ecspi_cmsis.h b/devices/MIMX8MQ6/cmsis_drivers/fsl_ecspi_cmsis.h new file mode 100644 index 000000000..0c94d202e --- /dev/null +++ b/devices/MIMX8MQ6/cmsis_drivers/fsl_ecspi_cmsis.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2020 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _FSL_SPI_CMSIS_H_ +#define _FSL_SPI_CMSIS_H_ + +#include "fsl_ecspi.h" +#include "RTE_Device.h" +#include "Driver_SPI.h" +#if ((defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN) || (defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN) || \ + (defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN)) +#if defined(FSL_FEATURE_SOC_SDMA_COUNT) && (FSL_FEATURE_SOC_SDMA_COUNT) +#include "fsl_ecspi_sdma.h" +#endif +#endif + +#if defined(ECSPI1) && defined(RTE_SPI1) && RTE_SPI1 +extern ARM_DRIVER_SPI Driver_SPI1; +#endif /* SPI1 */ + +#if defined(ECSPI2) && defined(RTE_SPI2) && RTE_SPI2 +extern ARM_DRIVER_SPI Driver_SPI2; +#endif /* SPI2 */ + +#if defined(ECSPI3) && defined(RTE_SPI3) && RTE_SPI3 +extern ARM_DRIVER_SPI Driver_SPI3; +#endif /* SPI3 */ + +#define SPI_FLAG_UNINIT (0UL) +#define SPI_FLAG_INIT (1UL << 0) +#define SPI_FLAG_POWER (1UL << 1) +#define SPI_FLAG_CONFIGURED (1UL << 2) +#define SPI_FLAG_MASTER (1UL << 3) + +#endif diff --git a/devices/MIMX8MQ6/cmsis_drivers/fsl_i2c_cmsis.c b/devices/MIMX8MQ6/cmsis_drivers/fsl_i2c_cmsis.c new file mode 100644 index 000000000..974c61fbe --- /dev/null +++ b/devices/MIMX8MQ6/cmsis_drivers/fsl_i2c_cmsis.c @@ -0,0 +1,983 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2020 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_i2c_cmsis.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ii2c_cmsis" +#endif + +#if ((defined(RTE_I2C0) && RTE_I2C0 && defined(I2C0)) || (defined(RTE_I2C1) && RTE_I2C1 && defined(I2C1)) || \ + (defined(RTE_I2C2) && RTE_I2C2 && defined(I2C2)) || (defined(RTE_I2C3) && RTE_I2C3 && defined(I2C3)) || \ + (defined(RTE_I2C4) && RTE_I2C4 && defined(I2C4))) + +#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (2)) + +/* + * ARMCC does not support split the data section automatically, so the driver + * needs to split the data to separate sections explicitly, to reduce codesize. + */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) +#endif + +typedef const struct _cmsis_i2c_resource +{ + I2C_Type *base; /*!< I2C peripheral base address. */ + uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ + +} cmsis_i2c_resource_t; + +typedef union _cmsis_i2c_handle +{ + i2c_master_handle_t master_handle; /*!< master Interupt transfer handle. */ + i2c_slave_handle_t slave_handle; /*!< slave Interupt transfer handle. */ +} cmsis_i2c_handle_t; + +typedef struct _cmsis_i2c_interrupt_driver_state +{ + cmsis_i2c_resource_t *resource; /*!< Basic I2C resource. */ + cmsis_i2c_handle_t *handle; + ARM_I2C_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_i2c_interrupt_driver_state_t; + +static const ARM_DRIVER_VERSION s_i2cDriverVersion = {ARM_I2C_API_VERSION, ARM_I2C_DRV_VERSION}; +static const ARM_I2C_CAPABILITIES s_i2cDriverCapabilities = { + 0, /*< supports 10-bit addressing */ +}; + +static ARM_DRIVER_VERSION I2Cx_GetVersion(void) +{ + return s_i2cDriverVersion; +} + +static ARM_I2C_CAPABILITIES I2Cx_GetCapabilities(void) +{ + return s_i2cDriverCapabilities; +} + +#endif + +#if ((defined(RTE_I2C0) && RTE_I2C0 && !(defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN)) || \ + (defined(RTE_I2C1) && RTE_I2C1 && !(defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN)) || \ + (defined(RTE_I2C2) && RTE_I2C2 && !(defined(RTE_I2C2_DMA_EN) && RTE_I2C2_DMA_EN)) || \ + (defined(RTE_I2C3) && RTE_I2C3 && !(defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN)) || \ + (defined(RTE_I2C4) && RTE_I2C4 && !(defined(RTE_I2C4_DMA_EN) && RTE_I2C4_DMA_EN))) + +static void KSDK_I2C_SLAVE_InterruptCallback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) +{ + uint32_t event = 0; + + switch (xfer->event) + { + case kI2C_SlaveCompletionEvent: /* Occurs after Slave Transmit/Receive operation has finished. */ + event = ARM_I2C_EVENT_TRANSFER_DONE; + break; + + default: + event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; + break; + } + + if (userData != NULL) + { + ((ARM_I2C_SignalEvent_t)userData)(event); + } +} + +static void KSDK_I2C_MASTER_InterruptCallback(I2C_Type *base, + i2c_master_handle_t *handle, + status_t status, + void *userData) +{ + uint32_t event = 0; + + switch (status) + { + case kStatus_Success: /* Occurs after Master Transmit/Receive operation has finished. */ + event = ARM_I2C_EVENT_TRANSFER_DONE; + break; + + case kStatus_I2C_Addr_Nak: /* Occurs in master mode when address is not acknowledged from slave.*/ + event = ARM_I2C_EVENT_ADDRESS_NACK; + break; + + case kStatus_I2C_ArbitrationLost: /* Occurs in master mode when arbitration is lost.*/ + event = ARM_I2C_EVENT_ARBITRATION_LOST; + break; + + default: + event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; + break; + } + + /* User data is actually CMSIS driver callback. */ + if (userData != NULL) + { + ((ARM_I2C_SignalEvent_t)userData)(event); + } +} + +static int32_t I2C_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + if (0U == (i2c->flags & (uint8_t)I2C_FLAG_INIT)) + { + i2c->cb_event = cb_event; /* cb_event is CMSIS driver callback. */ + i2c->flags = (uint8_t)I2C_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t I2C_InterruptUninitialize(cmsis_i2c_interrupt_driver_state_t *i2c) +{ + i2c->flags = (uint8_t)I2C_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t I2C_Master_InterruptTransmit( + uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + i2c_master_transfer_t masterXfer; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (i2c->handle->master_handle.state != 0U) + { + return ARM_DRIVER_ERROR_BUSY; + } + + /* Create master_handle */ + I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle), + KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event); + + masterXfer.slaveAddress = (uint8_t)addr; /*7-bit slave address.*/ + masterXfer.direction = kI2C_Write; /* Transfer direction.*/ + masterXfer.subaddress = 0U; /* Sub address */ + masterXfer.subaddressSize = 0U; /* Size of command buffer.*/ + masterXfer.data = (uint8_t *)data; /* Transfer buffer.*/ + masterXfer.dataSize = num; /* Transfer size.*/ + masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/ + + if ((i2c->resource->base->I2SR & 0x20U) != 0U) + { + masterXfer.flags |= (uint32_t)kI2C_TransferRepeatedStartFlag; + } + + if (xfer_pending) + { + masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag; + } + + status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + + case kStatus_I2C_Timeout: + ret = ARM_DRIVER_ERROR_TIMEOUT; + break; + + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t I2C_Master_InterruptReceive( + uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + i2c_master_transfer_t masterXfer; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (i2c->handle->master_handle.state != 0U) + { + return ARM_DRIVER_ERROR_BUSY; + } + + /* Create master_handle */ + I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle), + KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event); + + masterXfer.slaveAddress = (uint8_t)addr; /*7-bit slave address.*/ + masterXfer.direction = kI2C_Read; /* Transfer direction.*/ + masterXfer.subaddress = 0U; /* Sub address */ + masterXfer.subaddressSize = 0U; /* Size of command buffer.*/ + masterXfer.data = data; /* Transfer buffer.*/ + masterXfer.dataSize = num; /* Transfer size.*/ + masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/ + + if ((i2c->resource->base->I2SR & 0x20U) != 0U) + { + masterXfer.flags |= (uint32_t)kI2C_TransferRepeatedStartFlag; + } + + if (xfer_pending) + { + masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag; + } + + status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + + case kStatus_I2C_Timeout: + ret = ARM_DRIVER_ERROR_TIMEOUT; + break; + + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t I2C_Slave_InterruptTransmit(const uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + + /* Create slave_handle */ + I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback, + (void *)i2c->cb_event); + + status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle), + (uint32_t)kI2C_SlaveCompletionEvent); + + i2c->handle->slave_handle.transfer.data = + (uint8_t *)data; /* Pointer to buffer with data to transmit to I2C Master */ + i2c->handle->slave_handle.transfer.dataSize = num; /* Number of data bytes to transmit */ + i2c->handle->slave_handle.transfer.transferredCount = + 0; /* Number of bytes actually transferred since start or last repeated start. */ + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t I2C_Slave_InterruptReceive(uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + + /* Create slave_handle */ + I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback, + (void *)i2c->cb_event); + + status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle), + (uint32_t)kI2C_SlaveCompletionEvent); + + i2c->handle->slave_handle.transfer.data = data; /* Pointer to buffer with data to transmit to I2C Master */ + i2c->handle->slave_handle.transfer.dataSize = num; /* Number of data bytes to transmit */ + i2c->handle->slave_handle.transfer.transferredCount = + 0; /* Number of bytes actually transferred since start or last repeated start. */ + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t I2C_InterruptGetDataCount(cmsis_i2c_interrupt_driver_state_t *i2c) +{ + uint32_t cnt; /* The number of currently transferred data bytes */ + + if (i2c->handle->slave_handle.transfer.transferredCount != 0U) + { + cnt = i2c->handle->slave_handle.transfer.transferredCount; + } + else + { + cnt = (uint32_t) & (i2c->handle->master_handle).transferSize - (uint32_t) & + (i2c->handle->master_handle).transfer.dataSize; + } + + return (int32_t)cnt; +} + +static int32_t I2C_InterruptControl(uint32_t control, uint32_t arg, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + uint32_t baudRate_Bps = 0; + int32_t result = ARM_DRIVER_OK; + switch (control) + { + /* Set Own Slave Address; arg = slave address */ + case ARM_I2C_OWN_ADDRESS: + i2c->resource->base->IADR = (uint16_t)(arg << 1U); + break; + + /* Set Bus Speed; arg = bus speed */ + case ARM_I2C_BUS_SPEED: + switch (arg) + { + case ARM_I2C_BUS_SPEED_STANDARD: + baudRate_Bps = 100000; + break; + + case ARM_I2C_BUS_SPEED_FAST: + baudRate_Bps = 400000; + break; + + case ARM_I2C_BUS_SPEED_FAST_PLUS: + baudRate_Bps = 1000000; + break; + + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + + I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq()); + break; + + /* Not supported */ + case ARM_I2C_BUS_CLEAR: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + /* Aborts the data transfer between Master and Slave for Transmit or Receive */ + case ARM_I2C_ABORT_TRANSFER: + if (0U == (i2c->resource->base->IADR)) + { + /* Disable master interrupt and send STOP signal */ + (void)I2C_MasterTransferAbort(i2c->resource->base, &(i2c->handle->master_handle)); + + i2c->handle->master_handle.transferSize = 0; + i2c->handle->master_handle.transfer.data = NULL; + i2c->handle->master_handle.transfer.dataSize = 0; + } + /* If slave receive */ + else if (0U == (i2c->resource->base->I2SR & (uint32_t)kI2C_TransferDirectionFlag)) + { + i2c->resource->base->I2CR |= (uint8_t)I2C_I2CR_TXAK_MASK; + + while (i2c->handle->slave_handle.state != 0U) + { + } + /* Disable slave interrupt */ + + I2C_SlaveTransferAbort(i2c->resource->base, &(i2c->handle->slave_handle)); + + i2c->handle->slave_handle.transfer.data = NULL; + i2c->handle->slave_handle.transfer.dataSize = 0; + } + else + { + /* Avoid MISRA 15.7 violation */ + } + break; + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + return result; +} + +static int32_t I2C_InterruptPowerControl(ARM_POWER_STATE state, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + i2c_master_config_t masterConfig; + i2c_slave_config_t slaveConfig; + int32_t result = ARM_DRIVER_OK; + switch (state) + { + /* Terminates any pending data transfers, disable i2c moduole and i2c clock */ + case ARM_POWER_OFF: + if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U) + { + (void)I2C_InterruptControl(ARM_I2C_ABORT_TRANSFER, 0, i2c); + + I2C_MasterDeinit(i2c->resource->base); + + i2c->flags = (uint8_t)I2C_FLAG_INIT; + } + break; + /* Not supported */ + case ARM_POWER_LOW: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + /* Enable i2c moduole and i2c clock */ + case ARM_POWER_FULL: + if (i2c->flags == (uint8_t)I2C_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U) + { + /* Driver already powered */ + break; + } + + I2C_MasterGetDefaultConfig(&masterConfig); + I2C_MasterInit(i2c->resource->base, &masterConfig, i2c->resource->GetFreq()); + + I2C_SlaveGetDefaultConfig(&slaveConfig); + I2C_SlaveInit(i2c->resource->base, &slaveConfig); + + i2c->flags |= (uint8_t)I2C_FLAG_POWER; + break; + + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + + return result; +} + +static ARM_I2C_STATUS I2C_InterruptGetStatus(cmsis_i2c_interrupt_driver_state_t *i2c) +{ + ARM_I2C_STATUS stat = {0}; + uint32_t ksdk_i2c_status = I2C_SlaveGetStatusFlags(i2c->resource->base); + uint32_t dataSize; + + if (0U == (i2c->resource->base->IADR)) + { + dataSize = i2c->handle->master_handle.transfer.dataSize; + stat.direction = (uint32_t)((ksdk_i2c_status & (uint32_t)kI2C_TransferDirectionFlag) != + 0U); /* Direction: 0=Transmitter, 1=Receiver.*/ + stat.mode = 1UL; /* Mode: 0=Slave, 1=Master.*/ + } + else + { + dataSize = i2c->handle->slave_handle.transfer.dataSize; + stat.direction = (uint32_t)((ksdk_i2c_status & (uint32_t)kI2C_TransferDirectionFlag) != + 0U); /* Direction: 0=Transmitter, 1=Receiver.*/ + stat.mode = 0; /* Mode: 0=Slave, 1=Master.*/ + } + + if (dataSize != 0U) + { + stat.busy = 1; /* Busy flag.*/ + } + else + { + stat.busy = 0; /* Busy flag.*/ + } + + stat.arbitration_lost = (uint32_t)((ksdk_i2c_status & (uint32_t)kI2C_ArbitrationLostFlag) != + 0U); /* Master lost arbitration (cleared on start of next Master operation)*/ + + return stat; +} + +#endif + +#if defined(I2C0) && defined(RTE_I2C0) && RTE_I2C0 +/* User needs to provide the implementation for I2C0_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C0_GetFreq(void); + +static cmsis_i2c_resource_t I2C0_Resource = {I2C0, I2C0_GetFreq}; + +static cmsis_i2c_handle_t I2C0_handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c0_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = { +#endif + &I2C0_Resource, + &I2C0_handle, + +}; + +static int32_t I2C0_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C0_PIN_INIT + RTE_I2C0_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C0_InterruptDriverState); +} + +static int32_t I2C0_InterruptUninitialize(void) +{ +#ifdef RTE_I2C0_PIN_DEINIT + RTE_I2C0_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C0_InterruptDriverState); +} + +static int32_t I2C0_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C0_InterruptDriverState); +} + +static int32_t I2C0_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C0_InterruptDriverState); +} + +static int32_t I2C0_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C0_InterruptDriverState); +} + +static int32_t I2C0_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C0_InterruptDriverState); +} + +static int32_t I2C0_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C0_InterruptDriverState); +} + +static int32_t I2C0_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C0_InterruptDriverState); +} + +static int32_t I2C0_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C0_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C0_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C0_InterruptDriverState); +} + +ARM_DRIVER_I2C Driver_I2C0 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, + I2C0_InterruptInitialize, + I2C0_InterruptUninitialize, + I2C0_InterruptPowerControl, + I2C0_Master_InterruptTransmit, + I2C0_Master_InterruptReceive, + I2C0_Slave_InterruptTransmit, + I2C0_Slave_InterruptReceive, + I2C0_InterruptGetDataCount, + I2C0_InterruptControl, + I2C0_InterruptGetStatus}; + +#endif + +#if defined(I2C1) && defined(RTE_I2C1) && RTE_I2C1 + +/* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C1_GetFreq(void); + +static cmsis_i2c_resource_t I2C1_Resource = {I2C1, I2C1_GetFreq}; +static cmsis_i2c_handle_t I2C1_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c1_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = { +#endif + &I2C1_Resource, + &I2C1_Handle, +}; + +static int32_t I2C1_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C1_PIN_INIT + RTE_I2C1_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C1_InterruptDriverState); +} + +static int32_t I2C1_InterruptUninitialize(void) +{ +#ifdef RTE_I2C1_PIN_DEINIT + RTE_I2C1_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C1_InterruptDriverState); +} + +static int32_t I2C1_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C1_InterruptDriverState); +} + +static int32_t I2C1_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C1_InterruptDriverState); +} + +static int32_t I2C1_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C1_InterruptDriverState); +} + +static int32_t I2C1_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C1_InterruptDriverState); +} + +static int32_t I2C1_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C1_InterruptDriverState); +} + +static int32_t I2C1_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C1_InterruptDriverState); +} + +static int32_t I2C1_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C1_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C1_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C1_InterruptDriverState); +} + +ARM_DRIVER_I2C Driver_I2C1 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, + I2C1_InterruptInitialize, + I2C1_InterruptUninitialize, + I2C1_InterruptPowerControl, + I2C1_Master_InterruptTransmit, + I2C1_Master_InterruptReceive, + I2C1_Slave_InterruptTransmit, + I2C1_Slave_InterruptReceive, + I2C1_InterruptGetDataCount, + I2C1_InterruptControl, + I2C1_InterruptGetStatus}; + +#endif + +#if defined(I2C2) && defined(RTE_I2C2) && RTE_I2C2 + +/* User needs to provide the implementation for I2C2_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C2_GetFreq(void); + +static cmsis_i2c_resource_t I2C2_Resource = {I2C2, I2C2_GetFreq}; + +static cmsis_i2c_handle_t I2C2_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c2_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = { +#endif + &I2C2_Resource, + &I2C2_Handle, + +}; + +static int32_t I2C2_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C2_PIN_INIT + RTE_I2C2_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C2_InterruptDriverState); +} + +static int32_t I2C2_InterruptUninitialize(void) +{ +#ifdef RTE_I2C2_PIN_DEINIT + RTE_I2C2_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C2_InterruptDriverState); +} + +static int32_t I2C2_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C2_InterruptDriverState); +} + +static int32_t I2C2_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C2_InterruptDriverState); +} + +static int32_t I2C2_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C2_InterruptDriverState); +} + +static int32_t I2C2_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C2_InterruptDriverState); +} + +static int32_t I2C2_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C2_InterruptDriverState); +} + +static int32_t I2C2_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C2_InterruptDriverState); +} + +static int32_t I2C2_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C2_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C2_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C2_InterruptDriverState); +} + +ARM_DRIVER_I2C Driver_I2C2 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, + I2C2_InterruptInitialize, + I2C2_InterruptUninitialize, + I2C2_InterruptPowerControl, + I2C2_Master_InterruptTransmit, + I2C2_Master_InterruptReceive, + I2C2_Slave_InterruptTransmit, + I2C2_Slave_InterruptReceive, + I2C2_InterruptGetDataCount, + I2C2_InterruptControl, + I2C2_InterruptGetStatus}; + +#endif + +#if defined(I2C3) && defined(RTE_I2C3) && RTE_I2C3 + +/* User needs to provide the implementation for I2C3_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C3_GetFreq(void); + +static cmsis_i2c_resource_t I2C3_Resource = {I2C3, I2C3_GetFreq}; +static cmsis_i2c_handle_t I2C3_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c3_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = { +#endif + &I2C3_Resource, + &I2C3_Handle, +}; + +static int32_t I2C3_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C3_PIN_INIT + RTE_I2C3_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C3_InterruptDriverState); +} + +static int32_t I2C3_InterruptUninitialize(void) +{ +#ifdef RTE_I2C3_PIN_DEINIT + RTE_I2C3_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C3_InterruptDriverState); +} + +static int32_t I2C3_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C3_InterruptDriverState); +} + +static int32_t I2C3_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C3_InterruptDriverState); +} + +static int32_t I2C3_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C3_InterruptDriverState); +} + +static int32_t I2C3_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C3_InterruptDriverState); +} + +static int32_t I2C3_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C3_InterruptDriverState); +} + +static int32_t I2C3_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C3_InterruptDriverState); +} + +static int32_t I2C3_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C3_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C3_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C3_InterruptDriverState); +} + +ARM_DRIVER_I2C Driver_I2C3 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, + I2C3_InterruptInitialize, + I2C3_InterruptUninitialize, + I2C3_InterruptPowerControl, + I2C3_Master_InterruptTransmit, + I2C3_Master_InterruptReceive, + I2C3_Slave_InterruptTransmit, + I2C3_Slave_InterruptReceive, + I2C3_InterruptGetDataCount, + I2C3_InterruptControl, + I2C3_InterruptGetStatus}; + +#endif + +#if defined(I2C4) && defined(RTE_I2C4) && RTE_I2C4 + +/* User needs to provide the implementation for I2C4_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C4_GetFreq(void); + +static cmsis_i2c_resource_t I2C4_Resource = {I2C4, I2C4_GetFreq}; +static cmsis_i2c_handle_t I2C4_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c3_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState = { +#endif + &I2C4_Resource, + &I2C4_Handle, +}; + +static int32_t I2C4_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C4_PIN_INIT + RTE_I2C4_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C4_InterruptDriverState); +} + +static int32_t I2C4_InterruptUninitialize(void) +{ +#ifdef RTE_I2C4_PIN_DEINIT + RTE_I2C4_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C4_InterruptDriverState); +} + +static int32_t I2C4_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C4_InterruptDriverState); +} + +static int32_t I2C4_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C4_InterruptDriverState); +} + +static int32_t I2C4_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C4_InterruptDriverState); +} + +static int32_t I2C4_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C4_InterruptDriverState); +} + +static int32_t I2C4_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C4_InterruptDriverState); +} + +static int32_t I2C4_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C4_InterruptDriverState); +} + +static int32_t I2C4_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C4_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C4_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C4_InterruptDriverState); +} + +ARM_DRIVER_I2C Driver_I2C4 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, + I2C4_InterruptInitialize, + I2C4_InterruptUninitialize, + I2C4_InterruptPowerControl, + I2C4_Master_InterruptTransmit, + I2C4_Master_InterruptReceive, + I2C4_Slave_InterruptTransmit, + I2C4_Slave_InterruptReceive, + I2C4_InterruptGetDataCount, + I2C4_InterruptControl, + I2C4_InterruptGetStatus}; + +#endif diff --git a/devices/MIMX8MQ6/cmsis_drivers/fsl_i2c_cmsis.h b/devices/MIMX8MQ6/cmsis_drivers/fsl_i2c_cmsis.h new file mode 100644 index 000000000..80fad4564 --- /dev/null +++ b/devices/MIMX8MQ6/cmsis_drivers/fsl_i2c_cmsis.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2020 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _FSL_I2C_CMSIS_H_ +#define _FSL_I2C_CMSIS_H_ +#include "fsl_common.h" +#include "Driver_I2C.h" +#include "RTE_Device.h" +#include "fsl_i2c.h" + +#if defined(I2C0) && defined(RTE_I2C0) && RTE_I2C0 +extern ARM_DRIVER_I2C Driver_I2C0; +#endif + +#if defined(I2C1) && defined(RTE_I2C1) && RTE_I2C1 +extern ARM_DRIVER_I2C Driver_I2C1; +#endif + +#if defined(I2C2) && defined(RTE_I2C2) && RTE_I2C2 +extern ARM_DRIVER_I2C Driver_I2C2; +#endif + +#if defined(I2C3) && defined(RTE_I2C3) && RTE_I2C3 +extern ARM_DRIVER_I2C Driver_I2C3; +#endif + +#if defined(I2C4) && defined(RTE_I2C4) && RTE_I2C4 +extern ARM_DRIVER_I2C Driver_I2C4; +#endif + +/* I2C Driver state flags */ +#define I2C_FLAG_UNINIT (0UL) +#define I2C_FLAG_INIT (1UL << 0) +#define I2C_FLAG_POWER (1UL << 1) + +#endif diff --git a/devices/MIMX8MQ6/cmsis_drivers/fsl_uart_cmsis.c b/devices/MIMX8MQ6/cmsis_drivers/fsl_uart_cmsis.c new file mode 100644 index 000000000..e6a92b1a3 --- /dev/null +++ b/devices/MIMX8MQ6/cmsis_drivers/fsl_uart_cmsis.c @@ -0,0 +1,1622 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017，2020 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_uart_cmsis.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iuart_cmsis" +#endif + +#if ((defined(UART1) && defined(RTE_USART1) && RTE_USART1) || (defined(UART2) && defined(RTE_USART2) && RTE_USART2) || \ + (defined(UART3) && defined(RTE_USART3) && RTE_USART3) || (RTE_USART4 && defined(UART4))) + +#define ARM_UART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (1)) + +/* + * ARMCC does not support split the data section automatically, so the driver + * needs to split the data to separate sections explicitly, to reduce codesize. + */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) +#endif + +typedef const struct _cmsis_uart_resource +{ + UART_Type *base; /*!< UART peripheral base address. */ + uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ +} cmsis_uart_resource_t; + +typedef struct _cmsis_uart_non_blocking_driver_state +{ + cmsis_uart_resource_t *resource; /*!< Basic UART resource. */ + uart_handle_t *handle; /*!< Interupt transfer handle. */ + ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_uart_non_blocking_driver_state_t; +#if (defined(FSL_FEATURE_SOC_SDMA_COUNT) && FSL_FEATURE_SOC_SDMA_COUNT) +typedef struct _cmsis_uart_sdma_resource +{ + SDMAARM_Type *txSdmaBase; /*!< SDMA peripheral base address for TX. */ + uint32_t txSdmaChannel; /*!< SDMA channel for UART TX. */ + uint32_t txSdmaRequest; /*!< TX SDMA request source. */ + uint8_t txSdmaPriority; /*!< TX SDMA channel priority. */ + + SDMAARM_Type *rxSdmaBase; /*!< SDMA peripheral base address for RX. */ + uint32_t rxSdmaChannel; /*!< SDMA channel for UART RX. */ + uint32_t rxSdmaRequest; /*!< RX SDMA request source. */ + uint8_t rxSdmaPriority; /*!< RX SDMA channel priority. */ +} cmsis_uart_sdma_resource_t; + +typedef struct _cmsis_uart_sdma_driver_state +{ + cmsis_uart_resource_t *resource; /*!< UART basic resource. */ + cmsis_uart_sdma_resource_t *sdmaResource; /*!< UART SDMA resource. */ + uart_sdma_handle_t *handle; /*!< UART SDMA transfer handle. */ + sdma_handle_t *rxHandle; /*!< SDMA RX handle. */ + sdma_handle_t *txHandle; /*!< SDMA TX handle. */ + ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_uart_sdma_driver_state_t; +#endif + +enum _uart_transfer_states +{ + kUART_TxIdle, /*!< TX idle. */ + kUART_TxBusy, /*!< TX busy. */ + kUART_RxIdle, /*!< RX idle. */ + kUART_RxBusy /*!< RX busy. */ +}; + +/* Driver Version */ +static const ARM_DRIVER_VERSION s_uartDriverVersion = {ARM_USART_API_VERSION, ARM_UART_DRV_VERSION}; + +static const ARM_USART_CAPABILITIES s_uartDriverCapabilities = { + 1, /* supports UART (Asynchronous) mode */ + 0, /* supports Synchronous Master mode */ + 0, /* supports Synchronous Slave mode */ + 0, /* supports UART Single-wire mode */ + 0, /* supports UART IrDA mode */ + 0, /* supports UART Smart Card mode */ + 0, /* Smart Card Clock generator */ + 0, /* RTS Flow Control available */ + 0, /* CTS Flow Control available */ + 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ + 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ + 0, /* RTS Line: 0=not available, 1=available */ + 0, /* CTS Line: 0=not available, 1=available */ + 0, /* DTR Line: 0=not available, 1=available */ + 0, /* DSR Line: 0=not available, 1=available */ + 0, /* DCD Line: 0=not available, 1=available */ + 0, /* RI Line: 0=not available, 1=available */ + 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ + 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ + 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ + 0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */ +}; + +/* + * Common control function used by UART_NonBlockingControl/UART_DmaControl + */ +static int32_t UART_CommonControl(uint32_t control, + uint32_t arg, + cmsis_uart_resource_t *resource, + uint8_t *isConfigured) +{ + uart_config_t config; + int32_t result = ARM_DRIVER_OK; + bool isContinue = false; + + UART_GetDefaultConfig(&config); + + switch (control & ARM_USART_CONTROL_Msk) + { + case ARM_USART_MODE_ASYNCHRONOUS: + /* USART Baudrate */ + config.baudRate_Bps = arg; + isContinue = true; + break; + + /* TX/RX IO is controlled in application layer. */ + case ARM_USART_CONTROL_TX: + if (0U != arg) + { + UART_EnableTx(resource->base, true); + } + else + { + UART_EnableTx(resource->base, false); + } + result = ARM_DRIVER_OK; + break; + + case ARM_USART_CONTROL_RX: + if (0U != arg) + { + UART_EnableRx(resource->base, true); + } + else + { + UART_EnableRx(resource->base, false); + } + + result = ARM_DRIVER_OK; + break; + + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + if (!isContinue) + { + return result; + } + + switch (control & ARM_USART_DATA_BITS_Msk) + { + case ARM_USART_DATA_BITS_7: + config.dataBitsCount = kUART_SevenDataBits; + break; + + case ARM_USART_DATA_BITS_8: + config.dataBitsCount = kUART_EightDataBits; + break; + + default: + result = ARM_USART_ERROR_DATA_BITS; + break; + } + if (result == ARM_USART_ERROR_DATA_BITS) + { + return result; + } + + switch (control & ARM_USART_PARITY_Msk) + { + case ARM_USART_PARITY_NONE: + config.parityMode = kUART_ParityDisabled; + break; + case ARM_USART_PARITY_EVEN: + config.parityMode = kUART_ParityEven; + break; + case ARM_USART_PARITY_ODD: + config.parityMode = kUART_ParityOdd; + break; + default: + result = ARM_USART_ERROR_PARITY; + break; + } + if (result == ARM_USART_ERROR_PARITY) + { + return result; + } + + switch (control & (uint32_t)ARM_USART_STOP_BITS_Msk) + { + case ARM_USART_STOP_BITS_1: + /* The GetDefaultConfig has already set for this case. */ + break; + case ARM_USART_STOP_BITS_2: + config.stopBitCount = kUART_TwoStopBit; + break; + default: + result = ARM_USART_ERROR_STOP_BITS; + break; + } + + /* If UART is already configured, deinit it first. */ + if (((*isConfigured) & (uint8_t)USART_FLAG_CONFIGURED) != 0U) + { + UART_Deinit(resource->base); + *isConfigured &= ~(uint8_t)(USART_FLAG_CONFIGURED); + } + + config.enableTx = true; + config.enableRx = true; + + if (kStatus_UART_BaudrateNotSupport == UART_Init(resource->base, &config, resource->GetFreq())) + { + result = ARM_USART_ERROR_BAUDRATE; + } + else + { + *isConfigured |= USART_FLAG_CONFIGURED; + } + return result; +} + +static ARM_DRIVER_VERSION UARTx_GetVersion(void) +{ + return s_uartDriverVersion; +} + +static ARM_USART_CAPABILITIES UARTx_GetCapabilities(void) +{ + return s_uartDriverCapabilities; +} + +static int32_t UARTx_SetModemControl(ARM_USART_MODEM_CONTROL control) +{ + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_USART_MODEM_STATUS UARTx_GetModemStatus(void) +{ + ARM_USART_MODEM_STATUS modem_status = {0}; + + modem_status.cts = 0U; + modem_status.dsr = 0U; + modem_status.ri = 0U; + modem_status.dcd = 0U; + modem_status.reserved = 0U; + + return modem_status; +} + +#endif + +#if ((defined(UART1) && defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN) || \ + (defined(UART2) && defined(RTE_USART2_DMA_EN) && RTE_USART2_DMA_EN) || \ + (defined(UART3) && defined(RTE_USART3_DMA_EN) && RTE_USART3_DMA_EN) || \ + (defined(UART4) && defined(RTE_USART4_DMA_EN) && RTE_USART4_DMA_EN) || \ + (defined(UART5) && defined(RTE_USART5_DMA_EN) && RTE_USART5_DMA_EN)) + +static void KSDK_UART_SdmaCallback(UART_Type *base, uart_sdma_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + if (kStatus_UART_TxIdle == status) + { + event = ARM_USART_EVENT_SEND_COMPLETE; + } + else if (kStatus_UART_RxIdle == status) + { + event = ARM_USART_EVENT_RECEIVE_COMPLETE; + } + else + { + ; /* Intentional empty */ + } + + /* User data is actually CMSIS driver callback. */ + if ((0U != event) && (NULL != userData)) + { + ((ARM_USART_SignalEvent_t)userData)(event); + } +} + +static int32_t UART_SdmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_uart_sdma_driver_state_t *uart) +{ + if ((uart->flags & (uint8_t)USART_FLAG_INIT) == 0U) + { + uart->cb_event = cb_event; + uart->flags = (uint8_t)USART_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t UART_SdmaUninitialize(cmsis_uart_sdma_driver_state_t *uart) +{ + uart->flags = (uint8_t)USART_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t UART_SdmaPowerControl(ARM_POWER_STATE state, + cmsis_uart_sdma_driver_state_t *uart, + sdma_context_data_t *rxContext, + sdma_context_data_t *txContext) +{ + status_t status; + uart_config_t config; + int32_t result = ARM_DRIVER_OK; + + switch (state) + { + case ARM_POWER_OFF: + if ((uart->flags & (uint8_t)USART_FLAG_POWER) != 0U) + { + UART_Deinit(uart->resource->base); + uart->flags = USART_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + case ARM_POWER_FULL: + /* Must be initialized first. */ + if (uart->flags == (uint8_t)USART_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if ((uart->flags & (uint8_t)USART_FLAG_POWER) != 0U) + { + /* Driver already powered */ + break; + } + + UART_GetDefaultConfig(&config); + config.enableTx = true; + config.enableRx = true; + + /* Set up DMA setting. */ + SDMA_CreateHandle(uart->txHandle, uart->sdmaResource->txSdmaBase, uart->sdmaResource->txSdmaChannel, + txContext); + SDMA_CreateHandle(uart->rxHandle, uart->sdmaResource->rxSdmaBase, uart->sdmaResource->rxSdmaChannel, + rxContext); + SDMA_SetChannelPriority(uart->sdmaResource->txSdmaBase, uart->sdmaResource->txSdmaChannel, + uart->sdmaResource->txSdmaPriority); + SDMA_SetChannelPriority(uart->sdmaResource->rxSdmaBase, uart->sdmaResource->rxSdmaChannel, + uart->sdmaResource->rxSdmaPriority); + /* Setup the UART. */ + status = UART_Init(uart->resource->base, &config, uart->resource->GetFreq()); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + /* Create UART SDMA handle. */ + UART_TransferCreateHandleSDMA(uart->resource->base, uart->handle, KSDK_UART_SdmaCallback, + (void *)uart->cb_event, uart->txHandle, uart->rxHandle, + uart->sdmaResource->txSdmaRequest, uart->sdmaResource->rxSdmaRequest); + + uart->flags = (uart->flags | (uint8_t)(USART_FLAG_POWER | (uint8_t)USART_FLAG_CONFIGURED)); + break; + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + + return result; +} + +static int32_t UART_SdmaSend(const void *data, uint32_t num, cmsis_uart_sdma_driver_state_t *uart) +{ + int32_t ret; + status_t status; + uart_transfer_t xfer; + + xfer.data = (uint8_t *)(uint32_t)data; + xfer.dataSize = num; + + status = UART_SendSDMA(uart->resource->base, uart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_UART_RxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t UART_SdmaReceive(void *data, uint32_t num, cmsis_uart_sdma_driver_state_t *uart) +{ + int32_t ret; + status_t status; + uart_transfer_t xfer; + + xfer.data = data; + xfer.dataSize = num; + + status = UART_ReceiveSDMA(uart->resource->base, uart->handle, &xfer); + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_UART_TxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t UART_SdmaTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_uart_sdma_driver_state_t *uart) +{ + /* Only in synchronous mode */ + return ARM_DRIVER_ERROR; +} + +static uint32_t UART_SdmaGetTxCount(cmsis_uart_sdma_driver_state_t *uart) +{ + /* Not supported by current driver. */ + return 0; +} + +static uint32_t UART_SdmaGetRxCount(cmsis_uart_sdma_driver_state_t *uart) +{ + /* Not supported by current driver. */ + return 0; +} + +static int32_t UART_SdmaControl(uint32_t control, uint32_t arg, cmsis_uart_sdma_driver_state_t *uart) +{ + /* Must be power on. */ + if ((uart->flags & (uint8_t)USART_FLAG_POWER) == 0U) + { + return ARM_DRIVER_ERROR; + } + + /* Does not support these features. */ + if ((control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) != 0U) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + int32_t result = ARM_DRIVER_OK; + bool isContinue = false; + switch (control & ARM_USART_CONTROL_Msk) + { + /* Abort Send */ + case ARM_USART_ABORT_SEND: + UART_TransferAbortSendSDMA(uart->resource->base, uart->handle); + result = ARM_DRIVER_OK; + break; + + /* Abort receive */ + case ARM_USART_ABORT_RECEIVE: + UART_TransferAbortReceiveSDMA(uart->resource->base, uart->handle); + result = ARM_DRIVER_OK; + break; + default: + isContinue = true; + break; + } + + if (isContinue) + { + result = UART_CommonControl(control, arg, uart->resource, &uart->flags); + } + return result; +} + +static ARM_USART_STATUS UART_SdmaGetStatus(cmsis_uart_sdma_driver_state_t *uart) +{ + ARM_USART_STATUS stat = {0}; + + stat.tx_busy = ((uint8_t)kUART_TxBusy == uart->handle->txState) ? (1U) : (0U); + stat.rx_busy = ((uint8_t)kUART_RxBusy == uart->handle->rxState) ? (1U) : (0U); + + stat.tx_underflow = 0U; + stat.rx_overflow = (uint32_t)UART_GetStatusFlag(uart->resource->base, (uint32_t)kUART_RxOverrunFlag); + stat.rx_break = (uint32_t)UART_GetStatusFlag(uart->resource->base, (uint32_t)kUART_BreakDetectFlag); + stat.rx_framing_error = (uint8_t)UART_GetStatusFlag(uart->resource->base, (uint8_t)kUART_FrameErrorFlag); + stat.rx_parity_error = (uint32_t)UART_GetStatusFlag(uart->resource->base, (uint32_t)kUART_ParityErrorFlag); + stat.reserved = 0U; + + return stat; +} +#endif + +#if ((defined(UART1) && defined(RTE_USART1) && RTE_USART1 && !(defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN)) || \ + (defined(UART2) && defined(RTE_USART2) && RTE_USART2 && !(defined(RTE_USART2_DMA_EN) && RTE_USART2_DMA_EN)) || \ + (defined(UART3) && defined(RTE_USART3) && RTE_USART3 && !(defined(RTE_USART3_DMA_EN) && RTE_USART3_DMA_EN)) || \ + (defined(UART4) && defined(RTE_USART4) && RTE_USART4 && !(defined(RTE_USART4_DMA_EN) && RTE_USART4_DMA_EN))) + +static void KSDK_UART_NonBlockingCallback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + if (kStatus_UART_TxIdle == status) + { + event = ARM_USART_EVENT_SEND_COMPLETE; + } + if (kStatus_UART_RxIdle == status) + { + event = ARM_USART_EVENT_RECEIVE_COMPLETE; + } + if (kStatus_UART_RxHardwareOverrun == status) + { + event = ARM_USART_EVENT_RX_OVERFLOW; + } + + /* User data is actually CMSIS driver callback. */ + if ((0U != event) && (userData != NULL)) + { + ((ARM_USART_SignalEvent_t)userData)(event); + } +} + +static int32_t UART_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event, + cmsis_uart_non_blocking_driver_state_t *uart) +{ + if (0U == (uart->flags & (uint8_t)USART_FLAG_INIT)) + { + uart->cb_event = cb_event; + uart->flags = (uint8_t)USART_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t UART_NonBlockingUninitialize(cmsis_uart_non_blocking_driver_state_t *uart) +{ + uart->flags = (uint8_t)USART_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t UART_NonBlockingPowerControl(ARM_POWER_STATE state, cmsis_uart_non_blocking_driver_state_t *uart) +{ + status_t status; + uart_config_t config; + int32_t result = ARM_DRIVER_OK; + + switch (state) + { + case ARM_POWER_OFF: + if ((uart->flags & (uint8_t)USART_FLAG_POWER) != 0U) + { + UART_Deinit(uart->resource->base); + uart->flags = USART_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + case ARM_POWER_FULL: + /* Must be initialized first. */ + if (uart->flags == USART_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if ((uart->flags & (uint8_t)USART_FLAG_POWER) != 0U) + { + /* Driver already powered */ + break; + } + + UART_GetDefaultConfig(&config); + config.enableTx = true; + config.enableRx = true; + + status = UART_Init(uart->resource->base, &config, uart->resource->GetFreq()); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + UART_TransferCreateHandle(uart->resource->base, uart->handle, KSDK_UART_NonBlockingCallback, + (void *)uart->cb_event); + uart->flags |= (USART_FLAG_POWER | USART_FLAG_CONFIGURED); + break; + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + + return result; +} + +static int32_t UART_NonBlockingSend(const void *data, uint32_t num, cmsis_uart_non_blocking_driver_state_t *uart) +{ + int32_t ret; + status_t status; + uart_transfer_t xfer; + + xfer.data = (uint8_t *)data; + xfer.dataSize = num; + + status = UART_TransferSendNonBlocking(uart->resource->base, uart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_UART_RxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t UART_NonBlockingReceive(void *data, uint32_t num, cmsis_uart_non_blocking_driver_state_t *uart) +{ + int32_t ret; + status_t status; + uart_transfer_t xfer; + + xfer.data = data; + xfer.dataSize = num; + + status = UART_TransferReceiveNonBlocking(uart->resource->base, uart->handle, &xfer, NULL); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_UART_TxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t UART_NonBlockingTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_uart_non_blocking_driver_state_t *uart) +{ + /* Only in synchronous mode */ + return ARM_DRIVER_ERROR; +} + +static uint32_t UART_NonBlockingGetTxCount(cmsis_uart_non_blocking_driver_state_t *uart) +{ + uint32_t cnt; + + /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */ + if (kStatus_NoTransferInProgress == UART_TransferGetSendCount(uart->resource->base, uart->handle, &cnt)) + { + cnt = uart->handle->txDataSizeAll; + } + + return cnt; +} + +static uint32_t UART_NonBlockingGetRxCount(cmsis_uart_non_blocking_driver_state_t *uart) +{ + uint32_t cnt; + + if (kStatus_NoTransferInProgress == UART_TransferGetReceiveCount(uart->resource->base, uart->handle, &cnt)) + { + cnt = uart->handle->rxDataSizeAll; + } + + return cnt; +} + +static int32_t UART_NonBlockingControl(uint32_t control, uint32_t arg, cmsis_uart_non_blocking_driver_state_t *uart) +{ + int32_t result = ARM_DRIVER_OK; + bool isContinue = false; + /* Must be power on. */ + if (0U == (uart->flags & (uint8_t)USART_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + /* Does not support these features. */ + if ((control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) != 0U) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_CONTROL_Msk) + { + /* Abort Send */ + case ARM_USART_ABORT_SEND: + UART_TransferAbortSend(uart->resource->base, uart->handle); + result = ARM_DRIVER_OK; + break; + + /* Abort receive */ + case ARM_USART_ABORT_RECEIVE: + UART_TransferAbortReceive(uart->resource->base, uart->handle); + result = ARM_DRIVER_OK; + break; + default: + isContinue = true; + break; + } + + if (isContinue) + { + result = UART_CommonControl(control, arg, uart->resource, &uart->flags); + } + return result; +} + +static ARM_USART_STATUS UART_NonBlockingGetStatus(cmsis_uart_non_blocking_driver_state_t *uart) +{ + ARM_USART_STATUS stat = {0}; + + stat.tx_busy = (((uint8_t)kUART_TxBusy == uart->handle->txState) ? (1U) : (0U)); + stat.rx_busy = (((uint8_t)kUART_RxBusy == uart->handle->rxState) ? (1U) : (0U)); + + stat.tx_underflow = 0U; + stat.rx_overflow = (uint32_t)UART_GetStatusFlag(uart->resource->base, (uint32_t)kUART_RxOverrunFlag); + stat.rx_break = (uint32_t)UART_GetStatusFlag(uart->resource->base, (uint32_t)kUART_BreakDetectFlag); + stat.rx_framing_error = (uint32_t)UART_GetStatusFlag(uart->resource->base, (uint32_t)kUART_FrameErrorFlag); + stat.rx_parity_error = (uint32_t)UART_GetStatusFlag(uart->resource->base, (uint32_t)kUART_ParityErrorFlag); + stat.reserved = 0U; + + return stat; +} + +#endif + +#if defined(UART1) && defined(RTE_USART1) && RTE_USART1 + +/* User needs to provide the implementation for UART1_GetFreq/InitPins/DeinitPins + * in the application for enabling according instance. + */ +extern uint32_t UART1_GetFreq(void); + +static cmsis_uart_resource_t UART1_Resource = {UART1, UART1_GetFreq}; + +#if defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN + +static cmsis_uart_sdma_resource_t UART1_SdmaResource = { + RTE_USART1_SDMA_TX_DMA_BASE, RTE_USART1_SDMA_TX_CH, RTE_USART1_SDMA_TX_REQUEST, RTE_USART1_SDMA_TX_PRIORITY, + RTE_USART1_SDMA_RX_DMA_BASE, RTE_USART1_SDMA_RX_CH, RTE_USART1_SDMA_RX_REQUEST, RTE_USART1_SDMA_RX_PRIORITY, +}; + +AT_NONCACHEABLE_SECTION_ALIGN(static uart_sdma_handle_t UART1_SdmaHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t UART1_SdmaTxHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t UART1_SdmaRxHandle, 4); + +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t UART1_SdmaTxContext, 4); +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t UART1_SdmaRxContext, 4); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("uart1_sdma_driver_state") +static cmsis_uart_sdma_driver_state_t UART1_SdmaDriverState = { +#else +static cmsis_uart_sdma_driver_state_t UART1_SdmaDriverState = { +#endif + &UART1_Resource, &UART1_SdmaResource, &UART1_SdmaHandle, &UART1_SdmaRxHandle, &UART1_SdmaTxHandle, +}; + +static int32_t UART1_SdmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART1_PIN_INIT + RTE_USART1_PIN_INIT(); +#endif + return UART_SdmaInitialize(cb_event, &UART1_SdmaDriverState); +} + +static int32_t UART1_SdmaUninitialize(void) +{ +#ifdef RTE_USART1_PIN_DEINIT + RTE_USART1_PIN_DEINIT(); +#endif + return UART_SdmaUninitialize(&UART1_SdmaDriverState); +} + +static int32_t UART1_SdmaPowerControl(ARM_POWER_STATE state) +{ + return UART_SdmaPowerControl(state, &UART1_SdmaDriverState, &UART1_SdmaRxContext, &UART1_SdmaTxContext); +} + +static int32_t UART1_SdmaSend(const void *data, uint32_t num) +{ + return UART_SdmaSend(data, num, &UART1_SdmaDriverState); +} + +static int32_t UART1_SdmaReceive(void *data, uint32_t num) +{ + return UART_SdmaReceive(data, num, &UART1_SdmaDriverState); +} + +static int32_t UART1_SdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return UART_SdmaTransfer(data_out, data_in, num, &UART1_SdmaDriverState); +} + +static uint32_t UART1_SdmaGetTxCount(void) +{ + return UART_SdmaGetTxCount(&UART1_SdmaDriverState); +} + +static uint32_t UART1_SdmaGetRxCount(void) +{ + return UART_SdmaGetRxCount(&UART1_SdmaDriverState); +} + +static int32_t UART1_SdmaControl(uint32_t control, uint32_t arg) +{ + return UART_SdmaControl(control, arg, &UART1_SdmaDriverState); +} + +static ARM_USART_STATUS UART1_SdmaGetStatus(void) +{ + return UART_SdmaGetStatus(&UART1_SdmaDriverState); +} + +#else + +static uart_handle_t UART1_Handle; + +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) +static uint8_t uart1_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("uart1_non_blocking_driver_state") +static cmsis_uart_non_blocking_driver_state_t UART1_NonBlockingDriverState = { +#else +static cmsis_uart_non_blocking_driver_state_t UART1_NonBlockingDriverState = { +#endif + &UART1_Resource, + &UART1_Handle, +}; + +static int32_t UART1_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART1_PIN_INIT + RTE_USART1_PIN_INIT(); +#endif + return UART_NonBlockingInitialize(cb_event, &UART1_NonBlockingDriverState); +} + +static int32_t UART1_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART1_PIN_DEINIT + RTE_USART1_PIN_DEINIT(); +#endif + return UART_NonBlockingUninitialize(&UART1_NonBlockingDriverState); +} + +static int32_t UART1_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = UART_NonBlockingPowerControl(state, &UART1_NonBlockingDriverState); + +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (UART1_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + UART_TransferStartRingBuffer(UART1_NonBlockingDriverState.resource->base, UART1_NonBlockingDriverState.handle, + uart1_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t UART1_NonBlockingSend(const void *data, uint32_t num) +{ + return UART_NonBlockingSend(data, num, &UART1_NonBlockingDriverState); +} + +static int32_t UART1_NonBlockingReceive(void *data, uint32_t num) +{ + return UART_NonBlockingReceive(data, num, &UART1_NonBlockingDriverState); +} + +static int32_t UART1_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return UART_NonBlockingTransfer(data_out, data_in, num, &UART1_NonBlockingDriverState); +} + +static uint32_t UART1_NonBlockingGetTxCount(void) +{ + return UART_NonBlockingGetTxCount(&UART1_NonBlockingDriverState); +} + +static uint32_t UART1_NonBlockingGetRxCount(void) +{ + return UART_NonBlockingGetRxCount(&UART1_NonBlockingDriverState); +} + +static int32_t UART1_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = UART_NonBlockingControl(control, arg, &UART1_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } + /* Enable the receive interrupts if ring buffer is used */ + if (UART1_NonBlockingDriverState.handle->rxRingBuffer != NULL) + { + UART_EnableInterrupts(UART1_NonBlockingDriverState.resource->base, + (kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable)); + } + + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS UART1_NonBlockingGetStatus(void) +{ + return UART_NonBlockingGetStatus(&UART1_NonBlockingDriverState); +} +#endif + +ARM_DRIVER_USART Driver_USART1 = { + UARTx_GetVersion, UARTx_GetCapabilities, +#if RTE_USART1_DMA_EN + UART1_SdmaInitialize, UART1_SdmaUninitialize, UART1_SdmaPowerControl, UART1_SdmaSend, UART1_SdmaReceive, + UART1_SdmaTransfer, UART1_SdmaGetTxCount, UART1_SdmaGetRxCount, UART1_SdmaControl, UART1_SdmaGetStatus, +#else + UART1_NonBlockingInitialize, + UART1_NonBlockingUninitialize, + UART1_NonBlockingPowerControl, + UART1_NonBlockingSend, + UART1_NonBlockingReceive, + UART1_NonBlockingTransfer, + UART1_NonBlockingGetTxCount, + UART1_NonBlockingGetRxCount, + UART1_NonBlockingControl, + UART1_NonBlockingGetStatus, +#endif + UARTx_SetModemControl, UARTx_GetModemStatus}; +#endif /* UART1 */ + +#if defined(UART2) && defined(RTE_USART2) && RTE_USART2 + +/* User needs to provide the implementation for UART2_GetFreq/InitPins/DeinitPins + * in the application for enabling according instance. + */ +extern uint32_t UART2_GetFreq(void); + +static cmsis_uart_resource_t UART2_Resource = {UART2, UART2_GetFreq}; + +#if defined(RTE_USART2_DMA_EN) && RTE_USART2_DMA_EN + +static cmsis_uart_sdma_resource_t UART2_SdmaResource = { + RTE_USART2_SDMA_TX_DMA_BASE, RTE_USART2_SDMA_TX_CH, RTE_USART2_SDMA_TX_REQUEST, RTE_USART2_SDMA_TX_PRIORITY, + RTE_USART2_SDMA_RX_DMA_BASE, RTE_USART2_SDMA_RX_CH, RTE_USART2_SDMA_RX_REQUEST, RTE_USART2_SDMA_RX_PRIORITY, +}; + +AT_NONCACHEABLE_SECTION_ALIGN(static uart_sdma_handle_t UART2_SdmaHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t UART2_SdmaTxHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t UART2_SdmaRxHandle, 4); + +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t UART2_SdmaTxContext, 4); +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t UART2_SdmaRxContext, 4); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("uart2_sdma_driver_state") +static cmsis_uart_sdma_driver_state_t UART2_SdmaDriverState = { +#else +static cmsis_uart_sdma_driver_state_t UART2_SdmaDriverState = { +#endif + &UART2_Resource, &UART2_SdmaResource, &UART2_SdmaHandle, &UART2_SdmaRxHandle, &UART2_SdmaTxHandle, +}; + +static int32_t UART2_SdmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART2_PIN_INIT + RTE_USART2_PIN_INIT(); +#endif + return UART_SdmaInitialize(cb_event, &UART2_SdmaDriverState); +} + +static int32_t UART2_SdmaUninitialize(void) +{ +#ifdef RTE_USART2_PIN_DEINIT + RTE_USART2_PIN_DEINIT(); +#endif + return UART_SdmaUninitialize(&UART2_SdmaDriverState); +} + +static int32_t UART2_SdmaPowerControl(ARM_POWER_STATE state) +{ + return UART_SdmaPowerControl(state, &UART2_SdmaDriverState, &UART2_SdmaRxContext, &UART2_SdmaTxContext); +} + +static int32_t UART2_SdmaSend(const void *data, uint32_t num) +{ + return UART_SdmaSend(data, num, &UART2_SdmaDriverState); +} + +static int32_t UART2_SdmaReceive(void *data, uint32_t num) +{ + return UART_SdmaReceive(data, num, &UART2_SdmaDriverState); +} + +static int32_t UART2_SdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return UART_SdmaTransfer(data_out, data_in, num, &UART2_SdmaDriverState); +} + +static uint32_t UART2_SdmaGetTxCount(void) +{ + return UART_SdmaGetTxCount(&UART2_SdmaDriverState); +} + +static uint32_t UART2_SdmaGetRxCount(void) +{ + return UART_SdmaGetRxCount(&UART2_SdmaDriverState); +} + +static int32_t UART2_SdmaControl(uint32_t control, uint32_t arg) +{ + return UART_SdmaControl(control, arg, &UART2_SdmaDriverState); +} + +static ARM_USART_STATUS UART2_SdmaGetStatus(void) +{ + return UART_SdmaGetStatus(&UART2_SdmaDriverState); +} + +#else + +static uart_handle_t UART2_Handle; + +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) +static uint8_t uart2_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("uart2_non_blocking_driver_state") +static cmsis_uart_non_blocking_driver_state_t UART2_NonBlockingDriverState = { +#else +static cmsis_uart_non_blocking_driver_state_t UART2_NonBlockingDriverState = { +#endif + &UART2_Resource, + &UART2_Handle, +}; + +static int32_t UART2_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART2_PIN_INIT + RTE_USART2_PIN_INIT(); +#endif + return UART_NonBlockingInitialize(cb_event, &UART2_NonBlockingDriverState); +} + +static int32_t UART2_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART2_PIN_DEINIT + RTE_USART2_PIN_DEINIT(); +#endif + return UART_NonBlockingUninitialize(&UART2_NonBlockingDriverState); +} + +static int32_t UART2_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = UART_NonBlockingPowerControl(state, &UART2_NonBlockingDriverState); + +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (UART2_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + UART_TransferStartRingBuffer(UART2_NonBlockingDriverState.resource->base, UART2_NonBlockingDriverState.handle, + uart2_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t UART2_NonBlockingSend(const void *data, uint32_t num) +{ + return UART_NonBlockingSend(data, num, &UART2_NonBlockingDriverState); +} + +static int32_t UART2_NonBlockingReceive(void *data, uint32_t num) +{ + return UART_NonBlockingReceive(data, num, &UART2_NonBlockingDriverState); +} + +static int32_t UART2_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return UART_NonBlockingTransfer(data_out, data_in, num, &UART2_NonBlockingDriverState); +} + +static uint32_t UART2_NonBlockingGetTxCount(void) +{ + return UART_NonBlockingGetTxCount(&UART2_NonBlockingDriverState); +} + +static uint32_t UART2_NonBlockingGetRxCount(void) +{ + return UART_NonBlockingGetRxCount(&UART2_NonBlockingDriverState); +} + +static int32_t UART2_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = UART_NonBlockingControl(control, arg, &UART2_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } + /* Enable the receive interrupts if ring buffer is used */ + if (UART2_NonBlockingDriverState.handle->rxRingBuffer != NULL) + { + UART_EnableInterrupts(UART2_NonBlockingDriverState.resource->base, + (kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable)); + } + + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS UART2_NonBlockingGetStatus(void) +{ + return UART_NonBlockingGetStatus(&UART2_NonBlockingDriverState); +} +#endif + +ARM_DRIVER_USART Driver_USART2 = { + UARTx_GetVersion, UARTx_GetCapabilities, +#if RTE_USART2_DMA_EN + UART2_SdmaInitialize, UART2_SdmaUninitialize, UART2_SdmaPowerControl, UART2_SdmaSend, UART2_SdmaReceive, + UART2_SdmaTransfer, UART2_SdmaGetTxCount, UART2_SdmaGetRxCount, UART2_SdmaControl, UART2_SdmaGetStatus, +#else + UART2_NonBlockingInitialize, + UART2_NonBlockingUninitialize, + UART2_NonBlockingPowerControl, + UART2_NonBlockingSend, + UART2_NonBlockingReceive, + UART2_NonBlockingTransfer, + UART2_NonBlockingGetTxCount, + UART2_NonBlockingGetRxCount, + UART2_NonBlockingControl, + UART2_NonBlockingGetStatus, +#endif + UARTx_SetModemControl, UARTx_GetModemStatus}; +#endif /* UART2 */ + +#if defined(UART3) && defined(RTE_USART3) && RTE_USART3 + +/* User needs to provide the implementation for UART3_GetFreq/InitPins/DeinitPins + * in the application for enabling according instance. + */ +extern uint32_t UART3_GetFreq(void); + +static cmsis_uart_resource_t UART3_Resource = {UART3, UART3_GetFreq}; + +#if defined(RTE_USART3_DMA_EN) && RTE_USART3_DMA_EN + +static cmsis_uart_sdma_resource_t UART3_SdmaResource = { + RTE_USART3_SDMA_TX_DMA_BASE, RTE_USART3_SDMA_TX_CH, RTE_USART3_SDMA_TX_REQUEST, RTE_USART3_SDMA_TX_PRIORITY, + RTE_USART3_SDMA_RX_DMA_BASE, RTE_USART3_SDMA_RX_CH, RTE_USART3_SDMA_RX_REQUEST, RTE_USART3_SDMA_RX_PRIORITY, +}; + +AT_NONCACHEABLE_SECTION_ALIGN(static uart_sdma_handle_t UART3_SdmaHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t UART3_SdmaTxHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t UART3_SdmaRxHandle, 4); + +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t UART3_SdmaTxContext, 4); +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t UART3_SdmaRxContext, 4); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("uart3_sdma_driver_state") +static cmsis_uart_sdma_driver_state_t UART3_SdmaDriverState = { +#else +static cmsis_uart_sdma_driver_state_t UART3_SdmaDriverState = { +#endif + &UART3_Resource, &UART3_SdmaResource, &UART3_SdmaHandle, &UART3_SdmaRxHandle, &UART3_SdmaTxHandle, +}; + +static int32_t UART3_SdmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART3_PIN_INIT + RTE_USART3_PIN_INIT(); +#endif + return UART_SdmaInitialize(cb_event, &UART3_SdmaDriverState); +} + +static int32_t UART3_SdmaUninitialize(void) +{ +#ifdef RTE_USART3_PIN_DEINIT + RTE_USART3_PIN_DEINIT(); +#endif + return UART_SdmaUninitialize(&UART3_SdmaDriverState); +} + +static int32_t UART3_SdmaPowerControl(ARM_POWER_STATE state) +{ + return UART_SdmaPowerControl(state, &UART3_SdmaDriverState, &UART3_SdmaRxContext, &UART3_SdmaTxContext); +} + +static int32_t UART3_SdmaSend(const void *data, uint32_t num) +{ + return UART_SdmaSend(data, num, &UART3_SdmaDriverState); +} + +static int32_t UART3_SdmaReceive(void *data, uint32_t num) +{ + return UART_SdmaReceive(data, num, &UART3_SdmaDriverState); +} + +static int32_t UART3_SdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return UART_SdmaTransfer(data_out, data_in, num, &UART3_SdmaDriverState); +} + +static uint32_t UART3_SdmaGetTxCount(void) +{ + return UART_SdmaGetTxCount(&UART3_SdmaDriverState); +} + +static uint32_t UART3_SdmaGetRxCount(void) +{ + return UART_SdmaGetRxCount(&UART3_SdmaDriverState); +} + +static int32_t UART3_SdmaControl(uint32_t control, uint32_t arg) +{ + return UART_SdmaControl(control, arg, &UART3_SdmaDriverState); +} + +static ARM_USART_STATUS UART3_SdmaGetStatus(void) +{ + return UART_SdmaGetStatus(&UART3_SdmaDriverState); +} + +#else + +static uart_handle_t UART3_Handle; + +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) +static uint8_t uart3_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("uart3_non_blocking_driver_state") +static cmsis_uart_non_blocking_driver_state_t UART3_NonBlockingDriverState = { +#else +static cmsis_uart_non_blocking_driver_state_t UART3_NonBlockingDriverState = { +#endif + &UART3_Resource, + &UART3_Handle, +}; + +static int32_t UART3_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART3_PIN_INIT + RTE_USART3_PIN_INIT(); +#endif + return UART_NonBlockingInitialize(cb_event, &UART3_NonBlockingDriverState); +} + +static int32_t UART3_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART3_PIN_DEINIT + RTE_USART3_PIN_DEINIT(); +#endif + return UART_NonBlockingUninitialize(&UART3_NonBlockingDriverState); +} + +static int32_t UART3_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = UART_NonBlockingPowerControl(state, &UART3_NonBlockingDriverState); + +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (UART3_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + UART_TransferStartRingBuffer(UART3_NonBlockingDriverState.resource->base, UART3_NonBlockingDriverState.handle, + uart3_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t UART3_NonBlockingSend(const void *data, uint32_t num) +{ + return UART_NonBlockingSend(data, num, &UART3_NonBlockingDriverState); +} + +static int32_t UART3_NonBlockingReceive(void *data, uint32_t num) +{ + return UART_NonBlockingReceive(data, num, &UART3_NonBlockingDriverState); +} + +static int32_t UART3_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return UART_NonBlockingTransfer(data_out, data_in, num, &UART3_NonBlockingDriverState); +} + +static uint32_t UART3_NonBlockingGetTxCount(void) +{ + return UART_NonBlockingGetTxCount(&UART3_NonBlockingDriverState); +} + +static uint32_t UART3_NonBlockingGetRxCount(void) +{ + return UART_NonBlockingGetRxCount(&UART3_NonBlockingDriverState); +} + +static int32_t UART3_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = UART_NonBlockingControl(control, arg, &UART3_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } + /* Enable the receive interrupts if ring buffer is used */ + if (UART3_NonBlockingDriverState.handle->rxRingBuffer != NULL) + { + UART_EnableInterrupts(UART3_NonBlockingDriverState.resource->base, + (kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable)); + } + + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS UART3_NonBlockingGetStatus(void) +{ + return UART_NonBlockingGetStatus(&UART3_NonBlockingDriverState); +} +#endif + +ARM_DRIVER_USART Driver_USART3 = { + UARTx_GetVersion, UARTx_GetCapabilities, +#if RTE_USART3_DMA_EN + UART3_SdmaInitialize, UART3_SdmaUninitialize, UART3_SdmaPowerControl, UART3_SdmaSend, UART3_SdmaReceive, + UART3_SdmaTransfer, UART3_SdmaGetTxCount, UART3_SdmaGetRxCount, UART3_SdmaControl, UART3_SdmaGetStatus, +#else + UART3_NonBlockingInitialize, + UART3_NonBlockingUninitialize, + UART3_NonBlockingPowerControl, + UART3_NonBlockingSend, + UART3_NonBlockingReceive, + UART3_NonBlockingTransfer, + UART3_NonBlockingGetTxCount, + UART3_NonBlockingGetRxCount, + UART3_NonBlockingControl, + UART3_NonBlockingGetStatus, +#endif + UARTx_SetModemControl, UARTx_GetModemStatus}; +#endif /* UART3 */ + +#if defined(UART4) && defined(RTE_USART4) && RTE_USART4 + +/* User needs to provide the implementation for UART4_GetFreq/InitPins/DeinitPins + * in the application for enabling according instance. + */ +extern uint32_t UART4_GetFreq(void); + +static cmsis_uart_resource_t UART4_Resource = {UART4, UART4_GetFreq}; + +#if defined(RTE_USART4_DMA_EN) && RTE_USART4_DMA_EN + +static cmsis_uart_sdma_resource_t UART4_SdmaResource = { + RTE_USART4_SDMA_TX_DMA_BASE, RTE_USART4_SDMA_TX_CH, RTE_USART4_SDMA_TX_REQUEST, RTE_USART4_SDMA_TX_PRIORITY, + RTE_USART4_SDMA_RX_DMA_BASE, RTE_USART4_SDMA_RX_CH, RTE_USART4_SDMA_RX_REQUEST, RTE_USART4_SDMA_RX_PRIORITY, +}; + +AT_NONCACHEABLE_SECTION_ALIGN(static uart_sdma_handle_t UART4_SdmaHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t UART4_SdmaTxHandle, 4); +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t UART4_SdmaRxHandle, 4); + +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t UART4_SdmaTxContext, 4); +AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t UART4_SdmaRxContext, 4); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("uart4_sdma_driver_state") +static cmsis_uart_sdma_driver_state_t UART4_SdmaDriverState = { +#else +static cmsis_uart_sdma_driver_state_t UART4_SdmaDriverState = { +#endif + &UART4_Resource, &UART4_SdmaResource, &UART4_SdmaHandle, &UART4_SdmaRxHandle, &UART4_SdmaTxHandle, +}; + +static int32_t UART4_SdmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART4_PIN_INIT + RTE_USART4_PIN_INIT(); +#endif + return UART_SdmaInitialize(cb_event, &UART4_SdmaDriverState); +} + +static int32_t UART4_SdmaUninitialize(void) +{ +#ifdef RTE_USART4_PIN_DEINIT + RTE_USART4_PIN_DEINIT(); +#endif + return UART_SdmaUninitialize(&UART4_SdmaDriverState); +} + +static int32_t UART4_SdmaPowerControl(ARM_POWER_STATE state) +{ + return UART_SdmaPowerControl(state, &UART4_SdmaDriverState, &UART4_SdmaRxContext, &UART4_SdmaTxContext); +} + +static int32_t UART4_SdmaSend(const void *data, uint32_t num) +{ + return UART_SdmaSend(data, num, &UART4_SdmaDriverState); +} + +static int32_t UART4_SdmaReceive(void *data, uint32_t num) +{ + return UART_SdmaReceive(data, num, &UART4_SdmaDriverState); +} + +static int32_t UART4_SdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return UART_SdmaTransfer(data_out, data_in, num, &UART4_SdmaDriverState); +} + +static uint32_t UART4_SdmaGetTxCount(void) +{ + return UART_SdmaGetTxCount(&UART4_SdmaDriverState); +} + +static uint32_t UART4_SdmaGetRxCount(void) +{ + return UART_SdmaGetRxCount(&UART4_SdmaDriverState); +} + +static int32_t UART4_SdmaControl(uint32_t control, uint32_t arg) +{ + return UART_SdmaControl(control, arg, &UART4_SdmaDriverState); +} + +static ARM_USART_STATUS UART4_SdmaGetStatus(void) +{ + return UART_SdmaGetStatus(&UART4_SdmaDriverState); +} + +#else + +static uart_handle_t UART4_Handle; + +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) +static uint8_t uart4_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("uart4_non_blocking_driver_state") +static cmsis_uart_non_blocking_driver_state_t UART4_NonBlockingDriverState = { +#else +static cmsis_uart_non_blocking_driver_state_t UART4_NonBlockingDriverState = { +#endif + &UART4_Resource, + &UART4_Handle, +}; + +static int32_t UART4_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART4_PIN_INIT + RTE_USART4_PIN_INIT(); +#endif + return UART_NonBlockingInitialize(cb_event, &UART4_NonBlockingDriverState); +} + +static int32_t UART4_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART4_PIN_DEINIT + RTE_USART4_PIN_DEINIT(); +#endif + return UART_NonBlockingUninitialize(&UART4_NonBlockingDriverState); +} + +static int32_t UART4_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + int32_t result; + + result = UART_NonBlockingPowerControl(state, &UART4_NonBlockingDriverState); + +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (UART4_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + UART_TransferStartRingBuffer(UART4_NonBlockingDriverState.resource->base, UART4_NonBlockingDriverState.handle, + uart4_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t UART4_NonBlockingSend(const void *data, uint32_t num) +{ + return UART_NonBlockingSend(data, num, &UART4_NonBlockingDriverState); +} + +static int32_t UART4_NonBlockingReceive(void *data, uint32_t num) +{ + return UART_NonBlockingReceive(data, num, &UART4_NonBlockingDriverState); +} + +static int32_t UART4_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return UART_NonBlockingTransfer(data_out, data_in, num, &UART4_NonBlockingDriverState); +} + +static uint32_t UART4_NonBlockingGetTxCount(void) +{ + return UART_NonBlockingGetTxCount(&UART4_NonBlockingDriverState); +} + +static uint32_t UART4_NonBlockingGetRxCount(void) +{ + return UART_NonBlockingGetRxCount(&UART4_NonBlockingDriverState); +} + +static int32_t UART4_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = UART_NonBlockingControl(control, arg, &UART4_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } + /* Enable the receive interrupts if ring buffer is used */ + if (UART4_NonBlockingDriverState.handle->rxRingBuffer != NULL) + { + UART_EnableInterrupts( + UART4_NonBlockingDriverState.resource->base, + ((uint32_t)kUART_RxReadyEnable | (uint32_t)kUART_AgingTimerEnable | (uint32_t)kUART_RxOverrunEnable | + (uint32_t)kUART_ParityErrorEnable | (uint32_t)kUART_FrameErrorEnable)); + } + + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS UART4_NonBlockingGetStatus(void) +{ + return UART_NonBlockingGetStatus(&UART4_NonBlockingDriverState); +} +#endif + +ARM_DRIVER_USART Driver_USART4 = { + UARTx_GetVersion, UARTx_GetCapabilities, +#if RTE_USART4_DMA_EN + UART4_SdmaInitialize, UART4_SdmaUninitialize, UART4_SdmaPowerControl, UART4_SdmaSend, UART4_SdmaReceive, + UART4_SdmaTransfer, UART4_SdmaGetTxCount, UART4_SdmaGetRxCount, UART4_SdmaControl, UART4_SdmaGetStatus, +#else + UART4_NonBlockingInitialize, + UART4_NonBlockingUninitialize, + UART4_NonBlockingPowerControl, + UART4_NonBlockingSend, + UART4_NonBlockingReceive, + UART4_NonBlockingTransfer, + UART4_NonBlockingGetTxCount, + UART4_NonBlockingGetRxCount, + UART4_NonBlockingControl, + UART4_NonBlockingGetStatus, +#endif + UARTx_SetModemControl, UARTx_GetModemStatus}; +#endif /* UART4 */ diff --git a/devices/MIMX8MQ6/cmsis_drivers/fsl_uart_cmsis.h b/devices/MIMX8MQ6/cmsis_drivers/fsl_uart_cmsis.h new file mode 100644 index 000000000..eb286db48 --- /dev/null +++ b/devices/MIMX8MQ6/cmsis_drivers/fsl_uart_cmsis.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _FSL_UART_CMSIS_H_ +#define _FSL_UART_CMSIS_H_ + +#include "fsl_common.h" +#include "Driver_USART.h" +#include "RTE_Device.h" +#include "fsl_uart.h" +#if (defined(FSL_FEATURE_SOC_SDMA_COUNT) && FSL_FEATURE_SOC_SDMA_COUNT) +#include "fsl_uart_sdma.h" +#endif +#if defined(UART1) && defined(RTE_USART1) && RTE_USART1 +extern ARM_DRIVER_USART Driver_USART1; +#endif /* UART1 */ + +#if defined(UART2) && defined(RTE_USART2) && RTE_USART2 +extern ARM_DRIVER_USART Driver_USART2; +#endif /* UART2 */ + +#if defined(UART3) && defined(RTE_USART3) && RTE_USART3 +extern ARM_DRIVER_USART Driver_USART3; +#endif /* UART3 */ + +#if defined(UART4) && defined(RTE_USART4) && RTE_USART4 +extern ARM_DRIVER_USART Driver_USART4; +#endif /* UART4 */ + +/* USART Driver state flags */ +#define USART_FLAG_UNINIT (0U) +#define USART_FLAG_INIT (1U << 0) +#define USART_FLAG_POWER (1U << 1) +#define USART_FLAG_CONFIGURED (1U << 2) + +#endif /* _FSL_UART_CMSIS_H_ */ diff --git a/devices/MIMX8MQ6/device_MIMX8MQ6_CMSIS_MIMX8MQ6.cmake b/devices/MIMX8MQ6/device_MIMX8MQ6_CMSIS_MIMX8MQ6.cmake new file mode 100644 index 000000000..bb60e41f1 --- /dev/null +++ b/devices/MIMX8MQ6/device_MIMX8MQ6_CMSIS_MIMX8MQ6.cmake @@ -0,0 +1,10 @@ +include_guard(GLOBAL) +message("device_MIMX8MQ6_CMSIS component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + +include(CMSIS_Include_core_cm_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/device_MIMX8MQ6_startup_MIMX8MQ6.cmake b/devices/MIMX8MQ6/device_MIMX8MQ6_startup_MIMX8MQ6.cmake new file mode 100644 index 000000000..abbfdf1ea --- /dev/null +++ b/devices/MIMX8MQ6/device_MIMX8MQ6_startup_MIMX8MQ6.cmake @@ -0,0 +1,10 @@ +include_guard(GLOBAL) +message("device_MIMX8MQ6_startup component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/gcc/startup_MIMX8MQ6_cm4.S +) + + +include(device_MIMX8MQ6_system_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/device_MIMX8MQ6_system_MIMX8MQ6.cmake b/devices/MIMX8MQ6/device_MIMX8MQ6_system_MIMX8MQ6.cmake new file mode 100644 index 000000000..6fa332e1b --- /dev/null +++ b/devices/MIMX8MQ6/device_MIMX8MQ6_system_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("device_MIMX8MQ6_system component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/system_MIMX8MQ6_cm4.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_cache_lmem_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_cache_lmem_MIMX8MQ6.cmake new file mode 100644 index 000000000..1c5c620e3 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_cache_lmem_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_cache_lmem component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_cache.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_clock_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_clock_MIMX8MQ6.cmake new file mode 100644 index 000000000..368c9b3c0 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_clock_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_clock component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_clock.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_common_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_common_MIMX8MQ6.cmake new file mode 100644 index 000000000..4cdff9a99 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_common_MIMX8MQ6.cmake @@ -0,0 +1,18 @@ +include_guard(GLOBAL) +message("driver_common component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_common.c + ${CMAKE_CURRENT_LIST_DIR}/fsl_common_arm.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_clock_MIMX8MQ6) + +include(device_MIMX8MQ6_CMSIS_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_ecspi_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_ecspi_MIMX8MQ6.cmake new file mode 100644 index 000000000..e55c9767b --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_ecspi_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_ecspi component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_ecspi.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_ecspi_freertos_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_ecspi_freertos_MIMX8MQ6.cmake new file mode 100644 index 000000000..3e558b2e1 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_ecspi_freertos_MIMX8MQ6.cmake @@ -0,0 +1,17 @@ +include_guard(GLOBAL) +message("driver_ecspi_freertos component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_ecspi_freertos.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_ecspi_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_gpt_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_gpt_MIMX8MQ6.cmake new file mode 100644 index 000000000..c6f1584f2 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_gpt_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_gpt component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_gpt.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_igpio_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_igpio_MIMX8MQ6.cmake new file mode 100644 index 000000000..da99cedec --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_igpio_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_igpio component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_gpio.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_ii2c_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_ii2c_MIMX8MQ6.cmake new file mode 100644 index 000000000..4d76c36b5 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_ii2c_MIMX8MQ6.cmake @@ -0,0 +1,13 @@ +include_guard(GLOBAL) +message("driver_ii2c component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_i2c.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + diff --git a/devices/MIMX8MQ6/drivers/driver_ii2c_freertos_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_ii2c_freertos_MIMX8MQ6.cmake new file mode 100644 index 000000000..d7117c212 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_ii2c_freertos_MIMX8MQ6.cmake @@ -0,0 +1,17 @@ +include_guard(GLOBAL) +message("driver_ii2c_freertos component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_i2c_freertos.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_ii2c_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_ipwm_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_ipwm_MIMX8MQ6.cmake new file mode 100644 index 000000000..56fbc052e --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_ipwm_MIMX8MQ6.cmake @@ -0,0 +1,13 @@ +include_guard(GLOBAL) +message("driver_ipwm component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_pwm.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + diff --git a/devices/MIMX8MQ6/drivers/driver_iuart_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_iuart_MIMX8MQ6.cmake new file mode 100644 index 000000000..d30036f70 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_iuart_MIMX8MQ6.cmake @@ -0,0 +1,13 @@ +include_guard(GLOBAL) +message("driver_iuart component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_uart.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + diff --git a/devices/MIMX8MQ6/drivers/driver_iuart_freertos_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_iuart_freertos_MIMX8MQ6.cmake new file mode 100644 index 000000000..16fd8d263 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_iuart_freertos_MIMX8MQ6.cmake @@ -0,0 +1,17 @@ +include_guard(GLOBAL) +message("driver_iuart_freertos component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_uart_freertos.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_iuart_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_mu_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_mu_MIMX8MQ6.cmake new file mode 100644 index 000000000..60ef4d0b7 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_mu_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_mu component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_mu.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_qspi_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_qspi_MIMX8MQ6.cmake new file mode 100644 index 000000000..1e668914b --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_qspi_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_qspi component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_qspi.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_rdc_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_rdc_MIMX8MQ6.cmake new file mode 100644 index 000000000..092d485ff --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_rdc_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_rdc component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_rdc.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_rdc_sema42_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_rdc_sema42_MIMX8MQ6.cmake new file mode 100644 index 000000000..221556342 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_rdc_sema42_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_rdc_sema42 component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_rdc_sema42.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_sai_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_sai_MIMX8MQ6.cmake new file mode 100644 index 000000000..417bf46c8 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_sai_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_sai component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_sai.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_sema4_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_sema4_MIMX8MQ6.cmake new file mode 100644 index 000000000..d560cc254 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_sema4_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_sema4 component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_sema4.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_tmu_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_tmu_MIMX8MQ6.cmake new file mode 100644 index 000000000..a8d2cb700 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_tmu_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_tmu component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_tmu.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/driver_wdog01_MIMX8MQ6.cmake b/devices/MIMX8MQ6/drivers/driver_wdog01_MIMX8MQ6.cmake new file mode 100644 index 000000000..f0e32513d --- /dev/null +++ b/devices/MIMX8MQ6/drivers/driver_wdog01_MIMX8MQ6.cmake @@ -0,0 +1,15 @@ +include_guard(GLOBAL) +message("driver_wdog01 component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_wdog.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/drivers/fsl_cache.c b/devices/MIMX8MQ6/drivers/fsl_cache.c new file mode 100644 index 000000000..616cde33b --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_cache.c @@ -0,0 +1,507 @@ +/* + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cache.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cache_lmem" +#endif + +#define L1CACHE_ONEWAYSIZE_BYTE (4096U) /*!< Cache size is 4K-bytes one way. */ +#define L1CACHE_CODEBUSADDR_BOUNDARY (0x1FFFFFFFU) /*!< The processor code bus address boundary. */ + +/******************************************************************************* + * Code + ******************************************************************************/ +#if (FSL_FEATURE_SOC_LMEM_COUNT == 1) +/*! + * brief Enables the processor code bus cache. + * + */ +void L1CACHE_EnableCodeCache(void) +{ + if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK)) + { + /* First, invalidate the entire cache. */ + L1CACHE_InvalidateCodeCache(); + + /* Now enable the cache. */ + LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK; + } +} + +/*! + * brief Disables the processor code bus cache. + * + */ +void L1CACHE_DisableCodeCache(void) +{ + /* First, push any modified contents. */ + L1CACHE_CleanCodeCache(); + + /* Now disable the cache. */ + LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; +} + +/*! + * brief Invalidates the processor code bus cache. + * + */ +void L1CACHE_InvalidateCodeCache(void) +{ + /* Enables the processor code bus to invalidate all lines in both ways. + and Initiate the processor code bus code cache command. */ + LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK); +} + +/*! + * brief Invalidates processor code bus cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be invalidated. + * note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pccReg = 0; + /* Align address to cache line size. */ + uint32_t startAddr = address & ~((uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE - 1U); + + /* Set the invalidate by line command and use the physical address. */ + pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(1) | LMEM_PCCLCR_LADSEL_MASK; + LMEM->PCCLCR = pccReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U) + { + } + startAddr += (uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE; + } +} + +/*! + * brief Cleans the processor code bus cache. + * + */ +void L1CACHE_CleanCodeCache(void) +{ + /* Enable the processor code bus to push all modified lines. */ + LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK); +} + +/*! + * brief Cleans processor code bus cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be cleaned. + * note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanCodeCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pccReg = 0; + /* Align address to cache line size. */ + uint32_t startAddr = address & ~((uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE - 1U); + + /* Set the push by line command. */ + pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(2) | LMEM_PCCLCR_LADSEL_MASK; + LMEM->PCCLCR = pccReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U) + { + } + startAddr += (uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE; + } +} + +/*! + * brief Cleans and invalidates the processor code bus cache. + * + */ +void L1CACHE_CleanInvalidateCodeCache(void) +{ + /* Push and invalidate all. */ + LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | + LMEM_PCCCR_GO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK); +} + +/*! + * brief Cleans and invalidate processor code bus cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be Cleaned and Invalidated. + * note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanInvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pccReg = 0; + /* Align address to cache line size. */ + uint32_t startAddr = address & ~((uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE - 1U); + + /* Set the push by line command. */ + pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(3) | LMEM_PCCLCR_LADSEL_MASK; + LMEM->PCCLCR = pccReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U) + { + } + startAddr += (uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE; + } +} + +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE +/*! + * brief Enables the processor system bus cache. + * + */ +void L1CACHE_EnableSystemCache(void) +{ + /* Only enable when not enabled. */ + if (0U == (LMEM->PSCCR & LMEM_PSCCR_ENCACHE_MASK)) + { + /* First, invalidate the entire cache. */ + L1CACHE_InvalidateSystemCache(); + + /* Now enable the cache. */ + LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK; + } +} + +/*! + * brief Disables the processor system bus cache. + * + */ +void L1CACHE_DisableSystemCache(void) +{ + /* First, push any modified contents. */ + L1CACHE_CleanSystemCache(); + + /* Now disable the cache. */ + LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK; +} + +/*! + * brief Invalidates the processor system bus cache. + * + */ +void L1CACHE_InvalidateSystemCache(void) +{ + /* Enables the processor system bus to invalidate all lines in both ways. + and Initiate the processor system bus cache command. */ + LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK; + + /* Wait until the cache command completes */ + while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK); +} + +/*! + * brief Invalidates processor system bus cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be invalidated. + * note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pscReg = 0; + uint32_t startAddr = + address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size */ + + /* Set the invalidate by line command and use the physical address. */ + pscReg = (LMEM->PSCLCR & ~LMEM_PSCLCR_LCMD_MASK) | LMEM_PSCLCR_LCMD(1) | LMEM_PSCLCR_LADSEL_MASK; + LMEM->PSCLCR = pscReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + LMEM->PSCSAR = (startAddr & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PSCSAR & LMEM_PSCSAR_LGO_MASK) != 0U) + { + } + startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; + } +} + +/*! + * brief Cleans the processor system bus cache. + * + */ +void L1CACHE_CleanSystemCache(void) +{ + /* Enable the processor system bus to push all modified lines. */ + LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK); +} + +/*! + * brief Cleans processor system bus cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be cleaned. + * note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanSystemCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pscReg = 0; + uint32_t startAddr = + address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ + + /* Set the push by line command. */ + pscReg = (LMEM->PSCLCR & ~LMEM_PSCLCR_LCMD_MASK) | LMEM_PSCLCR_LCMD(2) | LMEM_PSCLCR_LADSEL_MASK; + LMEM->PSCLCR = pscReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + LMEM->PSCSAR = (startAddr & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PSCSAR & LMEM_PSCSAR_LGO_MASK) != 0U) + { + } + startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; + } +} + +/*! + * brief Cleans and invalidates the processor system bus cache. + * + */ +void L1CACHE_CleanInvalidateSystemCache(void) +{ + /* Push and invalidate all. */ + LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | + LMEM_PSCCR_GO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK); +} + +/*! + * brief Cleans and Invalidates processor system bus cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be Clean and Invalidated. + * note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanInvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pscReg = 0; + uint32_t startAddr = + address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ + + /* Set the push by line command. */ + pscReg = (LMEM->PSCLCR & ~LMEM_PSCLCR_LCMD_MASK) | LMEM_PSCLCR_LCMD(3) | LMEM_PSCLCR_LADSEL_MASK; + LMEM->PSCLCR = pscReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + LMEM->PSCSAR = (startAddr & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PSCSAR & LMEM_PSCSAR_LGO_MASK) != 0U) + { + } + startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; + } +} + +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ +#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */ + +/*! + * brief Invalidates cortex-m4 L1 instrument cache by range. + * + * param address The start address of the memory to be invalidated. + * param size_byte The memory size. + * note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + */ +void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte) +{ +#if (FSL_FEATURE_SOC_LMEM_COUNT == 1) + uint32_t endAddr = address + size_byte; + uint32_t size = size_byte; + + if (endAddr <= L1CACHE_CODEBUSADDR_BOUNDARY) + { + L1CACHE_InvalidateCodeCacheByRange(address, size); + } + else if (address <= L1CACHE_CODEBUSADDR_BOUNDARY) + { + size = L1CACHE_CODEBUSADDR_BOUNDARY - address; + L1CACHE_InvalidateCodeCacheByRange(address, size); +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE + size = size_byte - size; + L1CACHE_InvalidateSystemCacheByRange((L1CACHE_CODEBUSADDR_BOUNDARY + 1U), size); +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + } + else + { +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE + L1CACHE_InvalidateSystemCacheByRange(address, size); +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + } +#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */ +} + +/*! + * brief Cleans cortex-m4 L1 data cache by range. + * + * param address The start address of the memory to be cleaned. + * param size_byte The memory size. + * note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + */ +void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte) +{ +#if (FSL_FEATURE_SOC_LMEM_COUNT == 1) + uint32_t endAddr = address + size_byte; + uint32_t size = size_byte; + + if (endAddr <= L1CACHE_CODEBUSADDR_BOUNDARY) + { + L1CACHE_CleanCodeCacheByRange(address, size); + } + else if (address <= L1CACHE_CODEBUSADDR_BOUNDARY) + { + size = L1CACHE_CODEBUSADDR_BOUNDARY - address; + L1CACHE_CleanCodeCacheByRange(address, size); +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE + size = size_byte - size; + L1CACHE_CleanSystemCacheByRange((L1CACHE_CODEBUSADDR_BOUNDARY + 1U), size); +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + } + else + { +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE + L1CACHE_CleanSystemCacheByRange(address, size); +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + } +#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */ +} + +/*! + * brief Cleans and Invalidates cortex-m4 L1 data cache by range. + * + * param address The start address of the memory to be clean and invalidated. + * param size_byte The memory size. + * note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + */ +void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte) +{ +#if (FSL_FEATURE_SOC_LMEM_COUNT == 1) + uint32_t endAddr = address + size_byte; + uint32_t size = size_byte; + + if (endAddr <= L1CACHE_CODEBUSADDR_BOUNDARY) + { + L1CACHE_CleanInvalidateCodeCacheByRange(address, size); + } + else if (address <= L1CACHE_CODEBUSADDR_BOUNDARY) + { + size = L1CACHE_CODEBUSADDR_BOUNDARY - address; + L1CACHE_CleanInvalidateCodeCacheByRange(address, size); +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE + size = size_byte - size; + L1CACHE_CleanInvalidateSystemCacheByRange((L1CACHE_CODEBUSADDR_BOUNDARY + 1U), size); +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + } + else + { +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE + L1CACHE_CleanInvalidateSystemCacheByRange(address, size); +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + } +#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */ +} diff --git a/devices/MIMX8MQ6/drivers/fsl_cache.h b/devices/MIMX8MQ6/drivers/fsl_cache.h new file mode 100644 index 000000000..0f32bb0c6 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_cache.h @@ -0,0 +1,340 @@ +/* + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CACHE_H_ +#define _FSL_CACHE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache_lmem + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version. */ +#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 6)) +/*@}*/ + +/*! @brief code bus cache line size is equal to system bus line size, so the unified I/D cache line size equals too. */ +#define L1CODEBUSCACHE_LINESIZE_BYTE \ + FSL_FEATURE_L1ICACHE_LINESIZE_BYTE /*!< The code bus CACHE line size is 16B = 128b. */ +#define L1SYSTEMBUSCACHE_LINESIZE_BYTE \ + L1CODEBUSCACHE_LINESIZE_BYTE /*!< The system bus CACHE line size is 16B = 128b. */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if (FSL_FEATURE_SOC_LMEM_COUNT == 1) +/*! + * @name cache control for L1 cache (local memory controller for code/system bus cache) + *@{ + */ + +/*! + * @brief Enables the processor code bus cache. + * + */ +void L1CACHE_EnableCodeCache(void); + +/*! + * @brief Disables the processor code bus cache. + * + */ +void L1CACHE_DisableCodeCache(void); + +/*! + * @brief Invalidates the processor code bus cache. + * + */ +void L1CACHE_InvalidateCodeCache(void); + +/*! + * @brief Invalidates processor code bus cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans the processor code bus cache. + * + */ +void L1CACHE_CleanCodeCache(void); + +/*! + * @brief Cleans processor code bus cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be cleaned. + * @note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanCodeCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and invalidates the processor code bus cache. + * + */ +void L1CACHE_CleanInvalidateCodeCache(void); + +/*! + * @brief Cleans and invalidate processor code bus cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be Cleaned and Invalidated. + * @note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanInvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Enables/disables the processor code bus write buffer. + * + * @param enable The enable or disable flag. + * true - enable the code bus write buffer. + * false - disable the code bus write buffer. + */ +static inline void L1CACHE_EnableCodeCacheWriteBuffer(bool enable) +{ + if (enable) + { + LMEM->PCCCR |= LMEM_PCCCR_ENWRBUF_MASK; + } + else + { + LMEM->PCCCR &= ~LMEM_PCCCR_ENWRBUF_MASK; + } +} + +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE +/*! + * @brief Enables the processor system bus cache. + * + */ +void L1CACHE_EnableSystemCache(void); + +/*! + * @brief Disables the processor system bus cache. + * + */ +void L1CACHE_DisableSystemCache(void); + +/*! + * @brief Invalidates the processor system bus cache. + * + */ +void L1CACHE_InvalidateSystemCache(void); + +/*! + * @brief Invalidates processor system bus cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans the processor system bus cache. + * + */ +void L1CACHE_CleanSystemCache(void); + +/*! + * @brief Cleans processor system bus cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be cleaned. + * @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanSystemCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and invalidates the processor system bus cache. + * + */ +void L1CACHE_CleanInvalidateSystemCache(void); + +/*! + * @brief Cleans and Invalidates processor system bus cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be Clean and Invalidated. + * @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanInvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Enables/disables the processor system bus write buffer. + * + * @param enable The enable or disable flag. + * true - enable the code bus write buffer. + * false - disable the code bus write buffer. + */ +static inline void L1CACHE_EnableSystemCacheWriteBuffer(bool enable) +{ + if (enable) + { + LMEM->PSCCR |= LMEM_PSCCR_ENWRBUF_MASK; + } + else + { + LMEM->PSCCR &= ~LMEM_PSCCR_ENWRBUF_MASK; + } +} +/*@}*/ +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + +/*! + * @name cache control for unified L1 cache driver + *@{ + */ + +/*! + * @brief Invalidates cortex-m4 L1 instrument cache by range. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + */ +void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Invalidates cortex-m4 L1 data cache by range. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + */ +static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_InvalidateICacheByRange(address, size_byte); +} + +/*! + * @brief Cleans cortex-m4 L1 data cache by range. + * + * @param address The start address of the memory to be cleaned. + * @param size_byte The memory size. + * @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + */ +void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and Invalidates cortex-m4 L1 data cache by range. + * + * @param address The start address of the memory to be clean and invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + */ +void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte); +/*@}*/ +#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */ + +/*! + * @name Unified Cache Control for all caches + *@{ + */ + +/*! + * @brief Invalidates instruction cache by range. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to 16-Byte due to the cache operation unit + * FSL_FEATURE_L1ICACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line + * size if startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_InvalidateICacheByRange(address, size_byte); +} + +/*! + * @brief Invalidates data cache by range. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to 16-Byte due to the cache operation unit + * FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line + * size if startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_InvalidateDCacheByRange(address, size_byte); +} + +/*! + * @brief Clean data cache by range. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned. + * @note Address and size should be aligned to 16-Byte due to the cache operation unit + * FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line + * size if startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanDCacheByRange(address, size_byte); +} + +/*! + * @brief Cleans and Invalidates data cache by range. + * + * @param address The physical address. + * @param size_byte size of the memory to be Cleaned and Invalidated. + * @note Address and size should be aligned to 16-Byte due to the cache operation unit + * FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line + * size if startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanInvalidateDCacheByRange(address, size_byte); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CACHE_H_*/ diff --git a/devices/MIMX8MQ6/drivers/fsl_clock.c b/devices/MIMX8MQ6/drivers/fsl_clock.c new file mode 100644 index 000000000..d7c8b735c --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_clock.c @@ -0,0 +1,967 @@ +/* + * Copyright 2017 - 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_common.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif +/*! @brief SSCG PLL FLITER range value */ +#define SSCG_PLL1_FILTER_RANGE (35000000U) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * param clockName Clock names defined in clock_name_t + * return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + + switch (clockName) + { + case kCLOCK_CoreM4Clk: + freq = CLOCK_GetCoreM4Freq(); + break; + case kCLOCK_AxiClk: + freq = CLOCK_GetAxiFreq(); + break; + case kCLOCK_AhbClk: + freq = CLOCK_GetAhbFreq(); + break; + case kCLOCK_IpgClk: + freq = CLOCK_GetAhbFreq(); + break; + default: + freq = 0U; + break; + } + return freq; +} + +/*! + * brief Get the CCM Cortex M4 core frequency. + * + * return Clock frequency; If the clock is invalid, returns 0. + */ +uint32_t CLOCK_GetCoreM4Freq(void) +{ + uint32_t freq; + uint32_t pre = CLOCK_GetRootPreDivider(kCLOCK_RootM4); + uint32_t post = CLOCK_GetRootPostDivider(kCLOCK_RootM4); + + switch (CLOCK_GetRootMux(kCLOCK_RootM4)) + { + case (uint32_t)kCLOCK_M4RootmuxOsc25m: + freq = OSC25M_CLK_FREQ; + break; + case (uint32_t)kCLOCK_M4RootmuxSysPll2Div5: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 5U; + break; + case (uint32_t)kCLOCK_M4RootmuxSysPll2Div4: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 4U; + break; + case (uint32_t)kCLOCK_M4RootmuxSysPll1Div3: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 3U; + break; + case (uint32_t)kCLOCK_M4RootmuxSysPll1: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl); + break; + case (uint32_t)kCLOCK_M4RootmuxAudioPll1: + freq = CLOCK_GetPllFreq(kCLOCK_AudioPll1Ctrl); + break; + case (uint32_t)kCLOCK_M4RootmuxVideoPll1: + freq = CLOCK_GetPllFreq(kCLOCK_VideoPll1Ctrl); + break; + case (uint32_t)kCLOCK_M4RootmuxSysPll3: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll3Ctrl); + break; + default: + freq = 0U; + break; + } + + return freq / pre / post; +} + +/*! + * brief Get the CCM Axi bus frequency. + * + * return Clock frequency; If the clock is invalid, returns 0. + */ +uint32_t CLOCK_GetAxiFreq(void) +{ + uint32_t freq; + uint32_t pre = CLOCK_GetRootPreDivider(kCLOCK_RootAxi); + uint32_t post = CLOCK_GetRootPostDivider(kCLOCK_RootAxi); + + switch (CLOCK_GetRootMux(kCLOCK_RootAxi)) + { + case (uint32_t)kCLOCK_AxiRootmuxOsc25m: + freq = OSC25M_CLK_FREQ; + break; + case (uint32_t)kCLOCK_AxiRootmuxSysPll2Div3: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 3U; + break; + case (uint32_t)kCLOCK_AxiRootmuxSysPll2Div4: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 4U; + break; + case (uint32_t)kCLOCK_AxiRootmuxSysPll2: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl); + break; + case (uint32_t)kCLOCK_AxiRootmuxAudioPll1: + freq = CLOCK_GetPllFreq(kCLOCK_AudioPll1Ctrl); + break; + case (uint32_t)kCLOCK_AxiRootmuxVideoPll1: + freq = CLOCK_GetPllFreq(kCLOCK_VideoPll1Ctrl); + break; + case (uint32_t)kCLOCK_AxiRootmuxSysPll1Div8: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 8U; + break; + case (uint32_t)kCLOCK_AxiRootmuxSysPll1: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl); + break; + default: + freq = 0U; + break; + } + + return freq / pre / post; +} + +/*! + * brief Get the CCM Ahb bus frequency. + * + * return Clock frequency; If the clock is invalid, returns 0. + */ +uint32_t CLOCK_GetAhbFreq(void) +{ + uint32_t freq; + uint32_t pre = CLOCK_GetRootPreDivider(kCLOCK_RootAhb); + uint32_t post = CLOCK_GetRootPostDivider(kCLOCK_RootAhb); + + switch (CLOCK_GetRootMux(kCLOCK_RootAhb)) + { + case (uint32_t)kCLOCK_AhbRootmuxOsc25m: + freq = OSC25M_CLK_FREQ; + break; + case (uint32_t)kCLOCK_AhbRootmuxSysPll1Div6: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 6U; + break; + case (uint32_t)kCLOCK_AhbRootmuxSysPll1Div2: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 2U; + break; + case (uint32_t)kCLOCK_AhbRootmuxSysPll1: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl); + break; + case (uint32_t)kCLOCK_AhbRootmuxSysPll2Div8: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 8U; + break; + case (uint32_t)kCLOCK_AhbRootmuxSysPll3: + freq = CLOCK_GetPllFreq(kCLOCK_SystemPll3Ctrl); + break; + case (uint32_t)kCLOCK_AhbRootmuxAudioPll1: + freq = CLOCK_GetPllFreq(kCLOCK_AudioPll1Ctrl); + break; + case (uint32_t)kCLOCK_AhbRootmuxVideoPll1: + freq = CLOCK_GetPllFreq(kCLOCK_VideoPll1Ctrl); + break; + default: + freq = 0U; + break; + } + + return freq / pre / post; +} + +/*! + * brief Gets PLL reference clock frequency. + * + * param type fractional pll type. + + * return Clock frequency + */ +uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl) +{ + uint32_t refClkFreq = 0U; + uint8_t clkSel = 0U; + + if (ctrl <= kCLOCK_ArmPllCtrl) + { + clkSel = (uint8_t)CCM_BIT_FIELD_EXTRACTION(CCM_ANALOG_TUPLE_REG(CCM_ANALOG, ctrl), + CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK, + CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT); + } + else + { + clkSel = (uint8_t)(CCM_ANALOG_TUPLE_REG(CCM_ANALOG, ctrl) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK); + } + + switch (clkSel) + { + case (uint8_t)kANALOG_PllRefOsc25M: + refClkFreq = OSC25M_CLK_FREQ / + (CCM_BIT_FIELD_EXTRACTION(XTALOSC->OSC25M_CTL_CFG, XTALOSC_OSC25M_CTL_CFG_OSC_DIV_MASK, + XTALOSC_OSC25M_CTL_CFG_OSC_DIV_SHIFT) + + 1U); + break; + + case (uint8_t)kANALOG_PllRefOsc27M: + refClkFreq = OSC27M_CLK_FREQ / + (CCM_BIT_FIELD_EXTRACTION(XTALOSC->OSC27M_CTL_CFG, XTALOSC_OSC27M_CTL_CFG_OSC_DIV_MASK, + XTALOSC_OSC27M_CTL_CFG_OSC_DIV_SHIFT) + + 1U); + break; + + case (uint8_t)kANALOG_PllRefOscHdmiPhy27M: + refClkFreq = HDMI_PHY_27M_FREQ; + break; + + case (uint8_t)kANALOG_PllRefClkPN: + refClkFreq = CLKPN_FREQ; + break; + default: + refClkFreq = 0U; + break; + } + + return refClkFreq; +} + +/*! + * brief Gets PLL clock frequency. + * + * param type fractional pll type. + + * return Clock frequency + */ +uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll) +{ + uint32_t pllFreq = 0U; + uint32_t pllRefFreq = 0U; + bool sscgPll1Bypass = false; + bool sscgPll2Bypass = false; + bool fracPllBypass = false; + + pllRefFreq = CLOCK_GetPllRefClkFreq(pll); + + switch (pll) + { + /* SSCG PLL frequency */ + case kCLOCK_SystemPll1Ctrl: + sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll1InternalPll1BypassCtrl); + sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll1InternalPll2BypassCtrl); + break; + case kCLOCK_SystemPll2Ctrl: + sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll2InternalPll1BypassCtrl); + sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll2InternalPll2BypassCtrl); + break; + case kCLOCK_SystemPll3Ctrl: + sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll3InternalPll1BypassCtrl); + sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll3InternalPll2BypassCtrl); + break; + case kCLOCK_VideoPll2Ctrl: + sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_VideoPll2InternalPll1BypassCtrl); + sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_VideoPll2InternalPll2BypassCtrl); + break; + case kCLOCK_DramPllCtrl: + sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_DramPllInternalPll1BypassCtrl); + sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_DramPllInternalPll2BypassCtrl); + break; + case kCLOCK_AudioPll1Ctrl: + fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_AudioPll1BypassCtrl); + break; + case kCLOCK_AudioPll2Ctrl: + fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_AudioPll2BypassCtrl); + break; + case kCLOCK_VideoPll1Ctrl: + fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_VideoPll1BypassCtrl); + break; + case kCLOCK_GpuPllCtrl: + fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_GpuPLLPwrBypassCtrl); + break; + case kCLOCK_VpuPllCtrl: + fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_VpuPllPwrBypassCtrl); + break; + case kCLOCK_ArmPllCtrl: + fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_ArmPllPwrBypassCtrl); + break; + default: + fracPllBypass = false; + break; + } + if (pll <= kCLOCK_ArmPllCtrl) + { + if (fracPllBypass) + { + pllFreq = pllRefFreq; + } + else + { + pllFreq = CLOCK_GetFracPllFreq(CCM_ANALOG, pll, pllRefFreq); + } + } + else + { + if (sscgPll2Bypass) + { + /* if PLL2 is bypass, return reference clock directly */ + pllFreq = pllRefFreq; + } + else + { + pllFreq = CLOCK_GetSSCGPllFreq(CCM_ANALOG, pll, pllRefFreq, sscgPll1Bypass); + } + } + + return pllFreq; +} + +/*! + * brief Initializes the ANALOG ARM PLL. + * + * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration). + * + * note This function can't detect whether the Arm PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitArmPll(const ccm_analog_frac_pll_config_t *config) +{ + assert(config != NULL); + + /* Disable PLL bypass */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_ArmPllPwrBypassCtrl, false); + /* Fractional pll configuration */ + CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_ArmPllCtrl); + /* Enable and power up PLL clock. */ + CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_ArmPllClke); + + /* Wait for PLL to be locked. */ + while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_ArmPllCtrl)) + { + } +} + +/*! + * brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void) +{ + CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_ArmPllCtrl); +} + +/*! + * brief Initializes the ANALOG AUDIO PLL1. + * + * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration). + * + * note This function can't detect whether the AUDIO PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config) +{ + assert(config != NULL); + + /* Disable PLL bypass */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_AudioPll1BypassCtrl, false); + /* Fractional pll configuration */ + CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_AudioPll1Ctrl); + /* Enable and power up PLL clock. */ + CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_AudioPll1Clke); + + /* Wait for PLL to be locked. */ + while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_AudioPll1Ctrl)) + { + } +} + +/*! + * brief De-initialize the Audio PLL1. + */ +void CLOCK_DeinitAudioPll1(void) +{ + CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_AudioPll1Ctrl); +} + +/*! + * brief Initializes the ANALOG AUDIO PLL2. + * + * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration). + * + * note This function can't detect whether the AUDIO PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config) +{ + assert(config != NULL); + + /* Disable PLL bypass */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_AudioPll2BypassCtrl, false); + /* Fractional pll configuration */ + CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_AudioPll2Ctrl); + /* Enable and power up PLL clock. */ + CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_AudioPll2Clke); + + /* Wait for PLL to be locked. */ + while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_AudioPll2Ctrl)) + { + } +} + +/*! + * brief De-initialize the Audio PLL2. + */ +void CLOCK_DeinitAudioPll2(void) +{ + CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_AudioPll2Ctrl); +} + +/*! + * brief Initializes the ANALOG VIDEO PLL1. + * + * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration). + * + */ +void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config) +{ + assert(config != NULL); + + /* Disable PLL bypass */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_VideoPll1BypassCtrl, false); + /* Fractional pll configuration */ + CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_VideoPll1Ctrl); + /* Enable and power up PLL clock. */ + CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_VideoPll1Clke); + + /* Wait for PLL to be locked. */ + while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_VideoPll1Ctrl)) + { + } +} + +/*! + * brief De-initialize the Video PLL1. + */ +void CLOCK_DeinitVideoPll1(void) +{ + CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_VideoPll1Ctrl); +} + +/*! + * brief Initializes the ANALOG SYS PLL1. + * + * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration). + * + * note This function can't detect whether the SYS PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitSysPll1(const ccm_analog_sscg_pll_config_t *config) +{ + assert(config != NULL); + + /* SSCG PLL configuration */ + CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_SystemPll1Ctrl); + /* Disable PLL bypass */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll1InternalPll1BypassCtrl, false); + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll1InternalPll2BypassCtrl, false); + /* Enable and power up PLL clock. */ + CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_SystemPll1Clke); + + /* Wait for PLL to be locked. */ + while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_SystemPll1Ctrl)) + { + } +} + +/*! + * brief De-initialize the System PLL1. + */ +void CLOCK_DeinitSysPll1(void) +{ + CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_SystemPll1Ctrl); +} + +/*! + * brief Initializes the ANALOG SYS PLL2. + * + * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration). + * + * note This function can't detect whether the SYS PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitSysPll2(const ccm_analog_sscg_pll_config_t *config) +{ + assert(config != NULL); + + /* SSCG PLL configuration */ + CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_SystemPll2Ctrl); + /* Disable PLL bypass */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll2InternalPll1BypassCtrl, false); + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll2InternalPll2BypassCtrl, false); + /* Enable and power up PLL clock. */ + CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_SystemPll2Clke); + + /* Wait for PLL to be locked. */ + while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_SystemPll2Ctrl)) + { + } +} + +/*! + * brief De-initialize the System PLL2. + */ +void CLOCK_DeinitSysPll2(void) +{ + CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_SystemPll2Ctrl); +} + +/*! + * brief Initializes the ANALOG SYS PLL3. + * + * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration). + * + * note This function can't detect whether the SYS PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitSysPll3(const ccm_analog_sscg_pll_config_t *config) +{ + assert(config != NULL); + + /* SSCG PLL configuration */ + CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_SystemPll3Ctrl); + /* Disable PLL bypass */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll3InternalPll1BypassCtrl, false); + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll3InternalPll2BypassCtrl, false); + /* Enable and power up PLL clock. */ + CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_SystemPll3Clke); + + /* Wait for PLL to be locked. */ + while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_SystemPll3Ctrl)) + { + } +} + +/*! + * brief De-initialize the System PLL3. + */ +void CLOCK_DeinitSysPll3(void) +{ + CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_SystemPll3Ctrl); +} + +/*! + * brief Initializes the ANALOG DDR PLL. + * + * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration). + * + * note This function can't detect whether the DDR PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitDramPll(const ccm_analog_sscg_pll_config_t *config) +{ + assert(config != NULL); + + /* init SSCG pll */ + CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_DramPllCtrl); + /* Disable PLL bypass */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_DramPllInternalPll1BypassCtrl, false); + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_DramPllInternalPll2BypassCtrl, false); + /* Enable and power up PLL clock. */ + CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_DramPllClke); + + /* make sure DDR is release from reset, DDR1 should be assigned to special domain first */ + /* trigger the DDR1 power up */ + GPC->PU_PGC_SW_PUP_REQ |= GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_MASK; + /* release DDR1 from reset status */ + SRC->DDRC2_RCR = (SRC->DDRC2_RCR & (~(SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_MASK | SRC_DDRC2_RCR_DDRC1_PHY_RESET_MASK | + SRC_DDRC2_RCR_DDRC2_CORE_RST_MASK | SRC_DDRC2_RCR_DDRC2_PRST_MASK))) | + SRC_DDRC2_RCR_DOM_EN_MASK | SRC_DDRC2_RCR_DOMAIN3_MASK | SRC_DDRC2_RCR_DOMAIN2_MASK | + SRC_DDRC2_RCR_DOMAIN1_MASK | SRC_DDRC2_RCR_DOMAIN0_MASK; + + while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_DramPllCtrl)) + { + } +} + +/*! + * brief De-initialize the Dram PLL. + */ +void CLOCK_DeinitDramPll(void) +{ + CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_DramPllCtrl); +} + +/*! + * brief Initializes the ANALOG VIDEO PLL2. + * + * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration). + * + * note This function can't detect whether the VIDEO PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitVideoPll2(const ccm_analog_sscg_pll_config_t *config) +{ + assert(config != NULL); + + /* init SSCG pll */ + CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_VideoPll2Ctrl); + + /* Disable PLL bypass */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_VideoPll2InternalPll1BypassCtrl, false); + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_VideoPll2InternalPll2BypassCtrl, false); + /* Enable and power up PLL clock. */ + CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_VideoPll2Clke); + + /* Wait for PLL to be locked. */ + while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_VideoPll2Ctrl)) + { + } +} + +/*! + * brief De-initialize the Video PLL2. + */ +void CLOCK_DeinitVideoPll2(void) +{ + CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_VideoPll2Ctrl); +} + +/*! + * brief Initializes the ANALOG Fractional PLL. + * + * param base CCM ANALOG base address. + * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration). + * param type fractional pll type. + * + */ +void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type) +{ + assert(config != NULL); + assert((config->refDiv != 0U) && (config->outDiv != 0U)); + assert((config->outDiv % 2U) == 0U); + assert(type <= kCLOCK_ArmPllCtrl); + + uint32_t fracCfg0 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) | CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_MASK; + uint32_t fracCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 4U); + + /* power down the fractional PLL first */ + CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) = fracCfg0; + + CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) = + (fracCfg0 & + (~(CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK | CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK | + CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK | CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK))) | + (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) / 2U - 1U)) | + (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL((uint32_t)(config->refDiv) - 1U)) | + CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL(config->refSel); + + CCM_ANALOG_TUPLE_REG_OFF(base, type, 4U) = + (fracCfg1 & + (~(CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK | CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK))) | + CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL(config->intDiv) | + CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL(config->fractionDiv); + + /* NEW_DIV_VAL */ + CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) |= CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK; + + /* power up the fractional pll */ + CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) &= ~CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_MASK; + + /* need to check NEW_DIV_ACK */ + while ((CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK) == 0U) + { + } +} + +/*! + * brief Gets the ANALOG Fractional PLL clock frequency. + * + * param base CCM_ANALOG base pointer. + * param type fractional pll type. + * param fractional pll reference clock frequency + * + * return Clock frequency + */ +uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq) +{ + assert(type <= kCLOCK_ArmPllCtrl); + + uint32_t fracCfg0 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U); + uint32_t fracCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 4U); + uint64_t fracClk = 0U; + + uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK, + CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT); + uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK, + CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT); + uint32_t fracDiv = CCM_BIT_FIELD_EXTRACTION(fracCfg1, CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK, + CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT); + uint8_t intDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg1, CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK, + CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT); + + refClkFreq /= (uint32_t)refDiv + 1UL; + fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24U); + + return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U)); +} + +/*! + * brief Initializes the ANALOG SSCG PLL. + * + * param base CCM ANALOG base address + * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration). + * param type sscg pll type + * + */ +void CLOCK_InitSSCGPll(CCM_ANALOG_Type *base, const ccm_analog_sscg_pll_config_t *config, clock_pll_ctrl_t type) +{ + assert(config != NULL); + assert(config->refDiv1 != 0U); + assert(config->refDiv2 != 0U); + assert(config->outDiv != 0U); + assert(config->loopDivider1 != 0U); + assert(config->loopDivider2 != 0U); + assert(type >= kCLOCK_SystemPll1Ctrl); + + uint32_t sscgCfg0 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) | CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_MASK; + uint32_t sscgCfg2 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 8U); + uint32_t pll1Filter = 0U; + + /* power down the SSCG PLL first */ + CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) = sscgCfg0; + + /* pll mux configuration */ + CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) = + (sscgCfg0 & (~CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK)) | config->refSel; + + /* reserve CFG1, spread spectrum */ + + /* match the PLL1 input clock range with PLL filter range */ + if ((CLOCK_GetPllRefClkFreq(type) / (config->refDiv1)) > SSCG_PLL1_FILTER_RANGE) + { + pll1Filter = 1U; + } + /* divider configuration */ + CCM_ANALOG_TUPLE_REG_OFF(base, type, 8U) = + (sscgCfg2 & + (~(CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK | CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK | + CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK | CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK | + CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK))) | + CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) - 1U) | + CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2(config->loopDivider2 - 1U) | + CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1(config->loopDivider1 - 1U) | + CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2((uint32_t)(config->refDiv2) - 1U) | + CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1((uint32_t)(config->refDiv1) - 1U) | pll1Filter; + + /* power up the SSCG PLL */ + CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) &= ~CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_MASK; +} + +/*! + * brief Get the ANALOG SSCG PLL clock frequency. + * + * param base CCM ANALOG base address. + * param type sscg pll type + * param pll1Bypass pll1 bypass flag + * + * return Clock frequency + */ +uint32_t CLOCK_GetSSCGPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass) +{ + assert(type >= kCLOCK_SystemPll1Ctrl); + + uint32_t sscgCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 4U); + uint32_t sscgCfg2 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 8U); + uint64_t pll2InputClock = 0U; + + uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK, + CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_SHIFT) + + 1U; + uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK, + CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_SHIFT) + + 1U; + uint8_t divf1 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK, + CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_SHIFT) + + 1U; + uint8_t divf2 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK, + CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_SHIFT) + + 1U; + uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK, + CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT) + + 1U; + + refClkFreq /= refDiv1; + + if (pll1Bypass) + { + pll2InputClock = refClkFreq; + } + else if ((sscgCfg1 & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_MASK) != 0U) + { + pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2; + } + else + { + pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2; + } + + return (uint32_t)(pll2InputClock * divf2 / outDiv); +} + +/*! + * brief Set root clock divider + * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value + * + * param ccmRootClk Root control (see ref clock_root_control_t enumeration) + * param pre Pre divider value (1-8) + * param post Post divider value (1-64) + */ +void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post) +{ + assert((pre <= 8U) && (pre != 0U)); + assert((post <= 64U) && (post != 0U)); + + CCM_REG(ccmRootClk) = (CCM_REG(ccmRootClk) & (~(CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) | + CCM_TARGET_ROOT_PRE_PODF(pre - 1U) | CCM_TARGET_ROOT_POST_PODF(post - 1U); +} + +/*! + * brief Update clock root in one step, for dynamical clock switching + * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value + * + * param ccmRootClk Root control (see ref clock_root_control_t enumeration) + * param root mux value (see ref _ccm_rootmux_xxx enumeration) + * param pre Pre divider value (0-7, divider=n+1) + * param post Post divider value (0-63, divider=n+1) + */ +void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post) +{ + assert((pre <= 8U) && (pre != 0U)); + assert((post <= 64U) && (post != 0U)); + + CCM_REG(ccmRootClk) = + (CCM_REG(ccmRootClk) & + (~(CCM_TARGET_ROOT_MUX_MASK | CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) | + CCM_TARGET_ROOT_MUX(mux) | CCM_TARGET_ROOT_PRE_PODF(pre - 1U) | CCM_TARGET_ROOT_POST_PODF(post - 1U); +} + +/*! + * brief OSC25M init + * + * param config osc configuration + */ +void CLOCK_InitOSC25M(const osc_config_t *config) +{ + assert(config != NULL); + assert(config->oscDiv != 0U); + + XTALOSC->OSC25M_CTL_CFG = + (XTALOSC->OSC25M_CTL_CFG & (~(XTALOSC_OSC25M_CTL_CFG_OSC_DIV_MASK | XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_MASK))) | + XTALOSC_OSC25M_CTL_CFG_OSC_DIV((uint32_t)(config->oscDiv) - 1U) | + XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS(config->oscMode); + + CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_OSC25MClke); +} + +/*! + * brief OSC25M deinit + * + */ +void CLOCK_DeinitOSC25M(void) +{ + CLOCK_DisableAnalogClock(CCM_ANALOG, kCLOCK_OSC25MClke); +} + +/*! + * brief OSC27M init + * + */ +void CLOCK_InitOSC27M(const osc_config_t *config) +{ + assert(config != NULL); + assert(config->oscDiv != 0U); + + XTALOSC->OSC27M_CTL_CFG = + (XTALOSC->OSC27M_CTL_CFG & (~(XTALOSC_OSC27M_CTL_CFG_OSC_DIV_MASK | XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_MASK))) | + XTALOSC_OSC27M_CTL_CFG_OSC_DIV((uint32_t)(config->oscDiv) - 1U) | + XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS(config->oscMode); + + CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_OSC27MClke); +} + +/*! + * brief OSC27M deinit + * + * param config osc configuration + */ +void CLOCK_DeinitOSC27M(void) +{ + CLOCK_DisableAnalogClock(CCM_ANALOG, kCLOCK_OSC27MClke); +} + +/*! + * brief Enable CCGR clock gate and root clock gate for each module + * User should set specific gate for each module according to the description + * of the table of system clocks, gating and override in CCM chapter of + * reference manual. Take care of that one module may need to set more than + * one clock gate. + * + * param ccmGate Gate control for each module (see ref clock_ip_name_t enumeration). + */ +void CLOCK_EnableClock(clock_ip_name_t ccmGate) +{ + uint32_t ccgr = CCM_TUPLE_CCGR(ccmGate); + uint32_t rootClk = CCM_TUPLE_ROOT(ccmGate); + + CCM_REG_SET(ccgr) = (uint32_t)kCLOCK_ClockNeededAll; + /* if root clock is 0xFFFFU, then skip enable root clock */ + if (rootClk != 0xFFFFU) + { + CCM_REG_SET(rootClk) = CCM_TARGET_ROOT_SET_ENABLE_MASK; + } +} + +/*! + * brief Disable CCGR clock gate for the each module + * User should set specific gate for each module according to the description + * of the table of system clocks, gating and override in CCM chapter of + * reference manual. Take care of that one module may need to set more than + * one clock gate. + * + * param ccmGate Gate control for each module (see ref clock_ip_name_t enumeration). + */ +void CLOCK_DisableClock(clock_ip_name_t ccmGate) +{ + uint32_t ccgr = CCM_TUPLE_CCGR(ccmGate); + uint32_t rootClk = CCM_TUPLE_ROOT(ccmGate); + + CCM_REG(ccgr) = (uint32_t)kCLOCK_ClockNotNeeded; + + /* if root clock is 0xFFFFU, then skip disable root clock */ + if (rootClk != 0xFFFFU) + { + CCM_REG_CLR(rootClk) = CCM_TARGET_ROOT_CLR_ENABLE_MASK; + } +} diff --git a/devices/MIMX8MQ6/drivers/fsl_clock.h b/devices/MIMX8MQ6/drivers/fsl_clock.h new file mode 100644 index 000000000..7fa1c38ef --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_clock.h @@ -0,0 +1,1349 @@ +/* + * Copyright 2017 - 2020, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_device_registers.h" +#include +#include +#include +#include + +/*! + * @addtogroup clock + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.3.3. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) +/*@}*/ + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (400000000UL) +#endif + +/*! + * @brief XTAL 25M clock frequency. + */ +#define OSC25M_CLK_FREQ 25000000U + +/*! + * @brief XTAL 27M clock frequency. + */ +#define OSC27M_CLK_FREQ 27000000U + +/*! + * @brief HDMI PHY 27M clock frequency. + */ +#define HDMI_PHY_27M_FREQ 27000000U + +/*! + * @brief clock1PN frequency. + */ +#define CLKPN_FREQ 0U + +/*! @brief Clock ip name array for ECSPI. */ +#define ECSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Ecspi1, kCLOCK_Ecspi2, kCLOCK_Ecspi3, \ + } + +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, \ + } + +/*! @brief Clock ip name array for GPT. */ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6, \ + } + +/*! @brief Clock ip name array for I2C. */ +#define I2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, \ + } + +/*! @brief Clock ip name array for IOMUX. */ +#define IOMUX_CLOCKS \ + { \ + kCLOCK_Iomux, \ + } + +/*! @brief Clock ip name array for IPMUX. */ +#define IPMUX_CLOCKS \ + { \ + kCLOCK_Ipmux1, kCLOCK_Ipmux2, kCLOCK_Ipmux3, kCLOCK_Ipmux4, \ + } + +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Pwm1, kCLOCK_Pwm2, kCLOCK_Pwm3, kCLOCK_Pwm4, \ + } + +/*! @brief Clock ip name array for RDC. */ +#define RDC_CLOCKS \ + { \ + kCLOCK_Rdc, \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4, kCLOCK_Sai5, kCLOCK_Sai6, \ + } + +/*! @brief Clock ip name array for RDC SEMA42. */ +#define RDC_SEMA42_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sema42_1, kCLOCK_Sema42_2 \ + } + +/*! @brief Clock ip name array for UART. */ +#define UART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \ + } + +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ + } + +/*! @brief Clock ip name array for WDOG. */ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3 \ + } + +/*! @brief Clock ip name array for TEMPSENSOR. */ +#define TMU_CLOCKS \ + { \ + kCLOCK_TempSensor, \ + } + +/*! @brief Clock ip name array for SDMA. */ +#define SDMA_CLOCKS \ + { \ + kCLOCK_Sdma1, kCLOCK_Sdma2 \ + } + +/*! @brief Clock ip name array for MU. */ +#define MU_CLOCKS \ + { \ + kCLOCK_Mu \ + } + +/*! @brief Clock ip name array for QSPI. */ +#define QSPI_CLOCKS \ + { \ + kCLOCK_Qspi \ + } + +/*! + * @brief CCM reg macros to extract corresponding registers bit field. + */ +#define CCM_BIT_FIELD_EXTRACTION(val, mask, shift) (((val) & (mask)) >> (shift)) + +/*! + * @brief CCM reg macros to map corresponding registers. + */ +#define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)(root) + (off)))) +#define CCM_REG(root) CCM_REG_OFF(root, 0U) +#define CCM_REG_SET(root) CCM_REG_OFF(root, 4U) +#define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U) + +/*! + * @brief CCM Analog registers offset. + */ +#define AUDIO_PLL1_CFG0_OFFSET 0x00 +#define AUDIO_PLL2_CFG0_OFFSET 0x08 +#define VIDEO_PLL1_CFG0_OFFSET 0x10 +#define GPU_PLL_CFG0_OFFSET 0x18 +#define VPU_PLL_CFG0_OFFSET 0x20 +#define ARM_PLL_CFG0_OFFSET 0x28 +#define SYS_PLL1_CFG0_OFFSET 0x30 +#define SYS_PLL2_CFG0_OFFSET 0x3C +#define SYS_PLL3_CFG0_OFFSET 0x48 +#define VIDEO_PLL2_CFG0_OFFSET 0x54 +#define DRAM_PLL_CFG0_OFFSET 0x60 +#define OSC_MISC_CFG_OFFSET 0x70 + +/*! + * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields. + */ +#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFFU) << 16U) | (shift)) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \ + (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFFU) + (off)))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U) + +/*! + * @brief CCM CCGR and root tuple + */ +#define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) +#define CCM_TUPLE_CCGR(tuple) ((uint32_t)(&(CCM)->CCGR[(uint32_t)(tuple) >> 16U].CCGR)) +#define CCM_TUPLE_ROOT(tuple) ((uint32_t)(&(CCM)->ROOT[(uint32_t)(tuple)&0xFFFFU].TARGET_ROOT)) + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CoreM4Clk, /*!< ARM M4 Core clock */ + + kCLOCK_AxiClk, /*!< Main AXI bus clock. */ + kCLOCK_AhbClk, /*!< AHB bus clock. */ + kCLOCK_IpgClk, /*!< IPG bus clock. */ + + /* -------------------------------- Other clock --------------------------*/ +} clock_name_t; + +#define kCLOCK_CoreSysClk kCLOCK_CoreM4Clk /*!< For compatible with other platforms without CCM. */ +#define CLOCK_GetCoreSysClkFreq CLOCK_GetCoreM4Freq /*!< For compatible with other platforms without CCM. */ + +/*! @brief CCM CCGR gate control. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = -1, + + kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/ + + kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/ + + kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/ + kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/ + kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/ + + kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/ + kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/ + kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/ + kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/ + kCLOCK_Gpio5 = CCM_TUPLE(15U, 33U), /*!< GPIO5 Clock Gate.*/ + + kCLOCK_Gpt1 = CCM_TUPLE(16U, 107U), /*!< GPT1 Clock Gate.*/ + kCLOCK_Gpt2 = CCM_TUPLE(17U, 108U), /*!< GPT2 Clock Gate.*/ + kCLOCK_Gpt3 = CCM_TUPLE(18U, 109U), /*!< GPT3 Clock Gate.*/ + kCLOCK_Gpt4 = CCM_TUPLE(19U, 110U), /*!< GPT4 Clock Gate.*/ + kCLOCK_Gpt5 = CCM_TUPLE(20U, 111U), /*!< GPT5 Clock Gate.*/ + kCLOCK_Gpt6 = CCM_TUPLE(21U, 112U), /*!< GPT6 Clock Gate.*/ + + kCLOCK_I2c1 = CCM_TUPLE(23U, 90U), /*!< I2C1 Clock Gate.*/ + kCLOCK_I2c2 = CCM_TUPLE(24U, 91U), /*!< I2C2 Clock Gate.*/ + kCLOCK_I2c3 = CCM_TUPLE(25U, 92U), /*!< I2C3 Clock Gate.*/ + kCLOCK_I2c4 = CCM_TUPLE(26U, 93U), /*!< I2C4 Clock Gate.*/ + + kCLOCK_Iomux = CCM_TUPLE(27U, 33U), /*!< IOMUX Clock Gate.*/ + kCLOCK_Ipmux1 = CCM_TUPLE(28U, 33U), /*!< IPMUX1 Clock Gate.*/ + kCLOCK_Ipmux2 = CCM_TUPLE(29U, 33U), /*!< IPMUX2 Clock Gate.*/ + kCLOCK_Ipmux3 = CCM_TUPLE(30U, 33U), /*!< IPMUX3 Clock Gate.*/ + kCLOCK_Ipmux4 = CCM_TUPLE(31U, 33U), /*!< IPMUX4 Clock Gate.*/ + + kCLOCK_M4 = CCM_TUPLE(32U, 1U), /*!< M4 Clock Gate.*/ + + kCLOCK_Mu = CCM_TUPLE(33U, 33U), /*!< MU Clock Gate.*/ + + kCLOCK_Ocram = CCM_TUPLE(35U, 16U), /*!< OCRAM Clock Gate.*/ + kCLOCK_OcramS = CCM_TUPLE(36U, 32U), /*!< OCRAM S Clock Gate.*/ + + kCLOCK_Pwm1 = CCM_TUPLE(40U, 103U), /*!< PWM1 Clock Gate.*/ + kCLOCK_Pwm2 = CCM_TUPLE(41U, 104U), /*!< PWM2 Clock Gate.*/ + kCLOCK_Pwm3 = CCM_TUPLE(42U, 105U), /*!< PWM3 Clock Gate.*/ + kCLOCK_Pwm4 = CCM_TUPLE(43U, 106U), /*!< PWM4 Clock Gate.*/ + + kCLOCK_Qspi = CCM_TUPLE(47U, 87U), /*!< QSPI Clock Gate.*/ + + kCLOCK_Rdc = CCM_TUPLE(49U, 33U), /*!< RDC Clock Gate.*/ + + kCLOCK_Sai1 = CCM_TUPLE(51U, 75U), /*!< SAI1 Clock Gate.*/ + kCLOCK_Sai2 = CCM_TUPLE(52U, 76U), /*!< SAI2 Clock Gate.*/ + kCLOCK_Sai3 = CCM_TUPLE(53U, 77U), /*!< SAI3 Clock Gate.*/ + kCLOCK_Sai4 = CCM_TUPLE(54U, 78U), /*!< SAI4 Clock Gate.*/ + kCLOCK_Sai5 = CCM_TUPLE(55U, 79U), /*!< SAI5 Clock Gate.*/ + kCLOCK_Sai6 = CCM_TUPLE(56U, 80U), /*!< SAI6 Clock Gate.*/ + + kCLOCK_Sdma1 = CCM_TUPLE(58U, 33U), /*!< SDMA1 Clock Gate.*/ + kCLOCK_Sdma2 = CCM_TUPLE(59U, 35U), /*!< SDMA2 Clock Gate.*/ + + kCLOCK_Sec_Debug = CCM_TUPLE(60U, 33U), /*!< SEC_DEBUG Clock Gate.*/ + + kCLOCK_Sema42_1 = CCM_TUPLE(61U, 33U), /*!< RDC SEMA42 Clock Gate.*/ + kCLOCK_Sema42_2 = CCM_TUPLE(62U, 33U), /*!< RDC SEMA42 Clock Gate.*/ + + kCLOCK_Sim_display = CCM_TUPLE(63U, 16U), /*!< SIM_Display Clock Gate.*/ + kCLOCK_Sim_m = CCM_TUPLE(65U, 32U), /*!< SIM_M Clock Gate.*/ + kCLOCK_Sim_main = CCM_TUPLE(66U, 16U), /*!< SIM_MAIN Clock Gate.*/ + kCLOCK_Sim_s = CCM_TUPLE(67U, 32U), /*!< SIM_S Clock Gate.*/ + kCLOCK_Sim_wakeup = CCM_TUPLE(68U, 32U), /*!< SIM_WAKEUP Clock Gate.*/ + + kCLOCK_Uart1 = CCM_TUPLE(73U, 94U), /*!< UART1 Clock Gate.*/ + kCLOCK_Uart2 = CCM_TUPLE(74U, 95U), /*!< UART2 Clock Gate.*/ + kCLOCK_Uart3 = CCM_TUPLE(75U, 96U), /*!< UART3 Clock Gate.*/ + kCLOCK_Uart4 = CCM_TUPLE(76U, 97U), /*!< UART4 Clock Gate.*/ + + kCLOCK_Wdog1 = CCM_TUPLE(83U, 114U), /*!< WDOG1 Clock Gate.*/ + kCLOCK_Wdog2 = CCM_TUPLE(84U, 114U), /*!< WDOG2 Clock Gate.*/ + kCLOCK_Wdog3 = CCM_TUPLE(85U, 114U), /*!< WDOG3 Clock Gate.*/ + + kCLOCK_TempSensor = CCM_TUPLE(98U, 0xFFFF), /*!< TempSensor Clock Gate.*/ + +} clock_ip_name_t; + +/*! @brief ccm root name used to get clock frequency. */ +typedef enum _clock_root_control +{ + kCLOCK_RootM4 = (uint32_t)(&(CCM)->ROOT[1].TARGET_ROOT), /*!< ARM Cortex-M4 Clock control name.*/ + kCLOCK_RootAxi = (uint32_t)(&(CCM)->ROOT[16].TARGET_ROOT), /*!< AXI Clock control name.*/ + kCLOCK_RootNoc = (uint32_t)(&(CCM)->ROOT[26].TARGET_ROOT), /*!< NOC Clock control name.*/ + kCLOCK_RootAhb = (uint32_t)(&(CCM)->ROOT[32].TARGET_ROOT), /*!< AHB Clock control name.*/ + kCLOCK_RootIpg = (uint32_t)(&(CCM)->ROOT[33].TARGET_ROOT), /*!< IPG Clock control name.*/ + kCLOCK_RootDramAlt = (uint32_t)(&(CCM)->ROOT[64].TARGET_ROOT), /*!< DRAM ALT Clock control name.*/ + + kCLOCK_RootSai1 = (uint32_t)(&(CCM)->ROOT[75].TARGET_ROOT), /*!< SAI1 Clock control name.*/ + kCLOCK_RootSai2 = (uint32_t)(&(CCM)->ROOT[76].TARGET_ROOT), /*!< SAI2 Clock control name.*/ + kCLOCK_RootSai3 = (uint32_t)(&(CCM)->ROOT[77].TARGET_ROOT), /*!< SAI3 Clock control name.*/ + kCLOCK_RootSai4 = (uint32_t)(&(CCM)->ROOT[78].TARGET_ROOT), /*!< SAI4 Clock control name.*/ + kCLOCK_RootSai5 = (uint32_t)(&(CCM)->ROOT[79].TARGET_ROOT), /*!< SAI5 Clock control name.*/ + kCLOCK_RootSai6 = (uint32_t)(&(CCM)->ROOT[80].TARGET_ROOT), /*!< SAI6 Clock control name.*/ + + kCLOCK_RootQspi = (uint32_t)(&(CCM)->ROOT[87].TARGET_ROOT), /*!< QSPI Clock control name.*/ + + kCLOCK_RootI2c1 = (uint32_t)(&(CCM)->ROOT[90].TARGET_ROOT), /*!< I2C1 Clock control name.*/ + kCLOCK_RootI2c2 = (uint32_t)(&(CCM)->ROOT[91].TARGET_ROOT), /*!< I2C2 Clock control name.*/ + kCLOCK_RootI2c3 = (uint32_t)(&(CCM)->ROOT[92].TARGET_ROOT), /*!< I2C3 Clock control name.*/ + kCLOCK_RootI2c4 = (uint32_t)(&(CCM)->ROOT[93].TARGET_ROOT), /*!< I2C4 Clock control name.*/ + + kCLOCK_RootUart1 = (uint32_t)(&(CCM)->ROOT[94].TARGET_ROOT), /*!< UART1 Clock control name.*/ + kCLOCK_RootUart2 = (uint32_t)(&(CCM)->ROOT[95].TARGET_ROOT), /*!< UART2 Clock control name.*/ + kCLOCK_RootUart3 = (uint32_t)(&(CCM)->ROOT[96].TARGET_ROOT), /*!< UART3 Clock control name.*/ + kCLOCK_RootUart4 = (uint32_t)(&(CCM)->ROOT[97].TARGET_ROOT), /*!< UART4 Clock control name.*/ + + kCLOCK_RootEcspi1 = (uint32_t)(&(CCM)->ROOT[101].TARGET_ROOT), /*!< ECSPI1 Clock control name.*/ + kCLOCK_RootEcspi2 = (uint32_t)(&(CCM)->ROOT[102].TARGET_ROOT), /*!< ECSPI2 Clock control name.*/ + kCLOCK_RootEcspi3 = (uint32_t)(&(CCM)->ROOT[131].TARGET_ROOT), /*!< ECSPI3 Clock control name.*/ + + kCLOCK_RootPwm1 = (uint32_t)(&(CCM)->ROOT[103].TARGET_ROOT), /*!< PWM1 Clock control name.*/ + kCLOCK_RootPwm2 = (uint32_t)(&(CCM)->ROOT[104].TARGET_ROOT), /*!< PWM2 Clock control name.*/ + kCLOCK_RootPwm3 = (uint32_t)(&(CCM)->ROOT[105].TARGET_ROOT), /*!< PWM3 Clock control name.*/ + kCLOCK_RootPwm4 = (uint32_t)(&(CCM)->ROOT[106].TARGET_ROOT), /*!< PWM4 Clock control name.*/ + + kCLOCK_RootGpt1 = (uint32_t)(&(CCM)->ROOT[107].TARGET_ROOT), /*!< GPT1 Clock control name.*/ + kCLOCK_RootGpt2 = (uint32_t)(&(CCM)->ROOT[108].TARGET_ROOT), /*!< GPT2 Clock control name.*/ + kCLOCK_RootGpt3 = (uint32_t)(&(CCM)->ROOT[109].TARGET_ROOT), /*!< GPT3 Clock control name.*/ + kCLOCK_RootGpt4 = (uint32_t)(&(CCM)->ROOT[110].TARGET_ROOT), /*!< GPT4 Clock control name.*/ + kCLOCK_RootGpt5 = (uint32_t)(&(CCM)->ROOT[111].TARGET_ROOT), /*!< GPT5 Clock control name.*/ + kCLOCK_RootGpt6 = (uint32_t)(&(CCM)->ROOT[112].TARGET_ROOT), /*!< GPT6 Clock control name.*/ + + kCLOCK_RootWdog = (uint32_t)(&(CCM)->ROOT[114].TARGET_ROOT), /*!< WDOG Clock control name.*/ +} clock_root_control_t; + +/*! @brief Root clock select enumeration for ARM Cortex-M4 core. */ +typedef enum _clock_rootmux_m4_clk_sel +{ + kCLOCK_M4RootmuxOsc25m = 0U, /*!< ARM Cortex-M4 Clock from OSC 25M.*/ + kCLOCK_M4RootmuxSysPll2Div5 = 1U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 5.*/ + kCLOCK_M4RootmuxSysPll2Div4 = 2U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 4.*/ + kCLOCK_M4RootmuxSysPll1Div3 = 3U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL1 divided by 3.*/ + kCLOCK_M4RootmuxSysPll1 = 4U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL1.*/ + kCLOCK_M4RootmuxAudioPll1 = 5U, /*!< ARM Cortex-M4 Clock from AUDIO PLL1.*/ + kCLOCK_M4RootmuxVideoPll1 = 6U, /*!< ARM Cortex-M4 Clock from VIDEO PLL1.*/ + kCLOCK_M4RootmuxSysPll3 = 7U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL3.*/ +} clock_rootmux_m4_clk_sel_t; + +/*! @brief Root clock select enumeration for AXI bus. */ +typedef enum _clock_rootmux_axi_clk_sel +{ + kCLOCK_AxiRootmuxOsc25m = 0U, /*!< ARM AXI Clock from OSC 25M.*/ + kCLOCK_AxiRootmuxSysPll2Div3 = 1U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 3.*/ + kCLOCK_AxiRootmuxSysPll1 = 2U, /*!< ARM AXI Clock from SYSTEM PLL1.*/ + kCLOCK_AxiRootmuxSysPll2Div4 = 3U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 4.*/ + kCLOCK_AxiRootmuxSysPll2 = 4U, /*!< ARM AXI Clock from SYSTEM PLL2.*/ + kCLOCK_AxiRootmuxAudioPll1 = 5U, /*!< ARM AXI Clock from AUDIO PLL1.*/ + kCLOCK_AxiRootmuxVideoPll1 = 6U, /*!< ARM AXI Clock from VIDEO PLL1.*/ + kCLOCK_AxiRootmuxSysPll1Div8 = 7U, /*!< ARM AXI Clock from SYSTEM PLL1 divided by 8.*/ +} clock_rootmux_axi_clk_sel_t; + +/*! @brief Root clock select enumeration for AHB bus. */ +typedef enum _clock_rootmux_ahb_clk_sel +{ + kCLOCK_AhbRootmuxOsc25m = 0U, /*!< ARM AHB Clock from OSC 25M.*/ + kCLOCK_AhbRootmuxSysPll1Div6 = 1U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 6.*/ + kCLOCK_AhbRootmuxSysPll1 = 2U, /*!< ARM AHB Clock from SYSTEM PLL1.*/ + kCLOCK_AhbRootmuxSysPll1Div2 = 3U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 2.*/ + kCLOCK_AhbRootmuxSysPll2Div8 = 4U, /*!< ARM AHB Clock from SYSTEM PLL2 divided by 8.*/ + kCLOCK_AhbRootmuxSysPll3 = 5U, /*!< ARM AHB Clock from SYSTEM PLL3.*/ + kCLOCK_AhbRootmuxAudioPll1 = 6U, /*!< ARM AHB Clock from AUDIO PLL1.*/ + kCLOCK_AhbRootmuxVideoPll1 = 7U, /*!< ARM AHB Clock from VIDEO PLL1.*/ +} clock_rootmux_ahb_clk_sel_t; + +/*! @brief Root clock select enumeration for QSPI peripheral. */ +typedef enum _clock_rootmux_qspi_clk_sel +{ + kCLOCK_QspiRootmuxOsc25m = 0U, /*!< ARM QSPI Clock from OSC 25M.*/ + kCLOCK_QspiRootmuxSysPll1Div2 = 1U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 2.*/ + kCLOCK_QspiRootmuxSysPll1 = 2U, /*!< ARM QSPI Clock from SYSTEM PLL1.*/ + kCLOCK_QspiRootmuxSysPll2Div2 = 3U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 2.*/ + kCLOCK_QspiRootmuxAudioPll2 = 4, /*!< ARM QSPI Clock from AUDIO PLL2.*/ + kCLOCK_QspiRootmuxSysPll1Div3 = 5U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 3 */ + kCLOCK_QspiRootmuxSysPll3 = 6U, /*!< ARM QSPI Clock from SYSTEM PLL3.*/ + kCLOCK_QspiRootmuxSysPll1Div8 = 7U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 8.*/ +} clock_rootmux_qspi_clk_sel_t; + +/*! @brief Root clock select enumeration for ECSPI peripheral. */ +typedef enum _clock_rootmux_ecspi_clk_sel +{ + kCLOCK_EcspiRootmuxOsc25m = 0U, /*!< ECSPI Clock from OSC 25M.*/ + kCLOCK_EcspiRootmuxSysPll2Div5 = 1U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 5.*/ + kCLOCK_EcspiRootmuxSysPll1Div20 = 2U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 20.*/ + kCLOCK_EcspiRootmuxSysPll1Div5 = 3U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 5.*/ + kCLOCK_EcspiRootmuxSysPll1 = 4U, /*!< ECSPI Clock from SYSTEM PLL1.*/ + kCLOCK_EcspiRootmuxSysPll3 = 5U, /*!< ECSPI Clock from SYSTEM PLL3.*/ + kCLOCK_EcspiRootmuxSysPll2Div4 = 6U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 4.*/ + kCLOCK_EcspiRootmuxAudioPll2 = 7U, /*!< ECSPI Clock from AUDIO PLL2.*/ +} clock_rootmux_ecspi_clk_sel_t; + +/*! @brief Root clock select enumeration for I2C peripheral. */ +typedef enum _clock_rootmux_i2c_clk_sel +{ + kCLOCK_I2cRootmuxOsc25m = 0U, /*!< I2C Clock from OSC 25M.*/ + kCLOCK_I2cRootmuxSysPll1Div5 = 1U, /*!< I2C Clock from SYSTEM PLL1 divided by 5.*/ + kCLOCK_I2cRootmuxSysPll2Div20 = 2U, /*!< I2C Clock from SYSTEM PLL2 divided by 20.*/ + kCLOCK_I2cRootmuxSysPll3 = 3U, /*!< I2C Clock from SYSTEM PLL3 .*/ + kCLOCK_I2cRootmuxAudioPll1 = 4U, /*!< I2C Clock from AUDIO PLL1.*/ + kCLOCK_I2cRootmuxVideoPll1 = 5U, /*!< I2C Clock from VIDEO PLL1.*/ + kCLOCK_I2cRootmuxAudioPll2 = 6U, /*!< I2C Clock from AUDIO PLL2.*/ + kCLOCK_I2cRootmuxSysPll1Div6 = 7U, /*!< I2C Clock from SYSTEM PLL1 divided by 6.*/ +} clock_rootmux_i2c_clk_sel_t; + +/*! @brief Root clock select enumeration for UART peripheral. */ +typedef enum _clock_rootmux_uart_clk_sel +{ + kCLOCK_UartRootmuxOsc25m = 0U, /*!< UART Clock from OSC 25M.*/ + kCLOCK_UartRootmuxSysPll1Div10 = 1U, /*!< UART Clock from SYSTEM PLL1 divided by 10.*/ + kCLOCK_UartRootmuxSysPll2Div5 = 2U, /*!< UART Clock from SYSTEM PLL2 divided by 5.*/ + kCLOCK_UartRootmuxSysPll2Div10 = 3U, /*!< UART Clock from SYSTEM PLL2 divided by 10.*/ + kCLOCK_UartRootmuxSysPll3 = 4U, /*!< UART Clock from SYSTEM PLL3.*/ + kCLOCK_UartRootmuxExtClk2 = 5U, /*!< UART Clock from External Clock 2.*/ + kCLOCK_UartRootmuxExtClk34 = 6U, /*!< UART Clock from External Clock 3, External Clock 4.*/ + kCLOCK_UartRootmuxAudioPll2 = 7U, /*!< UART Clock from Audio PLL2.*/ +} clock_rootmux_uart_clk_sel_t; + +/*! @brief Root clock select enumeration for GPT peripheral. */ +typedef enum _clock_rootmux_gpt +{ + kCLOCK_GptRootmuxOsc25m = 0U, /*!< GPT Clock from OSC 25M.*/ + kCLOCK_GptRootmuxSystemPll2Div10 = 1U, /*!< GPT Clock from SYSTEM PLL2 divided by 10.*/ + kCLOCK_GptRootmuxSysPll1Div2 = 2U, /*!< GPT Clock from SYSTEM PLL1 divided by 2.*/ + kCLOCK_GptRootmuxSysPll1Div20 = 3U, /*!< GPT Clock from SYSTEM PLL1 divided by 20.*/ + kCLOCK_GptRootmuxVideoPll1 = 4U, /*!< GPT Clock from VIDEO PLL1.*/ + kCLOCK_GptRootmuxSystemPll1Div10 = 5U, /*!< GPT Clock from SYSTEM PLL1 divided by 10.*/ + kCLOCK_GptRootmuxAudioPll1 = 6U, /*!< GPT Clock from AUDIO PLL1.*/ + kCLOCK_GptRootmuxExtClk123 = 7U, /*!< GPT Clock from External Clock1, External Clock2, External Clock3.*/ +} clock_rootmux_gpt_t; + +/*! @brief Root clock select enumeration for WDOG peripheral. */ +typedef enum _clock_rootmux_wdog_clk_sel +{ + kCLOCK_WdogRootmuxOsc25m = 0U, /*!< WDOG Clock from OSC 25M.*/ + kCLOCK_WdogRootmuxSysPll1Div6 = 1U, /*!< WDOG Clock from SYSTEM PLL1 divided by 6.*/ + kCLOCK_WdogRootmuxSysPll1Div5 = 2U, /*!< WDOG Clock from SYSTEM PLL1 divided by 5.*/ + kCLOCK_WdogRootmuxVpuPll = 3U, /*!< WDOG Clock from VPU DLL.*/ + kCLOCK_WdogRootmuxSystemPll2Div8 = 4U, /*!< WDOG Clock from SYSTEM PLL2 divided by 8.*/ + kCLOCK_WdogRootmuxSystemPll3 = 5U, /*!< WDOG Clock from SYSTEM PLL3.*/ + kCLOCK_WdogRootmuxSystemPll1Div10 = 6U, /*!< WDOG Clock from SYSTEM PLL1 divided by 10.*/ + kCLOCK_WdogRootmuxSystemPll2Div6 = 7U, /*!< WDOG Clock from SYSTEM PLL2 divided by 6.*/ +} clock_rootmux_wdog_clk_sel_t; + +/*! @brief Root clock select enumeration for PWM peripheral. */ +typedef enum _clock_rootmux_pwm_clk_sel +{ + kCLOCK_PwmRootmuxOsc25m = 0U, /*!< PWM Clock from OSC 25M.*/ + kCLOCK_PwmRootmuxSysPll2Div10 = 1U, /*!< PWM Clock from SYSTEM PLL2 divided by 10.*/ + kCLOCK_PwmRootmuxSysPll1Div5 = 2U, /*!< PWM Clock from SYSTEM PLL1 divided by 5.*/ + kCLOCK_PwmRootmuxSysPll1Div20 = 3U, /*!< PWM Clock from SYSTEM PLL1 divided by 20.*/ + kCLOCK_PwmRootmuxSystemPll3 = 4U, /*!< PWM Clock from SYSTEM PLL3.*/ + kCLOCK_PwmRootmuxExtClk12 = 5U, /*!< PWM Clock from External Clock1, External Clock2.*/ + kCLOCK_PwmRootmuxSystemPll1Div10 = 6U, /*!< PWM Clock from SYSTEM PLL1 divided by 10.*/ + kCLOCK_PwmRootmuxVideoPll1 = 7U, /*!< PWM Clock from VIDEO PLL1.*/ +} clock_rootmux_Pwm_clk_sel_t; + +/*! @brief Root clock select enumeration for SAI peripheral. */ +typedef enum _clock_rootmux_sai_clk_sel +{ + kCLOCK_SaiRootmuxOsc25m = 0U, /*!< SAI Clock from OSC 25M.*/ + kCLOCK_SaiRootmuxAudioPll1 = 1U, /*!< SAI Clock from AUDIO PLL1.*/ + kCLOCK_SaiRootmuxAudioPll2 = 2U, /*!< SAI Clock from AUDIO PLL2.*/ + kCLOCK_SaiRootmuxVideoPll1 = 3U, /*!< SAI Clock from VIDEO PLL1.*/ + kCLOCK_SaiRootmuxSysPll1Div6 = 4U, /*!< SAI Clock from SYSTEM PLL1 divided by 6.*/ + kCLOCK_SaiRootmuxOsc27m = 5U, /*!< SAI Clock from OSC 27M.*/ + kCLOCK_SaiRootmuxExtClk123 = 6U, /*!< SAI Clock from External Clock1, External Clock2, External Clock3.*/ + kCLOCK_SaiRootmuxExtClk234 = 7U, /*!< SAI Clock from External Clock2, External Clock3, External Clock4.*/ +} clock_rootmux_sai_clk_sel_t; + +/*! @brief Root clock select enumeration for NOC CLK. */ +typedef enum _clock_rootmux_noc_clk_sel +{ + kCLOCK_NocRootmuxOsc25m = 0U, /*!< NOC Clock from OSC 25M.*/ + kCLOCK_NocRootmuxSysPll1 = 1U, /*!< NOC Clock from SYSTEM PLL1.*/ + kCLOCK_NocRootmuxSysPll3 = 2U, /*!< NOC Clock from SYSTEM PLL3.*/ + kCLOCK_NocRootmuxSysPll2 = 3U, /*!< NOC Clock from SYSTEM PLL2.*/ + kCLOCK_NocRootmuxSysPll2Div2 = 4U, /*!< NOC Clock from SYSTEM PLL2 divided by 2.*/ + kCLOCK_NocRootmuxAudioPll1 = 5U, /*!< NOC Clock from AUDIO PLL1.*/ + kCLOCK_NocRootmuxVideoPll1 = 6U, /*!< NOC Clock from VIDEO PLL1.*/ + kCLOCK_NocRootmuxAudioPll2 = 7U, /*!< NOC Clock from AUDIO PLL2.*/ + +} clock_rootmux_noc_clk_sel_t; + +/*! @brief CCM PLL gate control. */ +typedef enum _clock_pll_gate +{ + kCLOCK_ArmPllGate = (uint32_t)(&(CCM)->PLL_CTRL[12].PLL_CTRL), /*!< ARM PLL Gate.*/ + + kCLOCK_GpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[13].PLL_CTRL), /*!< GPU PLL Gate.*/ + kCLOCK_VpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[14].PLL_CTRL), /*!< VPU PLL Gate.*/ + kCLOCK_DramPllGate = (uint32_t)(&(CCM)->PLL_CTRL[15].PLL_CTRL), /*!< DRAM PLL1 Gate.*/ + + kCLOCK_SysPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[16].PLL_CTRL), /*!< SYSTEM PLL1 Gate.*/ + kCLOCK_SysPll1Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[17].PLL_CTRL), /*!< SYSTEM PLL1 Div2 Gate.*/ + kCLOCK_SysPll1Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[18].PLL_CTRL), /*!< SYSTEM PLL1 Div3 Gate.*/ + kCLOCK_SysPll1Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[19].PLL_CTRL), /*!< SYSTEM PLL1 Div4 Gate.*/ + kCLOCK_SysPll1Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[20].PLL_CTRL), /*!< SYSTEM PLL1 Div5 Gate.*/ + kCLOCK_SysPll1Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[21].PLL_CTRL), /*!< SYSTEM PLL1 Div6 Gate.*/ + kCLOCK_SysPll1Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[22].PLL_CTRL), /*!< SYSTEM PLL1 Div8 Gate.*/ + kCLOCK_SysPll1Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[23].PLL_CTRL), /*!< SYSTEM PLL1 Div10 Gate.*/ + kCLOCK_SysPll1Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[24].PLL_CTRL), /*!< SYSTEM PLL1 Div20 Gate.*/ + + kCLOCK_SysPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[25].PLL_CTRL), /*!< SYSTEM PLL2 Gate.*/ + kCLOCK_SysPll2Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[26].PLL_CTRL), /*!< SYSTEM PLL2 Div2 Gate.*/ + kCLOCK_SysPll2Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[27].PLL_CTRL), /*!< SYSTEM PLL2 Div3 Gate.*/ + kCLOCK_SysPll2Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[28].PLL_CTRL), /*!< SYSTEM PLL2 Div4 Gate.*/ + kCLOCK_SysPll2Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[29].PLL_CTRL), /*!< SYSTEM PLL2 Div5 Gate.*/ + kCLOCK_SysPll2Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[30].PLL_CTRL), /*!< SYSTEM PLL2 Div6 Gate.*/ + kCLOCK_SysPll2Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[31].PLL_CTRL), /*!< SYSTEM PLL2 Div8 Gate.*/ + kCLOCK_SysPll2Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[32].PLL_CTRL), /*!< SYSTEM PLL2 Div10 Gate.*/ + kCLOCK_SysPll2Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[33].PLL_CTRL), /*!< SYSTEM PLL2 Div20 Gate.*/ + + kCLOCK_SysPll3Gate = (uint32_t)(&(CCM)->PLL_CTRL[34].PLL_CTRL), /*!< SYSTEM PLL3 Gate.*/ + + kCLOCK_AudioPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[35].PLL_CTRL), /*!< AUDIO PLL1 Gate.*/ + kCLOCK_AudioPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[36].PLL_CTRL), /*!< AUDIO PLL2 Gate.*/ + kCLOCK_VideoPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[37].PLL_CTRL), /*!< VIDEO PLL1 Gate.*/ + kCLOCK_VideoPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[38].PLL_CTRL), /*!< VIDEO PLL2 Gate.*/ +} clock_pll_gate_t; + +/*! @brief CCM gate control value. */ +typedef enum _clock_gate_value +{ + kCLOCK_ClockNotNeeded = 0x0U, /*!< Clock always disabled.*/ + kCLOCK_ClockNeededRun = 0x1111U, /*!< Clock enabled when CPU is running.*/ + kCLOCK_ClockNeededRunWait = 0x2222U, /*!< Clock enabled when CPU is running or in WAIT mode.*/ + kCLOCK_ClockNeededAll = 0x3333U, /*!< Clock always enabled.*/ +} clock_gate_value_t; + +/*! + * @brief PLL control names for PLL bypass. + * + * These constants define the PLL control names for PLL bypass.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: bypass bit shift. + */ +typedef enum _clock_pll_bypass_ctrl +{ + kCLOCK_AudioPll1BypassCtrl = CCM_ANALOG_TUPLE( + AUDIO_PLL1_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL1 bypass Control.*/ + kCLOCK_AudioPll2BypassCtrl = CCM_ANALOG_TUPLE( + AUDIO_PLL2_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL2 bypass Control.*/ + kCLOCK_VideoPll1BypassCtrl = CCM_ANALOG_TUPLE( + VIDEO_PLL1_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Video Pll1 bypass Control.*/ + kCLOCK_GpuPLLPwrBypassCtrl = CCM_ANALOG_TUPLE( + GPU_PLL_CFG0_OFFSET, CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Gpu PLL bypass Control.*/ + kCLOCK_VpuPllPwrBypassCtrl = CCM_ANALOG_TUPLE( + VPU_PLL_CFG0_OFFSET, CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Vpu PLL bypass Control.*/ + kCLOCK_ArmPllPwrBypassCtrl = CCM_ANALOG_TUPLE( + ARM_PLL_CFG0_OFFSET, CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Arm PLL bypass Control.*/ + + kCLOCK_SysPll1InternalPll1BypassCtrl = CCM_ANALOG_TUPLE( + SYS_PLL1_CFG0_OFFSET, + CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM System PLL1 internal pll1 bypass Control.*/ + kCLOCK_SysPll1InternalPll2BypassCtrl = CCM_ANALOG_TUPLE( + SYS_PLL1_CFG0_OFFSET, + CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM System PLL1 internal pll2 bypass Control.*/ + + kCLOCK_SysPll2InternalPll1BypassCtrl = CCM_ANALOG_TUPLE( + SYS_PLL2_CFG0_OFFSET, + CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog System PLL1 internal pll1 bypass Control.*/ + kCLOCK_SysPll2InternalPll2BypassCtrl = CCM_ANALOG_TUPLE( + SYS_PLL2_CFG0_OFFSET, + CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog VIDEO System PLL1 internal pll1 bypass Control.*/ + + kCLOCK_SysPll3InternalPll1BypassCtrl = CCM_ANALOG_TUPLE( + SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog VIDEO PLL bypass Control.*/ + kCLOCK_SysPll3InternalPll2BypassCtrl = CCM_ANALOG_TUPLE( + SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog VIDEO PLL bypass Control.*/ + + kCLOCK_VideoPll2InternalPll1BypassCtrl = + CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET, + CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/ + kCLOCK_VideoPll2InternalPll2BypassCtrl = + CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET, + CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/ + + kCLOCK_DramPllInternalPll1BypassCtrl = CCM_ANALOG_TUPLE( + DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/ + kCLOCK_DramPllInternalPll2BypassCtrl = CCM_ANALOG_TUPLE( + DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/ +} clock_pll_bypass_ctrl_t; + +/*! + * @brief PLL clock names for clock enable/disable settings. + * + * These constants define the PLL clock names for PLL clock enable/disable operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Clock enable bit shift. + */ +typedef enum _ccm_analog_pll_clke +{ + kCLOCK_AudioPll1Clke = + CCM_ANALOG_TUPLE(AUDIO_PLL1_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_SHIFT), /*!< Audio pll1 clke */ + kCLOCK_AudioPll2Clke = + CCM_ANALOG_TUPLE(AUDIO_PLL2_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_SHIFT), /*!< Audio pll2 clke */ + kCLOCK_VideoPll1Clke = + CCM_ANALOG_TUPLE(VIDEO_PLL1_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_SHIFT), /*!< Video pll1 clke */ + kCLOCK_GpuPllClke = + CCM_ANALOG_TUPLE(GPU_PLL_CFG0_OFFSET, CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Gpu pll clke */ + kCLOCK_VpuPllClke = + CCM_ANALOG_TUPLE(VPU_PLL_CFG0_OFFSET, CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Vpu pll clke */ + kCLOCK_ArmPllClke = + CCM_ANALOG_TUPLE(ARM_PLL_CFG0_OFFSET, CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Arm pll clke */ + + kCLOCK_SystemPll1Clke = + CCM_ANALOG_TUPLE(SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_SHIFT), /*!< System pll1 clke */ + kCLOCK_SystemPll1Div2Clke = CCM_ANALOG_TUPLE( + SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_SHIFT), /*!< System pll1 Div2 clke */ + kCLOCK_SystemPll1Div3Clke = CCM_ANALOG_TUPLE( + SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_SHIFT), /*!< System pll1 Div3 clke */ + kCLOCK_SystemPll1Div4Clke = CCM_ANALOG_TUPLE( + SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_SHIFT), /*!< System pll1 Div4 clke */ + kCLOCK_SystemPll1Div5Clke = CCM_ANALOG_TUPLE( + SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_SHIFT), /*!< System pll1 Div5 clke */ + kCLOCK_SystemPll1Div6Clke = CCM_ANALOG_TUPLE( + SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_SHIFT), /*!< System pll1 Div6 clke */ + kCLOCK_SystemPll1Div8Clke = CCM_ANALOG_TUPLE( + SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_SHIFT), /*!< System pll1 Div8 clke */ + kCLOCK_SystemPll1Div10Clke = CCM_ANALOG_TUPLE( + SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_SHIFT), /*!< System pll1 Div10 clke */ + kCLOCK_SystemPll1Div20Clke = CCM_ANALOG_TUPLE( + SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_SHIFT), /*!< System pll1 Div20 clke */ + + kCLOCK_SystemPll2Clke = + CCM_ANALOG_TUPLE(SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_SHIFT), /*!< System pll2 clke */ + kCLOCK_SystemPll2Div2Clke = CCM_ANALOG_TUPLE( + SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_SHIFT), /*!< System pll2 Div2 clke */ + kCLOCK_SystemPll2Div3Clke = CCM_ANALOG_TUPLE( + SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_SHIFT), /*!< System pll2 Div3 clke */ + kCLOCK_SystemPll2Div4Clke = CCM_ANALOG_TUPLE( + SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_SHIFT), /*!< System pll2 Div4 clke */ + kCLOCK_SystemPll2Div5Clke = CCM_ANALOG_TUPLE( + SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_SHIFT), /*!< System pll2 Div5 clke */ + kCLOCK_SystemPll2Div6Clke = CCM_ANALOG_TUPLE( + SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_SHIFT), /*!< System pll2 Div6 clke */ + kCLOCK_SystemPll2Div8Clke = CCM_ANALOG_TUPLE( + SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_SHIFT), /*!< System pll2 Div8 clke */ + kCLOCK_SystemPll2Div10Clke = CCM_ANALOG_TUPLE( + SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_SHIFT), /*!< System pll2 Div10 clke */ + kCLOCK_SystemPll2Div20Clke = CCM_ANALOG_TUPLE( + SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_SHIFT), /*!< System pll2 Div20 clke */ + + kCLOCK_SystemPll3Clke = + CCM_ANALOG_TUPLE(SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_SHIFT), /*!< System pll3 clke */ + kCLOCK_VideoPll2Clke = + CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_SHIFT), /*!< Video pll2 clke */ + kCLOCK_DramPllClke = + CCM_ANALOG_TUPLE(DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Dram pll clke */ + kCLOCK_OSC25MClke = + CCM_ANALOG_TUPLE(OSC_MISC_CFG_OFFSET, CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_SHIFT), /*!< OSC25M clke */ + kCLOCK_OSC27MClke = + CCM_ANALOG_TUPLE(OSC_MISC_CFG_OFFSET, CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_SHIFT), /*!< OSC27M clke */ + +} clock_pll_clke_t; + +/*! + * @brief ANALOG Power down override control. + */ +typedef enum _clock_pll_ctrl +{ + kCLOCK_AudioPll1Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL1_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_SHIFT), + kCLOCK_AudioPll2Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL2_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_SHIFT), + kCLOCK_VideoPll1Ctrl = CCM_ANALOG_TUPLE(VIDEO_PLL1_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_SHIFT), + kCLOCK_GpuPllCtrl = CCM_ANALOG_TUPLE(GPU_PLL_CFG0_OFFSET, CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_SHIFT), + kCLOCK_VpuPllCtrl = CCM_ANALOG_TUPLE(VPU_PLL_CFG0_OFFSET, CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_SHIFT), + kCLOCK_ArmPllCtrl = CCM_ANALOG_TUPLE(ARM_PLL_CFG0_OFFSET, CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_SHIFT), + + kCLOCK_SystemPll1Ctrl = CCM_ANALOG_TUPLE(SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_SHIFT), + kCLOCK_SystemPll2Ctrl = CCM_ANALOG_TUPLE(SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_SHIFT), + kCLOCK_SystemPll3Ctrl = CCM_ANALOG_TUPLE(SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_SHIFT), + kCLOCK_VideoPll2Ctrl = CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_SHIFT), + kCLOCK_DramPllCtrl = CCM_ANALOG_TUPLE(DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_SHIFT), + +} clock_pll_ctrl_t; + +/*! @brief OSC work mode. */ +enum _osc_mode +{ + kOSC_OscMode = 0U, /*!< OSC oscillator mode */ + kOSC_ExtMode = 1U, /*!< OSC external mode */ +}; + +/*! @brief OSC 32K input select. */ +typedef enum _osc32_src +{ + kOSC32_Src25MDiv800 = 0U, /*!< source from 25M divide 800 */ + kOSC32_SrcRTC, /*!< source from RTC */ +} osc32_src_t; + +/*! @brief PLL reference clock select. */ +enum _ccm_analog_pll_ref_clk +{ + kANALOG_PllRefOsc25M = 0U, /*!< reference OSC 25M */ + kANALOG_PllRefOsc27M = 1U, /*!< reference OSC 27M */ + kANALOG_PllRefOscHdmiPhy27M = 2U, /*!< reference HDMI PHY 27M */ + kANALOG_PllRefClkPN = 3U, /*!< reference CLK_P_N */ +}; + +/*! + * @brief OSC configuration structure. + */ +typedef struct _osc_config +{ + uint8_t oscMode; /*!< ext or osc mode */ + uint8_t oscDiv; /*!< osc divider */ +} osc_config_t; + +/*! + * @brief Fractional-N PLL configuration. + * Note: all the dividers in this configuration structure are the actually divider, software will map it to register + * value + */ +typedef struct _ccm_analog_frac_pll_config +{ + uint8_t refSel; /*!< pll reference clock sel */ + + uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */ + + uint32_t fractionDiv; /*!< Inlcude fraction divider(divider:1:2^24) output clock + range is 2000MHZ-4000MHZ */ + uint8_t intDiv; /*and integer divide(divider: 1:32)*/ + uint8_t outDiv; /*!< output clock divide, output clock range is 30MHZ to 2000MHZ, must be a even value */ + +} ccm_analog_frac_pll_config_t; + +/*! + * @brief SSCG PLL configuration. + * Note: all the dividers in this configuration structure are the actually divider, software will map it to register + * value + */ +typedef struct _ccm_analog_sscg_pll_config +{ + uint8_t refSel; /*!< pll reference clock sel */ + + uint8_t refDiv1; /*!< A 3bit divider to make sure the REF must be within the range 25MHZ~235MHZ ,post_divide REF + must be within the range 25MHZ~54MHZ */ + uint8_t refDiv2; /*!< A 6bit divider to make sure the post_divide REF must be within the range 54MHZ~75MHZ */ + + uint32_t loopDivider1; /*!< A 6bit internal PLL1 feedback clock divider, output clock range must be within the range + 1600MHZ-2400MHZ */ + uint32_t loopDivider2; /*!< A 6bit internal PLL2 feedback clock divider, output clock range must be within the range + 1200MHZ-2400MHZ */ + + uint8_t outDiv; /*!< A 6bit output clock divide, output clock range is 20MHZ to 1200MHZ */ + +} ccm_analog_sscg_pll_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name CCM Root Clock Setting + * @{ + */ + +/*! + * @brief Set clock root mux. + * User maybe need to set more than one mux ROOT according to the clock tree + * description in the reference manual. + * + * @param rootClk Root clock control (see @ref clock_root_control_t enumeration). + * @param mux Root mux value (see _ccm_rootmux_xxx enumeration). + */ +static inline void CLOCK_SetRootMux(clock_root_control_t rootClk, uint32_t mux) +{ + CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); +} + +/*! + * @brief Get clock root mux. + * In order to get the clock source of root, user maybe need to get more than one + * ROOT's mux value to obtain the final clock source of root. + * + * @param rootClk Root clock control (see @ref clock_root_control_t enumeration). + * @return Root mux value (see _ccm_rootmux_xxx enumeration). + */ +static inline uint32_t CLOCK_GetRootMux(clock_root_control_t rootClk) +{ + return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; +} + +/*! + * @brief Enable clock root + * + * @param rootClk Root clock control (see @ref clock_root_control_t enumeration) + */ +static inline void CLOCK_EnableRoot(clock_root_control_t rootClk) +{ + CCM_REG_SET(rootClk) = CCM_TARGET_ROOT_SET_ENABLE_MASK; +} + +/*! + * @brief Disable clock root + * + * @param rootClk Root control (see @ref clock_root_control_t enumeration) + */ +static inline void CLOCK_DisableRoot(clock_root_control_t rootClk) +{ + CCM_REG_CLR(rootClk) = CCM_TARGET_ROOT_CLR_ENABLE_MASK; +} + +/*! + * @brief Check whether clock root is enabled + * + * @param rootClk Root control (see @ref clock_root_control_t enumeration) + * @return CCM root enabled or not. + * - true: Clock root is enabled. + * - false: Clock root is disabled. + */ +static inline bool CLOCK_IsRootEnabled(clock_root_control_t rootClk) +{ + return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); +} + +/*! + * @brief Update clock root in one step, for dynamical clock switching + * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value + * + * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration) + * @param mux root mux value (see _ccm_rootmux_xxx enumeration) + * @param pre Pre divider value (0-7, divider=n+1) + * @param post Post divider value (0-63, divider=n+1) + */ +void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post); + +/*! + * @brief Set root clock divider + * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value + * + * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration) + * @param pre Pre divider value (1-8) + * @param post Post divider value (1-64) + */ +void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post); + +/*! + * @brief Get clock root PRE_PODF. + * In order to get the clock source of root, user maybe need to get more than one + * ROOT's mux value to obtain the final clock source of root. + * + * @param rootClk Root clock name (see @ref clock_root_control_t enumeration). + * @return Root Pre divider value. + */ +static inline uint32_t CLOCK_GetRootPreDivider(clock_root_control_t rootClk) +{ + return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; +} + +/*! + * @brief Get clock root POST_PODF. + * In order to get the clock source of root, user maybe need to get more than one + * ROOT's mux value to obtain the final clock source of root. + * + * @param rootClk Root clock name (see @ref clock_root_control_t enumeration). + * @return Root Post divider value. + */ +static inline uint32_t CLOCK_GetRootPostDivider(clock_root_control_t rootClk) +{ + return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + 1U; +} + +/*! + * @name OSC setting + * @{ + */ +/*! + * @brief OSC25M init + * + * @param config osc configuration. + */ +void CLOCK_InitOSC25M(const osc_config_t *config); + +/*! + * @brief OSC25M deinit + * + */ +void CLOCK_DeinitOSC25M(void); + +/*! + * @brief OSC27M init + * @param config osc configuration. + * + */ +void CLOCK_InitOSC27M(const osc_config_t *config); + +/*! + * @brief OSC27M deinit + * + */ +void CLOCK_DeinitOSC27M(void); + +/*! + * @brief switch 32KHZ OSC input + * @param sel OSC32 input clock select + */ +static inline void CLOCK_SwitchOSC32Src(osc32_src_t sel) +{ + CCM_ANALOG->OSC_MISC_CFG = (CCM_ANALOG->OSC_MISC_CFG & (~CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK)) | (uint32_t)sel; +} + +/*! + * @name CCM Gate Control + * @{ + */ + +/*! + * @brief Set PLL or CCGR gate control + * + * @param ccmGate Gate control (see @ref clock_pll_gate_t and @ref clock_ip_name_t enumeration) + * @param control Gate control value (see @ref clock_gate_value_t) + */ +static inline void CLOCK_ControlGate(uint32_t ccmGate, clock_gate_value_t control) +{ + CCM_REG(ccmGate) = (uint32_t)control; +} + +/*! + * @brief Enable CCGR clock gate and root clock gate for each module + * User should set specific gate for each module according to the description + * of the table of system clocks, gating and override in CCM chapter of + * reference manual. Take care of that one module may need to set more than + * one clock gate. + * + * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration). + */ +void CLOCK_EnableClock(clock_ip_name_t ccmGate); + +/*! + * @brief Disable CCGR clock gate for the each module + * User should set specific gate for each module according to the description + * of the table of system clocks, gating and override in CCM chapter of + * reference manual. Take care of that one module may need to set more than + * one clock gate. + * + * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration). + */ +void CLOCK_DisableClock(clock_ip_name_t ccmGate); + +/*! + * @name CCM Analog PLL Operatoin Functions + * @{ + */ + +/*! + * @brief Power up PLL + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration) + */ +static inline void CLOCK_PowerUpPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl) +{ + CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl)); +} + +/*! + * @brief Power down PLL + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration) + */ +static inline void CLOCK_PowerDownPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl) +{ + CCM_ANALOG_TUPLE_REG(base, pllControl) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl); +} + +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see ccm_analog_pll_control_t enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false: Do not bypass the PLL. + */ +static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl, bool bypass) +{ + if (bypass) + { + CCM_ANALOG_TUPLE_REG(base, pllControl) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl); + } + else + { + CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl)); + } +} + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl))); +} + +/*! + * @brief Check if PLL clock is locked + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration) + * @return PLL lock status. + * - true: The PLL clock is locked. + * - false: The PLL clock is not locked. + */ +static inline bool CLOCK_IsPllLocked(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_MASK); +} + +/*! + * @brief Enable PLL clock + * + * @param base CCM_ANALOG base pointer. + * @param pllClock PLL clock name (see ccm_analog_pll_clock_t enumeration) + */ +static inline void CLOCK_EnableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock) +{ + CCM_ANALOG_TUPLE_REG(base, pllClock) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock); +} + +/*! + * @brief Disable PLL clock + * + * @param base CCM_ANALOG base pointer. + * @param pllClock PLL clock name (see ccm_analog_pll_clock_t enumeration) + */ +static inline void CLOCK_DisableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock) +{ + CCM_ANALOG_TUPLE_REG(base, pllClock) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock)); +} + +/*! + * @brief Override PLL clock output enable + * + * @param base CCM_ANALOG base pointer. + * @param ovClock PLL clock name (see @ref clock_pll_clke_t enumeration) + * @param override Override the PLL. + * - true: Override the PLL clke, CCM will handle it. + * - false: Do not override the PLL clke. + */ +static inline void CLOCK_OverrideAnalogClke(CCM_ANALOG_Type *base, clock_pll_clke_t ovClock, bool override) +{ + if (override) + { + CCM_ANALOG_TUPLE_REG(base, ovClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL); + } + else + { + CCM_ANALOG_TUPLE_REG(base, ovClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL)); + } +} + +/*! + * @brief Override PLL power down + * + * @param base CCM_ANALOG base pointer. + * @param pdClock PLL clock name (see @ref clock_pll_ctrl_t enumeration) + * @param override Override the PLL. + * - true: Override the PLL clke, CCM will handle it. + * - false: Do not override the PLL clke. + */ +static inline void CLOCK_OverridePllPd(CCM_ANALOG_Type *base, clock_pll_ctrl_t pdClock, bool override) +{ + if (override) + { + CCM_ANALOG_TUPLE_REG(base, pdClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL); + } + else + { + CCM_ANALOG_TUPLE_REG(base, pdClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL)); + } +} + +/*! + * @brief Initializes the ANALOG ARM PLL. + * + * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration). + * + * @note This function can't detect whether the Arm PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitArmPll(const ccm_analog_frac_pll_config_t *config); + +/*! + * @brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void); + +/*! + * @brief Initializes the ANALOG SYS PLL1. + * + * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration). + * + * @note This function can't detect whether the SYS PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitSysPll1(const ccm_analog_sscg_pll_config_t *config); + +/*! + * @brief De-initialize the System PLL1. + */ +void CLOCK_DeinitSysPll1(void); + +/*! + * @brief Initializes the ANALOG SYS PLL2. + * + * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration). + * + * @note This function can't detect whether the SYS PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitSysPll2(const ccm_analog_sscg_pll_config_t *config); + +/*! + * @brief De-initialize the System PLL2. + */ +void CLOCK_DeinitSysPll2(void); + +/*! + * @brief Initializes the ANALOG SYS PLL3. + * + * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration). + * + * @note This function can't detect whether the SYS PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitSysPll3(const ccm_analog_sscg_pll_config_t *config); + +/*! + * @brief De-initialize the System PLL3. + */ +void CLOCK_DeinitSysPll3(void); + +/*! + * @brief Initializes the ANALOG DDR PLL. + * + * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration). + * + * @note This function can't detect whether the DDR PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitDramPll(const ccm_analog_sscg_pll_config_t *config); + +/*! + * @brief De-initialize the Dram PLL. + */ +void CLOCK_DeinitDramPll(void); + +/*! + * @brief Initializes the ANALOG AUDIO PLL1. + * + * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration). + * + * @note This function can't detect whether the AUDIO PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config); + +/*! + * @brief De-initialize the Audio PLL1. + */ +void CLOCK_DeinitAudioPll1(void); + +/*! + * @brief Initializes the ANALOG AUDIO PLL2. + * + * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration). + * + * @note This function can't detect whether the AUDIO PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config); + +/*! + * @brief De-initialize the Audio PLL2. + */ +void CLOCK_DeinitAudioPll2(void); + +/*! + * @brief Initializes the ANALOG VIDEO PLL1. + * + * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration). + * + */ +void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config); + +/*! + * @brief De-initialize the Video PLL1. + */ +void CLOCK_DeinitVideoPll1(void); + +/*! + * @brief Initializes the ANALOG VIDEO PLL2. + * + * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration). + * + * @note This function can't detect whether the VIDEO PLL has been enabled and + * used by some IPs. + */ +void CLOCK_InitVideoPll2(const ccm_analog_sscg_pll_config_t *config); + +/*! + * @brief De-initialize the Video PLL2. + */ +void CLOCK_DeinitVideoPll2(void); + +/*! + * @brief Initializes the ANALOG SSCG PLL. + * + * @param base CCM ANALOG base address + * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration). + * @param type sscg pll type + * + */ +void CLOCK_InitSSCGPll(CCM_ANALOG_Type *base, const ccm_analog_sscg_pll_config_t *config, clock_pll_ctrl_t type); + +/*! + * @brief Get the ANALOG SSCG PLL clock frequency. + * + * @param base CCM ANALOG base address. + * @param type sscg pll type + * @param refClkFreq reference clock frequency + * @param pll1Bypass pll1 bypass flag + * + * @return Clock frequency + */ +uint32_t CLOCK_GetSSCGPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass); + +/*! + * @brief Initializes the ANALOG Fractional PLL. + * + * @param base CCM ANALOG base address. + * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration). + * @param type fractional pll type. + * + */ +void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type); + +/*! + * @brief Gets the ANALOG Fractional PLL clock frequency. + * + * @param base CCM_ANALOG base pointer. + * @param type fractional pll type. + * @param refClkFreq reference clock frequency + * + * @return Clock frequency + */ +uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq); + +/*! + * @brief Gets PLL clock frequency. + * + * @param pll fractional pll type. + + * @return Clock frequency + */ +uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll); + +/*! + * @brief Gets PLL reference clock frequency. + * + * @param ctrl fractional pll type. + + * @return Clock frequency + */ +uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl); + +/*! + * @name CCM Get frequency + * @{ + */ + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! + * @brief Get the CCM Cortex M4 core frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +uint32_t CLOCK_GetCoreM4Freq(void); + +/*! + * @brief Get the CCM Axi bus frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +uint32_t CLOCK_GetAxiFreq(void); + +/*! + * @brief Get the CCM Ahb bus frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +uint32_t CLOCK_GetAhbFreq(void); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/* @} */ +#endif diff --git a/devices/MIMX8MQ6/drivers/fsl_common.c b/devices/MIMX8MQ6/drivers/fsl_common.c new file mode 100644 index 000000000..8b17fc366 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_common.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize; + + /* Check overflow. */ + alignedsize = SDK_SIZEALIGN(size, alignbytes); + if (alignedsize < size) + { + return NULL; + } + + if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) + { + return NULL; + } + + alignedsize += alignbytes + sizeof(mem_align_cb_t); + + union + { + void *pointer_value; + uint32_t unsigned_value; + } p_align_addr, p_addr; + + p_addr.pointer_value = malloc(alignedsize); + + if (p_addr.pointer_value == NULL) + { + return NULL; + } + + p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); + + return p_align_addr.pointer_value; +} + +void SDK_Free(void *ptr) +{ + union + { + void *pointer_value; + uint32_t unsigned_value; + } p_free; + p_free.pointer_value = ptr; + mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; + + free(p_free.pointer_value); +} diff --git a/devices/MIMX8MQ6/drivers/fsl_common.h b/devices/MIMX8MQ6/drivers/fsl_common.h new file mode 100644 index 000000000..cc4f04ca3 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_common.h @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Macro to use the default weak IRQ handler in drivers. */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ + kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ + kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ + kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ + kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ + kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ + kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ + kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ + kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ + kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ + kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ + kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */ +}; + +/*! \public + * @brief Generic status return codes. + */ +enum +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ + kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/*! + * @name Min/max macros + * @{ + */ +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Suppress fallthrough warning macro */ +/* For switch case code block, if case section ends without "break;" statement, there wil be + fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + case section which misses "break;"statement. + */ +/* @{ */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__ ((fallthrough)) +#else +#define SUPPRESS_FALL_THROUGH_WARNING() +#endif +/* @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ +void *SDK_Malloc(size_t size, size_t alignbytes); + +/*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ +void SDK_Free(void *ptr); + +/*! +* @brief Delay at least for some time. +* Please note that, this API uses while loop for delay, different run-time environments make the time not precise, +* if precise delay count was needed, please implement a new delay function with hardware timer. +* +* @param delayTime_us Delay time in unit of microsecond. +* @param coreClock_Hz Core clock frequency with Hz. +*/ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#if (defined(__DSC__) && defined(__CW__)) +#include "fsl_common_dsc.h" +#elif defined(__XCC__) +#include "fsl_common_dsp.h" +#else +#include "fsl_common_arm.h" +#endif + +#endif /* _FSL_COMMON_H_ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_common_arm.c b/devices/MIMX8MQ6/drivers/fsl_common_arm.c new file mode 100644 index 000000000..e77a265ce --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_common_arm.c @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_arm" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +#ifdef __VECTOR_TABLE +#undef __VECTOR_TABLE +#endif + +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[(int32_t)irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) + +/* + * When the SYSCON STARTER registers are discontinuous, these functions are + * implemented in fsl_power.c. + */ +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1UL << intNumber; + (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1UL << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) +/* Use WDT. */ +static void enableCpuCycleCounter(void) +{ + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } +} + +static uint32_t getCpuCycleCount(void) +{ + return DWT->CYCCNT; +} +#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ +/* Use software loop. */ +#if defined(__CC_ARM) /* This macro is arm v5 specific */ +/* clang-format off */ +__ASM static void DelayLoop(uint32_t count) +{ +loop + SUBS R0, R0, #1 + CMP R0, #0 + BNE loop + BX LR +} +/* clang-format on */ +#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) +/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, + * use SUB and CMP here for compatibility */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV R0, %0" : : "r"(count)); + __ASM volatile( + "loop: \n" +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + " SUB R0, R0, #1 \n" +#else + " SUBS R0, R0, #1 \n" +#endif + " CMP R0, #0 \n" + + " BNE loop \n" + : + : + : "r0"); +} +#endif /* defined(__CC_ARM) */ +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + +/*! + * @brief Delay at least for some time. + * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have + * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and + * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports + * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + uint64_t count; + + if (delayTime_us > 0U) + { + count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + + assert(count <= UINT32_MAX); + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ + + enableCpuCycleCounter(); + /* Calculate the count ticks. */ + count += getCpuCycleCount(); + + if (count > UINT32_MAX) + { + count -= UINT32_MAX; + /* Wait for cyccnt overflow. */ + while (count < getCpuCycleCount()) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > getCpuCycleCount()) + { + } +#else + /* Divide value may be different in various environment to ensure delay is precise. + * Every loop count includes three instructions, due to Cortex-M7 sometimes executes + * two instructions in one period, through test here set divide 1.5. Other M cores use + * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does + * not matter because other instructions outside while loop is enough to fill the time. + */ +#if (__CORTEX_M == 7) + count = count / 3U * 2U; +#else + count = count / 4U; +#endif + DelayLoop((uint32_t)count); +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + } +} diff --git a/devices/MIMX8MQ6/drivers/fsl_common_arm.h b/devices/MIMX8MQ6/drivers/fsl_common_arm.h new file mode 100644 index 000000000..8b28aa888 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_common_arm.h @@ -0,0 +1,660 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_ARM_H_ +#define _FSL_COMMON_ARM_H_ + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @name Atomic modification + * + * These macros are used for atomic access, such as read-modify-write + * to the peripheral registers. + * + * - SDK_ATOMIC_LOCAL_ADD + * - SDK_ATOMIC_LOCAL_SET + * - SDK_ATOMIC_LOCAL_CLEAR + * - SDK_ATOMIC_LOCAL_TOGGLE + * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET + * + * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr + * means the address of the peripheral register or variable you want to modify + * atomically, the parameter @c clearBits is the bits to clear, the parameter + * @c setBits it the bits to set. + * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: + * + * @code + volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; + + SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); + @endcode + * + * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, + * register bit1:bit0 = 0b10. + * + * @note For the platforms don't support exclusive load and store, these macros + * disable the global interrupt to pretect the modification. + * + * @note These macros only guarantee the local processor atomic operations. For + * the multi-processor devices, use hardware semaphore such as SEMA42 to + * guarantee exclusive access if necessary. + * + * @{ + */ + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ + +/* If the LDREX and STREX are supported, use them. */ +#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXB(addr); \ + (ops); \ + } while (0UL != __STREXB((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXH(addr); \ + (ops); \ + } while (0UL != __STREXH((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXW(addr); \ + (ops); \ + } while (0UL != __STREXW((val), (addr))) + +static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd1Byte((volatile uint8_t*)(volatile void*)(addr), (val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t*)(volatile void*)(addr), (val)) : \ + _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void*)(addr), (val)))) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \ + _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void*)(addr), (bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \ + _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void*)(addr), (bits)))) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \ + _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void*)(addr), (bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t*)(volatile void*)(addr), (clearBits), (setBits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t*)(volatile void*)(addr), (clearBits), (setBits)) : \ + _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void*)(addr), (clearBits), (setBits)))) +#else + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) += (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) |= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) &= ~(bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) ^= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000U / (clockFreqInHz)) +/* @} */ + +/*! @name ISR exit barrier + * @{ + * + * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + * exception return operation might vector to incorrect interrupt. + * For Cortex-M7, if core speed much faster than peripheral register write speed, + * the peripheral interrupt flags may be still set after exiting ISR, this results to + * the same error similar with errata 83869. + */ +#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) +#define SDK_ISR_EXIT_BARRIER __DSB() +#else +#define SDK_ISR_EXIT_BARRIER +#endif + +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/* + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) +_Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported +#endif + +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/* @{ */ + +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) + +#if (defined(__ICCARM__)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" + +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if(defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif + +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif + +#else + +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) + +#endif + +/* @} */ + +/*! + * @name Time sensitive region + * @{ + */ +#if (defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) + +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ + +#else /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ + +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func + +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif(defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ + +#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) +void DefaultISR(void); +#endif + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif +} + +/*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif +} + +#if defined(ENABLE_RAM_VECTOR_TABLE) +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) +/*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void EnableDeepSleepIRQ(IRQn_Type interrupt); + +/*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @} */ + +#endif /* _FSL_COMMON_ARM_H_ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_ecspi.c b/devices/MIMX8MQ6/drivers/fsl_ecspi.c new file mode 100644 index 000000000..2a8f2b9ac --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_ecspi.c @@ -0,0 +1,1001 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ecspi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ecspi" +#endif + +/*! @brief ECSPI transfer state, which is used for ECSPI transactiaonl APIs' internal state. */ +enum +{ + kECSPI_Idle = 0x0, /*!< ECSPI is idle state */ + kECSPI_Busy /*!< ECSPI is busy tranferring data. */ +}; + +/*! @brief Typedef for ecspi master interrupt handler. ecspi master and slave handle is the same. */ +typedef void (*ecspi_isr_t)(ECSPI_Type *base, ecspi_master_handle_t *ecspiHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Sends a buffer of data bytes in non-blocking way. + * + * @param base ECSPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to send + */ +static void ECSPI_WriteNonBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Receive a buffer of data bytes in non-blocking way. + * + * @param base ECSPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to send + */ +static void ECSPI_ReadNonBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Send a piece of data for ECSPI. + * + * This function computes the number of data to be written into D register or Tx FIFO, + * and write the data into it. At the same time, this function updates the values in + * master handle structure. + * + * @param base ECSPI base pointer + * @param handle Pointer to ECSPI master handle structure. + */ +static void ECSPI_SendTransfer(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/*! + * @brief Receive a piece of data for ECSPI master. + * + * This function computes the number of data to receive from D register or Rx FIFO, + * and write the data to destination address. At the same time, this function updates + * the values in master handle structure. + * + * @param base ECSPI base pointer + * @param handle Pointer to ECSPI master handle structure. + */ +static void ECSPI_ReceiveTransfer(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/*! + * @brief Sets the ECSPI channel configuration structure to default values. + * + * This function is to get the channel configuration structure initialized for use in ECSPI_SetChannelConfig(). + * User may use the initialized structure unchanged in ECSPI_SetChannelConfig(), or modify + * some fields of the structure before calling ECSPI_SetChannelConfig(). + * + * @param config pointer to config structure + */ +static void ECSPI_GetDefaultChannelConfig(ecspi_channel_config_t *config); + +/*! + * @brief Common IRQ handler for SPI. + * + * @param base SPI base pointer. + * @param instance SPI instance number. + */ +static void ECSPI_CommonIRQHandler(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Base pointer array */ +static ECSPI_Type *const s_ecspiBases[] = ECSPI_BASE_PTRS; +/*! @brief ECSPI internal handle pointer array */ +static ecspi_master_handle_t *s_ecspiHandle[ARRAY_SIZE(s_ecspiBases)]; +/*! @brief IRQ name array */ +static const IRQn_Type s_ecspiIRQ[] = ECSPI_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Clock array name */ +static const clock_ip_name_t s_ecspiClock[] = ECSPI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointer to master IRQ handler for each instance. */ +static ecspi_isr_t s_ecspiMasterIsr; +/*! @brief Pointer to slave IRQ handler for each instance. */ +static ecspi_isr_t s_ecspiSlaveIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Get the instance for ECSPI module. + * + * param base ECSPI base address + */ +uint32_t ECSPI_GetInstance(ECSPI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_ecspiBases); instance++) + { + if (s_ecspiBases[instance] == base) + { + break; + } + } + assert(instance <= ARRAY_SIZE(s_ecspiBases)); + return instance; +} + +static void ECSPI_WriteNonBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size) +{ + size_t i = 0U; + + for (i = 0U; i < size; i++) + { + if (buffer != NULL) + { + base->TXDATA = *buffer++; + } + else + { + ECSPI_WriteData(base, ECSPI_DUMMYDATA); + } + } +} + +static void ECSPI_ReadNonBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size) +{ + if (NULL != buffer) + { + while ((size--) != 0UL) + { + *buffer++ = ECSPI_ReadData(base); + } + } + else + { + while ((size--) != 0UL) + { + (void)ECSPI_ReadData(base); + } + } +} + +static void ECSPI_SendTransfer(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + assert(base != NULL); + assert(handle != NULL); + + uint32_t dataCounts = 0U; + uint32_t txRemainingBytes = (uint32_t)(handle->txRemainingBytes); + /* Caculate the data size to send */ + dataCounts = + ((uint32_t)FSL_FEATURE_ECSPI_TX_FIFO_SIZEn(base) - (uint32_t)ECSPI_GetTxFifoCount(base)) < txRemainingBytes ? + ((uint32_t)FSL_FEATURE_ECSPI_TX_FIFO_SIZEn(base) - (uint32_t)ECSPI_GetTxFifoCount(base)) : + txRemainingBytes; + while ((dataCounts--) != 0UL) + { + ECSPI_WriteNonBlocking(base, handle->txData, 1); + if (NULL != handle->txData) + { + handle->txData += 1U; + } + handle->txRemainingBytes -= 1U; + } +} + +static void ECSPI_ReceiveTransfer(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + assert(base != NULL); + + uint32_t dataCounts = 0U; + /* Caculate the data size need to receive */ + dataCounts = + (ECSPI_GetRxFifoCount(base) < handle->rxRemainingBytes) ? ECSPI_GetRxFifoCount(base) : handle->rxRemainingBytes; + + ECSPI_ReadNonBlocking(base, handle->rxData, dataCounts); + if (NULL != handle->rxData) + { + handle->rxData += dataCounts; + } + handle->rxRemainingBytes -= dataCounts; +} +static void ECSPI_GetDefaultChannelConfig(ecspi_channel_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->channelMode = kECSPI_Slave; /*!< ECSPI peripheral operates in slave mode.*/ + config->clockInactiveState = kECSPI_ClockInactiveStateLow; /*!< Clock line (SCLK) inactive state */ + config->dataLineInactiveState = kECSPI_DataLineInactiveStateLow; /*!< Data line (MOSI&MISO) inactive state */ + config->chipSlectActiveState = kECSPI_ChipSelectActiveStateLow; /*!< Chip select(SS) line active state */ + config->polarity = kECSPI_PolarityActiveHigh; /*!< Clock polarity */ + config->phase = kECSPI_ClockPhaseFirstEdge; /*!< clock phase */ +} + +/*! + * brief Sets the ECSPI configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in ECSPI_MasterInit(). + * User may use the initialized structure unchanged in ECSPI_MasterInit, or modify + * some fields of the structure before calling ECSPI_MasterInit. After calling this API, + * the master is ready to transfer. + * Example: + code + ecspi_master_config_t config; + ECSPI_MasterGetDefaultConfig(&config); + endcode + * + * param config pointer to config structure + */ +void ECSPI_MasterGetDefaultConfig(ecspi_master_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->channel = kECSPI_Channel0; + config->burstLength = 8; + config->samplePeriodClock = kECSPI_spiClock; + config->baudRate_Bps = 500000; + config->chipSelectDelay = 0; + config->samplePeriod = 0; + config->txFifoThreshold = 1; + config->rxFifoThreshold = 0; + /* Default configuration of channel */ + ECSPI_GetDefaultChannelConfig(&config->channelConfig); + /*!< ECSPI peripheral operates in slave mode.*/ + config->channelConfig.channelMode = kECSPI_Master; + config->enableLoopback = false; +} + +/*! + * brief Initializes the ECSPI with configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by ECSPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + code + ecspi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + ECSPI_MasterInit(ECSPI0, &config); + endcode + * + * param base ECSPI base pointer + * param config pointer to master configuration structure + * param srcClock_Hz Source clock frequency. + */ +void ECSPI_MasterInit(ECSPI_Type *base, const ecspi_master_config_t *config, uint32_t srcClock_Hz) +{ + assert((config != NULL) && (srcClock_Hz != 0U)); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Open clock gate for SPI and open interrupt */ + CLOCK_EnableClock(s_ecspiClock[ECSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Reset control register to default value */ + ECSPI_SoftwareReset(base); + /* Config CONREG register */ + base->CONREG = + ECSPI_CONREG_BURST_LENGTH((uint32_t)config->burstLength - 1UL) | ECSPI_CONREG_SMC(1U) | ECSPI_CONREG_EN(1U); + /* Config CONFIGREG register */ + ECSPI_SetChannelConfig(base, config->channel, &config->channelConfig); + /* Config DMAREG register */ + base->DMAREG |= + ECSPI_DMAREG_TX_THRESHOLD(config->txFifoThreshold) | ECSPI_DMAREG_RX_THRESHOLD(config->rxFifoThreshold); + /* Config PERIODREG register */ + base->PERIODREG |= ECSPI_PERIODREG_CSRC(config->samplePeriodClock) | + ECSPI_PERIODREG_SAMPLE_PERIOD(config->samplePeriod) | + ECSPI_PERIODREG_CSD_CTL(config->chipSelectDelay); + /* Config TESTING register if enable the loopback function. */ + base->TESTREG |= ECSPI_TESTREG_LBC(config->enableLoopback); + /* Set baud rate */ + ECSPI_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); +} + +/*! + * brief Sets the ECSPI configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in ECSPI_SlaveInit(). + * User may use the initialized structure unchanged in ECSPI_SlaveInit(), or modify + * some fields of the structure before calling ECSPI_SlaveInit(). After calling this API, + * the master is ready to transfer. + * Example: + code + ecspi_Slaveconfig_t config; + ECSPI_SlaveGetDefaultConfig(&config); + endcode + * + * param config pointer to config structure + */ +void ECSPI_SlaveGetDefaultConfig(ecspi_slave_config_t *config) +{ + /* Default configuration of channel nember */ + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + config->channel = kECSPI_Channel0; + + config->burstLength = 8; + config->txFifoThreshold = 1; + config->rxFifoThreshold = 0; + /* Set default channel configuration */ + ECSPI_GetDefaultChannelConfig(&config->channelConfig); + /* ECSPI peripheral operates in slave mode.*/ + config->channelConfig.channelMode = kECSPI_Slave; +} + +/*! + * brief Initializes the ECSPI with configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by ECSPI_SlaveGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + code + ecspi_Salveconfig_t config = { + .baudRate_Bps = 400000, + ... + }; + ECSPI_SlaveInit(ECSPI1, &config); + endcode + * + * param base ECSPI base pointer + * param config pointer to master configuration structure + */ +void ECSPI_SlaveInit(ECSPI_Type *base, const ecspi_slave_config_t *config) +{ + assert((base != NULL) && (config != NULL)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Open clock gate for SPI and open interrupt */ + CLOCK_EnableClock(s_ecspiClock[ECSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset control register to default value */ + ECSPI_SoftwareReset(base); + /* Config CONREG register */ + base->CONREG = ECSPI_CONREG_BURST_LENGTH(config->burstLength - 1UL) | ECSPI_CONREG_EN(1UL); + /* Config DMAREG register */ + base->DMAREG |= + ECSPI_DMAREG_TX_THRESHOLD(config->txFifoThreshold) | ECSPI_DMAREG_RX_THRESHOLD(config->rxFifoThreshold); + /* Setup channel configuration */ + ECSPI_SetChannelConfig(base, config->channel, &config->channelConfig); +} + +/*! + * brief De-initializes the ECSPI. + * + * Calling this API resets the ECSPI module, gates the ECSPI clock. + * The ECSPI module can't work unless calling the ECSPI_MasterInit/ECSPI_SlaveInit to initialize module. + * + * param base ECSPI base pointer + */ +void ECSPI_Deinit(ECSPI_Type *base) +{ + /* Disable ECSPI module before shutting down */ + base->CONREG &= ~ECSPI_CONREG_EN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the clock */ + CLOCK_DisableClock(s_ecspiClock[ECSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Sets the baud rate for ECSPI transfer. This is only used in master. + * + * param base ECSPI base pointer + * param baudRate_Bps baud rate needed in Hz. + * param srcClock_Hz ECSPI source clock frequency in Hz. + */ +void ECSPI_SetBaudRate(ECSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + assert(base != NULL); + + uint8_t bestPreDividerValue = 0U, preDividerValue = 0U; + uint8_t bestPostDividerValue = 0U, postDividerValue = 0U; + uint32_t realBaudrate = 0U; + uint32_t diff = 0xFFFFFFFFU; + uint32_t min_diff = 0xFFFFFFFFU; + + for (preDividerValue = 0U; preDividerValue < 16U; preDividerValue++) + { + if (diff == 0U) + { + break; + } + + for (postDividerValue = 0U; postDividerValue < 16U; postDividerValue++) + { + if (diff == 0U) + { + break; + } + + realBaudrate = (srcClock_Hz / (preDividerValue + 1UL)) >> postDividerValue; + if (realBaudrate > baudRate_Bps) + { + diff = realBaudrate - baudRate_Bps; + if (diff < min_diff) + { + min_diff = diff; + bestPreDividerValue = preDividerValue; + bestPostDividerValue = postDividerValue; + } + } + else + { + diff = baudRate_Bps - realBaudrate; + if (diff < min_diff) + { + min_diff = diff; + bestPreDividerValue = preDividerValue; + bestPostDividerValue = postDividerValue; + } + } + } + } + + base->CONREG |= ECSPI_CONREG_PRE_DIVIDER(bestPreDividerValue) | ECSPI_CONREG_POST_DIVIDER(bestPostDividerValue); +} + +/*! + * brief Set channel select configuration for transfer. + * + * The purpose of this API is to set the channel will be use to transfer. + * User may use this API after instance has been initialized or before transfer start. + * The configuration structure #_ecspi_channel_config_ can be filled by user from scratch. + * After calling this API, user can select this channel as transfer channel. + * + * param base ECSPI base pointer + * param channel Channel source. + * param config Configuration struct of channel + */ +void ECSPI_SetChannelConfig(ECSPI_Type *base, ecspi_channel_source_t channel, const ecspi_channel_config_t *config) +{ + switch (channel) + { + case kECSPI_Channel0: + base->CONREG |= ECSPI_CONREG_CHANNEL_MODE(config->channelMode); + base->CONFIGREG |= (ECSPI_CONFIGREG_SCLK_CTL(config->clockInactiveState) | + ECSPI_CONFIGREG_DATA_CTL(config->dataLineInactiveState) | + ECSPI_CONFIGREG_SS_POL(config->chipSlectActiveState) | + ECSPI_CONFIGREG_SCLK_POL(config->polarity) | ECSPI_CONFIGREG_SCLK_PHA(config->phase)); + break; + + case kECSPI_Channel1: + base->CONREG |= ECSPI_CONREG_CHANNEL_MODE(config->channelMode) << 1U; + base->CONFIGREG |= + ((ECSPI_CONFIGREG_SCLK_CTL(config->clockInactiveState) << 1U) | + (ECSPI_CONFIGREG_DATA_CTL(config->dataLineInactiveState) << 1U) | + (ECSPI_CONFIGREG_SS_POL(config->chipSlectActiveState) << 1U) | + (ECSPI_CONFIGREG_SCLK_POL(config->polarity) << 1U) | (ECSPI_CONFIGREG_SCLK_PHA(config->phase) << 1U)); + break; + + case kECSPI_Channel2: + base->CONREG |= ECSPI_CONREG_CHANNEL_MODE(config->channelMode) << 2; + base->CONFIGREG |= + ((ECSPI_CONFIGREG_SCLK_CTL(config->clockInactiveState) << 2) | + (ECSPI_CONFIGREG_DATA_CTL(config->dataLineInactiveState) << 2) | + (ECSPI_CONFIGREG_SS_POL(config->chipSlectActiveState) << 2) | + (ECSPI_CONFIGREG_SCLK_POL(config->polarity) << 2) | (ECSPI_CONFIGREG_SCLK_PHA(config->phase) << 2)); + break; + + case kECSPI_Channel3: + base->CONREG |= ECSPI_CONREG_CHANNEL_MODE(config->channelMode) << 3; + base->CONFIGREG |= + ((ECSPI_CONFIGREG_SCLK_CTL(config->clockInactiveState) << 3) | + (ECSPI_CONFIGREG_DATA_CTL(config->dataLineInactiveState) << 3) | + (ECSPI_CONFIGREG_SS_POL(config->chipSlectActiveState) << 3) | + (ECSPI_CONFIGREG_SCLK_POL(config->polarity) << 3) | (ECSPI_CONFIGREG_SCLK_PHA(config->phase) << 3)); + break; + + default: + assert(false); + break; + } +} + +/*! + * brief Sends a buffer of data bytes using a blocking method. + * + * note This function blocks via polling until all bytes have been sent. + * + * param base ECSPI base pointer + * param buffer The data bytes to send + * param size The number of data bytes to send + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_ECSPI_Timeout The transfer timed out and was aborted. + */ +status_t ECSPI_WriteBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size) +{ + size_t i = 0U; +#if SPI_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (i < size) + { + /* Wait for TX fifo buffer empty */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while (((base->STATREG & ECSPI_STATREG_TE_MASK) == 0UL) && (--waitTimes != 0U)) +#else + while ((base->STATREG & ECSPI_STATREG_TE_MASK) == 0UL) +#endif + { + } + +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_ECSPI_Timeout; + } +#endif + + /* Write data to tx register */ + if (NULL != buffer) + { + ECSPI_WriteData(base, *buffer++); + } + else + { + ECSPI_WriteData(base, ECSPI_DUMMYDATA); + } + i++; + } + return kStatus_Success; +} + +static status_t ECSPI_ReadBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size) +{ + assert(base != NULL); + + uint32_t state = 0U; + size_t i = 0U; +#if SPI_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (i < size) + { + /* Wait for RX FIFO buffer ready */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while (((base->STATREG & ECSPI_STATREG_RR_MASK) == 0UL) && (--waitTimes != 0U)) +#else + while ((base->STATREG & ECSPI_STATREG_RR_MASK) == 0UL) +#endif + { + /* Get status flags of ECSPI */ + state = ECSPI_GetStatusFlags(base); + /* If hardware overflow happen */ + if ((ECSPI_STATREG_RO_MASK & state) != 0UL) + { + /* Clear overflow flag for next transfer */ + ECSPI_ClearStatusFlags(base, kECSPI_RxFifoOverFlowFlag); + return kStatus_ECSPI_HardwareOverFlow; + } + } + +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_ECSPI_Timeout; + } +#endif + + /* Read data from rx register */ + if (NULL != buffer) + { + *buffer++ = ECSPI_ReadData(base); + } + else + { + (void)ECSPI_ReadData(base); + } + i++; + } + return kStatus_Success; +} + +/*! + * brief Initializes the ECSPI master handle. + * + * This function initializes the ECSPI master handle which can be used for other ECSPI master transactional APIs. + * Usually, + * for a specified ECSPI instance, call this API once to get the initialized handle. + * + * param base ECSPI peripheral base address. + * param handle ECSPI handle pointer. + * param callback Callback function. + * param userData User data. + */ +void ECSPI_MasterTransferCreateHandle(ECSPI_Type *base, + ecspi_master_handle_t *handle, + ecspi_master_callback_t callback, + void *userData) +{ + assert(base != NULL); + assert(handle != NULL); + + uint32_t instance = ECSPI_GetInstance(base); + + /* Initialize the handle */ + s_ecspiHandle[instance] = handle; + handle->callback = callback; + handle->userData = userData; + s_ecspiMasterIsr = ECSPI_MasterTransferHandleIRQ; + + /* Enable ECSPI NVIC */ + (void)EnableIRQ(s_ecspiIRQ[instance]); +} + +/*! + * brief Transfers a block of data using a polling method. + * + * param base SPI base pointer + * param xfer pointer to spi_xfer_config_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_ECSPI_Timeout The transfer timed out and was aborted. + */ +status_t ECSPI_MasterTransferBlocking(ECSPI_Type *base, ecspi_transfer_t *xfer) +{ + assert((base != NULL) && (xfer != NULL)); + + status_t state; + uint32_t burstLength = 0U; + uint32_t dataCounts = 0U; + /* Check if the argument is legal */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + /* Select ECSPI channel to current channel + * Note: + * xfer.channel must be configured before transfer, because every channel has + * it's own configuration,if don't configure this parameter, transfer channel + * will use the default channel0. + */ + ECSPI_SetChannelSelect(base, xfer->channel); + /* Caculate the data size need to be send for one burst */ + burstLength = ((base->CONREG & ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT) + 1UL; + dataCounts = ((burstLength % 32UL) != 0UL) ? (burstLength / 32UL + 1UL) : (burstLength / 32UL); + + while (xfer->dataSize > 0UL) + { + /* ECSPI will transmit and receive at the same time, if txData is NULL, + * instance will transmit dummy data, the dummy data can be set by user. + * if rxData is NULL, data will be read from RX FIFO buffer, but the + * data will be ignored by driver. + * Note that, txData and rxData can not be both NULL. + */ + state = ECSPI_WriteBlocking(base, xfer->txData, dataCounts); + if (kStatus_Success != state) + { + return state; + } + if (NULL != xfer->txData) + { + xfer->txData += dataCounts; + } + state = ECSPI_ReadBlocking(base, xfer->rxData, dataCounts); + if (kStatus_Success != state) + { + return state; + } + if (NULL != xfer->rxData) + { + xfer->rxData += dataCounts; + } + + xfer->dataSize -= dataCounts; + } + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking ECSPI interrupt transfer. + * + * note The API immediately returns after transfer initialization is finished. + * note If ECSPI transfer data frame size is 16 bits, the transfer size cannot be an odd number. + * + * param base ECSPI peripheral base address. + * param handle pointer to ecspi_master_handle_t structure which stores the transfer state + * param xfer pointer to ecspi_transfer_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_ECSPI_Busy ECSPI is not idle, is running another transfer. + */ +status_t ECSPI_MasterTransferNonBlocking(ECSPI_Type *base, ecspi_master_handle_t *handle, ecspi_transfer_t *xfer) +{ + assert((base != NULL) && (handle != NULL) && (xfer != NULL)); + + /* Check if ECSPI is busy */ + if (handle->state == (uint32_t)kECSPI_Busy) + { + return kStatus_ECSPI_Busy; + } + + /* Check if the input arguments valid */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* Set the handle information */ + handle->channel = xfer->channel; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->transferSize = xfer->dataSize; + handle->txRemainingBytes = xfer->dataSize; + handle->rxRemainingBytes = xfer->dataSize; + + /* Set the ECSPI state to busy */ + handle->state = kECSPI_Busy; + + /* Select ECSPI channel to current channel + * Note: + * xfer.channel must be configured before transferfer, because every channel has + * it's own configuration, if don't configure this parameter, transfer channel + * will use the default channel0. + */ + ECSPI_SetChannelSelect(base, xfer->channel); + + /* First send data to Tx FIFO to start a ECSPI transfer */ + ECSPI_SendTransfer(base, handle); + + if (NULL != xfer->rxData) + { + /* Enable Rx data request interrupt and receive overflow interrupt, when data in RX FIFO buffer is greater + * than the RX_THRESHOLD, then a interrupt occurred. Only enable Rx interrupt, + * use rx interrupt to driver ECSPI transfer. + */ + ECSPI_EnableInterrupts( + base, (uint32_t)kECSPI_RxFifoReadyInterruptEnable | (uint32_t)kECSPI_RxFifoOverFlowInterruptEnable); + } + else + { + /* Enable Tx data request interrupt, when data in TX FIFO buffer is greater + * than the TX_THRESHOLD, then a interrupt occurred. + */ + ECSPI_EnableInterrupts(base, kECSPI_TxFifoDataRequstInterruptEnable); + } + + return kStatus_Success; +} + +/*! + * brief Gets the bytes of the ECSPI interrupt transferred. + * + * param base ECSPI peripheral base address. + * param handle Pointer to ECSPI transfer handle, this should be a static variable. + * param count Transferred bytes of ECSPI master. + * retval kStatus_ECSPI_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t ECSPI_MasterTransferGetCount(ECSPI_Type *base, ecspi_master_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + status_t status = kStatus_Success; + + if (handle->state != (uint32_t)kStatus_ECSPI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + /* Return remaing bytes in different cases */ + if (handle->rxData != NULL) + { + *count = handle->transferSize - handle->rxRemainingBytes; + } + else + { + *count = handle->transferSize - handle->txRemainingBytes; + } + } + + return status; +} + +/*! + * brief Aborts an ECSPI transfer using interrupt. + * + * param base ECSPI peripheral base address. + * param handle Pointer to ECSPI transfer handle, this should be a static variable. + */ +void ECSPI_MasterTransferAbort(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + assert(handle != NULL); + + /* Stop interrupts */ + if (NULL != handle->rxData) + { + ECSPI_DisableInterrupts( + base, (uint32_t)kECSPI_RxFifoReadyInterruptEnable | (uint32_t)kECSPI_RxFifoOverFlowInterruptEnable); + } + else + { + ECSPI_DisableInterrupts(base, kECSPI_TxFifoDataRequstInterruptEnable); + } + /* Transfer finished, set the state to Done*/ + handle->state = kECSPI_Idle; + + /* Clear the internal state */ + handle->rxRemainingBytes = 0; + handle->txRemainingBytes = 0; +} + +/*! + * brief Interrupts the handler for the ECSPI. + * + * param base ECSPI peripheral base address. + * param handle pointer to ecspi_master_handle_t structure which stores the transfer state. + */ +void ECSPI_MasterTransferHandleIRQ(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + assert(handle != NULL); + + /* If hardware overflow happens */ + if ((base->STATREG & ECSPI_STATREG_RO_MASK) != 0UL) + { + /* Clear overflow flag for next transfer */ + ECSPI_ClearStatusFlags(base, kECSPI_RxFifoOverFlowFlag); + if ((handle->callback) != NULL) + { + (handle->callback)(base, handle, kStatus_ECSPI_HardwareOverFlow, handle->userData); + } + } + /* If need to receive data, do a receive */ + if ((handle->rxRemainingBytes) != 0UL) + { + ECSPI_ReceiveTransfer(base, handle); + } + + /* We always need to send a data to make the ECSPI run */ + if ((handle->txRemainingBytes) != 0UL) + { + ECSPI_SendTransfer(base, handle); + } + + /* All the transfer finished */ + if ((handle->txRemainingBytes == 0UL) && (handle->rxRemainingBytes == 0UL)) + { + /* Complete the transfer */ + ECSPI_MasterTransferAbort(base, handle); + + if ((handle->callback) != NULL) + { + (handle->callback)(base, handle, kStatus_Success, handle->userData); + } + } +} + +/*! + * brief Initializes the ECSPI slave handle. + * + * This function initializes the ECSPI slave handle which can be used for other ECSPI slave transactional APIs. Usually, + * for a specified ECSPI instance, call this API once to get the initialized handle. + * + * param base ECSPI peripheral base address. + * param handle ECSPI handle pointer. + * param callback Callback function. + * param userData User data. + */ +void ECSPI_SlaveTransferCreateHandle(ECSPI_Type *base, + ecspi_slave_handle_t *handle, + ecspi_slave_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + /* Slave create handle share same logic with master create handle, the only difference + is the Isr pointer. */ + ECSPI_MasterTransferCreateHandle(base, handle, callback, userData); + s_ecspiSlaveIsr = ECSPI_SlaveTransferHandleIRQ; +} + +/*! + * brief Interrupts a handler for the ECSPI slave. + * + * param base ECSPI peripheral base address. + * param handle pointer to ecspi_slave_handle_t structure which stores the transfer state + */ +void ECSPI_SlaveTransferHandleIRQ(ECSPI_Type *base, ecspi_slave_handle_t *handle) +{ + assert(handle != NULL); + /* If hardware overflow happens */ + if ((base->STATREG & ECSPI_STATREG_RO_MASK) != 0UL) + { + /* Clear overflow flag for next transfer */ + ECSPI_ClearStatusFlags(base, kECSPI_RxFifoOverFlowFlag); + if ((handle->callback) != NULL) + { + (handle->callback)(base, handle, kStatus_ECSPI_HardwareOverFlow, handle->userData); + } + } + /* If needs to receive data, do a receive */ + if ((handle->rxRemainingBytes) != 0UL) + { + ECSPI_ReceiveTransfer(base, handle); + } + + /* We always need to send a data to make the ECSPI run */ + if ((handle->txRemainingBytes) != 0UL) + { + ECSPI_SendTransfer(base, handle); + } + + /* All the transfer finished */ + if ((handle->txRemainingBytes == 0UL) && (handle->rxRemainingBytes == 0UL)) + { + /* Complete the transfer */ + ECSPI_SlaveTransferAbort(base, handle); + + if ((handle->callback) != NULL) + { + (handle->callback)(base, handle, kStatus_Success, handle->userData); + } + } +} + +static void ECSPI_CommonIRQHandler(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + if (ECSPI_IsMaster(base, handle->channel)) + { + s_ecspiMasterIsr(base, handle); + } + else + { + s_ecspiSlaveIsr(base, handle); + } + SDK_ISR_EXIT_BARRIER; +} + +#if defined(ECSPI1) +void ECSPI1_DriverIRQHandler(void); +void ECSPI1_DriverIRQHandler(void) +{ + assert(s_ecspiHandle[1] != NULL); + ECSPI_CommonIRQHandler(ECSPI1, s_ecspiHandle[1]); +} +#endif /* ECSPI1 */ + +#if defined(ECSPI2) +void ECSPI2_DriverIRQHandler(void); +void ECSPI2_DriverIRQHandler(void) +{ + assert(s_ecspiHandle[2] != NULL); + ECSPI_CommonIRQHandler(ECSPI2, s_ecspiHandle[2]); +} +#endif /* ECSPI2 */ + +#if defined(ECSPI3) +void ECSPI3_DriverIRQHandler(void); +void ECSPI3_DriverIRQHandler(void) +{ + assert(s_ecspiHandle[3] != NULL); + ECSPI_CommonIRQHandler(ECSPI3, s_ecspiHandle[3]); +} +#endif /* ECSPI3 */ + +#if defined(ECSPI4) +void ECSPI4_DriverIRQHandler(void); +void ECSPI4_DriverIRQHandler(void) +{ + assert(s_ecspiHandle[4] != NULL); + ECSPI_CommonIRQHandler(ECSPI4, s_ecspiHandle[4]); +} +#endif /* ECSPI4 */ diff --git a/devices/MIMX8MQ6/drivers/fsl_ecspi.h b/devices/MIMX8MQ6/drivers/fsl_ecspi.h new file mode 100644 index 000000000..de2dee157 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_ecspi.h @@ -0,0 +1,740 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_ECSPI_H_ +#define _FSL_ECSPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ecspi_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief ECSPI driver version. */ +#define FSL_ECSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +#ifndef ECSPI_DUMMYDATA +/*! @brief ECSPI dummy transfer data, the data is sent while txBuff is NULL. */ +#define ECSPI_DUMMYDATA (0xFFFFFFFFU) +#endif + +/*! @brief Retry times for waiting flag. */ +#ifndef SPI_RETRY_TIMES +#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief Return status for the ECSPI driver. */ +enum +{ + kStatus_ECSPI_Busy = MAKE_STATUS(kStatusGroup_ECSPI, 0), /*!< ECSPI bus is busy */ + kStatus_ECSPI_Idle = MAKE_STATUS(kStatusGroup_ECSPI, 1), /*!< ECSPI is idle */ + kStatus_ECSPI_Error = MAKE_STATUS(kStatusGroup_ECSPI, 2), /*!< ECSPI error */ + kStatus_ECSPI_HardwareOverFlow = MAKE_STATUS(kStatusGroup_ECSPI, 3), /*!< ECSPI hardware overflow */ + kStatus_ECSPI_Timeout = MAKE_STATUS(kStatusGroup_ECSPI, 4), /*!< ECSPI timeout polling status flags. */ +}; + +/*! @brief ECSPI clock polarity configuration. */ +typedef enum _ecspi_clock_polarity +{ + kECSPI_PolarityActiveHigh = 0x0U, /*!< Active-high ECSPI polarity high (idles low). */ + kECSPI_PolarityActiveLow, /*!< Active-low ECSPI polarity low (idles high). */ +} ecspi_clock_polarity_t; + +/*! @brief ECSPI clock phase configuration. */ +typedef enum _ecspi_clock_phase +{ + kECSPI_ClockPhaseFirstEdge = + 0x0U, /*!< First edge on SPSCK occurs at the middle of the first cycle of a data transfer. */ + kECSPI_ClockPhaseSecondEdge, /*!< First edge on SPSCK occurs at the start of the first cycle of a data transfer. */ +} ecspi_clock_phase_t; + +/*! @brief ECSPI interrupt sources. */ +enum +{ + kECSPI_TxfifoEmptyInterruptEnable = ECSPI_INTREG_TEEN_MASK, /*!< Transmit FIFO buffer empty interrupt */ + kECSPI_TxFifoDataRequstInterruptEnable = ECSPI_INTREG_TDREN_MASK, /*!< Transmit FIFO data requst interrupt */ + kECSPI_TxFifoFullInterruptEnable = ECSPI_INTREG_TFEN_MASK, /*!< Transmit FIFO full interrupt */ + kECSPI_RxFifoReadyInterruptEnable = ECSPI_INTREG_RREN_MASK, /*!< Receiver FIFO ready interrupt */ + kECSPI_RxFifoDataRequstInterruptEnable = ECSPI_INTREG_RDREN_MASK, /*!< Receiver FIFO data requst interrupt */ + kECSPI_RxFifoFullInterruptEnable = ECSPI_INTREG_RFEN_MASK, /*!< Receiver FIFO full interrupt */ + kECSPI_RxFifoOverFlowInterruptEnable = ECSPI_INTREG_ROEN_MASK, /*!< Receiver FIFO buffer overflow interrupt */ + kECSPI_TransferCompleteInterruptEnable = ECSPI_INTREG_TCEN_MASK, /*!< Transfer complete interrupt */ + kECSPI_AllInterruptEnable = (ECSPI_INTREG_TEEN_MASK | ECSPI_INTREG_TDREN_MASK | ECSPI_INTREG_TFEN_MASK | + ECSPI_INTREG_RREN_MASK | ECSPI_INTREG_RDREN_MASK | ECSPI_INTREG_RFEN_MASK | + ECSPI_INTREG_ROEN_MASK | ECSPI_INTREG_TCEN_MASK), /*!< All interrupt */ +}; + +/*! @brief ECSPI status flags. */ +enum +{ + kECSPI_TxfifoEmptyFlag = ECSPI_STATREG_TE_MASK, /*!< Transmit FIFO buffer empty flag */ + kECSPI_TxFifoDataRequstFlag = ECSPI_STATREG_TDR_MASK, /*!< Transmit FIFO data requst flag */ + kECSPI_TxFifoFullFlag = ECSPI_STATREG_TF_MASK, /*!< Transmit FIFO full flag */ + kECSPI_RxFifoReadyFlag = ECSPI_STATREG_RR_MASK, /*!< Receiver FIFO ready flag */ + kECSPI_RxFifoDataRequstFlag = ECSPI_STATREG_RDR_MASK, /*!< Receiver FIFO data requst flag */ + kECSPI_RxFifoFullFlag = ECSPI_STATREG_RF_MASK, /*!< Receiver FIFO full flag */ + kECSPI_RxFifoOverFlowFlag = ECSPI_STATREG_RO_MASK, /*!< Receiver FIFO buffer overflow flag */ + kECSPI_TransferCompleteFlag = ECSPI_STATREG_TC_MASK, /*!< Transfer complete flag */ +}; +/*! @brief ECSPI DMA enable.*/ +enum +{ + kECSPI_TxDmaEnable = ECSPI_DMAREG_TEDEN_MASK, /*!< Tx DMA request source */ + kECSPI_RxDmaEnable = ECSPI_DMAREG_RXDEN_MASK, /*!< Rx DMA request source */ + kECSPI_DmaAllEnable = (ECSPI_DMAREG_TEDEN_MASK | ECSPI_DMAREG_RXDEN_MASK) /*!< All DMA request source*/ +}; + +/*! @brief ECSPI SPI_RDY signal configuration. */ +typedef enum _ecspi_data_ready +{ + kECSPI_DataReadyIgnore = 0x0U, /*!< SPI_RDY signal is ignored */ + kECSPI_DataReadyFallingEdge, /*!< SPI_RDY signal will be triggerd by the falling edge */ + kECSPI_DataReadyLowLevel, /*!< SPI_RDY signal will be triggerd by a low level */ +} ecspi_Data_ready_t; + +/*! @brief ECSPI channel select source. */ +typedef enum _ecspi_channel_source +{ + kECSPI_Channel0 = 0x0U, /*!< Channel 0 is selectd */ + kECSPI_Channel1, /*!< Channel 1 is selectd */ + kECSPI_Channel2, /*!< Channel 2 is selectd */ + kECSPI_Channel3, /*!< Channel 3 is selectd */ +} ecspi_channel_source_t; + +/*! @brief ECSPI master or slave mode configuration. */ +typedef enum _ecspi_master_slave_mode +{ + kECSPI_Slave = 0U, /*!< ECSPI peripheral operates in slave mode.*/ + kECSPI_Master, /*!< ECSPI peripheral operates in master mode.*/ +} ecspi_master_slave_mode_t; + +/*! @brief ECSPI data line inactive state configuration. */ +typedef enum _ecspi_data_line_inactive_state_t +{ + kECSPI_DataLineInactiveStateHigh = 0x0U, /*!< The data line inactive state stays high. */ + kECSPI_DataLineInactiveStateLow, /*!< The data line inactive state stays low. */ +} ecspi_data_line_inactive_state_t; + +/*! @brief ECSPI clock inactive state configuration. */ +typedef enum _ecspi_clock_inactive_state_t +{ + kECSPI_ClockInactiveStateLow = 0x0U, /*!< The SCLK inactive state stays low. */ + kECSPI_ClockInactiveStateHigh, /*!< The SCLK inactive state stays high. */ +} ecspi_clock_inactive_state_t; + +/*! @brief ECSPI active state configuration.*/ +typedef enum _ecspi_chip_select_active_state_t +{ + kECSPI_ChipSelectActiveStateLow = 0x0U, /*!< The SS signal line active stays low. */ + kECSPI_ChipSelectActiveStateHigh, /*!< The SS signal line active stays high. */ +} ecspi_chip_select_active_state_t; + +/*! @brief ECSPI sample period clock configuration.*/ +typedef enum _ecspi_sample_period_clock_source +{ + kECSPI_spiClock = 0x0U, /*!< The sample period clock source is SCLK. */ + kECSPI_lowFreqClock, /*!< The sample seriod clock source is low_frequency reference clock(32.768 kHz). */ +} ecspi_sample_period_clock_source_t; + +/*! @brief ECSPI user channel configure structure.*/ +typedef struct _ecspi_channel_config +{ + ecspi_master_slave_mode_t channelMode; /*!< Channel mode */ + ecspi_clock_inactive_state_t clockInactiveState; /*!< Clock line (SCLK) inactive state */ + ecspi_data_line_inactive_state_t dataLineInactiveState; /*!< Data line (MOSI&MISO) inactive state */ + ecspi_chip_select_active_state_t chipSlectActiveState; /*!< Chip select(SS) line active state */ + ecspi_clock_polarity_t polarity; /*!< Clock polarity */ + ecspi_clock_phase_t phase; /*!< Clock phase */ +} ecspi_channel_config_t; + +/*! @brief ECSPI master configure structure.*/ +typedef struct _ecspi_master_config +{ + ecspi_channel_source_t channel; /*!< Channel number */ + ecspi_channel_config_t channelConfig; /*!< Channel configuration */ + ecspi_sample_period_clock_source_t samplePeriodClock; /*!< Sample period clock source */ + + uint8_t burstLength; /*!< Burst length */ + uint8_t chipSelectDelay; /*!< SS delay time */ + uint16_t samplePeriod; /*!< Sample period */ + uint8_t txFifoThreshold; /*!< TX Threshold */ + uint8_t rxFifoThreshold; /*!< RX Threshold */ + uint32_t baudRate_Bps; /*!< ECSPI baud rate for master mode */ + bool enableLoopback; /*!< Enable the ECSPI loopback test. */ +} ecspi_master_config_t; + +/*! @brief ECSPI slave configure structure.*/ +typedef struct _ecspi_slave_config +{ + ecspi_channel_source_t channel; /*Channel number */ + uint8_t burstLength; /*!< Burst length */ + uint8_t txFifoThreshold; /*!< TX Threshold */ + uint8_t rxFifoThreshold; /*!< RX Threshold */ + ecspi_channel_config_t channelConfig; /*!< Channel configuration */ +} ecspi_slave_config_t; + +/*! @brief ECSPI transfer structure */ +typedef struct _ecspi_transfer +{ + uint32_t *txData; /*!< Send buffer */ + uint32_t *rxData; /*!< Receive buffer */ + size_t dataSize; /*!< Transfer bytes */ + ecspi_channel_source_t channel; /*!< ECSPI channel select */ +} ecspi_transfer_t; + +typedef struct _ecspi_master_handle ecspi_master_handle_t; +/*! @brief Slave handle is the same with master handle */ +typedef ecspi_master_handle_t ecspi_slave_handle_t; + +/*! @brief ECSPI master callback for finished transmit */ +typedef void (*ecspi_master_callback_t)(ECSPI_Type *base, + ecspi_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief ECSPI slave callback for finished transmit */ +typedef void (*ecspi_slave_callback_t)(ECSPI_Type *base, ecspi_slave_handle_t *handle, status_t status, void *userData); + +/*! @brief ECSPI master handle structure */ +struct _ecspi_master_handle +{ + ecspi_channel_source_t channel; /*!< Channel number */ + uint32_t *volatile txData; /*!< Transfer buffer */ + uint32_t *volatile rxData; /*!< Receive buffer */ + volatile size_t txRemainingBytes; /*!< Send data remaining in bytes */ + volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes */ + volatile uint32_t state; /*!< ECSPI internal state */ + size_t transferSize; /*!< Bytes to be transferred */ + ecspi_master_callback_t callback; /*!< ECSPI callback */ + void *userData; /*!< Callback parameter */ +}; + +#if defined(__cplusplus) +extern "C" { +#endif +/******************************************************************************* + * APIs + ******************************************************************************/ +/*! + * @brief Get the instance for ECSPI module. + * + * @param base ECSPI base address + */ +uint32_t ECSPI_GetInstance(ECSPI_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Sets the ECSPI configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in ECSPI_MasterInit(). + * User may use the initialized structure unchanged in ECSPI_MasterInit, or modify + * some fields of the structure before calling ECSPI_MasterInit. After calling this API, + * the master is ready to transfer. + * Example: + @code + ecspi_master_config_t config; + ECSPI_MasterGetDefaultConfig(&config); + @endcode + * + * @param config pointer to config structure + */ +void ECSPI_MasterGetDefaultConfig(ecspi_master_config_t *config); + +/*! + * @brief Initializes the ECSPI with configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by ECSPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + @code + ecspi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + ECSPI_MasterInit(ECSPI0, &config); + @endcode + * + * @param base ECSPI base pointer + * @param config pointer to master configuration structure + * @param srcClock_Hz Source clock frequency. + */ +void ECSPI_MasterInit(ECSPI_Type *base, const ecspi_master_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Sets the ECSPI configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in ECSPI_SlaveInit(). + * User may use the initialized structure unchanged in ECSPI_SlaveInit(), or modify + * some fields of the structure before calling ECSPI_SlaveInit(). After calling this API, + * the master is ready to transfer. + * Example: + @code + ecspi_Slaveconfig_t config; + ECSPI_SlaveGetDefaultConfig(&config); + @endcode + * + * @param config pointer to config structure + */ +void ECSPI_SlaveGetDefaultConfig(ecspi_slave_config_t *config); + +/*! + * @brief Initializes the ECSPI with configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by ECSPI_SlaveGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + @code + ecspi_Salveconfig_t config = { + .baudRate_Bps = 400000, + ... + }; + ECSPI_SlaveInit(ECSPI1, &config); + @endcode + * + * @param base ECSPI base pointer + * @param config pointer to master configuration structure + */ +void ECSPI_SlaveInit(ECSPI_Type *base, const ecspi_slave_config_t *config); + +/*! + * @brief De-initializes the ECSPI. + * + * Calling this API resets the ECSPI module, gates the ECSPI clock. + * The ECSPI module can't work unless calling the ECSPI_MasterInit/ECSPI_SlaveInit to initialize module. + * + * @param base ECSPI base pointer + */ +void ECSPI_Deinit(ECSPI_Type *base); + +/*! + * @brief Enables or disables the ECSPI. + * + * @param base ECSPI base pointer + * @param enable pass true to enable module, false to disable module + */ +static inline void ECSPI_Enable(ECSPI_Type *base, bool enable) +{ + if (enable) + { + base->CONREG |= ECSPI_CONREG_EN_MASK; + } + else + { + base->CONREG &= ~ECSPI_CONREG_EN_MASK; + } +} +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the status flag. + * + * @param base ECSPI base pointer + * @return ECSPI Status, use status flag to AND _ecspi_flags could get the related status. + */ +static inline uint32_t ECSPI_GetStatusFlags(ECSPI_Type *base) +{ + return (base->STATREG); +} + +/*! + * @brief Clear the status flag. + * + * @param base ECSPI base pointer + * @param mask ECSPI Status, use status flag to AND _ecspi_flags could get the related status. + */ +static inline void ECSPI_ClearStatusFlags(ECSPI_Type *base, uint32_t mask) +{ + base->STATREG |= mask; +} +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt for the ECSPI. + * + * @param base ECSPI base pointer + * @param mask ECSPI interrupt source. The parameter can be any combination of the following values: + * @arg kECSPI_TxfifoEmptyInterruptEnable + * @arg kECSPI_TxFifoDataRequstInterruptEnable + * @arg kECSPI_TxFifoFullInterruptEnable + * @arg kECSPI_RxFifoReadyInterruptEnable + * @arg kECSPI_RxFifoDataRequstInterruptEnable + * @arg kECSPI_RxFifoFullInterruptEnable + * @arg kECSPI_RxFifoOverFlowInterruptEnable + * @arg kECSPI_TransferCompleteInterruptEnable + * @arg kECSPI_AllInterruptEnable + */ +static inline void ECSPI_EnableInterrupts(ECSPI_Type *base, uint32_t mask) +{ + base->INTREG |= mask; +} + +/*! + * @brief Disables the interrupt for the ECSPI. + * + * @param base ECSPI base pointer + * @param mask ECSPI interrupt source. The parameter can be any combination of the following values: + * @arg kECSPI_TxfifoEmptyInterruptEnable + * @arg kECSPI_TxFifoDataRequstInterruptEnable + * @arg kECSPI_TxFifoFullInterruptEnable + * @arg kECSPI_RxFifoReadyInterruptEnable + * @arg kECSPI_RxFifoDataRequstInterruptEnable + * @arg kECSPI_RxFifoFullInterruptEnable + * @arg kECSPI_RxFifoOverFlowInterruptEnable + * @arg kECSPI_TransferCompleteInterruptEnable + * @arg kECSPI_AllInterruptEnable + */ +static inline void ECSPI_DisableInterrupts(ECSPI_Type *base, uint32_t mask) +{ + base->INTREG &= ~(mask); +} +/*! @} */ + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Software reset. + * + * @param base ECSPI base pointer + */ +static inline void ECSPI_SoftwareReset(ECSPI_Type *base) +{ + /* Disables the block and resets the internal logic with the exception of the ECSPI control register */ + base->CONREG &= ~ECSPI_CONREG_EN_MASK; + /* Software reset can not reset the control register, so clear the control register manually */ + base->CONREG = 0x0U; +} +/*! @} */ + +/*! + * @name Channel mode check + * @{ + */ + +/*! + * @brief Mode check + * + * @param base ECSPI base pointer + * @param channel ECSPI channel source + * @return mode of channel + */ +static inline bool ECSPI_IsMaster(ECSPI_Type *base, ecspi_channel_source_t channel) +{ + return (bool)(((base->CONREG & ECSPI_CONREG_CHANNEL_MODE_MASK) >> + (ECSPI_CONREG_CHANNEL_MODE_SHIFT + (uint32_t)channel)) & + 0x1U); +} +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the DMA source for ECSPI. + * + * @param base ECSPI base pointer + * @param mask ECSPI DMA source. The parameter can be any of the following values: + * @arg kECSPI_TxDmaEnable + * @arg kECSPI_RxDmaEnable + * @arg kECSPI_DmaAllEnable + * @param enable True means enable DMA, false means disable DMA + */ +static inline void ECSPI_EnableDMA(ECSPI_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->DMAREG |= mask; + } + else + { + base->DMAREG &= ~mask; + } +} +/*! @} */ + +/*! + * @name FIFO Operation + * @{ + */ + +/*! + * @brief Get the Tx FIFO data count. + * + * @param base ECSPI base pointer. + * @return the number of words in Tx FIFO buffer. + */ +static inline uint8_t ECSPI_GetTxFifoCount(ECSPI_Type *base) +{ + return (uint8_t)((base->TESTREG & ECSPI_TESTREG_TXCNT_MASK) >> ECSPI_TESTREG_TXCNT_SHIFT); +} + +/*! + * @brief Get the Rx FIFO data count. + * + * @param base ECSPI base pointer. + * @return the number of words in Rx FIFO buffer. + */ +static inline uint8_t ECSPI_GetRxFifoCount(ECSPI_Type *base) +{ + return (uint8_t)((base->TESTREG & ECSPI_TESTREG_RXCNT_MASK) >> ECSPI_TESTREG_RXCNT_SHIFT); +} +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Set channel select for transfer. + * + * @param base ECSPI base pointer + * @param channel Channel source. + */ +static inline void ECSPI_SetChannelSelect(ECSPI_Type *base, ecspi_channel_source_t channel) +{ + /* Clear Channel select bits in CONREG register */ + uint32_t temp = base->CONREG & (~(ECSPI_CONREG_CHANNEL_SELECT_MASK)); + /* Set channel select bits */ + base->CONREG = (temp | ECSPI_CONREG_CHANNEL_SELECT(channel)); +} +/*! + * @brief Set channel select configuration for transfer. + * + * The purpose of this API is to set the channel will be use to transfer. + * User may use this API after instance has been initialized or before transfer start. + * The configuration structure _ecspi_channel_config_ can be filled by user from scratch. + * After calling this API, user can select this channel as transfer channel. + * + * @param base ECSPI base pointer + * @param channel Channel source. + * @param config Configuration struct of channel + */ +void ECSPI_SetChannelConfig(ECSPI_Type *base, ecspi_channel_source_t channel, const ecspi_channel_config_t *config); + +/*! + * @brief Sets the baud rate for ECSPI transfer. This is only used in master. + * + * @param base ECSPI base pointer + * @param baudRate_Bps baud rate needed in Hz. + * @param srcClock_Hz ECSPI source clock frequency in Hz. + */ +void ECSPI_SetBaudRate(ECSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends a buffer of data bytes using a blocking method. + * + * @note This function blocks via polling until all bytes have been sent. + * + * @param base ECSPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to send + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_ECSPI_Timeout The transfer timed out and was aborted. + */ +status_t ECSPI_WriteBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Writes a data into the ECSPI data register. + * + * @param base ECSPI base pointer + * @param data Data needs to be write. + */ +static inline void ECSPI_WriteData(ECSPI_Type *base, uint32_t data) +{ + base->TXDATA = data; +} + +/*! + * @brief Gets a data from the ECSPI data register. + * + * @param base ECSPI base pointer + * @return Data in the register. + */ +static inline uint32_t ECSPI_ReadData(ECSPI_Type *base) +{ + return (uint32_t)(base->RXDATA); +} +/*! @} */ + +/*! + * @name Transactional + * @{ + */ +/*! + * @brief Initializes the ECSPI master handle. + * + * This function initializes the ECSPI master handle which can be used for other ECSPI master transactional APIs. + * Usually, + * for a specified ECSPI instance, call this API once to get the initialized handle. + * + * @param base ECSPI peripheral base address. + * @param handle ECSPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void ECSPI_MasterTransferCreateHandle(ECSPI_Type *base, + ecspi_master_handle_t *handle, + ecspi_master_callback_t callback, + void *userData); + +/*! + * @brief Transfers a block of data using a polling method. + * + * @param base SPI base pointer + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_ECSPI_Timeout The transfer timed out and was aborted. + */ +status_t ECSPI_MasterTransferBlocking(ECSPI_Type *base, ecspi_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking ECSPI interrupt transfer. + * + * @note The API immediately returns after transfer initialization is finished. + * @note If ECSPI transfer data frame size is 16 bits, the transfer size cannot be an odd number. + * + * @param base ECSPI peripheral base address. + * @param handle pointer to ecspi_master_handle_t structure which stores the transfer state + * @param xfer pointer to ecspi_transfer_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_ECSPI_Busy ECSPI is not idle, is running another transfer. + */ +status_t ECSPI_MasterTransferNonBlocking(ECSPI_Type *base, ecspi_master_handle_t *handle, ecspi_transfer_t *xfer); + +/*! + * @brief Gets the bytes of the ECSPI interrupt transferred. + * + * @param base ECSPI peripheral base address. + * @param handle Pointer to ECSPI transfer handle, this should be a static variable. + * @param count Transferred bytes of ECSPI master. + * @retval kStatus_ECSPI_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t ECSPI_MasterTransferGetCount(ECSPI_Type *base, ecspi_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an ECSPI transfer using interrupt. + * + * @param base ECSPI peripheral base address. + * @param handle Pointer to ECSPI transfer handle, this should be a static variable. + */ +void ECSPI_MasterTransferAbort(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/*! + * @brief Interrupts the handler for the ECSPI. + * + * @param base ECSPI peripheral base address. + * @param handle pointer to ecspi_master_handle_t structure which stores the transfer state. + */ +void ECSPI_MasterTransferHandleIRQ(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/*! + * @brief Initializes the ECSPI slave handle. + * + * This function initializes the ECSPI slave handle which can be used for other ECSPI slave transactional APIs. Usually, + * for a specified ECSPI instance, call this API once to get the initialized handle. + * + * @param base ECSPI peripheral base address. + * @param handle ECSPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void ECSPI_SlaveTransferCreateHandle(ECSPI_Type *base, + ecspi_slave_handle_t *handle, + ecspi_slave_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking ECSPI slave interrupt transfer. + * + * @note The API returns immediately after the transfer initialization is finished. + * + * @param base ECSPI peripheral base address. + * @param handle pointer to ecspi_master_handle_t structure which stores the transfer state + * @param xfer pointer to ecspi_transfer_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_ECSPI_Busy ECSPI is not idle, is running another transfer. + */ +static inline status_t ECSPI_SlaveTransferNonBlocking(ECSPI_Type *base, + ecspi_slave_handle_t *handle, + ecspi_transfer_t *xfer) +{ + return ECSPI_MasterTransferNonBlocking(base, handle, xfer); +} + +/*! + * @brief Gets the bytes of the ECSPI interrupt transferred. + * + * @param base ECSPI peripheral base address. + * @param handle Pointer to ECSPI transfer handle, this should be a static variable. + * @param count Transferred bytes of ECSPI slave. + * @retval kStatus_ECSPI_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +static inline status_t ECSPI_SlaveTransferGetCount(ECSPI_Type *base, ecspi_slave_handle_t *handle, size_t *count) +{ + return ECSPI_MasterTransferGetCount(base, handle, count); +} + +/*! + * @brief Aborts an ECSPI slave transfer using interrupt. + * + * @param base ECSPI peripheral base address. + * @param handle Pointer to ECSPI transfer handle, this should be a static variable. + */ +static inline void ECSPI_SlaveTransferAbort(ECSPI_Type *base, ecspi_slave_handle_t *handle) +{ + ECSPI_MasterTransferAbort(base, handle); +} + +/*! + * @brief Interrupts a handler for the ECSPI slave. + * + * @param base ECSPI peripheral base address. + * @param handle pointer to ecspi_slave_handle_t structure which stores the transfer state + */ +void ECSPI_SlaveTransferHandleIRQ(ECSPI_Type *base, ecspi_slave_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_ECSPI_H_*/ diff --git a/devices/MIMX8MQ6/drivers/fsl_ecspi_freertos.c b/devices/MIMX8MQ6/drivers/fsl_ecspi_freertos.c new file mode 100644 index 000000000..413175e80 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_ecspi_freertos.c @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ecspi_freertos.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ecspi_freertos" +#endif + +static void ECSPI_RTOS_Callback(ECSPI_Type *base, ecspi_master_handle_t *drv_handle, status_t status, void *userData) +{ + ecspi_rtos_handle_t *handle = (ecspi_rtos_handle_t *)userData; + BaseType_t reschedule; + handle->async_status = status; + (void)xSemaphoreGiveFromISR(handle->event, &reschedule); + portYIELD_FROM_ISR(reschedule); +} + +/*! + * brief Initializes ECSPI. + * + * This function initializes the ECSPI module and related RTOS context. + * + * param handle The RTOS ECSPI handle, the pointer to an allocated space for RTOS context. + * param base The pointer base address of the ECSPI instance to initialize. + * param masterConfig Configuration structure to set-up ECSPI in master mode. + * param srcClock_Hz Frequency of input clock of the ECSPI module. + * return status of the operation. + */ +status_t ECSPI_RTOS_Init(ecspi_rtos_handle_t *handle, + ECSPI_Type *base, + const ecspi_master_config_t *masterConfig, + uint32_t srcClock_Hz) +{ + if (handle == NULL) + { + return kStatus_InvalidArgument; + } + + if (base == NULL) + { + return kStatus_InvalidArgument; + } + + (void)memset(handle, 0, sizeof(ecspi_rtos_handle_t)); +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->mutex = xSemaphoreCreateMutexStatic(&handle->mutexBuffer); +#else + handle->mutex = xSemaphoreCreateMutex(); +#endif + if (handle->mutex == NULL) + { + return kStatus_Fail; + } + +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->event = xSemaphoreCreateBinaryStatic(&handle->semaphoreBuffer); +#else + handle->event = xSemaphoreCreateBinary(); +#endif + if (handle->event == NULL) + { + vSemaphoreDelete(handle->mutex); + return kStatus_Fail; + } + + handle->base = base; + + ECSPI_MasterInit(handle->base, masterConfig, srcClock_Hz); + ECSPI_MasterTransferCreateHandle(handle->base, &handle->drv_handle, ECSPI_RTOS_Callback, (void *)handle); + + return kStatus_Success; +} + +/*! + * brief Deinitializes the ECSPI. + * + * This function deinitializes the ECSPI module and related RTOS context. + * + * param handle The RTOS ECSPI handle. + */ +status_t ECSPI_RTOS_Deinit(ecspi_rtos_handle_t *handle) +{ + ECSPI_Deinit(handle->base); + vSemaphoreDelete(handle->event); + vSemaphoreDelete(handle->mutex); + + return kStatus_Success; +} + +/*! + * brief Performs ECSPI transfer. + * + * This function performs an ECSPI transfer according to data given in the transfer structure. + * + * param handle The RTOS ECSPI handle. + * param transfer Structure specifying the transfer parameters. + * return status of the operation. + */ +status_t ECSPI_RTOS_Transfer(ecspi_rtos_handle_t *handle, ecspi_transfer_t *transfer) +{ + status_t status; + + /* Lock resource mutex */ + if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) + { + return kStatus_ECSPI_Busy; + } + + status = ECSPI_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->mutex); + return status; + } + + /* Wait for transfer to finish */ + if (xSemaphoreTake(handle->event, portMAX_DELAY) != pdTRUE) + { + return kStatus_ECSPI_Error; + } + + /* Unlock resource mutex */ + (void)xSemaphoreGive(handle->mutex); + + /* Return status captured by callback function */ + return handle->async_status; +} diff --git a/devices/MIMX8MQ6/drivers/fsl_ecspi_freertos.h b/devices/MIMX8MQ6/drivers/fsl_ecspi_freertos.h new file mode 100644 index 000000000..dc129c4de --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_ecspi_freertos.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __FSL_ECSPI_FREERTOS_H__ +#define __FSL_ECSPI_FREERTOS_H__ + +#include "FreeRTOS.h" +#include "portable.h" +#include "semphr.h" + +#include "fsl_ecspi.h" + +/*! + * @addtogroup ecspi_freertos_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief ECSPI FreeRTOS driver version. */ +#define FSL_ECSPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +/*! + * @cond RTOS_PRIVATE + * @brief ECSPI FreeRTOS handle + */ +typedef struct _ecspi_rtos_handle +{ + ECSPI_Type *base; /*!< ECSPI base address */ + ecspi_master_handle_t drv_handle; /*!< Handle of the underlying driver, treated as opaque by the RTOS layer */ + status_t async_status; /*!< Transactional state of the underlying driver */ + SemaphoreHandle_t mutex; /*!< Mutex to lock the handle during a trasfer */ + SemaphoreHandle_t event; /*!< Semaphore to notify and unblock task when transfer ends */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t mutexBuffer; /*!< Statically allocated memory for mutex */ + StaticSemaphore_t semaphoreBuffer; /*!< Statically allocated memory for event */ +#endif +} ecspi_rtos_handle_t; +/*! \endcond */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name ECSPI RTOS Operation + * @{ + */ + +/*! + * @brief Initializes ECSPI. + * + * This function initializes the ECSPI module and related RTOS context. + * + * @param handle The RTOS ECSPI handle, the pointer to an allocated space for RTOS context. + * @param base The pointer base address of the ECSPI instance to initialize. + * @param masterConfig Configuration structure to set-up ECSPI in master mode. + * @param srcClock_Hz Frequency of input clock of the ECSPI module. + * @return status of the operation. + */ +status_t ECSPI_RTOS_Init(ecspi_rtos_handle_t *handle, + ECSPI_Type *base, + const ecspi_master_config_t *masterConfig, + uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the ECSPI. + * + * This function deinitializes the ECSPI module and related RTOS context. + * + * @param handle The RTOS ECSPI handle. + */ +status_t ECSPI_RTOS_Deinit(ecspi_rtos_handle_t *handle); + +/*! + * @brief Performs ECSPI transfer. + * + * This function performs an ECSPI transfer according to data given in the transfer structure. + * + * @param handle The RTOS ECSPI handle. + * @param transfer Structure specifying the transfer parameters. + * @return status of the operation. + */ +status_t ECSPI_RTOS_Transfer(ecspi_rtos_handle_t *handle, ecspi_transfer_t *transfer); + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* __FSL_ECSPI_FREERTOS_H__ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_gpio.c b/devices/MIMX8MQ6/drivers/fsl_gpio.c new file mode 100644 index 000000000..341757d91 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_gpio.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.igpio" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of GPIO peripheral base address. */ +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of GPIO clock name. */ +static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the GPIO instance according to the GPIO base + * + * @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval GPIO instance + */ +static uint32_t GPIO_GetInstance(GPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GPIO_GetInstance(GPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_gpioBases); instance++) + { + if (s_gpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gpioBases)); + + return instance; +} + +/*! + * brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * param base GPIO base pointer. + * param pin Specifies the pin number + * param initConfig pointer to a ref gpio_pin_config_t structure that + * contains the configuration information. + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable GPIO clock. */ + uint32_t instance = GPIO_GetInstance(base); + + /* If The clock IP is valid, enable the clock gate. */ + if ((instance < ARRAY_SIZE(s_gpioClock)) && (kCLOCK_IpInvalid != s_gpioClock[instance])) + { + (void)CLOCK_EnableClock(s_gpioClock[instance]); + } +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Register reset to default value */ + base->IMR &= ~(1UL << pin); + + /* Configure GPIO pin direction */ + if (Config->direction == kGPIO_DigitalInput) + { + base->GDIR &= ~(1UL << pin); + } + else + { + GPIO_PinWrite(base, pin, Config->outputLogic); + base->GDIR |= (1UL << pin); + } + + /* Configure GPIO pin interrupt mode */ + GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode); +} + +/*! + * brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * param base GPIO base pointer. + * param pin GPIO port pin number. + * param output GPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + assert(pin < 32U); + if (output == 0U) + { +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && FSL_FEATURE_IGPIO_HAS_DR_CLEAR) + base->DR_CLEAR = (1UL << pin); +#else + base->DR &= ~(1UL << pin); /* Set pin output to low level.*/ +#endif + } + else + { +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && FSL_FEATURE_IGPIO_HAS_DR_SET) + base->DR_SET = (1UL << pin); +#else + base->DR |= (1UL << pin); /* Set pin output to high level.*/ +#endif + } +} + +/*! + * brief Sets the current pin interrupt mode. + * + * param base GPIO base pointer. + * param pin GPIO port pin number. + * param pininterruptMode pointer to a ref gpio_interrupt_mode_t structure + * that contains the interrupt mode information. + */ +void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +{ + volatile uint32_t *icr; + uint32_t icrShift; + + icrShift = pin; + + /* Register reset to default value */ + base->EDGE_SEL &= ~(1UL << pin); + + if (pin < 16U) + { + icr = &(base->ICR1); + } + else + { + icr = &(base->ICR2); + icrShift -= 16U; + } + switch (pinInterruptMode) + { + case (kGPIO_IntLowLevel): + *icr &= ~(3UL << (2UL * icrShift)); + break; + case (kGPIO_IntHighLevel): + *icr = (*icr & (~(3UL << (2UL * icrShift)))) | (1UL << (2UL * icrShift)); + break; + case (kGPIO_IntRisingEdge): + *icr = (*icr & (~(3UL << (2UL * icrShift)))) | (2UL << (2UL * icrShift)); + break; + case (kGPIO_IntFallingEdge): + *icr |= (3UL << (2UL * icrShift)); + break; + case (kGPIO_IntRisingOrFallingEdge): + base->EDGE_SEL |= (1UL << pin); + break; + default:; /* Intentional empty default */ + break; + } +} diff --git a/devices/MIMX8MQ6/drivers/fsl_gpio.h b/devices/MIMX8MQ6/drivers/fsl_gpio.h new file mode 100644 index 000000000..bfbda2522 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_gpio.h @@ -0,0 +1,344 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPIO driver version. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*@}*/ + +/*! @brief GPIO direction definition. */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/ +} gpio_pin_direction_t; + +/*! @brief GPIO interrupt mode definition. */ +typedef enum _gpio_interrupt_mode +{ + kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/ + kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/ + kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/ + kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/ + kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/ + kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/ +} gpio_interrupt_mode_t; + +/*! @brief GPIO Init structure definition. */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ + gpio_interrupt_mode_t + interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ +} gpio_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name GPIO Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * @param base GPIO base pointer. + * @param pin Specifies the pin number + * @param Config pointer to a @ref gpio_pin_config_t structure that + * contains the configuration information. + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config); +/*@}*/ + +/*! + * @name GPIO Reads and Write Functions + * @{ + */ + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param output GPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output); + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. + */ +static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + GPIO_PinWrite(base, pin, output); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && (FSL_FEATURE_IGPIO_HAS_DR_SET == 1)) + base->DR_SET = mask; +#else + base->DR |= mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_SET */ +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet. + */ +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortSet(base, mask); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && (FSL_FEATURE_IGPIO_HAS_DR_CLEAR == 1)) + base->DR_CLEAR = mask; +#else + base->DR &= ~mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_CLEAR */ +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear. + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortClear(base, mask); +} + +/*! + * @brief Reverses the current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1)) + base->DR_TOGGLE = mask; +#else + base->DR ^= mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */ +} + +/*! + * @brief Reads the current input value of the GPIO port. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO port input value. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) +{ + assert(pin < 32U); + + return (((base->DR) >> pin) & 0x1U); +} + +/*! + * @brief Reads the current input value of the GPIO port. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) +{ + return GPIO_PinRead(base, pin); +} +/*@}*/ + +/*! + * @name GPIO Reads Pad Status Functions + * @{ + */ + +/*! + * @brief Reads the current GPIO pin pad status. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO pin pad status value. + */ +static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin) +{ + assert(pin < 32U); + + return (uint8_t)(((base->PSR) >> pin) & 0x1U); +} + +/*! + * @brief Reads the current GPIO pin pad status. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinReadPadStatus. + */ +static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin) +{ + return GPIO_PinReadPadStatus(base, pin); +} + +/*@}*/ + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Sets the current pin interrupt mode. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param pinInterruptMode pointer to a @ref gpio_interrupt_mode_t structure + * that contains the interrupt mode information. + */ +void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode); + +/*! + * @brief Sets the current pin interrupt mode. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinSetInterruptConfig. + */ +static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +{ + GPIO_PinSetInterruptConfig(base, pin, pinInterruptMode); +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask) +{ + base->IMR |= mask; +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortEnableInterrupts(base, mask); +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask) +{ + base->IMR &= ~mask; +} + +/*! + * @brief Disables the specific pin interrupt. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortDisableInterrupts. + */ +static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortDisableInterrupts(base, mask); +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base) +{ + return base->ISR; +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) +{ + return GPIO_PortGetInterruptFlags(base); +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + base->ISR = mask; +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortClearInterruptFlags(base, mask); +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_GPIO_H_*/ diff --git a/devices/MIMX8MQ6/drivers/fsl_gpt.c b/devices/MIMX8MQ6/drivers/fsl_gpt.c new file mode 100644 index 000000000..050ebf1f5 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_gpt.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gpt" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to GPT bases for each instance. */ +static GPT_Type *const s_gptBases[] = GPT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to GPT clocks for each instance. */ +static const clock_ip_name_t s_gptClocks[] = GPT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t GPT_GetInstance(GPT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_gptBases); instance++) + { + if (s_gptBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gptBases)); + + return instance; +} + +/*! + * brief Initialize GPT to reset state and initialize running mode. + * + * param base GPT peripheral base address. + * param initConfig GPT mode setting configuration. + */ +void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig) +{ + assert(NULL != initConfig); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the GPT clock*/ + (void)CLOCK_EnableClock(s_gptClocks[GPT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + base->CR = 0U; + + GPT_SoftwareReset(base); + + base->CR = + (initConfig->enableFreeRun ? GPT_CR_FRR_MASK : 0UL) | (initConfig->enableRunInWait ? GPT_CR_WAITEN_MASK : 0UL) | + (initConfig->enableRunInStop ? GPT_CR_STOPEN_MASK : 0UL) | + (initConfig->enableRunInDoze ? GPT_CR_DOZEEN_MASK : 0UL) | + (initConfig->enableRunInDbg ? GPT_CR_DBGEN_MASK : 0UL) | (initConfig->enableMode ? GPT_CR_ENMOD_MASK : 0UL); + + GPT_SetClockSource(base, initConfig->clockSource); + GPT_SetClockDivider(base, initConfig->divider); +} + +/*! + * brief Disables the module and gates the GPT clock. + * + * param base GPT peripheral base address. + */ +void GPT_Deinit(GPT_Type *base) +{ + /* Disable GPT timers */ + base->CR = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the GPT clock*/ + (void)CLOCK_DisableClock(s_gptClocks[GPT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Fills in the GPT configuration structure with default settings. + * + * The default values are: + * code + * config->clockSource = kGPT_ClockSource_Periph; + * config->divider = 1U; + * config->enableRunInStop = true; + * config->enableRunInWait = true; + * config->enableRunInDoze = false; + * config->enableRunInDbg = false; + * config->enableFreeRun = false; + * config->enableMode = true; + * endcode + * param config Pointer to the user configuration structure. + */ +void GPT_GetDefaultConfig(gpt_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->clockSource = kGPT_ClockSource_Periph; + config->divider = 1U; + config->enableRunInStop = true; + config->enableRunInWait = true; + config->enableRunInDoze = false; + config->enableRunInDbg = false; + config->enableFreeRun = false; + config->enableMode = true; +} diff --git a/devices/MIMX8MQ6/drivers/fsl_gpt.h b/devices/MIMX8MQ6/drivers/fsl_gpt.h new file mode 100644 index 000000000..0cf070a6c --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_gpt.h @@ -0,0 +1,509 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_GPT_H_ +#define _FSL_GPT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpt + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +/*! + * @brief List of clock sources + * @note Actual number of clock sources is SoC dependent + */ +typedef enum _gpt_clock_source +{ + kGPT_ClockSource_Off = 0U, /*!< GPT Clock Source Off.*/ + kGPT_ClockSource_Periph = 1U, /*!< GPT Clock Source from Peripheral Clock.*/ + kGPT_ClockSource_HighFreq = 2U, /*!< GPT Clock Source from High Frequency Reference Clock.*/ + kGPT_ClockSource_Ext = 3U, /*!< GPT Clock Source from external pin.*/ + kGPT_ClockSource_LowFreq = 4U, /*!< GPT Clock Source from Low Frequency Reference Clock.*/ + kGPT_ClockSource_Osc = 5U, /*!< GPT Clock Source from Crystal oscillator.*/ +} gpt_clock_source_t; + +/*! @brief List of input capture channel number. */ +typedef enum _gpt_input_capture_channel +{ + kGPT_InputCapture_Channel1 = 0U, /*!< GPT Input Capture Channel1.*/ + kGPT_InputCapture_Channel2 = 1U, /*!< GPT Input Capture Channel2.*/ +} gpt_input_capture_channel_t; + +/*! @brief List of input capture operation mode. */ +typedef enum _gpt_input_operation_mode +{ + kGPT_InputOperation_Disabled = 0U, /*!< Don't capture.*/ + kGPT_InputOperation_RiseEdge = 1U, /*!< Capture on rising edge of input pin.*/ + kGPT_InputOperation_FallEdge = 2U, /*!< Capture on falling edge of input pin.*/ + kGPT_InputOperation_BothEdge = 3U, /*!< Capture on both edges of input pin.*/ +} gpt_input_operation_mode_t; + +/*! @brief List of output compare channel number. */ +typedef enum _gpt_output_compare_channel +{ + kGPT_OutputCompare_Channel1 = 0U, /*!< Output Compare Channel1.*/ + kGPT_OutputCompare_Channel2 = 1U, /*!< Output Compare Channel2.*/ + kGPT_OutputCompare_Channel3 = 2U, /*!< Output Compare Channel3.*/ +} gpt_output_compare_channel_t; + +/*! @brief List of output compare operation mode. */ +typedef enum _gpt_output_operation_mode +{ + kGPT_OutputOperation_Disconnected = 0U, /*!< Don't change output pin.*/ + kGPT_OutputOperation_Toggle = 1U, /*!< Toggle output pin.*/ + kGPT_OutputOperation_Clear = 2U, /*!< Set output pin low.*/ + kGPT_OutputOperation_Set = 3U, /*!< Set output pin high.*/ + kGPT_OutputOperation_Activelow = 4U, /*!< Generate a active low pulse on output pin.*/ +} gpt_output_operation_mode_t; + +/*! @brief List of GPT interrupts */ +typedef enum _gpt_interrupt_enable +{ + kGPT_OutputCompare1InterruptEnable = GPT_IR_OF1IE_MASK, /*!< Output Compare Channel1 interrupt enable*/ + kGPT_OutputCompare2InterruptEnable = GPT_IR_OF2IE_MASK, /*!< Output Compare Channel2 interrupt enable*/ + kGPT_OutputCompare3InterruptEnable = GPT_IR_OF3IE_MASK, /*!< Output Compare Channel3 interrupt enable*/ + kGPT_InputCapture1InterruptEnable = GPT_IR_IF1IE_MASK, /*!< Input Capture Channel1 interrupt enable*/ + kGPT_InputCapture2InterruptEnable = GPT_IR_IF2IE_MASK, /*!< Input Capture Channel1 interrupt enable*/ + kGPT_RollOverFlagInterruptEnable = GPT_IR_ROVIE_MASK, /*!< Counter rolled over interrupt enable*/ +} gpt_interrupt_enable_t; + +/*! @brief Status flag. */ +typedef enum _gpt_status_flag +{ + kGPT_OutputCompare1Flag = GPT_SR_OF1_MASK, /*!< Output compare channel 1 event.*/ + kGPT_OutputCompare2Flag = GPT_SR_OF2_MASK, /*!< Output compare channel 2 event.*/ + kGPT_OutputCompare3Flag = GPT_SR_OF3_MASK, /*!< Output compare channel 3 event.*/ + kGPT_InputCapture1Flag = GPT_SR_IF1_MASK, /*!< Input Capture channel 1 event.*/ + kGPT_InputCapture2Flag = GPT_SR_IF2_MASK, /*!< Input Capture channel 2 event.*/ + kGPT_RollOverFlag = GPT_SR_ROV_MASK, /*!< Counter reaches maximum value and rolled over to 0 event.*/ +} gpt_status_flag_t; + +/*! @brief Structure to configure the running mode. */ +typedef struct _gpt_init_config +{ + gpt_clock_source_t clockSource; /*!< clock source for GPT module. */ + uint32_t divider; /*!< clock divider (prescaler+1) from clock source to counter. */ + bool enableFreeRun; /*!< true: FreeRun mode, false: Restart mode. */ + bool enableRunInWait; /*!< GPT enabled in wait mode. */ + bool enableRunInStop; /*!< GPT enabled in stop mode. */ + bool enableRunInDoze; /*!< GPT enabled in doze mode. */ + bool enableRunInDbg; /*!< GPT enabled in debug mode. */ + bool enableMode; /*!< true: counter reset to 0 when enabled; + false: counter retain its value when enabled. */ +} gpt_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initialize GPT to reset state and initialize running mode. + * + * @param base GPT peripheral base address. + * @param initConfig GPT mode setting configuration. + */ +void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig); + +/*! + * @brief Disables the module and gates the GPT clock. + * + * @param base GPT peripheral base address. + */ +void GPT_Deinit(GPT_Type *base); + +/*! + * @brief Fills in the GPT configuration structure with default settings. + * + * The default values are: + * @code + * config->clockSource = kGPT_ClockSource_Periph; + * config->divider = 1U; + * config->enableRunInStop = true; + * config->enableRunInWait = true; + * config->enableRunInDoze = false; + * config->enableRunInDbg = false; + * config->enableFreeRun = false; + * config->enableMode = true; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void GPT_GetDefaultConfig(gpt_config_t *config); + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Software reset of GPT module. + * + * @param base GPT peripheral base address. + */ +static inline void GPT_SoftwareReset(GPT_Type *base) +{ + base->CR |= GPT_CR_SWR_MASK; + /* Wait reset finished. */ + while ((base->CR & GPT_CR_SWR_MASK) == GPT_CR_SWR_MASK) + { + } +} + +/*! + * @name Clock source and frequency control + * @{ + */ + +/*! + * @brief Set clock source of GPT. + * + * @param base GPT peripheral base address. + * @param gptClkSource Clock source (see @ref gpt_clock_source_t typedef enumeration). + */ +static inline void GPT_SetClockSource(GPT_Type *base, gpt_clock_source_t gptClkSource) +{ + if (gptClkSource == kGPT_ClockSource_Osc) + { + base->CR = (base->CR & ~GPT_CR_CLKSRC_MASK) | GPT_CR_EN_24M_MASK | GPT_CR_CLKSRC(gptClkSource); + } + else + { + base->CR = (base->CR & ~(GPT_CR_CLKSRC_MASK | GPT_CR_EN_24M_MASK)) | GPT_CR_CLKSRC(gptClkSource); + } +} + +/*! + * @brief Get clock source of GPT. + * + * @param base GPT peripheral base address. + * @return clock source (see @ref gpt_clock_source_t typedef enumeration). + */ +static inline gpt_clock_source_t GPT_GetClockSource(GPT_Type *base) +{ + return (gpt_clock_source_t)(uint8_t)((base->CR & GPT_CR_CLKSRC_MASK) >> GPT_CR_CLKSRC_SHIFT); +} + +/*! + * @brief Set pre scaler of GPT. + * + * @param base GPT peripheral base address. + * @param divider Divider of GPT (1-4096). + */ +static inline void GPT_SetClockDivider(GPT_Type *base, uint32_t divider) +{ + assert(divider - 1U <= GPT_PR_PRESCALER_MASK); + + base->PR = (base->PR & ~GPT_PR_PRESCALER_MASK) | GPT_PR_PRESCALER(divider - 1U); +} + +/*! + * @brief Get clock divider in GPT module. + * + * @param base GPT peripheral base address. + * @return clock divider in GPT module (1-4096). + */ +static inline uint32_t GPT_GetClockDivider(GPT_Type *base) +{ + return ((base->PR & GPT_PR_PRESCALER_MASK) >> GPT_PR_PRESCALER_SHIFT) + 1U; +} + +/*! + * @brief OSC 24M pre-scaler before selected by clock source. + * + * @param base GPT peripheral base address. + * @param divider OSC Divider(1-16). + */ +static inline void GPT_SetOscClockDivider(GPT_Type *base, uint32_t divider) +{ + assert(divider - 1U <= (GPT_PR_PRESCALER24M_MASK >> GPT_PR_PRESCALER24M_SHIFT)); + + base->PR = (base->PR & ~GPT_PR_PRESCALER24M_MASK) | GPT_PR_PRESCALER24M(divider - 1U); +} + +/*! + * @brief Get OSC 24M clock divider in GPT module. + * + * @param base GPT peripheral base address. + * @return OSC clock divider in GPT module (1-16). + */ +static inline uint32_t GPT_GetOscClockDivider(GPT_Type *base) +{ + return ((base->PR & GPT_PR_PRESCALER24M_MASK) >> GPT_PR_PRESCALER24M_SHIFT) + 1U; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ +/*! + * @brief Start GPT timer. + * + * @param base GPT peripheral base address. + */ +static inline void GPT_StartTimer(GPT_Type *base) +{ + base->CR |= GPT_CR_EN_MASK; +} + +/*! + * @brief Stop GPT timer. + * + * @param base GPT peripheral base address. + */ +static inline void GPT_StopTimer(GPT_Type *base) +{ + base->CR &= ~GPT_CR_EN_MASK; +} + +/*! + * @name Read the timer period + * @{ + */ + +/*! + * @brief Reads the current GPT counting value. + * + * @param base GPT peripheral base address. + * @return Current GPT counter value. + */ +static inline uint32_t GPT_GetCurrentTimerCount(GPT_Type *base) +{ + return base->CNT; +} + +/*@}*/ + +/*! + * @name GPT Input/Output Signal Control + * @{ + */ + +/*! + * @brief Set GPT operation mode of input capture channel. + * + * @param base GPT peripheral base address. + * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration). + * @param mode GPT input capture operation mode (see @ref gpt_input_operation_mode_t typedef enumeration). + */ +static inline void GPT_SetInputOperationMode(GPT_Type *base, + gpt_input_capture_channel_t channel, + gpt_input_operation_mode_t mode) +{ + assert(channel <= kGPT_InputCapture_Channel2); + + base->CR = + (base->CR & ~(GPT_CR_IM1_MASK << ((uint32_t)channel * 2UL))) | (GPT_CR_IM1(mode) << ((uint32_t)channel * 2UL)); +} + +/*! + * @brief Get GPT operation mode of input capture channel. + * + * @param base GPT peripheral base address. + * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration). + * @return GPT input capture operation mode (see @ref gpt_input_operation_mode_t typedef enumeration). + */ +static inline gpt_input_operation_mode_t GPT_GetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel) +{ + assert(channel <= kGPT_InputCapture_Channel2); + + return (gpt_input_operation_mode_t)(uint8_t)((base->CR >> (GPT_CR_IM1_SHIFT + (uint32_t)channel * 2UL)) & + (GPT_CR_IM1_MASK >> GPT_CR_IM1_SHIFT)); +} + +/*! + * @brief Get GPT input capture value of certain channel. + * + * @param base GPT peripheral base address. + * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration). + * @return GPT input capture value. + */ +static inline uint32_t GPT_GetInputCaptureValue(GPT_Type *base, gpt_input_capture_channel_t channel) +{ + assert(channel <= kGPT_InputCapture_Channel2); + + return base->ICR[(uint32_t)channel]; +} + +/*! + * @brief Set GPT operation mode of output compare channel. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + * @param mode GPT output operation mode (see @ref gpt_output_operation_mode_t typedef enumeration). + */ +static inline void GPT_SetOutputOperationMode(GPT_Type *base, + gpt_output_compare_channel_t channel, + gpt_output_operation_mode_t mode) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + base->CR = + (base->CR & ~(GPT_CR_OM1_MASK << ((uint32_t)channel * 3UL))) | (GPT_CR_OM1(mode) << ((uint32_t)channel * 3UL)); +} + +/*! + * @brief Get GPT operation mode of output compare channel. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + * @return GPT output operation mode (see @ref gpt_output_operation_mode_t typedef enumeration). + */ +static inline gpt_output_operation_mode_t GPT_GetOutputOperationMode(GPT_Type *base, + gpt_output_compare_channel_t channel) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + return (gpt_output_operation_mode_t)(uint8_t)((base->CR >> (GPT_CR_OM1_SHIFT + (uint32_t)channel * 3UL)) & + (GPT_CR_OM1_MASK >> GPT_CR_OM1_SHIFT)); +} + +/*! + * @brief Set GPT output compare value of output compare channel. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + * @param value GPT output compare value. + */ +static inline void GPT_SetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel, uint32_t value) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + base->OCR[(uint32_t)channel] = value; +} + +/*! + * @brief Get GPT output compare value of output compare channel. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + * @return GPT output compare value. + */ +static inline uint32_t GPT_GetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + return base->OCR[(uint32_t)channel]; +} + +/*! + * @brief Force GPT output action on output compare channel, ignoring comparator. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + */ +static inline void GPT_ForceOutput(GPT_Type *base, gpt_output_compare_channel_t channel) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + base->CR |= (GPT_CR_FO1_MASK << (uint32_t)channel); +} + +/*@}*/ + +/*! + * @name GPT Interrupt and Status Interface + * @{ + */ + +/*! + * @brief Enables the selected GPT interrupts. + * + * @param base GPT peripheral base address. + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::gpt_interrupt_enable_t + */ +static inline void GPT_EnableInterrupts(GPT_Type *base, uint32_t mask) +{ + base->IR |= mask; +} + +/*! + * @brief Disables the selected GPT interrupts. + * + * @param base GPT peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::gpt_interrupt_enable_t + */ +static inline void GPT_DisableInterrupts(GPT_Type *base, uint32_t mask) +{ + base->IR &= ~mask; +} + +/*! + * @brief Gets the enabled GPT interrupts. + * + * @param base GPT peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::gpt_interrupt_enable_t + */ +static inline uint32_t GPT_GetEnabledInterrupts(GPT_Type *base) +{ + return (base->IR & (GPT_IR_OF1IE_MASK | GPT_IR_OF2IE_MASK | GPT_IR_OF3IE_MASK | GPT_IR_IF1IE_MASK | + GPT_IR_IF2IE_MASK | GPT_IR_ROVIE_MASK)); +} + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Get GPT status flags. + * + * @param base GPT peripheral base address. + * @param flags GPT status flag mask (see @ref gpt_status_flag_t for bit definition). + * @return GPT status, each bit represents one status flag. + */ +static inline uint32_t GPT_GetStatusFlags(GPT_Type *base, gpt_status_flag_t flags) +{ + return base->SR & (uint32_t)flags; +} + +/*! + * @brief Clears the GPT status flags. + * + * @param base GPT peripheral base address. + * @param flags GPT status flag mask (see @ref gpt_status_flag_t for bit definition). + */ +static inline void GPT_ClearStatusFlags(GPT_Type *base, gpt_status_flag_t flags) +{ + base->SR = (uint32_t)flags; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_GPT_H_ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_i2c.c b/devices/MIMX8MQ6/drivers/fsl_i2c.c new file mode 100644 index 000000000..5d81474f2 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_i2c.c @@ -0,0 +1,1787 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_i2c.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ii2c" +#endif + +/*! @brief i2c transfer state. */ +enum _i2c_transfer_states +{ + kIdleState = 0x0U, /*!< I2C bus idle. */ + kCheckAddressState = 0x1U, /*!< 7-bit address check state. */ + kSendCommandState = 0x2U, /*!< Send command byte phase. */ + kSendDataState = 0x3U, /*!< Send data transfer phase. */ + kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */ + kReceiveDataState = 0x5U, /*!< Receive data transfer phase. */ +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _i2c_flag_constants +{ + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag, + kIrqFlags = kI2C_GlobalInterruptEnable, +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for I2C module. + * + * @param base I2C peripheral base address. + */ +static uint32_t I2C_GetInstance(I2C_Type *base); + +/*! + * @brief Set up master transfer, send slave address and decide the initial + * transfer state. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + */ +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Check and clear status operation. + * + * @param base I2C peripheral base address. + * @param status current i2c hardware status. + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + */ +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status); + +/*! + * @brief Master run transfer state machine to perform a byte of transfer. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + * @param isDone input param to get whether the thing is done, true is done + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); + +/*! + * @brief I2C common interrupt handler. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle); + +/*! + * @brief Wait for status ready. + * + * @param base I2C peripheral base address. + * @param statusFlag statusFlag #_i2c_flags + * @retval kStatus_I2C_Timeout Wait signal timeout. + * @retval kStatus_Success Polling flag successfully. + */ +static status_t I2C_WaitForStatusReady(I2C_Type *base, uint8_t statusFlag); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief SCL clock divider used to calculate baudrate. */ +static const uint16_t s_i2cDividerTable[] = { + 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, 160, 192, 240, + 288, 320, 384, 480, 576, 640, 768, 960, 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840, + 22, 24, 26, 28, 32, 36, 40, 44, 48, 56, 64, 72, 80, 96, 112, 128, + 160, 192, 224, 256, 320, 384, 448, 512, 640, 768, 896, 1024, 1280, 1536, 1792, 2048}; + +/*! @brief Pointers to i2c bases for each instance. */ +static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS; + +/*! @brief Pointers to i2c IRQ number for each instance. */ +static const IRQn_Type s_i2cIrqs[] = I2C_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to i2c clocks for each instance. */ +static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to i2c handles for each instance. */ +static void *s_i2cHandle[ARRAY_SIZE(s_i2cBases)]; + +/*! @brief Pointer to master IRQ handler for each instance. */ +static i2c_isr_t s_i2cMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static i2c_isr_t s_i2cSlaveIsr; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static uint32_t I2C_GetInstance(I2C_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_i2cBases); instance++) + { + if (s_i2cBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_i2cBases)); + + return instance; +} + +static status_t I2C_WaitForStatusReady(I2C_Type *base, uint8_t statusFlag) +{ +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; + /* Wait for TCF bit and manually trigger tx interrupt. */ + while ((0U == (base->I2SR & statusFlag)) && (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait for TCF bit and manually trigger tx interrupt. */ + while (0U == (base->I2SR & statusFlag)) + { + } +#endif + return kStatus_Success; +} + +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result = kStatus_Success; + i2c_direction_t direction = xfer->direction; + + /* Initialize the handle transfer information. */ + handle->transfer = *xfer; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Initial transfer state. */ + if (handle->transfer.subaddressSize > 0U) + { + if (xfer->direction == kI2C_Read) + { + direction = kI2C_Write; + } + } + + handle->state = (uint8_t)kCheckAddressState; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, (uint32_t)kClearFlags); + + /* Handle no start option. */ + if ((handle->transfer.flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) + { + /* No need to send start flag, directly go to send command or data */ + if (handle->transfer.subaddressSize > 0U) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = (uint8_t)kSendDataState; + } + else + { + /* Only support write with no stop signal. */ + return kStatus_InvalidArgument; + } + } + + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_TransferCompleteFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + I2C_MasterTransferHandleIRQ(base, handle); + } + /* If repeated start is requested, send repeated start. */ + else if ((handle->transfer.flags & (uint32_t)kI2C_TransferRepeatedStartFlag) != 0U) + { + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); + } + + return result; +} + +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check arbitration lost. */ + if ((status & (uint32_t)kI2C_ArbitrationLostFlag) != 0U) + { + /* Clear arbitration lost flag. */ + base->I2SR &= (~(uint8_t)kI2C_ArbitrationLostFlag); + + /* Reset I2C controller*/ + base->I2CR &= ~(uint16_t)I2C_I2CR_IEN_MASK; + base->I2CR |= I2C_I2CR_IEN_MASK; + + result = kStatus_I2C_ArbitrationLost; + } + /* Check NAK */ + else if ((status & (uint32_t)kI2C_ReceiveNakFlag) != 0U) + { + result = kStatus_I2C_Nak; + } + else + { + /* Avoid MISRA 2012 rule 15.7 violation */ + } + + return result; +} + +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = base->I2SR; + *isDone = false; + volatile uint8_t dummy = 0U; + bool ignoreNak = ((handle->state == (uint8_t)kSendDataState) && (handle->transfer.dataSize == 0U)) || + ((handle->state == (uint8_t)kReceiveDataState) && (handle->transfer.dataSize == 1U)); + + /* Add this to avoid build warning. */ + dummy++; + + /* Check & clear error flags. */ + result = I2C_CheckAndClearError(base, statusFlags); + + /* Ignore Nak when it's appeared for last byte. */ + if ((result == kStatus_I2C_Nak) && ignoreNak) + { + result = kStatus_Success; + } + + /* Handle Check address state to check the slave address is Acked in slave + probe application. */ + if (handle->state == (uint8_t)kCheckAddressState) + { + if ((statusFlags & (uint32_t)kI2C_ReceiveNakFlag) != 0U) + { + result = kStatus_I2C_Addr_Nak; + } + else + { + if (handle->transfer.subaddressSize > 0U) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = (uint8_t)kSendDataState; + } + else + { + /* Next state, receive data begin. */ + handle->state = (uint8_t)kReceiveDataBeginState; + } + } + } + } + + if (result != kStatus_Success) + { + return result; + } + + /* Run state machine. */ + switch (handle->state) + { + /* Send I2C command. */ + case (uint8_t)kSendCommandState: + if (handle->transfer.subaddressSize != 0U) + { + handle->transfer.subaddressSize--; + base->I2DR = (uint16_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize)); + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Send first byte of data. */ + if (handle->transfer.dataSize > 0U) + { + /* Next state, send data. */ + handle->state = (uint8_t)kSendDataState; + base->I2DR = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + *isDone = true; + } + } + else + { + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); + + /* Next state, receive data begin. */ + handle->state = (uint8_t)kReceiveDataBeginState; + } + } + break; + + /* Send I2C data. */ + case (uint8_t)kSendDataState: + /* Send one byte of data. */ + if (handle->transfer.dataSize > 0U) + { + base->I2DR = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + *isDone = true; + } + break; + + /* Start I2C data receive. */ + case (uint8_t)kReceiveDataBeginState: + base->I2CR &= ~((uint16_t)I2C_I2CR_MTX_MASK | (uint16_t)I2C_I2CR_TXAK_MASK); + + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1U) + { + base->I2CR |= I2C_I2CR_TXAK_MASK; + } + + /* Read dummy to release the bus. */ + dummy = (uint8_t)base->I2DR; + + /* Next state, receive data. */ + handle->state = (uint8_t)kReceiveDataState; + break; + + /* Receive I2C data. */ + case (uint8_t)kReceiveDataState: + /* Receive one byte of data. */ + if (0U != handle->transfer.dataSize--) + { + if (handle->transfer.dataSize == 0U) + { + *isDone = true; + + /* Send stop if kI2C_TransferNoStop is not asserted. */ + if (0U == (handle->transfer.flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + result = I2C_MasterStop(base); + } + else + { + base->I2CR |= I2C_I2CR_MTX_MASK; + } + } + + /* Send NAK at the last receive byte. */ + if (handle->transfer.dataSize == 1U) + { + base->I2CR |= I2C_I2CR_TXAK_MASK; + } + + /* Read the data byte into the transfer buffer. */ + *handle->transfer.data = (uint8_t)base->I2DR; + handle->transfer.data++; + } + break; + + default: + assert(false); + break; + } + + return result; +} + +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle) +{ + /* Check if master interrupt. */ + if (((base->I2SR & (uint8_t)kI2C_ArbitrationLostFlag) != 0U) || ((base->I2CR & (uint8_t)I2C_I2CR_MSTA_MASK) != 0U)) + { + s_i2cMasterIsr(base, handle); + } + else + { + s_i2cSlaveIsr(base, handle); + } + __DSB(); +} + +/*! + * brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and configure the I2C with master configuration. + * + * note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can be custom filled + * or it can be set with default values by using the I2C_MasterGetDefaultConfig(). + * After calling this API, the master is ready to transfer. + * This is an example. + * code + * i2c_master_config_t config = { + * .enableMaster = true, + * .baudRate_Bps = 100000 + * }; + * I2C_MasterInit(I2C0, &config, 12000000U); + * endcode + * + * param base I2C base pointer + * param masterConfig A pointer to the master configuration structure + * param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert((masterConfig != NULL) && (srcClock_Hz != 0U)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable I2C clock. */ + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the module. */ + base->IADR = 0; + base->IFDR = 0; + base->I2CR = 0; + base->I2SR = 0; + + /* Disable I2C prior to configuring it. */ + base->I2CR &= ~((uint16_t)I2C_I2CR_IEN_MASK); + + /* Clear all flags. */ + I2C_MasterClearStatusFlags(base, (uint32_t)kClearFlags); + + /* Configure baud rate. */ + I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); + + /* Enable the I2C peripheral based on the configuration. */ + base->I2CR = I2C_I2CR_IEN(masterConfig->enableMaster); +} + +/*! + * brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock. + * The I2C master module can't work unless the I2C_MasterInit is called. + * param base I2C base pointer + */ +void I2C_MasterDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Sets the I2C master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterInit(). + * Use the initialized structure unchanged in the I2C_MasterInit() or modify + * the structure before calling the I2C_MasterInit(). + * This is an example. + * code + * i2c_master_config_t config; + * I2C_MasterGetDefaultConfig(&config); + * endcode + * param masterConfig A pointer to the master configuration structure. + */ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) +{ + assert(masterConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + /* Default baud rate at 100kbps. */ + masterConfig->baudRate_Bps = 100000U; + + /* Enable the I2C peripheral. */ + masterConfig->enableMaster = true; +} + +/*! + * brief Enables I2C interrupt requests. + * + * param base I2C base pointer + * param mask interrupt source + * The parameter can be combination of the following source if defined: + * arg kI2C_GlobalInterruptEnable + * arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kI2C_GlobalInterruptEnable) != 0U) + { + base->I2CR |= I2C_I2CR_IIEN_MASK; + } +} + +/*! + * brief Disables I2C interrupt requests. + * + * param base I2C base pointer + * param mask interrupt source + * The parameter can be combination of the following source if defined: + * arg kI2C_GlobalInterruptEnable + * arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kI2C_GlobalInterruptEnable) != 0U) + { + base->I2CR &= ~(uint16_t)I2C_I2CR_IIEN_MASK; + } +} + +/*! + * brief Sets the I2C master transfer baud rate. + * + * param base I2C base pointer + * param baudRate_Bps the baud rate value in bps + * param srcClock_Hz Source clock + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t computedRate; + uint32_t absError; + uint32_t bestError = UINT32_MAX; + uint32_t bestIcr = 0u; + uint8_t i; + + /* Scan table to find best match. */ + for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(s_i2cDividerTable[0]); ++i) + { + computedRate = srcClock_Hz / s_i2cDividerTable[i]; + absError = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps); + + if (absError < bestError) + { + bestIcr = i; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0U) + { + break; + } + } + } + + /* Set frequency register based on best settings. */ + base->IFDR = I2C_IFDR_IC(bestIcr); +} + +/*! + * brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * param base I2C peripheral base pointer + * param address 7-bit slave device address. + * param direction Master transfer directions(transmit/receive). + * retval kStatus_Success Successfully send the start signal. + * retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + + /* Return an error if the bus is already in use. */ + if ((statusFlags & (uint32_t)kI2C_BusBusyFlag) != 0U) + { + result = kStatus_I2C_Busy; + } + else + { + /* Send the START signal. */ + base->I2CR |= I2C_I2CR_MSTA_MASK | I2C_I2CR_MTX_MASK; + + base->I2DR = (uint16_t)(((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +/*! + * brief Sends a REPEATED START on the I2C bus. + * + * param base I2C peripheral base pointer + * param address 7-bit slave device address. + * param direction Master transfer directions(transmit/receive). + * retval kStatus_Success Successfully send the start signal. + * retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + + /* Return an error if the bus is already in use, but not by us. */ + if (((statusFlags & (uint32_t)kI2C_BusBusyFlag) != 0U) && ((base->I2CR & (uint16_t)I2C_I2CR_MSTA_MASK) == 0U)) + { + result = kStatus_I2C_Busy; + } + else + { + /* We are already in a transfer, so send a repeated start. */ + base->I2CR |= I2C_I2CR_RSTA_MASK | I2C_I2CR_MTX_MASK; + + base->I2DR = (uint16_t)(((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +/*! + * brief Sends a STOP signal on the I2C bus. + * + * retval kStatus_Success Successfully send the stop signal. + * retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base) +{ + /* Issue the STOP command on the bus. */ + base->I2CR &= ~((uint16_t)I2C_I2CR_MSTA_MASK | (uint16_t)I2C_I2CR_MTX_MASK | (uint16_t)I2C_I2CR_TXAK_MASK); + +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; + /* Wait for IBB bit is cleared. */ + while ((0U != (base->I2SR & (uint8_t)kI2C_BusBusyFlag)) && (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait for IBB bit is cleared. */ + while (0U != (base->I2SR & (uint8_t)kI2C_BusBusyFlag)) + { + } +#endif + return kStatus_Success; +} + +/*! + * brief Performs a polling send transaction on the I2C bus. + * + * param base The I2C peripheral base pointer. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag + * to issue a stop and kI2C_TransferNoStop to not send a stop. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags) +{ + status_t result = kStatus_Success; + uint8_t statusFlags = 0; + + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_TransferCompleteFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + + /* Clear the IICIF flag. */ + base->I2SR &= ~(uint16_t)kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to transmit data. */ + base->I2CR |= I2C_I2CR_MTX_MASK; + + while (0U != txSize--) + { + /* Send a byte of data. */ + base->I2DR = *txBuff++; + + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_IntPendingFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + + statusFlags = (uint8_t)base->I2SR; + + /* Clear the IICIF flag. */ + base->I2SR &= ~(uint16_t)kI2C_IntPendingFlag; + + /* Check if arbitration lost or no acknowledgement (NAK), return failure status. */ + if ((statusFlags & (uint8_t)kI2C_ArbitrationLostFlag) != 0U) + { + base->I2SR = (uint16_t)kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + + if (((statusFlags & (uint8_t)kI2C_ReceiveNakFlag) != 0U) && (txSize != 0U)) + { + base->I2SR = (uint16_t)kI2C_ReceiveNakFlag; + result = kStatus_I2C_Nak; + } + + if (result != kStatus_Success) + { + /* Breaking out of the send loop. */ + break; + } + } + + if (((result == kStatus_Success) && (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag))) || + (result == kStatus_I2C_Nak)) + { + /* Clear the IICIF flag. */ + base->I2SR &= ~(uint16_t)kI2C_IntPendingFlag; + + /* Send stop. */ + result = I2C_MasterStop(base); + } + + return result; +} + +/*! + * brief Performs a polling receive transaction on the I2C bus. + * + * note The I2C_MasterReadBlocking function stops the bus before reading the final byte. + * Without stopping the bus prior for the final read, the bus issues another read, resulting + * in garbage data being read into the data register. + * + * param base I2C peripheral base pointer. + * param rxBuff The pointer to the data to store the received data. + * param rxSize The length in bytes of the data to be received. + * param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag + * to issue a stop and kI2C_TransferNoStop to not send a stop. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_TransferCompleteFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + + /* Clear the IICIF flag. */ + base->I2SR &= ~(uint16_t)kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to receive data. */ + base->I2CR &= ~((uint16_t)I2C_I2CR_MTX_MASK | (uint16_t)I2C_I2CR_TXAK_MASK); + + /* If rxSize equals 1, configure to send NAK. */ + if (rxSize == 1U) + { + /* Issue NACK on read. */ + base->I2CR |= I2C_I2CR_TXAK_MASK; + } + + /* Do dummy read. */ + dummy = (uint8_t)base->I2DR; + + while (0U != (rxSize--)) + { + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_IntPendingFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + + /* Clear the IICIF flag. */ + base->I2SR &= ~(uint16_t)kI2C_IntPendingFlag; + + /* Single byte use case. */ + if (rxSize == 0U) + { + if (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + /* Issue STOP command before reading last byte. */ + result = I2C_MasterStop(base); + } + else + { + /* Change direction to Tx to avoid extra clocks. */ + base->I2CR |= I2C_I2CR_MTX_MASK; + } + } + + if (rxSize == 1U) + { + /* Issue NACK on read. */ + base->I2CR |= I2C_I2CR_TXAK_MASK; + } + + /* Read from the data register. */ + *rxBuff++ = (uint8_t)base->I2DR; + } + + return result; +} + +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * param base I2C peripheral base address. + * param xfer Pointer to the transfer structure. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) +{ + assert(xfer != NULL); + + i2c_direction_t direction = xfer->direction; + status_t result = kStatus_Success; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, (uint32_t)kClearFlags); + + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_TransferCompleteFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + + /* Change to send write address when it's a read operation with command. */ + if ((xfer->subaddressSize > 0U) && (xfer->direction == kI2C_Read)) + { + direction = kI2C_Write; + } + + /* Handle no start option, only support write with no start signal. */ + if ((xfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) + { + if (direction == kI2C_Read) + { + return kStatus_InvalidArgument; + } + } + /* If repeated start is requested, send repeated start. */ + else if ((xfer->flags & (uint32_t)kI2C_TransferRepeatedStartFlag) != 0U) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, xfer->slaveAddress, direction); + } + + if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) + { + /* Return if error. */ + if (result != kStatus_Success) + { + return result; + } + + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_IntPendingFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->I2SR); + + /* Return if error. */ + if (result != kStatus_Success) + { + if (result == kStatus_I2C_Nak) + { + result = kStatus_I2C_Addr_Nak; + + (void)I2C_MasterStop(base); + } + + return result; + } + } + + /* Send subaddress. */ + if (xfer->subaddressSize != 0U) + { + do + { + /* Clear interrupt pending flag. */ + base->I2SR &= ~(uint16_t)kI2C_IntPendingFlag; + + xfer->subaddressSize--; + base->I2DR = (uint16_t)((xfer->subaddress) >> (8U * xfer->subaddressSize)); + + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_IntPendingFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->I2SR); + + if (result != kStatus_Success) + { + if (result == kStatus_I2C_Nak) + { + (void)I2C_MasterStop(base); + } + + return result; + } + + } while (xfer->subaddressSize > 0U); + + if (xfer->direction == kI2C_Read) + { + /* Clear pending flag. */ + base->I2SR &= ~(uint16_t)kI2C_IntPendingFlag; + + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read); + + /* Return if error. */ + if (result != kStatus_Success) + { + return result; + } + + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_IntPendingFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->I2SR); + + if (result != kStatus_Success) + { + if (result == kStatus_I2C_Nak) + { + result = kStatus_I2C_Addr_Nak; + + (void)I2C_MasterStop(base); + } + + return result; + } + } + } + + /* Transmit data. */ + if (xfer->direction == kI2C_Write) + { + if (xfer->dataSize > 0U) + { + /* Send Data. */ + result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + else if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + /* Send stop. */ + result = I2C_MasterStop(base); + } + else + { + /* Avoid MISRA 2012 rule 15.7 violation */ + } + } + /* Receive Data. */ + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0U)) + { + result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + + return result; +} + +/*! + * brief Initializes the I2C handle which is used in transactional functions. + * + * param base I2C base pointer. + * param handle pointer to i2c_master_handle_t structure to store the transfer state. + * param callback pointer to user callback function. + * param userData user parameter passed to the callback function. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save master interrupt handler. */ + s_i2cMasterIsr = I2C_MasterTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + (void)EnableIRQ(s_i2cIrqs[instance]); +} + +/*! + * brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * note Calling the API returns immediately after transfer initiates. The user needs + * to call I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer + * is finished. + * + * param base I2C base pointer. + * param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * param xfer pointer to i2c_master_transfer_t structure. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + + status_t result = kStatus_Success; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != (uint8_t)kIdleState) + { + result = kStatus_I2C_Busy; + } + else + { + /* Start up the master transfer state machine. */ + result = I2C_InitTransferStateMachine(base, handle, xfer); + + if (result == kStatus_Success) + { + /* Enable the I2C interrupts. */ + I2C_EnableInterrupts(base, (uint32_t)kI2C_GlobalInterruptEnable); + } + } + + return result; +} + +/*! + * brief Aborts an interrupt non-blocking transfer early. + * + * note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base I2C base pointer. + * param handle pointer to i2c_master_handle_t structure which stores the transfer state + * retval kStatus_I2C_Timeout Timeout during polling flag. + * retval kStatus_Success Successfully abort the transfer. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +{ + assert(handle != NULL); + + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_GlobalInterruptEnable); + + /* Reset the state to idle. */ + handle->state = (uint8_t)kIdleState; + + /* Send STOP signal. */ + if (handle->transfer.direction == kI2C_Read) + { + base->I2CR |= I2C_I2CR_TXAK_MASK; + + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_IntPendingFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + base->I2SR &= ~(uint16_t)kI2C_IntPendingFlag; + + base->I2CR &= ~((uint16_t)I2C_I2CR_MSTA_MASK | (uint16_t)I2C_I2CR_MTX_MASK | (uint16_t)I2C_I2CR_TXAK_MASK); + dummy = (uint8_t)base->I2DR; + } + else + { + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_IntPendingFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + base->I2SR &= ~(uint16_t)kI2C_IntPendingFlag; + base->I2CR &= ~((uint16_t)I2C_I2CR_MSTA_MASK | (uint16_t)I2C_I2CR_MTX_MASK | (uint16_t)I2C_I2CR_TXAK_MASK); + } + return kStatus_Success; +} + +/*! + * brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * param base I2C base pointer. + * param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + *count = handle->transferSize - handle->transfer.dataSize; + + return kStatus_Success; +} + +/*! + * brief Master interrupt handler. + * + * param base I2C base pointer. + * param i2cHandle pointer to i2c_master_handle_t structure. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle != NULL); + + i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle; + status_t result = kStatus_Success; + bool isDone; + + /* Clear the interrupt flag. */ + base->I2SR &= ~(uint16_t)kI2C_IntPendingFlag; + + /* Check transfer complete flag. */ + result = I2C_MasterTransferRunStateMachine(base, handle, &isDone); + + if (isDone || (result != kStatus_Success)) + { + /* Send stop command if transfer done or received Nak. */ + if ((0U == (handle->transfer.flags & (uint32_t)kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak) || + (result == kStatus_I2C_Addr_Nak)) + { + /* Ensure stop command is a need. */ + if ((base->I2CR & I2C_I2CR_MSTA_MASK) != 0U) + { + if (I2C_MasterStop(base) != kStatus_Success) + { + result = kStatus_I2C_Timeout; + } + } + } + + /* Restore handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_GlobalInterruptEnable); + + /* Call the callback function after the function has completed. */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +/*! + * brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and initialize the I2C with the slave configuration. + * + * note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can partly be set + * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user. + * This is an example. + * code + * i2c_slave_config_t config = { + * .enableSlave = true, + * .slaveAddress = 0x1DU, + * }; + * I2C_SlaveInit(I2C0, &config); + * endcode + * + * param base I2C base pointer + * param slaveConfig A pointer to the slave configuration structure + * param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable I2C clock. */ + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the module. */ + base->IADR = 0; + base->IFDR = 0; + base->I2CR = 0; + base->I2SR = 0; + + base->IADR = (uint16_t)((uint32_t)(slaveConfig->slaveAddress)) << 1U; + base->I2CR = I2C_I2CR_IEN(slaveConfig->enableSlave); +} + +/*! + * brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. + * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock. + * param base I2C base pointer + */ +void I2C_SlaveDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Sets the I2C slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveInit(). + * Modify fields of the structure before calling the I2C_SlaveInit(). + * This is an example. + * code + * i2c_slave_config_t config; + * I2C_SlaveGetDefaultConfig(&config); + * endcode + * param slaveConfig A pointer to the slave configuration structure. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + /* Enable the I2C peripheral. */ + slaveConfig->enableSlave = true; +} + +/*! + * brief Performs a polling send transaction on the I2C bus. + * + * param base The I2C peripheral base pointer. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_AddressMatchFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + + /* Read dummy to release bus. */ + dummy = (uint8_t)base->I2DR; + + result = I2C_MasterWriteBlocking(base, txBuff, txSize, (uint32_t)kI2C_TransferDefaultFlag); + + /* Switch to receive mode. */ + base->I2CR &= ~((uint16_t)I2C_I2CR_MTX_MASK | (uint16_t)I2C_I2CR_TXAK_MASK); + + /* Read dummy to release bus. */ + dummy = (uint8_t)base->I2DR; + + return result; +} + +/*! + * brief Performs a polling receive transaction on the I2C bus. + * + * param base I2C peripheral base pointer. + * param rxBuff The pointer to the data to store the received data. + * param rxSize The length in bytes of the data to be received. + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_AddressMatchFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + + /* Read dummy to release bus. */ + dummy = (uint8_t)base->I2DR; + + /* Clear the IICIF flag. */ + base->I2SR &= ~(uint16_t)kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to receive data. */ + base->I2CR &= ~((uint16_t)I2C_I2CR_MTX_MASK); + + while (0U != rxSize--) + { + if (I2C_WaitForStatusReady(base, (uint8_t)kI2C_IntPendingFlag) != kStatus_Success) + { + return kStatus_I2C_Timeout; + } + /* Clear the IICIF flag. */ + base->I2SR &= ~(uint16_t)kI2C_IntPendingFlag; + + /* Read from the data register. */ + *rxBuff++ = (uint8_t)base->I2DR; + } + return kStatus_Success; +} + +/*! + * brief Initializes the I2C handle which is used in transactional functions. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure to store the transfer state. + * param callback pointer to user callback function. + * param userData user parameter passed to the callback function. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save slave interrupt handler. */ + s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + (void)EnableIRQ(s_i2cIrqs[instance]); +} + +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval #kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) +{ + assert(handle != NULL); + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != (uint8_t)kIdleState) + { + return kStatus_I2C_Busy; + } + else + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + (void)I2C_DisableInterrupts(base, (uint32_t)kIrqFlags); + + /* Clear transfer in handle. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->state = (uint8_t)kCheckAddressState; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | (uint32_t)kI2C_SlaveTransmitEvent | (uint32_t)kI2C_SlaveReceiveEvent; + + /* Clear all flags. */ + I2C_SlaveClearStatusFlags(base, (uint32_t)kClearFlags); + + /* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I2C_EnableInterrupts(base, (uint32_t)kIrqFlags); + } + + return kStatus_Success; +} + +/*! + * brief Aborts the slave transfer. + * + * note This API can be called at any time to stop slave for handling the bus events. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) +{ + assert(handle != NULL); + + if (handle->state != (uint8_t)kIdleState) + { + /* Disable interrupts. */ + I2C_DisableInterrupts(base, (uint32_t)kIrqFlags); + + /* Reset transfer info. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Reset the state to idle. */ + handle->state = (uint8_t)kIdleState; + } +} + +/*! + * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transfer.transferredCount; + + return kStatus_Success; +} + +/*! + * brief Slave interrupt handler. + * + * param base I2C base pointer. + * param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle != NULL); + + uint32_t status; + bool doTransmit = false; + i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle; + i2c_slave_transfer_t *xfer; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + status = I2C_SlaveGetStatusFlags(base); + xfer = &(handle->transfer); + + /* Clear the interrupt flag. */ + base->I2SR &= ~(uint16_t)kI2C_IntPendingFlag; + + /* Check NAK */ + if ((status & (uint32_t)kI2C_ReceiveNakFlag) != 0U) + { + /* Set receive mode. */ + base->I2CR &= ~((uint16_t)I2C_I2CR_MTX_MASK | (uint16_t)I2C_I2CR_TXAK_MASK); + + /* Read dummy. */ + dummy = (uint8_t)base->I2DR; + + if (handle->transfer.dataSize != 0U) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_I2C_Nak; + handle->state = (uint8_t)kIdleState; + + if (((handle->eventMask & (uint32_t)xfer->event) != 0U) && (handle->callback != NULL)) + { + handle->callback(base, xfer, handle->userData); + } + } + else + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->state = (uint8_t)kIdleState; + + if (((handle->eventMask & (uint32_t)xfer->event) != 0U) && (handle->callback != NULL)) + { + handle->callback(base, xfer, handle->userData); + } + } + } + /* Check address match. */ + else if ((status & (uint32_t)kI2C_AddressMatchFlag) != 0U) + { + xfer->event = kI2C_SlaveAddressMatchEvent; + + /* Slave transmit, master reading from slave. */ + if ((status & (uint32_t)kI2C_TransferDirectionFlag) != 0U) + { + handle->state = (uint8_t)kSendDataState; + /* Change direction to send data. */ + base->I2CR |= I2C_I2CR_MTX_MASK; + + doTransmit = true; + } + else + { + handle->state = (uint8_t)kReceiveDataState; + /* Slave receive, master writing to slave. */ + base->I2CR &= ~((uint16_t)I2C_I2CR_MTX_MASK | (uint16_t)I2C_I2CR_TXAK_MASK); + + /* Read dummy to release the bus. */ + dummy = (uint8_t)base->I2DR; + } + + if (((handle->eventMask & (uint32_t)xfer->event) != 0U) && (handle->callback != NULL)) + { + handle->callback(base, xfer, handle->userData); + } + } + /* Check transfer complete flag. */ + else if ((status & (uint32_t)kI2C_TransferCompleteFlag) != 0U) + { + /* Slave transmit, master reading from slave. */ + if (handle->state == (uint8_t)kSendDataState) + { + doTransmit = true; + } + else + { + /* If we're out of data, invoke callback to get more. */ + if ((NULL == xfer->data) || (0U == xfer->dataSize)) + { + xfer->event = kI2C_SlaveReceiveEvent; + + if (handle->callback != NULL) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + /* Slave receive, master writing to slave. */ + uint8_t data = (uint8_t)base->I2DR; + + if (handle->transfer.dataSize != 0U) + { + /* Receive data. */ + *handle->transfer.data++ = data; + handle->transfer.dataSize--; + xfer->transferredCount++; + + if (0U == handle->transfer.dataSize) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->state = (uint8_t)kIdleState; + + /* Proceed receive complete event. */ + if (((handle->eventMask & (uint32_t)xfer->event) != 0U) && (handle->callback != NULL)) + { + handle->callback(base, xfer, handle->userData); + } + } + } + } + } + else + { + /* Read dummy to release bus. */ + dummy = (uint8_t)base->I2DR; + } + + /* Send data if there is the need. */ + if (doTransmit) + { + /* If we're out of data, invoke callback to get more. */ + if ((NULL == xfer->data) || (0U == xfer->dataSize)) + { + xfer->event = kI2C_SlaveTransmitEvent; + + if (handle->callback != NULL) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + if (handle->transfer.dataSize != 0U) + { + /* Send data. */ + base->I2DR = *handle->transfer.data++; + handle->transfer.dataSize--; + xfer->transferredCount++; + } + else + { + /* Switch to receive mode. */ + base->I2CR &= ~((uint16_t)I2C_I2CR_MTX_MASK | (uint16_t)I2C_I2CR_TXAK_MASK); + + /* Read dummy to release bus. */ + dummy = (uint8_t)base->I2DR; + + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->state = (uint8_t)kIdleState; + + /* Proceed txdone event. */ + if (((handle->eventMask & (uint32_t)xfer->event) != 0U) && (handle->callback != NULL)) + { + handle->callback(base, xfer, handle->userData); + } + } + } +} + +#if defined(I2C1) +void I2C1_DriverIRQHandler(void); +void I2C1_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]); +} +#endif + +#if defined(I2C2) +void I2C2_DriverIRQHandler(void); +void I2C2_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]); +} +#endif + +#if defined(I2C3) +void I2C3_DriverIRQHandler(void); +void I2C3_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]); +} +#endif + +#if defined(I2C4) +void I2C4_DriverIRQHandler(void); +void I2C4_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C4, s_i2cHandle[4]); +} +#endif + +#if defined(I2C5) +void I2C5_DriverIRQHandler(void); +void I2C5_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C5, s_i2cHandle[5]); +} +#endif + +#if defined(I2C6) +void I2C6_DriverIRQHandler(void); +void I2C6_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C6, s_i2cHandle[6]); +} +#endif diff --git a/devices/MIMX8MQ6/drivers/fsl_i2c.h b/devices/MIMX8MQ6/drivers/fsl_i2c.h new file mode 100644 index 000000000..45028e532 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_i2c.h @@ -0,0 +1,656 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2C_H_ +#define _FSL_I2C_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C driver version. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 7)) +/*@}*/ + +/*! @brief Retry times for waiting flag. */ +#ifndef I2C_RETRY_TIMES +#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief I2C status return codes. */ +enum +{ + kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0), /*!< I2C is busy with current transfer. */ + kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< Bus is Idle. */ + kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< NAK received during transfer. */ + kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */ + kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Timeout polling status flags. */ + kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_I2C, 5), /*!< NAK received during the address probe. */ +}; + +/*! + * @brief I2C peripheral flags + * + * The following status register flags can be cleared: + * - #kI2C_ArbitrationLostFlag + * - #kI2C_IntPendingFlag + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + * + */ +enum _i2c_flags +{ + kI2C_ReceiveNakFlag = I2C_I2SR_RXAK_MASK, /*!< I2C receive NAK flag. */ + kI2C_IntPendingFlag = I2C_I2SR_IIF_MASK, /*!< I2C interrupt pending flag. */ + kI2C_TransferDirectionFlag = I2C_I2SR_SRW_MASK, /*!< I2C transfer direction flag. */ + kI2C_ArbitrationLostFlag = I2C_I2SR_IAL_MASK, /*!< I2C arbitration lost flag. */ + kI2C_BusBusyFlag = I2C_I2SR_IBB_MASK, /*!< I2C bus busy flag. */ + kI2C_AddressMatchFlag = I2C_I2SR_IAAS_MASK, /*!< I2C address match flag. */ + kI2C_TransferCompleteFlag = I2C_I2SR_ICF_MASK, + /*!< I2C transfer complete flag. */ +}; + +/*! @brief I2C feature interrupt source. */ +enum _i2c_interrupt_enable +{ + kI2C_GlobalInterruptEnable = I2C_I2CR_IIEN_MASK, /*!< I2C global interrupt. */ +}; + +/*! @brief The direction of master and slave transfers. */ +typedef enum _i2c_direction +{ + kI2C_Write = 0x0U, /*!< Master transmits to the slave. */ + kI2C_Read = 0x1U, /*!< Master receives from the slave. */ +} i2c_direction_t; + +/*! @brief I2C transfer control flag. */ +enum _i2c_master_transfer_flags +{ + kI2C_TransferDefaultFlag = 0x0U, /*!< A transfer starts with a start signal, stops with a stop signal. */ + kI2C_TransferNoStartFlag = 0x1U, /*!< A transfer starts without a start signal, only support write only or + write+read with no start flag, do not support read only with no start flag. */ + kI2C_TransferRepeatedStartFlag = 0x2U, /*!< A transfer starts with a repeated start signal. */ + kI2C_TransferNoStopFlag = 0x4U, /*!< A transfer ends without a stop signal. */ +}; + +/*! @brief I2C master user configuration. */ +typedef struct _i2c_master_config +{ + bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */ + uint32_t baudRate_Bps; /*!< Baud rate configuration of I2C peripheral. */ +} i2c_master_config_t; + +/*! @brief I2C master handle typedef. */ +typedef struct _i2c_master_handle i2c_master_handle_t; + +/*! @brief I2C master transfer callback typedef. */ +typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, + i2c_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C master transfer structure. */ +typedef struct _i2c_master_transfer +{ + uint32_t flags; /*!< A transfer flag which controls the transfer. */ + uint8_t slaveAddress; /*!< 7-bit slave address. */ + i2c_direction_t direction; /*!< A transfer direction, read or write. */ + uint32_t subaddress; /*!< A sub address. Transferred MSB first. */ + uint8_t subaddressSize; /*!< A size of the command buffer. */ + uint8_t *volatile data; /*!< A transfer buffer. */ + volatile size_t dataSize; /*!< A transfer size. */ +} i2c_master_transfer_t; + +/*! @brief I2C master handle structure. */ +struct _i2c_master_handle +{ + i2c_master_transfer_t transfer; /*!< I2C master transfer copy. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< A transfer state maintained during transfer. */ + i2c_master_transfer_callback_t completionCallback; /*!< A callback function called when the transfer is finished. */ + void *userData; /*!< A callback parameter passed to the callback function. */ +}; + +/*! + * @brief Set of events sent to the callback for nonblocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to I2C_SlaveTransferNonBlocking() to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _i2c_slave_transfer_event +{ + kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kI2C_SlaveTransmitEvent = 0x02U, /*!< A callback is requested to provide data to transmit + (slave-transmitter role). */ + kI2C_SlaveReceiveEvent = 0x04U, /*!< A callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kI2C_SlaveTransmitAckEvent = 0x08U, /*!< A callback needs to either transmit an ACK or NACK. */ + kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */ + /*! A bit mask of all available events. */ + kI2C_SlaveAllEvents = + kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | kI2C_SlaveCompletionEvent, +} i2c_slave_transfer_event_t; + +/*! @brief I2C slave handle typedef. */ +typedef struct _i2c_slave_handle i2c_slave_handle_t; + +/*! @brief I2C slave user configuration. */ +typedef struct _i2c_slave_config +{ + bool enableSlave; /*!< Enables the I2C peripheral at initialization time. */ + uint16_t slaveAddress; /*!< A slave address configuration. */ +} i2c_slave_config_t; + +/*! @brief I2C slave transfer structure. */ +typedef struct _i2c_slave_transfer +{ + i2c_slave_transfer_event_t event; /*!< A reason that the callback is invoked. */ + uint8_t *volatile data; /*!< A transfer buffer. */ + volatile size_t dataSize; /*!< A transfer size. */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< A number of bytes actually transferred since the start or since the last repeated + start. */ +} i2c_slave_transfer_t; + +/*! @brief I2C slave transfer callback typedef. */ +typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData); + +/*! @brief I2C slave handle structure. */ +struct _i2c_slave_handle +{ + volatile uint8_t state; /*!< A transfer state maintained during transfer. */ + i2c_slave_transfer_t transfer; /*!< I2C slave transfer copy. */ + uint32_t eventMask; /*!< A mask of enabled events. */ + i2c_slave_transfer_callback_t callback; /*!< A callback function called at the transfer event. */ + void *userData; /*!< A callback parameter passed to the callback. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and configure the I2C with master configuration. + * + * @note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can be custom filled + * or it can be set with default values by using the I2C_MasterGetDefaultConfig(). + * After calling this API, the master is ready to transfer. + * This is an example. + * @code + * i2c_master_config_t config = { + * .enableMaster = true, + * .baudRate_Bps = 100000 + * }; + * I2C_MasterInit(I2C0, &config, 12000000U); + * @endcode + * + * @param base I2C base pointer + * @param masterConfig A pointer to the master configuration structure + * @param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock. + * The I2C master module can't work unless the I2C_MasterInit is called. + * @param base I2C base pointer + */ +void I2C_MasterDeinit(I2C_Type *base); + +/*! + * @brief Sets the I2C master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterInit(). + * Use the initialized structure unchanged in the I2C_MasterInit() or modify + * the structure before calling the I2C_MasterInit(). + * This is an example. + * @code + * i2c_master_config_t config; + * I2C_MasterGetDefaultConfig(&config); + * @endcode + * @param masterConfig A pointer to the master configuration structure. + */ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and initialize the I2C with the slave configuration. + * + * @note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can partly be set + * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user. + * This is an example. + * @code + * i2c_slave_config_t config = { + * .enableSlave = true, + * .slaveAddress = 0x1DU, + * }; + * I2C_SlaveInit(I2C0, &config); + * @endcode + * + * @param base I2C base pointer + * @param slaveConfig A pointer to the slave configuration structure + */ +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. + * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock. + * @param base I2C base pointer + */ +void I2C_SlaveDeinit(I2C_Type *base); + +/*! + * @brief Sets the I2C slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveInit(). + * Modify fields of the structure before calling the I2C_SlaveInit(). + * This is an example. + * @code + * i2c_slave_config_t config; + * I2C_SlaveGetDefaultConfig(&config); + * @endcode + * @param slaveConfig A pointer to the slave configuration structure. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); + +/*! + * @brief Enables or disables the I2C peripheral operation. + * + * @param base I2C base pointer + * @param enable Pass true to enable and false to disable the module. + */ +static inline void I2C_Enable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->I2CR |= I2C_I2CR_IEN_MASK; + } + else + { + base->I2CR &= ~(uint16_t)I2C_I2CR_IEN_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags to get the related status. + */ +static inline uint32_t I2C_MasterGetStatusFlags(I2C_Type *base) +{ + return base->I2SR; +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag. + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter can be any combination of the following values: + * @arg kI2C_ArbitrationLostFlag + * @arg kI2C_IntPendingFlag + */ +static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + base->I2SR &= (~(uint16_t)statusMask); +} + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags to get the related status. + */ +static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base) +{ + return I2C_MasterGetStatusFlags(base); +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter can be any combination of the following values: + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + I2C_MasterClearStatusFlags(base, statusMask); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask); + +/*! + * @brief Disables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask); + +/* @} */ +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the I2C master transfer baud rate. + * + * @param base I2C base pointer + * @param baudRate_Bps the baud rate value in bps + * @param srcClock_Hz Source clock + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * @retval kStatus_Success Successfully send the stop signal. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base); + +/*! + * @brief Sends a REPEATED START on the I2C bus. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag + * to issue a stop and kI2C_TransferNoStop to not send a stop. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte. + * Without stopping the bus prior for the final read, the bus issues another read, resulting + * in garbage data being read into the data register. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag + * to issue a stop and kI2C_TransferNoStop to not send a stop. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * @param base I2C peripheral base address. + * @param xfer Pointer to the transfer structure. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * @note Calling the API returns immediately after transfer initiates. The user needs + * to call I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer + * is finished. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + * @retval kStatus_I2C_Timeout Timeout during polling flag. + * @retval kStatus_Success Successfully abort the transfer. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_master_handle_t structure. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Aborts the slave transfer. + * + * @note This API can be called at any time to stop slave for handling the bus events. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Slave interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ + +#endif /* _FSL_I2C_H_*/ diff --git a/devices/MIMX8MQ6/drivers/fsl_i2c_freertos.c b/devices/MIMX8MQ6/drivers/fsl_i2c_freertos.c new file mode 100644 index 000000000..0a8335260 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_i2c_freertos.c @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i2c_freertos.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ii2c_freertos" +#endif + +static void I2C_RTOS_Callback(I2C_Type *base, i2c_master_handle_t *drv_handle, status_t status, void *userData) +{ + i2c_rtos_handle_t *handle = (i2c_rtos_handle_t *)userData; + BaseType_t reschedule; + handle->async_status = status; + (void)xSemaphoreGiveFromISR(handle->semaphore, &reschedule); + portYIELD_FROM_ISR(reschedule); +} + +/*! + * brief Initializes I2C. + * + * This function initializes the I2C module and the related RTOS context. + * + * param handle The RTOS I2C handle, the pointer to an allocated space for RTOS context. + * param base The pointer base address of the I2C instance to initialize. + * param masterConfig The configuration structure to set-up I2C in master mode. + * param srcClock_Hz The frequency of an input clock of the I2C module. + * return status of the operation. + */ +status_t I2C_RTOS_Init(i2c_rtos_handle_t *handle, + I2C_Type *base, + const i2c_master_config_t *masterConfig, + uint32_t srcClock_Hz) +{ + if (handle == NULL) + { + return kStatus_InvalidArgument; + } + + if (base == NULL) + { + return kStatus_InvalidArgument; + } + + (void)memset(handle, 0, sizeof(i2c_rtos_handle_t)); +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->mutex = xSemaphoreCreateMutexStatic(&handle->mutexBuffer); +#else + handle->mutex = xSemaphoreCreateMutex(); +#endif + if (handle->mutex == NULL) + { + return kStatus_Fail; + } +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->semaphore = xSemaphoreCreateBinaryStatic(&handle->semaphoreBuffer); +#else + handle->semaphore = xSemaphoreCreateBinary(); +#endif + if (handle->semaphore == NULL) + { + vSemaphoreDelete(handle->mutex); + return kStatus_Fail; + } + + handle->base = base; + + I2C_MasterInit(handle->base, masterConfig, srcClock_Hz); + I2C_MasterTransferCreateHandle(base, &handle->drv_handle, I2C_RTOS_Callback, (void *)handle); + + return kStatus_Success; +} + +/*! + * brief Deinitializes the I2C. + * + * This function deinitializes the I2C module and the related RTOS context. + * + * param handle The RTOS I2C handle. + */ +status_t I2C_RTOS_Deinit(i2c_rtos_handle_t *handle) +{ + I2C_MasterDeinit(handle->base); + + vSemaphoreDelete(handle->semaphore); + vSemaphoreDelete(handle->mutex); + + return kStatus_Success; +} + +/*! + * brief Performs the I2C transfer. + * + * This function performs the I2C transfer according to the data given in the transfer structure. + * + * param handle The RTOS I2C handle. + * param transfer A structure specifying the transfer parameters. + * return status of the operation. + */ +status_t I2C_RTOS_Transfer(i2c_rtos_handle_t *handle, i2c_master_transfer_t *transfer) +{ + status_t status; + + /* Lock resource mutex */ + if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) + { + return kStatus_I2C_Busy; + } + + status = I2C_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->mutex); + return status; + } + + /* Wait for transfer to finish */ + (void)xSemaphoreTake(handle->semaphore, portMAX_DELAY); + + /* Unlock resource mutex */ + (void)xSemaphoreGive(handle->mutex); + + /* Return status captured by callback function */ + return handle->async_status; +} diff --git a/devices/MIMX8MQ6/drivers/fsl_i2c_freertos.h b/devices/MIMX8MQ6/drivers/fsl_i2c_freertos.h new file mode 100644 index 000000000..3a361cdbf --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_i2c_freertos.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __FSL_I2C_FREERTOS_H__ +#define __FSL_I2C_FREERTOS_H__ + +#include "FreeRTOS.h" +#include "portable.h" +#include "semphr.h" + +#include "fsl_i2c.h" + +/*! + * @addtogroup i2c_freertos_driver I2C FreeRTOS Driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C FreeRTOS driver version. */ +#define FSL_I2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 7)) +/*@}*/ + +/*! + * @cond RTOS_PRIVATE + * @brief I2C FreeRTOS handle + */ +typedef struct _i2c_rtos_handle +{ + I2C_Type *base; /*!< I2C base address */ + i2c_master_handle_t drv_handle; /*!< A handle of the underlying driver, treated as opaque by the RTOS layer */ + status_t async_status; /*!< Transactional state of the underlying driver */ + SemaphoreHandle_t mutex; /*!< A mutex to lock the handle during a transfer */ + SemaphoreHandle_t semaphore; /*!< A semaphore to notify and unblock task when the transfer ends */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t mutexBuffer; /*!< Statically allocated memory for mutex */ + StaticSemaphore_t semaphoreBuffer; /*!< Statically allocated memory for semaphore */ +#endif +} i2c_rtos_handle_t; +/*! \endcond */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name I2C RTOS Operation + * @{ + */ + +/*! + * @brief Initializes I2C. + * + * This function initializes the I2C module and the related RTOS context. + * + * @param handle The RTOS I2C handle, the pointer to an allocated space for RTOS context. + * @param base The pointer base address of the I2C instance to initialize. + * @param masterConfig The configuration structure to set-up I2C in master mode. + * @param srcClock_Hz The frequency of an input clock of the I2C module. + * @return status of the operation. + */ +status_t I2C_RTOS_Init(i2c_rtos_handle_t *handle, + I2C_Type *base, + const i2c_master_config_t *masterConfig, + uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the I2C. + * + * This function deinitializes the I2C module and the related RTOS context. + * + * @param handle The RTOS I2C handle. + */ +status_t I2C_RTOS_Deinit(i2c_rtos_handle_t *handle); + +/*! + * @brief Performs the I2C transfer. + * + * This function performs the I2C transfer according to the data given in the transfer structure. + * + * @param handle The RTOS I2C handle. + * @param transfer A structure specifying the transfer parameters. + * @return status of the operation. + */ +status_t I2C_RTOS_Transfer(i2c_rtos_handle_t *handle, i2c_master_transfer_t *transfer); + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* __FSL_I2C_FREERTOS_H__ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_iomuxc.h b/devices/MIMX8MQ6/drivers/fsl_iomuxc.h new file mode 100644 index 000000000..c668299a3 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_iomuxc.h @@ -0,0 +1,606 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8 +#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC +#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0 +#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4 +#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8 +#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0 +#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC +#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC +#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404 +#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408 +#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C +#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410 +#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414 +#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418 +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438 +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448 +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468 +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468 +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478 +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478 +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498 +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8 +#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8 +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC +#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0 +#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4 +#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4 +#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4 +#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8 +#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8 +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8 +#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C +#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 +#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278 + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the I2C4_SDA as the pwm1_OUT: + * @code + * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0); + * @endcode + * + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param inputOnfield The pad->module input inversion_ + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT: + * @code + * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U)) + * @endcode + * + * @param muxRegister The pin mux register_ + * @param muxMode The pin mux mode_ + * @param inputRegister The select input register_ + * @param inputDaisy The input daisy_ + * @param configRegister The config register_ + * @param configValue The pin config value_ + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_mu.c b/devices/MIMX8MQ6/drivers/fsl_mu.c new file mode 100644 index 000000000..40b8dfd0f --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_mu.c @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_mu.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mu" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to mu clocks for each instance. */ +static const clock_ip_name_t s_muClocks[] = MU_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/*! @brief Pointers to mu bases for each instance. */ +static MU_Type *const s_muBases[] = MU_BASE_PTRS; + +/****************************************************************************** + * Code + *****************************************************************************/ +static uint32_t MU_GetInstance(MU_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < (sizeof(s_muBases) / sizeof(s_muBases[0])); instance++) + { + if (s_muBases[instance] == base) + { + break; + } + } + + assert(instance < (sizeof(s_muBases) / sizeof(s_muBases[0]))); + + return instance; +} + +/*! + * brief Initializes the MU module. + * + * This function enables the MU clock only. + * + * param base MU peripheral base address. + */ +void MU_Init(MU_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + (void)CLOCK_EnableClock(s_muClocks[MU_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief De-initializes the MU module. + * + * This function disables the MU clock only. + * + * param base MU peripheral base address. + */ +void MU_Deinit(MU_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + (void)CLOCK_DisableClock(s_muClocks[MU_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Blocks to send a message. + * + * This function waits until the TX register is empty and sends the message. + * + * param base MU peripheral base address. + * param regIndex TX register index. + * param msg Message to send. + */ +void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg) +{ + assert(regIndex < MU_TR_COUNT); + + /* Wait TX register to be empty. */ + while (0U == (base->SR & (((uint32_t)kMU_Tx0EmptyFlag) >> regIndex))) + { + ; /* Intentional empty while*/ + } + + base->TR[regIndex] = msg; +} + +/*! + * brief Blocks to receive a message. + * + * This function waits until the RX register is full and receives the message. + * + * param base MU peripheral base address. + * param regIndex RX register index. + * return The received message. + */ +uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex) +{ + assert(regIndex < MU_TR_COUNT); + + /* Wait RX register to be full. */ + while (0U == (base->SR & (((uint32_t)kMU_Rx0FullFlag) >> regIndex))) + { + ; /* Intentional empty while*/ + } + + return base->RR[regIndex]; +} + +/*! + * brief Blocks setting the 3-bit MU flags reflect on the other MU side. + * + * This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, + * the status flag \c kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are + * updating to the other side. After the 3-bit MU flags are updated, the status flag + * \c kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, + * the flags cannot be changed. This function waits for the MU status flag + * \c kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags. + * + * param base MU peripheral base address. + * param flags The 3-bit MU flags to set. + */ +void MU_SetFlags(MU_Type *base, uint32_t flags) +{ + /* Wait for update finished. */ + while (0U != (base->SR & ((uint32_t)MU_SR_FUP_MASK))) + { + ; /* Intentional empty while*/ + } + + MU_SetFlagsNonBlocking(base, flags); +} + +/*! + * brief Triggers interrupts to the other core. + * + * This function triggers the specific interrupts to the other core. The interrupts + * to trigger are passed in as bit mask. See \ref _mu_interrupt_trigger. + * The MU should not trigger an interrupt to the other core when the previous interrupt + * has not been processed by the other core. This function checks whether the + * previous interrupts have been processed. If not, it returns an error. + * + * code + * if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger)) + * { + * Previous general purpose interrupt 0 or general purpose interrupt 2 + * has not been processed by the other core. + * } + * endcode + * + * param base MU peripheral base address. + * param mask Bit mask of the interrupts to trigger. See _mu_interrupt_trigger. + * retval kStatus_Success Interrupts have been triggered successfully. + * retval kStatus_Fail Previous interrupts have not been accepted. + */ +status_t MU_TriggerInterrupts(MU_Type *base, uint32_t mask) +{ + status_t status = kStatus_Success; + uint32_t reg = base->CR; + + /* Previous interrupt has been accepted. */ + if (0U == (reg & mask)) + { + /* All interrupts have been accepted, trigger now. */ + reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | mask; + base->CR = reg; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +#if !(defined(FSL_FEATURE_MU_NO_RSTH) && FSL_FEATURE_MU_NO_RSTH) +/*! + * brief Boots the core at B side. + * + * This function sets the B side core's boot configuration and releases the + * core from reset. + * + * param base MU peripheral base address. + * param mode Core B boot mode. + * note Only MU side A can use this function. + */ +void MU_BootCoreB(MU_Type *base, mu_core_boot_mode_t mode) +{ +#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + /* Clean the reset de-assert pending flag. */ + base->SR = MU_SR_RDIP_MASK; +#endif + +#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) + uint32_t reg = base->CCR; + + reg = (reg & ~(MU_CCR_HR_MASK | MU_CCR_RSTH_MASK | MU_CCR_BOOT_MASK)) | MU_CCR_BOOT(mode); + + base->CCR = reg; +#else + uint32_t reg = base->CR; + + reg = (reg & ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | MU_CR_HR_MASK | MU_CR_RSTH_MASK | MU_CR_BBOOT_MASK)) | + MU_CR_BBOOT(mode); + + base->CR = reg; +#endif +} + +/*! + * brief Boots the other core. + * + * This function boots the other core with a boot configuration. + * + * param base MU peripheral base address. + * param mode The other core boot mode. + */ +void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode) +{ + /* + * MU_BootOtherCore and MU_BootCoreB are the same, MU_BootCoreB is kept + * for compatible with older platforms. + */ + MU_BootCoreB(base, mode); +} +#endif /* FSL_FEATURE_MU_NO_RSTH */ + +#if !(defined(FSL_FEATURE_MU_NO_HR) && FSL_FEATURE_MU_NO_HR) +#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) +/*! + * brief Hardware reset the other core. + * + * This function resets the other core, the other core could mask the + * hardware reset by calling ref MU_MaskHardwareReset. The hardware reset + * mask feature is only available for some platforms. + * This function could be used together with MU_BootOtherCore to control the + * other core reset workflow. + * + * Example 1: Reset the other core, and no hold reset + * code + * MU_HardwareResetOtherCore(MU_A, true, false, bootMode); + * endcode + * In this example, the core at MU side B will reset with the specified boot mode. + * + * Example 2: Reset the other core and hold it, then boot the other core later. + * code + * Here the other core enters reset, and the reset is hold + * MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare); + * Current core boot the other core when necessary. + * MU_BootOtherCore(MU_A, bootMode); + * endcode + * + * param base MU peripheral base address. + * param waitReset Wait the other core enters reset. + * - true: Wait until the other core enters reset, if the other + * core has masked the hardware reset, then this function will + * be blocked. + * - false: Don't wait the reset. + * param holdReset Hold the other core reset or not. + * - true: Hold the other core in reset, this function returns + * directly when the other core enters reset. + * - false: Don't hold the other core in reset, this function + * waits until the other core out of reset. + * param bootMode Boot mode of the other core, if p holdReset is true, this + * parameter is useless. + */ +void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode) +{ +#if (defined(FSL_FEATURE_MU_NO_RSTH) && FSL_FEATURE_MU_NO_RSTH) + /* If MU does not support hold reset, then the parameter must be false. */ + assert(false == holdReset); +#endif + uint32_t ccr = base->CCR & ~(MU_CCR_HR_MASK | MU_CCR_RSTH_MASK | MU_CCR_BOOT_MASK); + + ccr |= MU_CCR_BOOT(bootMode); + + if (holdReset) + { + ccr |= MU_CCR_RSTH_MASK; + } + + /* Clean the reset assert pending flag. */ + base->SR = (MU_SR_RAIP_MASK | MU_SR_RDIP_MASK); + + /* Set CCR[HR] to trigger hardware reset. */ + base->CCR = ccr | MU_CCR_HR_MASK; + + /* If wait the other core enters reset. */ + if (waitReset) + { + /* Wait for the other core go to reset. */ + while (0U == (base->SR & MU_SR_RAIP_MASK)) + { + ; /* Intentional empty while*/ + } + + if (!holdReset) + { + /* Clear CCR[HR]. */ + base->CCR = ccr; + + /* Wait for the other core out of reset. */ + while (0U == (base->SR & MU_SR_RDIP_MASK)) + { + ; /* Intentional empty while*/ + } + } + } +} +#else /* FSL_FEATURE_MU_HAS_CCR */ +/*! + * brief Hardware reset the other core. + * + * This function resets the other core, the other core could mask the + * hardware reset by calling ref MU_MaskHardwareReset. The hardware reset + * mask feature is only available for some platforms. + * This function could be used together with MU_BootOtherCore to control the + * other core reset workflow. + * + * Example 1: Reset the other core, and no hold reset + * code + * MU_HardwareResetOtherCore(MU_A, true, false, bootMode); + * endcode + * In this example, the core at MU side B will reset with the specified boot mode. + * + * Example 2: Reset the other core and hold it, then boot the other core later. + * code + * Here the other core enters reset, and the reset is hold + * MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare); + * Current core boot the other core when necessary. + * MU_BootOtherCore(MU_A, bootMode); + * endcode + * + * param base MU peripheral base address. + * param waitReset Wait the other core enters reset. + * - true: Wait until the other core enters reset, if the other + * core has masked the hardware reset, then this function will + * be blocked. + * - false: Don't wait the reset. + * param holdReset Hold the other core reset or not. + * - true: Hold the other core in reset, this function returns + * directly when the other core enters reset. + * - false: Don't hold the other core in reset, this function + * waits until the other core out of reset. + * param bootMode Boot mode of the other core, if p holdReset is true, this + * parameter is useless. + */ +void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode) +{ +#if (defined(FSL_FEATURE_MU_NO_RSTH) && FSL_FEATURE_MU_NO_RSTH) + /* If MU does not support hold reset, then the parameter must be false. */ + assert(false == holdReset); +#endif + uint32_t resetFlag = 0; + + uint32_t cr = base->CR & ~(MU_CR_HR_MASK | MU_CR_RSTH_MASK | MU_CR_BOOT_MASK | MU_CR_GIRn_MASK | MU_CR_NMI_MASK); + + cr |= MU_CR_BOOT(bootMode); + + if (holdReset) + { + cr |= MU_CR_RSTH_MASK; + } + +#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + resetFlag |= MU_SR_RAIP_MASK; +#endif +#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + resetFlag |= MU_SR_RDIP_MASK; +#endif + /* Clean the reset assert pending flag. */ + base->SR = resetFlag; + + /* Set CR[HR] to trigger hardware reset. */ + base->CR = cr | MU_CR_HR_MASK; + + /* If wait the other core enters reset. */ + if (waitReset) + { +#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + /* Wait for the other core go to reset. */ + while (0U == (base->SR & MU_SR_RAIP_MASK)) + { + ; /* Intentional empty while*/ + } +#endif + + if (!holdReset) + { + /* Clear CR[HR]. */ + base->CR = cr; + +#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + /* Wait for the other core out of reset. */ + while (0U == (base->SR & MU_SR_RDIP_MASK)) + { + ; /* Intentional empty while*/ + } +#endif + } + } +} +#endif /* FSL_FEATURE_MU_HAS_CCR */ +#endif /* FSL_FEATURE_MU_NO_HR */ diff --git a/devices/MIMX8MQ6/drivers/fsl_mu.h b/devices/MIMX8MQ6/drivers/fsl_mu.h new file mode 100644 index 000000000..d73216bcb --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_mu.h @@ -0,0 +1,741 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_MU_H_ +#define _FSL_MU_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mu + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/* Compatibility Macros */ +#ifndef MU_CR_NMI_MASK +#define MU_CR_NMI_MASK 0U +#endif + +#if (defined(FSL_FEATURE_MU_HAS_RESET_INT) && FSL_FEATURE_MU_HAS_RESET_INT) + +#ifndef FSL_FEATURE_MU_HAS_RESET_ASSERT_INT +#define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT 1 +#endif + +#ifndef FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT +#define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT 1 +#endif + +#endif /* FSL_FEATURE_MU_HAS_RESET_INT */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief MU driver version. */ +#define FSL_MU_DRIVER_VERSION (MAKE_VERSION(2, 0, 6)) +/*@}*/ + +/*! + * @brief MU status flags. + */ +enum _mu_status_flags +{ + kMU_Tx0EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 3U)), /*!< TX0 empty. */ + kMU_Tx1EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 2U)), /*!< TX1 empty. */ + kMU_Tx2EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 1U)), /*!< TX2 empty. */ + kMU_Tx3EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 0U)), /*!< TX3 empty. */ + + kMU_Rx0FullFlag = (1U << (MU_SR_RFn_SHIFT + 3U)), /*!< RX0 full. */ + kMU_Rx1FullFlag = (1U << (MU_SR_RFn_SHIFT + 2U)), /*!< RX1 full. */ + kMU_Rx2FullFlag = (1U << (MU_SR_RFn_SHIFT + 1U)), /*!< RX2 full. */ + kMU_Rx3FullFlag = (1U << (MU_SR_RFn_SHIFT + 0U)), /*!< RX3 full. */ + + kMU_GenInt0Flag = (1U << (MU_SR_GIPn_SHIFT + 3U)), /*!< General purpose interrupt 0 pending. */ + kMU_GenInt1Flag = (1U << (MU_SR_GIPn_SHIFT + 2U)), /*!< General purpose interrupt 0 pending. */ + kMU_GenInt2Flag = (1U << (MU_SR_GIPn_SHIFT + 1U)), /*!< General purpose interrupt 0 pending. */ + kMU_GenInt3Flag = (1U << (MU_SR_GIPn_SHIFT + 0U)), /*!< General purpose interrupt 0 pending. */ + + kMU_EventPendingFlag = MU_SR_EP_MASK, /*!< MU event pending. */ + kMU_FlagsUpdatingFlag = MU_SR_FUP_MASK, /*!< MU flags update is on-going. */ + +#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + kMU_ResetAssertInterruptFlag = MU_SR_RAIP_MASK, /*!< The other core reset assert interrupt pending. */ +#endif +#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) + kMU_ResetDeassertInterruptFlag = MU_SR_RDIP_MASK, /*!< The other core reset de-assert interrupt pending. */ +#endif + +#if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS) + kMU_OtherSideInResetFlag = MU_SR_RS_MASK, /*!< The other side is in reset. */ +#endif + +#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) + kMU_MuResetInterruptFlag = MU_SR_MURIP_MASK, /*!< The other side initializes MU reset. */ +#endif +#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) + kMU_HardwareResetInterruptFlag = MU_SR_HRIP_MASK, /*!< Current side has been hardware reset by the other side. */ +#endif +}; + +/*! + * @brief MU interrupt source to enable. + */ +enum _mu_interrupt_enable +{ + kMU_Tx0EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 3U)), /*!< TX0 empty. */ + kMU_Tx1EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 2U)), /*!< TX1 empty. */ + kMU_Tx2EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 1U)), /*!< TX2 empty. */ + kMU_Tx3EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 0U)), /*!< TX3 empty. */ + + kMU_Rx0FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 3U)), /*!< RX0 full. */ + kMU_Rx1FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 2U)), /*!< RX1 full. */ + kMU_Rx2FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 1U)), /*!< RX2 full. */ + kMU_Rx3FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 0U)), /*!< RX3 full. */ + + kMU_GenInt0InterruptEnable = (int)(1U << (MU_CR_GIEn_SHIFT + 3U)), /*!< General purpose interrupt 0. */ + kMU_GenInt1InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 2U)), /*!< General purpose interrupt 1. */ + kMU_GenInt2InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 1U)), /*!< General purpose interrupt 2. */ + kMU_GenInt3InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 0U)), /*!< General purpose interrupt 3. */ + +#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + kMU_ResetAssertInterruptEnable = MU_CR_RAIE_MASK, /*!< The other core reset assert interrupt. */ +#endif +#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + kMU_ResetDeassertInterruptEnable = MU_CR_RDIE_MASK, /*!< The other core reset de-assert interrupt. */ +#endif +#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) + kMU_MuResetInterruptEnable = MU_CR_MURIE_MASK, /*!< The other side initializes MU reset. The interrupt + is ORed with the general purpose interrupt 3. The + general purpose interrupt 3 is issued when the other side + set the MU reset and this interrupt is enabled. */ +#endif +#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) + kMU_HardwareResetInterruptEnable = MU_CR_HRIE_MASK, /*!< Current side has been hardware reset by the other side. */ +#endif +}; + +/*! + * @brief MU interrupt that could be triggered to the other core. + */ +enum _mu_interrupt_trigger +{ +#if !(defined(FSL_FEATURE_MU_NO_NMI) && FSL_FEATURE_MU_NO_NMI) + kMU_NmiInterruptTrigger = MU_CR_NMI_MASK, /*!< NMI interrupt. */ +#endif + kMU_GenInt0InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 3U)), /*!< General purpose interrupt 0. */ + kMU_GenInt1InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 2U)), /*!< General purpose interrupt 1. */ + kMU_GenInt2InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 1U)), /*!< General purpose interrupt 2. */ + kMU_GenInt3InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 0U)) /*!< General purpose interrupt 3. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name MU initialization. + * @{ + */ +/*! + * @brief Initializes the MU module. + * + * This function enables the MU clock only. + * + * @param base MU peripheral base address. + */ +void MU_Init(MU_Type *base); + +/*! + * @brief De-initializes the MU module. + * + * This function disables the MU clock only. + * + * @param base MU peripheral base address. + */ +void MU_Deinit(MU_Type *base); + +/* @} */ + +/*! + * @name MU Message + * @{ + */ + +/*! + * @brief Writes a message to the TX register. + * + * This function writes a message to the specific TX register. It does not check + * whether the TX register is empty or not. The upper layer should make sure the TX + * register is empty before calling this function. This function can be used + * in ISR for better performance. + * + * @code + * while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { } Wait for TX0 register empty. + * MU_SendMsgNonBlocking(base, 0U, MSG_VAL); Write message to the TX0 register. + * @endcode + * + * @param base MU peripheral base address. + * @param regIndex TX register index. + * @param msg Message to send. + */ +static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint32_t msg) +{ + assert(regIndex < MU_TR_COUNT); + + base->TR[regIndex] = msg; +} + +/*! + * @brief Blocks to send a message. + * + * This function waits until the TX register is empty and sends the message. + * + * @param base MU peripheral base address. + * @param regIndex TX register index. + * @param msg Message to send. + */ +void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg); + +/*! + * @brief Reads a message from the RX register. + * + * This function reads a message from the specific RX register. It does not check + * whether the RX register is full or not. The upper layer should make sure the RX + * register is full before calling this function. This function can be used + * in ISR for better performance. + * + * @code + * uint32_t msg; + * while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base))) + * { + * } Wait for the RX0 register full. + * + * msg = MU_ReceiveMsgNonBlocking(base, 0U); Read message from RX0 register. + * @endcode + * + * @param base MU peripheral base address. + * @param regIndex TX register index. + * @return The received message. + */ +static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex) +{ + assert(regIndex < MU_TR_COUNT); + + return base->RR[regIndex]; +} + +/*! + * @brief Blocks to receive a message. + * + * This function waits until the RX register is full and receives the message. + * + * @param base MU peripheral base address. + * @param regIndex RX register index. + * @return The received message. + */ +uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex); + +/* @} */ + +/*! + * @name MU Flags + * @{ + */ + +/*! + * @brief Sets the 3-bit MU flags reflect on the other MU side. + * + * This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed, + * the status flag \c kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are + * updating to the other side. After the 3-bit MU flags are updated, the status flag + * \c kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, + * the flags cannot be changed. The upper layer should make sure the status flag + * \c kMU_FlagsUpdatingFlag is cleared before calling this function. + * + * @code + * while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base)) + * { + * } Wait for previous MU flags updating. + * + * MU_SetFlagsNonBlocking(base, 0U); Set the mU flags. + * @endcode + * + * @param base MU peripheral base address. + * @param flags The 3-bit MU flags to set. + */ +static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags) +{ + uint32_t reg = base->CR; + reg = (reg & ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | MU_CR_Fn_MASK)) | MU_CR_Fn(flags); + base->CR = reg; +} + +/*! + * @brief Blocks setting the 3-bit MU flags reflect on the other MU side. + * + * This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, + * the status flag \c kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are + * updating to the other side. After the 3-bit MU flags are updated, the status flag + * \c kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, + * the flags cannot be changed. This function waits for the MU status flag + * \c kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags. + * + * @param base MU peripheral base address. + * @param flags The 3-bit MU flags to set. + */ +void MU_SetFlags(MU_Type *base, uint32_t flags); + +/*! + * @brief Gets the current value of the 3-bit MU flags set by the other side. + * + * This function gets the current 3-bit MU flags on the current side. + * + * @param base MU peripheral base address. + * @return flags Current value of the 3-bit flags. + */ +static inline uint32_t MU_GetFlags(MU_Type *base) +{ + return (base->SR & MU_SR_Fn_MASK) >> MU_SR_Fn_SHIFT; +} + +/* @} */ + +/*! + * @name Status and Interrupt. + * @{ + */ + +/*! + * @brief Gets the MU status flags. + * + * This function returns the bit mask of the MU status flags. See _mu_status_flags. + * + * @code + * uint32_t flags; + * flags = MU_GetStatusFlags(base); Get all status flags. + * if (kMU_Tx0EmptyFlag & flags) + * { + * The TX0 register is empty. Message can be sent. + * MU_SendMsgNonBlocking(base, 0U, MSG0_VAL); + * } + * if (kMU_Tx1EmptyFlag & flags) + * { + * The TX1 register is empty. Message can be sent. + * MU_SendMsgNonBlocking(base, 1U, MSG1_VAL); + * } + * @endcode + * + * @param base MU peripheral base address. + * @return Bit mask of the MU status flags, see _mu_status_flags. + */ +static inline uint32_t MU_GetStatusFlags(MU_Type *base) +{ + return (base->SR & (MU_SR_TEn_MASK | MU_SR_RFn_MASK | MU_SR_GIPn_MASK | MU_SR_EP_MASK | MU_SR_FUP_MASK +#if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS) + | MU_SR_RS_MASK +#endif +#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + | MU_SR_RAIP_MASK +#endif +#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + | MU_SR_RDIP_MASK +#endif +#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) + | MU_SR_MURIP_MASK +#endif +#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) + | MU_SR_HRIP_MASK +#endif + )); +} + +/*! + * @brief Gets the MU IRQ pending status. + * + * This function returns the bit mask of the pending MU IRQs. + * + * @param base MU peripheral base address. + * @return Bit mask of the MU IRQs pending. + */ +static inline uint32_t MU_GetInterruptsPending(MU_Type *base) +{ + uint32_t irqMask = base->CR & (MU_CR_GIEn_MASK | MU_CR_TIEn_MASK | MU_CR_RIEn_MASK); + return (base->SR & irqMask); +} + +/*! + * @brief Clears the specific MU status flags. + * + * This function clears the specific MU status flags. The flags to clear should + * be passed in as bit mask. See _mu_status_flags. + * + * @code + * Clear general interrupt 0 and general interrupt 1 pending flags. + * MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag); + * @endcode + * + * @param base MU peripheral base address. + * @param mask Bit mask of the MU status flags. See _mu_status_flags. The following + * flags are cleared by hardware, this function could not clear them. + * - kMU_Tx0EmptyFlag + * - kMU_Tx1EmptyFlag + * - kMU_Tx2EmptyFlag + * - kMU_Tx3EmptyFlag + * - kMU_Rx0FullFlag + * - kMU_Rx1FullFlag + * - kMU_Rx2FullFlag + * - kMU_Rx3FullFlag + * - kMU_EventPendingFlag + * - kMU_FlagsUpdatingFlag + * - kMU_OtherSideInResetFlag + */ +static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t mask) +{ + /* regMask is the mask of w1c status bits. */ + uint32_t regMask = MU_SR_GIPn_MASK; + +#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + regMask |= MU_SR_RAIP_MASK; +#endif +#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + regMask |= MU_SR_RDIP_MASK; +#endif + +#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) + regMask |= MU_SR_MURIP_MASK; +#endif + +#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) + regMask |= MU_SR_HRIP_MASK; +#endif + + base->SR = (mask & regMask); +} + +/*! + * @brief Enables the specific MU interrupts. + * + * This function enables the specific MU interrupts. The interrupts to enable + * should be passed in as bit mask. See _mu_interrupt_enable. + * + * @code + * Enable general interrupt 0 and TX0 empty interrupt. + * MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable); + * @endcode + * + * @param base MU peripheral base address. + * @param mask Bit mask of the MU interrupts. See _mu_interrupt_enable. + */ +static inline void MU_EnableInterrupts(MU_Type *base, uint32_t mask) +{ + uint32_t reg = base->CR; + reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | mask; + base->CR = reg; +} + +/*! + * @brief Disables the specific MU interrupts. + * + * This function disables the specific MU interrupts. The interrupts to disable + * should be passed in as bit mask. See _mu_interrupt_enable. + * + * @code + * Disable general interrupt 0 and TX0 empty interrupt. + * MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable); + * @endcode + * + * @param base MU peripheral base address. + * @param mask Bit mask of the MU interrupts. See _mu_interrupt_enable. + */ +static inline void MU_DisableInterrupts(MU_Type *base, uint32_t mask) +{ + uint32_t reg = base->CR; + reg &= ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | mask); + base->CR = reg; +} + +/*! + * @brief Triggers interrupts to the other core. + * + * This function triggers the specific interrupts to the other core. The interrupts + * to trigger are passed in as bit mask. See \ref _mu_interrupt_trigger. + * The MU should not trigger an interrupt to the other core when the previous interrupt + * has not been processed by the other core. This function checks whether the + * previous interrupts have been processed. If not, it returns an error. + * + * @code + * if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger)) + * { + * Previous general purpose interrupt 0 or general purpose interrupt 2 + * has not been processed by the other core. + * } + * @endcode + * + * @param base MU peripheral base address. + * @param mask Bit mask of the interrupts to trigger. See _mu_interrupt_trigger. + * @retval kStatus_Success Interrupts have been triggered successfully. + * @retval kStatus_Fail Previous interrupts have not been accepted. + */ +status_t MU_TriggerInterrupts(MU_Type *base, uint32_t mask); + +#if !(defined(FSL_FEATURE_MU_NO_NMI) && FSL_FEATURE_MU_NO_NMI) +/*! + * @brief Clear non-maskable interrupt (NMI) sent by the other core. + * + * This function clears non-maskable interrupt (NMI) sent by the other core. + * + * @param base MU peripheral base address. + */ +static inline void MU_ClearNmi(MU_Type *base) +{ + base->SR = MU_SR_NMIC_MASK; +} +#endif /* FSL_FEATURE_MU_NO_NMI */ + +/* @} */ + +/*! + * @name MU misc functions + * @{ + */ + +#if !(defined(FSL_FEATURE_MU_NO_RSTH) && FSL_FEATURE_MU_NO_RSTH) +/*! + * @brief Boots the core at B side. + * + * This function sets the B side core's boot configuration and releases the + * core from reset. + * + * @param base MU peripheral base address. + * @param mode Core B boot mode. + * @note Only MU side A can use this function. + */ +void MU_BootCoreB(MU_Type *base, mu_core_boot_mode_t mode); + +/*! + * @brief Holds the core reset of B side. + * + * This function causes the core of B side to be held in reset following any reset event. + * + * @param base MU peripheral base address. + * @note Only A side could call this function. + */ +static inline void MU_HoldCoreBReset(MU_Type *base) +{ +#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) + base->CCR |= MU_CCR_RSTH_MASK; +#else /* FSL_FEATURE_MU_HAS_CCR */ + uint32_t reg = base->CR; + reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_RSTH_MASK; + base->CR = reg; +#endif /* FSL_FEATURE_MU_HAS_CCR */ +} + +/*! + * @brief Boots the other core. + * + * This function boots the other core with a boot configuration. + * + * @param base MU peripheral base address. + * @param mode The other core boot mode. + */ +void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode); + +/*! + * @brief Holds the other core reset. + * + * This function causes the other core to be held in reset following any reset event. + * + * @param base MU peripheral base address. + */ +static inline void MU_HoldOtherCoreReset(MU_Type *base) +{ + /* + * MU_HoldOtherCoreReset and MU_HoldCoreBReset are the same, MU_HoldCoreBReset + * is kept for compatible with older platforms. + */ + MU_HoldCoreBReset(base); +} +#endif /* FSL_FEATURE_MU_NO_RSTH */ + +#if !(defined(FSL_FEATURE_MU_NO_MUR) && FSL_FEATURE_MU_NO_MUR) +/*! + * @brief Resets the MU for both A side and B side. + * + * This function resets the MU for both A side and B side. Before reset, it is + * recommended to interrupt processor B, because this function may affect the + * ongoing processor B programs. + * + * @param base MU peripheral base address. + * @note For some platforms, only MU side A could use this function, check + * reference manual for details. + */ +static inline void MU_ResetBothSides(MU_Type *base) +{ + uint32_t reg = base->CR; + reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_MUR_MASK; + base->CR = reg; + +#if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS) + /* Wait for the other side out of reset. */ + while (0U != (base->SR & MU_SR_RS_MASK)) + { + } +#endif /* FSL_FEATURE_MU_HAS_SR_RS */ +} +#endif /* FSL_FEATURE_MU_NO_MUR */ + +#if (defined(FSL_FEATURE_MU_HAS_HRM) && FSL_FEATURE_MU_HAS_HRM) +/*! + * @brief Mask hardware reset by the other core. + * + * The other core could call MU_HardwareResetOtherCore() to reset current core. + * To mask the reset, call this function and pass in true. + * + * @param base MU peripheral base address. + * @param mask Pass true to mask the hardware reset, pass false to unmask it. + */ +static inline void MU_MaskHardwareReset(MU_Type *base, bool mask) +{ +#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) + if (mask) + { + base->CCR |= MU_CCR_HRM_MASK; + } + else + { + base->CCR &= ~MU_CCR_HRM_MASK; + } +#else /* FSL_FEATURE_MU_HAS_CCR */ + if (mask) + { + base->CR |= MU_CR_HRM_MASK; + } + else + { + base->CR &= ~MU_CR_HRM_MASK; + } +#endif /* FSL_FEATURE_MU_HAS_CCR */ +} +#endif /* FSL_FEATURE_MU_HAS_HRM */ + +#if !(defined(FSL_FEATURE_MU_NO_HR) && FSL_FEATURE_MU_NO_HR) +/*! + * @brief Hardware reset the other core. + * + * This function resets the other core, the other core could mask the + * hardware reset by calling MU_MaskHardwareReset. The hardware reset + * mask feature is only available for some platforms. + * This function could be used together with MU_BootOtherCore to control the + * other core reset workflow. + * + * Example 1: Reset the other core, and no hold reset + * @code + * MU_HardwareResetOtherCore(MU_A, true, false, bootMode); + * @endcode + * In this example, the core at MU side B will reset with the specified boot mode. + * + * Example 2: Reset the other core and hold it, then boot the other core later. + * @code + * Here the other core enters reset, and the reset is hold + * MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare); + * Current core boot the other core when necessary. + * MU_BootOtherCore(MU_A, bootMode); + * @endcode + * + * @param base MU peripheral base address. + * @param waitReset Wait the other core enters reset. + * - true: Wait until the other core enters reset, if the other + * core has masked the hardware reset, then this function will + * be blocked. + * - false: Don't wait the reset. + * @param holdReset Hold the other core reset or not. + * - true: Hold the other core in reset, this function returns + * directly when the other core enters reset. + * - false: Don't hold the other core in reset, this function + * waits until the other core out of reset. + * @param bootMode Boot mode of the other core, if @p holdReset is true, this + * parameter is useless. + */ +void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode); +#endif /* FSL_FEATURE_MU_NO_HR */ + +#if !(defined(FSL_FEATURE_MU_NO_CLKE) && FSL_FEATURE_MU_NO_CLKE) +/*! + * @brief Enables or disables the clock on the other core. + * + * This function enables or disables the platform clock on the other core when + * that core enters a stop mode. If disabled, the platform clock for the other + * core is disabled when it enters stop mode. If enabled, the platform clock + * keeps running on the other core in stop mode, until this core also enters + * stop mode. + * + * @param base MU peripheral base address. + * @param enable Enable or disable the clock on the other core. + */ +static inline void MU_SetClockOnOtherCoreEnable(MU_Type *base, bool enable) +{ +#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) + if (enable) + { + base->CCR |= MU_CCR_CLKE_MASK; + } + else + { + base->CCR &= ~MU_CCR_CLKE_MASK; + } +#else /* FSL_FEATURE_MU_HAS_CCR */ + uint32_t reg = base->CR; + + reg &= ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK); + + if (enable) + { + reg |= MU_CR_CLKE_MASK; + } + else + { + reg &= ~MU_CR_CLKE_MASK; + } + + base->CR = reg; +#endif /* FSL_FEATURE_MU_HAS_CCR */ +} +#endif /* FSL_FEATURE_MU_NO_CLKE */ + +#if !(defined(FSL_FEATURE_MU_NO_PM) && FSL_FEATURE_MU_NO_PM) +/*! + * @brief Gets the power mode of the other core. + * + * This function gets the power mode of the other core. + * + * @param base MU peripheral base address. + * @return Power mode of the other core. + */ +static inline mu_power_mode_t MU_GetOtherCorePowerMode(MU_Type *base) +{ + uint32_t ret = (base->SR & MU_SR_PM_MASK) >> MU_SR_PM_SHIFT; + + return (mu_power_mode_t)ret; +} +#endif /* FSL_FEATURE_MU_NO_PM */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /* _FSL_MU_H_*/ diff --git a/devices/MIMX8MQ6/drivers/fsl_pwm.c b/devices/MIMX8MQ6/drivers/fsl_pwm.c new file mode 100644 index 000000000..90de0ee4b --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_pwm.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pwm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ipwm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance from the base address + * + * @param base PWM peripheral base address + * + * @return The PWM module instance + */ +static uint32_t PWM_GetInstance(PWM_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PWM bases for each instance. */ +static PWM_Type *const s_pwmBases[] = PWM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of PWM clock name. */ +static const clock_ip_name_t s_pwmClock[] = PWM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t PWM_GetInstance(PWM_Type *base) +{ + uint32_t instance; + uint32_t pwmArrayCount = (sizeof(s_pwmBases) / sizeof(s_pwmBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < pwmArrayCount; instance++) + { + if (s_pwmBases[instance] == base) + { + break; + } + } + + assert(instance < pwmArrayCount); + + return instance; +} + +/*! + * brief Ungates the PWM clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the PWM driver. + * + * param base PWM peripheral base address + * param config Pointer to user's PWM config structure. + * + * return kStatus_Success means success; else failed. + */ +status_t PWM_Init(PWM_Type *base, const pwm_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate PWM clock */ + CLOCK_EnableClock(s_pwmClock[PWM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Setup the PWM operation */ + base->PWMCR = (PWM_PWMCR_REPEAT(config->sampleRepeat) | PWM_PWMCR_PRESCALER(config->prescale) | + PWM_PWMCR_CLKSRC(config->clockSource) | PWM_PWMCR_POUTC(config->outputConfig) | + PWM_PWMCR_HCTR(config->halfWordSwap) | PWM_PWMCR_BCTR(config->byteSwap) | + PWM_PWMCR_STOPEN(config->enableStopMode) | PWM_PWMCR_DBGEN(config->enableDebugMode) | + PWM_PWMCR_WAITEN(config->enableWaitMode) | PWM_PWMCR_DOZEN(config->enableDozeMode) | + PWM_PWMCR_FWM(config->fifoWater)); + + return kStatus_Success; +} + +/*! + * brief Gate the PWM submodule clock + * + * param base PWM peripheral base address + */ +void PWM_Deinit(PWM_Type *base) +{ + /* Set clock source to none to disable counter */ + base->PWMCR &= ~(PWM_PWMCR_CLKSRC_MASK); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the PWM clock */ + CLOCK_DisableClock(s_pwmClock[PWM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Fill in the PWM config struct with the default settings + * + * The default values are: + * code + * config->enableStopMode = false; + * config->enableDozeMode = false; + * config->enableWaitMode = false; + * config->enableDozeMode = false; + * config->clockSource = kPWM_LowFrequencyClock; + * config->prescale = 0U; + * config->outputConfig = kPWM_SetAtRolloverAndClearAtcomparison; + * config->fifoWater = kPWM_FIFOWaterMark_2; + * config->sampleRepeat = kPWM_EachSampleOnce; + * config->byteSwap = kPWM_ByteNoSwap; + * config->halfWordSwap = kPWM_HalfWordNoSwap; + * endcode + * param config Pointer to user's PWM config structure. + */ +void PWM_GetDefaultConfig(pwm_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Stop mode disabled */ + config->enableStopMode = false; + /* Doze mode disabled */ + config->enableDozeMode = false; + /* Wait mode disabled */ + config->enableWaitMode = false; + /* Debug mode disabled */ + config->enableDebugMode = false; + /* Choose low frequency clock to control counter operation */ + config->clockSource = kPWM_LowFrequencyClock; + /* PWM clock devide by (config->prescale + 1) */ + config->prescale = 0U; + /* Output pin is set at rollover and cleared at comparison */ + config->outputConfig = kPWM_SetAtRolloverAndClearAtcomparison; + /* FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO */ + config->fifoWater = kPWM_FIFOWaterMark_2; + /* Use each sample once */ + config->sampleRepeat = kPWM_EachSampleOnce; + /* byte ordering remains the same */ + config->byteSwap = kPWM_ByteNoSwap; + /* Half word swapping does not take place */ + config->halfWordSwap = kPWM_HalfWordNoSwap; +} diff --git a/devices/MIMX8MQ6/drivers/fsl_pwm.h b/devices/MIMX8MQ6/drivers/fsl_pwm.h new file mode 100644 index 000000000..88ace843f --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_pwm.h @@ -0,0 +1,402 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_PWM_H_ +#define _FSL_PWM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pwm_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief PWM clock source select. */ +typedef enum _pwm_clock_source +{ + kPWM_PeripheralClock = 1U, /*!< The Peripheral clock is used as the clock */ + kPWM_HighFrequencyClock, /*!< High-frequency reference clock is used as the clock */ + kPWM_LowFrequencyClock /*!< Low-frequency reference clock(32KHz) is used as the clock */ +} pwm_clock_source_t; + +/*! + * @brief PWM FIFO water mark select. + * Sets the data level at which the FIFO empty flag will be set + */ +typedef enum _pwm_fifo_water_mark +{ + kPWM_FIFOWaterMark_1 = 0U, /*!< FIFO empty flag is set when there are more than or equal to 1 empty slots */ + kPWM_FIFOWaterMark_2, /*!< FIFO empty flag is set when there are more than or equal to 2 empty slots */ + kPWM_FIFOWaterMark_3, /*!< FIFO empty flag is set when there are more than or equal to 3 empty slots */ + kPWM_FIFOWaterMark_4 /*!< FIFO empty flag is set when there are more than or equal to 4 empty slots */ +} pwm_fifo_water_mark_t; + +/*! + * @brief PWM byte data swap select. + * It determines the byte ordering of the 16-bit data when it goes into the FIFO from the sample register. + */ +typedef enum _pwm_byte_data_swap +{ + kPWM_ByteNoSwap = 0U, /*!< byte ordering remains the same */ + kPWM_ByteSwap /*!< byte ordering is reversed */ +} pwm_byte_data_swap_t; + +/*! @brief PWM half-word data swap select. */ +typedef enum _pwm_half_word_data_swap +{ + kPWM_HalfWordNoSwap = 0U, /*!< Half word swapping does not take place */ + kPWM_HalfWordSwap /*!< Half word from write data bus are swapped */ +} pwm_half_word_data_swap_t; + +/*! @brief PWM Output Configuration */ +typedef enum _pwm_output_configuration +{ + kPWM_SetAtRolloverAndClearAtcomparison = 0U, /*!< Output pin is set at rollover and cleared at comparison */ + kPWM_ClearAtRolloverAndSetAtcomparison, /*!< Output pin is cleared at rollover and set at comparison */ + kPWM_NoConfigure /*!< PWM output is disconnected */ +} pwm_output_configuration_t; + +/*! + * @brief PWM FIFO sample repeat + * It determines the number of times each sample from the FIFO is to be used. + */ +typedef enum _pwm_sample_repeat +{ + kPWM_EachSampleOnce = 0u, /*!< Use each sample once */ + kPWM_EachSampletwice, /*!< Use each sample twice */ + kPWM_EachSampleFourTimes, /*!< Use each sample four times */ + kPWM_EachSampleEightTimes /*!< Use each sample eight times */ +} pwm_sample_repeat_t; + +/*! @brief List of PWM interrupt options */ +typedef enum _pwm_interrupt_enable +{ + kPWM_FIFOEmptyInterruptEnable = (1U << 0), /*!< This bit controls the generation of the FIFO Empty interrupt. */ + kPWM_RolloverInterruptEnable = (1U << 1), /*!< This bit controls the generation of the Rollover interrupt. */ + kPWM_CompareInterruptEnable = (1U << 2) /*!< This bit controls the generation of the Compare interrupt */ +} pwm_interrupt_enable_t; + +/*! @brief List of PWM status flags */ +typedef enum _pwm_status_flags +{ + kPWM_FIFOEmptyFlag = (1U << 3), /*!< This bit indicates the FIFO data level in comparison to the water + level set by FWM field in the control register. */ + kPWM_RolloverFlag = (1U << 4), /*!< This bit shows that a roll-over event has occurred. */ + kPWM_CompareFlag = (1U << 5), /*!< This bit shows that a compare event has occurred. */ + kPWM_FIFOWriteErrorFlag = + (1U << 6) /*!< This bit shows that an attempt has been made to write FIFO when it is full. */ +} pwm_status_flags_t; + +/*! @brief List of PWM FIFO available */ +typedef enum _pwm_fifo_available +{ + kPWM_NoDataInFIFOFlag = 0U, /*!< No data available */ + kPWM_OneWordInFIFOFlag, /*!< 1 word of data in FIFO */ + kPWM_TwoWordsInFIFOFlag, /*!< 2 word of data in FIFO */ + kPWM_ThreeWordsInFIFOFlag, /*!< 3 word of data in FIFO */ + kPWM_FourWordsInFIFOFlag /*!< 4 word of data in FIFO */ +} pwm_fifo_available_t; + +typedef struct _pwm_config +{ + bool enableStopMode; /*!< True: PWM continues to run in stop mode; + False: PWM is paused in stop mode. */ + bool enableDozeMode; /*!< True: PWM continues to run in doze mode; + False: PWM is paused in doze mode. */ + bool enableWaitMode; /*!< True: PWM continues to run in wait mode; + False: PWM is paused in wait mode. */ + bool enableDebugMode; /*!< True: PWM continues to run in debug mode; + False: PWM is paused in debug mode. */ + uint16_t prescale; /*!< Pre-scaler to divide down the clock + The prescaler value is not more than 0xFFF. Divide by (value + 1)*/ + pwm_clock_source_t clockSource; /*!< Clock source for the counter */ + pwm_output_configuration_t outputConfig; /*!< Set the mode of the PWM output on the output pin. */ + pwm_fifo_water_mark_t fifoWater; /*!< Set the data level for FIFO. */ + pwm_sample_repeat_t sampleRepeat; /*!< The number of times each sample from the FIFO is to be used. */ + pwm_byte_data_swap_t byteSwap; /*!< It determines the byte ordering of the 16-bit data when it goes into the + FIFO from the sample register. */ + pwm_half_word_data_swap_t halfWordSwap; /*!< It determines which half word data from the 32-bit IP Bus interface is + written into the lower 16 bits of the sample register. */ +} pwm_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PWM clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the PWM driver. + * + * @param base PWM peripheral base address + * @param config Pointer to user's PWM config structure. + * + * @return kStatus_Success means success; else failed. + */ +status_t PWM_Init(PWM_Type *base, const pwm_config_t *config); + +/*! + * @brief Gate the PWM submodule clock + * + * @param base PWM peripheral base address + */ +void PWM_Deinit(PWM_Type *base); + +/*! + * @brief Fill in the PWM config struct with the default settings + * + * The default values are: + * @code + * config->enableStopMode = false; + * config->enableDozeMode = false; + * config->enableWaitMode = false; + * config->enableDozeMode = false; + * config->clockSource = kPWM_LowFrequencyClock; + * config->prescale = 0U; + * config->outputConfig = kPWM_SetAtRolloverAndClearAtcomparison; + * config->fifoWater = kPWM_FIFOWaterMark_2; + * config->sampleRepeat = kPWM_EachSampleOnce; + * config->byteSwap = kPWM_ByteNoSwap; + * config->halfWordSwap = kPWM_HalfWordNoSwap; + * @endcode + * @param config Pointer to user's PWM config structure. + */ +void PWM_GetDefaultConfig(pwm_config_t *config); + +/*! @}*/ + +/*! + * @name PWM start and stop. + * @{ + */ + +/*! + * @brief Starts the PWM counter when the PWM is enabled. + * + * When the PWM is enabled, it begins a new period, the output pin is set to start a new period while + * the prescaler and counter are released and counting begins. + * + * @param base PWM peripheral base address + */ +static inline void PWM_StartTimer(PWM_Type *base) +{ + base->PWMCR |= PWM_PWMCR_EN_MASK; +} + +/*! + * @brief Stops the PWM counter when the pwm is disabled. + * + * @param base PWM peripheral base address + */ +static inline void PWM_StopTimer(PWM_Type *base) +{ + base->PWMCR &= ~(PWM_PWMCR_EN_MASK); +} + +/*! @}*/ + +/*! + * @brief Sofrware reset. + * + * PWM is reset when this bit is set to 1. It is a self clearing bit. + * Setting this bit resets all the registers to their reset values except for the STOPEN, + * DOZEN, WAITEN, and DBGEN bits in this control register. + * + * @param base PWM peripheral base address + */ +static inline void PWM_SoftwareReset(PWM_Type *base) +{ + base->PWMCR |= PWM_PWMCR_SWR_MASK; +} + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected PWM interrupts. + * + * @param base PWM peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +static inline void PWM_EnableInterrupts(PWM_Type *base, uint32_t mask) +{ + base->PWMIR |= (mask & (PWM_PWMIR_FIE_MASK | PWM_PWMIR_RIE_MASK | PWM_PWMIR_CIE_MASK)); +} + +/*! + * @brief Disables the selected PWM interrupts. + * + * @param base PWM peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +static inline void PWM_DisableInterrupts(PWM_Type *base, uint32_t mask) +{ + base->PWMIR &= ~(mask & (PWM_PWMIR_FIE_MASK | PWM_PWMIR_RIE_MASK | PWM_PWMIR_CIE_MASK)); +} + +/*! + * @brief Gets the enabled PWM interrupts. + * + * @param base PWM peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +static inline uint32_t PWM_GetEnabledInterrupts(PWM_Type *base) +{ + return base->PWMIR; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the PWM status flags. + * + * @param base PWM peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +static inline uint32_t PWM_GetStatusFlags(PWM_Type *base) +{ + uint32_t statusFlags = base->PWMSR; + + statusFlags &= (PWM_PWMSR_FE_MASK | PWM_PWMSR_ROV_MASK | PWM_PWMSR_CMP_MASK | PWM_PWMSR_FWE_MASK); + return statusFlags; +} + +/*! + * @brief Clears the PWM status flags. + * + * @param base PWM peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +static inline void PWM_clearStatusFlags(PWM_Type *base, uint32_t mask) +{ + base->PWMSR = (mask & (PWM_PWMSR_FE_MASK | PWM_PWMSR_ROV_MASK | PWM_PWMSR_CMP_MASK | PWM_PWMSR_FWE_MASK)); +} + +/*! + * @brief Gets the PWM FIFO available. + * + * @param base PWM peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pwm_fifo_available_t + */ +static inline uint32_t PWM_GetFIFOAvailable(PWM_Type *base) +{ + return (base->PWMSR & PWM_PWMSR_FIFOAV_MASK); +} + +/*! @}*/ + +/*! + * @name Sample Interface + * @{ + */ + +/*! + * @brief Sets the PWM sample value. + * + * @param base PWM peripheral base address + * @param value The sample value. This is the input to the 4x16 FIFO. The value in this register denotes + * the value of the sample being currently used. + */ +static inline void PWM_SetSampleValue(PWM_Type *base, uint32_t value) +{ + base->PWMSAR = (value & PWM_PWMSAR_SAMPLE_MASK); +} + +/*! + * @brief Gets the PWM sample value. + * + * @param base PWM peripheral base address + * + * @return The sample value. It can be read only when the PWM is enable. + */ +static inline uint32_t PWM_GetSampleValue(PWM_Type *base) +{ + return base->PWMSAR; +} + +/*! @}*/ + +/*! + * @brief Sets the PWM period value. + * + * @param base PWM peripheral base address + * @param value The period value. The PWM period register (PWM_PWMPR) determines the period of + * the PWM output signal. + * Writing 0xFFFF to this register will achieve the same result as writing 0xFFFE. + * PWMO (Hz) = PCLK(Hz) / (period +2) + */ +static inline void PWM_SetPeriodValue(PWM_Type *base, uint32_t value) +{ + base->PWMPR = (value & PWM_PWMPR_PERIOD_MASK); +} + +/*! + * @brief Gets the PWM period value. + * + * @param base PWM peripheral base address + * + * @return The period value. The PWM period register (PWM_PWMPR) determines the period of + * the PWM output signal. + */ +static inline uint32_t PWM_GetPeriodValue(PWM_Type *base) +{ + return (base->PWMPR & PWM_PWMPR_PERIOD_MASK); +} + +/*! + * @brief Gets the PWM counter value. + * + * @param base PWM peripheral base address + * + * @return The counter value. The current count value. + */ +static inline uint32_t PWM_GetCounterValue(PWM_Type *base) +{ + return (base->PWMCNR & PWM_PWMCNR_COUNT_MASK); +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PWM_H_ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_qspi.c b/devices/MIMX8MQ6/drivers/fsl_qspi.c new file mode 100644 index 000000000..10f48d2cf --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_qspi.c @@ -0,0 +1,581 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_qspi.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.qspi" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ +enum _qspi_transfer_state +{ + kQSPI_TxBusy = 0x0U, /*!< QSPI is busy */ + kQSPI_TxIdle, /*!< Transfer is done. */ + kQSPI_TxError /*!< Transfer error occurred. */ +}; + +#define QSPI_AHB_BUFFER_REG(base, index) (((volatile uint32_t *)&((base)->BUF0CR))[(index)]) + +#if (!defined(FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG)) || !FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG +#ifndef QuadSPI_SOCCR_DQS_LOOPBACK_EN_MASK +#define QuadSPI_SOCCR_DQS_LOOPBACK_EN_MASK (0x100U) +#endif + +#ifndef QuadSPI_SOCCR_DQS_LOOPBACK_FROM_PAD_MASK +#define QuadSPI_SOCCR_DQS_LOOPBACK_FROM_PAD_MASK (0x200U) +#endif + +#ifndef QuadSPI_SOCCR_DQS_PHASE_SEL_MASK +#define QuadSPI_SOCCR_DQS_PHASE_SEL_MASK (0xC00U) +#define QuadSPI_SOCCR_DQS_PHASE_SEL_SHIFT (10U) +#define QuadSPI_SOCCR_DQS_PHASE_SEL(x) \ + (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQS_PHASE_SEL_SHIFT)) & QuadSPI_SOCCR_DQS_PHASE_SEL_MASK) +#endif + +#ifndef QuadSPI_SOCCR_DQS_INV_EN_MASK +#define QuadSPI_SOCCR_DQS_INV_EN_MASK (0x1000U) +#define QuadSPI_SOCCR_DQS_INV_EN_SHIFT (12U) +#define QuadSPI_SOCCR_DQS_INV_EN(x) \ + (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQS_INV_EN_SHIFT)) & QuadSPI_SOCCR_DQS_INV_EN_MASK) +#endif + +#ifndef QuadSPI_SOCCR_DQS_IFA_DELAY_CHAIN_SEL_MASK +#define QuadSPI_SOCCR_DQS_IFA_DELAY_CHAIN_SEL_MASK (0x7F0000U) +#define QuadSPI_SOCCR_DQS_IFA_DELAY_CHAIN_SEL_SHIFT (16U) +#define QuadSPI_SOCCR_DQS_IFA_DELAY_CHAIN_SEL(x) \ + (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQS_IFA_DELAY_CHAIN_SEL_SHIFT)) & \ + QuadSPI_SOCCR_DQS_IFA_DELAY_CHAIN_SEL_MASK) +#endif +#endif /* FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Base pointer array */ +static QuadSPI_Type *const s_qspiBases[] = QuadSPI_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Clock name array */ +static const clock_ip_name_t s_qspiClock[] = QSPI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Get the instance number for QSPI. + * + * param base QSPI base pointer. + */ +uint32_t QSPI_GetInstance(QuadSPI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_qspiBases); instance++) + { + if (s_qspiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_qspiBases)); + + return instance; +} + +/*! + * brief Initializes the QSPI module and internal state. + * + * This function enables the clock for QSPI and also configures the QSPI with the + * input configure parameters. Users should call this function before any QSPI operations. + * + * param base Pointer to QuadSPI Type. + * param config QSPI configure structure. + * param srcClock_Hz QSPI source clock frequency in Hz. + */ +void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz) +{ + uint32_t i = 0; + uint32_t val = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable QSPI clock */ + CLOCK_EnableClock(s_qspiClock[QSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Do software reset to QSPI module */ + QSPI_SoftwareReset(base); + + /* Clear the FIFO region */ + QSPI_ClearFifo(base, (uint32_t)kQSPI_AllFifo); + + /* Configure QSPI */ + QSPI_Enable(base, false); + +#if !defined(FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) + /* Set qspi clock source */ + base->SOCCR = config->clockSource; + + /* Read MCR value, mask SCLKCFG field */ + val = base->MCR; + val &= ~QuadSPI_MCR_SCLKCFG_MASK; + + /* To avoid the configured baudrate exceeds the expected baudrate value, which may possibly put the + QSPI work under unsupported frequency, set the divider higher when there is reminder, use ceiling + operation, ceiling(a/b) = (a-1)/b + 1. */ + val |= QuadSPI_MCR_SCLKCFG((srcClock_Hz - 1U) / config->baudRate); + base->MCR = val; +#endif /* FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL */ + + /* Set AHB buffer size and buffer master */ + for (i = 0; i < (uint32_t)FSL_FEATURE_QSPI_AHB_BUFFER_COUNT; i++) + { + val = QuadSPI_BUF0CR_MSTRID(config->AHBbufferMaster[i]) | QuadSPI_BUF0CR_ADATSZ(config->AHBbufferSize[i] / 8U); + QSPI_AHB_BUFFER_REG(base, i) = val; + } + if (config->enableAHBbuffer3AllMaster) + { + base->BUF3CR |= QuadSPI_BUF3CR_ALLMST_MASK; + } + else + { + base->BUF3CR &= ~QuadSPI_BUF3CR_ALLMST_MASK; + } + + /* Set watermark */ + base->RBCT &= ~QuadSPI_RBCT_WMRK_MASK; + base->RBCT |= QuadSPI_RBCT_WMRK((uint32_t)config->rxWatermark - 1U); + +#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA) + base->TBCT &= ~QuadSPI_TBCT_WMRK_MASK; + base->TBCT |= QuadSPI_TBCT_WMRK((uint32_t)config->txWatermark - 1U); +#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */ + + /* Enable QSPI module */ + if (config->enableQspi) + { + QSPI_Enable(base, true); + } +} + +/*! + * brief Gets default settings for QSPI. + * + * param config QSPI configuration structure. + */ +void QSPI_GetDefaultQspiConfig(qspi_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->clockSource = 2U; + config->baudRate = 24000000U; + config->AHBbufferMaster[0] = 0xE; + config->AHBbufferMaster[1] = 0xE; + config->AHBbufferMaster[2] = 0xE; + config->enableAHBbuffer3AllMaster = true; + config->txWatermark = 8U; + config->rxWatermark = 8U; + config->enableQspi = true; +} + +/*! + * brief Deinitializes the QSPI module. + * + * Clears the QSPI state and QSPI module registers. + * param base Pointer to QuadSPI Type. + */ +void QSPI_Deinit(QuadSPI_Type *base) +{ + QSPI_Enable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_qspiClock[QSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Configures the serial flash parameter. + * + * This function configures the serial flash relevant parameters, such as the size, command, and so on. + * The flash configuration value cannot have a default value. The user needs to configure it according to the + * QSPI features. + * + * param base Pointer to QuadSPI Type. + * param config Flash configuration parameters. + */ +void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config) +{ + uint32_t address = FSL_FEATURE_QSPI_AMBA_BASE + config->flashA1Size; + uint32_t val = 0; + uint32_t i = 0; + + /* Disable module */ + QSPI_Enable(base, false); + + /* Config the serial flash size */ + base->SFA1AD = address; + address += config->flashA2Size; + base->SFA2AD = address; +#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) + address += config->flashB1Size; + base->SFB1AD = address; + address += config->flashB2Size; + base->SFB2AD = address; +#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */ + +#if !defined(FSL_FEATURE_QSPI_HAS_NO_SFACR) || (!FSL_FEATURE_QSPI_HAS_NO_SFACR) + /* Set Word Addressable feature */ + val = QuadSPI_SFACR_WA(config->enableWordAddress) | QuadSPI_SFACR_CAS(config->cloumnspace); + base->SFACR = val; +#endif /* FSL_FEATURE_QSPI_HAS_NO_SFACR */ + + /* Config look up table */ + base->LUTKEY = 0x5AF05AF0U; + base->LCKCR = 0x2U; + for (i = 0; i < (uint32_t)FSL_FEATURE_QSPI_LUT_DEPTH; i++) + { + base->LUT[i] = config->lookuptable[i]; + } + base->LUTKEY = 0x5AF05AF0U; + base->LCKCR = 0x1U; + +#if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH) + /* Config flash timing */ + val = QuadSPI_FLSHCR_TCSS(config->CSHoldTime) | QuadSPI_FLSHCR_TDH(config->dataHoldTime) | + QuadSPI_FLSHCR_TCSH(config->CSSetupTime); +#else + val = QuadSPI_FLSHCR_TCSS(config->CSHoldTime) | QuadSPI_FLSHCR_TCSH(config->CSSetupTime); +#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */ + base->FLSHCR = val; + + /* Set flash endianness */ + base->MCR &= ~QuadSPI_MCR_END_CFG_MASK; + base->MCR |= QuadSPI_MCR_END_CFG(config->endian); + + /* Enable QSPI again */ + QSPI_Enable(base, true); +} + +#if (!defined(FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG)) || !FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG +/*! + * @brief Configures the serial flash DQS parameter. + * + * This function configures the serial flash DQS relevant parameters, such as the delay chain tap number, . + * DQS shift phase, whether need to inverse and the rxc sample clock selection. + * + * @param base Pointer to QuadSPI Type. + * @param config Dqs configuration parameters. + */ +void QSPI_SetDqsConfig(QuadSPI_Type *base, qspi_dqs_config_t *config) +{ + uint32_t soccrVal; + uint32_t mcrVal; + + /* Disable module */ + QSPI_Enable(base, false); + + mcrVal = base->MCR; + + mcrVal &= ~(QuadSPI_MCR_DQS_EN_MASK | QuadSPI_MCR_DQS_LAT_EN_MASK); + /* Enable DQS. */ + mcrVal |= QuadSPI_MCR_DQS_EN_MASK; + + /* Configure DQS phase, inverse and loopback atrribute */ + soccrVal = base->SOCCR; + soccrVal &= + ~(QuadSPI_SOCCR_DQS_LOOPBACK_EN_MASK | QuadSPI_SOCCR_DQS_LOOPBACK_FROM_PAD_MASK | + QuadSPI_SOCCR_DQS_PHASE_SEL_MASK | QuadSPI_SOCCR_DQS_INV_EN_MASK | QuadSPI_SOCCR_DQS_IFA_DELAY_CHAIN_SEL_MASK +#if defined(QuadSPI_SOCCR_DQS_IFB_DELAY_CHAIN_SEL_MASK) + | QuadSPI_SOCCR_DQS_IFB_DELAY_CHAIN_SEL_MASK +#endif + ); + soccrVal |= QuadSPI_SOCCR_DQS_PHASE_SEL(config->shift); + + switch (config->rxSampleClock) + { + case kQSPI_ReadSampleClkInternalLoopback: + soccrVal |= QuadSPI_SOCCR_DQS_LOOPBACK_EN_MASK; + break; + case kQSPI_ReadSampleClkExternalInputFromDqsPad: + mcrVal |= QuadSPI_MCR_DQS_LAT_EN_MASK; + break; + case kQSPI_ReadSampleClkLoopbackFromDqsPad: + soccrVal |= QuadSPI_SOCCR_DQS_LOOPBACK_FROM_PAD_MASK; + break; + default: + assert(false); + break; + } + + soccrVal |= (QuadSPI_SOCCR_DQS_INV_EN(config->enableDQSClkInverse) | + QuadSPI_SOCCR_DQS_IFA_DELAY_CHAIN_SEL(config->portADelayTapNum) +#if defined(QuadSPI_SOCCR_DQS_IFB_DELAY_CHAIN_SEL_MASK) + | QuadSPI_SOCCR_DQS_IFB_DELAY_CHAIN_SEL(config->portBDelayTapNum) +#endif + ); + + base->MCR = mcrVal; + base->SOCCR = soccrVal; + + /* Enable QSPI again */ + QSPI_Enable(base, true); +} +#endif /* FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG */ + +/*! + * brief Software reset for the QSPI logic. + * + * This function sets the software reset flags for both AHB and buffer domain and + * resets both AHB buffer and also IP FIFOs. + * + * param base Pointer to QuadSPI Type. + */ +void QSPI_SoftwareReset(QuadSPI_Type *base) +{ + uint32_t i = 0; + + /* Reset AHB domain and buffer domian */ + base->MCR |= (QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK); + /* Clear buffer generic configuration. */ + base->BFGENCR = 0x00U; + + /* Wait several time for the reset to finish, this method came from IC team */ + for (i = 0; i < 100U; i++) + { + __NOP(); + } + + /* Disable QSPI module */ + QSPI_Enable(base, false); + + /* Clear the reset flags */ + base->MCR &= ~(QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK); + + /* Enable QSPI module */ + QSPI_Enable(base, true); +} + +/*! + * brief Gets the Rx data register address used for DMA operation. + * + * This function returns the Rx data register address or Rx buffer address + * according to the Rx read area settings. + * + * param base Pointer to QuadSPI Type. + * return QSPI Rx data register address. + */ +uint32_t QSPI_GetRxDataRegisterAddress(QuadSPI_Type *base) +{ + /* From RDBR */ + if (0U != (base->RBCT & QuadSPI_RBCT_RXBRD_MASK)) + { + return (uint32_t)(&(base->RBDR[0])); + } + else + { + /* From ARDB */ + return FSL_FEATURE_QSPI_ARDB_BASE; + } +} + +/*! brief Executes IP commands located in LUT table. + * + * param base Pointer to QuadSPI Type. + * param index IP command located in which LUT table index. + */ +void QSPI_ExecuteIPCommand(QuadSPI_Type *base, uint32_t index) +{ + while (0U != (QSPI_GetStatusFlags(base) & ((uint32_t)kQSPI_Busy | (uint32_t)kQSPI_IPAccess))) + { + } + QSPI_ClearCommandSequence(base, kQSPI_IPSeq); + + /* Write the seqid bit */ + base->IPCR = ((base->IPCR & (~QuadSPI_IPCR_SEQID_MASK)) | QuadSPI_IPCR_SEQID(index / 4U)); +} + +/*! brief Executes AHB commands located in LUT table. + * + * param base Pointer to QuadSPI Type. + * param index AHB command located in which LUT table index. + */ +void QSPI_ExecuteAHBCommand(QuadSPI_Type *base, uint32_t index) +{ + while (0U != (QSPI_GetStatusFlags(base) & ((uint32_t)kQSPI_Busy | (uint32_t)kQSPI_AHBAccess))) + { + } + QSPI_ClearCommandSequence(base, kQSPI_BufferSeq); + base->BFGENCR = ((base->BFGENCR & (~QuadSPI_BFGENCR_SEQID_MASK)) | QuadSPI_BFGENCR_SEQID(index / 4U)); +} + +/*! brief Updates the LUT table. + * + * param base Pointer to QuadSPI Type. + * param index Which LUT index needs to be located. It should be an integer divided by 4. + * param cmd Command sequence array. + */ +void QSPI_UpdateLUT(QuadSPI_Type *base, uint32_t index, uint32_t *cmd) +{ + uint8_t i = 0; + + /* Unlock the LUT */ + base->LUTKEY = 0x5AF05AF0U; + base->LCKCR = 0x2U; + + /* Write data into LUT */ + for (i = 0; i < 4U; i++) + { + base->LUT[index + i] = *cmd; + cmd++; + } + + /* Lcok LUT again */ + base->LUTKEY = 0x5AF05AF0U; + base->LCKCR = 0x1U; +} + +#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) + +/*! brief Clears the QSPI cache. + * + * param base Pointer to QuadSPI Type. + */ +void QSPI_ClearCache(QuadSPI_Type *base) +{ + uint32_t soccrVal; + + soccrVal = base->SOCCR; + /* Write 1 to clear cache. */ + base->SOCCR = (soccrVal | QuadSPI_SOCCR_CLR_LPCAC_MASK); + + /* Write 0 to after cache is cleared. */ + base->SOCCR = (soccrVal & (~QuadSPI_SOCCR_CLR_LPCAC_MASK)); +} +#endif + +/*! brief Set the RX buffer readout area. + * + * This function can set the RX buffer readout, from AHB bus or IP Bus. + * param base QSPI base address. + * param area QSPI Rx buffer readout area. AHB bus buffer or IP bus buffer. + */ +void QSPI_SetReadDataArea(QuadSPI_Type *base, qspi_read_area_t area) +{ + base->RBCT &= ~QuadSPI_RBCT_RXBRD_MASK; + base->RBCT |= QuadSPI_RBCT_RXBRD(area); +} + +/*! + * brief Receives data from data FIFO. + * + * param base QSPI base pointer + * return The data in the FIFO. + */ +uint32_t QSPI_ReadData(QuadSPI_Type *base) +{ + if (0U != (base->RBCT & QuadSPI_RBCT_RXBRD_MASK)) + { + return base->RBDR[0]; + } + else + { + /* Data from ARDB. */ + return *((uint32_t *)FSL_FEATURE_QSPI_ARDB_BASE); + } +} + +/*! + * brief Sends a buffer of data bytes using a blocking method. + * note This function blocks via polling until all bytes have been sent. + * param base QSPI base pointer + * param buffer The data bytes to send + * param size The number of data bytes to send + */ +void QSPI_WriteBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size) +{ + assert(size >= 16U); + + uint32_t i = 0; + + for (i = 0; i < size / 4U; i++) + { + /* Check if the buffer is full */ + while (0U != (QSPI_GetStatusFlags(base) & (uint32_t)kQSPI_TxBufferFull)) + { + } + base->TBDR = *buffer++; + } +} + +/*! + * brief Receives a buffer of data bytes using a blocking method. + * note This function blocks via polling until all bytes have been sent. Users shall notice that + * this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers. + * For flash contents read, please use AHB bus read, this is much more efficiency. + * + * param base QSPI base pointer + * param buffer The data bytes to send + * param size The number of data bytes to receive + */ +void QSPI_ReadBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size) +{ + uint32_t i = 0; + uint32_t j = 0; + uint32_t temp = 0; + uint32_t level = (base->RBCT & QuadSPI_RBCT_WMRK_MASK) + 1U; + + while (i < size / 4U) + { + /* Check if there is data */ + if ((size / 4U - i) < level) + { + do + { + temp = (base->RBSR & QuadSPI_RBSR_RDBFL_MASK) >> QuadSPI_RBSR_RDBFL_SHIFT; + } while (0U == temp); + } + else + { + while ((QSPI_GetStatusFlags(base) & (uint32_t)kQSPI_RxWatermark) == 0U) + { + } + } + + level = (level < (size / 4U - i)) ? level : (size / 4U - i); + + /* Data from RBDR */ + if (0U != (base->RBCT & QuadSPI_RBCT_RXBRD_MASK)) + { + for (j = 0; j < level; j++) + { + buffer[i + j] = base->RBDR[j]; + } + } + else + { + /* Data from ARDB. */ + for (j = 0; j < level; j++) + { + buffer[i + j] = ((uint32_t *)FSL_FEATURE_QSPI_ARDB_BASE)[j]; + } + } + i += level; + + /* Clear the Buffer */ + QSPI_ClearErrorFlag(base, (uint32_t)kQSPI_RxBufferDrain); + } +} diff --git a/devices/MIMX8MQ6/drivers/fsl_qspi.h b/devices/MIMX8MQ6/drivers/fsl_qspi.h new file mode 100644 index 000000000..5a7e5dcfd --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_qspi.h @@ -0,0 +1,751 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_QSPI_H_ +#define _FSL_QSPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup qspi_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief QSPI driver version 2.2.3. */ +#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) +/*@}*/ + +/*! @brief Macro functions for LUT table */ +#define QSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (QuadSPI_LUT_INSTR0(cmd0) | QuadSPI_LUT_PAD0(pad0) | QuadSPI_LUT_OPRND0(op0) | QuadSPI_LUT_INSTR1(cmd1) | \ + QuadSPI_LUT_PAD1(pad1) | QuadSPI_LUT_OPRND1(op1)) + +/*! @brief Macro for QSPI LUT command */ +#define QSPI_CMD (0x1U) +#define QSPI_ADDR (0x2U) +#define QSPI_DUMMY (0x3U) +#define QSPI_MODE (0x4U) +#define QSPI_MODE2 (0x5U) +#define QSPI_MODE4 (0x6U) +#define QSPI_READ (0x7U) +#define QSPI_WRITE (0x8U) +#define QSPI_JMP_ON_CS (0x9U) +#define QSPI_ADDR_DDR (0xAU) +#define QSPI_MODE_DDR (0xBU) +#define QSPI_MODE2_DDR (0xCU) +#define QSPI_MODE4_DDR (0xDU) +#define QSPI_READ_DDR (0xEU) +#define QSPI_WRITE_DDR (0xFU) +#define QSPI_DATA_LEARN (0x10U) +#define QSPI_CMD_DDR (0x11U) +#define QSPI_CADDR (0x12U) +#define QSPI_CADDR_DDR (0x13U) +#define QSPI_STOP (0x0U) + +/*! @brief Macro for QSPI PAD */ +#define QSPI_PAD_1 (0x0U) +#define QSPI_PAD_2 (0x1U) +#define QSPI_PAD_4 (0x2U) +#define QSPI_PAD_8 (0x3U) + +/*! @brief Status structure of QSPI.*/ +enum +{ + kStatus_QSPI_Idle = MAKE_STATUS(kStatusGroup_QSPI, 0), /*!< QSPI is in idle state */ + kStatus_QSPI_Busy = MAKE_STATUS(kStatusGroup_QSPI, 1), /*!< QSPI is busy */ + kStatus_QSPI_Error = MAKE_STATUS(kStatusGroup_QSPI, 2), /*!< Error occurred during QSPI transfer */ +}; + +/*! @brief QSPI read data area, from IP FIFO or AHB buffer.*/ +typedef enum _qspi_read_area +{ + kQSPI_ReadAHB = 0x0U, /*!< QSPI read from AHB buffer. */ + kQSPI_ReadIP /*!< QSPI read from IP FIFO. */ +} qspi_read_area_t; + +/*! @brief QSPI command sequence type */ +typedef enum _qspi_command_seq +{ + kQSPI_IPSeq = QuadSPI_SPTRCLR_IPPTRC_MASK, /*!< IP command sequence */ + kQSPI_BufferSeq = QuadSPI_SPTRCLR_BFPTRC_MASK, /*!< Buffer command sequence */ + kQSPI_AllSeq = QuadSPI_SPTRCLR_IPPTRC_MASK | QuadSPI_SPTRCLR_BFPTRC_MASK /* All command sequence */ +} qspi_command_seq_t; + +/*! @brief QSPI buffer type */ +typedef enum _qspi_fifo +{ + kQSPI_TxFifo = QuadSPI_MCR_CLR_TXF_MASK, /*!< QSPI Tx FIFO */ + kQSPI_RxFifo = QuadSPI_MCR_CLR_RXF_MASK, /*!< QSPI Rx FIFO */ + kQSPI_AllFifo = QuadSPI_MCR_CLR_TXF_MASK | QuadSPI_MCR_CLR_RXF_MASK /*!< QSPI all FIFO, including Tx and Rx */ +} qspi_fifo_t; + +/*! @brief QSPI transfer endianess*/ +typedef enum _qspi_endianness +{ + kQSPI_64BigEndian = 0x0U, /*!< 64 bits big endian */ + kQSPI_32LittleEndian, /*!< 32 bit little endian */ + kQSPI_32BigEndian, /*!< 32 bit big endian */ + kQSPI_64LittleEndian /*!< 64 bit little endian */ +} qspi_endianness_t; + +/*! @brief QSPI error flags */ +enum _qspi_error_flags +{ + kQSPI_DataLearningFail = (int)QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */ + kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, /*!< Tx buffer fill flag */ + kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, /*!< Tx buffer underrun flag */ + kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */ + kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, /*!< Rx buffer overflow flag */ + kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, /*!< Rx buffer drain flag */ + kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */ +#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF) + kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK, /*!< AHB illegal transaction error flag */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */ +#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF) + kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */ + kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, /*!< AHB buffer overflow flag */ +#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) + kQSPI_IPCommandUsageError = QuadSPI_FR_IUEF_MASK, /*!< IP command usage error flag */ +#endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */ + kQSPI_IPCommandTriggerDuringAHBAccess = QuadSPI_FR_IPAEF_MASK, /*!< IP command trigger during AHB access error */ + kQSPI_IPCommandTriggerDuringIPAccess = QuadSPI_FR_IPIEF_MASK, /*!< IP command trigger cannot be executed */ + kQSPI_IPCommandTriggerDuringAHBGrant = QuadSPI_FR_IPGEF_MASK, /*!< IP command trigger during AHB grant error */ + kQSPI_IPCommandTransactionFinished = QuadSPI_FR_TFF_MASK, /*!< IP command transaction finished flag */ + kQSPI_FlagAll = (int)0x8C83F8D1U /*!< All error flag */ +}; + +/*! @brief QSPI state bit */ +enum _qspi_flags +{ + kQSPI_DataLearningSamplePoint = (int)QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */ + kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK, /*!< Tx buffer full flag */ +#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA) + kQSPI_TxDMA = QuadSPI_SR_TXDMA_MASK, /*!< Tx DMA is requested or running */ + kQSPI_TxWatermark = QuadSPI_SR_TXWA_MASK, /*!< Tx buffer watermark available */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */ + kQSPI_TxBufferEnoughData = QuadSPI_SR_TXEDA_MASK, /*!< Tx buffer enough data available */ + kQSPI_RxDMA = QuadSPI_SR_RXDMA_MASK, /*!< Rx DMA is requesting or running */ + kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK, /*!< Rx buffer full */ + kQSPI_RxWatermark = QuadSPI_SR_RXWE_MASK, /*!< Rx buffer watermark exceeded */ + kQSPI_AHB3BufferFull = QuadSPI_SR_AHB3FUL_MASK, /*!< AHB buffer 3 full*/ + kQSPI_AHB2BufferFull = QuadSPI_SR_AHB2FUL_MASK, /*!< AHB buffer 2 full */ + kQSPI_AHB1BufferFull = QuadSPI_SR_AHB1FUL_MASK, /*!< AHB buffer 1 full */ + kQSPI_AHB0BufferFull = QuadSPI_SR_AHB0FUL_MASK, /*!< AHB buffer 0 full */ + kQSPI_AHB3BufferNotEmpty = QuadSPI_SR_AHB3NE_MASK, /*!< AHB buffer 3 not empty */ + kQSPI_AHB2BufferNotEmpty = QuadSPI_SR_AHB2NE_MASK, /*!< AHB buffer 2 not empty */ + kQSPI_AHB1BufferNotEmpty = QuadSPI_SR_AHB1NE_MASK, /*!< AHB buffer 1 not empty */ + kQSPI_AHB0BufferNotEmpty = QuadSPI_SR_AHB0NE_MASK, /*!< AHB buffer 0 not empty */ + kQSPI_AHBTransactionPending = QuadSPI_SR_AHBTRN_MASK, /*!< AHB access transaction pending */ + kQSPI_AHBCommandPriorityGranted = QuadSPI_SR_AHBGNT_MASK, /*!< AHB command priority granted */ + kQSPI_AHBAccess = QuadSPI_SR_AHB_ACC_MASK, /*!< AHB access */ + kQSPI_IPAccess = QuadSPI_SR_IP_ACC_MASK, /*!< IP access */ + kQSPI_Busy = QuadSPI_SR_BUSY_MASK, /*!< Module busy */ + kQSPI_StateAll = (int)0xEF897FE7U /*!< All flags */ +}; + +/*! @brief QSPI interrupt enable */ +enum _qspi_interrupt_enable +{ + kQSPI_DataLearningFailInterruptEnable = + (int)QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */ + kQSPI_TxBufferFillInterruptEnable = QuadSPI_RSER_TBFIE_MASK, /*!< Tx buffer fill interrupt enable */ + kQSPI_TxBufferUnderrunInterruptEnable = QuadSPI_RSER_TBUIE_MASK, /*!< Tx buffer underrun interrupt enable */ + kQSPI_IllegalInstructionInterruptEnable = + QuadSPI_RSER_ILLINIE_MASK, /*!< Illegal instruction error interrupt enable */ + kQSPI_RxBufferOverflowInterruptEnable = QuadSPI_RSER_RBOIE_MASK, /*!< Rx buffer overflow interrupt enable */ + kQSPI_RxBufferDrainInterruptEnable = QuadSPI_RSER_RBDIE_MASK, /*!< Rx buffer drain interrupt enable */ + kQSPI_AHBSequenceErrorInterruptEnable = QuadSPI_RSER_ABSEIE_MASK, /*!< AHB sequence error interrupt enable */ +#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF) + kQSPI_AHBIllegalTransactionInterruptEnable = + QuadSPI_RSER_AITIE_MASK, /*!< AHB illegal transaction error interrupt enable */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */ +#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF) + kQSPI_AHBIllegalBurstSizeInterruptEnable = + QuadSPI_RSER_AIBSIE_MASK, /*!< AHB illegal burst error interrupt enable */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */ + kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, /*!< AHB buffer overflow interrupt enable */ +#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) + kQSPI_IPCommandUsageErrorInterruptEnable = QuadSPI_RSER_IUEIE_MASK, /*!< IP command usage error interrupt enable */ +#endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */ + kQSPI_IPCommandTriggerDuringAHBAccessInterruptEnable = + QuadSPI_RSER_IPAEIE_MASK, /*!< IP command trigger during AHB access error */ + kQSPI_IPCommandTriggerDuringIPAccessInterruptEnable = + QuadSPI_RSER_IPIEIE_MASK, /*!< IP command trigger cannot be executed */ + kQSPI_IPCommandTriggerDuringAHBGrantInterruptEnable = + QuadSPI_RSER_IPGEIE_MASK, /*!< IP command trigger during AHB grant error */ + kQSPI_IPCommandTransactionFinishedInterruptEnable = + QuadSPI_RSER_TFIE_MASK, /*!< IP command transaction finished interrupt enable */ + kQSPI_AllInterruptEnable = (int)0x8C83F8D1U /*!< All error interrupt enable */ +}; + +/*! @brief QSPI DMA request flag */ +enum _qspi_dma_enable +{ +#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA) + kQSPI_TxBufferFillDMAEnable = QuadSPI_RSER_TBFDE_MASK, /*!< Tx buffer fill DMA */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */ + kQSPI_RxBufferDrainDMAEnable = QuadSPI_RSER_RBDDE_MASK, /*!< Rx buffer drain DMA */ +#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA) + kQSPI_AllDDMAEnable = QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK /*!< All DMA source */ +#else + kQSPI_AllDDMAEnable = QuadSPI_RSER_RBDDE_MASK /* All DMA source */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */ +}; + +/*! @brief Phrase shift number for DQS mode. */ +typedef enum _qspi_dqs_phrase_shift +{ + kQSPI_DQSNoPhraseShift = 0x0U, /*!< No phase shift */ + kQSPI_DQSPhraseShift45Degree, /*!< Select 45 degree phase shift*/ + kQSPI_DQSPhraseShift90Degree, /*!< Select 90 degree phase shift */ + kQSPI_DQSPhraseShift135Degree /*!< Select 135 degree phase shift */ +} qspi_dqs_phrase_shift_t; + +/*! @brief Qspi read sampling option. */ +typedef enum _qspi_dqs_read_sample_clock +{ + kQSPI_ReadSampleClkInternalLoopback = 0x0U, /*!< Read sample clock adopts internal loopback mode. */ + kQSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by QSPI Controller + and loopback from DQS pad. */ + kQSPI_ReadSampleClkExternalInputFromDqsPad = 0x2U, /*!< Flash provided Read strobe and input from DQS pad. */ +} qspi_dqs_read_sample_clock_t; + +/*! @brief DQS configure features*/ +typedef struct QspiDQSConfig +{ + uint32_t portADelayTapNum; /*!< Delay chain tap number selection for QSPI port A DQS */ +#if defined(QuadSPI_SOCCR_DQS_IFB_DELAY_CHAIN_SEL_MASK) + uint32_t portBDelayTapNum; /*!< Delay chain tap number selection for QSPI port B DQS*/ +#endif + qspi_dqs_phrase_shift_t shift; /*!< Phase shift for internal DQS generation */ + qspi_dqs_read_sample_clock_t rxSampleClock; /*!< Read sample clock for Dqs. */ + bool enableDQSClkInverse; /*!< Enable inverse clock for internal DQS generation */ +} qspi_dqs_config_t; + +/*! @brief Flash timing configuration. */ +typedef struct QspiFlashTiming +{ + uint32_t dataHoldTime; /*!< Serial flash data in hold time */ + uint32_t CSHoldTime; /*!< Serial flash CS hold time in terms of serial flash clock cycles */ + uint32_t CSSetupTime; /*!< Serial flash CS setup time in terms of serial flash clock cycles */ +} qspi_flash_timing_t; + +/*! @brief QSPI configuration structure*/ +typedef struct QspiConfig +{ + uint32_t clockSource; /*!< Clock source for QSPI module */ + uint32_t baudRate; /*!< Serial flash clock baud rate */ + uint8_t txWatermark; /*!< QSPI transmit watermark value */ + uint8_t rxWatermark; /*!< QSPI receive watermark value. */ + uint32_t AHBbufferSize[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */ + uint8_t AHBbufferMaster[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer master. */ + bool enableAHBbuffer3AllMaster; /*!< Is AHB buffer3 for all master.*/ + qspi_read_area_t area; /*!< Which area Rx data readout */ + bool enableQspi; /*!< Enable QSPI after initialization */ +} qspi_config_t; + +/*! @brief External flash configuration items*/ +typedef struct _qspi_flash_config +{ + uint32_t flashA1Size; /*!< Flash A1 size */ + uint32_t flashA2Size; /*!< Flash A2 size */ +#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) + uint32_t flashB1Size; /*!< Flash B1 size */ + uint32_t flashB2Size; /*!< Flash B2 size */ +#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */ + uint32_t lookuptable[FSL_FEATURE_QSPI_LUT_DEPTH]; /*!< Flash command in LUT */ +#if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH) + uint32_t dataHoldTime; /*!< Data line hold time. */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */ + uint32_t CSHoldTime; /*!< CS line hold time */ + uint32_t CSSetupTime; /*!< CS line setup time*/ + uint32_t cloumnspace; /*!< Column space size */ + uint32_t dataLearnValue; /*!< Data Learn value if enable data learn */ + qspi_endianness_t endian; /*!< Flash data endianess. */ + bool enableWordAddress; /*!< If enable word address.*/ +} qspi_flash_config_t; + +/*! @brief Transfer structure for QSPI */ +typedef struct _qspi_transfer +{ + uint32_t *data; /*!< Pointer to data to transmit */ + size_t dataSize; /*!< Bytes to be transmit */ +} qspi_transfer_t; + +/*! @brief 16-bit access reg for IPCR register */ +typedef struct _ip_command_config +{ + union + { + __IO uint32_t IPCR; /*!< IP Configuration Register */ + struct + { + __IO uint16_t IDATZ; /*!< 16-bit access for IDATZ field in IPCR register */ + __IO uint8_t RESERVED_0; /*!< 8-bit access for RESERVED_0 field in IPCR register */ + __IO uint8_t SEQID; /*!< 8-bit access for SEQID field in IPCR register */ + } BITFIELD; + } IPCR_REG; +} ip_command_config_t; + +/****************************************************************************** + * API + *****************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Get the instance number for QSPI. + * + * @param base QSPI base pointer. + */ +uint32_t QSPI_GetInstance(QuadSPI_Type *base); + +/*! + * @brief Initializes the QSPI module and internal state. + * + * This function enables the clock for QSPI and also configures the QSPI with the + * input configure parameters. Users should call this function before any QSPI operations. + * + * @param base Pointer to QuadSPI Type. + * @param config QSPI configure structure. + * @param srcClock_Hz QSPI source clock frequency in Hz. + */ +void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Gets default settings for QSPI. + * + * @param config QSPI configuration structure. + */ +void QSPI_GetDefaultQspiConfig(qspi_config_t *config); + +/*! + * @brief Deinitializes the QSPI module. + * + * Clears the QSPI state and QSPI module registers. + * @param base Pointer to QuadSPI Type. + */ +void QSPI_Deinit(QuadSPI_Type *base); + +/*! + * @brief Configures the serial flash parameter. + * + * This function configures the serial flash relevant parameters, such as the size, command, and so on. + * The flash configuration value cannot have a default value. The user needs to configure it according to the + * QSPI features. + * + * @param base Pointer to QuadSPI Type. + * @param config Flash configuration parameters. + */ +void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config); + +#if (!defined(FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG)) || !FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG +/*! + * @brief Configures the serial flash DQS parameter. + * + * This function configures the serial flash DQS relevant parameters, such as the delay chain tap number, . + * DQS shift phase, whether need to inverse and the rxc sample clock selection. + * + * @param base Pointer to QuadSPI Type. + * @param config Dqs configuration parameters. + */ +void QSPI_SetDqsConfig(QuadSPI_Type *base, qspi_dqs_config_t *config); +#endif + +/*! + * @brief Software reset for the QSPI logic. + * + * This function sets the software reset flags for both AHB and buffer domain and + * resets both AHB buffer and also IP FIFOs. + * + * @param base Pointer to QuadSPI Type. + */ +void QSPI_SoftwareReset(QuadSPI_Type *base); + +/*! + * @brief Enables or disables the QSPI module. + * + * @param base Pointer to QuadSPI Type. + * @param enable True means enable QSPI, false means disable. + */ +static inline void QSPI_Enable(QuadSPI_Type *base, bool enable) +{ + if (enable) + { + base->MCR &= ~QuadSPI_MCR_MDIS_MASK; + } + else + { + base->MCR |= QuadSPI_MCR_MDIS_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the state value of QSPI. + * + * @param base Pointer to QuadSPI Type. + * @return status flag, use status flag to AND #_qspi_flags could get the related status. + */ +static inline uint32_t QSPI_GetStatusFlags(QuadSPI_Type *base) +{ + return base->SR; +} + +/*! + * @brief Gets QSPI error status flags. + * + * @param base Pointer to QuadSPI Type. + * @return status flag, use status flag to AND #_qspi_error_flags could get the related status. + */ +static inline uint32_t QSPI_GetErrorStatusFlags(QuadSPI_Type *base) +{ + return base->FR; +} + +/*! @brief Clears the QSPI error flags. + * + * @param base Pointer to QuadSPI Type. + * @param mask Which kind of QSPI flags to be cleared, a combination of _qspi_error_flags. + */ +static inline void QSPI_ClearErrorFlag(QuadSPI_Type *base, uint32_t mask) +{ + base->FR = mask; +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the QSPI interrupts. + * + * @param base Pointer to QuadSPI Type. + * @param mask QSPI interrupt source. + */ +static inline void QSPI_EnableInterrupts(QuadSPI_Type *base, uint32_t mask) +{ + base->RSER |= mask; +} + +/*! + * @brief Disables the QSPI interrupts. + * + * @param base Pointer to QuadSPI Type. + * @param mask QSPI interrupt source. + */ +static inline void QSPI_DisableInterrupts(QuadSPI_Type *base, uint32_t mask) +{ + base->RSER &= ~mask; +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the QSPI DMA source. + * + * @param base Pointer to QuadSPI Type. + * @param mask QSPI DMA source. + * @param enable True means enable DMA, false means disable. + */ +static inline void QSPI_EnableDMA(QuadSPI_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->RSER |= mask; + } + else + { + base->RSER &= ~mask; + } +} + +/*! + * @brief Gets the Tx data register address. It is used for DMA operation. + * + * @param base Pointer to QuadSPI Type. + * @return QSPI Tx data register address. + */ +static inline uint32_t QSPI_GetTxDataRegisterAddress(QuadSPI_Type *base) +{ + return (uint32_t)(&base->TBDR); +} + +/*! + * @brief Gets the Rx data register address used for DMA operation. + * + * This function returns the Rx data register address or Rx buffer address + * according to the Rx read area settings. + * + * @param base Pointer to QuadSPI Type. + * @return QSPI Rx data register address. + */ +uint32_t QSPI_GetRxDataRegisterAddress(QuadSPI_Type *base); + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! @brief Sets the IP command address. + * + * @param base Pointer to QuadSPI Type. + * @param addr IP command address. + */ +static inline void QSPI_SetIPCommandAddress(QuadSPI_Type *base, uint32_t addr) +{ + base->SFAR = addr; +} + +/*! @brief Sets the IP command size. + * + * @param base Pointer to QuadSPI Type. + * @param size IP command size. + */ +static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint32_t size) +{ + union + { + volatile uint32_t *commandRegBase; + ip_command_config_t *commandConfigPtr; + } command; + command.commandRegBase = &(base->IPCR); + ip_command_config_t *ipCommand = command.commandConfigPtr; + size = QuadSPI_IPCR_IDATSZ(size); + ipCommand->IPCR_REG.BITFIELD.IDATZ = (uint16_t)size; +} + +/*! @brief Executes IP commands located in LUT table. + * + * @param base Pointer to QuadSPI Type. + * @param index IP command located in which LUT table index. + */ +void QSPI_ExecuteIPCommand(QuadSPI_Type *base, uint32_t index); + +/*! @brief Executes AHB commands located in LUT table. + * + * @param base Pointer to QuadSPI Type. + * @param index AHB command located in which LUT table index. + */ +void QSPI_ExecuteAHBCommand(QuadSPI_Type *base, uint32_t index); + +#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) +/*! @brief Enables/disables the QSPI IP command parallel mode. + * + * @param base Pointer to QuadSPI Type. + * @param enable True means enable parallel mode, false means disable parallel mode. + */ +static inline void QSPI_EnableIPParallelMode(QuadSPI_Type *base, bool enable) +{ + if (enable) + { + base->IPCR |= QuadSPI_IPCR_PAR_EN_MASK; + } + else + { + base->IPCR &= ~QuadSPI_IPCR_PAR_EN_MASK; + } +} + +/*! @brief Enables/disables the QSPI AHB command parallel mode. + * + * @param base Pointer to QuadSPI Type. + * @param enable True means enable parallel mode, false means disable parallel mode. + */ +static inline void QSPI_EnableAHBParallelMode(QuadSPI_Type *base, bool enable) +{ + if (enable) + { + base->BFGENCR |= QuadSPI_BFGENCR_PAR_EN_MASK; + } + else + { + base->BFGENCR &= ~QuadSPI_BFGENCR_PAR_EN_MASK; + } +} +#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */ + +/*! @brief Updates the LUT table. + * + * @param base Pointer to QuadSPI Type. + * @param index Which LUT index needs to be located. It should be an integer divided by 4. + * @param cmd Command sequence array. + */ +void QSPI_UpdateLUT(QuadSPI_Type *base, uint32_t index, uint32_t *cmd); + +/*! @brief Clears the QSPI FIFO logic. + * + * @param base Pointer to QuadSPI Type. + * @param mask Which kind of QSPI FIFO to be cleared. + */ +static inline void QSPI_ClearFifo(QuadSPI_Type *base, uint32_t mask) +{ + base->MCR |= mask; +} + +/*!@ brief Clears the command sequence for the IP/buffer command. + * + * This function can reset the command sequence. + * @param base QSPI base address. + * @param seq Which command sequence need to reset, IP command, buffer command or both. + */ +static inline void QSPI_ClearCommandSequence(QuadSPI_Type *base, qspi_command_seq_t seq) +{ + base->SPTRCLR = (uint32_t)seq; +} + +/*! + * @brief Enable or disable DDR mode. + * + * @param base QSPI base pointer + * @param enable True means enable DDR mode, false means disable DDR mode. + */ +static inline void QSPI_EnableDDRMode(QuadSPI_Type *base, bool enable) +{ + if (enable) + { + base->MCR |= QuadSPI_MCR_DDR_EN_MASK; + } + else + { + base->MCR &= ~QuadSPI_MCR_DDR_EN_MASK; + } +} + +#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) + +/*! @brief Clears the QSPI cache. + * + * @param base Pointer to QuadSPI Type. + */ +void QSPI_ClearCache(QuadSPI_Type *base); +#endif + +/*!@ brief Set the RX buffer readout area. + * + * This function can set the RX buffer readout, from AHB bus or IP Bus. + * @param base QSPI base address. + * @param area QSPI Rx buffer readout area. AHB bus buffer or IP bus buffer. + */ +void QSPI_SetReadDataArea(QuadSPI_Type *base, qspi_read_area_t area); + +/*! + * @brief Sends a buffer of data bytes using a blocking method. + * @note This function blocks via polling until all bytes have been sent. + * @param base QSPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to send + */ +void QSPI_WriteBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Writes data into FIFO. + * + * @param base QSPI base pointer + * @param data The data bytes to send + */ +static inline void QSPI_WriteData(QuadSPI_Type *base, uint32_t data) +{ + base->TBDR = data; +} + +/*! + * @brief Receives a buffer of data bytes using a blocking method. + * @note This function blocks via polling until all bytes have been sent. Users shall notice that + * this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers. + * For flash contents read, please use AHB bus read, this is much more efficiency. + * + * @param base QSPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to receive + */ +void QSPI_ReadBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Receives data from data FIFO. + * + * @param base QSPI base pointer + * @return The data in the FIFO. + */ +uint32_t QSPI_ReadData(QuadSPI_Type *base); + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Writes data to the QSPI transmit buffer. + * + * This function writes a continuous data to the QSPI transmit FIFO. This function is a block function + * and can return only when finished. This function uses polling methods. + * + * @param base Pointer to QuadSPI Type. + * @param xfer QSPI transfer structure. + */ +static inline void QSPI_TransferSendBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer) +{ + QSPI_WriteBlocking(base, xfer->data, xfer->dataSize); +} + +/*! + * @brief Reads data from the QSPI receive buffer in polling way. + * + * This function reads continuous data from the QSPI receive buffer/FIFO. This function is a blocking + * function and can return only when finished. This function uses polling methods. Users shall notice that + * this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers. + * For flash contents read, please use AHB bus read, this is much more efficiency. + * + * @param base Pointer to QuadSPI Type. + * @param xfer QSPI transfer structure. + */ +static inline void QSPI_TransferReceiveBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer) +{ + QSPI_ReadBlocking(base, xfer->data, xfer->dataSize); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/* @}*/ + +#endif /* _FSL_QSPI_H_*/ diff --git a/devices/MIMX8MQ6/drivers/fsl_rdc.c b/devices/MIMX8MQ6/drivers/fsl_rdc.c new file mode 100644 index 000000000..816770dbd --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_rdc.c @@ -0,0 +1,310 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_rdc.h" + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.rdc" +#endif + +typedef union +{ + rdc_domain_assignment_t _mda; + uint32_t _u32; +} rdc_mda_reg_t; + +typedef union +{ + rdc_hardware_config_t _vir; + uint32_t _u32; +} rdc_vir_reg_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for RDC module. + * + * @param base RDC peripheral base address. + */ +uint32_t RDC_GetInstance(RDC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to rdc bases for each instance. */ +static RDC_Type *const s_rdcBases[] = RDC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to rdc clocks for each instance. */ +static const clock_ip_name_t s_rdcClocks[] = RDC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/****************************************************************************** + * CODE + *****************************************************************************/ + +uint32_t RDC_GetInstance(RDC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_rdcBases); instance++) + { + if (s_rdcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_rdcBases)); + + return instance; +} + +/*! + * brief Initializes the RDC module. + * + * This function enables the RDC clock. + * + * param base RDC peripheral base address. + */ +void RDC_Init(RDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(s_rdcClocks[RDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief De-initializes the RDC module. + * + * This function disables the RDC clock. + * + * param base RDC peripheral base address. + */ +void RDC_Deinit(RDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_rdcClocks[RDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the RDC hardware configuration. + * + * This function gets the RDC hardware configurations, including number of bus + * masters, number of domains, number of memory regions and number of peripherals. + * + * param base RDC peripheral base address. + * param config Pointer to the structure to get the configuration. + */ +void RDC_GetHardwareConfig(RDC_Type *base, rdc_hardware_config_t *config) +{ + assert(NULL != config); + + rdc_vir_reg_t vir; + vir._u32 = base->VIR; + + *config = vir._vir; +} + +/*! + * brief Set master domain assignment + * + * param base RDC peripheral base address. + * param master Which master to set. + * param domainAssignment Pointer to the assignment. + */ +void RDC_SetMasterDomainAssignment(RDC_Type *base, rdc_master_t master, const rdc_domain_assignment_t *domainAssignment) +{ + assert((uint32_t)master < RDC_MDA_COUNT); + + rdc_mda_reg_t mda; + + mda._mda = *domainAssignment; + + base->MDA[master] = mda._u32; +} + +/*! + * brief Get default master domain assignment + * + * The default configuration is: + * code + assignment->domainId = 0U; + assignment->lock = 0U; + endcode + * + * param domainAssignment Pointer to the assignment. + */ +void RDC_GetDefaultMasterDomainAssignment(rdc_domain_assignment_t *domainAssignment) +{ + assert(NULL != domainAssignment); + + rdc_mda_reg_t mda; + mda._u32 = 0U; + + *domainAssignment = mda._mda; +} + +/*! + * brief Set peripheral access policy. + * + * param base RDC peripheral base address. + * param config Pointer to the policy configuration. + */ +void RDC_SetPeriphAccessConfig(RDC_Type *base, const rdc_periph_access_config_t *config) +{ + assert((uint32_t)config->periph < RDC_PDAP_COUNT); + + uint32_t periph = (uint32_t)config->periph; + uint32_t regPDAP = config->policy; + + if (config->lock) + { + regPDAP |= RDC_PDAP_LCK_MASK; + } + + if (config->enableSema) + { + regPDAP |= RDC_PDAP_SREQ_MASK; + } + + base->PDAP[periph] = regPDAP; + + __DSB(); +} + +/*! + * brief Get default peripheral access policy. + * + * The default configuration is: + * code + config->lock = false; + config->enableSema = false; + config->policy = RDC_ACCESS_POLICY(0, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(1, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(2, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(3, kRDC_ReadWrite); + endcode + * + * param config Pointer to the policy configuration. + */ +void RDC_GetDefaultPeriphAccessConfig(rdc_periph_access_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->lock = false; + config->enableSema = false; + config->policy = RDC_ACCESS_POLICY(0U, kRDC_ReadWrite) | RDC_ACCESS_POLICY(1U, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(2U, kRDC_ReadWrite) | RDC_ACCESS_POLICY(3U, kRDC_ReadWrite); +} + +/*! + * brief Set memory region access policy. + * + * Note that when setting the baseAddress and endAddress in p config, + * should be aligned to the region resolution, see rdc_mem_t + * definitions. + * + * param base RDC peripheral base address. + * param config Pointer to the policy configuration. + */ +void RDC_SetMemAccessConfig(RDC_Type *base, const rdc_mem_access_config_t *config) +{ + assert((uint32_t)config->mem < RDC_MRC_COUNT); + + uint32_t mem = (uint32_t)config->mem; + /* The configuration is enabled by default. */ + uint32_t regMRC = config->policy | RDC_MRC_ENA_MASK; + + if (config->lock) + { + regMRC |= RDC_MRC_LCK_MASK; + } + +#if (defined(FSL_FEATURE_RDC_MEM_REGION_ADDR_SHIFT) && FSL_FEATURE_RDC_MEM_REGION_ADDR_SHIFT) + base->MR[mem].MRSA = (uint32_t)(config->baseAddress >> (uint32_t)FSL_FEATURE_RDC_MEM_REGION_ADDR_SHIFT); + base->MR[mem].MREA = (uint32_t)(config->endAddress >> (uint32_t)FSL_FEATURE_RDC_MEM_REGION_ADDR_SHIFT); +#else + base->MR[mem].MRSA = (uint32_t)config->baseAddress; + base->MR[mem].MREA = (uint32_t)config->endAddress; +#endif + base->MR[mem].MRC = regMRC; + + __DSB(); +} + +/*! + * brief Get default memory region access policy. + * + * The default configuration is: + * code + config->lock = false; + config->baseAddress = 0; + config->endAddress = 0; + config->policy = RDC_ACCESS_POLICY(0, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(1, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(2, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(3, kRDC_ReadWrite); + endcode + * + * param config Pointer to the policy configuration. + */ +void RDC_GetDefaultMemAccessConfig(rdc_mem_access_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->lock = false; + config->baseAddress = 0; + config->endAddress = 0; + config->policy = RDC_ACCESS_POLICY(0U, kRDC_ReadWrite) | RDC_ACCESS_POLICY(1U, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(2U, kRDC_ReadWrite) | RDC_ACCESS_POLICY(3U, kRDC_ReadWrite); +} + +/*! + * brief Get the memory region violation status. + * + * The first access violation is captured. Subsequent violations are ignored + * until the status register is cleared. Contents are cleared upon reading the + * register. Clearing of contents occurs only when the status is read by the + * memory region's associated domain ID(s). + * + * param base RDC peripheral base address. + * param mem Which memory region to get. + * param status The returned status. + */ +void RDC_GetMemViolationStatus(RDC_Type *base, rdc_mem_t mem, rdc_mem_status_t *status) +{ + assert((uint32_t)mem < RDC_MRC_COUNT); + + uint32_t regMRVS = base->MR[mem].MRVS; + + status->hasViolation = ((regMRVS & RDC_MRVS_AD_MASK) != 0U); + status->domainID = (uint8_t)((regMRVS & RDC_MRVS_VDID_MASK) >> RDC_MRVS_VDID_SHIFT); +#if (defined(FSL_FEATURE_RDC_MEM_REGION_ADDR_SHIFT) && FSL_FEATURE_RDC_MEM_REGION_ADDR_SHIFT) + regMRVS &= RDC_MRVS_VADR_MASK; + status->address = ((uint64_t)regMRVS) << (uint32_t)FSL_FEATURE_RDC_MEM_REGION_ADDR_SHIFT; +#else + regMRVS &= RDC_MRVS_VADR_MASK; + status->address = (uint64_t)regMRVS; +#endif +} diff --git a/devices/MIMX8MQ6/drivers/fsl_rdc.h b/devices/MIMX8MQ6/drivers/fsl_rdc.h new file mode 100644 index 000000000..41d3f5aca --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_rdc.h @@ -0,0 +1,447 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RDC_H_ +#define _FSL_RDC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rdc + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ +#define FSL_RDC_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) + +#define RDC_ACCESS_POLICY(domainID, policy) (uint16_t)((uint16_t)(policy) << ((domainID)*2U)) + +/*! + * @brief RDC hardware configuration. + */ +typedef struct _rdc_hardware_config +{ + uint32_t domainNumber : 4; /*!< Number of domains. */ + uint32_t masterNumber : 8; /*!< Number of bus masters. */ + uint32_t periphNumber : 8; /*!< Number of peripherals. */ + uint32_t memNumber : 8; /*!< Number of memory regions. */ + uint32_t : 4; +} rdc_hardware_config_t; + +/*! + * @brief RDC interrupts + */ +enum _rdc_interrupts +{ + kRDC_RestoreCompleteInterrupt = RDC_INTCTRL_RCI_EN_MASK, + /*!< Interrupt generated when the RDC has completed restoring state to a recently re-powered memory regions. */ +}; + +/*! + * @brief RDC status + */ +enum _rdc_flags +{ + kRDC_PowerDownDomainOn = RDC_STAT_PDS_MASK, /*!< Power down domain is ON. */ +}; + +/*! + * @brief Master domain assignment. + */ +typedef struct _rdc_domain_assignment +{ + uint32_t domainId : 2U; /*!< Domain ID. */ + uint32_t : 29U; /*!< Reserved. */ + uint32_t lock : 1U; /*!< Lock the domain assignment. */ +} rdc_domain_assignment_t; + +/*! + * @brief Access permission policy. + */ +enum _rdc_access_policy +{ + kRDC_NoAccess = 0, /*!< Could not read or write. */ + kRDC_WriteOnly = 1, /*!< Write only. */ + kRDC_ReadOnly = 2, /*!< Read only. */ + kRDC_ReadWrite = 3, /*!< Read and write. */ +}; + +/*! + * @brief Peripheral domain access permission configuration. + */ +typedef struct _rdc_periph_access_config +{ + rdc_periph_t periph; /*!< Peripheral name. */ + bool lock; /*!< Lock the permission until reset. */ + bool enableSema; /*!< Enable semaphore or not, when enabled, master should + call @ref RDC_SEMA42_Lock to lock the semaphore gate + accordingly before access the peripheral. */ + uint16_t policy; /*!< Access policy. */ +} rdc_periph_access_config_t; + +/*! + * @brief Memory region domain access control configuration. + * + * Note that when setting the @ref baseAddress and @ref endAddress, + * should be aligned to the region resolution, see rdc_mem_t + * definitions. + */ +typedef struct _rdc_mem_access_config +{ + rdc_mem_t mem; /*!< Memory region descriptor name. */ + + bool lock; /*!< Lock the configuration. */ + uint64_t baseAddress; /*!< Start address of the memory region. */ + uint64_t endAddress; /*!< End address of the memory region. */ + uint16_t policy; /*!< Access policy. */ +} rdc_mem_access_config_t; + +/*! + * @brief Memory region access violation status. + */ +typedef struct _rdc_mem_status +{ + bool hasViolation; /*!< Violating happens or not. */ + uint8_t domainID; /*!< Violating Domain ID. */ + uint64_t address; /*!< Violating Address. */ +} rdc_mem_status_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the RDC module. + * + * This function enables the RDC clock. + * + * @param base RDC peripheral base address. + */ +void RDC_Init(RDC_Type *base); + +/*! + * @brief De-initializes the RDC module. + * + * This function disables the RDC clock. + * + * @param base RDC peripheral base address. + */ +void RDC_Deinit(RDC_Type *base); + +/*! + * @brief Gets the RDC hardware configuration. + * + * This function gets the RDC hardware configurations, including number of bus + * masters, number of domains, number of memory regions and number of peripherals. + * + * @param base RDC peripheral base address. + * @param config Pointer to the structure to get the configuration. + */ +void RDC_GetHardwareConfig(RDC_Type *base, rdc_hardware_config_t *config); + +/*! + * @brief Enable interrupts. + * + * @param base RDC peripheral base address. + * @param mask Interrupts to enable, it is OR'ed value of enum @ref _rdc_interrupts. + */ +static inline void RDC_EnableInterrupts(RDC_Type *base, uint32_t mask) +{ + base->INTCTRL |= mask; +} + +/*! + * @brief Disable interrupts. + * + * @param base RDC peripheral base address. + * @param mask Interrupts to disable, it is OR'ed value of enum @ref _rdc_interrupts. + */ +static inline void RDC_DisableInterrupts(RDC_Type *base, uint32_t mask) +{ + base->INTCTRL &= ~mask; +} + +/*! + * @brief Get the interrupt pending status. + * + * @param base RDC peripheral base address. + * @return Interrupts pending status, it is OR'ed value of enum @ref _rdc_interrupts. + */ +static inline uint32_t RDC_GetInterruptStatus(RDC_Type *base) +{ + return base->INTSTAT; +} + +/*! + * @brief Clear interrupt pending status. + * + * @param base RDC peripheral base address. + * @param mask Status to clear, it is OR'ed value of enum @ref _rdc_interrupts. + */ +static inline void RDC_ClearInterruptStatus(RDC_Type *base, uint32_t mask) +{ + base->INTSTAT = mask; +} + +/*! + * @brief Get RDC status. + * + * @param base RDC peripheral base address. + * @return mask RDC status, it is OR'ed value of enum @ref _rdc_flags. + */ +static inline uint32_t RDC_GetStatus(RDC_Type *base) +{ + return base->STAT; +} + +/*! + * @brief Clear RDC status. + * + * @param base RDC peripheral base address. + * @param mask RDC status to clear, it is OR'ed value of enum @ref _rdc_flags. + */ +static inline void RDC_ClearStatus(RDC_Type *base, uint32_t mask) +{ + base->STAT = mask; +} + +/*! + * @brief Set master domain assignment + * + * @param base RDC peripheral base address. + * @param master Which master to set. + * @param domainAssignment Pointer to the assignment. + */ +void RDC_SetMasterDomainAssignment(RDC_Type *base, + rdc_master_t master, + const rdc_domain_assignment_t *domainAssignment); + +/*! + * @brief Get default master domain assignment + * + * The default configuration is: + * @code + assignment->domainId = 0U; + assignment->lock = 0U; + @endcode + * + * @param domainAssignment Pointer to the assignment. + */ +void RDC_GetDefaultMasterDomainAssignment(rdc_domain_assignment_t *domainAssignment); + +/*! + * @brief Lock master domain assignment + * + * Once locked, it could not be unlocked until next reset. + * + * @param base RDC peripheral base address. + * @param master Which master to lock. + */ +static inline void RDC_LockMasterDomainAssignment(RDC_Type *base, rdc_master_t master) +{ + assert((uint32_t)master < RDC_MDA_COUNT); + + base->MDA[master] |= RDC_MDA_LCK_MASK; + __DSB(); +} + +/*! + * @brief Set peripheral access policy. + * + * @param base RDC peripheral base address. + * @param config Pointer to the policy configuration. + */ +void RDC_SetPeriphAccessConfig(RDC_Type *base, const rdc_periph_access_config_t *config); + +/*! + * @brief Get default peripheral access policy. + * + * The default configuration is: + * @code + config->lock = false; + config->enableSema = false; + config->policy = RDC_ACCESS_POLICY(0, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(1, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(2, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(3, kRDC_ReadWrite); + @endcode + * + * @param config Pointer to the policy configuration. + */ +void RDC_GetDefaultPeriphAccessConfig(rdc_periph_access_config_t *config); + +/*! + * @brief Lock peripheral access policy configuration. + * + * Once locked, it could not be unlocked until reset. + * + * @param base RDC peripheral base address. + * @param periph Which peripheral to lock. + */ +static inline void RDC_LockPeriphAccessConfig(RDC_Type *base, rdc_periph_t periph) +{ + assert((uint32_t)periph < RDC_PDAP_COUNT); + + base->PDAP[periph] |= RDC_PDAP_LCK_MASK; + __DSB(); +} + +/*! + * @brief Get the peripheral access policy for specific domain. + * + * @param base RDC peripheral base address. + * @param periph Which peripheral to get. + * @param domainId Get policy for which domain. + * @return Access policy, see @ref _rdc_access_policy. + */ +static inline uint8_t RDC_GetPeriphAccessPolicy(RDC_Type *base, rdc_periph_t periph, uint8_t domainId) +{ + assert((uint32_t)periph < RDC_PDAP_COUNT); + + return (uint8_t)((base->PDAP[periph] >> (domainId * 2U)) & 0x03U); +} + +/*! + * @brief Set memory region access policy. + * + * Note that when setting the baseAddress and endAddress in @p config, + * should be aligned to the region resolution, see rdc_mem_t + * definitions. + * + * @param base RDC peripheral base address. + * @param config Pointer to the policy configuration. + */ +void RDC_SetMemAccessConfig(RDC_Type *base, const rdc_mem_access_config_t *config); + +/*! + * @brief Get default memory region access policy. + * + * The default configuration is: + * @code + config->lock = false; + config->baseAddress = 0; + config->endAddress = 0; + config->policy = RDC_ACCESS_POLICY(0, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(1, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(2, kRDC_ReadWrite) | + RDC_ACCESS_POLICY(3, kRDC_ReadWrite); + @endcode + * + * @param config Pointer to the policy configuration. + */ +void RDC_GetDefaultMemAccessConfig(rdc_mem_access_config_t *config); + +/*! + * @brief Lock memory access policy configuration. + * + * Once locked, it could not be unlocked until reset. After locked, you can + * only call @ref RDC_SetMemAccessValid to enable the configuration, but can not + * disable it or change other settings. + * + * @param base RDC peripheral base address. + * @param mem Which memory region to lock. + */ +static inline void RDC_LockMemAccessConfig(RDC_Type *base, rdc_mem_t mem) +{ + assert((uint32_t)mem < RDC_MRC_COUNT); + + base->MR[mem].MRC |= RDC_MRC_LCK_MASK; + __DSB(); +} + +/*! + * @brief Enable or disable memory access policy configuration. + * + * @param base RDC peripheral base address. + * @param mem Which memory region to operate. + * @param valid Pass in true to valid, false to invalid. + */ +static inline void RDC_SetMemAccessValid(RDC_Type *base, rdc_mem_t mem, bool valid) +{ + assert((uint32_t)mem < RDC_MRC_COUNT); + + if (valid) + { + base->MR[mem].MRC |= RDC_MRC_ENA_MASK; + } + else + { + base->MR[mem].MRC &= ~RDC_MRC_ENA_MASK; + } + __DSB(); +} + +/*! + * @brief Get the memory region violation status. + * + * The first access violation is captured. Subsequent violations are ignored + * until the status register is cleared. Contents are cleared upon reading the + * register. Clearing of contents occurs only when the status is read by the + * memory region's associated domain ID(s). + * + * @param base RDC peripheral base address. + * @param mem Which memory region to get. + * @param status The returned status. + */ +void RDC_GetMemViolationStatus(RDC_Type *base, rdc_mem_t mem, rdc_mem_status_t *status); + +/*! + * @brief Clear the memory region violation flag. + * + * @param base RDC peripheral base address. + * @param mem Which memory region to clear. + */ +static inline void RDC_ClearMemViolationFlag(RDC_Type *base, rdc_mem_t mem) +{ + assert((uint32_t)mem < RDC_MRC_COUNT); + + base->MR[mem].MRVS = RDC_MRVS_AD_MASK; +} + +/*! + * @brief Get the memory region access policy for specific domain. + * + * @param base RDC peripheral base address. + * @param mem Which memory region to get. + * @param domainId Get policy for which domain. + * @return Access policy, see @ref _rdc_access_policy. + */ +static inline uint8_t RDC_GetMemAccessPolicy(RDC_Type *base, rdc_mem_t mem, uint8_t domainId) +{ + assert((uint32_t)mem < RDC_MRC_COUNT); + + return (uint8_t)((base->MR[mem].MRC >> (domainId * 2U)) & 0x03U); +} + +/*! + * @brief Gets the domain ID of the current bus master. + * + * This function returns the domain ID of the current bus master. + * + * @param base RDC peripheral base address. + * @return Domain ID of current bus master. + */ +static inline uint8_t RDC_GetCurrentMasterDomainId(RDC_Type *base) +{ + return (uint8_t)((base->STAT & RDC_STAT_DID_MASK) >> RDC_STAT_DID_SHIFT); +} + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_RDC_H_ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_rdc_sema42.c b/devices/MIMX8MQ6/drivers/fsl_rdc_sema42.c new file mode 100644 index 000000000..4d78fc5bf --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_rdc_sema42.c @@ -0,0 +1,251 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_rdc_sema42.h" + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.rdc_sema42" +#endif + +/* The first number write to RSTGDP when reset RDC_SEMA42 gate. */ +#define RDC_SEMA42_GATE_RESET_PATTERN_1 (0xE2U) +/* The second number write to RSTGDP when reset RDC_SEMA42 gate. */ +#define RDC_SEMA42_GATE_RESET_PATTERN_2 (0x1DU) + +#if !defined(RDC_SEMAPHORE_GATE_COUNT) +/* Compatible remap. */ +#define RDC_SEMAPHORE_GATE_LDOM(x) RDC_SEMAPHORE_GATE0_LDOM(x) +#define RDC_SEMAPHORE_GATE_GTFSM(x) RDC_SEMAPHORE_GATE0_GTFSM(x) +#define RDC_SEMAPHORE_GATE_LDOM_MASK RDC_SEMAPHORE_GATE0_LDOM_MASK +#define RDC_SEMAPHORE_GATE_LDOM_SHIFT RDC_SEMAPHORE_GATE0_LDOM_SHIFT +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for RDC_SEMA42 module. + * + * @param base RDC_SEMA42 peripheral base address. + */ +uint32_t RDC_SEMA42_GetInstance(RDC_SEMAPHORE_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to sema42 bases for each instance. */ +static RDC_SEMAPHORE_Type *const s_sema42Bases[] = RDC_SEMAPHORE_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(RDC_SEMA42_CLOCKS) +/*! @brief Pointers to sema42 clocks for each instance. */ +static const clock_ip_name_t s_sema42Clocks[] = RDC_SEMA42_CLOCKS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/****************************************************************************** + * CODE + *****************************************************************************/ + +uint32_t RDC_SEMA42_GetInstance(RDC_SEMAPHORE_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_sema42Bases); instance++) + { + if (s_sema42Bases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_sema42Bases)); + + return instance; +} + +/*! + * brief Initializes the RDC_SEMA42 module. + * + * This function initializes the RDC_SEMA42 module. It only enables the clock but does + * not reset the gates because the module might be used by other processors + * at the same time. To reset the gates, call either RDC_SEMA42_ResetGate or + * RDC_SEMA42_ResetAllGates function. + * + * param base RDC_SEMA42 peripheral base address. + */ +void RDC_SEMA42_Init(RDC_SEMAPHORE_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(RDC_SEMA42_CLOCKS) + CLOCK_EnableClock(s_sema42Clocks[RDC_SEMA42_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief De-initializes the RDC_SEMA42 module. + * + * This function de-initializes the RDC_SEMA42 module. It only disables the clock. + * + * param base RDC_SEMA42 peripheral base address. + */ +void RDC_SEMA42_Deinit(RDC_SEMAPHORE_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(RDC_SEMA42_CLOCKS) + CLOCK_DisableClock(s_sema42Clocks[RDC_SEMA42_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Tries to lock the RDC_SEMA42 gate. + * + * This function tries to lock the specific RDC_SEMA42 gate. If the gate has been + * locked by another processor, this function returns an error code. + * + * param base RDC_SEMA42 peripheral base address. + * param gateNum Gate number to lock. + * param masterIndex Current processor master index. + * param domainId Current processor domain ID. + * + * retval kStatus_Success Lock the sema42 gate successfully. + * retval kStatus_Failed Sema42 gate has been locked by another processor. + */ +status_t RDC_SEMA42_TryLock(RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId) +{ + assert(gateNum < RDC_SEMA42_GATE_COUNT); + + status_t status = kStatus_Success; + uint8_t regGate; + + ++masterIndex; + + regGate = (uint8_t)(RDC_SEMAPHORE_GATE_LDOM(domainId) | RDC_SEMAPHORE_GATE_GTFSM(masterIndex)); + + /* Try to lock. */ + RDC_SEMA42_GATEn(base, gateNum) = masterIndex; + + /* Check locked or not. */ + if (regGate != RDC_SEMA42_GATEn(base, gateNum)) + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Locks the RDC_SEMA42 gate. + * + * This function locks the specific RDC_SEMA42 gate. If the gate has been + * locked by other processors, this function waits until it is unlocked and then + * lock it. + * + * param base RDC_SEMA42 peripheral base address. + * param gateNum Gate number to lock. + * param masterIndex Current processor master index. + * param domainId Current processor domain ID. + */ +void RDC_SEMA42_Lock(RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId) +{ + assert(gateNum < RDC_SEMA42_GATE_COUNT); + + uint8_t regGate; + + ++masterIndex; + + regGate = (uint8_t)(RDC_SEMAPHORE_GATE_LDOM(domainId) | RDC_SEMAPHORE_GATE_GTFSM(masterIndex)); + + while (regGate != RDC_SEMA42_GATEn(base, gateNum)) + { + /* Wait for unlocked status. */ + while (0U != (RDC_SEMA42_GATEn(base, gateNum) & RDC_SEMAPHORE_GATE_GTFSM_MASK)) + { + } + + /* Lock the gate. */ + RDC_SEMA42_GATEn(base, gateNum) = masterIndex; + } +} + +/*! + * brief Gets which domain has currently locked the gate. + * + * param base RDC_SEMA42 peripheral base address. + * param gateNum Gate number. + * + * return Return -1 if the gate is not locked by any domain, otherwise return the + * domain ID. + */ +int32_t RDC_SEMA42_GetLockDomainID(RDC_SEMAPHORE_Type *base, uint8_t gateNum) +{ + assert(gateNum < RDC_SEMA42_GATE_COUNT); + + int32_t ret; + uint8_t regGate = RDC_SEMA42_GATEn(base, gateNum); + + /* Current gate is not locked. */ + if (0U == (regGate & RDC_SEMAPHORE_GATE_GTFSM_MASK)) + { + ret = -1; + } + else + { + ret = (int32_t)((uint8_t)((regGate & RDC_SEMAPHORE_GATE_LDOM_MASK) >> RDC_SEMAPHORE_GATE_LDOM_SHIFT)); + } + + return ret; +} + +/*! + * brief Resets the RDC_SEMA42 gate to an unlocked status. + * + * This function resets a RDC_SEMA42 gate to an unlocked status. + * + * param base RDC_SEMA42 peripheral base address. + * param gateNum Gate number. + * + * retval kStatus_Success RDC_SEMA42 gate is reset successfully. + * retval kStatus_Failed Some other reset process is ongoing. + */ +status_t RDC_SEMA42_ResetGate(RDC_SEMAPHORE_Type *base, uint8_t gateNum) +{ + status_t status; + + /* + * Reset all gates if gateNum >= RDC_SEMA42_GATE_NUM_RESET_ALL + * Reset specific gate if gateNum < RDC_SEMA42_GATE_COUNT + */ + + /* Check whether some reset is ongoing. */ + if (0U != (base->RSTGT_R & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)) + { + status = kStatus_Fail; + } + else + { + /* First step. */ + base->RSTGT_W = RDC_SEMAPHORE_RSTGT_W_RSTGDP(RDC_SEMA42_GATE_RESET_PATTERN_1); + /* Second step. */ + base->RSTGT_W = + RDC_SEMAPHORE_RSTGT_W_RSTGDP(RDC_SEMA42_GATE_RESET_PATTERN_2) | RDC_SEMAPHORE_RSTGT_W_RSTGTN(gateNum); + + status = kStatus_Success; + } + + return status; +} diff --git a/devices/MIMX8MQ6/drivers/fsl_rdc_sema42.h b/devices/MIMX8MQ6/drivers/fsl_rdc_sema42.h new file mode 100644 index 000000000..1f76aaf18 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_rdc_sema42.h @@ -0,0 +1,194 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RDC_SEMA42_H_ +#define _FSL_RDC_SEMA42_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rdc_sema42 + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief RDC_SEMA42 driver version */ +#define FSL_RDC_SEMA42_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +/*! @brief The number to reset all RDC_SEMA42 gates. */ +#define RDC_SEMA42_GATE_NUM_RESET_ALL (64U) + +#if defined(RDC_SEMAPHORE_GATE_COUNT) + +/*! @brief RDC_SEMA42 gate n register address. */ +#define RDC_SEMA42_GATEn(base, n) ((base)->GATE[(n)]) + +/*! @brief RDC_SEMA42 gate count. */ +#define RDC_SEMA42_GATE_COUNT (RDC_SEMAPHORE_GATE_COUNT) + +#else /* RDC_SEMAPHORE_GATE_COUNT */ + +/*! @brief RDC_SEMA42 gate n register address. */ +#define RDC_SEMA42_GATEn(base, n) (((volatile uint8_t *)(&((base)->GATE0)))[(n)]) + +/*! @brief RDC_SEMA42 gate count. */ +#define RDC_SEMA42_GATE_COUNT (64U) + +/* Compatible remap. */ +#define RDC_SEMAPHORE_GATE_GTFSM_MASK RDC_SEMAPHORE_GATE0_GTFSM_MASK + +#endif /* RDC_SEMAPHORE_GATE_COUNT */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the RDC_SEMA42 module. + * + * This function initializes the RDC_SEMA42 module. It only enables the clock but does + * not reset the gates because the module might be used by other processors + * at the same time. To reset the gates, call either RDC_SEMA42_ResetGate or + * RDC_SEMA42_ResetAllGates function. + * + * @param base RDC_SEMA42 peripheral base address. + */ +void RDC_SEMA42_Init(RDC_SEMAPHORE_Type *base); + +/*! + * @brief De-initializes the RDC_SEMA42 module. + * + * This function de-initializes the RDC_SEMA42 module. It only disables the clock. + * + * @param base RDC_SEMA42 peripheral base address. + */ +void RDC_SEMA42_Deinit(RDC_SEMAPHORE_Type *base); + +/*! + * @brief Tries to lock the RDC_SEMA42 gate. + * + * This function tries to lock the specific RDC_SEMA42 gate. If the gate has been + * locked by another processor, this function returns an error code. + * + * @param base RDC_SEMA42 peripheral base address. + * @param gateNum Gate number to lock. + * @param masterIndex Current processor master index. + * @param domainId Current processor domain ID. + * + * @retval kStatus_Success Lock the sema42 gate successfully. + * @retval kStatus_Failed Sema42 gate has been locked by another processor. + */ +status_t RDC_SEMA42_TryLock(RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId); + +/*! + * @brief Locks the RDC_SEMA42 gate. + * + * This function locks the specific RDC_SEMA42 gate. If the gate has been + * locked by other processors, this function waits until it is unlocked and then + * lock it. + * + * @param base RDC_SEMA42 peripheral base address. + * @param gateNum Gate number to lock. + * @param masterIndex Current processor master index. + * @param domainId Current processor domain ID. + */ +void RDC_SEMA42_Lock(RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId); + +/*! + * @brief Unlocks the RDC_SEMA42 gate. + * + * This function unlocks the specific RDC_SEMA42 gate. It only writes unlock value + * to the RDC_SEMA42 gate register. However, it does not check whether the RDC_SEMA42 gate is locked + * by the current processor or not. As a result, if the RDC_SEMA42 gate is not locked by the current + * processor, this function has no effect. + * + * @param base RDC_SEMA42 peripheral base address. + * @param gateNum Gate number to unlock. + */ +static inline void RDC_SEMA42_Unlock(RDC_SEMAPHORE_Type *base, uint8_t gateNum) +{ + assert(gateNum < RDC_SEMA42_GATE_COUNT); + + RDC_SEMA42_GATEn(base, gateNum) = 0U; +} + +/*! + * @brief Gets which master has currently locked the gate. + * + * @param base RDC_SEMA42 peripheral base address. + * @param gateNum Gate number. + * + * @return Return -1 if the gate is not locked by any master, otherwise return the + * master index. + */ +static inline int32_t RDC_SEMA42_GetLockMasterIndex(RDC_SEMAPHORE_Type *base, uint8_t gateNum) +{ + assert(gateNum < RDC_SEMA42_GATE_COUNT); + + uint8_t regGate = RDC_SEMA42_GATEn(base, gateNum); + + return (int32_t)((uint8_t)(regGate & RDC_SEMAPHORE_GATE_GTFSM_MASK)) - 1; +} + +/*! + * @brief Gets which domain has currently locked the gate. + * + * @param base RDC_SEMA42 peripheral base address. + * @param gateNum Gate number. + * + * @return Return -1 if the gate is not locked by any domain, otherwise return the + * domain ID. + */ +int32_t RDC_SEMA42_GetLockDomainID(RDC_SEMAPHORE_Type *base, uint8_t gateNum); + +/*! + * @brief Resets the RDC_SEMA42 gate to an unlocked status. + * + * This function resets a RDC_SEMA42 gate to an unlocked status. + * + * @param base RDC_SEMA42 peripheral base address. + * @param gateNum Gate number. + * + * @retval kStatus_Success RDC_SEMA42 gate is reset successfully. + * @retval kStatus_Failed Some other reset process is ongoing. + */ +status_t RDC_SEMA42_ResetGate(RDC_SEMAPHORE_Type *base, uint8_t gateNum); + +/*! + * @brief Resets all RDC_SEMA42 gates to an unlocked status. + * + * This function resets all RDC_SEMA42 gate to an unlocked status. + * + * @param base RDC_SEMA42 peripheral base address. + * + * @retval kStatus_Success RDC_SEMA42 is reset successfully. + * @retval kStatus_RDC_SEMA42_Reseting Some other reset process is ongoing. + */ +static inline status_t RDC_SEMA42_ResetAllGates(RDC_SEMAPHORE_Type *base) +{ + return RDC_SEMA42_ResetGate(base, RDC_SEMA42_GATE_NUM_RESET_ALL); +} + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_RDC_SEMA42_H_ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_sai.c b/devices/MIMX8MQ6/drivers/fsl_sai.c new file mode 100644 index 000000000..9af30dcb2 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_sai.c @@ -0,0 +1,3818 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sai.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sai" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ +/*! @brief _sai_transfer_state sai transfer state.*/ +enum +{ + kSAI_Busy = 0x0U, /*!< SAI is busy */ + kSAI_Idle, /*!< Transfer is done. */ + kSAI_Error /*!< Transfer error occurred. */ +}; + +/*! @brief Typedef for sai tx interrupt handler. */ +typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief Typedef for sai rx interrupt handler. */ +typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief check flag avalibility */ +#define IS_SAI_FLAG_SET(reg, flag) (((reg) & ((uint32_t)flag)) != 0UL) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief sai get rx enabled interrupt status. + * + * + * @param base SAI base pointer. + * @param enableFlag enable flag to check. + * @param statusFlag status flag to check. + */ +static bool SAI_RxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag); + +/*! + * @brief sai get tx enabled interrupt status. + * + * + * @param base SAI base pointer. + * @param enableFlag enable flag to check. + * @param statusFlag status flag to check. + */ +static bool SAI_TxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag); + +/*! + * @brief Set the master clock divider. + * + * This API will compute the master clock divider according to master clock frequency and master + * clock source clock source frequency. + * + * @param base SAI base pointer. + * @param mclk_Hz Mater clock frequency in Hz. + * @param mclkSrcClock_Hz Master clock source frequency in Hz. + */ +static bool SAI_TxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag); + +#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV))) + +/*! + * @brief Set the master clock divider. + * + * This API will compute the master clock divider according to master clock frequency and master + * clock source clock source frequency. + * + * @param base SAI base pointer. + * @param mclk_Hz Mater clock frequency in Hz. + * @param mclkSrcClock_Hz Master clock source frequency in Hz. + */ +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz); +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +/*! + * @brief Get the instance number for SAI. + * + * @param base SAI base pointer. + */ +static uint32_t SAI_GetInstance(I2S_Type *base); + +/*! + * @brief sends a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel start channel number. + * @param channelMask enabled channels mask. + * @param endChannel end channel numbers. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +static void SAI_WriteNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint8_t bitWidth, + uint8_t *buffer, + uint32_t size); + +/*! + * @brief Receive a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel start channel number. + * @param channelMask enabled channels mask. + * @param endChannel end channel numbers. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +static void SAI_ReadNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint8_t bitWidth, + uint8_t *buffer, + uint32_t size); + +/*! + * @brief Get classic I2S mode configurations. + * + * @param config transceiver configurations + * @param bitWidth audio data bitWidth. + * @param mode audio data channel + * @param saiChannelMask channel mask value to enable + */ +static void SAI_GetCommonConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Base pointer array */ +static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; +/*!@brief SAI handle pointer */ +static sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2]; +/* IRQ number array */ +static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; +static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Clock name array */ +static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_tx_isr_t s_saiTxIsr; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_rx_isr_t s_saiRxIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool SAI_RxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag) +{ + uint32_t rcsr = base->RCSR; + + return IS_SAI_FLAG_SET(rcsr, enableFlag) && IS_SAI_FLAG_SET(rcsr, statusFlag); +} + +static bool SAI_TxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag) +{ + uint32_t tcsr = base->TCSR; + + return IS_SAI_FLAG_SET(tcsr, enableFlag) && IS_SAI_FLAG_SET(tcsr, statusFlag); +} + +#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV))) +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz) +{ + assert(mclk_Hz <= mclkSrcClock_Hz); + + uint32_t sourceFreq = mclkSrcClock_Hz / 100U; /*In order to prevent overflow */ + uint32_t targetFreq = mclk_Hz / 100U; /*In order to prevent overflow */ + +#if FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV + uint32_t postDivider = sourceFreq / targetFreq; + + /* if source equal to target, then disable divider */ + if (postDivider == 1U) + { + base->MCR &= ~I2S_MCR_DIVEN_MASK; + } + else + { + base->MCR = (base->MCR & (~I2S_MCR_DIV_MASK)) | I2S_MCR_DIV(postDivider / 2U - 1U) | I2S_MCR_DIVEN_MASK; + } +#endif +#if FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER + uint16_t fract, divide; + uint32_t remaind = 0; + uint32_t current_remainder = 0xFFFFFFFFU; + uint16_t current_fract = 0; + uint16_t current_divide = 0; + uint32_t mul_freq = 0; + uint32_t max_fract = 256; + + /* Compute the max fract number */ + max_fract = targetFreq * 4096U / sourceFreq + 1U; + if (max_fract > 256U) + { + max_fract = 256U; + } + + /* Looking for the closet frequency */ + for (fract = 1; fract < max_fract; fract++) + { + mul_freq = sourceFreq * fract; + remaind = mul_freq % targetFreq; + divide = (uint16_t)(mul_freq / targetFreq); + + /* Find the exactly frequency */ + if (remaind == 0U) + { + current_fract = fract; + current_divide = (uint16_t)(mul_freq / targetFreq); + break; + } + + /* Closer to next one, set the closest to next data */ + if (remaind > mclk_Hz / 2U) + { + remaind = targetFreq - remaind; + divide += 1U; + } + + /* Update the closest div and fract */ + if (remaind < current_remainder) + { + current_fract = fract; + current_divide = divide; + current_remainder = remaind; + } + } + + /* Fill the computed fract and divider to registers */ + base->MDR = I2S_MDR_DIVIDE(current_divide - 1UL) | I2S_MDR_FRACT(current_fract - 1UL); + + /* Waiting for the divider updated */ + while ((base->MCR & I2S_MCR_DUF_MASK) != 0UL) + { + } +#endif +} +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +static uint32_t SAI_GetInstance(I2S_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_saiBases); instance++) + { + if (s_saiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_saiBases)); + + return instance; +} + +static void SAI_WriteNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint8_t bitWidth, + uint8_t *buffer, + uint32_t size) +{ + uint32_t i = 0, j = 0U; + uint8_t m = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + uint32_t temp = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + for (j = channel; j <= endChannel; j++) + { + if (IS_SAI_FLAG_SET((1UL << j), channelMask)) + { + for (m = 0; m < bytesPerWord; m++) + { + temp = (uint32_t)(*buffer); + data |= (temp << (8U * m)); + buffer++; + } + base->TDR[j] = data; + data = 0; + } + } + } +} + +static void SAI_ReadNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint8_t bitWidth, + uint8_t *buffer, + uint32_t size) +{ + uint32_t i = 0, j = 0; + uint8_t m = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + for (j = channel; j <= endChannel; j++) + { + if (IS_SAI_FLAG_SET((1UL << j), channelMask)) + { + data = base->RDR[j]; + for (m = 0; m < bytesPerWord; m++) + { + *buffer = (uint8_t)(data >> (8U * m)) & 0xFFU; + buffer++; + } + } + } + } +} + +static void SAI_GetCommonConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + (void)memset(config, 0, sizeof(sai_transceiver_t)); + + config->channelMask = (uint8_t)saiChannelMask; + /* sync mode default configurations */ + config->syncMode = kSAI_ModeAsync; + + /* master mode default */ + config->masterSlave = kSAI_Master; + + /* bit default configurations */ + config->bitClock.bclkSrcSwap = false; + config->bitClock.bclkInputDelay = false; + config->bitClock.bclkPolarity = kSAI_SampleOnRisingEdge; + config->bitClock.bclkSource = kSAI_BclkSourceMclkDiv; + + /* frame sync default configurations */ + config->frameSync.frameSyncWidth = (uint8_t)bitWidth; + config->frameSync.frameSyncEarly = true; +#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND + config->frameSync.frameSyncGenerateOnDemand = false; +#endif + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveLow; + + /* serial data default configurations */ +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE + config->serialData.dataMode = kSAI_DataPinStateOutputZero; +#endif + config->serialData.dataOrder = kSAI_DataMSB; + config->serialData.dataWord0Length = (uint8_t)bitWidth; + config->serialData.dataWordLength = (uint8_t)bitWidth; + config->serialData.dataWordNLength = (uint8_t)bitWidth; + config->serialData.dataFirstBitShifted = (uint8_t)bitWidth; + config->serialData.dataWordNum = 2U; + config->serialData.dataMaskedWord = (uint32_t)mode; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* fifo configurations */ + config->fifo.fifoWatermark = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNT / 2U); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + config->fifo.fifoContinueOneError = true; +#endif +} + +/*! + * brief Initializes the SAI Tx peripheral. + * + * deprecated Do not use this function. It has been superceded by @ref SAI_Init + * + * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_TxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault + * because the clock is not enabled. + * + * param base SAI base pointer + * param config SAI configuration structure. + */ +void SAI_TxInit(I2S_Type *base, const sai_config_t *config) +{ + uint32_t val = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SAI clock */ + (void)CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + + SAI_TxReset(base); + + /* Configure audio protocol */ + if (config->protocol == kSAI_BusLeftJustified) + { + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + } + else if (config->protocol == kSAI_BusRightJustified) + { + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + } + else if (config->protocol == kSAI_BusI2S) + { + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(1U) | I2S_TCR4_FRSZ(1U); + } + else if (config->protocol == kSAI_BusPCMA) + { + base->TCR2 &= ~I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + } + else + { + base->TCR2 &= ~I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + } + + /* Set master or slave */ + if (config->masterSlave == kSAI_Master) + { + base->TCR2 |= I2S_TCR2_BCD_MASK; + base->TCR4 |= I2S_TCR4_FSD_MASK; + + /* Bit clock source setting */ + val = base->TCR2 & (~I2S_TCR2_MSEL_MASK); + base->TCR2 = (val | I2S_TCR2_MSEL(config->bclkSource)); + } + else + { + base->TCR2 &= ~I2S_TCR2_BCD_MASK; + base->TCR4 &= ~I2S_TCR4_FSD_MASK; + } + + /* Set Sync mode */ + if (config->syncMode == kSAI_ModeAsync) + { + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + } + if (config->syncMode == kSAI_ModeSync) + { + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(1U)); + /* If sync with Rx, should set Rx to async mode */ + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + } +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + if (config->syncMode == kSAI_ModeSyncWithOtherTx) + { + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(2U)); + } + if (config->syncMode == kSAI_ModeSyncWithOtherRx) + { + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(3U)); + } +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + SAI_TxSetFIFOErrorContinue(base, true); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ +} + +/*! + * brief Initializes the SAI Rx peripheral. + * + * deprecated Do not use this function. It has been superceded by @ref SAI_Init + * + * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_RxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault + * because the clock is not enabled. + * + * param base SAI base pointer + * param config SAI configuration structure. + */ +void SAI_RxInit(I2S_Type *base, const sai_config_t *config) +{ + uint32_t val = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable SAI clock first. */ + (void)CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + + SAI_RxReset(base); + + /* Configure audio protocol */ + if (config->protocol == kSAI_BusLeftJustified) + { + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + } + else if (config->protocol == kSAI_BusRightJustified) + { + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + } + else if (config->protocol == kSAI_BusI2S) + { + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(1U) | I2S_RCR4_FRSZ(1U); + } + else if (config->protocol == kSAI_BusPCMA) + { + base->RCR2 &= ~I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + } + else + { + base->RCR2 &= ~I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + } + + /* Set master or slave */ + if (config->masterSlave == kSAI_Master) + { + base->RCR2 |= I2S_RCR2_BCD_MASK; + base->RCR4 |= I2S_RCR4_FSD_MASK; + + /* Bit clock source setting */ + val = base->RCR2 & (~I2S_RCR2_MSEL_MASK); + base->RCR2 = (val | I2S_RCR2_MSEL(config->bclkSource)); + } + else + { + base->RCR2 &= ~I2S_RCR2_BCD_MASK; + base->RCR4 &= ~I2S_RCR4_FSD_MASK; + } + + /* Set Sync mode */ + if (config->syncMode == kSAI_ModeAsync) + { + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + } + if (config->syncMode == kSAI_ModeSync) + { + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(1U)); + /* If sync with Tx, should set Tx to async mode */ + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + } +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + if (config->syncMode == kSAI_ModeSyncWithOtherTx) + { + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(2U)); + } + if (config->syncMode == kSAI_ModeSyncWithOtherRx) + { + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(3U)); + } +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + SAI_RxSetFIFOErrorContinue(base, true); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ +} + +/*! + * brief Initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock. + * + * param base SAI base pointer + */ +void SAI_Init(I2S_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SAI clock */ + (void)CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* disable interrupt and DMA request*/ + base->TCSR &= + ~(I2S_TCSR_FRIE_MASK | I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK | I2S_TCSR_FRDE_MASK | I2S_TCSR_FWDE_MASK); + base->RCSR &= + ~(I2S_RCSR_FRIE_MASK | I2S_RCSR_FWIE_MASK | I2S_RCSR_FEIE_MASK | I2S_RCSR_FRDE_MASK | I2S_RCSR_FWDE_MASK); +#else + /* disable interrupt and DMA request*/ + base->TCSR &= ~(I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK | I2S_TCSR_FWDE_MASK); + base->RCSR &= ~(I2S_RCSR_FWIE_MASK | I2S_RCSR_FEIE_MASK | I2S_RCSR_FWDE_MASK); +#endif +} + +/*! + * brief De-initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit + * or SAI_RxInit is called to enable the clock. + * + * param base SAI base pointer + */ +void SAI_Deinit(I2S_Type *base) +{ + SAI_TxEnable(base, false); + SAI_RxEnable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + (void)CLOCK_DisableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Sets the SAI Tx configuration structure to default values. + * + * deprecated Do not use this function. It has been superceded by @ref + * SAI_GetClassicI2SConfig, SAI_GetLeftJustifiedConfig,SAI_GetRightJustifiedConfig, SAI_GetDSPConfig,SAI_GetTDMConfig + * + * This API initializes the configuration structure for use in SAI_TxConfig(). + * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified + * before calling SAI_TxConfig(). + * This is an example. + code + sai_config_t config; + SAI_TxGetDefaultConfig(&config); + endcode + * + * param config pointer to master configuration structure + */ +void SAI_TxGetDefaultConfig(sai_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->bclkSource = kSAI_BclkSourceMclkDiv; + config->masterSlave = kSAI_Master; +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + config->mclkOutputEnable = true; +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + config->mclkSource = kSAI_MclkSourceSysclk; +#endif +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + config->protocol = kSAI_BusI2S; + config->syncMode = kSAI_ModeAsync; +} + +/*! + * brief Sets the SAI Rx configuration structure to default values. + * + * deprecated Do not use this function. It has been superceded by @ref + * SAI_GetClassicI2SConfig,SAI_GetLeftJustifiedConfig,SAI_GetRightJustifiedConfig,SAI_GetDSPConfig,SAI_GetTDMConfig + * + * This API initializes the configuration structure for use in SAI_RxConfig(). + * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified + * before calling SAI_RxConfig(). + * This is an example. + code + sai_config_t config; + SAI_RxGetDefaultConfig(&config); + endcode + * + * param config pointer to master configuration structure + */ +void SAI_RxGetDefaultConfig(sai_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->bclkSource = kSAI_BclkSourceMclkDiv; + config->masterSlave = kSAI_Master; +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + config->mclkOutputEnable = true; +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + config->mclkSource = kSAI_MclkSourceSysclk; +#endif +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + config->protocol = kSAI_BusI2S; + config->syncMode = kSAI_ModeSync; +} + +/*! + * brief Resets the SAI Tx. + * + * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. + * + * param base SAI base pointer + */ +void SAI_TxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->TCSR = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->TCSR &= ~I2S_TCSR_SR_MASK; + + /* Reset all Tx register values */ + base->TCR2 = 0; + base->TCR3 = 0; + base->TCR4 = 0; + base->TCR5 = 0; + base->TMR = 0; +} + +/*! + * brief Resets the SAI Rx. + * + * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. + * + * param base SAI base pointer + */ +void SAI_RxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->RCSR = I2S_RCSR_SR_MASK | I2S_RCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->RCSR &= ~I2S_RCSR_SR_MASK; + + /* Reset all Rx register values */ + base->RCR2 = 0; + base->RCR3 = 0; + base->RCR4 = 0; + base->RCR5 = 0; + base->RMR = 0; +} + +/*! + * brief Enables/disables the SAI Tx. + * + * param base SAI base pointer + * param enable True means enable SAI Tx, false means disable. + */ +void SAI_TxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Rx, should enable RE bit. */ + if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) == 0x1U) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + } + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + /* Also need to clear the FIFO error flag before start */ + SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag); + } + else + { + /* If Rx not in sync with Tx, then disable Tx, otherwise, shall not disable Tx */ + if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) != 0x1U) + { + /* Disable TE bit */ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~I2S_TCSR_TE_MASK)); + } + } +} + +/*! + * brief Enables/disables the SAI Rx. + * + * param base SAI base pointer + * param enable True means enable SAI Rx, false means disable. + */ +void SAI_RxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Tx, should enable TE bit. */ + if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) == 0x1U) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + } + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + /* Also need to clear the FIFO error flag before start */ + SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag); + } + else + { + /* If Tx not in sync with Rx, then disable Rx, otherwise, shall not disable Rx */ + if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) != 0x1U) + { + /* Disable RE bit */ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~I2S_RCSR_RE_MASK)); + } + } +} + +/*! + * brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like TCR1~TCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * param base SAI base pointer + * param type Reset type, FIFO reset or software reset + */ +void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type) +{ + base->TCSR |= (uint32_t)type; + + /* Clear the software reset */ + base->TCSR &= ~I2S_TCSR_SR_MASK; +} + +/*! + * brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like RCR1~RCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * param base SAI base pointer + * param type Reset type, FIFO reset or software reset + */ +void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type) +{ + base->RCSR |= (uint32_t)type; + + /* Clear the software reset */ + base->RCSR &= ~I2S_RCSR_SR_MASK; +} + +/*! + * brief Set the Tx channel FIFO enable mask. + * + * param base SAI base pointer + * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) +{ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(mask); +} + +/*! + * brief Set the Rx channel FIFO enable mask. + * + * param base SAI base pointer + * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) +{ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + base->RCR3 |= I2S_RCR3_RCE(mask); +} + +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order) +{ + uint32_t val = (base->TCR4) & (~I2S_TCR4_MF_MASK); + + val |= I2S_TCR4_MF(order); + base->TCR4 = val; +} + +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order) +{ + uint32_t val = (base->RCR4) & (~I2S_RCR4_MF_MASK); + + val |= I2S_RCR4_MF(order); + base->RCR4 = val; +} + +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->TCR2) & (~I2S_TCR2_BCP_MASK); + + val |= I2S_TCR2_BCP(polarity); + base->TCR2 = val; +} + +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->RCR2) & (~I2S_RCR2_BCP_MASK); + + val |= I2S_RCR2_BCP(polarity); + base->RCR2 = val; +} + +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->TCR4) & (~I2S_TCR4_FSP_MASK); + + val |= I2S_TCR4_FSP(polarity); + base->TCR4 = val; +} + +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->RCR4) & (~I2S_RCR4_FSP_MASK); + + val |= I2S_RCR4_FSP(polarity); + base->RCR4 = val; +} + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * brief Set Tx FIFO packing feature. + * + * param base SAI base pointer. + * param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) +{ + uint32_t val = base->TCR4; + + val &= ~I2S_TCR4_FPACK_MASK; + val |= I2S_TCR4_FPACK(pack); + base->TCR4 = val; +} + +/*! + * brief Set Rx FIFO packing feature. + * + * param base SAI base pointer. + * param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) +{ + uint32_t val = base->RCR4; + + val &= ~I2S_RCR4_FPACK_MASK; + val |= I2S_RCR4_FPACK(pack); + base->RCR4 = val; +} +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +/*! + * brief Transmitter bit clock rate configurations. + * + * param base SAI base pointer. + * param sourceClockHz, bit clock source frequency. + * param sampleRate audio data sample rate. + * param bitWidth, audio data bitWidth. + * param channelNumbers, audio channel numbers. + */ +void SAI_TxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) +{ + uint32_t tcr2 = base->TCR2; + uint32_t bitClockDiv = 0; + uint32_t bitClockFreq = sampleRate * bitWidth * channelNumbers; + + assert(sourceClockHz >= bitClockFreq); + + tcr2 &= ~I2S_TCR2_DIV_MASK; + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + bitClockDiv = sourceClockHz / bitClockFreq; + /* for the condition where the source clock is smaller than target bclk */ + if (bitClockDiv == 0U) + { + bitClockDiv++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((sourceClockHz / bitClockDiv) > bitClockFreq) + { + bitClockDiv++; + } + +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (bitClockDiv == 1U) + { + tcr2 |= I2S_TCR2_BYP_MASK; + } + else +#endif + { + tcr2 |= I2S_TCR2_DIV(bitClockDiv / 2U - 1UL); + } + + base->TCR2 = tcr2; +} + +/*! + * brief Receiver bit clock rate configurations. + * + * param base SAI base pointer. + * param sourceClockHz, bit clock source frequency. + * param sampleRate audio data sample rate. + * param bitWidth, audio data bitWidth. + * param channelNumbers, audio channel numbers. + */ +void SAI_RxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) +{ + uint32_t rcr2 = base->RCR2; + uint32_t bitClockDiv = 0; + uint32_t bitClockFreq = sampleRate * bitWidth * channelNumbers; + + assert(sourceClockHz >= bitClockFreq); + + rcr2 &= ~I2S_RCR2_DIV_MASK; + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + bitClockDiv = sourceClockHz / bitClockFreq; + /* for the condition where the source clock is smaller than target bclk */ + if (bitClockDiv == 0U) + { + bitClockDiv++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((sourceClockHz / bitClockDiv) > bitClockFreq) + { + bitClockDiv++; + } + +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (bitClockDiv == 1U) + { + rcr2 |= I2S_RCR2_BYP_MASK; + } + else +#endif + { + rcr2 |= I2S_RCR2_DIV(bitClockDiv / 2U - 1UL); + } + + base->RCR2 = rcr2; +} + +/*! + * brief Transmitter Bit clock configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config) +{ + uint32_t tcr2 = base->TCR2; + + if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Master_FrameSync_Slave)) + { + assert(config != NULL); + + tcr2 &= ~(I2S_TCR2_BCD_MASK | I2S_TCR2_BCP_MASK | I2S_TCR2_BCI_MASK | I2S_TCR2_BCS_MASK | I2S_TCR2_MSEL_MASK); + tcr2 |= I2S_TCR2_BCD(1U) | I2S_TCR2_BCP(config->bclkPolarity) | I2S_TCR2_BCI(config->bclkInputDelay) | + I2S_TCR2_BCS(config->bclkSrcSwap) | I2S_TCR2_MSEL(config->bclkSource); + } + else + { + tcr2 &= ~(I2S_TCR2_BCD_MASK); + tcr2 |= I2S_TCR2_BCP(config->bclkPolarity); + } + + base->TCR2 = tcr2; +} + +/*! + * brief Receiver Bit clock configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config) +{ + uint32_t rcr2 = base->RCR2; + + if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Master_FrameSync_Slave)) + { + assert(config != NULL); + + rcr2 &= ~(I2S_RCR2_BCD_MASK | I2S_RCR2_BCP_MASK | I2S_RCR2_BCI_MASK | I2S_RCR2_BCS_MASK | I2S_RCR2_MSEL_MASK); + rcr2 |= I2S_RCR2_BCD(1U) | I2S_RCR2_BCP(config->bclkPolarity) | I2S_RCR2_BCI(config->bclkInputDelay) | + I2S_RCR2_BCS(config->bclkSrcSwap) | I2S_RCR2_MSEL(config->bclkSource); + } + else + { + rcr2 &= ~(I2S_RCR2_BCD_MASK); + rcr2 |= I2S_RCR2_BCP(config->bclkPolarity); + } + + base->RCR2 = rcr2; +} + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) +/*! + * brief Master clock configurations. + * + * param base SAI base pointer. + * param config master clock configurations. + */ +void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config) +{ + assert(config != NULL); + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + uint32_t val = 0; +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + +#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV))) + /* Check if master clock divider enabled, then set master clock divider */ + if (config->mclkOutputEnable) + { + SAI_SetMasterClockDivider(base, config->mclkHz, config->mclkSourceClkHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ +} +#endif + +#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE +/*! + * brief SAI transmitter fifo configurations. + * + * param base SAI base pointer. + * param config fifo configurations. + */ +void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config) +{ + assert(config != NULL); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + assert(config->fifoWatermark <= (I2S_TCR1_TFW_MASK >> I2S_TCR1_TFW_SHIFT)); +#endif + + uint32_t tcr4 = base->TCR4; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE + tcr4 &= ~I2S_TCR4_FCOMB_MASK; + tcr4 |= I2S_TCR4_FCOMB(config->fifoCombine); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + tcr4 &= ~I2S_TCR4_FCONT_MASK; + /* ERR05144: not set FCONT = 1 when TMR > 0, the transmit shift register may not load correctly that will cause TX + * not work */ + if (base->TMR == 0U) + { + tcr4 |= I2S_TCR4_FCONT(config->fifoContinueOneError); + } +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING + tcr4 &= ~I2S_TCR4_FPACK_MASK; + tcr4 |= I2S_TCR4_FPACK(config->fifoPacking); +#endif + + base->TCR4 = tcr4; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + base->TCR1 = (base->TCR1 & (~I2S_TCR1_TFW_MASK)) | I2S_TCR1_TFW(config->fifoWatermark); +#endif +} + +/*! + * brief SAI receiver fifo configurations. + * + * param base SAI base pointer. + * param config fifo configurations. + */ +void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config) +{ + assert(config != NULL); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + assert(config->fifoWatermark <= (I2S_TCR1_TFW_MASK >> I2S_TCR1_TFW_SHIFT)); +#endif + uint32_t rcr4 = base->RCR4; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE + rcr4 &= ~I2S_RCR4_FCOMB_MASK; + rcr4 |= I2S_RCR4_FCOMB(config->fifoCombine); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + rcr4 &= ~I2S_RCR4_FCONT_MASK; + rcr4 |= I2S_RCR4_FCONT(config->fifoContinueOneError); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING + rcr4 &= ~I2S_RCR4_FPACK_MASK; + rcr4 |= I2S_RCR4_FPACK(config->fifoPacking); +#endif + + base->RCR4 = rcr4; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + base->RCR1 = (base->RCR1 & (~I2S_RCR1_RFW_MASK)) | I2S_RCR1_RFW(config->fifoWatermark); +#endif +} +#endif + +/*! + * brief SAI transmitter Frame sync configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config) +{ + assert(config != NULL); + assert((config->frameSyncWidth - 1UL) <= (I2S_TCR4_SYWD_MASK >> I2S_TCR4_SYWD_SHIFT)); + + uint32_t tcr4 = base->TCR4; + + tcr4 &= ~(I2S_TCR4_FSE_MASK | I2S_TCR4_FSP_MASK | I2S_TCR4_FSD_MASK | I2S_TCR4_SYWD_MASK); + +#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND + tcr4 &= ~I2S_TCR4_ONDEM_MASK; + tcr4 |= I2S_TCR4_ONDEM(config->frameSyncGenerateOnDemand); +#endif + + tcr4 |= + I2S_TCR4_FSE(config->frameSyncEarly) | I2S_TCR4_FSP(config->frameSyncPolarity) | + I2S_TCR4_FSD(((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Slave_FrameSync_Master)) ? 1UL : 0U) | + I2S_TCR4_SYWD(config->frameSyncWidth - 1UL); + + base->TCR4 = tcr4; +} + +/*! + * brief SAI receiver Frame sync configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config) +{ + assert(config != NULL); + assert((config->frameSyncWidth - 1UL) <= (I2S_RCR4_SYWD_MASK >> I2S_RCR4_SYWD_SHIFT)); + + uint32_t rcr4 = base->RCR4; + + rcr4 &= ~(I2S_RCR4_FSE_MASK | I2S_RCR4_FSP_MASK | I2S_RCR4_FSD_MASK | I2S_RCR4_SYWD_MASK); + +#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND + rcr4 &= ~I2S_RCR4_ONDEM_MASK; + rcr4 |= I2S_RCR4_ONDEM(config->frameSyncGenerateOnDemand); +#endif + + rcr4 |= + I2S_RCR4_FSE(config->frameSyncEarly) | I2S_RCR4_FSP(config->frameSyncPolarity) | + I2S_RCR4_FSD(((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Slave_FrameSync_Master)) ? 1UL : 0U) | + I2S_RCR4_SYWD(config->frameSyncWidth - 1UL); + + base->RCR4 = rcr4; +} + +/*! + * brief SAI transmitter Serial data configurations. + * + * param base SAI base pointer. + * param config serial data configurations. + */ +void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config) +{ + assert(config != NULL); + + uint32_t tcr4 = base->TCR4; + + base->TCR5 = I2S_TCR5_WNW(config->dataWordNLength - 1UL) | I2S_TCR5_W0W(config->dataWord0Length - 1UL) | + I2S_TCR5_FBT(config->dataFirstBitShifted - 1UL); + base->TMR = config->dataMaskedWord; +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + /* ERR05144: not set FCONT = 1 when TMR > 0, the transmit shift register may not load correctly that will cause TX + * not work */ + if (config->dataMaskedWord > 0U) + { + tcr4 &= ~I2S_TCR4_FCONT_MASK; + } +#endif + tcr4 &= ~(I2S_TCR4_FRSZ_MASK | I2S_TCR4_MF_MASK); + tcr4 |= I2S_TCR4_FRSZ(config->dataWordNum - 1UL) | I2S_TCR4_MF(config->dataOrder); + +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE + tcr4 &= ~I2S_TCR4_CHMOD_MASK; + tcr4 |= I2S_TCR4_CHMOD(config->dataMode); +#endif + + base->TCR4 = tcr4; +} + +/*! + * @brief SAI receiver Serial data configurations. + * + * @param base SAI base pointer. + * @param config serial data configurations. + */ +void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config) +{ + assert(config != NULL); + + uint32_t rcr4 = base->RCR4; + + base->RCR5 = I2S_RCR5_WNW(config->dataWordNLength - 1UL) | I2S_RCR5_W0W(config->dataWord0Length - 1UL) | + I2S_RCR5_FBT(config->dataFirstBitShifted - 1UL); + base->RMR = config->dataMaskedWord; + + rcr4 &= ~(I2S_RCR4_FRSZ_MASK | I2S_RCR4_MF_MASK); + rcr4 |= I2S_RCR4_FRSZ(config->dataWordNum - 1uL) | I2S_RCR4_MF(config->dataOrder); + + base->RCR4 = rcr4; +} + +/*! + * brief SAI transmitter configurations. + * + * param base SAI base pointer. + * param config transmitter configurations. + */ +void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config) +{ + assert(config != NULL); + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint8_t i = 0U; + uint32_t val = 0U; + uint8_t channelNums = 0U; + + /* reset transmitter */ + SAI_TxReset(base); + + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (config->channelMask == 0U) + { + config->channelMask = 1U << config->startChannel; + } + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET(1UL << i, config->channelMask)) + { + channelNums++; + config->endChannel = i; + } + } + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), config->channelMask)) + { + config->startChannel = i; + break; + } + } + + config->channelNums = channelNums; +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (config->channelNums > 1U) + { + base->TCR4 &= ~I2S_TCR4_FCOMB_MASK; + } +#endif + + /* Set data channel */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(config->channelMask); + + if (config->syncMode == kSAI_ModeAsync) + { + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + } + if (config->syncMode == kSAI_ModeSync) + { + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(1U)); + /* If sync with Rx, should set Rx to async mode */ + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + } +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + if (config->syncMode == kSAI_ModeSyncWithOtherTx) + { + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(2U)); + } + if (config->syncMode == kSAI_ModeSyncWithOtherRx) + { + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(3U)); + } +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ + + /* bit clock configurations */ + SAI_TxSetBitclockConfig(base, config->masterSlave, &config->bitClock); + /* serial data configurations */ + SAI_TxSetSerialDataConfig(base, &config->serialData); + /* frame sync configurations */ + SAI_TxSetFrameSyncConfig(base, config->masterSlave, &config->frameSync); +#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE + /* fifo configurations */ + SAI_TxSetFifoConfig(base, &config->fifo); +#endif +} + +/*! + * brief SAI transmitter transfer configurations. + * + * This function initializes the TX, include bit clock, frame sync, master clock, serial data and fifo configurations. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param config tranmitter configurations. + */ +void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + assert(config->channelNums <= (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + + handle->bitWidth = config->frameSync.frameSyncWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = config->fifo.fifoWatermark; +#endif + + /* transmitter configurations */ + SAI_TxSetConfig(base, config); + + handle->channel = config->startChannel; + /* used for multi channel */ + handle->channelMask = config->channelMask; + handle->channelNums = config->channelNums; + handle->endChannel = config->endChannel; +} + +/*! + * brief SAI receiver configurations. + * + * param base SAI base pointer. + * param config transmitter configurations. + */ +void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config) +{ + assert(config != NULL); + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint8_t i = 0U; + uint32_t val = 0U; + uint8_t channelNums = 0U; + + /* reset receiver */ + SAI_RxReset(base); + + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (config->channelMask == 0U) + { + config->channelMask = 1U << config->startChannel; + } + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), config->channelMask)) + { + channelNums++; + config->endChannel = i; + } + } + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), config->channelMask)) + { + config->startChannel = i; + break; + } + } + + config->channelNums = channelNums; +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (config->channelNums > 1U) + { + base->RCR4 &= ~I2S_RCR4_FCOMB_MASK; + } +#endif + + /* Set data channel */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + base->RCR3 |= I2S_RCR3_RCE(config->channelMask); + + /* Set Sync mode */ + if (config->syncMode == kSAI_ModeAsync) + { + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + } + if (config->syncMode == kSAI_ModeSync) + { + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(1U)); + /* If sync with Tx, should set Tx to async mode */ + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + } +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + if (config->syncMode == kSAI_ModeSyncWithOtherTx) + { + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(2U)); + } + if (config->syncMode == kSAI_ModeSyncWithOtherRx) + { + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(3U)); + } +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ + + /* bit clock configurations */ + SAI_RxSetBitclockConfig(base, config->masterSlave, &config->bitClock); + /* serial data configurations */ + SAI_RxSetSerialDataConfig(base, &config->serialData); + /* frame sync configurations */ + SAI_RxSetFrameSyncConfig(base, config->masterSlave, &config->frameSync); +#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE + /* fifo configurations */ + SAI_RxSetFifoConfig(base, &config->fifo); +#endif +} + +/*! + * brief SAI receiver transfer configurations. + * + * This function initializes the TX, include bit clock, frame sync, master clock, serial data and fifo configurations. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param config tranmitter configurations. + */ +void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + + handle->bitWidth = config->frameSync.frameSyncWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = config->fifo.fifoWatermark; +#endif + + /* receiver configurations */ + SAI_RxSetConfig(base, config); + + handle->channel = config->startChannel; + /* used for multi channel */ + handle->channelMask = config->channelMask; + handle->channelNums = config->channelNums; + handle->endChannel = config->endChannel; +} + +/*! + * brief Get classic I2S mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetClassicI2SConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); +} + +/*! + * brief Get left justified mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); + + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; +} + +/*! + * brief Get right justified mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetRightJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); + + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; +} + +/*! + * brief Get DSP mode configurations. + * + * note DSP mode is also called PCM mode which support MODE A and MODE B, + * DSP/PCM MODE A configuration flow. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig: + * code + * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask) + * config->frameSync.frameSyncEarly = true; + * SAI_TxSetConfig(base, config) + * endcode + * + * DSP/PCM MODE B configuration flow for TX. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig: + * code + * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask) + * SAI_TxSetConfig(base, config) + * endcode + * + * param config transceiver configurations. + * param frameSyncWidth length of frame sync. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask mask value of the channel to enable. + */ +void SAI_GetDSPConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); + + /* frame sync default configurations */ + switch (frameSyncWidth) + { + case kSAI_FrameSyncLenOneBitClk: + config->frameSync.frameSyncWidth = 1U; + break; + default: + assert(false); + break; + } + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; +} + +/*! + * brief Get TDM mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetTDMConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + uint32_t dataWordNum, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + assert(dataWordNum <= 32U); + + SAI_GetCommonConfig(config, bitWidth, kSAI_Stereo, saiChannelMask); + + /* frame sync default configurations */ + switch (frameSyncWidth) + { + case kSAI_FrameSyncLenOneBitClk: + config->frameSync.frameSyncWidth = 1U; + break; + case kSAI_FrameSyncLenPerWordWidth: + break; + default: + assert(false); + break; + } + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; + config->serialData.dataWordNum = (uint8_t)dataWordNum; +} + +/*! + * brief Configures the SAI Tx audio format. + * + * deprecated Do not use this function. It has been superceded by @ref SAI_TxSetConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. + */ +void SAI_TxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint32_t bclk = 0; + uint32_t val = 0; + uint8_t i = 0U, channelNums = 0U; + uint32_t divider = 0U; + + if (format->isFrameSyncCompact) + { + bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); + val = (base->TCR4 & (~I2S_TCR4_SYWD_MASK)); + val |= I2S_TCR4_SYWD(format->bitWidth - 1U); + base->TCR4 = val; + } + else + { + bclk = format->sampleRate_Hz * 32U * 2U; + } + +/* Compute the mclk */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + /* Check if master clock divider enabled, then set master clock divider */ + if (IS_SAI_FLAG_SET(base->MCR, I2S_MCR_MOE_MASK)) + { + SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + + /* Set bclk if needed */ + if (IS_SAI_FLAG_SET(base->TCR2, I2S_TCR2_BCD_MASK)) + { + base->TCR2 &= ~I2S_TCR2_DIV_MASK; + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + divider = bclkSourceClockHz / bclk; + /* for the condition where the source clock is smaller than target bclk */ + if (divider == 0U) + { + divider++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((bclkSourceClockHz / divider) > bclk) + { + divider++; + } + +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (divider == 1U) + { + base->TCR2 |= I2S_TCR2_BYP_MASK; + } + else +#endif + { + base->TCR2 |= I2S_TCR2_DIV(divider / 2U - 1U); + } + } + + /* Set bitWidth */ + val = (format->isFrameSyncCompact) ? (format->bitWidth - 1U) : 31U; + if (format->protocol == kSAI_BusRightJustified) + { + base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(val); + } + else + { + if (IS_SAI_FLAG_SET(base->TCR4, I2S_TCR4_MF_MASK)) + { + base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1UL); + } + else + { + base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(0); + } + } + + /* Set mono or stereo */ + base->TMR = (uint32_t)format->stereo; + + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (format->channelMask == 0U) + { + format->channelMask = 1U << format->channel; + } + + /* if channel nums is not set, calculate it here according to channelMask*/ + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), format->channelMask)) + { + channelNums++; + format->endChannel = i; + } + } + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), format->channelMask)) + { + format->channel = i; + break; + } + } + + format->channelNums = channelNums; +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (format->channelNums > 1U) + { + base->TCR4 &= ~I2S_TCR4_FCOMB_MASK; + } +#endif + + /* Set data channel */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(format->channelMask); + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Set watermark */ + base->TCR1 = format->watermark; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +/*! + * brief Configures the SAI Rx audio format. + * + * deprecated Do not use this function. It has been superceded by @ref SAI_RxSetConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. + */ +void SAI_RxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint32_t bclk = 0; + uint32_t val = 0; + uint8_t i = 0U, channelNums = 0U; + uint32_t divider = 0U; + + if (format->isFrameSyncCompact) + { + bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); + val = (base->RCR4 & (~I2S_RCR4_SYWD_MASK)); + val |= I2S_RCR4_SYWD(format->bitWidth - 1U); + base->RCR4 = val; + } + else + { + bclk = format->sampleRate_Hz * 32U * 2U; + } + +/* Compute the mclk */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + /* Check if master clock divider enabled */ + if (IS_SAI_FLAG_SET(base->MCR, I2S_MCR_MOE_MASK)) + { + SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + + /* Set bclk if needed */ + if (IS_SAI_FLAG_SET(base->RCR2, I2S_RCR2_BCD_MASK)) + { + base->RCR2 &= ~I2S_RCR2_DIV_MASK; + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + divider = bclkSourceClockHz / bclk; + /* for the condition where the source clock is smaller than target bclk */ + if (divider == 0U) + { + divider++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((bclkSourceClockHz / divider) > bclk) + { + divider++; + } +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (divider == 1U) + { + base->RCR2 |= I2S_RCR2_BYP_MASK; + } + else +#endif + { + base->RCR2 |= I2S_RCR2_DIV(divider / 2U - 1U); + } + } + + /* Set bitWidth */ + val = (format->isFrameSyncCompact) ? (format->bitWidth - 1U) : 31U; + if (format->protocol == kSAI_BusRightJustified) + { + base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(val); + } + else + { + if (IS_SAI_FLAG_SET(base->RCR4, I2S_RCR4_MF_MASK)) + { + base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1UL); + } + else + { + base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(0UL); + } + } + + /* Set mono or stereo */ + base->RMR = (uint32_t)format->stereo; + + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (format->channelMask == 0U) + { + format->channelMask = 1U << format->channel; + } + + /* if channel nums is not set, calculate it here according to channelMask*/ + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), format->channelMask)) + { + channelNums++; + format->endChannel = i; + } + } + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), format->channelMask)) + { + format->channel = i; + break; + } + } + + format->channelNums = channelNums; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (format->channelNums > 1U) + { + base->RCR4 &= ~I2S_RCR4_FCOMB_MASK; + } +#endif + + /* Set data channel */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + /* enable all the channel */ + base->RCR3 |= I2S_RCR3_RCE(format->channelMask); + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Set watermark */ + base->RCR1 = format->watermark; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +/*! + * brief Sends data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be written. + * param size Bytes to be written. + */ +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint32_t bytesPerWord = bitWidth / 8U; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (((uint32_t)FSL_FEATURE_SAI_FIFO_COUNT - base->TCR1) * bytesPerWord); +#endif + + while (i < size) + { + /* Wait until it can write data */ + while (!(IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK))) + { + } + + SAI_WriteNonBlocking(base, channel, 1UL << channel, channel, (uint8_t)bitWidth, buffer, bytesPerWord); + buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord); + i += bytesPerWord; + } + + /* Wait until the last data is sent */ + while (!(IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK))) + { + } +} + +/*! + * brief Sends data to multi channel using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param channelMask channel mask. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be written. + * param size Bytes to be written. + */ +void SAI_WriteMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint32_t i = 0, j = 0; + uint32_t bytesPerWord = bitWidth / 8U; + uint32_t channelNums = 0U, endChannel = 0U; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (((uint32_t)FSL_FEATURE_SAI_FIFO_COUNT - base->TCR1) * bytesPerWord); +#endif + + for (i = 0U; (i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), channelMask)) + { + channelNums++; + endChannel = i; + } + } + + bytesPerWord *= channelNums; + + while (j < size) + { + /* Wait until it can write data */ + while (!(IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK))) + { + } + + SAI_WriteNonBlocking(base, channel, channelMask, endChannel, (uint8_t)bitWidth, buffer, + bytesPerWord * channelNums); + buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord * channelNums); + j += bytesPerWord * channelNums; + } + + /* Wait until the last data is sent */ + while (!(IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK))) + { + } +} + +/*! + * brief Receives multi channel data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param channelMask channel mask. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be read. + * param size Bytes to be read. + */ +void SAI_ReadMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint32_t i = 0, j = 0; + uint32_t bytesPerWord = bitWidth / 8U; + uint32_t channelNums = 0U, endChannel = 0U; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = base->RCR1 * bytesPerWord; +#endif + for (i = 0U; (i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), channelMask)) + { + channelNums++; + endChannel = i; + } + } + + bytesPerWord *= channelNums; + + while (j < size) + { + /* Wait until data is received */ + while (!(IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FWF_MASK))) + { + } + + SAI_ReadNonBlocking(base, channel, channelMask, endChannel, (uint8_t)bitWidth, buffer, + bytesPerWord * channelNums); + buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord * channelNums); + j += bytesPerWord * channelNums; + } +} + +/*! + * brief Receives data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be read. + * param size Bytes to be read. + */ +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint32_t bytesPerWord = bitWidth / 8U; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = base->RCR1 * bytesPerWord; +#endif + + while (i < size) + { + /* Wait until data is received */ + while (!(IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FWF_MASK))) + { + } + + SAI_ReadNonBlocking(base, channel, 1UL << channel, channel, (uint8_t)bitWidth, buffer, bytesPerWord); + buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord); + i += bytesPerWord; + } +} + +/*! + * brief Initializes the SAI Tx handle. + * + * This function initializes the Tx handle for the SAI Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SAI base pointer + * param handle SAI handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function + */ +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle != NULL); + + /* Zero the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + s_saiHandle[SAI_GetInstance(base)][0] = handle; + + handle->callback = callback; + handle->userData = userData; + handle->base = base; + + /* Set the isr pointer */ + s_saiTxIsr = SAI_TransferTxHandleIRQ; + + /* Enable Tx irq */ + (void)EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); +} + +/*! + * brief Initializes the SAI Rx handle. + * + * This function initializes the Rx handle for the SAI Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function. + */ +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle != NULL); + + /* Zero the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + s_saiHandle[SAI_GetInstance(base)][1] = handle; + + handle->callback = callback; + handle->userData = userData; + handle->base = base; + + /* Set the isr pointer */ + s_saiRxIsr = SAI_TransferRxHandleIRQ; + + /* Enable Rx irq */ + (void)EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); +} + +/*! + * brief Configures the SAI Tx audio format. + * + * deprecated Do not use this function. It has been superceded by @ref SAI_TransferTxSetConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * return Status of this function. Return value is the status_t. + */ +status_t SAI_TransferTxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle != NULL); + + if ((bclkSourceClockHz < format->sampleRate_Hz) +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + || (mclkSourceClockHz < format->sampleRate_Hz) +#endif + ) + { + return kStatus_InvalidArgument; + } + + /* Copy format to handle */ + handle->bitWidth = (uint8_t)format->bitWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = format->watermark; +#endif + + SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + handle->channel = format->channel; + /* used for multi channel */ + handle->channelMask = format->channelMask; + handle->channelNums = format->channelNums; + handle->endChannel = format->endChannel; + + return kStatus_Success; +} + +/*! + * brief Configures the SAI Rx audio format. + * + * deprecated Do not use this function. It has been superceded by @ref SAI_TransferRxSetConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * return Status of this function. Return value is one of status_t. + */ +status_t SAI_TransferRxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle != NULL); + + if ((bclkSourceClockHz < format->sampleRate_Hz) +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + || (mclkSourceClockHz < format->sampleRate_Hz) +#endif + ) + { + return kStatus_InvalidArgument; + } + + /* Copy format to handle */ + handle->bitWidth = (uint8_t)format->bitWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = format->watermark; +#endif + + SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + handle->channel = format->channel; + /* used for multi channel */ + handle->channelMask = format->channelMask; + handle->channelNums = format->channelNums; + handle->endChannel = format->endChannel; + + return kStatus_Success; +} + +/*! + * brief Performs an interrupt non-blocking send transfer on SAI. + * + * note This API returns immediately after the transfer initiates. + * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param xfer Pointer to the sai_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SAI_TxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->channelNums <= (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data != NULL) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE; + + /* Set the state to busy */ + handle->state = (uint32_t)kSAI_Busy; + + /* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error*/ + SAI_TxEnableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FRIE_MASK); +#else + SAI_TxEnableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FWIE_MASK); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* Enable Tx transfer */ + SAI_TxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Performs an interrupt non-blocking receive transfer on SAI. + * + * note This API returns immediately after the transfer initiates. + * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * param base SAI base pointer + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param xfer Pointer to the sai_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SAI_RxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->channelNums <= (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data != NULL) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE; + + /* Set state to busy */ + handle->state = (uint32_t)kSAI_Busy; + +/* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error*/ + SAI_RxEnableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FRIE_MASK); +#else + SAI_RxEnableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FWIE_MASK); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* Enable Rx transfer */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Gets a set byte count. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param count Bytes count sent. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + status_t status = kStatus_Success; + uint32_t queueDriverIndex = handle->queueDriver; + + if (handle->state != (uint32_t)kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[queueDriverIndex] - handle->saiQueue[queueDriverIndex].dataSize); + } + + return status; +} + +/*! + * brief Gets a received byte count. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param count Bytes count received. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + status_t status = kStatus_Success; + uint32_t queueDriverIndex = handle->queueDriver; + + if (handle->state != (uint32_t)kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[queueDriverIndex] - handle->saiQueue[queueDriverIndex].dataSize); + } + + return status; +} + +/*! + * brief Aborts the current send. + * + * note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle != NULL); + + /* Stop Tx transfer and disable interrupt */ + SAI_TxEnable(base, false); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error */ + SAI_TxDisableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FRIE_MASK); +#else + SAI_TxDisableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FWIE_MASK); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + handle->state = (uint32_t)kSAI_Idle; + + /* Clear the queue */ + (void)memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * (uint8_t)SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +/*! + * brief Aborts the current IRQ receive. + * + * note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SAI base pointer + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle != NULL); + + /* Stop Tx transfer and disable interrupt */ + SAI_RxEnable(base, false); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error */ + SAI_RxDisableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FRIE_MASK); +#else + SAI_RxDisableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FWIE_MASK); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + handle->state = (uint32_t)kSAI_Idle; + + /* Clear the queue */ + (void)memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * (uint8_t)SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +/*! + * brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSend. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle != NULL); + + /* Abort the current transfer */ + SAI_TransferAbortSend(base, handle); + + /* Clear all the internal information */ + (void)memset(handle->saiQueue, 0, sizeof(handle->saiQueue)); + (void)memset(handle->transferSize, 0, sizeof(handle->transferSize)); + + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +/*! + * brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceive. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle != NULL); + + /* Abort the current transfer */ + SAI_TransferAbortReceive(base, handle); + + /* Clear all the internal information */ + (void)memset(handle->saiQueue, 0, sizeof(handle->saiQueue)); + (void)memset(handle->transferSize, 0, sizeof(handle->transferSize)); + + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +/*! + * brief Tx interrupt handler. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle != NULL); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint32_t dataSize = (handle->bitWidth / 8UL) * handle->channelNums; + + /* Handle Error */ + if (IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FEF_MASK)) + { + /* Clear FIFO error flag to continue transfer */ + SAI_TxClearStatusFlags(base, I2S_TCSR_FEF_MASK); + + /* Reset FIFO for safety */ + SAI_TxSoftwareReset(base, kSAI_ResetTypeFIFO); + + /* Call the callback */ + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_SAI_TxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if (IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FRF_MASK)) + { + /* Judge if the data need to transmit is less than space */ + size_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), + (size_t)(((uint32_t)FSL_FEATURE_SAI_FIFO_COUNT - handle->watermark) * dataSize)); + + /* Copy the data from sai buffer to FIFO */ + SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size); + } +#else + if (IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK)) + { + size_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); + + /* Update internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size); + } +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* If finished a block, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + (void)memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE; + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_SAI_TxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortSend(base, handle); + } +} + +/*! + * brief Tx interrupt handler. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle != NULL); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint32_t dataSize = (handle->bitWidth / 8UL) * handle->channelNums; + + /* Handle Error */ + if (IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FEF_MASK)) + { + /* Clear FIFO error flag to continue transfer */ + SAI_RxClearStatusFlags(base, I2S_TCSR_FEF_MASK); + + /* Reset FIFO for safety */ + SAI_RxSoftwareReset(base, kSAI_ResetTypeFIFO); + + /* Call the callback */ + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_SAI_RxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if (IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FRF_MASK)) + { + /* Judge if the data need to transmit is less than space */ + size_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), handle->watermark * dataSize); + + /* Copy the data from sai buffer to FIFO */ + SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size); + } +#else + if (IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FWF_MASK)) + { + size_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); + + /* Update internal state */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size); + } +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* If finished a block, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + (void)memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE; + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_SAI_RxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortReceive(base, handle); + } +} + +#if defined(I2S0) +void I2S0_DriverIRQHandler(void); +void I2S0_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[0][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S0, s_saiHandle[0][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[0][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S0, s_saiHandle[0][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S0_Tx_DriverIRQHandler(void); +void I2S0_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][0] != NULL); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S0_Rx_DriverIRQHandler(void); +void I2S0_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][1] != NULL); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif /* I2S0*/ + +#if defined(I2S1) +void I2S1_DriverIRQHandler(void); +void I2S1_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S1, s_saiHandle[1][1]); + } + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S1, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S1_Tx_DriverIRQHandler(void); +void I2S1_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][0] != NULL); + s_saiTxIsr(I2S1, s_saiHandle[1][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S1_Rx_DriverIRQHandler(void); +void I2S1_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][1] != NULL); + s_saiRxIsr(I2S1, s_saiHandle[1][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif /* I2S1*/ + +#if defined(I2S2) +void I2S2_DriverIRQHandler(void); +void I2S2_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[2][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S2, s_saiHandle[2][1]); + } + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[2][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S2, s_saiHandle[2][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S2_Tx_DriverIRQHandler(void); +void I2S2_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[2][0] != NULL); + s_saiTxIsr(I2S2, s_saiHandle[2][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S2_Rx_DriverIRQHandler(void); +void I2S2_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[2][1] != NULL); + s_saiRxIsr(I2S2, s_saiHandle[2][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif /* I2S2*/ + +#if defined(I2S3) +void I2S3_DriverIRQHandler(void); +void I2S3_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[3][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S3, s_saiHandle[3][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[3][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S3, s_saiHandle[3][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S3_Tx_DriverIRQHandler(void); +void I2S3_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][0] != NULL); + s_saiTxIsr(I2S3, s_saiHandle[3][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S3_Rx_DriverIRQHandler(void); +void I2S3_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][1] != NULL); + s_saiRxIsr(I2S3, s_saiHandle[3][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif /* I2S3*/ + +#if defined(I2S4) +void I2S4_DriverIRQHandler(void); +void I2S4_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[4][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[4][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S4, s_saiHandle[4][1]); + } + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[4][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[4][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S4, s_saiHandle[4][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S4_Tx_DriverIRQHandler(void); +void I2S4_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[4][0] != NULL); + s_saiTxIsr(I2S4, s_saiHandle[4][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S4_Rx_DriverIRQHandler(void); +void I2S4_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[4][1] != NULL); + s_saiRxIsr(I2S4, s_saiHandle[4][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ) && (FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ) && defined(I2S5) && \ + defined(I2S6) +void I2S56_DriverIRQHandler(void); +void I2S56_DriverIRQHandler(void) +{ + /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */ + I2S_Type *base = s_saiHandle[5][1]->base; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(base, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(base, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(base, s_saiHandle[5][1]); + } + + base = s_saiHandle[5][0]->base; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(base, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(base, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(base, s_saiHandle[5][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S56_Tx_DriverIRQHandler(void); +void I2S56_Tx_DriverIRQHandler(void) +{ + /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */ + assert(s_saiHandle[5][0] != NULL); + s_saiTxIsr(s_saiHandle[5][0]->base, s_saiHandle[5][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S56_Rx_DriverIRQHandler(void); +void I2S56_Rx_DriverIRQHandler(void) +{ + /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */ + assert(s_saiHandle[5][1] != NULL); + s_saiRxIsr(s_saiHandle[5][1]->base, s_saiHandle[5][1]); + SDK_ISR_EXIT_BARRIER; +} + +#else + +#if defined(I2S5) +void I2S5_DriverIRQHandler(void); +void I2S5_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S5, s_saiHandle[5][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S5, s_saiHandle[5][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S5_Tx_DriverIRQHandler(void); +void I2S5_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[5][0] != NULL); + s_saiTxIsr(I2S5, s_saiHandle[5][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S5_Rx_DriverIRQHandler(void); +void I2S5_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[5][1] != NULL); + s_saiRxIsr(I2S5, s_saiHandle[5][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(I2S6) +void I2S6_DriverIRQHandler(void); +void I2S6_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[6][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S6, s_saiHandle[6][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[6][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S6, s_saiHandle[6][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S6_Tx_DriverIRQHandler(void); +void I2S6_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[6][0] != NULL); + s_saiTxIsr(I2S6, s_saiHandle[6][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S6_Rx_DriverIRQHandler(void); +void I2S6_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[6][1] != NULL); + s_saiRxIsr(I2S6, s_saiHandle[6][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(AUDIO__SAI0) +void AUDIO_SAI0_INT_DriverIRQHandler(void); +void AUDIO_SAI0_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[0][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(AUDIO__SAI0, s_saiHandle[0][1]); + } + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[0][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(AUDIO__SAI0, s_saiHandle[0][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* AUDIO__SAI0 */ + +#if defined(AUDIO__SAI1) +void AUDIO_SAI1_INT_DriverIRQHandler(void); +void AUDIO_SAI1_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(AUDIO__SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(AUDIO__SAI1, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* AUDIO__SAI1 */ + +#if defined(AUDIO__SAI2) +void AUDIO_SAI2_INT_DriverIRQHandler(void); +void AUDIO_SAI2_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[2][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(AUDIO__SAI2, s_saiHandle[2][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[2][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(AUDIO__SAI2, s_saiHandle[2][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* AUDIO__SAI2 */ + +#if defined(AUDIO__SAI3) +void AUDIO_SAI3_INT_DriverIRQHandler(void); +void AUDIO_SAI3_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[3][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(AUDIO__SAI3, s_saiHandle[3][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[3][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(AUDIO__SAI3, s_saiHandle[3][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(AUDIO__SAI6) +void AUDIO_SAI6_INT_DriverIRQHandler(void); +void AUDIO_SAI6_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[6][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(AUDIO__SAI6, s_saiHandle[6][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[6][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(AUDIO__SAI6, s_saiHandle[6][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* AUDIO__SAI6 */ + +#if defined(AUDIO__SAI7) +void AUDIO_SAI7_INT_DriverIRQHandler(void); +void AUDIO_SAI7_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[7][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI7, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[7][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI7, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(AUDIO__SAI7, s_saiHandle[7][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[7][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI7, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[7][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI7, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(AUDIO__SAI7, s_saiHandle[7][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* AUDIO__SAI7 */ + +#if defined(ADMA__SAI0) +void ADMA_SAI0_INT_DriverIRQHandler(void); +void ADMA_SAI0_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(ADMA__SAI0, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(ADMA__SAI0, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ADMA__SAI0 */ + +#if defined(ADMA__SAI1) +void ADMA_SAI1_INT_DriverIRQHandler(void); +void ADMA_SAI1_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(ADMA__SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(ADMA__SAI1, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ADMA__SAI1 */ + +#if defined(ADMA__SAI2) +void ADMA_SAI2_INT_DriverIRQHandler(void); +void ADMA_SAI2_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(ADMA__SAI2, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(ADMA__SAI2, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ADMA__SAI2 */ + +#if defined(ADMA__SAI3) +void ADMA_SAI3_INT_DriverIRQHandler(void); +void ADMA_SAI3_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(ADMA__SAI3, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(ADMA__SAI3, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ADMA__SAI3 */ + +#if defined(ADMA__SAI4) +void ADMA_SAI4_INT_DriverIRQHandler(void); +void ADMA_SAI4_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(ADMA__SAI4, s_saiHandle[1][1]); + } + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(ADMA__SAI4, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ADMA__SAI4 */ + +#if defined(ADMA__SAI5) +void ADMA_SAI5_INT_DriverIRQHandler(void); +void ADMA_SAI5_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(ADMA__SAI5, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(ADMA__SAI5, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ADMA__SAI5 */ + +#if defined(SAI0) +void SAI0_DriverIRQHandler(void); +void SAI0_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[0][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI0, s_saiHandle[0][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[0][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI0, s_saiHandle[0][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI0 */ + +#if defined(SAI1) +void SAI1_DriverIRQHandler(void); +void SAI1_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI1, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI1 */ + +#if defined(SAI2) +void SAI2_DriverIRQHandler(void); +void SAI2_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[2][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI2, s_saiHandle[2][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[2][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI2, s_saiHandle[2][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI2 */ + +#if defined(SAI3) +void SAI3_DriverIRQHandler(void); +void SAI3_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[3][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI3, s_saiHandle[3][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[3][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI3, s_saiHandle[3][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void SAI3_TX_DriverIRQHandler(void); +void SAI3_TX_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][0] != NULL); + s_saiTxIsr(SAI3, s_saiHandle[3][0]); + SDK_ISR_EXIT_BARRIER; +} + +void SAI3_RX_DriverIRQHandler(void); +void SAI3_RX_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][1] != NULL); + s_saiRxIsr(SAI3, s_saiHandle[3][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI3 */ + +#if defined(SAI4) +void SAI4_DriverIRQHandler(void); +void SAI4_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[4][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[4][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI4, s_saiHandle[4][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[4][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[4][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI4, s_saiHandle[4][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI4 */ + +#if defined(SAI5) +void SAI5_DriverIRQHandler(void); +void SAI5_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI5, s_saiHandle[5][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI5, s_saiHandle[5][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI5 */ + +#if defined(SAI6) +void SAI6_DriverIRQHandler(void); +void SAI6_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[6][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI6, s_saiHandle[6][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[6][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI6, s_saiHandle[6][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI6 */ diff --git a/devices/MIMX8MQ6/drivers/fsl_sai.h b/devices/MIMX8MQ6/drivers/fsl_sai.h new file mode 100644 index 000000000..f82830db3 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_sai.h @@ -0,0 +1,1586 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SAI_H_ +#define _FSL_SAI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sai_driver SAI Driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) /*!< Version 2.3.3 */ +/*@}*/ + +/*! @brief _sai_status_t, SAI return status.*/ +enum +{ + kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */ + kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */ + kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */ + kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */ + kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), /*!< SAI transfer queue is full. */ + kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */ + kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */ +}; + +/*! @brief _sai_channel_mask,.sai channel mask value, actual channel numbers is depend soc specific */ +enum +{ + kSAI_Channel0Mask = 1 << 0U, /*!< channel 0 mask value */ + kSAI_Channel1Mask = 1 << 1U, /*!< channel 1 mask value */ + kSAI_Channel2Mask = 1 << 2U, /*!< channel 2 mask value */ + kSAI_Channel3Mask = 1 << 3U, /*!< channel 3 mask value */ + kSAI_Channel4Mask = 1 << 4U, /*!< channel 4 mask value */ + kSAI_Channel5Mask = 1 << 5U, /*!< channel 5 mask value */ + kSAI_Channel6Mask = 1 << 6U, /*!< channel 6 mask value */ + kSAI_Channel7Mask = 1 << 7U, /*!< channel 7 mask value */ +}; + +/*! @brief Define the SAI bus type */ +typedef enum _sai_protocol +{ + kSAI_BusLeftJustified = 0x0U, /*!< Uses left justified format.*/ + kSAI_BusRightJustified, /*!< Uses right justified format. */ + kSAI_BusI2S, /*!< Uses I2S format. */ + kSAI_BusPCMA, /*!< Uses I2S PCM A format.*/ + kSAI_BusPCMB /*!< Uses I2S PCM B format. */ +} sai_protocol_t; + +/*! @brief Master or slave mode */ +typedef enum _sai_master_slave +{ + kSAI_Master = 0x0U, /*!< Master mode include bclk and frame sync */ + kSAI_Slave = 0x1U, /*!< Slave mode include bclk and frame sync */ + kSAI_Bclk_Master_FrameSync_Slave = 0x2U, /*!< bclk in master mode, frame sync in slave mode */ + kSAI_Bclk_Slave_FrameSync_Master = 0x3U, /*!< bclk in slave mode, frame sync in master mode */ +} sai_master_slave_t; + +/*! @brief Mono or stereo audio format */ +typedef enum _sai_mono_stereo +{ + kSAI_Stereo = 0x0U, /*!< Stereo sound. */ + kSAI_MonoRight, /*!< Only Right channel have sound. */ + kSAI_MonoLeft /*!< Only left channel have sound. */ +} sai_mono_stereo_t; + +/*! @brief SAI data order, MSB or LSB */ +typedef enum _sai_data_order +{ + kSAI_DataLSB = 0x0U, /*!< LSB bit transferred first */ + kSAI_DataMSB /*!< MSB bit transferred first */ +} sai_data_order_t; + +/*! @brief SAI clock polarity, active high or low */ +typedef enum _sai_clock_polarity +{ + kSAI_PolarityActiveHigh = 0x0U, /*!< Drive outputs on rising edge */ + kSAI_PolarityActiveLow = 0x1U, /*!< Drive outputs on falling edge */ + kSAI_SampleOnFallingEdge = 0x0U, /*!< Sample inputs on falling edge */ + kSAI_SampleOnRisingEdge = 0x1U, /*!< Sample inputs on rising edge */ +} sai_clock_polarity_t; + +/*! @brief Synchronous or asynchronous mode */ +typedef enum _sai_sync_mode +{ + kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */ + kSAI_ModeSync, /*!< Synchronous mode (with receiver or transmit) */ +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + kSAI_ModeSyncWithOtherTx, /*!< Synchronous with another SAI transmit */ + kSAI_ModeSyncWithOtherRx /*!< Synchronous with another SAI receiver */ +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ +} sai_sync_mode_t; + +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) +/*! @brief Mater clock source */ +typedef enum _sai_mclk_source +{ + kSAI_MclkSourceSysclk = 0x0U, /*!< Master clock from the system clock */ + kSAI_MclkSourceSelect1, /*!< Master clock from source 1 */ + kSAI_MclkSourceSelect2, /*!< Master clock from source 2 */ + kSAI_MclkSourceSelect3 /*!< Master clock from source 3 */ +} sai_mclk_source_t; +#endif + +/*! @brief Bit clock source */ +typedef enum _sai_bclk_source +{ + kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */ + /* General device bit source definition */ + kSAI_BclkSourceMclkOption1 = 0x1U, /*!< Bit clock MCLK option 1 */ + kSAI_BclkSourceMclkOption2 = 0x2U, /*!< Bit clock MCLK option2 */ + kSAI_BclkSourceMclkOption3 = 0x3U, /*!< Bit clock MCLK option3 */ + /* Kinetis device bit clock source definition */ + kSAI_BclkSourceMclkDiv = 0x1U, /*!< Bit clock using master clock divider */ + kSAI_BclkSourceOtherSai0 = 0x2U, /*!< Bit clock from other SAI device */ + kSAI_BclkSourceOtherSai1 = 0x3U /*!< Bit clock from other SAI device */ +} sai_bclk_source_t; + +/*! @brief _sai_interrupt_enable_t, The SAI interrupt enable flag */ +enum +{ + kSAI_WordStartInterruptEnable = + I2S_TCSR_WSIE_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, /*!< FIFO warning flag, means the FIFO is empty */ + kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK, /*!< FIFO request, means reached watermark */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +}; + +/*! @brief _sai_dma_enable_t, The DMA request sources */ +enum +{ + kSAI_FIFOWarningDMAEnable = I2S_TCSR_FWDE_MASK, /*!< FIFO warning caused by the DMA request */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestDMAEnable = I2S_TCSR_FRDE_MASK, /*!< FIFO request caused by the DMA request */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +}; + +/*! @brief _sai_flags, The SAI status flag */ +enum +{ + kSAI_WordStartFlag = I2S_TCSR_WSF_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorFlag = I2S_TCSR_SEF_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOErrorFlag = I2S_TCSR_FEF_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestFlag = I2S_TCSR_FRF_MASK, /*!< FIFO request flag. */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + kSAI_FIFOWarningFlag = I2S_TCSR_FWF_MASK, /*!< FIFO warning flag */ +}; + +/*! @brief The reset type */ +typedef enum _sai_reset_type +{ + kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */ + kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */ + kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */ +} sai_reset_type_t; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief The SAI packing mode + * The mode includes 8 bit and 16 bit packing. + */ +typedef enum _sai_fifo_packing +{ + kSAI_FifoPackingDisabled = 0x0U, /*!< Packing disabled */ + kSAI_FifoPacking8bit = 0x2U, /*!< 8 bit packing enabled */ + kSAI_FifoPacking16bit = 0x3U /*!< 16bit packing enabled */ +} sai_fifo_packing_t; +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +/*! @brief SAI user configuration structure */ +typedef struct _sai_config +{ + sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ + sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */ +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */ +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + sai_mclk_source_t mclkSource; /*!< Master Clock source */ +#endif /* FSL_FEATURE_SAI_HAS_MCR */ +#endif + sai_bclk_source_t bclkSource; /*!< Bit Clock source */ + sai_master_slave_t masterSlave; /*!< Master or slave */ +} sai_config_t; + +#ifndef SAI_XFER_QUEUE_SIZE +/*!@brief SAI transfer queue size, user can refine it according to use case. */ +#define SAI_XFER_QUEUE_SIZE (4U) +#endif + +/*! @brief Audio sample rate */ +typedef enum _sai_sample_rate +{ + kSAI_SampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */ + kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ + kSAI_SampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */ + kSAI_SampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */ + kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ + kSAI_SampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */ + kSAI_SampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ + kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ + kSAI_SampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ + kSAI_SampleRate96KHz = 96000U, /*!< Sample rate 96000 Hz */ + kSAI_SampleRate192KHz = 192000U, /*!< Sample rate 192000 Hz */ + kSAI_SampleRate384KHz = 384000U, /*!< Sample rate 384000 Hz */ +} sai_sample_rate_t; + +/*! @brief Audio word width */ +typedef enum _sai_word_width +{ + kSAI_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ + kSAI_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ + kSAI_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ + kSAI_WordWidth32bits = 32U /*!< Audio data width 32 bits */ +} sai_word_width_t; + +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE +/*! @brief sai data pin state definition */ +typedef enum _sai_data_pin_state +{ + kSAI_DataPinStateTriState = + 0U, /*!< transmit data pins are tri-stated when slots are masked or channels are disabled */ + kSAI_DataPinStateOutputZero = 1U, /*!< transmit data pins are never tri-stated and will output zero when slots + are masked or channel disabled */ +} sai_data_pin_state_t; +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE +/*! @brief sai fifo combine mode definition */ +typedef enum _sai_fifo_combine +{ + kSAI_FifoCombineDisabled = 0U, /*!< sai fifo combine mode disabled */ + kSAI_FifoCombineModeEnabledOnRead, /*!< sai fifo combine mode enabled on FIFO reads */ + kSAI_FifoCombineModeEnabledOnWrite, /*!< sai fifo combine mode enabled on FIFO write */ + kSAI_FifoCombineModeEnabledOnReadWrite, /*!< sai fifo combined mode enabled on FIFO read/writes */ +} sai_fifo_combine_t; +#endif + +/*! @brief sai transceiver type */ +typedef enum _sai_transceiver_type +{ + kSAI_Transmitter = 0U, /*!< sai transmitter */ + kSAI_Receiver = 1U, /*!< sai receiver */ +} sai_transceiver_type_t; + +/*! @brief sai frame sync len */ +typedef enum _sai_frame_sync_len +{ + kSAI_FrameSyncLenOneBitClk = 0U, /*!< 1 bit clock frame sync len for DSP mode */ + kSAI_FrameSyncLenPerWordWidth = 1U, /*!< Frame sync length decided by word width */ +} sai_frame_sync_len_t; + +/*! @brief sai transfer format */ +typedef struct _sai_transfer_format +{ + uint32_t sampleRate_Hz; /*!< Sample rate of audio data */ + uint32_t bitWidth; /*!< Data length of audio data, usually 8/16/24/32 bits */ + sai_mono_stereo_t stereo; /*!< Mono or stereo */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + uint32_t masterClockHz; /*!< Master clock frequency in Hz */ +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t watermark; /*!< Watermark value */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle + * other parameter carefully, such as + * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask + * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. + * for the single channel usage, user can provide channel or channel mask only, such as, + * channel = 0 or channelMask = kSAI_Channel0Mask. + */ + uint8_t channel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + + sai_protocol_t protocol; /*!< Which audio protocol used */ + bool isFrameSyncCompact; /*!< True means Frame sync length is configurable according to bitWidth, false means frame + sync length is 64 times of bit clock. */ +} sai_transfer_format_t; + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) +/*! @brief master clock configurations */ +typedef struct _sai_master_clock +{ +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + bool mclkOutputEnable; /*!< master clock output enable */ +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + sai_mclk_source_t mclkSource; /*!< Master Clock source */ +#endif +#endif + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) + uint32_t mclkHz; /*!< target mclk frequency */ + uint32_t mclkSourceClkHz; /*!< mclk source frequency*/ +#endif +} sai_master_clock_t; +#endif + +/*! @brief sai fifo feature*/ +#if (defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) || \ + (defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) || \ + (defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING) || \ + (defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)) +#define FSL_SAI_HAS_FIFO_EXTEND_FEATURE 1 +#else +#define FSL_SAI_HAS_FIFO_EXTEND_FEATURE 0 +#endif + +#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE +/*! @brief sai fifo configurations */ +typedef struct _sai_fifo +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + bool fifoContinueOneError; /*!< fifo continues when error occur */ +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE + sai_fifo_combine_t fifoCombine; /*!< fifo combine mode */ +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING + sai_fifo_packing_t fifoPacking; /*!< fifo packing mode */ +#endif +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t fifoWatermark; /*!< fifo watermark */ +#endif +} sai_fifo_t; +#endif + +/*! @brief sai bit clock configurations */ +typedef struct _sai_bit_clock +{ + bool bclkSrcSwap; /*!< bit clock source swap */ + bool bclkInputDelay; /*!< bit clock actually used by the transmitter is delayed by the pad output delay, + this has effect of decreasing the data input setup time, but increasing the data output valid + time .*/ + sai_clock_polarity_t bclkPolarity; /*!< bit clock polarity */ + sai_bclk_source_t bclkSource; /*!< bit Clock source */ +} sai_bit_clock_t; + +/*! @brief sai frame sync configurations */ +typedef struct _sai_frame_sync +{ + uint8_t frameSyncWidth; /*!< frame sync width in number of bit clocks */ + bool frameSyncEarly; /*!< TRUE is frame sync assert one bit before the first bit of frame + FALSE is frame sync assert with the first bit of the frame */ + +#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND + bool frameSyncGenerateOnDemand; /*!< internal frame sync is generated when FIFO waring flag is clear */ +#endif + + sai_clock_polarity_t frameSyncPolarity; /*!< frame sync polarity */ + +} sai_frame_sync_t; + +/*! @brief sai serial data configurations */ +typedef struct _sai_serial_data +{ +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE + sai_data_pin_state_t dataMode; /*!< sai data pin state when slots masked or channel disabled */ +#endif + + sai_data_order_t dataOrder; /*!< configure whether the LSB or MSB is transmitted first */ + uint8_t dataWord0Length; /*!< configure the number of bits in the first word in each frame */ + uint8_t dataWordNLength; /*!< configure the number of bits in the each word in each frame, except the first word */ + uint8_t dataWordLength; /*!< used to record the data length for dma transfer */ + uint8_t + dataFirstBitShifted; /*!< Configure the bit index for the first bit transmitted for each word in the frame */ + uint8_t dataWordNum; /*!< configure the number of words in each frame */ + uint32_t dataMaskedWord; /*!< configure whether the transmit word is masked */ +} sai_serial_data_t; + +/*! @brief sai transceiver configurations */ +typedef struct _sai_transceiver +{ + sai_serial_data_t serialData; /*!< serial data configurations */ + sai_frame_sync_t frameSync; /*!< ws configurations */ + sai_bit_clock_t bitClock; /*!< bit clock configurations */ +#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE + sai_fifo_t fifo; /*!< fifo configurations */ +#endif + sai_master_slave_t masterSlave; /*!< transceiver is master or slave */ + + sai_sync_mode_t syncMode; /*!< transceiver sync mode */ + + uint8_t startChannel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + +} sai_transceiver_t; + +/*! @brief SAI transfer structure */ +typedef struct _sai_transfer +{ + uint8_t *data; /*!< Data start address to transfer. */ + size_t dataSize; /*!< Transfer size. */ +} sai_transfer_t; + +typedef struct _sai_handle sai_handle_t; + +/*! @brief SAI transfer callback prototype */ +typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData); + +/*! @brief SAI handle structure */ +struct _sai_handle +{ + I2S_Type *base; /*!< base address */ + + uint32_t state; /*!< Transfer status */ + sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32 bits */ + + /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle + * other parameter carefully, such as + * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask + * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. + * for the single channel usage, user can provide channel or channel mask only, such as, + * channel = 0 or channelMask = kSAI_Channel0Mask. + */ + uint8_t channel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, refernece _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t watermark; /*!< Watermark value */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the SAI Tx peripheral. + * @deprecated Do not use this function. It has been superceded by @ref SAI_Init + * + * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_TxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault + * because the clock is not enabled. + * + * @param base SAI base pointer + * @param config SAI configuration structure. + */ +void SAI_TxInit(I2S_Type *base, const sai_config_t *config); + +/*! + * @brief Initializes the SAI Rx peripheral. + * @deprecated Do not use this function. It has been superceded by @ref SAI_Init + * + * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_RxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault + * because the clock is not enabled. + * + * @param base SAI base pointer + * @param config SAI configuration structure. + */ +void SAI_RxInit(I2S_Type *base, const sai_config_t *config); + +/*! + * @brief Sets the SAI Tx configuration structure to default values. + * @deprecated Do not use this function. It has been superceded by + * @ref SAI_GetClassicI2SConfig, @ref SAI_GetLeftJustifiedConfig , @ref SAI_GetRightJustifiedConfig, @ref + SAI_GetDSPConfig, @ref SAI_GetTDMConfig + * + * This API initializes the configuration structure for use in SAI_TxConfig(). + * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified + * before calling SAI_TxConfig(). + * This is an example. + @code + sai_config_t config; + SAI_TxGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SAI_TxGetDefaultConfig(sai_config_t *config); + +/*! + * @brief Sets the SAI Rx configuration structure to default values. + * @deprecated Do not use this function. It has been superceded by + * @ref SAI_GetClassicI2SConfig, @ref SAI_GetLeftJustifiedConfig , @ref SAI_GetRightJustifiedConfig, @ref + SAI_GetDSPConfig, @ref SAI_GetTDMConfig + * + * This API initializes the configuration structure for use in SAI_RxConfig(). + * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified + * before calling SAI_RxConfig(). + * This is an example. + @code + sai_config_t config; + SAI_RxGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SAI_RxGetDefaultConfig(sai_config_t *config); + +/*! + * @brief Initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock. + * + * @param base SAI base pointer. + */ +void SAI_Init(I2S_Type *base); + +/*! + * @brief De-initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit + * or SAI_RxInit is called to enable the clock. + * + * @param base SAI base pointer. + */ +void SAI_Deinit(I2S_Type *base); + +/*! + * @brief Resets the SAI Tx. + * + * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_TxReset(I2S_Type *base); + +/*! + * @brief Resets the SAI Rx. + * + * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_RxReset(I2S_Type *base); + +/*! + * @brief Enables/disables the SAI Tx. + * + * @param base SAI base pointer. + * @param enable True means enable SAI Tx, false means disable. + */ +void SAI_TxEnable(I2S_Type *base, bool enable); + +/*! + * @brief Enables/disables the SAI Rx. + * + * @param base SAI base pointer. + * @param enable True means enable SAI Rx, false means disable. + */ +void SAI_RxEnable(I2S_Type *base, bool enable); + +/*! + * @brief Set Rx bit clock direction. + * + * Select bit clock direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_TxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->TCR2 |= I2S_TCR2_BCD_MASK; + } + else + { + base->TCR2 &= ~I2S_TCR2_BCD_MASK; + } +} + +/*! + * @brief Set Rx bit clock direction. + * + * Select bit clock direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_RxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->RCR2 |= I2S_RCR2_BCD_MASK; + } + else + { + base->RCR2 &= ~I2S_RCR2_BCD_MASK; + } +} + +/*! + * @brief Set Rx frame sync direction. + * + * Select frame sync direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_RxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->RCR4 |= I2S_RCR4_FSD_MASK; + } + else + { + base->RCR4 &= ~I2S_RCR4_FSD_MASK; + } +} + +/*! + * @brief Set Tx frame sync direction. + * + * Select frame sync direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_TxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->TCR4 |= I2S_TCR4_FSD_MASK; + } + else + { + base->TCR4 &= ~I2S_TCR4_FSD_MASK; + } +} + +/*! + * @brief Transmitter bit clock rate configurations. + * + * @param base SAI base pointer. + * @param sourceClockHz Bit clock source frequency. + * @param sampleRate Audio data sample rate. + * @param bitWidth Audio data bitWidth. + * @param channelNumbers Audio channel numbers. + */ +void SAI_TxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); + +/*! + * @brief Receiver bit clock rate configurations. + * + * @param base SAI base pointer. + * @param sourceClockHz Bit clock source frequency. + * @param sampleRate Audio data sample rate. + * @param bitWidth Audio data bitWidth. + * @param channelNumbers Audio channel numbers. + */ +void SAI_RxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); + +/*! + * @brief Transmitter Bit clock configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config); + +/*! + * @brief Receiver Bit clock configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config); + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) +/*! + * @brief Master clock configurations. + * + * @param base SAI base pointer. + * @param config master clock configurations. + */ +void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config); +#endif + +#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE +/*! + * @brief SAI transmitter fifo configurations. + * + * @param base SAI base pointer. + * @param config fifo configurations. + */ +void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config); + +/*! + * @brief SAI receiver fifo configurations. + * + * @param base SAI base pointer. + * @param config fifo configurations. + */ +void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config); +#endif + +/*! + * @brief SAI transmitter Frame sync configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config); + +/*! + * @brief SAI receiver Frame sync configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config); + +/*! + * @brief SAI transmitter Serial data configurations. + * + * @param base SAI base pointer. + * @param config serial data configurations. + */ +void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config); + +/*! + * @brief SAI receiver Serial data configurations. + * + * @param base SAI base pointer. + * @param config serial data configurations. + */ +void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config); + +/*! + * @brief SAI transmitter configurations. + * + * @param base SAI base pointer. + * @param config transmitter configurations. + */ +void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config); + +/*! + * @brief SAI receiver configurations. + * + * @param base SAI base pointer. + * @param config receiver configurations. + */ +void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config); + +/*! + * @brief Get classic I2S mode configurations. + * + * @param config transceiver configurations. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetClassicI2SConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); + +/*! + * @brief Get left justified mode configurations. + * + * @param config transceiver configurations. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); + +/*! + * @brief Get right justified mode configurations. + * + * @param config transceiver configurations. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetRightJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); + +/*! + * @brief Get TDM mode configurations. + * + * @param config transceiver configurations. + * @param frameSyncWidth length of frame sync. + * @param bitWidth audio data word width. + * @param dataWordNum word number in one frame. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetTDMConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + uint32_t dataWordNum, + uint32_t saiChannelMask); + +/*! + * @brief Get DSP mode configurations. + * + * @note DSP mode is also called PCM mode which support MODE A and MODE B, + * DSP/PCM MODE A configuration flow. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig: + * @code + * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask) + * config->frameSync.frameSyncEarly = true; + * SAI_TxSetConfig(base, config) + * @endcode + * + * DSP/PCM MODE B configuration flow for TX. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig: + * @code + * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask) + * SAI_TxSetConfig(base, config) + * @endcode + * + * @param config transceiver configurations. + * @param frameSyncWidth length of frame sync. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to enable. + */ +void SAI_GetDSPConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Tx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base) +{ + return base->TCSR; +} + +/*! + * @brief Clears the SAI Tx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following source if defined: + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Rx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base) +{ + return base->RCSR; +} + +/*! + * @brief Clears the SAI Rx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following sources if defined. + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like TCR1~TCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * @param base SAI base pointer + * @param type Reset type, FIFO reset or software reset + */ +void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type); + +/*! + * @brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like RCR1~RCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * @param base SAI base pointer + * @param type Reset type, FIFO reset or software reset + */ +void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type); + +/*! + * @brief Set the Tx channel FIFO enable mask. + * + * @param base SAI base pointer + * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); + +/*! + * @brief Set the Rx channel FIFO enable mask. + * + * @param base SAI base pointer + * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param polarity + */ +void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param polarity + */ +void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param polarity + */ +void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param polarity + */ +void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief Set Tx FIFO packing feature. + * + * @param base SAI base pointer. + * @param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); + +/*! + * @brief Set Rx FIFO packing feature. + * + * @param base SAI base pointer. + * @param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR +/*! + * @brief Set Tx FIFO error continue. + * + * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature + * not enabled, SAI will hang and users need to clear FEF flag in TCSR register. + * + * @param base SAI base pointer. + * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. + */ +static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) +{ + if (isEnabled) + { + base->TCR4 |= I2S_TCR4_FCONT_MASK; + } + else + { + base->TCR4 &= ~I2S_TCR4_FCONT_MASK; + } +} + +/*! + * @brief Set Rx FIFO error continue. + * + * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature + * not enabled, SAI will hang and users need to clear FEF flag in RCSR register. + * + * @param base SAI base pointer. + * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. + */ +static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) +{ + if (isEnabled) + { + base->RCR4 |= I2S_RCR4_FCONT_MASK; + } + else + { + base->RCR4 &= ~I2S_RCR4_FCONT_MASK; + } +} +#endif + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Enables the SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Disables the SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! + * @brief Disables the SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the SAI Tx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be combination of the following sources if defined. + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Enables/disables the SAI Rx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Gets the SAI Tx data register address. + * + * This API is used to provide a transfer address for the SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->TDR)[channel]); +} + +/*! + * @brief Gets the SAI Rx data register address. + * + * This API is used to provide a transfer address for the SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->RDR)[channel]); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the SAI Tx audio format. + * @deprecated Do not use this function. It has been superceded by @ref SAI_TxSetConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. + */ +void SAI_TxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * @deprecated Do not use this function. It has been superceded by @ref SAI_RxSetConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. + */ +void SAI_RxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Sends data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Sends data to multi channel using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param channelMask channel mask. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SAI_WriteMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Writes data into SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param data Data needs to be written. + */ +static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data) +{ + base->TDR[channel] = data; +} + +/*! + * @brief Receives data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Receives multi channel data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param channelMask channel mask. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SAI_ReadMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Reads data from the SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @return Data in SAI FIFO. + */ +static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel) +{ + return base->RDR[channel]; +} + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SAI Tx handle. + * + * This function initializes the Tx handle for the SAI Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SAI base pointer + * @param handle SAI handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function + */ +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief Initializes the SAI Rx handle. + * + * This function initializes the Rx handle for the SAI Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function. + */ +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief SAI transmitter transfer configurations. + * + * This function initializes the Tx, include bit clock, frame sync, master clock, serial data and fifo + * configurations. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param config tranmitter configurations. + */ +void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config); + +/*! + * @brief SAI receiver transfer configurations. + * + * This function initializes the Rx, include bit clock, frame sync, master clock, serial data and fifo + * configurations. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param config receiver configurations. + */ +void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config); + +/*! + * @brief Configures the SAI Tx audio format. + * @deprecated Do not use this function. It has been superceded by @ref SAI_TransferTxSetConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * @return Status of this function. Return value is the status_t. + */ +status_t SAI_TransferTxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * @deprecated Do not use this function. It has been superceded by @ref SAI_TransferRxSetConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * @return Status of this function. Return value is one of status_t. + */ +status_t SAI_TransferRxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Performs an interrupt non-blocking send transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param xfer Pointer to the sai_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_TxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs an interrupt non-blocking receive transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param xfer Pointer to the sai_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_RxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Gets a set byte count. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param count Bytes count sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Gets a received byte count. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param count Bytes count received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the current send. + * + * @note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Aborts the current IRQ receive. + * + * @note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSend. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceive. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* _FSL_SAI_H_ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_sema4.c b/devices/MIMX8MQ6/drivers/fsl_sema4.c new file mode 100644 index 000000000..9c48c0bdf --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_sema4.c @@ -0,0 +1,263 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sema4.h" + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sema4" +#endif + +/* The first number write to RSTGDP when reset SEMA4 gate. */ +#define SEMA4_GATE_RESET_PATTERN_1 (0xE2U) +/* The second number write to RSTGDP when reset SEMA4 gate. */ +#define SEMA4_GATE_RESET_PATTERN_2 (0x1DU) + +/* The first number write to RSTGDP when reset SEMA4 gate IRQ notification. */ +#define SEMA4_GATE_IRQ_RESET_PATTERN_1 (0x47U) +/* The second number write to RSTGDP when reset SEMA4 gate IRQ notification. */ +#define SEMA4_GATE_IRQ_RESET_PATTERN_2 (0xB8U) + +#define SEMA4_RSTGT_RSTNSM_MASK (0x30U) + +#define SEMA4_RSTNTF_RSTNSM_MASK (0x30U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if defined(SEMA4_CLOCKS) +/*! + * @brief Get instance number for SEMA4 module. + * + * @param base SEMA4 peripheral base address. + */ +uint32_t SEMA4_GetInstance(SEMA4_Type *base); +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if defined(SEMA4_CLOCKS) +/*! @brief Pointers to sema4 bases for each instance. */ +static SEMA4_Type *const s_sema4Bases[] = SEMA4_BASE_PTRS; +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(SEMA4_CLOCKS) +/*! @brief Pointers to sema4 clocks for each instance. */ +static const clock_ip_name_t s_sema4Clocks[] = SEMA4_CLOCKS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/****************************************************************************** + * CODE + *****************************************************************************/ + +#if defined(SEMA4_CLOCKS) +uint32_t SEMA4_GetInstance(SEMA4_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_sema4Bases); instance++) + { + if (s_sema4Bases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_sema4Bases)); + + return instance; +} +#endif + +/*! + * brief Initializes the SEMA4 module. + * + * This function initializes the SEMA4 module. It only enables the clock but does + * not reset the gates because the module might be used by other processors + * at the same time. To reset the gates, call either SEMA4_ResetGate or + * SEMA4_ResetAllGates function. + * + * param base SEMA4 peripheral base address. + */ +void SEMA4_Init(SEMA4_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(SEMA4_CLOCKS) + CLOCK_EnableClock(s_sema4Clocks[SEMA4_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief De-initializes the SEMA4 module. + * + * This function de-initializes the SEMA4 module. It only disables the clock. + * + * param base SEMA4 peripheral base address. + */ +void SEMA4_Deinit(SEMA4_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(SEMA4_CLOCKS) + CLOCK_DisableClock(s_sema4Clocks[SEMA4_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Tries to lock the SEMA4 gate. + * + * This function tries to lock the specific SEMA4 gate. If the gate has been + * locked by another processor, this function returns an error code. + * + * param base SEMA4 peripheral base address. + * param gateNum Gate number to lock. + * param procNum Current processor number. + * + * retval kStatus_Success Lock the sema4 gate successfully. + * retval kStatus_Fail Sema4 gate has been locked by another processor. + */ +status_t SEMA4_TryLock(SEMA4_Type *base, uint8_t gateNum, uint8_t procNum) +{ + status_t status; + + assert(gateNum < (uint8_t)FSL_FEATURE_SEMA4_GATE_COUNT); + + ++procNum; + + /* Try to lock. */ + SEMA4_GATEn(base, gateNum) = procNum; + + /* Check locked or not. */ + if (procNum != SEMA4_GATEn(base, gateNum)) + { + status = kStatus_Fail; + } + else + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Locks the SEMA4 gate. + * + * This function locks the specific SEMA4 gate. If the gate has been + * locked by other processors, this function waits until it is unlocked and then + * lock it. + * + * param base SEMA4 peripheral base address. + * param gateNum Gate number to lock. + * param procNum Current processor number. + */ +void SEMA4_Lock(SEMA4_Type *base, uint8_t gateNum, uint8_t procNum) +{ + assert(gateNum < (uint8_t)FSL_FEATURE_SEMA4_GATE_COUNT); + + ++procNum; + + while (procNum != SEMA4_GATEn(base, gateNum)) + { + /* Wait for unlocked status. */ + while (0U != SEMA4_GATEn(base, gateNum)) + { + } + + /* Lock the gate. */ + SEMA4_GATEn(base, gateNum) = procNum; + } +} + +/*! + * brief Resets the SEMA4 gate to an unlocked status. + * + * This function resets a SEMA4 gate to an unlocked status. + * + * param base SEMA4 peripheral base address. + * param gateNum Gate number. + * + * retval kStatus_Success SEMA4 gate is reset successfully. + * retval kStatus_Fail Some other reset process is ongoing. + */ +status_t SEMA4_ResetGate(SEMA4_Type *base, uint8_t gateNum) +{ + status_t status; + + /* + * Reset all gates if gateNum >= SEMA4_GATE_NUM_RESET_ALL + * Reset specific gate if gateNum < FSL_FEATURE_SEMA4_GATE_COUNT + */ + assert(!((gateNum < SEMA4_GATE_NUM_RESET_ALL) && (gateNum >= (uint8_t)FSL_FEATURE_SEMA4_GATE_COUNT))); + + /* Check whether some reset is ongoing. */ + if (0U != (base->RSTGT & SEMA4_RSTGT_RSTNSM_MASK)) + { + status = kStatus_Fail; + } + else + { + /* First step. */ + base->RSTGT = SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(SEMA4_GATE_RESET_PATTERN_1); + /* Second step. */ + base->RSTGT = SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(SEMA4_GATE_RESET_PATTERN_2) | SEMA4_RSTGT_RSTGTN(gateNum); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Resets the SEMA4 gate IRQ notification. + * + * This function resets a SEMA4 gate IRQ notification. + * + * param base SEMA4 peripheral base address. + * param gateNum Gate number. + * + * retval kStatus_Success Reset successfully. + * retval kStatus_Fail Some other reset process is ongoing. + */ +status_t SEMA4_ResetGateNotify(SEMA4_Type *base, uint8_t gateNum) +{ + status_t status; + + /* + * Reset all gates if gateNum >= SEMA4_GATE_NUM_RESET_ALL + * Reset specific gate if gateNum < FSL_FEATURE_SEMA4_GATE_COUNT + */ + assert(!((gateNum < (uint8_t)SEMA4_GATE_NUM_RESET_ALL) && (gateNum >= (uint8_t)FSL_FEATURE_SEMA4_GATE_COUNT))); + + /* Check whether some reset is ongoing. */ + if (0U != (base->RSTNTF & SEMA4_RSTNTF_RSTNSM_MASK)) + { + status = kStatus_Fail; + } + else + { + /* First step. */ + base->RSTNTF = SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(SEMA4_GATE_IRQ_RESET_PATTERN_1); + /* Second step. */ + base->RSTNTF = SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(SEMA4_GATE_IRQ_RESET_PATTERN_2) | SEMA4_RSTNTF_RSTNTN(gateNum); + + status = kStatus_Success; + } + + return status; +} diff --git a/devices/MIMX8MQ6/drivers/fsl_sema4.h b/devices/MIMX8MQ6/drivers/fsl_sema4.h new file mode 100644 index 000000000..a9dcb913a --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_sema4.h @@ -0,0 +1,260 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SEMA4_H_ +#define _FSL_SEMA4_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sema4 + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SEMA4 driver version */ +#define FSL_SEMA4_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief The number to reset all SEMA4 gates. */ +#define SEMA4_GATE_NUM_RESET_ALL (64U) + +#if defined(SEMA4_GATE_COUNT) + +/*! + * @brief SEMA4 gate n register address. + */ +#define SEMA4_GATEn(base, n) ((base)->GATE[(n)]) + +#ifndef FSL_FEATURE_SEMA4_GATE_COUNT +#define FSL_FEATURE_SEMA4_GATE_COUNT SEMA4_GATE_COUNT +#endif + +#else + +/*! + * @brief SEMA4 gate n register address. + */ +#define SEMA4_GATEn(base, n) (((volatile uint8_t *)(&((base)->Gate00)))[(n)]) + +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the SEMA4 module. + * + * This function initializes the SEMA4 module. It only enables the clock but does + * not reset the gates because the module might be used by other processors + * at the same time. To reset the gates, call either SEMA4_ResetGate or + * SEMA4_ResetAllGates function. + * + * @param base SEMA4 peripheral base address. + */ +void SEMA4_Init(SEMA4_Type *base); + +/*! + * @brief De-initializes the SEMA4 module. + * + * This function de-initializes the SEMA4 module. It only disables the clock. + * + * @param base SEMA4 peripheral base address. + */ +void SEMA4_Deinit(SEMA4_Type *base); + +/*! + * @brief Tries to lock the SEMA4 gate. + * + * This function tries to lock the specific SEMA4 gate. If the gate has been + * locked by another processor, this function returns an error code. + * + * @param base SEMA4 peripheral base address. + * @param gateNum Gate number to lock. + * @param procNum Current processor number. + * + * @retval kStatus_Success Lock the sema4 gate successfully. + * @retval kStatus_Fail Sema4 gate has been locked by another processor. + */ +status_t SEMA4_TryLock(SEMA4_Type *base, uint8_t gateNum, uint8_t procNum); + +/*! + * @brief Locks the SEMA4 gate. + * + * This function locks the specific SEMA4 gate. If the gate has been + * locked by other processors, this function waits until it is unlocked and then + * lock it. + * + * @param base SEMA4 peripheral base address. + * @param gateNum Gate number to lock. + * @param procNum Current processor number. + */ +void SEMA4_Lock(SEMA4_Type *base, uint8_t gateNum, uint8_t procNum); + +/*! + * @brief Unlocks the SEMA4 gate. + * + * This function unlocks the specific SEMA4 gate. It only writes unlock value + * to the SEMA4 gate register. However, it does not check whether the SEMA4 gate is locked + * by the current processor or not. As a result, if the SEMA4 gate is not locked by the current + * processor, this function has no effect. + * + * @param base SEMA4 peripheral base address. + * @param gateNum Gate number to unlock. + */ +static inline void SEMA4_Unlock(SEMA4_Type *base, uint8_t gateNum) +{ + assert(gateNum < (uint8_t)FSL_FEATURE_SEMA4_GATE_COUNT); + + SEMA4_GATEn(base, gateNum) = 0U; +} + +/*! + * @brief Gets the status of the SEMA4 gate. + * + * This function checks the lock status of a specific SEMA4 gate. + * + * @param base SEMA4 peripheral base address. + * @param gateNum Gate number. + * + * @return Return -1 if the gate is unlocked, otherwise return the + * processor number which has locked the gate. + */ +static inline int32_t SEMA4_GetLockProc(SEMA4_Type *base, uint8_t gateNum) +{ + assert(gateNum < (uint8_t)FSL_FEATURE_SEMA4_GATE_COUNT); + + return (int32_t)(SEMA4_GATEn(base, gateNum)) - 1; +} + +/*! + * @brief Resets the SEMA4 gate to an unlocked status. + * + * This function resets a SEMA4 gate to an unlocked status. + * + * @param base SEMA4 peripheral base address. + * @param gateNum Gate number. + * + * @retval kStatus_Success SEMA4 gate is reset successfully. + * @retval kStatus_Fail Some other reset process is ongoing. + */ +status_t SEMA4_ResetGate(SEMA4_Type *base, uint8_t gateNum); + +/*! + * @brief Resets all SEMA4 gates to an unlocked status. + * + * This function resets all SEMA4 gate to an unlocked status. + * + * @param base SEMA4 peripheral base address. + * + * @retval kStatus_Success SEMA4 is reset successfully. + * @retval kStatus_Fail Some other reset process is ongoing. + */ +static inline status_t SEMA4_ResetAllGates(SEMA4_Type *base) +{ + return SEMA4_ResetGate(base, SEMA4_GATE_NUM_RESET_ALL); +} + +/*! + * @brief Enable the gate notification interrupt. + * + * Gate notification provides such feature, when core tried to lock the gate + * and failed, it could get notification when the gate is idle. + * + * @param base SEMA4 peripheral base address. + * @param procNum Current processor number. + * @param mask OR'ed value of the gate index, for example: (1<<0) | (1<<1) means + * gate 0 and gate 1. + */ +static inline void SEMA4_EnableGateNotifyInterrupt(SEMA4_Type *base, uint8_t procNum, uint32_t mask) +{ + mask = __REV(__RBIT(mask)); + base->CPINE[procNum].CPINE |= (uint16_t)mask; +} + +/*! + * @brief Disable the gate notification interrupt. + * + * Gate notification provides such feature, when core tried to lock the gate + * and failed, it could get notification when the gate is idle. + * + * @param base SEMA4 peripheral base address. + * @param procNum Current processor number. + * @param mask OR'ed value of the gate index, for example: (1<<0) | (1<<1) means + * gate 0 and gate 1. + */ +static inline void SEMA4_DisableGateNotifyInterrupt(SEMA4_Type *base, uint8_t procNum, uint32_t mask) +{ + mask = __REV(__RBIT(mask)); + base->CPINE[procNum].CPINE &= (uint16_t)(~mask); +} + +/*! + * @brief Get the gate notification flags. + * + * Gate notification provides such feature, when core tried to lock the gate + * and failed, it could get notification when the gate is idle. The status flags + * are cleared automatically when the gate is locked by current core or locked + * again before the other core. + * + * @param base SEMA4 peripheral base address. + * @param procNum Current processor number. + * @return OR'ed value of the gate index, for example: (1<<0) | (1<<1) means + * gate 0 and gate 1 flags are pending. + */ +static inline uint32_t SEMA4_GetGateNotifyStatus(SEMA4_Type *base, uint8_t procNum) +{ + return __REV(__RBIT(base->CPNTF[procNum].CPNTF)); +} + +/*! + * @brief Resets the SEMA4 gate IRQ notification. + * + * This function resets a SEMA4 gate IRQ notification. + * + * @param base SEMA4 peripheral base address. + * @param gateNum Gate number. + * + * @retval kStatus_Success Reset successfully. + * @retval kStatus_Fail Some other reset process is ongoing. + */ +status_t SEMA4_ResetGateNotify(SEMA4_Type *base, uint8_t gateNum); + +/*! + * @brief Resets all SEMA4 gates IRQ notification. + * + * This function resets all SEMA4 gate IRQ notifications. + * + * @param base SEMA4 peripheral base address. + * + * @retval kStatus_Success Reset successfully. + * @retval kStatus_Fail Some other reset process is ongoing. + */ +static inline status_t SEMA4_ResetAllGateNotify(SEMA4_Type *base) +{ + return SEMA4_ResetGateNotify(base, SEMA4_GATE_NUM_RESET_ALL); +} + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_SEMA4_H_ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_tmu.c b/devices/MIMX8MQ6/drivers/fsl_tmu.c new file mode 100644 index 000000000..c31ccc020 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_tmu.c @@ -0,0 +1,423 @@ +/* + * Copyright 2017-2019, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_tmu.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.tmu" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for TMU module. + * + * @param base TMU peripheral base address + */ +static uint32_t TMU_GetInstance(TMU_Type *base); + +/*! + * @brief Programming the sensor translation table. + * + * @param base TMU peripheral base address. + */ +static void TMU_SetTranslationTable(TMU_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to TMU bases for each instance. */ +static TMU_Type *const s_tmuBases[] = TMU_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to TMU clocks for each instance. */ +static const clock_ip_name_t s_tmuClocks[] = TMU_CLOCKS; +#endif +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t TMU_GetInstance(TMU_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_tmuBases); instance++) + { + if (s_tmuBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_tmuBases)); + + return instance; +} + +static void TMU_SetTranslationTable(TMU_Type *base) +{ + /* programming the sensor translation table. */ + base->TTRCR[0] = TMU_TTRCR_TEMP(0U) | TMU_TTRCR_CAL_PTS(11U); /* Range0. */ + base->TTRCR[1] = TMU_TTRCR_TEMP(44U) | TMU_TTRCR_CAL_PTS(9U); /* Range1. */ + base->TTRCR[2] = TMU_TTRCR_TEMP(78U) | TMU_TTRCR_CAL_PTS(6U); /* Range2. */ + base->TTRCR[3] = TMU_TTRCR_TEMP(102U) | TMU_TTRCR_CAL_PTS(3U); /* Range3. */ + /* For range0. */ + base->TTCFGR = 0x00000000U; + base->TSCFGR = 0x00000020U; + base->TTCFGR = 0x00000001U; + base->TSCFGR = 0x00000024U; + base->TTCFGR = 0x00000002U; + base->TSCFGR = 0x0000002AU; + base->TTCFGR = 0x00000003U; + base->TSCFGR = 0x00000032U; + base->TTCFGR = 0x00000004U; + base->TSCFGR = 0x00000038U; + base->TTCFGR = 0x00000005U; + base->TSCFGR = 0x0000003EU; + base->TTCFGR = 0x00000006U; + base->TSCFGR = 0x00000043U; + base->TTCFGR = 0x00000007U; + base->TSCFGR = 0x0000004AU; + base->TTCFGR = 0x00000008U; + base->TSCFGR = 0x00000050U; + base->TTCFGR = 0x00000009U; + base->TSCFGR = 0x00000059U; + base->TTCFGR = 0x0000000AU; + base->TSCFGR = 0x0000005FU; + base->TTCFGR = 0x0000000BU; + base->TSCFGR = 0x00000066U; + /* For range1. */ + base->TTCFGR = 0x00010000U; + base->TSCFGR = 0x00000023U; + base->TTCFGR = 0x00010001U; + base->TSCFGR = 0x0000002BU; + base->TTCFGR = 0x00010002U; + base->TSCFGR = 0x00000033U; + base->TTCFGR = 0x00010003U; + base->TSCFGR = 0x0000003AU; + base->TTCFGR = 0x00010004U; + base->TSCFGR = 0x00000042U; + base->TTCFGR = 0x00010005U; + base->TSCFGR = 0x0000004AU; + base->TTCFGR = 0x00010006U; + base->TSCFGR = 0x00000054U; + base->TTCFGR = 0x00010007U; + base->TSCFGR = 0x0000005CU; + base->TTCFGR = 0x00010008U; + base->TSCFGR = 0x00000065U; + base->TTCFGR = 0x00010009U; + base->TSCFGR = 0x0000006FU; + /* For range2. */ + base->TTCFGR = 0x00020000U; + base->TSCFGR = 0x00000029U; + base->TTCFGR = 0x00020001U; + base->TSCFGR = 0x00000033U; + base->TTCFGR = 0x00020002U; + base->TSCFGR = 0x0000003DU; + base->TTCFGR = 0x00020003U; + base->TSCFGR = 0x00000048U; + base->TTCFGR = 0x00020004U; + base->TSCFGR = 0x00000054U; + base->TTCFGR = 0x00020005U; + base->TSCFGR = 0x00000060U; + base->TTCFGR = 0x00020006U; + base->TSCFGR = 0x0000006CU; + /* For range3. */ + base->TTCFGR = 0x00030000U; + base->TSCFGR = 0x00000025U; + base->TTCFGR = 0x00030001U; + base->TSCFGR = 0x00000033U; + base->TTCFGR = 0x00030002U; + base->TSCFGR = 0x00000043U; + base->TTCFGR = 0x00030003U; + base->TSCFGR = 0x00000055U; +} +/*! + * brief Enable the access to TMU registers and Initialize TMU module. + * + * param base TMU peripheral base address. + * param config Pointer to configuration structure. Refer to "tmu_config_t" structure. + */ +void TMU_Init(TMU_Type *base, const tmu_config_t *config) +{ + assert(NULL != base); + assert(NULL != config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable TMU clock. */ + CLOCK_EnableClock(s_tmuClocks[TMU_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL. */ + + /* Disable TMU monitor mode. */ + TMU_Enable(base, false); + + /* Set the sensor translation table. */ + TMU_SetTranslationTable(base); + + /* Clear interrupt relevant register. */ + TMU_ClearInterruptStatusFlags(base, (uint32_t)kTMU_ImmediateTemperatureStatusFlags | + (uint32_t)kTMU_AverageTemperatureStatusFlags | + (uint32_t)kTMU_AverageTemperatureCriticalStatusFlags); + + /* Configure TMR register. */ + base->TMR = TMU_TMR_ALPF(config->averageLPF) | TMU_TMR_MSITE(config->monitorSiteSelection); + + /* Configure the time interval. */ + base->TMTMIR = TMU_TMTMIR_TMI(config->monitorInterval); +} + +/*! + * brief De-initialize TMU module and Disable the access to DCDC registers. + * + * param base TMU peripheral base address. + */ +void TMU_Deinit(TMU_Type *base) +{ + /* Disable TMU monitor mode.. */ + TMU_Enable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable TMU clock. */ + CLOCK_DisableClock(s_tmuClocks[TMU_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL. */ +} + +/*! + * brief Gets the default configuration for TMU. + * + * This function initializes the user configuration structure to default value. The default value are: + * + * Example: + code + config->monitorInterval = 0U; + config->monitorSiteSelection = 0U; + config->averageLPF = kTMU_AverageLowPassFilter1_0; + endcode + * + * param config Pointer to TMU configuration structure. + */ +void TMU_GetDefaultConfig(tmu_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->monitorInterval = 0U; + config->monitorSiteSelection = 0U; /* If no site is selected, site 0 is monitored by default. */ + config->averageLPF = kTMU_AverageLowPassFilter1_0; +} + +/*! + * brief Get interrupt status flags. + * + * param base TMU peripheral base address. + * param status The pointer to interrupt status structure. Record the current interrupt status. + * Please refer to "tmu_interrupt_status_t" structure. + */ +void TMU_GetInterruptStatusFlags(TMU_Type *base, tmu_interrupt_status_t *status) +{ + assert(NULL != status); + + status->interruptDetectMask = base->TIDR; + status->immediateInterruptsSiteMask = (uint16_t)((TMU_TISCR_ISITE_MASK & base->TISCR) >> TMU_TISCR_ISITE_SHIFT); + status->AverageInterruptsSiteMask = (uint16_t)((TMU_TISCR_ASITE_MASK & base->TISCR) >> TMU_TISCR_ASITE_SHIFT); + status->AverageCriticalInterruptsSiteMask = + (uint16_t)((TMU_TICSCR_CASITE_MASK & base->TICSCR) >> TMU_TICSCR_CASITE_SHIFT); +} + +/*! + * brief Clear interrupt status flags and corresponding interrupt critical site capture register. + * + * param base TMU peripheral base address. + * param The mask of interrupt status flags. Refer to "_tmu_interrupt_status_flags" enumeration. + */ +void TMU_ClearInterruptStatusFlags(TMU_Type *base, uint32_t mask) +{ + /* For immediate temperature threshold interrupt. */ + if (0U != ((uint32_t)kTMU_ImmediateTemperatureStatusFlags & mask)) + { + base->TIDR = TMU_TIDR_ITTE_MASK; /* Clear interrupt detect register. */ + base->TISCR &= ~TMU_TISCR_ISITE_MASK; /* Clear interrupt site capture register. */ + } + /* For average temperature threshold interrupt. */ + if (0U != ((uint32_t)kTMU_AverageTemperatureStatusFlags & mask)) + { + base->TIDR = TMU_TIDR_ATTE_MASK; /* Clear interrupt detect register. */ + base->TISCR &= ~TMU_TISCR_ASITE_MASK; /* Clear interrupt site capture register. */ + } + /* For Average temperature critical threshold interrupt. */ + if (0U != ((uint32_t)kTMU_AverageTemperatureCriticalStatusFlags & mask)) + { + base->TIDR = TMU_TIDR_ATCTE_MASK; /* Clear interrupt detect register. */ + base->TICSCR &= ~TMU_TICSCR_CASITE_MASK; /* Clear interrupt critical site capture register. */ + } +} + +/*! + * brief Get the highest temperature reached for any enabled monitored site within the temperature + * sensor range. + * + * param base TMU peripheral base address. + * param temperature Highest temperature recorded in degrees Celsius by any enabled monitored site. + * + * return Execution status. + * retval kStatus_Success Temperature reading is valid. + * retval kStatus_Fail Temperature reading is not valid due to no measured temperature within the + * sensor range of 0-125 °C for an enabled monitored site. + */ +status_t TMU_GetHighestTemperature(TMU_Type *base, uint32_t *temperature) +{ + assert(NULL != temperature); + + status_t ret = kStatus_Success; + + if (0U == (TMU_TMHTCRH_V_MASK & base->TMHTCRH)) + { + ret = kStatus_Fail; + } + else + { + *temperature = (TMU_TMHTCRH_TEMP_MASK & base->TMHTCRH) >> TMU_TMHTCRH_TEMP_SHIFT; + } + + return ret; +} + +/*! + * brief Get the lowest temperature reached for any enabled monitored site within the temperature + * sensor range. + * + * param base TMU peripheral base address. + * param temperature Lowest temperature recorded in degrees Celsius by any enabled monitored site. + * + * return Execution status. + * retval kStatus_Success Temperature reading is valid. + * retval kStatus_Fail Temperature reading is not valid due to no measured temperature within the + * sensor range of 0-125 °C for an enabled monitored site. + */ +status_t TMU_GetLowestTemperature(TMU_Type *base, uint32_t *temperature) +{ + assert(NULL != temperature); + + status_t ret = kStatus_Success; + + if (0U == (TMU_TMHTCRL_V_MASK & base->TMHTCRL)) + { + ret = kStatus_Fail; + } + else + { + *temperature = (TMU_TMHTCRL_TEMP_MASK & base->TMHTCRL) >> TMU_TMHTCRL_TEMP_SHIFT; + } + + return ret; +} + +/*! + * brief Get the last immediate temperature at site n. The site must be part of the list of enabled + * monitored sites as defined by monitorSiteSelection in "tmu_config_t" structure. + * + * param base TMU peripheral base address. + * param siteIndex The index of the site user want to read. 0U: site0 ~ 15U: site15. + * param temperature Last immediate temperature reading at site n . + * + * return Execution status. + * retval kStatus_Success Temperature reading is valid. + * retval kStatus_Fail Temperature reading is not valid because temperature out of sensor range or + * first measurement still pending. + */ +status_t TMU_GetImmediateTemperature(TMU_Type *base, uint32_t siteIndex, uint32_t *temperature) +{ + assert(NULL != temperature); + assert(siteIndex < TMU_TRITSR_COUNT); + + status_t ret = kStatus_Success; + + if (0U == (TMU_TRITSR_V_MASK & base->TRTSR[siteIndex].TRITSR)) + { + ret = kStatus_Fail; + } + else + { + *temperature = (TMU_TRITSR_TEMP_MASK & base->TRTSR[siteIndex].TRITSR) >> TMU_TRITSR_TEMP_SHIFT; + } + + return ret; +} + +/*! + * brief Get the last average temperature at site n. The site must be part of the list of enabled + * monitored sites as defined by monitorSiteSelection in "tmu_config_t" structure. + * + * param base TMU peripheral base address. + * param siteIndex The index of the site user want to read. 0U: site0 ~ 15U: site15. + * param temperature Last average temperature reading at site n . + * + * return Execution status. + * retval kStatus_Success Temperature reading is valid. + * retval kStatus_Fail Temperature reading is not valid because temperature out of sensor range or + * first measurement still pending. + */ +status_t TMU_GetAverageTemperature(TMU_Type *base, uint32_t siteIndex, uint32_t *temperature) +{ + assert(NULL != temperature); + assert(siteIndex < TMU_TRATSR_COUNT); + + status_t ret = kStatus_Success; + + if (0U == (TMU_TRATSR_V_MASK & base->TRTSR[siteIndex].TRATSR)) + { + ret = kStatus_Fail; + } + else + { + *temperature = (TMU_TRATSR_TEMP_MASK & base->TRTSR[siteIndex].TRATSR) >> TMU_TRATSR_TEMP_SHIFT; + } + + return ret; +} + +/*! + * brief Configure the high temperature thresold value and enable/disable relevant thresold. + * + * param base TMU peripheral base address. + * param config Pointer to configuration structure. Refer to "tmu_thresold_config_t" structure. + */ +void TMU_SetHighTemperatureThresold(TMU_Type *base, const tmu_thresold_config_t *config) +{ + assert(NULL != config); + + /* Configure the high temperature immediate threshold. */ + if (config->immediateThresoldEnable) + { + base->TMHTITR = TMU_TMHTITR_EN_MASK | TMU_TMHTITR_TEMP(config->immediateThresoldValue); + } + else + { + base->TMHTITR = 0U; + } + /* Configure the high temperature average threshold. */ + if (config->AverageThresoldEnable) + { + base->TMHTATR = TMU_TMHTATR_EN_MASK | TMU_TMHTATR_TEMP(config->averageThresoldValue); + } + else + { + base->TMHTATR = 0U; + } + /* Configure the high temperature average critical thresold. */ + if (config->AverageCriticalThresoldEnable) + { + base->TMHTACTR = TMU_TMHTACTR_EN_MASK | TMU_TMHTACTR_TEMP(config->averageCriticalThresoldValue); + } + else + { + base->TMHTACTR = 0U; + } +} diff --git a/devices/MIMX8MQ6/drivers/fsl_tmu.h b/devices/MIMX8MQ6/drivers/fsl_tmu.h new file mode 100644 index 000000000..4e3aeebcc --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_tmu.h @@ -0,0 +1,329 @@ +/* + * Copyright 2017-2020, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_TMU_H__ +#define __FSL_TMU_H__ + +#include "fsl_common.h" + +/*! + * @addtogroup tmu + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief TMU driver version. */ +#define FSL_TMU_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */ + +enum _tmu_monitor_site +{ + kTMU_MonitorSite0 = 1U << 15U, /* TMU monitoring site 0. */ + kTMU_MonitorSite1 = 1U << 14U, /* TMU monitoring site 1. */ + kTMU_MonitorSite2 = 1U << 13U, /* TMU monitoring site 2. */ + kTMU_MonitorSite3 = 1U << 12U, /* TMU monitoring site 3. */ + kTMU_MonitorSite4 = 1U << 11U, /* TMU monitoring site 4. */ + kTMU_MonitorSite5 = 1U << 10U, /* TMU monitoring site 5. */ + kTMU_MonitorSite6 = 1U << 9U, /* TMU monitoring site 6. */ + kTMU_MonitorSite7 = 1U << 8U, /* TMU monitoring site 7. */ + kTMU_MonitorSite8 = 1U << 7U, /* TMU monitoring site 8. */ + kTMU_MonitorSite9 = 1U << 6U, /* TMU monitoring site 9. */ + kTMU_MonitorSite10 = 1U << 5U, /* TMU monitoring site 10. */ + kTMU_MonitorSite11 = 1U << 4U, /* TMU monitoring site 11. */ + kTMU_MonitorSite12 = 1U << 3U, /* TMU monitoring site 12. */ + kTMU_MonitorSite13 = 1U << 2U, /* TMU monitoring site 13. */ + kTMU_MonitorSite14 = 1U << 1U, /* TMU monitoring site 14. */ + kTMU_MonitorSite15 = 1U << 0U, /* TMU monitoring site 15. */ +}; + +/*! + * @brief TMU interrupt enable. + */ +enum _tmu_interrupt_enable +{ + kTMU_ImmediateTemperatureInterruptEnable = + TMU_TIER_ITTEIE_MASK, /*!< Immediate temperature threshold exceeded interrupt enable. */ + kTMU_AverageTemperatureInterruptEnable = + TMU_TIER_ATTEIE_MASK, /*!< Average temperature threshold exceeded interrupt enable. */ + kTMU_AverageTemperatureCriticalInterruptEnable = + TMU_TIER_ATCTEIE_MASK, /*!< Average temperature critical threshold exceeded interrupt enable. >*/ +}; + +/*! + * @brief TMU interrupt status flags. + */ +enum _tmu_interrupt_status_flags +{ + kTMU_ImmediateTemperatureStatusFlags = TMU_TIDR_ITTE_MASK, /*!< Immediate temperature threshold exceeded(ITTE). */ + kTMU_AverageTemperatureStatusFlags = TMU_TIDR_ATTE_MASK, /*!< Average temperature threshold exceeded(ATTE). */ + kTMU_AverageTemperatureCriticalStatusFlags = + TMU_TIDR_ATCTE_MASK, /*!< Average temperature critical threshold exceeded.(ATCTE) */ +}; + +/*! + * @brief TMU status flags. + */ +enum _tmu_status_flags +{ + kTMU_IntervalExceededStatusFlags = TMU_TSR_MIE_MASK, /*!< Monitoring interval exceeded. The time required to perform + measurement of all monitored sites has + exceeded the monitoring interval as defined by TMTMIR. */ + kTMU_OutOfLowRangeStatusFlags = TMU_TSR_ORL_MASK, /*!< Out-of-range low temperature measurement detected. A + temperature sensor detected a temperature + reading below the lowest measurable temperature of 0 °C. */ + kTMU_OutOfHighRangeStatusFlags = + TMU_TSR_ORH_MASK, /*!< Out-of-range high temperature measurement detected. A temperature sensor detected a + temperature + reading above the highest measurable temperature of 125 °C. */ +}; + +/*! + * @brief configuration for TMU thresold. + */ +typedef struct _tmu_thresold_config +{ + bool immediateThresoldEnable; /*!< Enable high temperature immediate threshold. */ + bool AverageThresoldEnable; /*!< Enable high temperature average threshold. */ + bool AverageCriticalThresoldEnable; /*!< Enable high temperature average critical threshold. */ + uint8_t immediateThresoldValue; /*!< Range:0U-125U. Valid when corresponding thresold is enabled. High temperature + immediate threshold value. + Determines the current upper temperature threshold, for anyenabled + monitored site. */ + uint8_t averageThresoldValue; /*!< Range:0U-125U. Valid when corresponding thresold is enabled. High temperature + average threshold value. + Determines the average upper temperature threshold, for any enabled + monitored site. */ + uint8_t averageCriticalThresoldValue; /*!< Range:0U-125U. Valid when corresponding thresold is enabled. High + temperature average critical threshold value. + Determines the average upper critical temperature threshold, for + any enabled monitored site. */ +} tmu_thresold_config_t; + +/*! + * @brief TMU interrupt status. + */ +typedef struct _tmu_interrupt_status +{ + uint32_t interruptDetectMask; /*!< The mask of interrupt status flags. Refer to "_tmu_interrupt_status_flags" + enumeration. */ + uint16_t immediateInterruptsSiteMask; /*!< The mask of the temperature sensor site associated with a detected ITTE + event. Please refer to "_tmu_monitor_site" enumeration. */ + uint16_t AverageInterruptsSiteMask; /*!< The mask of the temperature sensor site associated with a detected ATTE + event. Please refer to "_tmu_monitor_site" enumeration. */ + uint16_t AverageCriticalInterruptsSiteMask; /*!< The mask of the temperature sensor site associated with a detected + ATCTE event. + Please refer to "_tmu_monitor_site" enumeration. */ +} tmu_interrupt_status_t; +/*! + * @brief Average low pass filter setting. + */ +typedef enum _tmu_average_low_pass_filter +{ + kTMU_AverageLowPassFilter1_0 = 0U, /*!< Average low pass filter = 1. */ + kTMU_AverageLowPassFilter0_5 = 1U, /*!< Average low pass filter = 0.5. */ + kTMU_AverageLowPassFilter0_25 = 2U, /*!< Average low pass filter = 0.25. */ + kTMU_AverageLowPassFilter0_125 = 3U, /*!< Average low pass filter = 0.125. */ +} tmu_average_low_pass_filter_t; + +/*! + * @brief Configuration for TMU module. + */ +typedef struct _tmu_config +{ + uint8_t monitorInterval; /*!< Temperature monitoring interval in seconds. Please refer to specific table in RM. */ + uint16_t monitorSiteSelection; /*!< By setting the select bit for a temperature sensor site, it is enabled and + included in all monitoring functions. + If no site is selected, site 0 is monitored by default. Refer to + "_tmu_monitor_site" enumeration. Please look up + relevant table in reference manual. */ + tmu_average_low_pass_filter_t + averageLPF; /*!< The average temperature is calculated as: ALPF x Current_Temp + (1 - ALPF) x Average_Temp. + For proper operation, this field should only change when monitoring is disabled. */ +} tmu_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief Enable the access to TMU registers and Initialize TMU module. + * + * @param base TMU peripheral base address. + * @param config Pointer to configuration structure. Refer to "tmu_config_t" structure. + */ +void TMU_Init(TMU_Type *base, const tmu_config_t *config); + +/*! + * @brief De-initialize TMU module and Disable the access to DCDC registers. + * + * @param base TMU peripheral base address. + */ +void TMU_Deinit(TMU_Type *base); + +/*! + * @brief Gets the default configuration for TMU. + * + * This function initializes the user configuration structure to default value. The default value are: + * + * Example: + @code + config->monitorInterval = 0U; + config->monitorSiteSelection = 0U; + config->averageLPF = kTMU_AverageLowPassFilter1_0; + @endcode + * + * @param config Pointer to TMU configuration structure. + */ +void TMU_GetDefaultConfig(tmu_config_t *config); + +/*! + * @brief Enable/Disable the TMU module. + * + * @param base TMU peripheral base address. + * @param enable Switcher to enable/disable TMU. + */ +static inline void TMU_Enable(TMU_Type *base, bool enable) +{ + if (enable) + { + base->TMR |= TMU_TMR_ME_MASK; + } + else + { + base->TMR &= ~TMU_TMR_ME_MASK; + } +} + +/*! + * @brief Enable the TMU interrupts. + * + * @param base TMU peripheral base address. + * @param mask The interrupt mask. Refer to "_tmu_interrupt_enable" enumeration. + */ +static inline void TMU_EnableInterrupts(TMU_Type *base, uint32_t mask) +{ + base->TIER |= mask; +} + +/*! + * @brief Disable the TMU interrupts. + * + * @param base TMU peripheral base address. + * @param mask The interrupt mask. Refer to "_tmu_interrupt_enable" enumeration. + */ +static inline void TMU_DisableInterrupts(TMU_Type *base, uint32_t mask) +{ + base->TIER &= ~mask; +} + +/*! + * @brief Get interrupt status flags. + * + * @param base TMU peripheral base address. + * @param status The pointer to interrupt status structure. Record the current interrupt status. + * Please refer to "tmu_interrupt_status_t" structure. + */ +void TMU_GetInterruptStatusFlags(TMU_Type *base, tmu_interrupt_status_t *status); + +/*! + * @brief Clear interrupt status flags and corresponding interrupt critical site capture register. + * + * @param base TMU peripheral base address. + * @param mask The mask of interrupt status flags. Refer to "_tmu_interrupt_status_flags" enumeration. + */ +void TMU_ClearInterruptStatusFlags(TMU_Type *base, uint32_t mask); + +/*! + * @brief Get TMU status flags. + * + * @param base TMU peripheral base address. + * + * @return The mask of status flags. Refer to "_tmu_status_flags" enumeration. + */ +static inline uint32_t TMU_GetStatusFlags(TMU_Type *base) +{ + return base->TSR; +} + +/*! + * @brief Get the highest temperature reached for any enabled monitored site within the temperature + * sensor range. + * + * @param base TMU peripheral base address. + * @param temperature Highest temperature recorded in degrees Celsius by any enabled monitored site. + * + * @return Execution status. + * @retval kStatus_Success Temperature reading is valid. + * @retval kStatus_Fail Temperature reading is not valid due to no measured temperature within the + * sensor range of 0-125 °C for an enabled monitored site. + */ +status_t TMU_GetHighestTemperature(TMU_Type *base, uint32_t *temperature); + +/*! + * @brief Get the lowest temperature reached for any enabled monitored site within the temperature + * sensor range. + * + * @param base TMU peripheral base address. + * @param temperature Lowest temperature recorded in degrees Celsius by any enabled monitored site. + * + * @return Execution status. + * @retval kStatus_Success Temperature reading is valid. + * @retval kStatus_Fail Temperature reading is not valid due to no measured temperature within the + * sensor range of 0-125 °C for an enabled monitored site. + */ +status_t TMU_GetLowestTemperature(TMU_Type *base, uint32_t *temperature); + +/*! + * @brief Get the last immediate temperature at site n. The site must be part of the list of enabled + * monitored sites as defined by monitorSiteSelection in "tmu_config_t" structure. + * + * @param base TMU peripheral base address. + * @param siteIndex The index of the site user want to read. 0U: site0 ~ 15U: site15. + * @param temperature Last immediate temperature reading at site n . + * + * @return Execution status. + * @retval kStatus_Success Temperature reading is valid. + * @retval kStatus_Fail Temperature reading is not valid because temperature out of sensor range or + * first measurement still pending. + */ +status_t TMU_GetImmediateTemperature(TMU_Type *base, uint32_t siteIndex, uint32_t *temperature); + +/*! + * @brief Get the last average temperature at site n. The site must be part of the list of enabled + * monitored sites as defined by monitorSiteSelection in "tmu_config_t" structure. + * + * @param base TMU peripheral base address. + * @param siteIndex The index of the site user want to read. 0U: site0 ~ 15U: site15. + * @param temperature Last average temperature reading at site n . + * + * @return Execution status. + * @retval kStatus_Success Temperature reading is valid. + * @retval kStatus_Fail Temperature reading is not valid because temperature out of sensor range or + * first measurement still pending. + */ +status_t TMU_GetAverageTemperature(TMU_Type *base, uint32_t siteIndex, uint32_t *temperature); + +/*! + * @brief Configure the high temperature thresold value and enable/disable relevant thresold. + * + * @param base TMU peripheral base address. + * @param config Pointer to configuration structure. Refer to "tmu_thresold_config_t" structure. + */ +void TMU_SetHighTemperatureThresold(TMU_Type *base, const tmu_thresold_config_t *config); + +#if defined(__cplusplus) +} +#endif + +/* @} */ + +#endif /* __FSL_TMU_H__ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_uart.c b/devices/MIMX8MQ6/drivers/fsl_uart.c new file mode 100644 index 000000000..b49ed238e --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_uart.c @@ -0,0 +1,1600 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iuart" +#endif + +/* UART transfer state. */ +enum _uart_tansfer_states +{ + kUART_TxIdle, /* TX idle. */ + kUART_TxBusy, /* TX busy. */ + kUART_RxIdle, /* RX idle. */ + kUART_RxBusy, /* RX busy. */ + kUART_RxFramingError, /* Rx framing error */ + kUART_RxParityError /* Rx parity error */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Check whether the RX ring buffer is full. + * + * @param handle UART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base UART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the buffer to be sent. + */ +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of UART peripheral base address. */ +static UART_Type *const s_uartBases[] = UART_BASE_PTRS; + +/* Array of UART IRQ number. */ +const IRQn_Type s_uartIRQ[] = UART_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of UART clock name. */ +static const clock_ip_name_t s_uartClock[] = UART_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* UART ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +uart_isr_t s_uartIsr = (uart_isr_t)DefaultISR; +#else +uart_isr_t s_uartIsr; +#endif + +void *s_uartHandle[ARRAY_SIZE(s_uartBases)]; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Get the UART instance from peripheral base address. + * + * param base UART peripheral base address. + * return UART instance. + */ +uint32_t UART_GetInstance(UART_Type *base) +{ + uint32_t instance; + uint32_t uartArrayCount = (sizeof(s_uartBases) / sizeof(s_uartBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < uartArrayCount; instance++) + { + if (s_uartBases[instance] == base) + { + break; + } + } + assert(instance < uartArrayCount); + + return instance; +} + +/*! + * brief Get the length of received data in RX ring buffer. + * + * param handle UART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle) +{ + assert(handle != NULL); + + size_t size; + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)handle->rxRingBufferHead + handle->rxRingBufferSize - (size_t)handle->rxRingBufferTail; + } + else + { + size = (size_t)handle->rxRingBufferHead - (size_t)handle->rxRingBufferTail; + } + + return size; +} + +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle) +{ + assert(handle != NULL); + + bool full; + + if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + + return full; +} + +/*! + * brief Initializes an UART instance with the user configuration structure and the peripheral clock. + * + * This function configures the UART module with user-defined settings. Call the UART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the UART. + * code + * uart_config_t uartConfig; + * uartConfig.baudRate_Bps = 115200U; + * uartConfig.parityMode = kUART_ParityDisabled; + * uartConfig.dataBitsCount = kUART_EightDataBits; + * uartConfig.stopBitCount = kUART_OneStopBit; + * uartConfig.txFifoWatermark = 2; + * uartConfig.rxFifoWatermark = 1; + * uartConfig.rxRTSWatermark = 16; + * uartConfig.enableAutoBaudrate = false; + * uartConfig.enableTx = true; + * uartConfig.enableRx = true; + * uartConfig.enableRxRTS = false; + * uartConfig.enableTxCTS = false; + * UART_Init(UART1, &uartConfig, 24000000U); + * endcode + * + * param base UART peripheral base address. + * param config Pointer to a user-defined configuration structure. + * param srcClock_Hz UART clock source frequency in HZ. + * retval kStatus_Success UART initialize succeed + */ +status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz) +{ + /* Check argument */ + assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable uart clock */ + CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable UART Module. */ + UART_Disable(base); + /* Reset the transmit and receive state machines, all FIFOs and register + * USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD and UTS[6-3]. */ + UART_SoftwareReset(base); + + /* Set UART Module Register content to default value */ + base->UCR1 = 0x0; + base->UCR2 = UART_UCR2_SRST_MASK; + base->UCR3 = UART_UCR3_DSR_MASK | UART_UCR3_DCD_MASK | UART_UCR3_RI_MASK; + base->UCR4 = UART_UCR4_CTSTL(32); + base->UFCR = UART_UFCR_TXTL(2) | UART_UFCR_RXTL(1); + base->UESC = UART_UESC_ESC_CHAR(0x2B); + base->UTIM = 0x0; + base->ONEMS = 0x0; + base->UTS = UART_UTS_TXEMPTY_MASK | UART_UTS_RXEMPTY_MASK; + base->UMCR = 0x0; + + /* Set UART data word length, stop bit count, parity mode and communication + * direction according to uart init struct, disable RTS hardware flow control. + */ + base->UCR2 |= + ((uint32_t)UART_UCR2_WS(config->dataBitsCount) | (uint32_t)UART_UCR2_STPB(config->stopBitCount) | + (((uint32_t)(config->parityMode) << UART_UCR2_PROE_SHIFT) & (UART_UCR2_PREN_MASK | UART_UCR2_PROE_MASK)) | + (uint32_t)UART_UCR2_TXEN(config->enableTx) | (uint32_t)UART_UCR2_RXEN(config->enableRx) | + (uint32_t)UART_UCR2_IRTS(!config->enableTxCTS) | (uint32_t)UART_UCR2_CTSC(config->enableRxRTS)); + +#if (defined(FSL_FEATURE_IUART_RXDMUXSEL) && FSL_FEATURE_IUART_RXDMUXSEL) + /* For imx family device, UARTs are used in MUXED mode, so that this bit should always be set.*/ + base->UCR3 |= UART_UCR3_RXDMUXSEL_MASK; +#endif /* FSL_FEATURE_IUART_RXDMUXSEL */ + + /* Set TX/RX fifo water mark */ + UART_SetTxFifoWatermark(base, config->txFifoWatermark); + UART_SetRxFifoWatermark(base, config->rxFifoWatermark); + UART_SetRxRTSWatermark(base, config->rxRTSWatermark); + + if (config->enableAutoBaudRate) + { + /* Start automatic baud rate detection */ + UART_EnableAutoBaudRate(base, true); + } + else if (config->baudRate_Bps != 0U) + { + /* Stop automatic baud rate detection */ + UART_EnableAutoBaudRate(base, false); + /* Set BaudRate according to uart initialize struct. Baud Rate = Ref Freq / (16 * (UBMR + 1)/(UBIR+1)) */ + if (kStatus_Success != UART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz)) + { + return kStatus_UART_BaudrateNotSupport; + } + } + else + { + /* Stop automatic baud rate detection */ + UART_EnableAutoBaudRate(base, false); + } + + /* Enable UART module */ + UART_Enable(base); + + return kStatus_Success; +} + +/*! + * brief Deinitializes a UART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the UART clock. + * + * param base UART peripheral base address. + */ +void UART_Deinit(UART_Type *base) +{ + /* Wait transmit FIFO buffer and shift register empty */ + while (UART_USR2_TXDC_MASK != (base->USR2 & UART_USR2_TXDC_MASK)) + { + } + /* Disable UART Module */ + UART_Disable(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable uart clock */ + CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*!l + * brief Gets the default configuration structure. + * + * This function initializes the UART configuration structure to a default value. The default + * values are: + * uartConfig->baudRate_Bps = 115200U; + * uartConfig->parityMode = kUART_ParityDisabled; + * uartConfig->dataBitsCount = kUART_EightDataBits; + * uartConfig->stopBitCount = kUART_OneStopBit; + * uartConfig->txFifoWatermark = 2; + * uartConfig->rxFifoWatermark = 1; + * uartConfig->rxRTSWatermark = 16; + * uartConfig->enableAutoBaudrate = flase; + * uartConfig->enableTx = false; + * uartConfig->enableRx = false; + * uartConfig->enableRxRTS = false; + * uartConfig->enableTxCTS = false; + * + * param config Pointer to a configuration structure. + */ +void UART_GetDefaultConfig(uart_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->baudRate_Bps = 115200U; + config->parityMode = kUART_ParityDisabled; + config->dataBitsCount = kUART_EightDataBits; + config->stopBitCount = kUART_OneStopBit; + config->txFifoWatermark = 2; + config->rxFifoWatermark = 1; + config->rxRTSWatermark = 16; + config->enableAutoBaudRate = false; + config->enableTx = false; + config->enableRx = false; + config->enableRxRTS = false; + config->enableTxCTS = false; +} + +/* This UART instantiation uses a slightly different baud rate calculation. + * Baud Rate = Ref Freq / (16 * (UBMR + 1)/(UBIR+1)). + * To get a baud rate, three register need to be writen, UFCR,UBMR and UBIR + * At first, find the approximately maximum divisor of src_Clock and baudRate_Bps. + * If the numerator and denominator are larger then register maximum value(0xFFFF), + * both of numerator and denominator will be divided by the same value, which + * will ensure numerator and denominator range from 0~maximum value(0xFFFF). + * Then calculate UFCR and UBIR value from numerator, and get UBMR value from denominator. + */ +/*! + * brief Sets the UART instance baud rate. + * + * This function configures the UART module baud rate. This function is used to update + * the UART module baud rate after the UART module is initialized by the UART_Init. + * code + * UART_SetBaudRate(UART1, 115200U, 20000000U); + * endcode + * + * param base UART peripheral base address. + * param baudRate_Bps UART baudrate to be set. + * param srcClock_Hz UART clock source frequency in Hz. + * retval kStatus_UART_BaudrateNotSupport Baudrate is not support in the current clock source. + * retval kStatus_Success Set baudrate succeeded. + */ +status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t numerator = 0u; + uint32_t denominator = 0U; + uint32_t divisor = 0U; + uint32_t refFreqDiv = 0U; + uint32_t divider = 1U; + uint64_t baudDiff = 0U; + uint64_t tempNumerator = 0U; + uint32_t tempDenominator = 0u; + + /* get the approximately maximum divisor */ + numerator = srcClock_Hz; + denominator = baudRate_Bps << 4U; + divisor = 1U; + + while (denominator != 0U) + { + divisor = denominator; + denominator = numerator % denominator; + numerator = divisor; + } + + numerator = srcClock_Hz / divisor; + denominator = (baudRate_Bps << 4U) / divisor; + + /* numerator ranges from 1 ~ 7 * 64k */ + /* denominator ranges from 1 ~ 64k */ + if ((numerator > (UART_UBIR_INC_MASK * 7U)) || (denominator > UART_UBIR_INC_MASK)) + { + uint32_t m = (numerator - 1U) / (UART_UBIR_INC_MASK * 7U) + 1U; + uint32_t n = (denominator - 1U) / UART_UBIR_INC_MASK + 1U; + uint32_t max = m > n ? m : n; + numerator /= max; + denominator /= max; + if (0U == numerator) + { + numerator = 1U; + } + if (0U == denominator) + { + denominator = 1U; + } + } + divider = (numerator - 1U) / UART_UBIR_INC_MASK + 1U; + + switch (divider) + { + case 1: + refFreqDiv = 0x05U; + break; + case 2: + refFreqDiv = 0x04U; + break; + case 3: + refFreqDiv = 0x03U; + break; + case 4: + refFreqDiv = 0x02U; + break; + case 5: + refFreqDiv = 0x01U; + break; + case 6: + refFreqDiv = 0x00U; + break; + case 7: + refFreqDiv = 0x06U; + break; + default: + refFreqDiv = 0x05U; + break; + } + /* Compare the difference between baudRate_Bps and calculated baud rate. + * Baud Rate = Ref Freq / (16 * (UBMR + 1)/(UBIR+1)). + * baudDiff = (srcClock_Hz/divider)/( 16 * ((numerator / divider)/ denominator). + */ + tempNumerator = (uint64_t)srcClock_Hz; + tempDenominator = (numerator << 4U); + divisor = 1U; + /* get the approximately maximum divisor */ + while (tempDenominator != 0U) + { + divisor = tempDenominator; + tempDenominator = (uint32_t)(tempNumerator % tempDenominator); + tempNumerator = (uint64_t)divisor; + } + tempNumerator = (uint64_t)srcClock_Hz / (uint64_t)divisor; + tempDenominator = (numerator << 4U) / divisor; + baudDiff = (tempNumerator * (uint64_t)denominator) / (uint64_t)tempDenominator; + baudDiff = (baudDiff >= (uint64_t)baudRate_Bps) ? (baudDiff - (uint64_t)baudRate_Bps) : + ((uint64_t)baudRate_Bps - baudDiff); + + if (baudDiff < ((uint64_t)baudRate_Bps / 100UL * 3UL)) + { + base->UFCR &= ~UART_UFCR_RFDIV_MASK; + base->UFCR |= UART_UFCR_RFDIV(refFreqDiv); + base->UBIR = UART_UBIR_INC(denominator - 1U); + base->UBMR = UART_UBMR_MOD(numerator / divider - 1U); + base->ONEMS = UART_ONEMS_ONEMS(srcClock_Hz / (1000U * divider)); + + return kStatus_Success; + } + else + { + return kStatus_UART_BaudrateNotSupport; + } +} + +/*! + * brief Enables UART interrupts according to the provided mask. + * + * This function enables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See ref _uart_interrupt_enable. + * For example, to enable TX empty interrupt and RX data ready interrupt, do the following. + * code + * UART_EnableInterrupts(UART1,kUART_TxEmptyEnable | kUART_RxDataReadyEnable); + * endcode + * + * param base UART peripheral base address. + * param mask The interrupts to enable. Logical OR of ref _uart_interrupt_enable. + */ +void UART_EnableInterrupts(UART_Type *base, uint32_t mask) +{ + assert((0x7F3FF73FU & mask) != 0U); + + if ((0X3FU & mask) != 0U) + { + base->UCR1 |= ((mask << UART_UCR1_ADEN_SHIFT) & UART_UCR1_ADEN_MASK) | + (((mask >> 1) << UART_UCR1_TRDYEN_SHIFT) & UART_UCR1_TRDYEN_MASK) | + (((mask >> 2) << UART_UCR1_IDEN_SHIFT) & UART_UCR1_IDEN_MASK) | + (((mask >> 3) << UART_UCR1_RRDYEN_SHIFT) & UART_UCR1_RRDYEN_MASK) | + (((mask >> 4) << UART_UCR1_TXMPTYEN_SHIFT) & UART_UCR1_TXMPTYEN_MASK) | + (((mask >> 5) << UART_UCR1_RTSDEN_SHIFT) & UART_UCR1_RTSDEN_MASK); + } + if ((0X700U & mask) != 0U) + { + base->UCR2 |= (((mask >> 8) << UART_UCR2_ESCI_SHIFT) & UART_UCR2_ESCI_MASK) | + (((mask >> 9) << UART_UCR2_RTSEN_SHIFT) & UART_UCR2_RTSEN_MASK) | + (((mask >> 10) << UART_UCR2_ATEN_SHIFT) & UART_UCR2_ATEN_MASK); + } + if ((0x3FF000U & mask) != 0U) + { + base->UCR3 |= (((mask >> 12) << UART_UCR3_DTREN_SHIFT) & UART_UCR3_DTREN_MASK) | + (((mask >> 13) << UART_UCR3_PARERREN_SHIFT) & UART_UCR3_PARERREN_MASK) | + (((mask >> 14) << UART_UCR3_FRAERREN_SHIFT) & UART_UCR3_FRAERREN_MASK) | + (((mask >> 15) << UART_UCR3_DCD_SHIFT) & UART_UCR3_DCD_MASK) | + (((mask >> 16) << UART_UCR3_RI_SHIFT) & UART_UCR3_RI_MASK) | + (((mask >> 17) << UART_UCR3_RXDSEN_SHIFT) & UART_UCR3_RXDSEN_MASK) | + (((mask >> 18) << UART_UCR3_AIRINTEN_SHIFT) & UART_UCR3_AIRINTEN_MASK) | + (((mask >> 19) << UART_UCR3_AWAKEN_SHIFT) & UART_UCR3_AWAKEN_MASK) | + (((mask >> 20) << UART_UCR3_DTRDEN_SHIFT) & UART_UCR3_DTRDEN_MASK) | + (((mask >> 21) << UART_UCR3_ACIEN_SHIFT) & UART_UCR3_ACIEN_MASK); + } + if ((0x7F000000U & mask) != 0U) + { + base->UCR4 |= (((mask >> 24) << UART_UCR4_ENIRI_SHIFT) & UART_UCR4_ENIRI_MASK) | + (((mask >> 25) << UART_UCR4_WKEN_SHIFT) & UART_UCR4_WKEN_MASK) | + (((mask >> 26) << UART_UCR4_TCEN_SHIFT) & UART_UCR4_TCEN_MASK) | + (((mask >> 27) << UART_UCR4_BKEN_SHIFT) & UART_UCR4_BKEN_MASK) | + (((mask >> 28) << UART_UCR4_OREN_SHIFT) & UART_UCR4_OREN_MASK) | + (((mask >> 29) << UART_UCR4_DREN_SHIFT) & UART_UCR4_DREN_MASK) | + (((mask >> 30) << UART_UCR4_IDDMAEN_SHIFT) & UART_UCR4_IDDMAEN_MASK); + } +} + +/*! + * brief Disables the UART interrupts according to the provided mask. + * + * This function disables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See ref _uart_interrupt_enable. + * For example, to disable TX empty interrupt and RX data ready interrupt do the following. + * code + * UART_EnableInterrupts(UART1,kUART_TxEmptyEnable | kUART_RxDataReadyEnable); + * endcode + * + * param base UART peripheral base address. + * param mask The interrupts to disable. Logical OR of ref _uart_interrupt_enable. + */ +void UART_DisableInterrupts(UART_Type *base, uint32_t mask) +{ + assert((0x7F3FF73FU & mask) != 0U); + + if ((0X3FU & mask) != 0U) + { + base->UCR1 &= ~(((mask << UART_UCR1_ADEN_SHIFT) & UART_UCR1_ADEN_MASK) | + (((mask >> 1) << UART_UCR1_TRDYEN_SHIFT) & UART_UCR1_TRDYEN_MASK) | + (((mask >> 2) << UART_UCR1_IDEN_SHIFT) & UART_UCR1_IDEN_MASK) | + (((mask >> 3) << UART_UCR1_RRDYEN_SHIFT) & UART_UCR1_RRDYEN_MASK) | + (((mask >> 4) << UART_UCR1_TXMPTYEN_SHIFT) & UART_UCR1_TXMPTYEN_MASK) | + (((mask >> 5) << UART_UCR1_RTSDEN_SHIFT) & UART_UCR1_RTSDEN_MASK)); + } + if ((0X700U & mask) != 0U) + { + base->UCR2 &= ~((((mask >> 8) << UART_UCR2_ESCI_SHIFT) & UART_UCR2_ESCI_MASK) | + (((mask >> 9) << UART_UCR2_RTSEN_SHIFT) & UART_UCR2_RTSEN_MASK) | + (((mask >> 10) << UART_UCR2_ATEN_SHIFT) & UART_UCR2_ATEN_MASK)); + } + if ((0x3FF000U & mask) != 0U) + { + base->UCR3 &= ~((((mask >> 12) << UART_UCR3_DTREN_SHIFT) & UART_UCR3_DTREN_MASK) | + (((mask >> 13) << UART_UCR3_PARERREN_SHIFT) & UART_UCR3_PARERREN_MASK) | + (((mask >> 14) << UART_UCR3_FRAERREN_SHIFT) & UART_UCR3_FRAERREN_MASK) | + (((mask >> 15) << UART_UCR3_DCD_SHIFT) & UART_UCR3_DCD_MASK) | + (((mask >> 16) << UART_UCR3_RI_SHIFT) & UART_UCR3_RI_MASK) | + (((mask >> 17) << UART_UCR3_RXDSEN_SHIFT) & UART_UCR3_RXDSEN_MASK) | + (((mask >> 18) << UART_UCR3_AIRINTEN_SHIFT) & UART_UCR3_AIRINTEN_MASK) | + (((mask >> 19) << UART_UCR3_AWAKEN_SHIFT) & UART_UCR3_AWAKEN_MASK) | + (((mask >> 20) << UART_UCR3_DTRDEN_SHIFT) & UART_UCR3_DTRDEN_MASK) | + (((mask >> 21) << UART_UCR3_ACIEN_SHIFT) & UART_UCR3_ACIEN_MASK)); + } + if ((0x7F000000U & mask) != 0U) + { + base->UCR4 &= ~((((mask >> 24) << UART_UCR4_ENIRI_SHIFT) & UART_UCR4_ENIRI_MASK) | + (((mask >> 25) << UART_UCR4_WKEN_SHIFT) & UART_UCR4_WKEN_MASK) | + (((mask >> 26) << UART_UCR4_TCEN_SHIFT) & UART_UCR4_TCEN_MASK) | + (((mask >> 27) << UART_UCR4_BKEN_SHIFT) & UART_UCR4_BKEN_MASK) | + (((mask >> 28) << UART_UCR4_OREN_SHIFT) & UART_UCR4_OREN_MASK) | + (((mask >> 29) << UART_UCR4_DREN_SHIFT) & UART_UCR4_DREN_MASK) | + (((mask >> 30) << UART_UCR4_IDDMAEN_SHIFT) & UART_UCR4_IDDMAEN_MASK)); + } +} + +/*! + * brief Gets enabled UART interrupts. + * + * This function gets the enabled UART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators ref _uart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in ref _uart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * code + * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1); + * + * if (kUART_TxEmptyEnable & enabledInterrupts) + * { + * ... + * } + * endcode + * + * param base UART peripheral base address. + * return UART interrupt flags which are logical OR of the enumerators in ref _uart_interrupt_enable. + */ +uint32_t UART_GetEnabledInterrupts(UART_Type *base) +{ + assert(base != NULL); + uint32_t temp = 0U; + /* Get enabled interrupts from UCR1 */ + temp |= ((base->UCR1 & UART_UCR1_ADEN_MASK) >> UART_UCR1_ADEN_SHIFT) | + (((base->UCR1 & UART_UCR1_TRDYEN_MASK) >> UART_UCR1_TRDYEN_SHIFT) << 1) | + (((base->UCR1 & UART_UCR1_IDEN_MASK) >> UART_UCR1_IDEN_SHIFT) << 2) | + (((base->UCR1 & UART_UCR1_RRDYEN_MASK) >> UART_UCR1_RRDYEN_SHIFT) << 3) | + (((base->UCR1 & UART_UCR1_TXMPTYEN_MASK) >> UART_UCR1_TXMPTYEN_SHIFT) << 4) | + (((base->UCR1 & UART_UCR1_RTSDEN_MASK) >> UART_UCR1_RTSDEN_SHIFT) << 5); + /* Get enabled interrupts from UCR2 */ + temp |= (((base->UCR2 & UART_UCR2_ESCI_MASK) >> UART_UCR2_ESCI_SHIFT) << 8) | + (((base->UCR2 & UART_UCR2_RTSEN_MASK) >> UART_UCR2_RTSEN_SHIFT) << 9) | + (((base->UCR2 & UART_UCR2_ATEN_MASK) >> UART_UCR2_ATEN_SHIFT) << 10); + /* Get enabled interrupts from UCR3 */ + temp |= (((base->UCR3 & UART_UCR3_DTREN_MASK) >> UART_UCR3_DTREN_SHIFT) << 12) | + (((base->UCR3 & UART_UCR3_PARERREN_MASK) >> UART_UCR3_PARERREN_SHIFT) << 13) | + (((base->UCR3 & UART_UCR3_FRAERREN_MASK) >> UART_UCR3_FRAERREN_SHIFT) << 14) | + (((base->UCR3 & UART_UCR3_DCD_MASK) >> UART_UCR3_DCD_SHIFT) << 15) | + (((base->UCR3 & UART_UCR3_RI_MASK) >> UART_UCR3_RI_SHIFT) << 16) | + (((base->UCR3 & UART_UCR3_RXDSEN_MASK) >> UART_UCR3_RXDSEN_SHIFT) << 17) | + (((base->UCR3 & UART_UCR3_AIRINTEN_MASK) >> UART_UCR3_AIRINTEN_SHIFT) << 18) | + (((base->UCR3 & UART_UCR3_AWAKEN_MASK) >> UART_UCR3_AWAKEN_SHIFT) << 19) | + (((base->UCR3 & UART_UCR3_DTRDEN_MASK) >> UART_UCR3_DTRDEN_SHIFT) << 20) | + (((base->UCR3 & UART_UCR3_ACIEN_MASK) >> UART_UCR3_ACIEN_SHIFT) << 21); + /* Get enabled interrupts from UCR4 */ + temp |= (((base->UCR4 & UART_UCR4_ENIRI_MASK) >> UART_UCR4_ENIRI_SHIFT) << 24) | + (((base->UCR4 & UART_UCR4_WKEN_MASK) >> UART_UCR4_WKEN_SHIFT) << 25) | + (((base->UCR4 & UART_UCR4_TCEN_MASK) >> UART_UCR4_TCEN_SHIFT) << 26) | + (((base->UCR4 & UART_UCR4_BKEN_MASK) >> UART_UCR4_BKEN_SHIFT) << 27) | + (((base->UCR4 & UART_UCR4_OREN_MASK) >> UART_UCR4_OREN_SHIFT) << 28) | + (((base->UCR4 & UART_UCR4_DREN_MASK) >> UART_UCR4_DREN_SHIFT) << 29) | + (((base->UCR4 & UART_UCR4_IDDMAEN_MASK) >> UART_UCR4_IDDMAEN_SHIFT) << 30); + + return temp; +} + +/*! + * brief This function is used to get the current status of specific + * UART status flag(including interrupt flag). The available + * status flag can be select from ref uart_status_flag_t enumeration. + * + * param base UART base pointer. + * param flag Status flag to check. + * retval current state of corresponding status flag. + */ +bool UART_GetStatusFlag(UART_Type *base, uint32_t flag) +{ + volatile uint32_t *uart_reg; + + uart_reg = (uint32_t *)((uint32_t)base + (flag >> 16)); + return (bool)(((*uart_reg) >> (flag & 0x1FU)) & 0x1U); +} + +/*! + * brief This function is used to clear the current status + * of specific UART status flag. The available status + * flag can be select from ref uart_status_flag_t enumeration. + * + * param base UART base pointer. + * param flag Status flag to clear. + */ +void UART_ClearStatusFlag(UART_Type *base, uint32_t flag) +{ + volatile uint32_t *uart_reg = NULL; + uint32_t uart_mask = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (flag >> 16)); + uart_mask = (1UL << (flag & 0x0000001FU)); + + *uart_reg = uart_mask; +} + +/*! + * brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * param base UART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_UART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + assert(data != NULL); +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (length-- != 0U) + { + /* Wait for TX fifo valid. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->USR1 & UART_USR1_TRDY_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->USR1 & UART_USR1_TRDY_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_UART_Timeout; + } +#endif + UART_WriteByte(base, *(data++)); + } +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->USR2 & UART_USR2_TXDC_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->USR2 & UART_USR2_TXDC_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_UART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data, and reads data from the TX register. + * + * param base UART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data. + * retval kStatus_UART_NoiseError A noise error occurred while receiving data. + * retval kStatus_UART_FramingError A framing error occurred while receiving data. + * retval kStatus_UART_ParityError A parity error occurred while receiving data. + * retval kStatus_UART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + assert(data != NULL); + status_t status = kStatus_Success; +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (length-- != 0U) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif + /* Wait for receive data in URXD register is ready */ + while ((base->USR2 & UART_USR2_RDR_MASK) == 0U) + { +#if UART_RETRY_TIMES + if (--waitTimes == 0U) + { + status = kStatus_UART_Timeout; + break; + } +#endif + /* Over run check for receiving character */ + if ((base->USR2 & UART_USR2_ORE_MASK) != 0U) + { + UART_ClearStatusFlag(base, (uint32_t)kUART_RxOverrunFlag); + status = kStatus_UART_RxHardwareOverrun; + break; + } + /* Parity error check for receiving character */ + if ((base->USR1 & UART_USR1_PARITYERR_MASK) != 0U) + { + UART_ClearStatusFlag(base, (uint32_t)kUART_ParityErrorFlag); + status = kStatus_UART_ParityError; + } + /* Framing error check for receiving character */ + if ((base->USR1 & UART_USR1_FRAMERR_MASK) != 0U) + { + UART_ClearStatusFlag(base, (uint32_t)kUART_FrameErrorFlag); + status = kStatus_UART_FramingError; + } + if (status != kStatus_Success) + { + break; + } + } + if (kStatus_Success == status) + { + /* Read data from URXD */ + *(data++) = UART_ReadByte(base); + } + else + { + break; + } + } + + return status; +} + +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + assert(data != NULL); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + * peripheral to write. UTXD register holds the parallel transmit data inputs. In 7-bit mode, + * D7 is ignored. In 8-bit mode, all bits are used. + */ + for (i = 0; i < length; i++) + { + base->UTXD = (uint32_t)data[i] & UART_UTXD_TX_DATA_MASK; + } +} + +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + assert(data != NULL); + + size_t i; + + /* The Non Blocking read data API assume user have ensured there is enough space in + * peripheral to write. The URXD holds the received character,In 7-bit mode, + * the most significant bit (MSB) is forced to 0.In 8-bit mode, all bits are active. + */ + for (i = 0; i < length; i++) + { + data[i] = (uint8_t)((base->URXD & UART_URXD_RX_DATA_MASK) >> UART_URXD_RX_DATA_SHIFT); + } +} + +/*! + * brief Initializes the UART handle. + * + * This function initializes the UART handle which can be used for other UART + * transactional APIs. Usually, for a specified UART instance, + * call this API once to get the initialized handle. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + uint32_t instance; + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kUART_RxIdle; + handle->txState = (uint8_t)kUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Get instance from peripheral base address. */ + instance = UART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_uartHandle[instance] = handle; + + s_uartIsr = UART_TransferHandleIRQ; + + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(s_uartIRQ[instance]); +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize Size of the ring buffer. + */ +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + assert(handle != NULL); + assert(ringBuffer != NULL); + + /* Setup the ringbuffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + UART_EnableInterrupts(base, (uint32_t)kUART_RxReadyEnable | (uint32_t)kUART_AgingTimerEnable | + (uint32_t)kUART_RxOverrunEnable | (uint32_t)kUART_ParityErrorEnable | + (uint32_t)kUART_FrameErrorEnable); +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + */ +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle) +{ + assert(handle != NULL); + + if (handle->rxState == (uint8_t)kUART_RxIdle) + { + UART_DisableInterrupts(base, (uint32_t)kUART_RxReadyEnable | (uint32_t)kUART_AgingTimerEnable | + (uint32_t)kUART_RxOverrunEnable | (uint32_t)kUART_ParityErrorEnable | + (uint32_t)kUART_FrameErrorEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the ref kStatus_UART_TxIdle as status parameter. + * + * note The kStatus_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX, + * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param xfer UART transfer structure. See #uart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_UART_TxBusy Previous transmission still not finished; data not all written to TX register yet. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + assert(xfer->dataSize != 0U); + assert(xfer->txData != NULL); + + status_t status; + + /* Return error if current TX busy. */ + if ((uint8_t)kUART_TxBusy == handle->txState) + { + status = kStatus_UART_TxBusy; + } + else + { + handle->txData = xfer->txData; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kUART_TxBusy; + + /* Enable transmiter interrupt. */ + UART_EnableInterrupts(base, (uint32_t)kUART_TxReadyEnable); + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + */ +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle) +{ + assert(handle != NULL); + + UART_DisableInterrupts(base, (uint32_t)kUART_TxEmptyEnable); + + handle->txDataSize = 0; + handle->txState = (uint8_t)kUART_TxIdle; +} + +/*! + * brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument The parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + assert(handle != NULL); + assert(count != NULL); + + if ((uint8_t)kUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the UART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param xfer UART transfer structure, see #uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into transmit queue. + * retval kStatus_UART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes) +{ + assert(handle != NULL); + assert(xfer != NULL); + assert(xfer->rxData != NULL); + assert(xfer->dataSize != 0U); + + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + + if ((uint8_t)kUART_RxBusy == handle->rxState) + { + status = kStatus_UART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer != NULL) + { + /* Disable UART RX IRQ, protect ring buffer. */ + UART_DisableInterrupts(base, (uint32_t)kUART_RxReadyEnable | (uint32_t)kUART_AgingTimerEnable); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = UART_TransferGetRxRingBufferLength(handle); + + if (bytesToCopy != 0U) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == (uint16_t)handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive != 0U) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = xfer->dataSize; + handle->rxState = (uint8_t)kUART_RxBusy; + } + + /* Enable UART RX IRQ if previously enabled. */ + UART_EnableInterrupts(base, (uint32_t)kUART_RxReadyEnable | (uint32_t)kUART_AgingTimerEnable); + + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if ((handle->callback) != NULL) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kUART_RxBusy; + + /* Enable RX/Rx overrun/framing error interrupt. */ + UART_EnableInterrupts(base, (uint32_t)kUART_RxReadyEnable | (uint32_t)kUART_AgingTimerEnable | + (uint32_t)kUART_RxOverrunEnable | (uint32_t)kUART_ParityErrorEnable | + (uint32_t)kUART_FrameErrorEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes != NULL) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + */ +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle) +{ + assert(handle != NULL); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (handle->rxRingBuffer == NULL) + { + /* Disable RX interrupt. */ + UART_DisableInterrupts(base, (uint32_t)kUART_RxReadyEnable | (uint32_t)kUART_AgingTimerEnable | + (uint32_t)kUART_RxOverrunEnable | (uint32_t)kUART_ParityErrorEnable | + (uint32_t)kUART_FrameErrorEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kUART_RxIdle; +} + +/*! + * brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + assert(handle != NULL); + assert(count != NULL); + + if ((uint8_t)kUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (count == NULL) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +/*! + * brief UART IRQ handle function. + * + * This function handles the UART transmit and receive IRQ request. + * + * param base UART peripheral base address. + * param irqHandle UART handle pointer. + */ +void UART_TransferHandleIRQ(UART_Type *base, void *irqHandle) +{ + assert(irqHandle != NULL); + + uint8_t count; + uint8_t tempCount; + uart_handle_t *handle = (uart_handle_t *)irqHandle; + + /* If RX framing error */ + if ((UART_USR1_FRAMERR_MASK & base->USR1) != 0U) + { + /* Write 1 to clear framing error flag */ + base->USR1 |= UART_USR1_FRAMERR_MASK; + + handle->rxState = (uint8_t)kUART_RxFramingError; + handle->rxDataSize = 0U; + /* Trigger callback. */ + if ((handle->callback) != NULL) + { + handle->callback(base, handle, kStatus_UART_FramingError, handle->userData); + } + } + + /* If RX parity error */ + if ((UART_USR1_PARITYERR_MASK & base->USR1) != 0U) + { + /* Write 1 to clear parity error flag. */ + base->USR1 |= UART_USR1_PARITYERR_MASK; + + handle->rxState = (uint8_t)kUART_RxParityError; + handle->rxDataSize = 0U; + /* Trigger callback. */ + if ((handle->callback) != NULL) + { + handle->callback(base, handle, kStatus_UART_ParityError, handle->userData); + } + } + + /* If RX overrun. */ + if ((UART_USR2_ORE_MASK & base->USR2) != 0U) + { + /* Write 1 to clear overrun flag. */ + base->USR2 |= UART_USR2_ORE_MASK; + /* Trigger callback. */ + if ((handle->callback) != NULL) + { + handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data FIFO buffer reach the trigger level */ + if (((UART_USR1_RRDY_MASK & base->USR1) != 0U) && ((UART_UCR1_RRDYEN_MASK & base->UCR1) != 0U)) + { + /* Get the size that stored in receive FIFO buffer for this interrupt. */ + count = (uint8_t)((base->UFCR & UART_UFCR_RXTL_MASK) >> UART_UFCR_RXTL_SHIFT); + + /* If count and handle->rxDataSize are not 0, first save data to handle->rxData. */ + while ((count != 0U) && (handle->rxDataSize != 0U)) + { + tempCount = (uint8_t)MIN(handle->rxDataSize, count); + /* Using non block API to read the data from the registers. */ + UART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (handle->rxDataSize == 0U) + { + handle->rxState = (uint8_t)kUART_RxIdle; + + if ((handle->callback) != NULL) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (handle->rxRingBuffer != NULL) + { + while (count-- != 0U) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + if ((handle->callback) != NULL) + { + handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == (uint16_t)handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = + (uint8_t)((base->URXD & UART_URXD_RX_DATA_MASK) >> UART_URXD_RX_DATA_SHIFT); + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == (uint16_t)handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + + else if (handle->rxDataSize == 0U) + { + /* Disable RX interrupt/overrun interrupt/framing error interrupt */ + UART_DisableInterrupts(base, (uint32_t)kUART_RxReadyEnable | (uint32_t)kUART_AgingTimerEnable | + (uint32_t)kUART_RxOverrunEnable | (uint32_t)kUART_ParityErrorEnable | + (uint32_t)kUART_FrameErrorEnable); + } + else + { + } + } + /* Receive FIFO buffer has been idle for a time of 8 characters, and FIFO data level + * is less than RxFIFO threshold level. + */ + if (((UART_USR1_AGTIM_MASK & base->USR1) != 0U) && ((UART_UCR2_ATEN_MASK & base->UCR2) != 0U)) + { + /* If count and handle->rxDataSize are not 0, first save data to handle->rxData. */ + while (((base->USR2 & UART_USR2_RDR_MASK) != 0U) && (handle->rxDataSize != 0U)) + { + /* Read one data from the URXD registers. */ + *handle->rxData = UART_ReadByte(base); + handle->rxData += 1U; + handle->rxDataSize -= 1U; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (handle->rxDataSize == 0U) + { + handle->rxState = (uint8_t)kUART_RxIdle; + + if ((handle->callback) != NULL) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (handle->rxRingBuffer != NULL) + { + while ((base->USR2 & UART_USR2_RDR_MASK) != 0U) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + if ((handle->callback) != NULL) + { + handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == (uint16_t)handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + /* Read one data from URXD register. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = UART_ReadByte(base); + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == (uint16_t)handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If ring buffer is not used and rxDataSize is 0 */ + else if (handle->rxDataSize == 0U) + { + /* Disable RX interrupt/overrun interrupt/framing error interrupt */ + UART_DisableInterrupts(base, (uint32_t)kUART_RxReadyEnable | (uint32_t)kUART_AgingTimerEnable | + (uint32_t)kUART_RxOverrunEnable | (uint32_t)kUART_ParityErrorEnable | + (uint32_t)kUART_FrameErrorEnable); + } + else + { + } + /* Clear aging timer flag for next interrupt */ + UART_ClearStatusFlag(base, (uint32_t)kUART_AgingTimerFlag); + } + /* If frame error or parity error happened, stop the RX interrupt when use no ring buffer */ + if (((handle->rxState == (uint8_t)kUART_RxFramingError) || (handle->rxState == (uint8_t)kUART_RxParityError)) && + (handle->rxRingBuffer == NULL)) + { + /* Disable Receive ready interrupt, aging timer interrupt, receive over run interrupt, + * parity error interrupt and frame error interrupt. + */ + UART_DisableInterrupts(base, (uint32_t)kUART_RxReadyEnable | (uint32_t)kUART_AgingTimerEnable | + (uint32_t)kUART_RxOverrunEnable | (uint32_t)kUART_ParityErrorEnable | + (uint32_t)kUART_FrameErrorEnable); + } + + /* Send data register empty and the interrupt is enabled. */ + if (((UART_USR1_TRDY_MASK & base->USR1) != 0U) && ((UART_UCR1_TRDYEN_MASK & base->UCR1) != 0U)) + { + /* Get the bytes that available at this moment. */ + if (0U != ((base->UFCR & UART_UFCR_TXTL_MASK) >> UART_UFCR_TXTL_SHIFT)) + { + if ((UART_UTS_TXEMPTY_MASK & base->UTS) != 0U) + { + count = FSL_FEATURE_IUART_FIFO_SIZEn(base); + } + else + { + count = (uint8_t)FSL_FEATURE_IUART_FIFO_SIZEn(base) - + (uint8_t)((base->UFCR & UART_UFCR_TXTL_MASK) >> UART_UFCR_TXTL_SHIFT); + } + } + else + { + count = 1U; + } + + while ((count != 0U) && (handle->txDataSize != 0U)) + { + if (0U != ((base->UFCR & UART_UFCR_TXTL_MASK) >> UART_UFCR_TXTL_SHIFT)) + { + tempCount = (uint8_t)MIN(handle->txDataSize, count); + } + else + { + tempCount = 1U; + } + /* Using non block API to write the data to the registers. */ + UART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData += tempCount; + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, TX finished. */ + if (handle->txDataSize == 0U) + { + handle->txState = (uint8_t)kUART_TxIdle; + /* Disable TX FIFO buffer empty interrupt. */ + UART_DisableInterrupts(base, (uint32_t)kUART_TxReadyEnable); + /* Enable TX complete interrupt. */ + UART_EnableInterrupts(base, (uint32_t)kUART_TxCompleteEnable); + } + } + } + + /* TX complete and the interrupt is enabled. */ + if ((0U != (UART_USR2_TXDC_MASK & base->USR2)) && (0U != (UART_UCR4_TCEN_MASK & base->UCR4)) && + (handle->txState == (uint8_t)kUART_TxIdle)) + { + /* Disable TX complete interrupt. */ + UART_DisableInterrupts(base, (uint32_t)kUART_TxCompleteEnable); + + /* Trigger callback. */ + if ((handle->callback) != NULL) + { + handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData); + } + } +} + +#if defined(UART1) +void UART1_DriverIRQHandler(void); +void UART1_DriverIRQHandler(void) +{ + s_uartIsr(UART1, s_uartHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(UART2) +void UART2_DriverIRQHandler(void); +void UART2_DriverIRQHandler(void) +{ + s_uartIsr(UART2, s_uartHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(UART3) +void UART3_DriverIRQHandler(void); +void UART3_DriverIRQHandler(void) +{ + s_uartIsr(UART3, s_uartHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(UART4) +void UART4_DriverIRQHandler(void); +void UART4_DriverIRQHandler(void) +{ + s_uartIsr(UART4, s_uartHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(UART5) +void UART5_DriverIRQHandler(void); +void UART5_DriverIRQHandler(void) +{ + s_uartIsr(UART5, s_uartHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(UART6) +void UART6_DriverIRQHandler(void); +void UART6_DriverIRQHandler(void) +{ + s_uartIsr(UART6, s_uartHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(UART7) +void UART7_DriverIRQHandler(void); +void UART7_DriverIRQHandler(void) +{ + s_uartIsr(UART7, s_uartHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(UART8) +void UART8_DriverIRQHandler(void); +void UART8_DriverIRQHandler(void) +{ + s_uartIsr(UART8, s_uartHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/devices/MIMX8MQ6/drivers/fsl_uart.h b/devices/MIMX8MQ6/drivers/fsl_uart.h new file mode 100644 index 000000000..b9e0c7ae0 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_uart.h @@ -0,0 +1,927 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_UART_H_ +#define _FSL_UART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup uart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief UART driver version. */ +#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) +/*@}*/ + +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + +/*! @brief Error codes for the UART driver. */ +enum +{ + kStatus_UART_TxBusy = MAKE_STATUS(kStatusGroup_IUART, 0), /*!< Transmitter is busy. */ + kStatus_UART_RxBusy = MAKE_STATUS(kStatusGroup_IUART, 1), /*!< Receiver is busy. */ + kStatus_UART_TxIdle = MAKE_STATUS(kStatusGroup_IUART, 2), /*!< UART transmitter is idle. */ + kStatus_UART_RxIdle = MAKE_STATUS(kStatusGroup_IUART, 3), /*!< UART receiver is idle. */ + kStatus_UART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_IUART, 4), /*!< TX FIFO watermark too large */ + kStatus_UART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_IUART, 5), /*!< RX FIFO watermark too large */ + kStatus_UART_FlagCannotClearManually = + MAKE_STATUS(kStatusGroup_IUART, 6), /*!< UART flag can't be manually cleared. */ + kStatus_UART_Error = MAKE_STATUS(kStatusGroup_IUART, 7), /*!< Error happens on UART. */ + kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_IUART, 8), /*!< UART RX software ring buffer overrun. */ + kStatus_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_IUART, 9), /*!< UART RX receiver overrun. */ + kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_IUART, 10), /*!< UART noise error. */ + kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_IUART, 11), /*!< UART framing error. */ + kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_IUART, 12), /*!< UART parity error. */ + kStatus_UART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_IUART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_UART_BreakDetect = MAKE_STATUS(kStatusGroup_IUART, 14), /*!< Receiver detect BREAK signal */ + kStatus_UART_Timeout = MAKE_STATUS(kStatusGroup_IUART, 15), /*!< UART times out. */ +}; + +/*! @brief UART data bits count. */ +typedef enum _uart_data_bits +{ + kUART_SevenDataBits = 0x0U, /*!< Seven data bit */ + kUART_EightDataBits = 0x1U, /*!< Eight data bit */ +} uart_data_bits_t; + +/*! @brief UART parity mode. */ +typedef enum _uart_parity_mode +{ + kUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUART_ParityEven = 0x2U, /*!< Even error check is selected */ + kUART_ParityOdd = 0x3U, /*!< Odd error check is selected */ +} uart_parity_mode_t; + +/*! @brief UART stop bit count. */ +typedef enum _uart_stop_bit_count +{ + kUART_OneStopBit = 0x0U, /*!< One stop bit */ + kUART_TwoStopBit = 0x1U, /*!< Two stop bits */ +} uart_stop_bit_count_t; + +/*! @brief UART idle condition detect. */ +typedef enum _uart_idle_condition +{ + kUART_IdleFor4Frames = 0x0U, /*!< Idle for more than 4 frames */ + kUART_IdleFor8Frames = 0x1U, /*!< Idle for more than 8 frames */ + kUART_IdleFor16Frames = 0x2U, /*!< Idle for more than 16 frames */ + kUART_IdleFor32Frames = 0x3U, /*!< Idle for more than 32 frames */ +} uart_idle_condition_t; + +/*! @brief This structure contains the settings for all of the UART interrupt configurations. */ +enum _uart_interrupt_enable +{ + kUART_AutoBaudEnable = 0x1U, /* !< Automatic baud rate detection Interrupt Enable. */ + kUART_TxReadyEnable = (0X1U << 1), /* !< transmitter ready Interrupt Enable. */ + kUART_IdleEnable = (0x1U << 2), /* !< IDLE Interrupt Enable. */ + kUART_RxReadyEnable = (0x1U << 3), /* !< Receiver Ready Interrupt Enable. */ + kUART_TxEmptyEnable = (0x1U << 4), /* !< Transmitter Empty Interrupt Enable. */ + kUART_RtsDeltaEnable = (0x1U << 5), /* !< RTS Delta Interrupt Enable. */ + kUART_EscapeEnable = (0x1U << 8), /* !< Escape Sequence Interrupt Enable. */ + kUART_RtsEnable = (0x1U << 9), /* !< Request to Send Interrupt Enable. */ + kUART_AgingTimerEnable = (0x1U << 10), /* !< Aging Timer Interrupt Enable. */ + kUART_DtrEnable = (0x1U << 12), /* !< Data Terminal Ready Interrupt Enable. */ + kUART_ParityErrorEnable = (0x1U << 13), /* !< Parity Error Interrupt Enable. */ + kUART_FrameErrorEnable = (0x1U << 14), /* !< Frame Error Interrupt Enable. */ + kUART_DcdEnable = (0x1U << 15), /* !< Data Carrier Detect Interrupt Enable. */ + kUART_RiEnable = (0x1U << 16), /* !< Ring Indicator Interrupt Enable. */ + kUART_RxDsEnable = (0x1U << 17), /* !< Receive Status Interrupt Enable. */ + kUART_tAirWakeEnable = (0x1U << 18), /* !< Asynchronous IR WAKE Interrupt Enable. */ + kUART_AwakeEnable = (0x1U << 19), /* !< Asynchronous WAKE Interrupt Enable. */ + kUART_DtrDeltaEnable = (0x1U << 20), /* !< Data Terminal Ready Delta Interrupt Enable. */ + kUART_AutoBaudCntEnable = (0x1U << 21), /* !< Auto-baud Counter Interrupt Enable. */ + kUART_IrEnable = (0X1U << 24), /* !< Serial Infrared Interrupt Enable. */ + kUART_WakeEnable = (0X1U << 25), /* !< WAKE Interrupt Enable. */ + kUART_TxCompleteEnable = (0X1U << 26), /* !< TransmitComplete Interrupt Enable. */ + kUART_BreakDetectEnable = (0X1U << 27), /* !< BREAK Condition Detected Interrupt Enable. */ + kUART_RxOverrunEnable = (0X1U << 28), /* !< Receiver Overrun Interrupt Enable. */ + kUART_RxDataReadyEnable = (0X1U << 29), /* !< Receive Data Ready Interrupt Enable. */ + kUART_RxDmaIdleEnable = (0X1U << 30), /* !< Receive DMA IDLE detect Interrupt Enable. */ + kUART_AllInterruptsEnable = + kUART_AutoBaudEnable | kUART_TxReadyEnable | kUART_IdleEnable | kUART_RxReadyEnable | kUART_TxEmptyEnable | + kUART_RtsDeltaEnable | kUART_EscapeEnable | kUART_RtsEnable | kUART_AgingTimerEnable | kUART_DtrEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable | kUART_DcdEnable | kUART_RiEnable | kUART_RxDsEnable | + kUART_tAirWakeEnable | kUART_AwakeEnable | kUART_DtrDeltaEnable | kUART_AutoBaudCntEnable | kUART_IrEnable | + kUART_WakeEnable | kUART_TxCompleteEnable | kUART_BreakDetectEnable | kUART_RxOverrunEnable | + kUART_RxDataReadyEnable | kUART_RxDmaIdleEnable, +}; + +/*! + * @brief UART status flags. + * + * This provides constants for the UART status flags for use in the UART functions. + */ +enum +{ + kUART_RxCharReadyFlag = 0x0000000FU, /*!< Rx Character Ready Flag. */ + kUART_RxErrorFlag = 0x0000000EU, /*!< Rx Error Detect Flag. */ + kUART_RxOverrunErrorFlag = 0x0000000DU, /*!< Rx Overrun Flag. */ + kUART_RxFrameErrorFlag = 0x0000000CU, /*!< Rx Frame Error Flag. */ + kUART_RxBreakDetectFlag = 0x0000000BU, /*!< Rx Break Detect Flag. */ + kUART_RxParityErrorFlag = 0x0000000AU, /*!< Rx Parity Error Flag. */ + kUART_ParityErrorFlag = 0x0094000FU, /*!< Parity Error Interrupt Flag. */ + kUART_RtsStatusFlag = 0x0094000EU, /*!< RTS_B Pin Status Flag. */ + kUART_TxReadyFlag = 0x0094000DU, /*!< Transmitter Ready Interrupt/DMA Flag. */ + kUART_RtsDeltaFlag = 0x0094000CU, /*!< RTS Delta Flag. */ + kUART_EscapeFlag = 0x0094000BU, /*!< Escape Sequence Interrupt Flag. */ + kUART_FrameErrorFlag = 0x0094000AU, /*!< Frame Error Interrupt Flag. */ + kUART_RxReadyFlag = 0x00940009U, /*!< Receiver Ready Interrupt/DMA Flag. */ + kUART_AgingTimerFlag = 0x00940008U, /*!< Aging Timer Interrupt Flag. */ + kUART_DtrDeltaFlag = 0x00940007U, /*!< DTR Delta Flag. */ + kUART_RxDsFlag = 0x00940006U, /*!< Receiver IDLE Interrupt Flag. */ + kUART_tAirWakeFlag = 0x00940005U, /*!< Asynchronous IR WAKE Interrupt Flag. */ + kUART_AwakeFlag = 0x00940004U, /*!< Asynchronous WAKE Interrupt Flag. */ + kUART_Rs485SlaveAddrMatchFlag = 0x00940003U, /*!< RS-485 Slave Address Detected Interrupt Flag. */ + kUART_AutoBaudFlag = 0x0098000FU, /*!< Automatic Baud Rate Detect Complete Flag. */ + kUART_TxEmptyFlag = 0x0098000EU, /*!< Transmit Buffer FIFO Empty. */ + kUART_DtrFlag = 0x0098000DU, /*!< DTR edge triggered interrupt flag. */ + kUART_IdleFlag = 0x0098000CU, /*!< Idle Condition Flag. */ + kUART_AutoBaudCntStopFlag = 0x0098000BU, /*!< Auto-baud Counter Stopped Flag. */ + kUART_RiDeltaFlag = 0x0098000AU, /*!< Ring Indicator Delta Flag. */ + kUART_RiFlag = 0x00980009U, /*!< Ring Indicator Input Flag. */ + kUART_IrFlag = 0x00980008U, /*!< Serial Infrared Interrupt Flag. */ + kUART_WakeFlag = 0x00980007U, /*!< Wake Flag. */ + kUART_DcdDeltaFlag = 0x00980006U, /*!< Data Carrier Detect Delta Flag. */ + kUART_DcdFlag = 0x00980005U, /*!< Data Carrier Detect Input Flag. */ + kUART_RtsFlag = 0x00980004U, /*!< RTS Edge Triggered Interrupt Flag. */ + kUART_TxCompleteFlag = 0x00980003U, /*!< Transmitter Complete Flag. */ + kUART_BreakDetectFlag = 0x00980002U, /*!< BREAK Condition Detected Flag. */ + kUART_RxOverrunFlag = 0x00980001U, /*!< Overrun Error Flag. */ + kUART_RxDataReadyFlag = 0x00980000U, /*!< Receive Data Ready Flag. */ +}; + +/*! @brief UART configuration structure. */ +typedef struct _uart_config +{ + uint32_t baudRate_Bps; /*!< UART baud rate. */ + uart_parity_mode_t parityMode; /*!< Parity error check mode of this module. */ + uart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits in one frame. */ + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ + uint8_t rxRTSWatermark; /*!< RX RTS watermark, RX FIFO data count being larger than this triggers RTS deassertion */ + bool enableAutoBaudRate; /*!< Enable automatic baud rate detection */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ +} uart_config_t; + +/*! @brief UART transfer structure. */ +typedef struct _uart_transfer +{ + /* + * Use separate TX and RX data pointer, because TX data is const data. + * The member data is kept for backward compatibility. + */ + union + { + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + }; + size_t dataSize; /*!< The byte count to be transfer. */ +} uart_transfer_t; + +/*! @brief Forward declaration of the handle typedef. */ +typedef struct _uart_handle uart_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData); + +/*! @brief UART handle structure. */ +struct _uart_handle +{ + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + uart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*uart_isr_t)(UART_Type *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of UART IRQ number. */ +extern const IRQn_Type s_uartIRQ[]; + +/* UART ISR for transactional APIs. */ +extern uart_isr_t s_uartIsr; + +/*! Pointers to uart handles for each instance. */ +extern void *s_uartHandle[]; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Get the UART instance from peripheral base address. + * + * @param base UART peripheral base address. + * @return UART instance. + */ +uint32_t UART_GetInstance(UART_Type *base); + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Resets the UART using software. + * + * This function resets the transmit and receive state machines, all FIFOs and register + * USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3] + * + * @param base UART peripheral base address. + */ +static inline void UART_SoftwareReset(UART_Type *base) +{ + base->UCR2 &= ~UART_UCR2_SRST_MASK; + while ((base->UCR2 & UART_UCR2_SRST_MASK) == 0U) + { + } +} + +/* @} */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an UART instance with the user configuration structure and the peripheral clock. + * + * This function configures the UART module with user-defined settings. Call the UART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the UART. + * @code + * uart_config_t uartConfig; + * uartConfig.baudRate_Bps = 115200U; + * uartConfig.parityMode = kUART_ParityDisabled; + * uartConfig.dataBitsCount = kUART_EightDataBits; + * uartConfig.stopBitCount = kUART_OneStopBit; + * uartConfig.txFifoWatermark = 2; + * uartConfig.rxFifoWatermark = 1; + * uartConfig.enableAutoBaudrate = false; + * uartConfig.enableTx = true; + * uartConfig.enableRx = true; + * UART_Init(UART1, &uartConfig, 24000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @param srcClock_Hz UART clock source frequency in HZ. + * @retval kStatus_Success UART initialize succeed + */ +status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a UART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the UART clock. + * + * @param base UART peripheral base address. + */ +void UART_Deinit(UART_Type *base); + +/*!l + * @brief Gets the default configuration structure. + * + * This function initializes the UART configuration structure to a default value. The default + * values are: + * uartConfig->baudRate_Bps = 115200U; + * uartConfig->parityMode = kUART_ParityDisabled; + * uartConfig->dataBitsCount = kUART_EightDataBits; + * uartConfig->stopBitCount = kUART_OneStopBit; + * uartConfig->txFifoWatermark = 2; + * uartConfig->rxFifoWatermark = 1; + * uartConfig->enableAutoBaudrate = flase; + * uartConfig->enableTx = false; + * uartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void UART_GetDefaultConfig(uart_config_t *config); + +/*! + * @brief Sets the UART instance baud rate. + * + * This function configures the UART module baud rate. This function is used to update + * the UART module baud rate after the UART module is initialized by the UART_Init. + * @code + * UART_SetBaudRate(UART1, 115200U, 20000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param baudRate_Bps UART baudrate to be set. + * @param srcClock_Hz UART clock source frequency in Hz. + * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief This function is used to Enable the UART Module. + * + * @param base UART base pointer. + */ +static inline void UART_Enable(UART_Type *base) +{ + base->UCR1 |= UART_UCR1_UARTEN_MASK; +} + +/*! + * @brief This function is used to configure the IDLE line condition. + * + * @param base UART base pointer. + * @param condition IDLE line detect condition of the enumerators in @ref uart_idle_condition_t. + */ +static inline void UART_SetIdleCondition(UART_Type *base, uart_idle_condition_t condition) +{ + base->UCR1 = (base->UCR1 & ~UART_UCR1_ICD_MASK) | UART_UCR1_ICD(condition); +} + +/*! + * @brief This function is used to Disable the UART Module. + * + * @param base UART base pointer. + */ +static inline void UART_Disable(UART_Type *base) +{ + base->UCR1 &= ~UART_UCR1_UARTEN_MASK; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief This function is used to get the current status of specific + * UART status flag(including interrupt flag). The available + * status flag can be select from uart_status_flag_t enumeration. + * + * @param base UART base pointer. + * @param flag Status flag to check. + * @retval current state of corresponding status flag. + */ +bool UART_GetStatusFlag(UART_Type *base, uint32_t flag); + +/*! + * @brief This function is used to clear the current status + * of specific UART status flag. The available status + * flag can be select from uart_status_flag_t enumeration. + * + * @param base UART base pointer. + * @param flag Status flag to clear. + */ +void UART_ClearStatusFlag(UART_Type *base, uint32_t flag); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables UART interrupts according to the provided mask. + * + * This function enables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to enable TX empty interrupt and RX data ready interrupt, do the following. + * @code + * UART_EnableInterrupts(UART1,kUART_TxEmptyEnable | kUART_RxDataReadyEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_EnableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Disables the UART interrupts according to the provided mask. + * + * This function disables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to disable TX empty interrupt and RX data ready interrupt do the following. + * @code + * UART_EnableInterrupts(UART1,kUART_TxEmptyEnable | kUART_RxDataReadyEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_DisableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled UART interrupts. + * + * This function gets the enabled UART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _uart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1); + * + * if (kUART_TxEmptyEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base UART peripheral base address. + * @return UART interrupt flags which are logical OR of the enumerators in @ref _uart_interrupt_enable. + */ +uint32_t UART_GetEnabledInterrupts(UART_Type *base); + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the UART transmitter. + * + * This function enables or disables the UART transmitter. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTx(UART_Type *base, bool enable) +{ + if (enable) + { + base->UCR2 |= UART_UCR2_TXEN_MASK; + } + else + { + base->UCR2 &= ~UART_UCR2_TXEN_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver. + * + * This function enables or disables the UART receiver. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRx(UART_Type *base, bool enable) +{ + if (enable) + { + base->UCR2 |= UART_UCR2_RXEN_MASK; + } + else + { + base->UCR2 &= ~UART_UCR2_RXEN_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function is used to write data to transmitter register. + * The upper layer must ensure that the TX register is empty or that + * the TX FIFO has room before calling this function. + * + * @param base UART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void UART_WriteByte(UART_Type *base, uint8_t data) +{ + base->UTXD = (uint32_t)data & UART_UTXD_TX_DATA_MASK; +} + +/*! + * @brief Reads the receiver register. + * + * This function is used to read data from receiver register. + * The upper layer must ensure that the receiver register is full or that + * the RX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t UART_ReadByte(UART_Type *base) +{ + return (uint8_t)((base->URXD & UART_URXD_RX_DATA_MASK) >> UART_URXD_RX_DATA_SHIFT); +} + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @param base UART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_UART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data, and reads data from the TX register. + * + * @param base UART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data. + * @retval kStatus_UART_NoiseError A noise error occurred while receiving data. + * @retval kStatus_UART_FramingError A framing error occurred while receiving data. + * @retval kStatus_UART_ParityError A parity error occurred while receiving data. + * @retval kStatus_UART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle. + * + * This function initializes the UART handle which can be used for other UART + * transactional APIs. Usually, for a specified UART instance, + * call this API once to get the initialized handle. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize Size of the ring buffer. + */ +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle UART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_UART_TxIdle as status parameter. + * + * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX, + * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure. See #uart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_UART_TxBusy Previous transmission still not finished; data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument The parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the UART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure, see #uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_UART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief UART IRQ handle function. + * + * This function handles the UART transmit and receive IRQ request. + * + * @param base UART peripheral base address. + * @param irqHandle UART handle pointer. + */ +void UART_TransferHandleIRQ(UART_Type *base, void *irqHandle); + +/*@}*/ + +/*! + * @name DMA control functions. + * @{ + */ + +/*! + * @brief Enables or disables the UART transmitter DMA request. + * + * This function enables or disables the transmit request when the transmitter + * has one or more slots available in the TxFIFO. The fill level in the TxFIFO + * that generates the DMA request is controlled by the TXTL bits. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTxDMA(UART_Type *base, bool enable) +{ + assert(base != NULL); + + if (enable) + { + base->UCR1 |= UART_UCR1_TXDMAEN_MASK; + } + else + { + base->UCR1 &= ~UART_UCR1_TXDMAEN_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver DMA request. + * + * This function enables or disables the receive request when the receiver + * has data in the RxFIFO. The fill level in the RxFIFO at which a DMA request + * is generated is controlled by the RXTL bits . + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRxDMA(UART_Type *base, bool enable) +{ + assert(base != NULL); + + if (enable) + { + base->UCR1 |= UART_UCR1_RXDMAEN_MASK; + } + else + { + base->UCR1 &= ~UART_UCR1_RXDMAEN_MASK; + } +} + +/*@}*/ + +/*! + * @name FIFO control functions. + * @{ + */ + +/*! + * @brief This function is used to set the watermark of UART Tx FIFO. + * A maskable interrupt is generated whenever the data level in + * the TxFIFO falls below the Tx FIFO watermark. + * + * @param base UART base pointer. + * @param watermark The Tx FIFO watermark. + */ +static inline void UART_SetTxFifoWatermark(UART_Type *base, uint8_t watermark) +{ + assert((watermark >= 2U) && ((int32_t)watermark <= (int32_t)FSL_FEATURE_IUART_FIFO_SIZEn(base))); + base->UFCR = (base->UFCR & ~UART_UFCR_TXTL_MASK) | UART_UFCR_TXTL(watermark); +} + +/*! + * @brief This function is used to set the watermark of UART RTS deassertion. + * + * The RTS signal deasserts whenever the data count in RxFIFO reaches the Rx + * RTS watermark. + * + * @param base UART base pointer. + * @param watermark The Rx RTS watermark. + */ +static inline void UART_SetRxRTSWatermark(UART_Type *base, uint8_t watermark) +{ + assert((int32_t)watermark <= (int32_t)FSL_FEATURE_IUART_FIFO_SIZEn(base)); + base->UCR4 = (base->UCR4 & ~UART_UCR4_CTSTL_MASK) | UART_UCR4_CTSTL(watermark); +} + +/*! + * @brief This function is used to set the watermark of UART Rx FIFO. + * A maskable interrupt is generated whenever the data level in + * the RxFIFO reaches the Rx FIFO watermark. + * + * @param base UART base pointer. + * @param watermark The Rx FIFO watermark. + */ +static inline void UART_SetRxFifoWatermark(UART_Type *base, uint8_t watermark) +{ + assert((int32_t)watermark <= (int32_t)FSL_FEATURE_IUART_FIFO_SIZEn(base)); + base->UFCR = (base->UFCR & ~UART_UFCR_RXTL_MASK) | UART_UFCR_RXTL(watermark); +} + +/*@}*/ + +/*! + * @name Auto baud rate detection. + * @{ + */ + +/*! + * @brief This function is used to set the enable condition of + * Automatic Baud Rate Detection feature. + * + * @param base UART base pointer. + * @param enable Enable/Disable Automatic Baud Rate Detection feature. + * - true: Enable Automatic Baud Rate Detection feature. + * - false: Disable Automatic Baud Rate Detection feature. + */ +static inline void UART_EnableAutoBaudRate(UART_Type *base, bool enable) +{ + if (enable) + { + /* When ADET=0 and ADBR=1, automatic baud rate detection starts */ + /* Enable automatic baud rate detection */ + base->UCR1 |= UART_UCR1_ADBR_MASK; + /* Clear ADET brfore start automatic baud rate detection*/ + base->USR2 |= UART_USR2_ADET_MASK; + } + else + { + /* Disable automatic baud rate detection */ + base->UCR1 &= ~UART_UCR1_ADBR_MASK; + } +} +/*! + * @brief This function is used to read if the automatic baud rate detection + * has finished. + * + * @param base UART base pointer. + * @return - true: Automatic baud rate detection has finished. + * - false: Automatic baud rate detection has not finished. + */ +static inline bool UART_IsAutoBaudRateComplete(UART_Type *base) +{ + if ((UART_USR2_ACST_MASK & base->USR2) != 0U) + { + base->USR2 |= UART_USR2_ACST_MASK; + return true; + } + else + { + return false; + } +} + +#ifdef __cplusplus +} +#endif + +/*@}*/ +/*! @}*/ + +#endif /* _FSL_UART_H_ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_uart_freertos.c b/devices/MIMX8MQ6/drivers/fsl_uart_freertos.c new file mode 100644 index 000000000..861b71cdc --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_uart_freertos.c @@ -0,0 +1,382 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_uart_freertos.h" +#include +#include +#include + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iuart_freertos" +#endif + +static void UART_RTOS_Callback(UART_Type *base, uart_handle_t *state, status_t status, void *param) +{ + uart_rtos_handle_t *handle = (uart_rtos_handle_t *)param; + BaseType_t xHigherPriorityTaskWoken, xResult; + + xHigherPriorityTaskWoken = pdFALSE; + xResult = pdFAIL; + + if (status == kStatus_UART_RxIdle) + { + xResult = xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_UART_COMPLETE, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_UART_TxIdle) + { + xResult = xEventGroupSetBitsFromISR(handle->txEvent, RTOS_UART_COMPLETE, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_UART_RxRingBufferOverrun) + { + xResult = xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_UART_RING_BUFFER_OVERRUN, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_UART_RxHardwareOverrun) + { + /* Clear Overrun flag (OR) in UART S1 register */ + UART_ClearStatusFlag(base, kUART_RxOverrunFlag); + xResult = + xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_UART_HARDWARE_BUFFER_OVERRUN, &xHigherPriorityTaskWoken); + } + else + { + xResult = pdFAIL; + } + + if (xResult != pdFAIL) + { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_RTOS_Init + * Description : Initializes the UART instance for application + * + *END**************************************************************************/ +/*! + * brief Initializes a UART instance for operation in RTOS. + * + * param handle The RTOS UART handle, the pointer to an allocated space for RTOS context. + * param t_handle The pointer to the allocated space to store the transactional layer internal state. + * param cfg The pointer to the parameters required to configure the UART after initialization. + * return kStatus_Success, otherwise fail. + */ +int UART_RTOS_Init(uart_rtos_handle_t *handle, uart_handle_t *t_handle, const uart_rtos_config_t *cfg) +{ + status_t status; + uart_config_t defcfg; + + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + if (NULL == t_handle) + { + return kStatus_InvalidArgument; + } + if (NULL == cfg) + { + return kStatus_InvalidArgument; + } + if (NULL == cfg->base) + { + return kStatus_InvalidArgument; + } + if (0u == cfg->srcclk) + { + return kStatus_InvalidArgument; + } + if (0u == cfg->baudrate) + { + return kStatus_InvalidArgument; + } + + handle->base = cfg->base; + handle->t_state = t_handle; +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->txSemaphore = xSemaphoreCreateMutexStatic(&handle->txSemaphoreBuffer); +#else + handle->txSemaphore = xSemaphoreCreateMutex(); +#endif + if (NULL == handle->txSemaphore) + { + return kStatus_Fail; + } +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->rxSemaphore = xSemaphoreCreateMutexStatic(&handle->rxSemaphoreBuffer); +#else + handle->rxSemaphore = xSemaphoreCreateMutex(); +#endif + if (NULL == handle->rxSemaphore) + { + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->txEvent = xEventGroupCreateStatic(&handle->txEventBuffer); +#else + handle->txEvent = xEventGroupCreate(); +#endif + if (NULL == handle->txEvent) + { + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->rxEvent = xEventGroupCreateStatic(&handle->rxEventBuffer); +#else + handle->rxEvent = xEventGroupCreate(); +#endif + if (NULL == handle->rxEvent) + { + vEventGroupDelete(handle->txEvent); + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } + UART_GetDefaultConfig(&defcfg); + + defcfg.baudRate_Bps = cfg->baudrate; + defcfg.parityMode = cfg->parity; +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + defcfg.stopBitCount = cfg->stopbits; +#endif + + status = UART_Init(handle->base, &defcfg, cfg->srcclk); + if (kStatus_Success != status) + { + vEventGroupDelete(handle->rxEvent); + vEventGroupDelete(handle->txEvent); + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } + UART_TransferCreateHandle(handle->base, handle->t_state, UART_RTOS_Callback, handle); + UART_TransferStartRingBuffer(handle->base, handle->t_state, cfg->buffer, cfg->buffer_size); + + UART_EnableTx(handle->base, true); + UART_EnableRx(handle->base, true); + + return kStatus_Success; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_RTOS_Deinit + * Description : Deinitializes the UART instance and frees resources + * + *END**************************************************************************/ +/*! + * brief Deinitializes a UART instance for operation. + * + * This function deinitializes the UART module, sets all register values to reset value, + * and frees the resources. + * + * param handle The RTOS UART handle. + */ +int UART_RTOS_Deinit(uart_rtos_handle_t *handle) +{ + UART_Deinit(handle->base); + + vEventGroupDelete(handle->txEvent); + vEventGroupDelete(handle->rxEvent); + + /* Give the semaphore. This is for functional safety */ + (void)xSemaphoreGive(handle->txSemaphore); + (void)xSemaphoreGive(handle->rxSemaphore); + + vSemaphoreDelete(handle->txSemaphore); + vSemaphoreDelete(handle->rxSemaphore); + + /* Invalidate the handle */ + handle->base = NULL; + handle->t_state = NULL; + + return kStatus_Success; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_RTOS_Send + * Description : Initializes the UART instance for application + * + *END**************************************************************************/ +/*! + * brief Sends data in the background. + * + * This function sends data. It is a synchronous API. + * If the hardware buffer is full, the task is in the blocked state. + * + * param handle The RTOS UART handle. + * param buffer The pointer to the buffer to send. + * param length The number of bytes to send. + */ +int UART_RTOS_Send(uart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length) +{ + EventBits_t ev; + int retval = kStatus_Success; + status_t status; + + if (NULL == handle->base) + { + /* Invalid handle. */ + return kStatus_Fail; + } + if (0u == length) + { + return kStatus_Success; + } + if (NULL == buffer) + { + return kStatus_InvalidArgument; + } + + if (pdFALSE == xSemaphoreTake(handle->txSemaphore, 0)) + { + /* We could not take the semaphore, exit with 0 data received */ + return kStatus_Fail; + } + + handle->txTransfer.data = (uint8_t *)buffer; + handle->txTransfer.dataSize = (uint32_t)length; + + /* Non-blocking call */ + status = UART_TransferSendNonBlocking(handle->base, handle->t_state, &handle->txTransfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->txSemaphore); + return kStatus_Fail; + } + + ev = xEventGroupWaitBits(handle->txEvent, RTOS_UART_COMPLETE, pdTRUE, pdFALSE, portMAX_DELAY); + if ((ev & RTOS_UART_COMPLETE) == 0U) + { + retval = kStatus_Fail; + } + + if (pdFALSE == xSemaphoreGive(handle->txSemaphore)) + { + /* We could not post the semaphore, exit with error */ + retval = kStatus_Fail; + } + + return retval; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_RTOS_Recv + * Description : Receives chars for the application + * + *END**************************************************************************/ +/*! + * brief Receives data. + * + * This function receives data from UART. It is a synchronous API. If data is immediately available, + * it is returned immediately and the number of bytes received. + * + * param handle The RTOS UART handle. + * param buffer The pointer to the buffer to write received data. + * param length The number of bytes to receive. + * param received The pointer to a variable of size_t where the number of received data is filled. + */ +int UART_RTOS_Receive(uart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received) +{ + EventBits_t ev; + size_t n = 0; + int retval = kStatus_Fail; + size_t local_received = 0; + status_t status; + + if (NULL == handle->base) + { + /* Invalid handle. */ + return kStatus_Fail; + } + if (0u == length) + { + if (received != NULL) + { + *received = n; + } + return kStatus_Success; + } + if (NULL == buffer) + { + return kStatus_InvalidArgument; + } + + /* New transfer can be performed only after current one is finished */ + if (pdFALSE == xSemaphoreTake(handle->rxSemaphore, portMAX_DELAY)) + { + /* We could not take the semaphore, exit with 0 data received */ + return kStatus_Fail; + } + + handle->rxTransfer.data = buffer; + handle->rxTransfer.dataSize = (uint32_t)length; + + /* Non-blocking call */ + status = UART_TransferReceiveNonBlocking(handle->base, handle->t_state, &handle->rxTransfer, &n); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->rxSemaphore); + return kStatus_Fail; + } + + ev = xEventGroupWaitBits(handle->rxEvent, + RTOS_UART_COMPLETE | RTOS_UART_RING_BUFFER_OVERRUN | RTOS_UART_HARDWARE_BUFFER_OVERRUN, + pdTRUE, pdFALSE, portMAX_DELAY); + if ((ev & RTOS_UART_HARDWARE_BUFFER_OVERRUN) != 0U) + { + /* Stop data transfer to application buffer, ring buffer is still active */ + UART_TransferAbortReceive(handle->base, handle->t_state); + /* Prevent false indication of successful transfer in next call of UART_RTOS_Receive. + RTOS_UART_COMPLETE flag could be set meanwhile overrun is handled */ + (void)xEventGroupClearBits(handle->rxEvent, RTOS_UART_COMPLETE); + retval = kStatus_UART_RxHardwareOverrun; + local_received = 0; + } + else if ((ev & RTOS_UART_RING_BUFFER_OVERRUN) != 0U) + { + /* Stop data transfer to application buffer, ring buffer is still active */ + UART_TransferAbortReceive(handle->base, handle->t_state); + /* Prevent false indication of successful transfer in next call of UART_RTOS_Receive. + RTOS_UART_COMPLETE flag could be set meanwhile overrun is handled */ + (void)xEventGroupClearBits(handle->rxEvent, RTOS_UART_COMPLETE); + retval = kStatus_UART_RxRingBufferOverrun; + local_received = 0; + } + else if ((ev & RTOS_UART_COMPLETE) != 0U) + { + retval = kStatus_Success; + local_received = length; + } + else + { + retval = kStatus_UART_Error; + local_received = 0; + } + + /* Prevent repetitive NULL check */ + if (received != NULL) + { + *received = local_received; + } + + /* Enable next transfer. Current one is finished */ + if (pdFALSE == xSemaphoreGive(handle->rxSemaphore)) + { + /* We could not post the semaphore, exit with error */ + retval = kStatus_Fail; + } + return retval; +} diff --git a/devices/MIMX8MQ6/drivers/fsl_uart_freertos.h b/devices/MIMX8MQ6/drivers/fsl_uart_freertos.h new file mode 100644 index 000000000..6e595572b --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_uart_freertos.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __FSL_UART_RTOS_H__ +#define __FSL_UART_RTOS_H__ + +#include "fsl_uart.h" +#include +#include +#include + +/*! + * @addtogroup uart_freertos_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief UART FreeRTOS driver version 2.1.1. */ +#define FSL_UART_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +/*! @brief UART configuration structure */ +typedef struct _uart_rtos_config +{ + UART_Type *base; /*!< UART base address */ + uint32_t srcclk; /*!< UART source clock in Hz*/ + uint32_t baudrate; /*!< Desired communication speed */ + uart_parity_mode_t parity; /*!< Parity setting */ + uart_stop_bit_count_t stopbits; /*!< Number of stop bits to use */ + uint8_t *buffer; /*!< Buffer for background reception */ + uint32_t buffer_size; /*!< Size of buffer for background reception */ +} uart_rtos_config_t; + +/*! + * @cond RTOS_PRIVATE + * @name UART FreeRTOS handler + * + * These are the only valid states for txEvent and rxEvent (uart_rtos_handle_t). + */ +/*@{*/ +/*! @brief Event flag - transfer complete. */ +#define RTOS_UART_COMPLETE 0x1U +/*! @brief Event flag - ring buffer overrun. */ +#define RTOS_UART_RING_BUFFER_OVERRUN 0x2U +/*! @brief Event flag - hardware buffer overrun. */ +#define RTOS_UART_HARDWARE_BUFFER_OVERRUN 0x4U +/*@}*/ + +/*! @brief UART FreeRTOS transfer structure. */ +typedef struct _uart_rtos_handle +{ + UART_Type *base; /*!< UART base address */ + uart_transfer_t txTransfer; /*!< TX transfer structure */ + uart_transfer_t rxTransfer; /*!< RX transfer structure */ + SemaphoreHandle_t rxSemaphore; /*!< RX semaphore for resource sharing */ + SemaphoreHandle_t txSemaphore; /*!< TX semaphore for resource sharing */ + EventGroupHandle_t rxEvent; /*!< RX completion event */ + EventGroupHandle_t txEvent; /*!< TX completion event */ + void *t_state; /*!< Transactional state of the underlying driver */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t txSemaphoreBuffer; /*!< Statically allocated memory for txSemaphore */ + StaticSemaphore_t rxSemaphoreBuffer; /*!< Statically allocated memory for rxSemaphore */ + StaticEventGroup_t txEventBuffer; /*!< Statically allocated memory for txEvent */ + StaticEventGroup_t rxEventBuffer; /*!< Statically allocated memory for rxEvent */ +#endif +} uart_rtos_handle_t; +/*! \endcond */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name UART RTOS Operation + * @{ + */ + +/*! + * @brief Initializes a UART instance for operation in RTOS. + * + * @param handle The RTOS UART handle, the pointer to an allocated space for RTOS context. + * @param t_handle The pointer to the allocated space to store the transactional layer internal state. + * @param cfg The pointer to the parameters required to configure the UART after initialization. + * @return 0 succeed; otherwise fail. + */ +int UART_RTOS_Init(uart_rtos_handle_t *handle, uart_handle_t *t_handle, const uart_rtos_config_t *cfg); + +/*! + * @brief Deinitializes a UART instance for operation. + * + * This function deinitializes the UART module, sets all register values to reset value, + * and frees the resources. + * + * @param handle The RTOS UART handle. + */ +int UART_RTOS_Deinit(uart_rtos_handle_t *handle); + +/*! + * @name UART transactional Operation + * @{ + */ + +/*! + * @brief Sends data in the background. + * + * This function sends data. It is a synchronous API. + * If the hardware buffer is full, the task is in the blocked state. + * + * @param handle The RTOS UART handle. + * @param buffer The pointer to the buffer to send. + * @param length The number of bytes to send. + */ +int UART_RTOS_Send(uart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length); + +/*! + * @brief Receives data. + * + * This function receives data from UART. It is a synchronous API. If data is immediately available, + * it is returned immediately and the number of bytes received. + * + * @param handle The RTOS UART handle. + * @param buffer The pointer to the buffer to write received data. + * @param length The number of bytes to receive. + * @param received The pointer to a variable of size_t where the number of received data is filled. + */ +int UART_RTOS_Receive(uart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __FSL_UART_RTOS_H__ */ diff --git a/devices/MIMX8MQ6/drivers/fsl_wdog.c b/devices/MIMX8MQ6/drivers/fsl_wdog.c new file mode 100644 index 000000000..ea6c970b3 --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_wdog.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_wdog.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wdog01" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +static WDOG_Type *const s_wdogBases[] = WDOG_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of WDOG clock name. */ +static const clock_ip_name_t s_wdogClock[] = WDOG_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +static const IRQn_Type s_wdogIRQ[] = WDOG_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t WDOG_GetInstance(WDOG_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_wdogBases); instance++) + { + if (s_wdogBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_wdogBases)); + + return instance; +} + +/*! + * brief Initializes the WDOG configuration structure. + * + * This function initializes the WDOG configuration structure to default values. The default + * values are as follows. + * code + * wdogConfig->enableWdog = true; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enablePowerdown = false; + * wdogConfig->resetExtension = flase; + * wdogConfig->timeoutValue = 0xFFU; + * wdogConfig->interruptTimeValue = 0x04u; + * endcode + * + * param config Pointer to the WDOG configuration structure. + * see wdog_config_t + */ +void WDOG_GetDefaultConfig(wdog_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableWdog = true; + config->workMode.enableWait = false; + config->workMode.enableStop = false; + config->workMode.enableDebug = false; + config->enableInterrupt = false; + config->softwareResetExtension = false; + config->enablePowerDown = false; + config->timeoutValue = 0xffu; + config->interruptTimeValue = 0x04u; + config->enableTimeOutAssert = false; +} + +/*! + * brief Initializes the WDOG. + * + * This function initializes the WDOG. When called, the WDOG runs according to the configuration. + * + * This is an example. + * code + * wdog_config_t config; + * WDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0xffU; + * config->interruptTimeValue = 0x04u; + * WDOG_Init(wdog_base,&config); + * endcode + * + * param base WDOG peripheral base address + * param config The configuration of WDOG + */ +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) +{ + assert(NULL != config); + + uint16_t value = 0u; + uint32_t primaskValue = 0U; + + value = WDOG_WCR_WDE(config->enableWdog) | WDOG_WCR_WDW(config->workMode.enableWait) | + WDOG_WCR_WDZST(config->workMode.enableStop) | WDOG_WCR_WDBG(config->workMode.enableDebug) | + WDOG_WCR_SRE(config->softwareResetExtension) | WDOG_WCR_WT(config->timeoutValue) | + WDOG_WCR_WDT(config->enableTimeOutAssert) | WDOG_WCR_SRS_MASK | WDOG_WCR_WDA_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Set configuration */ + CLOCK_EnableClock(s_wdogClock[WDOG_GetInstance(base)]); +#endif + + primaskValue = DisableGlobalIRQ(); + base->WICR = WDOG_WICR_WICT(config->interruptTimeValue) | WDOG_WICR_WIE(config->enableInterrupt); + base->WMCR = WDOG_WMCR_PDE(config->enablePowerDown); + base->WCR = value; + EnableGlobalIRQ(primaskValue); + if (config->enableInterrupt) + { + (void)EnableIRQ(s_wdogIRQ[WDOG_GetInstance(base)]); + } +} + +/*! + * brief Shuts down the WDOG. + * + * This function shuts down the WDOG. + * Watchdog Enable bit is a write one once only bit. It is not + * possible to clear this bit by a software write, once the bit is set. + * This bit(WDE) can be set/reset only in debug mode(exception). + */ +void WDOG_Deinit(WDOG_Type *base) +{ + if (0U != (base->WCR & WDOG_WCR_WDBG_MASK)) + { + WDOG_Disable(base); + } +} + +/*! + * brief Gets the WDOG all reset status flags. + * + * This function gets all reset status flags. + * + * code + * uint16_t status; + * status = WDOG_GetStatusFlags (wdog_base); + * endcode + * param base WDOG peripheral base address + * return State of the status flag: asserted (true) or not-asserted (false).see _wdog_status_flags + * - true: a related status flag has been set. + * - false: a related status flag is not set. + */ +uint16_t WDOG_GetStatusFlags(WDOG_Type *base) +{ + uint16_t status_flag = 0U; + + status_flag |= (base->WCR & WDOG_WCR_WDE_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_POR_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_TOUT_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_SFTW_MASK); + status_flag |= (base->WICR & WDOG_WICR_WTIS_MASK); + + return status_flag; +} + +/*! + * brief Clears the WDOG flag. + * + * This function clears the WDOG status flag. + * + * This is an example for clearing the interrupt flag. + * code + * WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag); + * endcode + * param base WDOG peripheral base address + * param mask The status flags to clear. + * The parameter could be any combination of the following values. + * kWDOG_TimeoutFlag + */ +void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask) +{ + if (0U != (mask & (uint16_t)kWDOG_InterruptFlag)) + { + base->WICR |= WDOG_WICR_WTIS_MASK; + } +} + +/*! + * brief Refreshes the WDOG timer. + * + * This function feeds the WDOG. + * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted. + * + * param base WDOG peripheral base address + */ +void WDOG_Refresh(WDOG_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->WSR = WDOG_REFRESH_KEY & 0xFFFFU; + base->WSR = (WDOG_REFRESH_KEY >> 16U) & 0xFFFFU; + EnableGlobalIRQ(primaskValue); +} diff --git a/devices/MIMX8MQ6/drivers/fsl_wdog.h b/devices/MIMX8MQ6/drivers/fsl_wdog.h new file mode 100644 index 000000000..c49b39abe --- /dev/null +++ b/devices/MIMX8MQ6/drivers/fsl_wdog.h @@ -0,0 +1,305 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_WDOG_H_ +#define _FSL_WDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wdog + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WDOG driver version */ +#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ +/*! @name Refresh sequence */ +/*@{*/ +#define WDOG_REFRESH_KEY (0xAAAA5555U) +/*@}*/ + +/*! @brief Defines WDOG work mode. */ +typedef struct _wdog_work_mode +{ + bool enableWait; /*!< continue or suspend WDOG in wait mode */ + bool enableStop; /*!< continue or suspend WDOG in stop mode */ + bool enableDebug; /*!< continue or suspend WDOG in debug mode */ +} wdog_work_mode_t; + +/*! @brief Describes WDOG configuration structure. */ +typedef struct _wdog_config +{ + bool enableWdog; /*!< Enables or disables WDOG */ + wdog_work_mode_t workMode; /*!< Configures WDOG work mode in debug stop and wait mode */ + bool enableInterrupt; /*!< Enables or disables WDOG interrupt */ + uint16_t timeoutValue; /*!< Timeout value */ + uint16_t interruptTimeValue; /*!< Interrupt count timeout value */ + bool softwareResetExtension; /*!< software reset extension */ + bool enablePowerDown; /*!< power down enable bit */ + bool enableTimeOutAssert; /*!< Enable WDOG_B timeout assertion. */ +} wdog_config_t; + +/*! + * @brief WDOG interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the WDOG interrupt configurations. + */ +enum _wdog_interrupt_enable +{ + kWDOG_InterruptEnable = WDOG_WICR_WIE_MASK /*!< WDOG timeout generates an interrupt before reset*/ +}; + +/*! + * @brief WDOG status flags. + * + * This structure contains the WDOG status flags for use in the WDOG functions. + */ +enum _wdog_status_flags +{ + kWDOG_RunningFlag = WDOG_WCR_WDE_MASK, /*!< Running flag, set when WDOG is enabled*/ + kWDOG_PowerOnResetFlag = WDOG_WRSR_POR_MASK, /*!< Power On flag, set when reset is the result of a powerOnReset*/ + kWDOG_TimeoutResetFlag = WDOG_WRSR_TOUT_MASK, /*!< Timeout flag, set when reset is the result of a timeout*/ + kWDOG_SoftwareResetFlag = WDOG_WRSR_SFTW_MASK, /*!< Software flag, set when reset is the result of a software*/ + kWDOG_InterruptFlag = WDOG_WICR_WTIS_MASK /*!< interrupt flag,whether interrupt has occurred or not*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WDOG Initialization and De-initialization. + * @{ + */ + +/*! + * @brief Initializes the WDOG configuration structure. + * + * This function initializes the WDOG configuration structure to default values. The default + * values are as follows. + * @code + * wdogConfig->enableWdog = true; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enablePowerdown = false; + * wdogConfig->resetExtension = flase; + * wdogConfig->timeoutValue = 0xFFU; + * wdogConfig->interruptTimeValue = 0x04u; + * @endcode + * + * @param config Pointer to the WDOG configuration structure. + * @see wdog_config_t + */ +void WDOG_GetDefaultConfig(wdog_config_t *config); + +/*! + * @brief Initializes the WDOG. + * + * This function initializes the WDOG. When called, the WDOG runs according to the configuration. + * + * This is an example. + * @code + * wdog_config_t config; + * WDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0xffU; + * config->interruptTimeValue = 0x04u; + * WDOG_Init(wdog_base,&config); + * @endcode + * + * @param base WDOG peripheral base address + * @param config The configuration of WDOG + */ +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config); + +/*! + * @brief Shuts down the WDOG. + * + * This function shuts down the WDOG. + * Watchdog Enable bit is a write one once only bit. It is not + * possible to clear this bit by a software write, once the bit is set. + * This bit(WDE) can be set/reset only in debug mode(exception). + */ +void WDOG_Deinit(WDOG_Type *base); + +/*! + * @brief Enables the WDOG module. + * + * This function writes a value into the WDOG_WCR register to enable the WDOG. + * This is a write one once only bit. It is not possible to clear this bit by a software write, + * once the bit is set. only debug mode exception. + * @param base WDOG peripheral base address + */ +static inline void WDOG_Enable(WDOG_Type *base) +{ + base->WCR |= WDOG_WCR_WDE_MASK; +} + +/*! + * @brief Disables the WDOG module. + * + * This function writes a value into the WDOG_WCR register to disable the WDOG. + * This is a write one once only bit. It is not possible to clear this bit by a software write,once the bit is set. + * only debug mode exception + * @param base WDOG peripheral base address + */ +static inline void WDOG_Disable(WDOG_Type *base) +{ + base->WCR &= ~(uint16_t)WDOG_WCR_WDE_MASK; +} + +/*! + * @brief Trigger the system software reset. + * + * This function will write to the WCR[SRS] bit to trigger a software system reset. + * This bit will automatically resets to "1" after it has been asserted to "0". + * Note: Calling this API will reset the system right now, please using it with more attention. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_TriggerSystemSoftwareReset(WDOG_Type *base) +{ + base->WCR &= ~(uint16_t)WDOG_WCR_SRS_MASK; +} + +/*! + * @brief Trigger an output assertion. + * + * This function will write to the WCR[WDA] bit to trigger WDOG_B signal assertion. + * The WDOG_B signal can be routed to external pin of the chip, the output pin will turn to + * assertion along with WDOG_B signal. + * Note: The WDOG_B signal will remain assert until a power on reset occurred, so, please + * take more attention while calling it. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_TriggerSoftwareSignal(WDOG_Type *base) +{ + base->WCR &= ~(uint16_t)WDOG_WCR_WDA_MASK; +} + +/*! + * @brief Enables the WDOG interrupt. + * + *This bit is a write once only bit. Once the software does a write access to this bit, it will get + *locked and cannot be reprogrammed until the next system reset assertion + * + * @param base WDOG peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined. + * @arg kWDOG_InterruptEnable + */ +static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint16_t mask) +{ + base->WICR |= mask; +} + +/*! + * @brief Gets the WDOG all reset status flags. + * + * This function gets all reset status flags. + * + * @code + * uint16_t status; + * status = WDOG_GetStatusFlags (wdog_base); + * @endcode + * @param base WDOG peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags + * - true: a related status flag has been set. + * - false: a related status flag is not set. + */ +uint16_t WDOG_GetStatusFlags(WDOG_Type *base); + +/*! + * @brief Clears the WDOG flag. + * + * This function clears the WDOG status flag. + * + * This is an example for clearing the interrupt flag. + * @code + * WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag); + * @endcode + * @param base WDOG peripheral base address + * @param mask The status flags to clear. + * The parameter could be any combination of the following values. + * kWDOG_TimeoutFlag + */ +void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask); + +/*! + * @brief Sets the WDOG timeout value. + * + * This function sets the timeout value. + * This function writes a value into WCR registers. + * The time-out value can be written at any point of time but it is loaded to the counter at the time + * when WDOG is enabled or after the service routine has been performed. + * + * @param base WDOG peripheral base address + * @param timeoutCount WDOG timeout value; count of WDOG clock tick. + */ +static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) +{ + base->WCR = (base->WCR & (uint16_t)~WDOG_WCR_WT_MASK) | WDOG_WCR_WT(timeoutCount); +} + +/*! + * @brief Sets the WDOG interrupt count timeout value. + * + * This function sets the interrupt count timeout value. + * This function writes a value into WIC registers which are wirte-once. + * This field is write once only. Once the software does a write access to this field, it will get locked + * and cannot be reprogrammed until the next system reset assertion. + * @param base WDOG peripheral base address + * @param timeoutCount WDOG timeout value; count of WDOG clock tick. + */ +static inline void WDOG_SetInterrputTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) +{ + base->WICR = (base->WICR & ~(uint16_t)WDOG_WICR_WICT_MASK) | WDOG_WICR_WICT(timeoutCount); +} + +/*! + * @brief Disable the WDOG power down enable bit. + * + * This function disable the WDOG power down enable(PDE). + * This function writes a value into WMCR registers which are wirte-once. + * This field is write once only. Once software sets this bit it cannot be reset until the next system reset. + * @param base WDOG peripheral base address + */ +static inline void WDOG_DisablePowerDownEnable(WDOG_Type *base) +{ + base->WMCR &= ~(uint16_t)WDOG_WMCR_PDE_MASK; +} + +/*! + * @brief Refreshes the WDOG timer. + * + * This function feeds the WDOG. + * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WDOG peripheral base address + */ +void WDOG_Refresh(WDOG_Type *base); +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_WDOG_H_ */ diff --git a/devices/MIMX8MQ6/fsl_device_registers.h b/devices/MIMX8MQ6/fsl_device_registers.h new file mode 100644 index 000000000..4918054ea --- /dev/null +++ b/devices/MIMX8MQ6/fsl_device_registers.h @@ -0,0 +1,38 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MIMX8MQ6CVAHZ) || defined(CPU_MIMX8MQ6DVAJZ)) + +#define MIMX8MQ6_cm4_SERIES + +/* Add global project definitions */ +#if defined(CMSIS_RTE_PROJECT) +#include "RTE_Components.h" +#endif +/* CMSIS-style register definitions */ +#include "MIMX8MQ6_cm4.h" +/* CPU specific feature definitions */ +#include "MIMX8MQ6_cm4_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MIMX8MQ6/gcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld b/devices/MIMX8MQ6/gcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld new file mode 100644 index 000000000..051946627 --- /dev/null +++ b/devices/MIMX8MQ6/gcc/MIMX8MQ6xxxJZ_cm4_ddr_ram.ld @@ -0,0 +1,226 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0 + m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data); + + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/devices/MIMX8MQ6/gcc/MIMX8MQ6xxxJZ_cm4_ram.ld b/devices/MIMX8MQ6/gcc/MIMX8MQ6xxxJZ_cm4_ram.ld new file mode 100644 index 000000000..9f6d37632 --- /dev/null +++ b/devices/MIMX8MQ6/gcc/MIMX8MQ6xxxJZ_cm4_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processor: MIMX8MQ6DVAJZ +** Compiler: GNU C Compiler +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b200331 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000 +} + +/* Define output sections */ +SECTIONS +{ +/* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __CACHE_REGION_START = ORIGIN(m_interrupts); + __CACHE_REGION_SIZE = 0; + __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */ + + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data2 + + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data2 + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/devices/MIMX8MQ6/gcc/startup_MIMX8MQ6_cm4.S b/devices/MIMX8MQ6/gcc/startup_MIMX8MQ6_cm4.S new file mode 100644 index 000000000..a522d5192 --- /dev/null +++ b/devices/MIMX8MQ6/gcc/startup_MIMX8MQ6_cm4.S @@ -0,0 +1,754 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MIMX8MQ6_cm4.s */ +/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ +/* MIMX8MQ6_cm4 */ +/* @version: 4.0 */ +/* @date: 2018-1-26 */ +/* @build: b190124 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2019 NXP */ +/* All rights reserved. */ +/* */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long GPR_IRQ_IRQHandler /* GPR Interrupt. Used to notify cores on exception condition while boot.*/ + .long DAP_IRQHandler /* DAP Interrupt*/ + .long SDMA1_IRQHandler /* AND of all 48 SDMA interrupts (events) from all the channels*/ + .long GPU_IRQHandler /* GPU Interrupt*/ + .long SNVS_IRQHandler /* ON-OFF button press shorter than 5 seconds (pulse event)*/ + .long LCDIF_IRQHandler /* LCDIF Sync Interrupt*/ + .long SPDIF1_IRQHandler /* SPDIF1 Interrupt*/ + .long H264_IRQHandler /* h264 Decoder Interrupt*/ + .long VPUDMA_IRQHandler /* VPU DMA Interrupt*/ + .long QOS_IRQHandler /* QOS interrupt*/ + .long WDOG3_IRQHandler /* Watchdog Timer reset*/ + .long HS_CP1_IRQHandler /* HS Interrupt Request*/ + .long APBHDMA_IRQHandler /* GPMI operation channel 0-3 description complete interrupt*/ + .long SPDIF2_IRQHandler /* SPDIF2 Interrupt*/ + .long BCH_IRQHandler /* BCH operation complete interrupt*/ + .long GPMI_IRQHandler /* GPMI operation TIMEOUT ERROR interrupt*/ + .long HDMI_IRQ0_IRQHandler /* HDMI Interrupt 0*/ + .long HDMI_IRQ1_IRQHandler /* HDMI Interrupt 1*/ + .long HDMI_IRQ2_IRQHandler /* HDMI Interrupt 2*/ + .long SNVS_Consolidated_IRQHandler /* SRTC Consolidated Interrupt. Non TZ.*/ + .long SNVS_Security_IRQHandler /* SRTC Security Interrupt. TZ.*/ + .long CSU_IRQHandler /* CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted.*/ + .long USDHC1_IRQHandler /* uSDHC1 Enhanced SDHC Interrupt Request*/ + .long USDHC2_IRQHandler /* uSDHC2 Enhanced SDHC Interrupt Request*/ + .long DDC_IRQHandler /* DC8000 Display Controller IRQ*/ + .long DTRC_IRQHandler /* DTRC interrupt*/ + .long UART1_IRQHandler /* UART-1 ORed interrupt*/ + .long UART2_IRQHandler /* UART-2 ORed interrupt*/ + .long UART3_IRQHandler /* UART-3 ORed interrupt*/ + .long UART4_IRQHandler /* UART-4 ORed interrupt*/ + .long VP9_IRQHandler /* VP9 Decoder interrupt*/ + .long ECSPI1_IRQHandler /* ECSPI1 interrupt request line to the core.*/ + .long ECSPI2_IRQHandler /* ECSPI2 interrupt request line to the core.*/ + .long ECSPI3_IRQHandler /* ECSPI3 interrupt request line to the core.*/ + .long MIPI_DSI_IRQHandler /* DSI Interrupt*/ + .long I2C1_IRQHandler /* I2C-1 Interrupt*/ + .long I2C2_IRQHandler /* I2C-2 Interrupt*/ + .long I2C3_IRQHandler /* I2C-3 Interrupt*/ + .long I2C4_IRQHandler /* I2C-4 Interrupt*/ + .long RDC_IRQHandler /* RDC interrupt*/ + .long USB1_IRQHandler /* USB1 Interrupt*/ + .long USB2_IRQHandler /* USB1 Interrupt*/ + .long CSI1_IRQHandler /* CSI1 interrupt*/ + .long CSI2_IRQHandler /* CSI2 interrupt*/ + .long MIPI_CSI1_IRQHandler /* MIPI-CSI-1 Interrupt*/ + .long MIPI_CSI2_IRQHandler /* MIPI-CSI-2 Interrupt*/ + .long GPT6_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ + .long SCTR_IRQ0_IRQHandler /* ISO7816IP Interrupt 0*/ + .long SCTR_IRQ1_IRQHandler /* ISO7816IP Interrupt 1*/ + .long TEMPMON_IRQHandler /* TempSensor (Temperature alarm).*/ + .long I2S3_IRQHandler /* SAI3 Receive / Transmit Interrupt*/ + .long GPT5_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ + .long GPT4_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ + .long GPT3_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ + .long GPT2_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ + .long GPT1_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ + .long GPIO1_INT7_IRQHandler /* Active HIGH Interrupt from INT7 from GPIO*/ + .long GPIO1_INT6_IRQHandler /* Active HIGH Interrupt from INT6 from GPIO*/ + .long GPIO1_INT5_IRQHandler /* Active HIGH Interrupt from INT5 from GPIO*/ + .long GPIO1_INT4_IRQHandler /* Active HIGH Interrupt from INT4 from GPIO*/ + .long GPIO1_INT3_IRQHandler /* Active HIGH Interrupt from INT3 from GPIO*/ + .long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/ + .long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/ + .long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/ + .long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/ + .long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/ + .long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/ + .long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/ + .long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/ + .long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/ + .long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/ + .long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/ + .long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/ + .long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/ + .long PCIE_CTRL2_IRQ0_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ + .long PCIE_CTRL2_IRQ1_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ + .long PCIE_CTRL2_IRQ2_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ + .long PCIE_CTRL2_IRQ3_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ + .long WDOG1_IRQHandler /* Watchdog Timer reset*/ + .long WDOG2_IRQHandler /* Watchdog Timer reset*/ + .long PCIE_CTRL2_IRQHandler /* Channels [63:32] interrupts requests*/ + .long PWM1_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ + .long PWM2_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ + .long PWM3_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ + .long PWM4_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ + .long CCM_IRQ1_IRQHandler /* CCM, Interrupt Request 1*/ + .long CCM_IRQ2_IRQHandler /* CCM, Interrupt Request 2*/ + .long GPC_IRQHandler /* GPC Interrupt Request 1*/ + .long MU_A53_IRQHandler /* Interrupt to A53*/ + .long SRC_IRQHandler /* SRC interrupt request*/ + .long I2S56_IRQHandler /* SAI5/6 Receive / Transmit Interrupt*/ + .long RTIC_IRQHandler /* RTIC Interrupt*/ + .long CPU_PerformanceUnit_IRQHandler /* Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n]*/ + .long CPU_CTI_Trigger_IRQHandler /* CTI trigger outputs (internal: nCTIIRQ[n]*/ + .long SRC_Combined_IRQHandler /* Combined CPU wdog interrupts (4x) out of SRC.*/ + .long I2S1_IRQHandler /* SAI1 Receive / Transmit Interrupt*/ + .long I2S2_IRQHandler /* SAI2 Receive / Transmit Interrupt*/ + .long MU_M4_IRQHandler /* Interrupt to M4*/ + .long DDR_PerformanceMonitor_IRQHandler /* ddr Interrupt for performance monitor*/ + .long DDR_IRQHandler /* ddr Interrupt*/ + .long I2S4_IRQHandler /* SAI4 Receive / Transmit Interrupt*/ + .long CPU_Error_AXI_IRQHandler /* CPU Error indicator for AXI transaction with a write response error condition*/ + .long CPU_Error_L2RAM_IRQHandler /* CPU Error indicator for L2 RAM double-bit ECC error*/ + .long SDMA2_IRQHandler /* AND of all 48 SDMA interrupts (events) from all the channels*/ + .long Reserved120_IRQHandler /* Reserved*/ + .long CAAM_IRQ0_IRQHandler /* CAAM interrupt queue for JQ*/ + .long CAAM_IRQ1_IRQHandler /* CAAM interrupt queue for JQ*/ + .long QSPI_IRQHandler /* QSPI Interrupt*/ + .long TZASC_IRQHandler /* TZASC (PL380) interrupt*/ + .long Reserved125_IRQHandler /* Reserved*/ + .long Reserved126_IRQHandler /* Reserved*/ + .long Reserved127_IRQHandler /* Reserved*/ + .long PERFMON1_IRQHandler /* General Interrupt*/ + .long PERFMON2_IRQHandler /* General Interrupt*/ + .long CAAM_IRQ2_IRQHandler /* CAAM interrupt queue for JQ*/ + .long CAAM_ERROR_IRQHandler /* Recoverable error interrupt*/ + .long HS_CP0_IRQHandler /* HS Interrupt Request*/ + .long HEVC_IRQHandler /* HEVC interrupt*/ + .long ENET_MAC0_Rx_Tx_Done1_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/ + .long ENET_MAC0_Rx_Tx_Done2_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/ + .long ENET_IRQHandler /* MAC 0 IRQ*/ + .long ENET_1588_IRQHandler /* MAC 0 1588 Timer Interrupt - synchronous*/ + .long PCIE_CTRL1_IRQ0_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ + .long PCIE_CTRL1_IRQ1_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ + .long PCIE_CTRL1_IRQ2_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ + .long PCIE_CTRL1_IRQ3_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ + .long Reserved142_IRQHandler /* Reserved*/ + .long PCIE_CTRL1_IRQHandler /* Channels [63:32] interrupts requests*/ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * __noncachedata_start__/__noncachedata_end__ : none cachable region + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#ifdef __PERFORMANCE_IMPLEMENTATION +/* Here are two copies of loop implementations. First one favors performance + * and the second one favors code size. Default uses the second one. + * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */ + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#else /* code size implemenation */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#endif +#ifdef __STARTUP_INITIALIZE_NONCACHEDATA + ldr r2, =__noncachedata_start__ + ldr r3, =__noncachedata_init_end__ +#ifdef __PERFORMANCE_IMPLEMENTATION +/* Here are two copies of loop implementations. First one favors performance + * and the second one favors code size. Default uses the second one. + * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */ + subs r3, r2 + ble .LC3 +.LC2: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC2 +.LC3: +#else /* code size implemenation */ +.LC2: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC2 +#endif +/* zero inited ncache section initialization */ + ldr r3, =__noncachedata_end__ + movs r0,0 +.LC4: + cmp r2,r3 + itt lt + strlt r0,[r2],#4 + blt .LC4 +#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */ + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC5: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC5 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak SDMA1_IRQHandler + .type SDMA1_IRQHandler, %function +SDMA1_IRQHandler: + ldr r0,=SDMA1_DriverIRQHandler + bx r0 + .size SDMA1_IRQHandler, . - SDMA1_IRQHandler + + .align 1 + .thumb_func + .weak SPDIF1_IRQHandler + .type SPDIF1_IRQHandler, %function +SPDIF1_IRQHandler: + ldr r0,=SPDIF1_DriverIRQHandler + bx r0 + .size SPDIF1_IRQHandler, . - SPDIF1_IRQHandler + + .align 1 + .thumb_func + .weak VPUDMA_IRQHandler + .type VPUDMA_IRQHandler, %function +VPUDMA_IRQHandler: + ldr r0,=VPUDMA_DriverIRQHandler + bx r0 + .size VPUDMA_IRQHandler, . - VPUDMA_IRQHandler + + .align 1 + .thumb_func + .weak APBHDMA_IRQHandler + .type APBHDMA_IRQHandler, %function +APBHDMA_IRQHandler: + ldr r0,=APBHDMA_DriverIRQHandler + bx r0 + .size APBHDMA_IRQHandler, . - APBHDMA_IRQHandler + + .align 1 + .thumb_func + .weak SPDIF2_IRQHandler + .type SPDIF2_IRQHandler, %function +SPDIF2_IRQHandler: + ldr r0,=SPDIF2_DriverIRQHandler + bx r0 + .size SPDIF2_IRQHandler, . - SPDIF2_IRQHandler + + .align 1 + .thumb_func + .weak USDHC1_IRQHandler + .type USDHC1_IRQHandler, %function +USDHC1_IRQHandler: + ldr r0,=USDHC1_DriverIRQHandler + bx r0 + .size USDHC1_IRQHandler, . - USDHC1_IRQHandler + + .align 1 + .thumb_func + .weak USDHC2_IRQHandler + .type USDHC2_IRQHandler, %function +USDHC2_IRQHandler: + ldr r0,=USDHC2_DriverIRQHandler + bx r0 + .size USDHC2_IRQHandler, . - USDHC2_IRQHandler + + .align 1 + .thumb_func + .weak UART1_IRQHandler + .type UART1_IRQHandler, %function +UART1_IRQHandler: + ldr r0,=UART1_DriverIRQHandler + bx r0 + .size UART1_IRQHandler, . - UART1_IRQHandler + + .align 1 + .thumb_func + .weak UART2_IRQHandler + .type UART2_IRQHandler, %function +UART2_IRQHandler: + ldr r0,=UART2_DriverIRQHandler + bx r0 + .size UART2_IRQHandler, . - UART2_IRQHandler + + .align 1 + .thumb_func + .weak UART3_IRQHandler + .type UART3_IRQHandler, %function +UART3_IRQHandler: + ldr r0,=UART3_DriverIRQHandler + bx r0 + .size UART3_IRQHandler, . - UART3_IRQHandler + + .align 1 + .thumb_func + .weak UART4_IRQHandler + .type UART4_IRQHandler, %function +UART4_IRQHandler: + ldr r0,=UART4_DriverIRQHandler + bx r0 + .size UART4_IRQHandler, . - UART4_IRQHandler + + .align 1 + .thumb_func + .weak ECSPI1_IRQHandler + .type ECSPI1_IRQHandler, %function +ECSPI1_IRQHandler: + ldr r0,=ECSPI1_DriverIRQHandler + bx r0 + .size ECSPI1_IRQHandler, . - ECSPI1_IRQHandler + + .align 1 + .thumb_func + .weak ECSPI2_IRQHandler + .type ECSPI2_IRQHandler, %function +ECSPI2_IRQHandler: + ldr r0,=ECSPI2_DriverIRQHandler + bx r0 + .size ECSPI2_IRQHandler, . - ECSPI2_IRQHandler + + .align 1 + .thumb_func + .weak ECSPI3_IRQHandler + .type ECSPI3_IRQHandler, %function +ECSPI3_IRQHandler: + ldr r0,=ECSPI3_DriverIRQHandler + bx r0 + .size ECSPI3_IRQHandler, . - ECSPI3_IRQHandler + + .align 1 + .thumb_func + .weak I2C1_IRQHandler + .type I2C1_IRQHandler, %function +I2C1_IRQHandler: + ldr r0,=I2C1_DriverIRQHandler + bx r0 + .size I2C1_IRQHandler, . - I2C1_IRQHandler + + .align 1 + .thumb_func + .weak I2C2_IRQHandler + .type I2C2_IRQHandler, %function +I2C2_IRQHandler: + ldr r0,=I2C2_DriverIRQHandler + bx r0 + .size I2C2_IRQHandler, . - I2C2_IRQHandler + + .align 1 + .thumb_func + .weak I2C3_IRQHandler + .type I2C3_IRQHandler, %function +I2C3_IRQHandler: + ldr r0,=I2C3_DriverIRQHandler + bx r0 + .size I2C3_IRQHandler, . - I2C3_IRQHandler + + .align 1 + .thumb_func + .weak I2C4_IRQHandler + .type I2C4_IRQHandler, %function +I2C4_IRQHandler: + ldr r0,=I2C4_DriverIRQHandler + bx r0 + .size I2C4_IRQHandler, . - I2C4_IRQHandler + + .align 1 + .thumb_func + .weak I2S3_IRQHandler + .type I2S3_IRQHandler, %function +I2S3_IRQHandler: + ldr r0,=I2S3_DriverIRQHandler + bx r0 + .size I2S3_IRQHandler, . - I2S3_IRQHandler + + .align 1 + .thumb_func + .weak I2S56_IRQHandler + .type I2S56_IRQHandler, %function +I2S56_IRQHandler: + ldr r0,=I2S56_DriverIRQHandler + bx r0 + .size I2S56_IRQHandler, . - I2S56_IRQHandler + + .align 1 + .thumb_func + .weak I2S1_IRQHandler + .type I2S1_IRQHandler, %function +I2S1_IRQHandler: + ldr r0,=I2S1_DriverIRQHandler + bx r0 + .size I2S1_IRQHandler, . - I2S1_IRQHandler + + .align 1 + .thumb_func + .weak I2S2_IRQHandler + .type I2S2_IRQHandler, %function +I2S2_IRQHandler: + ldr r0,=I2S2_DriverIRQHandler + bx r0 + .size I2S2_IRQHandler, . - I2S2_IRQHandler + + .align 1 + .thumb_func + .weak I2S4_IRQHandler + .type I2S4_IRQHandler, %function +I2S4_IRQHandler: + ldr r0,=I2S4_DriverIRQHandler + bx r0 + .size I2S4_IRQHandler, . - I2S4_IRQHandler + + .align 1 + .thumb_func + .weak SDMA2_IRQHandler + .type SDMA2_IRQHandler, %function +SDMA2_IRQHandler: + ldr r0,=SDMA2_DriverIRQHandler + bx r0 + .size SDMA2_IRQHandler, . - SDMA2_IRQHandler + + .align 1 + .thumb_func + .weak QSPI_IRQHandler + .type QSPI_IRQHandler, %function +QSPI_IRQHandler: + ldr r0,=QSPI_DriverIRQHandler + bx r0 + .size QSPI_IRQHandler, . - QSPI_IRQHandler + + .align 1 + .thumb_func + .weak ENET_MAC0_Rx_Tx_Done1_IRQHandler + .type ENET_MAC0_Rx_Tx_Done1_IRQHandler, %function +ENET_MAC0_Rx_Tx_Done1_IRQHandler: + ldr r0,=ENET_MAC0_Rx_Tx_Done1_DriverIRQHandler + bx r0 + .size ENET_MAC0_Rx_Tx_Done1_IRQHandler, . - ENET_MAC0_Rx_Tx_Done1_IRQHandler + + .align 1 + .thumb_func + .weak ENET_MAC0_Rx_Tx_Done2_IRQHandler + .type ENET_MAC0_Rx_Tx_Done2_IRQHandler, %function +ENET_MAC0_Rx_Tx_Done2_IRQHandler: + ldr r0,=ENET_MAC0_Rx_Tx_Done2_DriverIRQHandler + bx r0 + .size ENET_MAC0_Rx_Tx_Done2_IRQHandler, . - ENET_MAC0_Rx_Tx_Done2_IRQHandler + + .align 1 + .thumb_func + .weak ENET_IRQHandler + .type ENET_IRQHandler, %function +ENET_IRQHandler: + ldr r0,=ENET_DriverIRQHandler + bx r0 + .size ENET_IRQHandler, . - ENET_IRQHandler + + .align 1 + .thumb_func + .weak ENET_1588_IRQHandler + .type ENET_1588_IRQHandler, %function +ENET_1588_IRQHandler: + ldr r0,=ENET_1588_DriverIRQHandler + bx r0 + .size ENET_1588_IRQHandler, . - ENET_1588_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler GPR_IRQ_IRQHandler + def_irq_handler DAP_IRQHandler + def_irq_handler SDMA1_DriverIRQHandler + def_irq_handler GPU_IRQHandler + def_irq_handler SNVS_IRQHandler + def_irq_handler LCDIF_IRQHandler + def_irq_handler SPDIF1_DriverIRQHandler + def_irq_handler H264_IRQHandler + def_irq_handler VPUDMA_DriverIRQHandler + def_irq_handler QOS_IRQHandler + def_irq_handler WDOG3_IRQHandler + def_irq_handler HS_CP1_IRQHandler + def_irq_handler APBHDMA_DriverIRQHandler + def_irq_handler SPDIF2_DriverIRQHandler + def_irq_handler BCH_IRQHandler + def_irq_handler GPMI_IRQHandler + def_irq_handler HDMI_IRQ0_IRQHandler + def_irq_handler HDMI_IRQ1_IRQHandler + def_irq_handler HDMI_IRQ2_IRQHandler + def_irq_handler SNVS_Consolidated_IRQHandler + def_irq_handler SNVS_Security_IRQHandler + def_irq_handler CSU_IRQHandler + def_irq_handler USDHC1_DriverIRQHandler + def_irq_handler USDHC2_DriverIRQHandler + def_irq_handler DDC_IRQHandler + def_irq_handler DTRC_IRQHandler + def_irq_handler UART1_DriverIRQHandler + def_irq_handler UART2_DriverIRQHandler + def_irq_handler UART3_DriverIRQHandler + def_irq_handler UART4_DriverIRQHandler + def_irq_handler VP9_IRQHandler + def_irq_handler ECSPI1_DriverIRQHandler + def_irq_handler ECSPI2_DriverIRQHandler + def_irq_handler ECSPI3_DriverIRQHandler + def_irq_handler MIPI_DSI_IRQHandler + def_irq_handler I2C1_DriverIRQHandler + def_irq_handler I2C2_DriverIRQHandler + def_irq_handler I2C3_DriverIRQHandler + def_irq_handler I2C4_DriverIRQHandler + def_irq_handler RDC_IRQHandler + def_irq_handler USB1_IRQHandler + def_irq_handler USB2_IRQHandler + def_irq_handler CSI1_IRQHandler + def_irq_handler CSI2_IRQHandler + def_irq_handler MIPI_CSI1_IRQHandler + def_irq_handler MIPI_CSI2_IRQHandler + def_irq_handler GPT6_IRQHandler + def_irq_handler SCTR_IRQ0_IRQHandler + def_irq_handler SCTR_IRQ1_IRQHandler + def_irq_handler TEMPMON_IRQHandler + def_irq_handler I2S3_DriverIRQHandler + def_irq_handler GPT5_IRQHandler + def_irq_handler GPT4_IRQHandler + def_irq_handler GPT3_IRQHandler + def_irq_handler GPT2_IRQHandler + def_irq_handler GPT1_IRQHandler + def_irq_handler GPIO1_INT7_IRQHandler + def_irq_handler GPIO1_INT6_IRQHandler + def_irq_handler GPIO1_INT5_IRQHandler + def_irq_handler GPIO1_INT4_IRQHandler + def_irq_handler GPIO1_INT3_IRQHandler + def_irq_handler GPIO1_INT2_IRQHandler + def_irq_handler GPIO1_INT1_IRQHandler + def_irq_handler GPIO1_INT0_IRQHandler + def_irq_handler GPIO1_Combined_0_15_IRQHandler + def_irq_handler GPIO1_Combined_16_31_IRQHandler + def_irq_handler GPIO2_Combined_0_15_IRQHandler + def_irq_handler GPIO2_Combined_16_31_IRQHandler + def_irq_handler GPIO3_Combined_0_15_IRQHandler + def_irq_handler GPIO3_Combined_16_31_IRQHandler + def_irq_handler GPIO4_Combined_0_15_IRQHandler + def_irq_handler GPIO4_Combined_16_31_IRQHandler + def_irq_handler GPIO5_Combined_0_15_IRQHandler + def_irq_handler GPIO5_Combined_16_31_IRQHandler + def_irq_handler PCIE_CTRL2_IRQ0_IRQHandler + def_irq_handler PCIE_CTRL2_IRQ1_IRQHandler + def_irq_handler PCIE_CTRL2_IRQ2_IRQHandler + def_irq_handler PCIE_CTRL2_IRQ3_IRQHandler + def_irq_handler WDOG1_IRQHandler + def_irq_handler WDOG2_IRQHandler + def_irq_handler PCIE_CTRL2_IRQHandler + def_irq_handler PWM1_IRQHandler + def_irq_handler PWM2_IRQHandler + def_irq_handler PWM3_IRQHandler + def_irq_handler PWM4_IRQHandler + def_irq_handler CCM_IRQ1_IRQHandler + def_irq_handler CCM_IRQ2_IRQHandler + def_irq_handler GPC_IRQHandler + def_irq_handler MU_A53_IRQHandler + def_irq_handler SRC_IRQHandler + def_irq_handler I2S56_DriverIRQHandler + def_irq_handler RTIC_IRQHandler + def_irq_handler CPU_PerformanceUnit_IRQHandler + def_irq_handler CPU_CTI_Trigger_IRQHandler + def_irq_handler SRC_Combined_IRQHandler + def_irq_handler I2S1_DriverIRQHandler + def_irq_handler I2S2_DriverIRQHandler + def_irq_handler MU_M4_IRQHandler + def_irq_handler DDR_PerformanceMonitor_IRQHandler + def_irq_handler DDR_IRQHandler + def_irq_handler I2S4_DriverIRQHandler + def_irq_handler CPU_Error_AXI_IRQHandler + def_irq_handler CPU_Error_L2RAM_IRQHandler + def_irq_handler SDMA2_DriverIRQHandler + def_irq_handler Reserved120_IRQHandler + def_irq_handler CAAM_IRQ0_IRQHandler + def_irq_handler CAAM_IRQ1_IRQHandler + def_irq_handler QSPI_DriverIRQHandler + def_irq_handler TZASC_IRQHandler + def_irq_handler Reserved125_IRQHandler + def_irq_handler Reserved126_IRQHandler + def_irq_handler Reserved127_IRQHandler + def_irq_handler PERFMON1_IRQHandler + def_irq_handler PERFMON2_IRQHandler + def_irq_handler CAAM_IRQ2_IRQHandler + def_irq_handler CAAM_ERROR_IRQHandler + def_irq_handler HS_CP0_IRQHandler + def_irq_handler HEVC_IRQHandler + def_irq_handler ENET_MAC0_Rx_Tx_Done1_DriverIRQHandler + def_irq_handler ENET_MAC0_Rx_Tx_Done2_DriverIRQHandler + def_irq_handler ENET_DriverIRQHandler + def_irq_handler ENET_1588_DriverIRQHandler + def_irq_handler PCIE_CTRL1_IRQ0_IRQHandler + def_irq_handler PCIE_CTRL1_IRQ1_IRQHandler + def_irq_handler PCIE_CTRL1_IRQ2_IRQHandler + def_irq_handler PCIE_CTRL1_IRQ3_IRQHandler + def_irq_handler Reserved142_IRQHandler + def_irq_handler PCIE_CTRL1_IRQHandler + + .end diff --git a/devices/MIMX8MQ6/project_template/board.c b/devices/MIMX8MQ6/project_template/board.c new file mode 100644 index 000000000..cfe975c19 --- /dev/null +++ b/devices/MIMX8MQ6/project_template/board.c @@ -0,0 +1,179 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_rdc.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_clock.h" +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + CLOCK_EnableClock(kCLOCK_Uart2); + DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, DEBUG_CONSOLE_DEVICE_TYPE_IUART, + uartClkSrcFreq); +} +/* Initialize MPU, configure non-cacheable memory */ +void BOARD_InitMemory(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Load$$LR$$LR_cache_region$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base; + uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart); +#else + extern uint32_t __CACHE_REGION_START[]; + extern uint32_t __CACHE_REGION_SIZE[]; + uint32_t cacheStart = (uint32_t)__CACHE_REGION_START; + uint32_t size = (uint32_t)__CACHE_REGION_SIZE; +#endif + uint32_t i = 0; + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* + * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but + * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need + * change the default memory attributes. + * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set + * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ + * 0x27FFFFFF) to use the + * background memory attributes. + */ + + /* Select Region 0 and set its base address to the M4 code bus start address. */ + MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos); + + /* Region 0 setting: + * 1) Disable Instruction Access; + * 2) AP = 011b, full access; + * 3) Non-shared device; + * 4) Region Not Shared; + * 5) Sub-Region 0,1 Disabled; + * 6) MPU Protection Region size = 512M byte; + * 7) Enable Region 0. + */ + MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | + (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* + * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 + * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in + * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of + * region size, + * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable). + * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR. + * The cacheable area base address should be multiples of its size in linker file, they can be modified per your + * needs. + */ + + /* Select Region 1 and set its base address to the DDR start address. */ + MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos); + + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 1. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + /* Select Region 2 and set its base address to the DDR start address. */ + MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos); + + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Shared Device; + * 4) MPU Protection Region size = 1024M byte; + * 5) Enable Region 2. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + + while ((size >> i) > 0x1U) + { + i++; + } + + /* If run on DDR, configure text and data section to be cacheable */ + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert((size & (size - 1)) == 0); + assert(!(cacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Select Region 3 and set its base address to the cache able region start address. */ + MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos); + + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) AP = 011b, full access; + * 3) Outer and inner Cacheable, write and read allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enabled; + * 6) MPU Protection Region size get from linker file; + * 7) Enable Region 3. + */ + MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | + (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; + } + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); +} + +void BOARD_RdcInit(void) +{ + /* Move M4 core to specific RDC domain 1 */ + rdc_domain_assignment_t assignment = {0}; + + assignment.domainId = BOARD_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment); + /* + * The M4 core is running at domain 1, enable clock gate for Iomux and Gpio to run at domain 1. + */ + CLOCK_EnableClock(kCLOCK_Gpio1); + CLOCK_EnableClock(kCLOCK_Gpio2); + CLOCK_EnableClock(kCLOCK_Gpio3); + CLOCK_EnableClock(kCLOCK_Gpio4); + CLOCK_EnableClock(kCLOCK_Gpio5); + + CLOCK_EnableClock(kCLOCK_Iomux0); + CLOCK_EnableClock(kCLOCK_Iomux1); + CLOCK_EnableClock(kCLOCK_Iomux2); + CLOCK_EnableClock(kCLOCK_Iomux3); + CLOCK_EnableClock(kCLOCK_Iomux4); + /* + * The M4 core is running at domain 1, enable the PLL clock sources to domain 1. + */ + CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enabel SysPLL1 to Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable SysPLL2 to Domain 1 */ + CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable SysPLL3 to Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable AudioPLL1 to Domain 1 */ + CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable AudioPLL2 to Domain 1 */ + CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable VideoPLL1 to Domain 1 */ +} diff --git a/devices/MIMX8MQ6/project_template/board.h b/devices/MIMX8MQ6/project_template/board.h new file mode 100644 index 000000000..4a442bd06 --- /dev/null +++ b/devices/MIMX8MQ6/project_template/board.h @@ -0,0 +1,46 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +#include "clock_config.h" +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMX8MQ-EVK" +#define MANUFACTURER_NAME "NXP" +#define BOARD_DOMAIN_ID (1) +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_UART +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_BASEADDR UART2_BASE +#define BOARD_DEBUG_UART_INSTANCE 2U +#define BOARD_DEBUG_UART_CLK_FREQ \ + CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \ + (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10 +#define BOARD_UART_IRQ UART2_IRQn +#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitMemory(void); +void BOARD_RdcInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/devices/MIMX8MQ6/project_template/clock_config.c b/devices/MIMX8MQ6/project_template/clock_config.c new file mode 100644 index 000000000..ef4a40577 --- /dev/null +++ b/devices/MIMX8MQ6/project_template/clock_config.c @@ -0,0 +1,145 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* OSC 27M configuration */ +const osc_config_t g_osc27MConfig = { + .oscMode = kOSC_OscMode, .oscDiv = 1U, +}; + +/* OSC 25M configuration */ +const osc_config_t g_osc25MConfig = { + .oscMode = kOSC_OscMode, .oscDiv = 1U, +}; + +/* AUDIO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* AUDIO PLL2 configuration */ +const ccm_analog_frac_pll_config_t g_audioPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* VIDEO PLL1 configuration */ +const ccm_analog_frac_pll_config_t g_videoPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */ + .fractionDiv = 0U, + .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */ + .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */ +}; + +/* SYSTEM PLL1 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll1Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */ + .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */ + .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */ +}; + +/* SYSTEM PLL2 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll2Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/* SYSTEM PLL3 configuration */ +const ccm_analog_sscg_pll_config_t g_sysPll3Config = { + .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */ + .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */ + .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */ + .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */ + .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */ + .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* OSC configuration */ + CLOCK_InitOSC25M(&g_osc25MConfig); + CLOCK_InitOSC27M(&g_osc27MConfig); + + /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side . + * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core + * would also do configuration on the SYSTEM PLL1 to 800Mhz and SYSTEM PLL2 to 1000Mhz by U-Boot.*/ + + /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */ + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m); + CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m); + /* switch AXI M4 root to 25M first in order to configure the SYSTEM PLL2. */ + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m); + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc25m); + + CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */ + CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */ + CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */ + + CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */ + CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */ + CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */ + CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/ + + CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ + + CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U); + CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */ + + CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */ + + CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ + + /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core + * enters the low power status.*/ + // CLOCK_EnableClock(kCLOCK_Sim_m); + // CLOCK_EnableClock(kCLOCK_Sim_main); + // CLOCK_EnableClock(kCLOCK_Sim_s); + // CLOCK_EnableClock(kCLOCK_Sim_wakeup); + // CLOCK_EnableClock(kCLOCK_Debug); + // CLOCK_EnableClock(kCLOCK_Dram); + // CLOCK_EnableClock(kCLOCK_Sec_Debug); + + /* Disable unused PLL */ + CLOCK_DeinitSysPll3(); + CLOCK_DeinitVideoPll1(); + CLOCK_DeinitAudioPll1(); + CLOCK_DeinitAudioPll2(); + /* Update core clock */ + SystemCoreClockUpdate(); +} diff --git a/devices/MIMX8MQ6/project_template/clock_config.h b/devices/MIMX8MQ6/project_template/clock_config.h new file mode 100644 index 000000000..84bbbed41 --- /dev/null +++ b/devices/MIMX8MQ6/project_template/clock_config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/devices/MIMX8MQ6/project_template/peripherals.c b/devices/MIMX8MQ6/project_template/peripherals.c new file mode 100644 index 000000000..ead892540 --- /dev/null +++ b/devices/MIMX8MQ6/project_template/peripherals.c @@ -0,0 +1,23 @@ +/* + * Copyright 2019 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v1.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Included files + ******************************************************************************/ +#include "peripherals.h" + +/******************************************************************************* + * BOARD_InitBootPeripherals function + ******************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ +} diff --git a/devices/MIMX8MQ6/project_template/peripherals.h b/devices/MIMX8MQ6/project_template/peripherals.h new file mode 100644 index 000000000..92e132099 --- /dev/null +++ b/devices/MIMX8MQ6/project_template/peripherals.h @@ -0,0 +1,23 @@ +/* + * Copyright 2019 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + /******************************************************************************* + * BOARD_InitBootPeripherals function + ******************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ + +#endif /* _PERIPHERALS_H_ */ diff --git a/devices/MIMX8MQ6/project_template/pin_mux.c b/devices/MIMX8MQ6/project_template/pin_mux.c new file mode 100644 index 000000000..ce6cc5ed8 --- /dev/null +++ b/devices/MIMX8MQ6/project_template/pin_mux.c @@ -0,0 +1,57 @@ +/* + * Copyright 2018 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v5.0 +processor: MIMX8MQ6xxxJZ +mcu_data: ksdk2_0 +processor_version: 0.0.12 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: a53_0} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-A53[a53_0] */ +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/devices/MIMX8MQ6/project_template/pin_mux.h b/devices/MIMX8MQ6/project_template/pin_mux.h new file mode 100644 index 000000000..018d54f57 --- /dev/null +++ b/devices/MIMX8MQ6/project_template/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2018 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "board.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-A53[a53_0] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/devices/MIMX8MQ6/system_MIMX8MQ6_cm4.c b/devices/MIMX8MQ6/system_MIMX8MQ6_cm4.c new file mode 100644 index 000000000..6c57c4e2f --- /dev/null +++ b/devices/MIMX8MQ6/system_MIMX8MQ6_cm4.c @@ -0,0 +1,269 @@ +/* +** ################################################################### +** Processors: MIMX8MQ6CVAHZ +** MIMX8MQ6DVAJZ +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b180903 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2017-01-10) +** Initial version. +** - rev. 2.0 (2017-04-27) +** Rev.B Header EAR1 +** - rev. 3.0 (2017-07-19) +** Rev.C Header EAR2 +** - rev. 4.0 (2018-01-26) +** Rev.D Header RFP +** +** ################################################################### +*/ + +/*! + * @file MIMX8MQ6_cm4 + * @version 4.0 + * @date 2018-01-26 + * @brief Device specific configuration file for MIMX8MQ6_cm4 (implementation + * file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +/*! + * @brief CCM reg macros to extract corresponding registers bit field. + */ +#define CCM_BIT_FIELD_VAL(val, mask, shift) (((val)&mask) >> shift) + +/*! + * @brief CCM reg macros to get corresponding registers values. + */ +#define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +uint32_t GetFracPllFreq(const volatile uint32_t *base); +uint32_t GetSSCGPllFreq(const volatile uint32_t *base); + +uint32_t GetFracPllFreq(const volatile uint32_t *base) +{ + uint32_t fracCfg0 = CCM_ANALOG_REG_VAL(base, 0U); + uint32_t fracCfg1 = CCM_ANALOG_REG_VAL(base, 4U); + uint32_t refClkFreq = 0U; + uint64_t fracClk = 0U; + + uint8_t refSel = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK, + CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT); + uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK, + CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT); + uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK, + CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT); + uint32_t fracDiv = CCM_BIT_FIELD_VAL(fracCfg1, CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK, + CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT); + uint8_t intDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg1, CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK, + CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT); + + if (refSel == 0U) /* OSC 25M Clock */ + { + refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ; + } + else if ((refSel == 1U) || /* OSC 27M Clock */ + (refSel == 2U)) /* HDMI_PYH 27M Clock */ + { + refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ; + } + else + { + refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it could be set at + system_MIMX8MQx_cm4.h :88 */ + } + refClkFreq /= (uint32_t)refDiv + 1U; + fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24U); + + return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U)); +} + +uint32_t GetSSCGPllFreq(const volatile uint32_t *base) +{ + uint32_t sscgCfg0 = CCM_ANALOG_REG_VAL(base, 0U); + uint32_t sscgCfg1 = CCM_ANALOG_REG_VAL(base, 4U); + uint32_t sscgCfg2 = CCM_ANALOG_REG_VAL(base, 8U); + uint32_t refClkFreq = 0U; + uint64_t pll2InputClock = 0U; + + uint8_t pll1Bypass = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg0, CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_MASK, + CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_SHIFT); + uint8_t refSel = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg0, CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK, + CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT); + uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK, + CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_SHIFT) + + 1U; + uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK, + CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_SHIFT) + + 1U; + uint8_t divf1 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK, + CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_SHIFT) + + 1U; + uint8_t divf2 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK, + CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_SHIFT) + + 1U; + uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK, + CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT) + + 1U; + + if (refSel == 0U) /* OSC 25M Clock */ + { + refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ; + } + else if ((refSel == 1U) || /* OSC 27M Clock */ + (refSel == 2U)) /* HDMI_PYH 27M Clock */ + { + refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ; + } + else + { + refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it could be set at + system_MIMX8MQx_cm4.h :88 */ + } + + refClkFreq /= refDiv1; + + if (pll1Bypass != 0U) + { + pll2InputClock = refClkFreq; + } + else if ((sscgCfg1 & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_MASK) != 0U) + { + pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2; + } + else + { + pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2; + } + + return (uint32_t)(pll2InputClock * divf2 / outDiv); +} + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit(void) +{ +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + /* Initialize Cache */ + /* Enable Code Bus Cache */ + /* set command to invalidate all ways, and write GO bit to initiate command */ + LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; + LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; + /* Wait until the command completes */ + while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) + { + } + /* Enable cache, enable write buffer */ + LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); + + /* Enable System Bus Cache */ + /* set command to invalidate all ways, and write GO bit to initiate command */ + LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; + LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; + /* Wait until the command completes */ + while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) + { + } + /* Enable cache, enable write buffer */ + LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); + + __ISB(); + __DSB(); + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate(void) +{ + volatile uint32_t *M4_ClockRoot = (volatile uint32_t *)(&(CCM)->ROOT[1].TARGET_ROOT); + uint32_t pre = ((*M4_ClockRoot & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; + uint32_t post = ((*M4_ClockRoot & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + 1U; + + uint32_t freq = 0U; + + switch ((*M4_ClockRoot & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT) + { + case 0U: /* OSC 25M Clock */ + freq = CPU_XTAL_SOSC_CLK_25MHZ; + break; + case 1U: /* System PLL2 DIV5 */ + freq = GetSSCGPllFreq(&(CCM_ANALOG->SYS_PLL2_CFG0)) / 5U; /* Get System PLL2 DIV5 freq */ + break; + case 2U: /* System PLL2 DIV4 */ + freq = GetSSCGPllFreq(&(CCM_ANALOG->SYS_PLL2_CFG0)) / 4U; /* Get System PLL2 DIV4 freq */ + break; + case 3U: /* System PLL1 DIV3 */ + freq = GetSSCGPllFreq(&(CCM_ANALOG->SYS_PLL1_CFG0)) / 3U; /* Get System PLL1 DIV3 freq */ + break; + case 4U: /* System PLL1 */ + freq = GetSSCGPllFreq(&(CCM_ANALOG->SYS_PLL1_CFG0)); /* Get System PLL1 freq */ + break; + case 5U: /* AUDIO PLL1 */ + freq = GetFracPllFreq(&(CCM_ANALOG->AUDIO_PLL1_CFG0)); /* Get AUDIO PLL1 freq */ + break; + case 6U: /* VIDEO PLL1 */ + freq = GetFracPllFreq(&(CCM_ANALOG->VIDEO_PLL1_CFG0)); /* Get VIDEO PLL1 freq */ + break; + case 7U: /* System PLL3 */ + freq = GetSSCGPllFreq(&(CCM_ANALOG->SYS_PLL3_CFG0)); /* Get System PLL3 freq */ + break; + default: + freq = CPU_XTAL_SOSC_CLK_25MHZ; + break; + } + + SystemCoreClock = freq / pre / post; +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__((weak)) void SystemInitHook(void) +{ + /* Void implementation of the weak function. */ +} diff --git a/devices/MIMX8MQ6/system_MIMX8MQ6_cm4.h b/devices/MIMX8MQ6/system_MIMX8MQ6_cm4.h new file mode 100644 index 000000000..55372719f --- /dev/null +++ b/devices/MIMX8MQ6/system_MIMX8MQ6_cm4.h @@ -0,0 +1,119 @@ +/* +** ################################################################### +** Processors: MIMX8MQ6CVAHZ +** MIMX8MQ6DVAJZ +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 +** Version: rev. 4.0, 2018-01-26 +** Build: b180903 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2017-01-10) +** Initial version. +** - rev. 2.0 (2017-04-27) +** Rev.B Header EAR1 +** - rev. 3.0 (2017-07-19) +** Rev.C Header EAR2 +** - rev. 4.0 (2018-01-26) +** Rev.D Header RFP +** +** ################################################################### +*/ + +/*! + * @file MIMX8MQ6_cm4 + * @version 4.0 + * @date 2018-01-26 + * @brief Device specific configuration file for MIMX8MQ6_cm4 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MIMX8MQ6_cm4_H_ +#define _SYSTEM_MIMX8MQ6_cm4_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +/* i.MX8MQ Definitions */ +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif +/* Define clock source values */ +#define CLK_P_N_FREQ 0u /* The value could be changeD according to the actual usage */ +#define CPU_XTAL_SOSC_CLK_25MHZ 25000000u /* Value of the external System Oscillator Clock(SOSC) frequency in Hz */ +#define CPU_XTAL_SOSC_CLK_27MHZ 27000000u /* Value of the external System Oscillator Clock(SOSC) frequency in Hz */ +#define CPU_HDMI_PHY_CLK_27MHZ 27000000u /* Value of the HDMI PHY 27M clock frequency in Hz*/ +#define DEFAULT_SYSTEM_CLOCK 266666666u /* Default System clock value */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MIMX8MQ6_cm4_H_ */ diff --git a/devices/MIMX8MQ6/template/RTE_Device.h b/devices/MIMX8MQ6/template/RTE_Device.h new file mode 100644 index 000000000..fbbbace1d --- /dev/null +++ b/devices/MIMX8MQ6/template/RTE_Device.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _RTE_DEVICE_H +#define _RTE_DEVICE_H + +#include "pin_mux.h" + +/* UART select, UART1-UART4 */ +/* User needs to provide the implementation of UARTX_GetFreq/UARTX_InitPins/UARTX_DeinitPins for the enabled UART + * instance. */ +#define RTE_USART1 0 +#define RTE_USART1_DMA_EN 0 +#define RTE_USART2 0 +#define RTE_USART2_DMA_EN 0 +#define RTE_USART3 0 +#define RTE_USART3_DMA_EN 0 +#define RTE_USART4 0 +#define RTE_USART4_DMA_EN 0 + +/* I2C select, I2C1 - I2C4. */ +/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. + */ +#define RTE_I2C1 0 +#define RTE_I2C1_DMA_EN 0 +#define RTE_I2C2 0 +#define RTE_I2C2_DMA_EN 0 +#define RTE_I2C3 0 +#define RTE_I2C3_DMA_EN 0 +#define RTE_I2C4 0 +#define RTE_I2C4_DMA_EN 0 + +/* SPI select, ECSPI1 - ECSPI3. */ +/* User needs to provide the implementation of ECSPIX_GetFreq/ECSPIX_InitPins/ECSPIX_DeinitPins for the enabled ECSPI + * instance. */ +#define RTE_SPI0 0 +#define RTE_SPI0_DMA_EN 0 +#define RTE_SPI1 0 +#define RTE_SPI1_DMA_EN 0 +#define RTE_SPI2 0 +#define RTE_SPI2_DMA_EN 0 + +#endif /* _RTE_DEVICE_H */ diff --git a/devices/MIMX8MQ6/utilities/debug_console/fsl_debug_console.c b/devices/MIMX8MQ6/utilities/debug_console/fsl_debug_console.c new file mode 100644 index 000000000..9eb416c92 --- /dev/null +++ b/devices/MIMX8MQ6/utilities/debug_console/fsl_debug_console.c @@ -0,0 +1,1356 @@ +/* + * This is a modified version of the file printf.c, which was distributed + * by Motorola as part of the M5407C3BOOT.zip package used to initialize + * the M5407C3 evaluation board. + * + * Copyright: + * 1999-2000 MOTOROLA, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Motorola, Inc. This + * software is provided on an "AS IS" basis and without warranty. + * + * To the maximum extent permitted by applicable law, MOTOROLA + * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING + * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR + * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE + * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY + * ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING + * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS + * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY + * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Motorola assumes no responsibility for the maintenance and support + * of this software + + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#include +#endif + +#ifdef SDK_OS_FREE_RTOS +#include "FreeRTOS.h" +#include "semphr.h" +#include "task.h" +#endif + +#include "fsl_debug_console_conf.h" +#include "fsl_str.h" + +#include "fsl_common.h" +#include "fsl_component_serial_manager.h" + +#include "fsl_debug_console.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#else +/* MISRA C-2012 Rule 17.2 */ +#undef assert +#define assert(n) \ + while (!(n)) \ + { \ + ; \ + } +#endif +#endif + +#if SDK_DEBUGCONSOLE +#define DEBUG_CONSOLE_FUNCTION_PREFIX +#else +#define DEBUG_CONSOLE_FUNCTION_PREFIX static +#endif + +/*! @brief character backspace ASCII value */ +#define DEBUG_CONSOLE_BACKSPACE 127U + +/* lock definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + +static SemaphoreHandle_t s_debugConsoleReadSemaphore; +#if configSUPPORT_STATIC_ALLOCATION +static StaticSemaphore_t s_debugConsoleReadSemaphoreStatic; +#endif +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore; +#if configSUPPORT_STATIC_ALLOCATION +static StaticSemaphore_t s_debugConsoleReadWaitSemaphoreStatic; +#endif +#endif + +#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +static volatile bool s_debugConsoleReadWaitSemaphore; +#endif + +#else + +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +/*! @brief get current runing environment is ISR or not */ +#ifdef __CA7_REV +#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel() +#else +#define IS_RUNNING_IN_ISR() __get_IPSR() +#endif /* __CA7_REV */ + +/* semaphore definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + +/* mutex semaphore */ +/* clang-format off */ +#if configSUPPORT_STATIC_ALLOCATION +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex, stack) ((mutex) = xSemaphoreCreateMutexStatic(stack)) +#else +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex()) +#endif +#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex) \ + do \ + { \ + if(NULL != (mutex)) \ + { \ + vSemaphoreDelete(mutex); \ + (mutex) = NULL; \ + } \ + } while(false) + +#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + (void)xSemaphoreGive(mutex); \ + } \ +} + +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + (void)xSemaphoreTake(mutex, portMAX_DELAY); \ + } \ +} + +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + result = xSemaphoreTake(mutex, 0U); \ + } \ + else \ + { \ + result = 1U; \ + } \ +} + +/* Binary semaphore */ +#if configSUPPORT_STATIC_ALLOCATION +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary,stack) ((binary) = xSemaphoreCreateBinaryStatic(stack)) +#else +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary()) +#endif +#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) \ + do \ + { \ + if(NULL != (binary)) \ + { \ + vSemaphoreDelete((binary)); \ + (binary) = NULL; \ + } \ + } while(false) +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake((binary), portMAX_DELAY)) +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR((binary), NULL)) + +#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE) + +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) (void)(mutex) +#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex) (void)(mutex) +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) (void)(mutex) +#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) (void)(mutex) +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U) + +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) (void)(binary) +#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) (void)(binary) +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \ + { \ + while (!(binary)) \ + { \ + } \ + (binary) = false; \ + } +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) \ + do \ + { \ + (binary) = true; \ + } while(false) +#else +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) (void)(binary) +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (void)(binary) +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +/* clang-format on */ + +/* add other implementation here + *such as : + * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx) + */ + +#else + +#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE. + +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/* receive state structure */ +typedef struct _debug_console_write_ring_buffer +{ + uint32_t ringBufferSize; + volatile uint32_t ringHead; + volatile uint32_t ringTail; + uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN]; +} debug_console_write_ring_buffer_t; +#endif + +typedef struct _debug_console_state_struct +{ + serial_handle_t serialHandle; /*!< serial manager handle */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + SERIAL_MANAGER_HANDLE_DEFINE(serialHandleBuffer); + debug_console_write_ring_buffer_t writeRingBuffer; + uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN]; + SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialWriteHandleBuffer); + SERIAL_MANAGER_READ_HANDLE_DEFINE(serialReadHandleBuffer); +#else + SERIAL_MANAGER_BLOCK_HANDLE_DEFINE(serialHandleBuffer); + SERIAL_MANAGER_WRITE_BLOCK_HANDLE_DEFINE(serialWriteHandleBuffer); + SERIAL_MANAGER_READ_BLOCK_HANDLE_DEFINE(serialReadHandleBuffer); +#endif +} debug_console_state_struct_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Debug console state information. */ +#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE > 0)) +AT_NONCACHEABLE_SECTION(static debug_console_state_struct_t s_debugConsoleState); +#else +static debug_console_state_struct_t s_debugConsoleState; +#endif +serial_handle_t g_serialHandle; /*!< serial manager handle */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief This is a printf call back function which is used to relocate the log to buffer + * or print the log immediately when the local buffer is full. + * + * @param[in] buf Buffer to store log. + * @param[in] indicator Buffer index. + * @param[in] val Target character to store. + * @param[in] len length of the character + * + */ +#if SDK_DEBUGCONSOLE +static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len); +#endif + +status_t DbgConsole_ReadOneCharacter(uint8_t *ch); +int DbgConsole_SendData(uint8_t *ch, size_t size); +int DbgConsole_SendDataReliable(uint8_t *ch, size_t size); +int DbgConsole_ReadLine(uint8_t *buf, size_t size); +int DbgConsole_ReadCharacter(uint8_t *ch); + +#if ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))) +DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +static void DbgConsole_SerialManagerTxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + debug_console_state_struct_t *ioState; + uint32_t sendDataLength; + + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + ioState = (debug_console_state_struct_t *)callbackParam; + + ioState->writeRingBuffer.ringTail += message->length; + if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize) + { + ioState->writeRingBuffer.ringTail = 0U; + } + + if (kStatus_SerialManager_Success == status) + { + if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead) + { + if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail) + { + sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail; + } + else + { + sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail; + } + + (void)SerialManager_WriteNonBlocking( + ((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]), + &ioState->writeRingBuffer.ringBuffer[ioState->writeRingBuffer.ringTail], sendDataLength); + } + } + else if (kStatus_SerialManager_Canceled == status) + { + ioState->writeRingBuffer.ringTail = 0U; + ioState->writeRingBuffer.ringHead = 0U; + } + else + { + /*MISRA rule 16.4*/ + } +} + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + +static void DbgConsole_SerialManagerRxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + if (kStatus_SerialManager_Notify == status) + { + } + else if (kStatus_SerialManager_Success == status) + { + /* release s_debugConsoleReadWaitSemaphore from RX callback */ + DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore); + } + else + { + /*MISRA rule 16.4*/ + } +} +#endif + +#endif + +status_t DbgConsole_ReadOneCharacter(uint8_t *ch) +{ +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) + return (status_t)kStatus_Fail; +#else /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \ + DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/ + serial_manager_status_t status = kStatus_SerialManager_Error; + +/* recieve one char every time */ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + status = + SerialManager_ReadNonBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); +#else /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/ + status = SerialManager_ReadBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); +#endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/ + if (kStatus_SerialManager_Success != status) + { + status = (serial_manager_status_t)kStatus_Fail; + } + else + { + /* wait s_debugConsoleReadWaitSemaphore from RX callback */ + DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore); + status = (serial_manager_status_t)kStatus_Success; + } + return (status_t)status; +#endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \ + DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/ + +#else /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/ + + return (status_t)kStatus_Fail; + +#endif /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/ +} + +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION +static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index) +{ + /* Due to scanf take \n and \r as end of string,should not echo */ + if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar)) + { + /* recieve one char every time */ + if (1 != DbgConsole_SendDataReliable(ch, 1U)) + { + return (status_t)kStatus_Fail; + } + } + + if ((!isGetChar) && (index != NULL)) + { + if (DEBUG_CONSOLE_BACKSPACE == *ch) + { + if ((*index >= 2)) + { + *index -= 2; + } + else + { + *index = 0; + } + } + } + + return (status_t)kStatus_Success; +} +#endif + +int DbgConsole_SendData(uint8_t *ch, size_t size) +{ + status_t status; +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + uint32_t sendDataLength; + int txBusy = 0; +#endif + assert(NULL != ch); + assert(0U != size); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + uint32_t regPrimask = DisableGlobalIRQ(); + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + txBusy = 1; + sendDataLength = + (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - + s_debugConsoleState.writeRingBuffer.ringTail) % + s_debugConsoleState.writeRingBuffer.ringBufferSize; + } + else + { + sendDataLength = 0U; + } + sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U; + if (sendDataLength < size) + { + EnableGlobalIRQ(regPrimask); + return -1; + } + for (int i = 0; i < (int)size; i++) + { + s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i]; + if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize) + { + s_debugConsoleState.writeRingBuffer.ringHead = 0U; + } + } + + status = (status_t)kStatus_SerialManager_Success; + + if (txBusy == 0) + { + if (s_debugConsoleState.writeRingBuffer.ringHead > s_debugConsoleState.writeRingBuffer.ringTail) + { + sendDataLength = + s_debugConsoleState.writeRingBuffer.ringHead - s_debugConsoleState.writeRingBuffer.ringTail; + } + else + { + sendDataLength = + s_debugConsoleState.writeRingBuffer.ringBufferSize - s_debugConsoleState.writeRingBuffer.ringTail; + } + + status = (status_t)SerialManager_WriteNonBlocking( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), + &s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringTail], + sendDataLength); + } + EnableGlobalIRQ(regPrimask); +#else + status = (status_t)SerialManager_WriteBlocking( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); +#endif + return (((status_t)kStatus_Success == status) ? (int)size : -1); +} + +int DbgConsole_SendDataReliable(uint8_t *ch, size_t size) +{ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) +#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) + serial_manager_status_t status = kStatus_SerialManager_Error; + uint32_t sendDataLength; + uint32_t totalLength = size; + int sentLength; +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ +#else /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + serial_manager_status_t status; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + + assert(NULL != ch); + + if (0U == size) + { + return 0; + } + + if (NULL == g_serialHandle) + { + return 0; + } + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) + do + { + uint32_t regPrimask = DisableGlobalIRQ(); + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + sendDataLength = + (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - + s_debugConsoleState.writeRingBuffer.ringTail) % + s_debugConsoleState.writeRingBuffer.ringBufferSize; + } + else + { + sendDataLength = 0U; + } + sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U; + + if (sendDataLength > 0U) + { + if (sendDataLength > totalLength) + { + sendDataLength = totalLength; + } + + sentLength = DbgConsole_SendData(&ch[size - totalLength], sendDataLength); + if (sentLength > 0) + { + totalLength = totalLength - (uint32_t)sentLength; + } + } + EnableGlobalIRQ(regPrimask); + + if (totalLength != 0U) + { + status = (serial_manager_status_t)DbgConsole_Flush(); + if (kStatus_SerialManager_Success != status) + { + break; + } + } + } while (totalLength != 0U); + return ((int)size - (int)totalLength); +#else /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + return DbgConsole_SendData(ch, size); +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + +#else /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + status = + SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); + return ((kStatus_SerialManager_Success == status) ? (int)size : -1); +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +} + +int DbgConsole_ReadLine(uint8_t *buf, size_t size) +{ + int i = 0; + + assert(buf != NULL); + + if (NULL == g_serialHandle) + { + return -1; + } + + /* take mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); +#endif + + do + { + /* recieve one char every time */ + if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i])) + { + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + i = -1; + break; + } +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter(&buf[i], false, &i); +#endif + /* analysis data */ + if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i])) + { + /* End of Line. */ + if (0 == i) + { + buf[i] = (uint8_t)'\0'; + continue; + } + else + { + break; + } + } + i++; + } while (i < (int)size); + + /* get char should not add '\0'*/ + if (i == (int)size) + { + buf[i] = (uint8_t)'\0'; + } + else + { + buf[i + 1] = (uint8_t)'\0'; + } + + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + + return i; +} + +int DbgConsole_ReadCharacter(uint8_t *ch) +{ + int ret; + + assert(ch); + + if (NULL == g_serialHandle) + { + return -1; + } + + /* take mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); +#endif + /* read one character */ + if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch)) + { + ret = 1; +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter(ch, true, NULL); +#endif + } + else + { + ret = -1; + } + + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + + return ret; +} + +#if SDK_DEBUGCONSOLE +static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len) +{ + int i = 0; + + for (i = 0; i < len; i++) + { + if (((uint32_t)*indicator + 1UL) >= (uint32_t)DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN) + { + (void)DbgConsole_SendDataReliable((uint8_t *)buf, (uint32_t)(*indicator)); + *indicator = 0; + } + + buf[*indicator] = dbgVal; + (*indicator)++; + } +} +#endif + +/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/ +#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) +#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE > 0U)) +#include "board.h" +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +static const serial_port_uart_config_t uartConfig = {.instance = BOARD_DEBUG_UART_INSTANCE, + .clockRate = BOARD_DEBUG_UART_CLK_FREQ, + .baudRate = BOARD_DEBUG_UART_BAUDRATE, + .parityMode = kSerialManager_UartParityDisabled, + .stopBitCount = kSerialManager_UartOneStopBit, +#if !defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + .mode = kSerialManager_UartBlockMode, +#endif +#endif + .enableRx = 1U, + .enableTx = 1U, + .enableRxRTS = 0U, + .enableTxCTS = 0U, +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + .txFifoWatermark = 0U, + .rxFifoWatermark = 0U +#endif +}; +#endif +#endif +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq) +{ + serial_manager_config_t serialConfig; + serial_manager_status_t status = kStatus_SerialManager_Success; + +#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE == 0U)) +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + serial_port_uart_config_t uartConfig = { + .instance = instance, + .clockRate = clkSrcFreq, + .baudRate = baudRate, + .parityMode = kSerialManager_UartParityDisabled, + .stopBitCount = kSerialManager_UartOneStopBit, +#if !defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + .mode = kSerialManager_UartBlockMode, +#endif +#endif + .enableRx = 1, + .enableTx = 1, + .enableRxRTS = 0U, + .enableTxCTS = 0U, +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + .txFifoWatermark = 0U, + .rxFifoWatermark = 0U +#endif + }; +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + serial_port_usb_cdc_config_t usbCdcConfig = { + .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + serial_port_swo_config_t swoConfig = { + .clockRate = clkSrcFreq, + .baudRate = baudRate, + .port = instance, + .protocol = kSerialManager_SwoProtocolNrz, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + serial_port_virtual_config_t serialPortVirtualConfig = { + .controllerIndex = (serial_port_virtual_controller_index_t)instance, + }; +#endif + + serialConfig.type = device; +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + serialConfig.ringBuffer = &s_debugConsoleState.readRingBuffer[0]; + serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN; + serialConfig.blockType = kSerialManager_NonBlocking; +#else + serialConfig.blockType = kSerialManager_Blocking; +#endif + + if (kSerialPort_Uart == device) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE > 0U)) + serialConfig.portConfig = (void *)&uartConfig; +#else + serialConfig.portConfig = &uartConfig; +#endif +#else + status = kStatus_SerialManager_Error; +#endif + } + else if (kSerialPort_UsbCdc == device) + { +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + serialConfig.portConfig = &usbCdcConfig; +#else + status = kStatus_SerialManager_Error; +#endif + } + else if (kSerialPort_Swo == device) + { +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + serialConfig.portConfig = &swoConfig; +#else + status = kStatus_SerialManager_Error; +#endif + } + else if (kSerialPort_Virtual == device) + { +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + serialConfig.portConfig = &serialPortVirtualConfig; +#else + status = kStatus_SerialManager_Error; +#endif + } + else + { + status = kStatus_SerialManager_Error; + } + + if (kStatus_SerialManager_Error != status) + { + (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState)); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN; +#endif + + s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0]; + status = SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig); + + assert(kStatus_SerialManager_Success == status); + +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) +#if configSUPPORT_STATIC_ALLOCATION + DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore, &s_debugConsoleReadSemaphoreStatic); +#else + DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif +#endif +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) && configSUPPORT_STATIC_ALLOCATION + DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore, &s_debugConsoleReadWaitSemaphoreStatic); +#else + DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore); +#endif +#endif + + { + status = + SerialManager_OpenWriteHandle(s_debugConsoleState.serialHandle, + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); + assert(kStatus_SerialManager_Success == status); +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_InstallTxCallback( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), + DbgConsole_SerialManagerTxCallback, &s_debugConsoleState); +#endif + } + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + { + status = + SerialManager_OpenReadHandle(s_debugConsoleState.serialHandle, + ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); + assert(kStatus_SerialManager_Success == status); +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_InstallRxCallback( + ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), + DbgConsole_SerialManagerRxCallback, &s_debugConsoleState); +#endif + } +#endif + + g_serialHandle = s_debugConsoleState.serialHandle; + } + return (status_t)status; +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_EnterLowpower(void) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + if (s_debugConsoleState.serialHandle != NULL) + { + status = SerialManager_EnterLowpower(s_debugConsoleState.serialHandle); + } + return (status_t)status; +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_ExitLowpower(void) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + + if (s_debugConsoleState.serialHandle != NULL) + { + status = SerialManager_ExitLowpower(s_debugConsoleState.serialHandle); + } + return (status_t)status; +} +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Deinit(void) +{ + { + if (s_debugConsoleState.serialHandle != NULL) + { + (void)SerialManager_CloseWriteHandle( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); + } + } +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + { + if (s_debugConsoleState.serialHandle != NULL) + { + (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); + } + } +#endif + if (NULL != s_debugConsoleState.serialHandle) + { + if (kStatus_SerialManager_Success == SerialManager_Deinit(s_debugConsoleState.serialHandle)) + { + s_debugConsoleState.serialHandle = NULL; + g_serialHandle = NULL; + } + } +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore); +#endif +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + + return (status_t)kStatus_Success; +} +#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ + +#if ((SDK_DEBUGCONSOLE > 0U) || \ + ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))) +DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void) +{ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) + + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + return (status_t)kStatus_Fail; + } + +#else + + while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + if (0U == IS_RUNNING_IN_ISR()) + { + if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState()) + { + vTaskDelay(1); + } + } + else + { + return (status_t)kStatus_Fail; + } +#endif + } + +#endif + +#endif + return (status_t)kStatus_Success; +} +#endif + +#if SDK_DEBUGCONSOLE +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Printf(const char *fmt_s, ...) +{ + va_list ap; + int logLength = 0, dbgResult = 0; + char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'}; + + if (NULL != g_serialHandle) + { + va_start(ap, fmt_s); + /* format print log first */ + logLength = StrFormatPrintf(fmt_s, ap, printBuf, DbgConsole_PrintCallback); + /* print log */ + dbgResult = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength); + + va_end(ap); + } + return dbgResult; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Putchar(int ch) +{ + /* print char */ + return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U); +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Scanf(char *formatString, ...) +{ + va_list ap; + int formatResult; + char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'}; + + /* scanf log */ + (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN); + /* get va_list */ + va_start(ap, formatString); + /* format scanf log */ + formatResult = StrFormatScanf(scanfBuf, formatString, ap); + + va_end(ap); + + return formatResult; +} +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_BlockingPrintf(const char *formatString, ...) +{ + va_list ap; + status_t status; + int logLength = 0, dbgResult = 0; + char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'}; + + if (NULL == g_serialHandle) + { + return 0; + } + + va_start(ap, formatString); + /* format print log first */ + logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_CancelWriting(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); +#endif + /* print log */ + status = + (status_t)SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), + (uint8_t *)printBuf, (size_t)logLength); + dbgResult = (((status_t)kStatus_Success == status) ? (int)logLength : -1); + va_end(ap); + + return dbgResult; +} + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +status_t DbgConsole_TryGetchar(char *ch) +{ +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + uint32_t length = 0; + status_t status = (status_t)kStatus_Fail; + + assert(ch); + + if (NULL == g_serialHandle) + { + return kStatus_Fail; + } + + /* take mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); +#endif + + if (kStatus_SerialManager_Success == + SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1, + &length)) + { + if (length != 0U) + { +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL); +#endif + status = (status_t)kStatus_Success; + } + } + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + return status; +#else + return (status_t)kStatus_Fail; +#endif +} +#endif + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Getchar(void) +{ + int ret = -1; + uint8_t ch = 0U; + + /* Get char */ + if (DbgConsole_ReadCharacter(&ch) > 0) + { + ret = (int)ch; + } + + return ret; +} + +#endif /* SDK_DEBUGCONSOLE */ + +/*************Code to support toolchain's printf, scanf *******************************/ +/* These function __write and __read is used to support IAR toolchain to printf and scanf*/ +#if (defined(__ICCARM__)) +#if defined(SDK_DEBUGCONSOLE_UART) +#pragma weak __write +size_t __write(int handle, const unsigned char *buffer, size_t size); +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + size_t ret; + if (NULL == buffer) + { + /* + * This means that we should flush internal buffers. Since we don't we just return. + * (Remember, "handle" == -1 means that all handles should be flushed.) + */ + ret = 0U; + } + else if ((handle != 1) && (handle != 2)) + { + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. + */ + ret = (size_t)-1; + } + else + { + /* Send data. */ + uint8_t buff[512]; + (void)memcpy(buff, buffer, size); + (void)DbgConsole_SendDataReliable((uint8_t *)buff, size); + + ret = size; + } + return ret; +} + +#pragma weak __read +size_t __read(int handle, unsigned char *buffer, size_t size); +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + uint8_t ch = 0U; + int actualSize = 0; + + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (0 != handle) + { + actualSize = -1; + } + else + { + /* Receive data.*/ + for (; size > 0U; size--) + { + (void)DbgConsole_ReadCharacter(&ch); + if (0U == ch) + { + break; + } + + *buffer++ = ch; + actualSize++; + } + } + return (size_t)actualSize; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* support LPC Xpresso with RedLib */ +#elif (defined(__REDLIB__)) + +#if (defined(SDK_DEBUGCONSOLE_UART)) +int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + DbgConsole_SendDataReliable((uint8_t *)buffer, size); + + return 0; +} + +int __attribute__((weak)) __sys_readc(void) +{ + char tmp; + + /* Receive data. */ + DbgConsole_ReadCharacter((uint8_t *)&tmp); + + return tmp; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/ +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#if defined(SDK_DEBUGCONSOLE_UART) +#if defined(__CC_ARM) +struct __FILE +{ + int handle; + /* + * Whatever you require here. If the only file you are using is standard output using printf() for debugging, + * no file handling is required. + */ +}; +#endif + +/* FILE is typedef in stdio.h. */ +#pragma weak __stdout +#pragma weak __stdin +FILE __stdout; +FILE __stdin; + +#pragma weak fputc +int fputc(int ch, FILE *f) +{ + /* Send data. */ + return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1); +} + +#pragma weak fgetc +int fgetc(FILE *f) +{ + char ch; + + /* Receive data. */ + DbgConsole_ReadCharacter((uint8_t *)&ch); + + return ch; +} + +/* + * Terminate the program, passing a return code back to the user. + * This function may not return. + */ +void _sys_exit(int returncode) +{ + while (1) + { + } +} + +/* + * Writes a character to the output channel. This function is used + * for last-resort error message output. + */ +void _ttywrch(int ch) +{ + char ench = ch; + DbgConsole_SendDataReliable((uint8_t *)(&ench), 1); +} + +char *_sys_command_string(char *cmd, int len) +{ + return (cmd); +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/ +#elif (defined(__GNUC__)) + +#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \ + (defined(__MCUXPRESSO) && (defined(SDK_DEBUGCONSOLE_UART)))) +int __attribute__((weak)) _write(int handle, char *buffer, int size); +int __attribute__((weak)) _write(int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size); + + return size; +} + +int __attribute__((weak)) _read(int handle, char *buffer, int size); +int __attribute__((weak)) _read(int handle, char *buffer, int size) +{ + uint8_t ch = 0U; + int actualSize = 0; + + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return -1; + } + + /* Receive data. */ + for (; size > 0; size--) + { + if (DbgConsole_ReadCharacter(&ch) < 0) + { + break; + } + + *buffer++ = (char)ch; + actualSize++; + + if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r')) + { + break; + } + } + + return (actualSize > 0) ? actualSize : -1; +} +#endif + +#endif /* __ICCARM__ */ diff --git a/devices/MIMX8MQ6/utilities/debug_console/fsl_debug_console.h b/devices/MIMX8MQ6/utilities/debug_console/fsl_debug_console.h new file mode 100644 index 000000000..45daa811b --- /dev/null +++ b/devices/MIMX8MQ6/utilities/debug_console/fsl_debug_console.h @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Debug console shall provide input and output functions to scan and print formatted data. + * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier" + * - [flags] :'-', '+', '#', ' ', '0' + * - [width]: number (0,1...) + * - [.precision]: number (0,1...) + * - [length]: do not support + * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n' + * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier" + * - [*]: is supported. + * - [width]: number (0,1...) + * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t') + * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's' + */ + +#ifndef _FSL_DEBUGCONSOLE_H_ +#define _FSL_DEBUGCONSOLE_H_ + +#include "fsl_common.h" +#include "fsl_component_serial_manager.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +extern serial_handle_t g_serialHandle; /*!< serial manager handle */ + +/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */ +#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */ +#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */ +#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */ + +/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support + * to be redefined in project setting. + */ +#ifndef SDK_DEBUGCONSOLE +#define SDK_DEBUGCONSOLE DEBUGCONSOLE_REDIRECT_TO_SDK +#endif + +#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE) +#include +#endif + +/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. + * + * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf. + * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf. + * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function. + */ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */ +static inline int DbgConsole_Disabled(void) +{ + return -1; +} +#define PRINTF(...) DbgConsole_Disabled() +#define SCANF(...) DbgConsole_Disabled() +#define PUTCHAR(...) DbgConsole_Disabled() +#define GETCHAR() DbgConsole_Disabled() +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */ +#define PRINTF DbgConsole_Printf +#define SCANF DbgConsole_Scanf +#define PUTCHAR DbgConsole_Putchar +#define GETCHAR DbgConsole_Getchar +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \ + */ +#define PRINTF printf +#define SCANF scanf +#define PUTCHAR putchar +#define GETCHAR getchar +#endif /* SDK_DEBUGCONSOLE */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name Initialization*/ +/* @{ */ + +#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) +/*! + * @brief Initializes the peripheral used for debug messages. + * + * Call this function to enable debug log messages to be output via the specified peripheral + * initialized by the serial manager module. + * After this function has returned, stdout and stdin are connected to the selected peripheral. + * + * @param instance The instance of the module.If the device is kSerialPort_Uart, + * the instance is UART peripheral instance. The UART hardware peripheral + * type is determined by UART adapter. For example, if the instance is 1, + * if the lpuart_adapter.c is added to the current project, the UART periheral + * is LPUART1. + * If the uart_adapter.c is added to the current project, the UART periheral + * is UART1. + * @param baudRate The desired baud rate in bits per second. + * @param device Low level device type for the debug console, can be one of the following. + * @arg kSerialPort_Uart, + * @arg kSerialPort_UsbCdc + * @param clkSrcFreq Frequency of peripheral source clock. + * + * @return Indicates whether initialization was successful or not. + * @retval kStatus_Success Execution successfully + */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq); + +/*! + * @brief De-initializes the peripheral used for debug messages. + * + * Call this function to disable debug log messages to be output via the specified peripheral + * initialized by the serial manager module. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_Deinit(void); +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_EnterLowpower(void); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_ExitLowpower(void); + +#else +/*! + * Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_Init(uint8_t instance, + uint32_t baudRate, + serial_port_type_t device, + uint32_t clkSrcFreq) +{ + (void)instance; + (void)baudRate; + (void)device; + (void)clkSrcFreq; + return (status_t)kStatus_Fail; +} +/*! + * Use an error to replace the DbgConsole_Deinit when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_Deinit(void) +{ + return (status_t)kStatus_Fail; +} + +/*! + * Use an error to replace the DbgConsole_EnterLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_EnterLowpower(void) +{ + return (status_t)kStatus_Fail; +} + +/*! + * Use an error to replace the DbgConsole_ExitLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_ExitLowpower(void) +{ + return (status_t)kStatus_Fail; +} + +#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ + +#if SDK_DEBUGCONSOLE +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param fmt_s Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Printf(const char *fmt_s, ...); + +/*! + * @brief Writes a character to stdout. + * + * Call this function to write a character to stdout. + * + * @param ch Character to be written. + * @return Returns the character written. + */ +int DbgConsole_Putchar(int ch); + +/*! + * @brief Reads formatted data from the standard input stream. + * + * Call this function to read formatted data from the standard input stream. + * + * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, + * other tasks will not be scheduled), the function cannot be used when the + * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. + * And an error is returned when the function called in this case. The suggestion + * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. + * + * @param formatString Format control string. + * @return Returns the number of fields successfully converted and assigned. + */ +int DbgConsole_Scanf(char *formatString, ...); + +/*! + * @brief Reads a character from standard input. + * + * Call this function to read a character from standard input. + * + * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, + * other tasks will not be scheduled), the function cannot be used when the + * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. + * And an error is returned when the function called in this case. The suggestion + * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. + * + * @return Returns the character read. + */ +int DbgConsole_Getchar(void); + +/*! + * @brief Writes formatted output to the standard output stream with the blocking mode. + * + * Call this function to write a formatted output to the standard output stream with the blocking mode. + * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set + * or not. + * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set. + * + * @param formatString Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_BlockingPrintf(const char *formatString, ...); + +/*! + * @brief Debug console flush. + * + * Call this function to wait the tx buffer empty. + * If interrupt transfer is using, make sure the global IRQ is enable before call this function + * This function should be called when + * 1, before enter power down mode + * 2, log is required to print to terminal immediately + * @return Indicates whether wait idle was successful or not. + */ +status_t DbgConsole_Flush(void); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief Debug console try to get char + * This function provides a API which will not block current task, if character is + * available return it, otherwise return fail. + * @param ch the address of char to receive + * @return Indicates get char was successful or not. + */ +status_t DbgConsole_TryGetchar(char *ch); +#endif + +#endif /* SDK_DEBUGCONSOLE */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/devices/MIMX8MQ6/utilities/debug_console/fsl_debug_console_conf.h b/devices/MIMX8MQ6/utilities/debug_console/fsl_debug_console_conf.h new file mode 100644 index 000000000..fd235b1e5 --- /dev/null +++ b/devices/MIMX8MQ6/utilities/debug_console/fsl_debug_console_conf.h @@ -0,0 +1,160 @@ +/* + * Copyright 2017 - 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_DEBUG_CONSOLE_CONF_H_ +#define _FSL_DEBUG_CONSOLE_CONF_H_ + +#include "fsl_common.h" + +/****************Debug console configuration********************/ + +/*! @brief If Non-blocking mode is needed, please define it at project setting, + * otherwise blocking mode is the default transfer mode. + * Warning: If you want to use non-blocking transfer,please make sure the corresponding + * IO interrupt is enable, otherwise there is no output. + * And non-blocking is combine with buffer, no matter bare-metal or rtos. + * Below shows how to configure in your project if you want to use non-blocking mode. + * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols". + * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define". + * For ARMGCC, open CmakeLists.txt and add the following lines, + * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target. + * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target. + * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C + * Complier->Preprocessor". + * + */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically + * when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed , because the log will not be + * buffered if the buffer is full, and the print will return immediately with -1. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN +#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U) +#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */ + +/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN +#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U) +#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */ + +/*!@ brief Whether enable the reliable TX function + * If the macro is zero, the reliable TX function of the debug console is disabled. + * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full. + */ +#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE +#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U) +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + +#else +#define DEBUG_CONSOLE_TRANSFER_BLOCKING +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/*!@ brief Whether enable the RX function + * If the macro is zero, the receive function of the debug console is disabled. + */ +#ifndef DEBUG_CONSOLE_RX_ENABLE +#define DEBUG_CONSOLE_RX_ENABLE (1U) +#endif /* DEBUG_CONSOLE_RX_ENABLE */ + +/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log + * length can not bigger than this value. + * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if + * the buffer is too big and current task stack size not big enough. + */ +#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN +#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U) +#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */ + +/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log + * length can not bigger than this value. + * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN. + */ +#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN +#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U) +#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */ + +/*! @brief Debug console synchronization + * User should not change these macro for synchronization mode, but add the + * corresponding synchronization mechanism per different software environment. + * Such as, if another RTOS is used, + * add: + * \#define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3 + * in this configuration file and implement the synchronization in fsl.log.c. + */ +/*! @brief synchronization for baremetal software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0 +/*! @brief synchronization for freertos software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1 + +/*! @brief RTOS synchronization mechanism disable + * If not defined, default is enable, to avoid multitask log print mess. + * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c + * If synchronization is disabled, log maybe messed on terminal. + */ +#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#ifdef SDK_OS_FREE_RTOS +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* SDK_OS_FREE_RTOS */ +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */ + +/*! @brief echo function support + * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO + * at your project setting. + */ +#ifndef DEBUG_CONSOLE_ENABLE_ECHO +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0 +#else +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1 +#endif /* DEBUG_CONSOLE_ENABLE_ECHO */ + +/*********************************************************************/ + +/***************Debug console other configuration*********************/ +/*! @brief Definition to printf the float number. */ +#ifndef PRINTF_FLOAT_ENABLE +#define PRINTF_FLOAT_ENABLE 0U +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! @brief Definition to scanf the float number. */ +#ifndef SCANF_FLOAT_ENABLE +#define SCANF_FLOAT_ENABLE 0U +#endif /* SCANF_FLOAT_ENABLE */ + +/*! @brief Definition to support advanced format specifier for printf. */ +#ifndef PRINTF_ADVANCED_ENABLE +#define PRINTF_ADVANCED_ENABLE 0U +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Definition to support advanced format specifier for scanf. */ +#ifndef SCANF_ADVANCED_ENABLE +#define SCANF_ADVANCED_ENABLE 0U +#endif /* SCANF_ADVANCED_ENABLE */ + +/*! @brief Definition to select virtual com(USB CDC) as the debug console. */ +#ifndef BOARD_USE_VIRTUALCOM +#define BOARD_USE_VIRTUALCOM 0U +#endif +/*******************************************************************/ + +#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */ diff --git a/devices/MIMX8MQ6/utilities/debug_console_lite/fsl_assert.c b/devices/MIMX8MQ6/utilities/debug_console_lite/fsl_assert.c new file mode 100644 index 000000000..d2cbe28ef --- /dev/null +++ b/devices/MIMX8MQ6/utilities/debug_console_lite/fsl_assert.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); +#else + (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); +#endif + + for (;;) + { + __BKPT(0); + } +} +#elif (defined(__GNUC__)) +#if defined(__REDLIB__) +void __assertion_failed(char *failedExpr) +{ + (void)PRINTF("ASSERT ERROR \" %s \n", failedExpr); + for (;;) + { + __BKPT(0); + } +} +#else +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, + func); + for (;;) + { + __BKPT(0); + } +} +#endif /* defined(__REDLIB__) */ +#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */ +#endif /* NDEBUG */ diff --git a/devices/MIMX8MQ6/utilities/debug_console_lite/fsl_debug_console.c b/devices/MIMX8MQ6/utilities/debug_console_lite/fsl_debug_console.c new file mode 100644 index 000000000..790610fba --- /dev/null +++ b/devices/MIMX8MQ6/utilities/debug_console_lite/fsl_debug_console.c @@ -0,0 +1,1877 @@ +/* + * Copyright 2017-2018, 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#include +#endif +#include +#include "fsl_debug_console.h" +#include "fsl_adapter_uart.h" + +/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */ +#if defined(__CC_ARM) +#pragma diag_suppress 1256 +#endif /* __CC_ARM */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief This definition is maximum line that debugconsole can scanf each time.*/ +#define IO_MAXLINE 20U + +/*! @brief The overflow value.*/ +#ifndef HUGE_VAL +#define HUGE_VAL (99.e99) +#endif /* HUGE_VAL */ + +/*! @brief State structure storing debug console. */ +typedef struct DebugConsoleState +{ + uint8_t uartHandleBuffer[HAL_UART_HANDLE_SIZE]; + hal_uart_status_t (*putChar)(hal_uart_handle_t handle, + const uint8_t *data, + size_t length); /*!< put char function pointer */ + hal_uart_status_t (*getChar)(hal_uart_handle_t handle, + uint8_t *data, + size_t length); /*!< get char function pointer */ + serial_port_type_t type; /*!< The initialized port of the debug console. */ +} debug_console_state_t; + +/*! @brief Type of KSDK printf function pointer. */ +typedef int (*PUTCHAR_FUNC)(int a); + +#if PRINTF_ADVANCED_ENABLE +/*! @brief Specification modifier flags for printf. */ +enum _debugconsole_printf_flag +{ + kPRINTF_Minus = 0x01U, /*!< Minus FLag. */ + kPRINTF_Plus = 0x02U, /*!< Plus Flag. */ + kPRINTF_Space = 0x04U, /*!< Space Flag. */ + kPRINTF_Zero = 0x08U, /*!< Zero Flag. */ + kPRINTF_Pound = 0x10U, /*!< Pound Flag. */ + kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */ + kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */ + kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */ + kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */ +}; +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Specification modifier flags for scanf. */ +enum _debugconsole_scanf_flag +{ + kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */ + kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */ + kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */ + kSCANF_DestString = 0x8U, /*!< Destination String FLag. */ + kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */ + kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */ + kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */ + kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */ +#if SCANF_ADVANCED_ENABLE + kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */ + kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */ + kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */ + kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */ +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */ +#endif /*SCANF_FLOAT_ENABLE */ + kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Debug UART state information. */ +static debug_console_state_t s_debugConsole; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if SDK_DEBUGCONSOLE +static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap); +static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr); +#endif /* SDK_DEBUGCONSOLE */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/ + +#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq) +{ + hal_uart_config_t usrtConfig; + + if (kSerialPort_Uart != device) + { + return kStatus_Fail; + } + + /* Set debug console to initialized to avoid duplicated initialized operation. */ + s_debugConsole.type = device; + + usrtConfig.srcClock_Hz = clkSrcFreq; + usrtConfig.baudRate_Bps = baudRate; + usrtConfig.parityMode = kHAL_UartParityDisabled; + usrtConfig.stopBitCount = kHAL_UartOneStopBit; + usrtConfig.enableRx = 1U; + usrtConfig.enableTx = 1U; + usrtConfig.enableRxRTS = 0U; + usrtConfig.enableTxCTS = 0U; + usrtConfig.instance = instance; +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + usrtConfig.txFifoWatermark = 0U; + usrtConfig.rxFifoWatermark = 0U; +#endif + /* Enable clock and initial UART module follow user configure structure. */ + (void)HAL_UartInit((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], &usrtConfig); + /* Set the function pointer for send and receive for this kind of device. */ + s_debugConsole.putChar = HAL_UartSendBlocking; + s_debugConsole.getChar = HAL_UartReceiveBlocking; + + return kStatus_Success; +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Deinit(void) +{ + if (kSerialPort_None == s_debugConsole.type) + { + return kStatus_Success; + } + + (void)HAL_UartDeinit((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0]); + + s_debugConsole.type = kSerialPort_None; + + return kStatus_Success; +} +#endif /* DEBUGCONSOLE_REDIRECT_TO_SDK */ + +#if SDK_DEBUGCONSOLE +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Printf(const char *fmt_s, ...) +{ + va_list ap; + int result; + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.type) + { + return -1; + } + va_start(ap, fmt_s); + result = DbgConsole_PrintfFormattedData(DbgConsole_Putchar, fmt_s, ap); + va_end(ap); + + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Putchar(int ch) +{ + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.type) + { + return -1; + } + (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1); + + return 1; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Scanf(char *fmt_ptr, ...) +{ + /* Plus one to store end of string char */ + char temp_buf[IO_MAXLINE + 1]; + va_list ap; + int32_t i; + char result; + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.type) + { + return -1; + } + va_start(ap, fmt_ptr); + temp_buf[0] = '\0'; + + i = 0; + while (true) + { + if (i >= (int32_t)IO_MAXLINE) + { + break; + } + + result = (char)DbgConsole_Getchar(); + temp_buf[i] = result; + + if ((result == '\r') || (result == '\n')) + { + /* End of Line. */ + if (i == 0) + { + temp_buf[i] = '\0'; + i = -1; + } + else + { + break; + } + } + + i++; + } + + if (i == (int32_t)IO_MAXLINE) + { + temp_buf[i] = '\0'; + } + else + { + temp_buf[i + 1] = '\0'; + } + result = (char)DbgConsole_ScanfFormattedData(temp_buf, fmt_ptr, ap); + va_end(ap); + + return (int)result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Getchar(void) +{ + char ch; + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.type) + { + return -1; + } + while (kStatus_HAL_UartSuccess != + s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1)) + { + return -1; + } + + return (int)ch; +} + +/*************Code for process formatted data*******************************/ +/*! + * @brief Scanline function which ignores white spaces. + * + * @param[in] s The address of the string pointer to update. + * @return String without white spaces. + */ +static uint32_t DbgConsole_ScanIgnoreWhiteSpace(const char **s) +{ + uint8_t count = 0; + char c; + + c = **s; + while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f')) + { + count++; + (*s)++; + c = **s; + } + return count; +} + +/*! + * @brief This function puts padding character. + * + * @param[in] c Padding character. + * @param[in] curlen Length of current formatted string . + * @param[in] width Width of expected formatted string. + * @param[in] count Number of characters. + * @param[in] func_ptr Function to put character out. + */ +static void DbgConsole_PrintfPaddingCharacter( + char c, int32_t curlen, int32_t width, int32_t *count, PUTCHAR_FUNC func_ptr) +{ + int32_t i; + + for (i = curlen; i < width; i++) + { + (void)func_ptr(c); + (*count)++; + } +} + +/*! + * @brief Converts a radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] neg Polarity of the number. + * @param[in] radix The radix to be converted to. + * @param[in] use_caps Used to identify %x/X output format. + + * @return Length of the converted string. + */ +static int32_t DbgConsole_ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps) +{ +#if PRINTF_ADVANCED_ENABLE + int64_t a; + int64_t b; + int64_t c; + + uint64_t ua; + uint64_t ub; + uint64_t uc; +#else + int32_t a; + int32_t b; + int32_t c; + + uint32_t ua; + uint32_t ub; + uint32_t uc; +#endif /* PRINTF_ADVANCED_ENABLE */ + + int32_t nlen; + char *nstrp; + + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + +#if !(PRINTF_ADVANCED_ENABLE > 0) + neg = 0; +#endif + + if (0 != neg) + { +#if PRINTF_ADVANCED_ENABLE + a = *(int64_t *)nump; +#else + a = *(int32_t *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (a == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (a != 0) + { +#if PRINTF_ADVANCED_ENABLE + b = (int64_t)a / (int64_t)radix; + c = (int64_t)a - ((int64_t)b * (int64_t)radix); + if (c < 0) + { + c = (int64_t)'0' - c; + } +#else + b = a / radix; + c = a - (b * radix); + if (c < 0) + { + c = (int32_t)'0' - c; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + else + { +#if PRINTF_ADVANCED_ENABLE + ua = *(uint64_t *)nump; +#else + ua = *(uint32_t *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (ua == 0U) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (ua != 0U) + { +#if PRINTF_ADVANCED_ENABLE + ub = (uint64_t)ua / (uint64_t)radix; + uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix); +#else + ub = ua / (uint32_t)radix; + uc = ua - (ub * (uint32_t)radix); +#endif /* PRINTF_ADVANCED_ENABLE */ + + if (uc < 10U) + { + uc = uc + '0'; + } + else + { + uc = uc - 10U + (use_caps ? 'A' : 'a'); + } + ua = ub; + *nstrp++ = (char)uc; + ++nlen; + } + } + return nlen; +} + +#if PRINTF_FLOAT_ENABLE +/*! + * @brief Converts a floating radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] radix The radix to be converted to. + * @param[in] precision_width Specify the precision width. + + * @return Length of the converted string. + */ +static int32_t DbgConsole_ConvertFloatRadixNumToString(char *numstr, + void *nump, + int32_t radix, + uint32_t precision_width) +{ + int32_t a; + int32_t b; + int32_t c; + uint32_t i; + double fa; + double dc; + double fb; + double r; + double fractpart; + double intpart; + + int32_t nlen; + char *nstrp; + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + r = *(double *)nump; + if (0.0 == r) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + fractpart = modf((double)r, (double *)&intpart); + /* Process fractional part. */ + for (i = 0; i < precision_width; i++) + { + fractpart *= (double)radix; + } + if (r >= 0.0) + { + fa = fractpart + (double)0.5; + if (fa >= pow((double)10, (double)precision_width)) + { + intpart++; + } + } + else + { + fa = fractpart - (double)0.5; + if (fa <= -pow((double)10, (double)precision_width)) + { + intpart--; + } + } + for (i = 0; i < precision_width; i++) + { + fb = fa / (double)radix; + dc = (fa - (double)(int64_t)fb * (double)radix); + c = (int32_t)dc; + if (c < 0) + { + c = (int32_t)'0' - c; + } + else + { + c = c + '0'; + } + fa = fb; + *nstrp++ = (char)c; + ++nlen; + } + *nstrp++ = (char)'.'; + ++nlen; + a = (int32_t)intpart; + if (a == 0) + { + *nstrp++ = '0'; + ++nlen; + } + else + { + while (a != 0) + { + b = (int32_t)a / (int32_t)radix; + c = (int32_t)a - ((int32_t)b * (int32_t)radix); + if (c < 0) + { + c = (int32_t)'0' - c; + } + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + return nlen; +} +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! + * @brief This function outputs its parameters according to a formatted string. + * + * @note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * @param[in] func_ptr Function to put character out. + * @param[in] fmt_ptr Format string for printf. + * @param[in] args_ptr Arguments to printf. + * + * @return Number of characters + */ +static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap) +{ + /* va_list ap; */ + const char *p; + char c; + + char vstr[33]; + char *vstrp = NULL; + int32_t vlen = 0; + + bool done; + int32_t count = 0; + + uint32_t field_width; + uint32_t precision_width; + char *sval; + int32_t cval; + bool use_caps; + uint8_t radix = 0; + +#if PRINTF_ADVANCED_ENABLE + uint32_t flags_used; + char schar; + bool dschar; + int64_t ival; + uint64_t uval = 0; + bool valid_precision_width; +#else + int32_t ival; + uint32_t uval = 0; +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_FLOAT_ENABLE + double fval; +#endif /* PRINTF_FLOAT_ENABLE */ + + /* Start parsing apart the format string and display appropriate formats and data. */ + p = fmt; + while (true) + { + if ('\0' == *p) + { + break; + } + c = *p; + /* + * All formats begin with a '%' marker. Special chars like + * '\n' or '\t' are normally converted to the appropriate + * character by the __compiler__. Thus, no need for this + * routine to account for the '\' character. + */ + if (c != '%') + { + (void)func_ptr(c); + count++; + p++; + /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */ + continue; + } + + use_caps = true; + +#if PRINTF_ADVANCED_ENABLE + /* First check for specification modifier flags. */ + flags_used = 0; + done = false; + while (!done) + { + switch (*++p) + { + case '-': + flags_used |= (uint32_t)kPRINTF_Minus; + break; + case '+': + flags_used |= (uint32_t)kPRINTF_Plus; + break; + case ' ': + flags_used |= (uint32_t)kPRINTF_Space; + break; + case '0': + flags_used |= (uint32_t)kPRINTF_Zero; + break; + case '#': + flags_used |= (uint32_t)kPRINTF_Pound; + break; + default: + /* We've gone one char too far. */ + --p; + done = true; + break; + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + + /* Next check for minimum field width. */ + field_width = 0; + done = false; + while (!done) + { + c = *++p; + if ((c >= '0') && (c <= '9')) + { + field_width = (field_width * 10U) + ((uint32_t)c - (uint32_t)'0'); + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + field_width = (uint32_t)va_arg(ap, uint32_t); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = true; + } + } + /* Next check for the width and precision field separator. */ +#if (PRINTF_ADVANCED_ENABLE || PRINTF_FLOAT_ENABLE) + precision_width = 6U; /* MISRA C-2012 Rule 2.2 */ +#endif +#if PRINTF_ADVANCED_ENABLE + valid_precision_width = false; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (*++p == '.') + { + /* Must get precision field width, if present. */ + precision_width = 0U; + done = false; + while (!done) + { + c = *++p; + if ((c >= '0') && (c <= '9')) + { + precision_width = (precision_width * 10U) + ((uint32_t)c - (uint32_t)'0'); +#if PRINTF_ADVANCED_ENABLE + valid_precision_width = true; +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + precision_width = (uint32_t)va_arg(ap, uint32_t); + valid_precision_width = true; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = true; + } + } + } + else + { + /* We've gone one char too far. */ + --p; + } +#if PRINTF_ADVANCED_ENABLE + /* + * Check for the length modifier. + */ + switch (/* c = */ *++p) + { + case 'h': + if (*++p != 'h') + { + flags_used |= (uint32_t)kPRINTF_LengthShortInt; + --p; + } + else + { + flags_used |= (uint32_t)kPRINTF_LengthChar; + } + break; + case 'l': + if (*++p != 'l') + { + flags_used |= (uint32_t)kPRINTF_LengthLongInt; + --p; + } + else + { + flags_used |= (uint32_t)kPRINTF_LengthLongLongInt; + } + break; + default: + /* we've gone one char too far */ + --p; + break; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + /* Now we're ready to examine the format. */ + c = *++p; + { + if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') || + (c == 'b') || (c == 'p') || (c == 'u')) + { + if ((c == 'd') || (c == 'i')) + { +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt)) + { + ival = (int64_t)va_arg(ap, int64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + ival = (int32_t)va_arg(ap, int32_t); + } + vlen = DbgConsole_ConvertRadixNumToString(vstr, &ival, 1, 10, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + if (ival < 0) + { + schar = '-'; + ++vlen; + } + else + { + if (0U != (flags_used & (uint32_t)kPRINTF_Plus)) + { + schar = '+'; + ++vlen; + } + else + { + if (0U != (flags_used & (uint32_t)kPRINTF_Space)) + { + schar = ' '; + ++vlen; + } + else + { + schar = '\0'; + } + } + } + dschar = false; + /* Do the ZERO pad. */ + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if ('\0' != schar) + { + (void)func_ptr(schar); + count++; + } + dschar = true; + + DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr); + vlen = (int32_t)field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + if ('\0' != schar) + { + (void)func_ptr(schar); + count++; + } + dschar = true; + } + } + /* The string was built in reverse order, now display in correct order. */ + if ((!dschar) && ('\0' != schar)) + { + (void)func_ptr(schar); + count++; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + +#if PRINTF_FLOAT_ENABLE + if ((c == 'f') || (c == 'F')) + { + fval = (double)va_arg(ap, double); + vlen = DbgConsole_ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + if (fval < 0.0) + { + schar = '-'; + ++vlen; + } + else + { + if (0U != (flags_used & (uint32_t)kPRINTF_Plus)) + { + schar = '+'; + ++vlen; + } + else + { + if (0U != (flags_used & (uint32_t)kPRINTF_Space)) + { + schar = ' '; + ++vlen; + } + else + { + schar = '\0'; + } + } + } + dschar = false; + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if ('\0' != schar) + { + (void)func_ptr(schar); + count++; + } + dschar = true; + DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr); + vlen = (int32_t)field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + if ('\0' != schar) + { + (void)func_ptr(schar); + count++; + } + dschar = true; + } + } + if ((!dschar) && ('\0' != schar)) + { + (void)func_ptr(schar); + count++; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#endif /* PRINTF_FLOAT_ENABLE */ + if ((c == 'X') || (c == 'x')) + { + if (c == 'x') + { + use_caps = false; + } +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt)) + { + uval = (uint64_t)va_arg(ap, uint64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (uint32_t)va_arg(ap, uint32_t); + } + vlen = DbgConsole_ConvertRadixNumToString(vstr, &uval, 0, 16, use_caps); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + dschar = false; + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + (void)func_ptr('0'); + (void)func_ptr((use_caps ? 'X' : 'x')); + count += 2; + /*vlen += 2;*/ + dschar = true; + } + DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr); + vlen = (int32_t)field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Pound)) + { + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + vlen += 2; + } + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + (void)func_ptr('0'); + (void)func_ptr(use_caps ? 'X' : 'x'); + count += 2; + + dschar = true; + } + } + } + + if ((0U != (flags_used & (uint32_t)kPRINTF_Pound)) && (!dschar)) + { + (void)func_ptr('0'); + (void)func_ptr(use_caps ? 'X' : 'x'); + count += 2; + vlen += 2; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u')) + { +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt)) + { + uval = (uint64_t)va_arg(ap, uint64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (uint32_t)va_arg(ap, uint32_t); + } + switch (c) + { + case 'o': + radix = 8; + break; + case 'b': + radix = 2; + break; + case 'p': + radix = 16; + break; + case 'u': + radix = 10; + break; + default: + /* MISRA C-2012 Rule 16.4 */ + break; + } + vlen = DbgConsole_ConvertRadixNumToString(vstr, &uval, 0, (int32_t)radix, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr); + vlen = (int32_t)field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if !PRINTF_ADVANCED_ENABLE + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); +#endif /* !PRINTF_ADVANCED_ENABLE */ + if (vstrp != NULL) + { + while ('\0' != *vstrp) + { + (void)func_ptr(*vstrp--); + count++; + } + } +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_Minus)) + { + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + else if (c == 'c') + { + cval = (int32_t)va_arg(ap, uint32_t); + (void)func_ptr(cval); + count++; + } + else if (c == 's') + { + sval = (char *)va_arg(ap, char *); + if (NULL != sval) + { +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + vlen = (int32_t)precision_width; + } + else + { + vlen = (int32_t)strlen(sval); + } +#else + vlen = (int32_t)strlen(sval); +#endif /* PRINTF_ADVANCED_ENABLE */ +#if PRINTF_ADVANCED_ENABLE + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) +#endif /* PRINTF_ADVANCED_ENABLE */ + { + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + } + +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + while (('\0' != *sval) && (vlen > 0)) + { + (void)func_ptr(*sval++); + count++; + vlen--; + } + /* In case that vlen sval is shorter than vlen */ + vlen = (int32_t)precision_width - vlen; + } + else + { +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != *sval) + { + (void)func_ptr(*sval++); + count++; + } +#if PRINTF_ADVANCED_ENABLE + } +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_Minus)) + { + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + } + else + { + (void)func_ptr(c); + count++; + } + } + p++; + } + return count; +} + +/*! + * @brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * @param[in] line_ptr The input line of ASCII data. + * @param[in] format Format first points to the format string. + * @param[in] args_ptr The list of parameters. + * + * @return Number of input items converted and assigned. + * @retval IO_EOF When line_ptr is empty string "". + */ +static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr) +{ + uint8_t base; + int8_t neg; + /* Identifier for the format string. */ + char *c = format; + char temp; + char *buf; + /* Flag telling the conversion specification. */ + uint32_t flag = 0; + /* Filed width for the matching input streams. */ + uint32_t field_width; + /* How many arguments are assigned except the suppress. */ + uint32_t nassigned = 0; + bool match_failure = false; + /* How many characters are read from the input streams. */ + uint32_t n_decode = 0; + + int32_t val; + + const char *s; + /* Identifier for the input string. */ + const char *p = line_ptr; + +#if SCANF_FLOAT_ENABLE + double fnum = 0.0; +#endif /* SCANF_FLOAT_ENABLE */ + + /* Return EOF error before any conversion. */ + if (*p == '\0') + { + return -1; + } + + /* Decode directives. */ + while (('\0' != (*c)) && ('\0' != (*p))) + { + /* Ignore all white-spaces in the format strings. */ + if (0U != DbgConsole_ScanIgnoreWhiteSpace((const char **)(void *)&c)) + { + n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p); + } + else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%'))) + { + /* Ordinary characters. */ + c++; + if (*p == *c) + { + n_decode++; + p++; + c++; + } + else + { + /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream. + * However, it is deserted now. */ + break; + } + } + else + { + /* convernsion specification */ + c++; + /* Reset. */ + flag = 0; + field_width = 0; + base = 0; + + /* Loop to get full conversion specification. */ + while (('\0' != *c) && (0U == (flag & (uint32_t)kSCANF_DestMask))) + { + switch (*c) + { +#if SCANF_ADVANCED_ENABLE + case '*': + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + /* Match failure. */ + match_failure = true; + break; + } + flag |= (uint32_t)kSCANF_Suppress; + c++; + break; + case 'h': + if (0U != (flag & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + match_failure = true; + break; + } + + if (c[1] == 'h') + { + flag |= (uint32_t)kSCANF_LengthChar; + c++; + } + else + { + flag |= (uint32_t)kSCANF_LengthShortInt; + } + c++; + break; + case 'l': + if (0U != (flag & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + match_failure = true; + break; + } + + if (c[1] == 'l') + { + flag |= (uint32_t)kSCANF_LengthLongLongInt; + c++; + } + else + { + flag |= (uint32_t)kSCANF_LengthLongInt; + } + c++; + break; +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + case 'L': + if (flag & (uint32_t)kSCANF_LengthMask) + { + /* Match failure. */ + match_failure = true; + break; + } + flag |= (uint32_t)kSCANF_LengthLongLongDouble; + c++; + break; +#endif /* SCANF_FLOAT_ENABLE */ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if (0U != field_width) + { + /* Match failure. */ + match_failure = true; + break; + } + do + { + field_width = field_width * 10U + ((uint32_t)*c - (uint32_t)'0'); + c++; + } while ((*c >= '0') && (*c <= '9')); + break; + case 'd': + base = 10; + flag |= (uint32_t)kSCANF_TypeSinged; + flag |= (uint32_t)kSCANF_DestInt; + c++; + break; + case 'u': + base = 10; + flag |= (uint32_t)kSCANF_DestInt; + c++; + break; + case 'o': + base = 8; + flag |= (uint32_t)kSCANF_DestInt; + c++; + break; + case 'x': + case 'X': + base = 16; + flag |= (uint32_t)kSCANF_DestInt; + c++; + break; + case 'i': + base = 0; + flag |= (uint32_t)kSCANF_DestInt; + c++; + break; +#if SCANF_FLOAT_ENABLE + case 'a': + case 'A': + case 'e': + case 'E': + case 'f': + case 'F': + case 'g': + case 'G': + flag |= kSCANF_DestFloat; + c++; + break; +#endif /* SCANF_FLOAT_ENABLE */ + case 'c': + flag |= (uint32_t)kSCANF_DestChar; + if (0U == field_width) + { + field_width = 1; + } + c++; + break; + case 's': + flag |= (uint32_t)kSCANF_DestString; + c++; + break; + default: + /* Match failure. */ + match_failure = true; + break; + } + + /* Match failure. */ + if (match_failure) + { + return (int)nassigned; + } + } + + if (0U == (flag & (uint32_t)kSCANF_DestMask)) + { + /* Format strings are exhausted. */ + return (int)nassigned; + } + + if (0U == field_width) + { + /* Large than length of a line. */ + field_width = 99; + } + + /* Matching strings in input streams and assign to argument. */ + switch (flag & (uint32_t)kSCANF_DestMask) + { + case (uint32_t)kSCANF_DestChar: + s = (const char *)p; + buf = va_arg(args_ptr, char *); + while (((field_width--) > 0U) && ('\0' != *p)) + { + if (0U == (flag & (uint32_t)kSCANF_Suppress)) + { + *buf++ = *p++; + } + else + { + p++; + } + n_decode++; + } + + if ((0U == (flag & (uint32_t)kSCANF_Suppress)) && (s != p)) + { + nassigned++; + } + break; + case (uint32_t)kSCANF_DestString: + n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p); + s = p; + buf = va_arg(args_ptr, char *); + while ((field_width-- > 0U) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') && + (*p != '\r') && (*p != '\v') && (*p != '\f')) + { + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + p++; + } + else + { + *buf++ = *p++; + } + n_decode++; + } + + if ((0U == (flag & (uint32_t)kSCANF_Suppress)) && (s != p)) + { + /* Add NULL to end of string. */ + *buf = '\0'; + nassigned++; + } + break; + case (uint32_t)kSCANF_DestInt: + n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p); + s = p; + val = 0; + if ((base == 0U) || (base == 16U)) + { + if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) + { + base = 16U; + if (field_width >= 1U) + { + p += 2; + n_decode += 2U; + field_width -= 2U; + } + } + } + + if (base == 0U) + { + if (s[0] == '0') + { + base = 8U; + } + else + { + base = 10U; + } + } + + neg = 1; + switch (*p) + { + case '-': + neg = -1; + n_decode++; + p++; + field_width--; + break; + case '+': + neg = 1; + n_decode++; + p++; + field_width--; + break; + default: + /* MISRA C-2012 Rule 16.4 */ + break; + } + + while ((field_width-- > 0U) && (*p > '\0')) + { + if ((*p <= '9') && (*p >= '0')) + { + temp = *p - '0' + (char)0; + } + else if ((*p <= 'f') && (*p >= 'a')) + { + temp = *p - 'a' + (char)10; + } + else if ((*p <= 'F') && (*p >= 'A')) + { + temp = *p - 'A' + (char)10; + } + else + { + temp = (char)base; + } + + if ((uint8_t)temp >= base) + { + break; + } + else + { + val = (int32_t)base * val + (int32_t)temp; + } + p++; + n_decode++; + } + val *= neg; + if (0U == (flag & (uint32_t)kSCANF_Suppress)) + { +#if SCANF_ADVANCED_ENABLE + switch (flag & (uint32_t)kSCANF_LengthMask) + { + case (uint32_t)kSCANF_LengthChar: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(args_ptr, signed char *) = (signed char)val; + } + else + { + *va_arg(args_ptr, unsigned char *) = (unsigned char)val; + } + break; + case (uint32_t)kSCANF_LengthShortInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(args_ptr, signed short *) = (signed short)val; + } + else + { + *va_arg(args_ptr, unsigned short *) = (unsigned short)val; + } + break; + case (uint32_t)kSCANF_LengthLongInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(args_ptr, signed long int *) = (signed long int)val; + } + else + { + *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val; + } + break; + case (uint32_t)kSCANF_LengthLongLongInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(args_ptr, signed long long int *) = (signed long long int)val; + } + else + { + *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val; + } + break; + default: + /* The default type is the type int. */ + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(args_ptr, unsigned int *) = (unsigned int)val; + } + break; + } +#else + /* The default type is the type int. */ + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(args_ptr, unsigned int *) = (unsigned int)val; + } +#endif /* SCANF_ADVANCED_ENABLE */ + nassigned++; + } + break; +#if SCANF_FLOAT_ENABLE + case (uint32_t)kSCANF_DestFloat: + n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p); + fnum = strtod(p, (char **)&s); + + if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL)) + { + break; + } + + n_decode += (int)(s) - (int)(p); + p = s; + if (0U == (flag & (uint32_t)kSCANF_Suppress)) + { + if (0U != (flag & (uint32_t)kSCANF_LengthLongLongDouble)) + { + *va_arg(args_ptr, double *) = fnum; + } + else + { + *va_arg(args_ptr, float *) = (float)fnum; + } + nassigned++; + } + break; +#endif /* SCANF_FLOAT_ENABLE */ + default: + /* Match failure. */ + match_failure = true; + break; + } + + /* Match failure. */ + if (match_failure) + { + return (int)nassigned; + } + } + } + return (int)nassigned; +} +#endif /* SDK_DEBUGCONSOLE */ + +/*************Code to support toolchain's printf, scanf *******************************/ +/* These function __write and __read is used to support IAR toolchain to printf and scanf*/ +#if (defined(__ICCARM__)) +#if defined(SDK_DEBUGCONSOLE_UART) +#pragma weak __write +size_t __write(int handle, const unsigned char *buffer, size_t size); +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + size_t ret; + if (NULL == buffer) + { + /* + * This means that we should flush internal buffers. Since we don't we just return. + * (Remember, "handle" == -1 means that all handles should be flushed.) + */ + ret = (size_t)0; + } + else if ((handle != 1) && (handle != 2)) + { + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. + */ + ret = (size_t)-1; + } + else if (kSerialPort_None == s_debugConsole.type) + { + /* Do nothing if the debug UART is not initialized. */ + ret = (size_t)-1; + } + else + { + /* Send data. */ + (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], buffer, size); + ret = size; + } + return ret; +} + +#pragma weak __read +size_t __read(int handle, unsigned char *buffer, size_t size); +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + size_t ret; + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + ret = ((size_t)-1); + } + else if (kSerialPort_None == s_debugConsole.type) + { + /* Do nothing if the debug UART is not initialized. */ + ret = ((size_t)-1); + } + else + { + /* Receive data. */ + (void)s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], buffer, size); + ret = size; + } + return ret; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* support LPC Xpresso with RedLib */ +#elif (defined(__REDLIB__)) + +#if (defined(SDK_DEBUGCONSOLE_UART)) +int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.type) + { + return -1; + } + + /* Send data. */ + (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size); + + return 0; +} + +int __attribute__((weak)) __sys_readc(void) +{ + char tmp; + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.type) + { + return -1; + } + + /* Receive data. */ + s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)&tmp, sizeof(tmp)); + + return tmp; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/ +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#if defined(SDK_DEBUGCONSOLE_UART) +#if defined(__CC_ARM) +struct __FILE +{ + int handle; + /* + * Whatever you require here. If the only file you are using is standard output using printf() for debugging, + * no file handling is required. + */ +}; +#endif + +/* FILE is typedef in stdio.h. */ +#pragma weak __stdout +#pragma weak __stdin +FILE __stdout; +FILE __stdin; + +#pragma weak fputc +int fputc(int ch, FILE *f) +{ + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.type) + { + return -1; + } + + /* Send data. */ + (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1); + return 1; +} + +#pragma weak fgetc +int fgetc(FILE *f) +{ + char ch; + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.type) + { + return -1; + } + + /* Receive data. */ + s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1); + return ch; +} + +/* + * Terminate the program, passing a return code back to the user. + * This function may not return. + */ +void _sys_exit(int returncode) +{ + while (1) + { + } +} + +/* + * Writes a character to the output channel. This function is used + * for last-resort error message output. + */ +void _ttywrch(int ch) +{ + char ench = ch; + /* Send data. */ + s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ench), 1); +} + +char *_sys_command_string(char *cmd, int len) +{ + return (cmd); +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function __write_r and __read_r are used to support Xtensa Clang toolchain to printf and scanf */ +#elif defined(__XTENSA__) && defined(__XT_CLANG__) +#if defined(SDK_DEBUGCONSOLE_UART) + +int __attribute__((weak)) _write_r(void *ptr, int handle, char *buffer, int size); +int __attribute__((weak)) _write_r(void *ptr, int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.type) + { + return -1; + } + + /* Send data. */ + (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size); + + return size; +} + +int __attribute__((weak)) _read_r(void *ptr, int handle, char *buffer, int size); +int __attribute__((weak)) _read_r(void *ptr, int handle, char *buffer, int size) +{ + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return -1; + } + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.type) + { + return -1; + } + + /* Receive data. */ + (void)s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size); + return size; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/ +#elif (defined(__GNUC__)) + +#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \ + (defined(__MCUXPRESSO) && (defined(SDK_DEBUGCONSOLE_UART)))) +int __attribute__((weak)) _write(int handle, char *buffer, int size); +int __attribute__((weak)) _write(int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.type) + { + return -1; + } + + /* Send data. */ + (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size); + + return size; +} + +int __attribute__((weak)) _read(int handle, char *buffer, int size); +int __attribute__((weak)) _read(int handle, char *buffer, int size) +{ + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return -1; + } + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.type) + { + return -1; + } + + /* Receive data. */ + (void)s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size); + return size; +} +#endif + +#endif /* __ICCARM__ */ diff --git a/devices/MIMX8MQ6/utilities/debug_console_lite/fsl_debug_console.h b/devices/MIMX8MQ6/utilities/debug_console_lite/fsl_debug_console.h new file mode 100644 index 000000000..755b434fe --- /dev/null +++ b/devices/MIMX8MQ6/utilities/debug_console_lite/fsl_debug_console.h @@ -0,0 +1,224 @@ +/* + * Copyright 2017-2018, 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Debug console shall provide input and output functions to scan and print formatted data. + * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier" + * - [flags] :'-', '+', '#', ' ', '0' + * - [width]: number (0,1...) + * - [.precision]: number (0,1...) + * - [length]: do not support + * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n' + * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier" + * - [*]: is supported. + * - [width]: number (0,1...) + * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t') + * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's' + */ + +#ifndef _FSL_DEBUGCONSOLE_H_ +#define _FSL_DEBUGCONSOLE_H_ + +#include "fsl_common.h" + +/* + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */ +#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */ +#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */ +#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */ + +/*! @brief Definition to select sdk or toolchain printf, scanf. */ +#ifndef SDK_DEBUGCONSOLE +#define SDK_DEBUGCONSOLE DEBUGCONSOLE_REDIRECT_TO_SDK +#endif + +#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE) +#include +#endif + +/*! @brief Definition to printf the float number. */ +#ifndef PRINTF_FLOAT_ENABLE +#define PRINTF_FLOAT_ENABLE 0U +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! @brief Definition to scanf the float number. */ +#ifndef SCANF_FLOAT_ENABLE +#define SCANF_FLOAT_ENABLE 0U +#endif /* SCANF_FLOAT_ENABLE */ + +/*! @brief Definition to support advanced format specifier for printf. */ +#ifndef PRINTF_ADVANCED_ENABLE +#define PRINTF_ADVANCED_ENABLE 0U +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Definition to support advanced format specifier for scanf. */ +#ifndef SCANF_ADVANCED_ENABLE +#define SCANF_ADVANCED_ENABLE 0U +#endif /* SCANF_ADVANCED_ENABLE */ + +/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. + * + * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf. + * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf. + * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function. + */ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */ +#define PRINTF +#define SCANF +#define PUTCHAR +#define GETCHAR +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */ +#define PRINTF DbgConsole_Printf +#define SCANF DbgConsole_Scanf +#define PUTCHAR DbgConsole_Putchar +#define GETCHAR DbgConsole_Getchar +#elif SDK_DEBUGCONSOLE == \ + DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ */ +#define PRINTF printf +#define SCANF scanf +#define PUTCHAR putchar +#define GETCHAR getchar +#endif /* SDK_DEBUGCONSOLE */ + +typedef enum _serial_port_type +{ + kSerialPort_None = 0U, /*!< Serial port is none */ + kSerialPort_Uart = 1U, /*!< Serial port UART */ +} serial_port_type_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name Initialization*/ +/* @{ */ + +#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) +/*! + * @brief Initializes the peripheral used for debug messages. + * + * Call this function to enable debug log messages to be output via the specified peripheral, + * frequency of peripheral source clock, and base address at the specified baud rate. + * After this function has returned, stdout and stdin are connected to the selected peripheral. + * + * @param instance The instance of the module.If the device is kSerialPort_Uart, + * the instance is UART peripheral instance. The UART hardware peripheral + * type is determined by UART adapter. For example, if the instance is 1, + * if the lpuart_adapter.c is added to the current project, the UART periheral + * is LPUART1. + * If the uart_adapter.c is added to the current project, the UART periheral + * is UART1. + * @param baudRate The desired baud rate in bits per second. + * @param device Low level device type for the debug console, can be one of the following. + * @arg kSerialPort_Uart. + * @param clkSrcFreq Frequency of peripheral source clock. + * + * @return Indicates whether initialization was successful or not. + * @retval kStatus_Success Execution successfully + * @retval kStatus_Fail Execution failure + */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq); + +/*! + * @brief De-initializes the peripheral used for debug messages. + * + * Call this function to disable debug log messages to be output via the specified peripheral + * base address and at the specified baud rate. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_Deinit(void); + +#else +/*! + * Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_Init(uint8_t instance, + uint32_t baudRate, + serial_port_type_t device, + uint32_t clkSrcFreq) +{ + (void)instance; + (void)baudRate; + (void)device; + (void)clkSrcFreq; + return (status_t)kStatus_Fail; +} +/*! + * Use an error to replace the DbgConsole_Deinit when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_Deinit(void) +{ + return (status_t)kStatus_Fail; +} + +#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ + +#if SDK_DEBUGCONSOLE +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param fmt_s Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Printf(const char *fmt_s, ...); + +/*! + * @brief Writes a character to stdout. + * + * Call this function to write a character to stdout. + * + * @param ch Character to be written. + * @return Returns the character written. + */ +int DbgConsole_Putchar(int ch); + +/*! + * @brief Reads formatted data from the standard input stream. + * + * Call this function to read formatted data from the standard input stream. + * + * @param fmt_ptr Format control string. + * @return Returns the number of fields successfully converted and assigned. + */ +int DbgConsole_Scanf(char *fmt_ptr, ...); + +/*! + * @brief Reads a character from standard input. + * + * Call this function to read a character from standard input. + * + * @return Returns the character read. + */ +int DbgConsole_Getchar(void); + +#endif /* SDK_DEBUGCONSOLE */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/devices/MIMX8MQ6/utilities/debug_console_lite/utility_assert_lite_MIMX8MQ6.cmake b/devices/MIMX8MQ6/utilities/debug_console_lite/utility_assert_lite_MIMX8MQ6.cmake new file mode 100644 index 000000000..2daaadd88 --- /dev/null +++ b/devices/MIMX8MQ6/utilities/debug_console_lite/utility_assert_lite_MIMX8MQ6.cmake @@ -0,0 +1,10 @@ +include_guard(GLOBAL) +message("utility_assert_lite component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_assert.c +) + + +include(utility_debug_console_lite_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/utilities/debug_console_lite/utility_debug_console_lite_MIMX8MQ6.cmake b/devices/MIMX8MQ6/utilities/debug_console_lite/utility_debug_console_lite_MIMX8MQ6.cmake new file mode 100644 index 000000000..c30ca10b1 --- /dev/null +++ b/devices/MIMX8MQ6/utilities/debug_console_lite/utility_debug_console_lite_MIMX8MQ6.cmake @@ -0,0 +1,17 @@ +include_guard(GLOBAL) +message("utility_debug_console_lite component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_debug_console.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(component_iuart_adapter_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/utilities/fsl_assert.c b/devices/MIMX8MQ6/utilities/fsl_assert.c new file mode 100644 index 000000000..d2cbe28ef --- /dev/null +++ b/devices/MIMX8MQ6/utilities/fsl_assert.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); +#else + (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); +#endif + + for (;;) + { + __BKPT(0); + } +} +#elif (defined(__GNUC__)) +#if defined(__REDLIB__) +void __assertion_failed(char *failedExpr) +{ + (void)PRINTF("ASSERT ERROR \" %s \n", failedExpr); + for (;;) + { + __BKPT(0); + } +} +#else +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, + func); + for (;;) + { + __BKPT(0); + } +} +#endif /* defined(__REDLIB__) */ +#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */ +#endif /* NDEBUG */ diff --git a/devices/MIMX8MQ6/utilities/fsl_sbrk.c b/devices/MIMX8MQ6/utilities/fsl_sbrk.c new file mode 100644 index 000000000..5727b2f86 --- /dev/null +++ b/devices/MIMX8MQ6/utilities/fsl_sbrk.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#if defined(__GNUC__) +#include +#include +#endif + +#if defined(__GNUC__) +/*! + * @brief Function to override ARMGCC default function _sbrk + * + * _sbrk is called by malloc. ARMGCC default _sbrk compares "SP" register and + * heap end, if heap end is larger than "SP", then _sbrk returns error and + * memory allocation failed. This function changes to compare __HeapLimit with + * heap end. + */ +caddr_t _sbrk(int incr); +caddr_t _sbrk(int incr) +{ + extern char end __asm("end"); + extern char heap_limit __asm("__HeapLimit"); + static char *heap_end; + char *prev_heap_end; + caddr_t ret; + + if (heap_end == NULL) + { + heap_end = &end; + } + + prev_heap_end = heap_end; + + if ((unsigned int)heap_end + (unsigned int)incr > (unsigned int)(&heap_limit)) + { + errno = ENOMEM; + + ret = (caddr_t)-1; + } + else + { + heap_end = (char *)((unsigned int)heap_end + (unsigned int)incr); + + ret = (caddr_t)prev_heap_end; + } + + return ret; +} +#endif diff --git a/devices/MIMX8MQ6/utilities/str/fsl_str.c b/devices/MIMX8MQ6/utilities/str/fsl_str.c new file mode 100644 index 000000000..c03ef8309 --- /dev/null +++ b/devices/MIMX8MQ6/utilities/str/fsl_str.c @@ -0,0 +1,1554 @@ +/* + * Copyright 2017, 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include +#include +#include +#include /* MISRA C-2012 Rule 22.9 */ +#include "fsl_str.h" +#include "fsl_debug_console_conf.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The overflow value.*/ +#ifndef HUGE_VAL +#define HUGE_VAL (99.e99) +#endif /* HUGE_VAL */ + +#ifndef MAX_FIELD_WIDTH +#define MAX_FIELD_WIDTH 99U +#endif + +#if PRINTF_ADVANCED_ENABLE +/*! @brief Specification modifier flags for printf. */ +enum _debugconsole_printf_flag +{ + kPRINTF_Minus = 0x01U, /*!< Minus FLag. */ + kPRINTF_Plus = 0x02U, /*!< Plus Flag. */ + kPRINTF_Space = 0x04U, /*!< Space Flag. */ + kPRINTF_Zero = 0x08U, /*!< Zero Flag. */ + kPRINTF_Pound = 0x10U, /*!< Pound Flag. */ + kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */ + kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */ + kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */ + kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */ +}; +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Specification modifier flags for scanf. */ +enum _debugconsole_scanf_flag +{ + kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */ + kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */ + kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */ + kSCANF_DestString = 0x8U, /*!< Destination String FLag. */ + kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */ + kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */ + kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */ + kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */ +#if SCANF_ADVANCED_ENABLE + kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */ + kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */ + kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */ + kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */ +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */ +#endif /*PRINTF_FLOAT_ENABLE */ + kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */ +}; + +/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */ +#if defined(__CC_ARM) +#pragma diag_suppress 1256 +#endif /* __CC_ARM */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Scanline function which ignores white spaces. + * + * @param[in] s The address of the string pointer to update. + * @return String without white spaces. + */ +static uint32_t ScanIgnoreWhiteSpace(const char **s); + +/*! + * @brief Converts a radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] neg Polarity of the number. + * @param[in] radix The radix to be converted to. + * @param[in] use_caps Used to identify %x/X output format. + + * @return Length of the converted string. + */ +static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps); + +#if PRINTF_FLOAT_ENABLE +/*! + * @brief Converts a floating radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] radix The radix to be converted to. + * @param[in] precision_width Specify the precision width. + + * @return Length of the converted string. + */ +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width); + +#endif /* PRINTF_FLOAT_ENABLE */ + +/*************Code for process formatted data*******************************/ +#if PRINTF_ADVANCED_ENABLE +static uint8_t PrintGetSignChar(int64_t ival, uint32_t flags_used, char *schar) +{ + uint8_t len = 1U; + if (ival < 0) + { + *schar = '-'; + } + else + { + if (0U != (flags_used & (uint32_t)kPRINTF_Plus)) + { + *schar = '+'; + } + else if (0U != (flags_used & (uint32_t)kPRINTF_Space)) + { + *schar = ' '; + } + else + { + *schar = '\0'; + len = 0U; + } + } + return len; +} +#endif + +static uint32_t PrintGetWidth(const char **p, va_list *ap) +{ + uint32_t field_width = 0; + uint8_t done = 0U; + char c; + + while (0U == done) + { + c = *(++(*p)); + if ((c >= '0') && (c <= '9')) + { + (field_width) = ((field_width)*10U) + ((uint32_t)c - (uint32_t)'0'); + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + (field_width) = (uint32_t)va_arg(*ap, uint32_t); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --(*p); + done = 1U; + } + } + return field_width; +} + +static uint32_t PrintGetPrecision(const char **s, va_list *ap, bool *valid_precision_width) +{ + const char *p = *s; + uint32_t precision_width = 6U; + uint8_t done = 0U; + +#if PRINTF_ADVANCED_ENABLE + if (NULL != valid_precision_width) + { + *valid_precision_width = false; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + if (*++p == '.') + { + /* Must get precision field width, if present. */ + precision_width = 0U; + done = 0U; + while (0U == done) + { + char c = *++p; + if ((c >= '0') && (c <= '9')) + { + precision_width = (precision_width * 10U) + ((uint32_t)c - (uint32_t)'0'); +#if PRINTF_ADVANCED_ENABLE + if (NULL != valid_precision_width) + { + *valid_precision_width = true; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + precision_width = (uint32_t)va_arg(*ap, uint32_t); + if (NULL != valid_precision_width) + { + *valid_precision_width = true; + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = 1U; + } + } + } + else + { + /* We've gone one char too far. */ + --p; + } + *s = p; + return precision_width; +} + +static uint32_t PrintIsobpu(const char c) +{ + uint32_t ret = 0U; + if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u')) + { + ret = 1U; + } + return ret; +} + +static uint32_t PrintIsdi(const char c) +{ + uint32_t ret = 0U; + if ((c == 'd') || (c == 'i')) + { + ret = 1U; + } + return ret; +} + +static void PrintOutputdifFobpu(uint32_t flags_used, + uint32_t field_width, + uint32_t vlen, + char schar, + char *vstrp, + printfCb cb, + char *buf, + int32_t *count) +{ +#if PRINTF_ADVANCED_ENABLE + /* Do the ZERO pad. */ + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if ('\0' != schar) + { + cb(buf, count, schar, 1); + schar = '\0'; + } + cb(buf, count, '0', (int)field_width - (int)vlen); + vlen = field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + cb(buf, count, ' ', (int)field_width - (int)vlen); + if ('\0' != schar) + { + cb(buf, count, schar, 1); + schar = '\0'; + } + } + } + /* The string was built in reverse order, now display in correct order. */ + if ('\0' != schar) + { + cb(buf, count, schar, 1); + } +#else + cb(buf, count, ' ', (int)field_width - (int)vlen); +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != (*vstrp)) + { + cb(buf, count, *vstrp--, 1); + } +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_Minus)) + { + cb(buf, count, ' ', (int)field_width - (int)vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ +} + +static void PrintOutputxX(uint32_t flags_used, + uint32_t field_width, + uint32_t vlen, + bool use_caps, + char *vstrp, + printfCb cb, + char *buf, + int32_t *count) +{ +#if PRINTF_ADVANCED_ENABLE + uint8_t dschar = 0; + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + cb(buf, count, '0', 1); + cb(buf, count, (use_caps ? 'X' : 'x'), 1); + dschar = 1U; + } + cb(buf, count, '0', (int)field_width - (int)vlen); + vlen = field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + vlen += 2U; + } + cb(buf, count, ' ', (int)field_width - (int)vlen); + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + cb(buf, count, '0', 1); + cb(buf, count, (use_caps ? 'X' : 'x'), 1); + dschar = 1U; + } + } + } + + if ((0U != (flags_used & (uint32_t)kPRINTF_Pound)) && (0U == dschar)) + { + cb(buf, count, '0', 1); + cb(buf, count, (use_caps ? 'X' : 'x'), 1); + vlen += 2U; + } +#else + cb(buf, count, ' ', (int)field_width - (int)vlen); +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != (*vstrp)) + { + cb(buf, count, *vstrp--, 1); + } +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_Minus)) + { + cb(buf, count, ' ', (int)field_width - (int)vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ +} + +static uint32_t PrintIsfF(const char c) +{ + uint32_t ret = 0U; + if ((c == 'f') || (c == 'F')) + { + ret = 1U; + } + return ret; +} + +static uint32_t PrintIsxX(const char c) +{ + uint32_t ret = 0U; + if ((c == 'x') || (c == 'X')) + { + ret = 1U; + } + return ret; +} + +#if PRINTF_ADVANCED_ENABLE +static uint32_t PrintCheckFlags(const char **s) +{ + const char *p = *s; + /* First check for specification modifier flags. */ + uint32_t flags_used = 0U; + bool done = false; + while (false == done) + { + switch (*++p) + { + case '-': + flags_used |= (uint32_t)kPRINTF_Minus; + break; + case '+': + flags_used |= (uint32_t)kPRINTF_Plus; + break; + case ' ': + flags_used |= (uint32_t)kPRINTF_Space; + break; + case '0': + flags_used |= (uint32_t)kPRINTF_Zero; + break; + case '#': + flags_used |= (uint32_t)kPRINTF_Pound; + break; + default: + /* We've gone one char too far. */ + --p; + done = true; + break; + } + } + *s = p; + return flags_used; +} +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE +/* + * Check for the length modifier. + */ +static uint32_t PrintGetLengthFlag(const char **s) +{ + const char *p = *s; + /* First check for specification modifier flags. */ + uint32_t flags_used = 0U; + + switch (/* c = */ *++p) + { + case 'h': + if (*++p != 'h') + { + flags_used |= (uint32_t)kPRINTF_LengthShortInt; + --p; + } + else + { + flags_used |= (uint32_t)kPRINTF_LengthChar; + } + break; + case 'l': + if (*++p != 'l') + { + flags_used |= (uint32_t)kPRINTF_LengthLongInt; + --p; + } + else + { + flags_used |= (uint32_t)kPRINTF_LengthLongLongInt; + } + break; + default: + /* we've gone one char too far */ + --p; + break; + } + *s = p; + return flags_used; +} +#else +static void PrintFilterLengthFlag(const char **s) +{ + const char *p = *s; + char ch; + + do + { + ch = *++p; + } while ((ch == 'h') || (ch == 'l')); + + *s = --p; +} +#endif /* PRINTF_ADVANCED_ENABLE */ + +static uint8_t PrintGetRadixFromobpu(const char c) +{ + uint8_t radix; + + if (c == 'o') + { + radix = 8U; + } + else if (c == 'b') + { + radix = 2U; + } + else if (c == 'p') + { + radix = 16U; + } + else + { + radix = 10U; + } + return radix; +} + +static uint32_t ScanIsWhiteSpace(const char c) +{ + uint32_t ret = 0U; + if ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f')) + { + ret = 1U; + } + return ret; +} + +static uint32_t ScanIgnoreWhiteSpace(const char **s) +{ + uint32_t count = 0U; + char c; + + c = **s; + while (1U == ScanIsWhiteSpace(c)) + { + count++; + (*s)++; + c = **s; + } + return count; +} + +static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps) +{ +#if PRINTF_ADVANCED_ENABLE + int64_t a; + int64_t b; + int64_t c; + + uint64_t ua; + uint64_t ub; + uint64_t uc; +#else + int32_t a; + int32_t b; + int32_t c; + + uint32_t ua; + uint32_t ub; + uint32_t uc; +#endif /* PRINTF_ADVANCED_ENABLE */ + + int32_t nlen; + char *nstrp; + + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + +#if !(PRINTF_ADVANCED_ENABLE > 0) + neg = 0; +#endif + + if (0 != neg) + { +#if PRINTF_ADVANCED_ENABLE + a = *(int64_t *)nump; +#else + a = *(int32_t *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (a == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (a != 0) + { +#if PRINTF_ADVANCED_ENABLE + b = (int64_t)a / (int64_t)radix; + c = (int64_t)a - ((int64_t)b * (int64_t)radix); + if (c < 0) + { + c = (int64_t)'0' - c; + } +#else + b = a / radix; + c = a - (b * radix); + if (c < 0) + { + c = (int32_t)'0' - c; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + c = c + (int32_t)'0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + else + { +#if PRINTF_ADVANCED_ENABLE + ua = *(uint64_t *)nump; +#else + ua = *(uint32_t *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (ua == 0U) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (ua != 0U) + { +#if PRINTF_ADVANCED_ENABLE + ub = (uint64_t)ua / (uint64_t)radix; + uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix); +#else + ub = ua / (uint32_t)radix; + uc = ua - (ub * (uint32_t)radix); +#endif /* PRINTF_ADVANCED_ENABLE */ + + if (uc < 10U) + { + uc = uc + (uint32_t)'0'; + } + else + { + uc = uc - 10U + (uint32_t)(use_caps ? 'A' : 'a'); + } + ua = ub; + *nstrp++ = (char)uc; + ++nlen; + } + } + return nlen; +} + +#if PRINTF_FLOAT_ENABLE +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width) +{ + int32_t a; + int32_t b; + int32_t c; + int32_t i; + double fa; + double dc; + double fb; + double r; + double fractpart; + double intpart; + + int32_t nlen; + char *nstrp; + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + r = *(double *)nump; + if (0.0 == r) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + fractpart = modf((double)r, (double *)&intpart); + /* Process fractional part. */ + for (i = 0; i < (int32_t)precision_width; i++) + { + fractpart *= (double)radix; + } + if (r >= (double)0.0) + { + fa = fractpart + (double)0.5; + if (fa >= pow((double)10, (double)precision_width)) + { + intpart++; + } + } + else + { + fa = fractpart - (double)0.5; + if (fa <= -pow((double)10, (double)precision_width)) + { + intpart--; + } + } + for (i = 0; i < (int32_t)precision_width; i++) + { + fb = fa / (double)radix; + dc = (fa - (double)(int64_t)fb * (double)radix); + c = (int32_t)dc; + if (c < 0) + { + c = (int32_t)'0' - c; + } + else + { + c = c + '0'; + } + fa = fb; + *nstrp++ = (char)c; + ++nlen; + } + *nstrp++ = (char)'.'; + ++nlen; + a = (int32_t)intpart; + if (a == 0) + { + *nstrp++ = '0'; + ++nlen; + } + else + { + while (a != 0) + { + b = (int32_t)a / (int32_t)radix; + c = (int32_t)a - ((int32_t)b * (int32_t)radix); + if (c < 0) + { + c = (int32_t)'0' - c; + } + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + return nlen; +} +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! + * brief This function outputs its parameters according to a formatted string. + * + * note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * param[in] fmt_ptr Format string for printf. + * param[in] args_ptr Arguments to printf. + * param[in] buf pointer to the buffer + * param cb print callback function pointer + * + * return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb) +{ + /* va_list ap; */ + const char *p; + char c; + + char vstr[33]; + char *vstrp = NULL; + int32_t vlen = 0; + + int32_t count = 0; + + uint32_t field_width; + uint32_t precision_width; + char *sval; + int32_t cval; + bool use_caps; + uint8_t radix = 0; + +#if PRINTF_ADVANCED_ENABLE + uint32_t flags_used; + char schar; + int64_t ival; + uint64_t uval = 0; + bool valid_precision_width; +#else + int32_t ival; + uint32_t uval = 0; +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_FLOAT_ENABLE + double fval; +#endif /* PRINTF_FLOAT_ENABLE */ + + /* Start parsing apart the format string and display appropriate formats and data. */ + p = fmt; + while (true) + { + if ('\0' == *p) + { + break; + } + c = *p; + /* + * All formats begin with a '%' marker. Special chars like + * '\n' or '\t' are normally converted to the appropriate + * character by the __compiler__. Thus, no need for this + * routine to account for the '\' character. + */ + if (c != '%') + { + cb(buf, &count, c, 1); + p++; + /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */ + continue; + } + + use_caps = true; + +#if PRINTF_ADVANCED_ENABLE + /* First check for specification modifier flags. */ + flags_used = PrintCheckFlags(&p); +#endif /* PRINTF_ADVANCED_ENABLE */ + + /* Next check for minimum field width. */ + field_width = PrintGetWidth(&p, &ap); + + /* Next check for the width and precision field separator. */ +#if PRINTF_ADVANCED_ENABLE + precision_width = PrintGetPrecision(&p, &ap, &valid_precision_width); +#else + precision_width = PrintGetPrecision(&p, &ap, NULL); + (void)precision_width; +#endif + +#if PRINTF_ADVANCED_ENABLE + /* Check for the length modifier. */ + flags_used |= PrintGetLengthFlag(&p); +#else + /* Filter length modifier. */ + PrintFilterLengthFlag(&p); +#endif + + /* Now we're ready to examine the format. */ + c = *++p; + { + if (1U == PrintIsdi(c)) + { +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt)) + { + ival = (int64_t)va_arg(ap, int64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + ival = (int32_t)va_arg(ap, int32_t); + } + vlen = ConvertRadixNumToString(vstr, (void *)&ival, 1, 10, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + vlen += (int32_t)PrintGetSignChar(ival, flags_used, &schar); + PrintOutputdifFobpu(flags_used, field_width, (uint32_t)vlen, schar, vstrp, cb, buf, &count); +#else + PrintOutputdifFobpu(0U, field_width, (uint32_t)vlen, '\0', vstrp, cb, buf, &count); +#endif + } + else if (1U == PrintIsfF(c)) + { +#if PRINTF_FLOAT_ENABLE + fval = (double)va_arg(ap, double); + vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + vlen += (int32_t)PrintGetSignChar(((fval < 0.0) ? ((int64_t)-1) : ((int64_t)fval)), flags_used, &schar); + PrintOutputdifFobpu(flags_used, field_width, (uint32_t)vlen, schar, vstrp, cb, buf, &count); +#else + PrintOutputdifFobpu(0, field_width, (uint32_t)vlen, '\0', vstrp, cb, buf, &count); +#endif + +#else + (void)va_arg(ap, double); +#endif /* PRINTF_FLOAT_ENABLE */ + } + else if (1U == PrintIsxX(c)) + { + if (c == 'x') + { + use_caps = false; + } +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt)) + { + uval = (uint64_t)va_arg(ap, uint64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (uint32_t)va_arg(ap, uint32_t); + } + vlen = ConvertRadixNumToString(vstr, &uval, 0, 16, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + PrintOutputxX(flags_used, field_width, (uint32_t)vlen, use_caps, vstrp, cb, buf, &count); +#else + PrintOutputxX(0U, field_width, (uint32_t)vlen, use_caps, vstrp, cb, buf, &count); +#endif + } + else if (1U == PrintIsobpu(c)) + { +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt)) + { + uval = (uint64_t)va_arg(ap, uint64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (uint32_t)va_arg(ap, uint32_t); + } + + radix = PrintGetRadixFromobpu(c); + + vlen = ConvertRadixNumToString(vstr, &uval, 0, (int32_t)radix, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + PrintOutputdifFobpu(flags_used, field_width, (uint32_t)vlen, '\0', vstrp, cb, buf, &count); +#else + PrintOutputdifFobpu(0U, field_width, (uint32_t)vlen, '\0', vstrp, cb, buf, &count); +#endif + } + else if (c == 'c') + { + cval = (int32_t)va_arg(ap, uint32_t); + cb(buf, &count, cval, 1); + } + else if (c == 's') + { + sval = (char *)va_arg(ap, char *); + if (NULL != sval) + { +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + vlen = (int32_t)precision_width; + } + else + { + vlen = (int32_t)strlen(sval); + } +#else + vlen = (int32_t)strlen(sval); +#endif /* PRINTF_ADVANCED_ENABLE */ +#if PRINTF_ADVANCED_ENABLE + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) +#endif /* PRINTF_ADVANCED_ENABLE */ + { + cb(buf, &count, ' ', (int)field_width - (int)vlen); + } + +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + while (('\0' != *sval) && (vlen > 0)) + { + cb(buf, &count, *sval++, 1); + vlen--; + } + /* In case that vlen sval is shorter than vlen */ + vlen = (int32_t)precision_width - vlen; + } + else + { +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != (*sval)) + { + cb(buf, &count, *sval++, 1); + } +#if PRINTF_ADVANCED_ENABLE + } +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_Minus)) + { + cb(buf, &count, ' ', (int32_t)field_width - vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + } + else + { + cb(buf, &count, c, 1); + } + } + p++; + } + + return count; +} + +#if SCANF_FLOAT_ENABLE +static uint8_t StrFormatScanIsFloat(char *c) +{ + uint8_t ret = 0U; + if (('a' == (*c)) || ('A' == (*c)) || ('e' == (*c)) || ('E' == (*c)) || ('f' == (*c)) || ('F' == (*c)) || + ('g' == (*c)) || ('G' == (*c))) + { + ret = 1U; + } + return ret; +} +#endif + +static uint8_t StrFormatScanIsFormatStarting(char *c) +{ + uint8_t ret = 1U; + if ((*c != '%')) + { + ret = 0U; + } + else if (*(c + 1) == '%') + { + ret = 0U; + } + else + { + /*MISRA rule 15.7*/ + } + + return ret; +} + +static uint8_t StrFormatScanGetBase(uint8_t base, const char *s) +{ + if (base == 0U) + { + if (s[0] == '0') + { + if ((s[1] == 'x') || (s[1] == 'X')) + { + base = 16; + } + else + { + base = 8; + } + } + else + { + base = 10; + } + } + return base; +} + +static uint8_t StrFormatScanCheckSymbol(const char *p, int8_t *neg) +{ + uint8_t len; + switch (*p) + { + case '-': + *neg = -1; + len = 1; + break; + case '+': + *neg = 1; + len = 1; + break; + default: + *neg = 1; + len = 0; + break; + } + return len; +} + +static uint8_t StrFormatScanFillInteger(uint32_t flag, va_list *args_ptr, int32_t val) +{ +#if SCANF_ADVANCED_ENABLE + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + return 0u; + } + + switch (flag & (uint32_t)kSCANF_LengthMask) + { + case (uint32_t)kSCANF_LengthChar: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed char *) = (signed char)val; + } + else + { + *va_arg(*args_ptr, unsigned char *) = (unsigned char)val; + } + break; + case (uint32_t)kSCANF_LengthShortInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed short *) = (signed short)val; + } + else + { + *va_arg(*args_ptr, unsigned short *) = (unsigned short)val; + } + break; + case (uint32_t)kSCANF_LengthLongInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed long int *) = (signed long int)val; + } + else + { + *va_arg(*args_ptr, unsigned long int *) = (unsigned long int)val; + } + break; + case (uint32_t)kSCANF_LengthLongLongInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed long long int *) = (signed long long int)val; + } + else + { + *va_arg(*args_ptr, unsigned long long int *) = (unsigned long long int)val; + } + break; + default: + /* The default type is the type int. */ + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(*args_ptr, unsigned int *) = (unsigned int)val; + } + break; + } +#else + /* The default type is the type int. */ + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(*args_ptr, unsigned int *) = (unsigned int)val; + } +#endif /* SCANF_ADVANCED_ENABLE */ + + return 1u; +} + +#if SCANF_FLOAT_ENABLE +static uint8_t StrFormatScanFillFloat(uint32_t flag, va_list *args_ptr, double fnum) +{ +#if SCANF_ADVANCED_ENABLE + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + return 0u; + } + else +#endif /* SCANF_ADVANCED_ENABLE */ + { + if (0U != (flag & (uint32_t)kSCANF_LengthLongLongDouble)) + { + *va_arg(*args_ptr, double *) = fnum; + } + else + { + *va_arg(*args_ptr, float *) = (float)fnum; + } + return 1u; + } +} +#endif /* SCANF_FLOAT_ENABLE */ + +static uint8_t StrFormatScanfStringHandling(char **str, uint32_t *flag, uint32_t *field_width, uint8_t *base) +{ + uint8_t exitPending = 0U; + char *c = *str; + + /* Loop to get full conversion specification. */ + while (('\0' != (*c)) && (0U == (*flag & (uint32_t)kSCANF_DestMask))) + { +#if SCANF_ADVANCED_ENABLE + if ('*' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_Suppress)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + (*flag) |= (uint32_t)kSCANF_Suppress; + } + } + else if ('h' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + if (c[1] == 'h') + { + (*flag) |= (uint32_t)kSCANF_LengthChar; + c++; + } + else + { + (*flag) |= (uint32_t)kSCANF_LengthShortInt; + } + } + } + else if ('l' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + if (c[1] == 'l') + { + (*flag) |= (uint32_t)kSCANF_LengthLongLongInt; + c++; + } + else + { + (*flag) |= (uint32_t)kSCANF_LengthLongInt; + } + } + } + else +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + if ('L' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + (*flag) |= (uint32_t)kSCANF_LengthLongLongDouble; + } + } + else +#endif /* SCANF_FLOAT_ENABLE */ + if (((*c) >= '0') && ((*c) <= '9')) + { + { + char *p; + errno = 0; + (*field_width) = strtoul(c, &p, 10); + if (0 != errno) + { + *field_width = 0U; + } + c = p - 1; + } + } + else if ('d' == (*c)) + { + (*base) = 10U; + (*flag) |= (uint32_t)kSCANF_TypeSinged; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('u' == (*c)) + { + (*base) = 10U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('o' == (*c)) + { + (*base) = 8U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if (('x' == (*c))) + { + (*base) = 16U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('X' == (*c)) + { + (*base) = 16U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('i' == (*c)) + { + (*base) = 0U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } +#if SCANF_FLOAT_ENABLE + else if (1U == StrFormatScanIsFloat(c)) + { + (*flag) |= (uint32_t)kSCANF_DestFloat; + } +#endif /* SCANF_FLOAT_ENABLE */ + else if ('c' == (*c)) + { + (*flag) |= (uint32_t)kSCANF_DestChar; + if (MAX_FIELD_WIDTH == (*field_width)) + { + (*field_width) = 1; + } + } + else if ('s' == (*c)) + { + (*flag) |= (uint32_t)kSCANF_DestString; + } + else + { + exitPending = 1U; + } + + if (1U == exitPending) + { + break; + } + else + { + c++; + } + } + *str = c; + return exitPending; +} + +/*! + * brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * param[in] line_ptr The input line of ASCII data. + * param[in] format Format first points to the format string. + * param[in] args_ptr The list of parameters. + * + * return Number of input items converted and assigned. + * retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) +{ + uint8_t base; + int8_t neg; + /* Identifier for the format string. */ + char *c = format; + char *buf; + /* Flag telling the conversion specification. */ + uint32_t flag = 0; + /* Filed width for the matching input streams. */ + uint32_t field_width; + /* How many arguments are assigned except the suppress. */ + uint32_t nassigned = 0; + /* How many characters are read from the input streams. */ + uint32_t n_decode = 0; + + int32_t val; + + uint8_t added; + + uint8_t exitPending = 0; + + const char *s; +#if SCANF_FLOAT_ENABLE + char *s_temp; /* MISRA C-2012 Rule 11.3 */ +#endif + + /* Identifier for the input string. */ + const char *p = line_ptr; + +#if SCANF_FLOAT_ENABLE + double fnum = 0.0; +#endif /* SCANF_FLOAT_ENABLE */ + /* Return EOF error before any conversion. */ + if (*p == '\0') + { + return -1; + } + + /* Decode directives. */ + while (('\0' != (*c)) && ('\0' != (*p))) + { + /* Ignore all white-spaces in the format strings. */ + if (0U != ScanIgnoreWhiteSpace((const char **)((void *)&c))) + { + n_decode += ScanIgnoreWhiteSpace(&p); + } + else if (0U == StrFormatScanIsFormatStarting(c)) + { + /* Ordinary characters. */ + c++; + if (*p == *c) + { + n_decode++; + p++; + c++; + } + else + { + /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream. + * However, it is deserted now. */ + break; + } + } + else + { + /* convernsion specification */ + c++; + /* Reset. */ + flag = 0; + field_width = MAX_FIELD_WIDTH; + base = 0; + added = 0U; + + exitPending = StrFormatScanfStringHandling(&c, &flag, &field_width, &base); + + if (1U == exitPending) + { + /* Format strings are exhausted. */ + break; + } + + /* Matching strings in input streams and assign to argument. */ + if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestChar) + { + s = (const char *)p; + buf = va_arg(args_ptr, char *); + while ((0U != (field_width--)) +#if SCANF_ADVANCED_ENABLE + && ('\0' != (*p)) +#endif + ) + { +#if SCANF_ADVANCED_ENABLE + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + p++; + } + else +#endif + { + *buf++ = *p++; +#if SCANF_ADVANCED_ENABLE + added = 1u; +#endif + } + n_decode++; + } + +#if SCANF_ADVANCED_ENABLE + if (1u == added) +#endif + { + nassigned++; + } + } + else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestString) + { + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + buf = va_arg(args_ptr, char *); + while ((0U != (field_width--)) && (*p != '\0') && (0U == ScanIsWhiteSpace(*p))) + { +#if SCANF_ADVANCED_ENABLE + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + p++; + } + else +#endif + { + *buf++ = *p++; +#if SCANF_ADVANCED_ENABLE + added = 1u; +#endif + } + n_decode++; + } + +#if SCANF_ADVANCED_ENABLE + if (1u == added) +#endif + { + /* Add NULL to end of string. */ + *buf = '\0'; + nassigned++; + } + } + else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestInt) + { + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + val = 0; + base = StrFormatScanGetBase(base, s); + + added = StrFormatScanCheckSymbol(p, &neg); + n_decode += added; + p += added; + field_width -= added; + + s = p; + if (strlen(p) > field_width) + { + char temp[12]; + char *tempEnd; + (void)memcpy(temp, p, sizeof(temp) - 1U); + temp[sizeof(temp) - 1U] = '\0'; + errno = 0; + val = (int32_t)strtoul(temp, &tempEnd, (int)base); + if (0 != errno) + { + break; + } + p = p + (tempEnd - temp); + } + else + { + char *tempEnd; + val = 0; + errno = 0; + val = (int32_t)strtoul(p, &tempEnd, (int)base); + if (0 != errno) + { + break; + } + p = tempEnd; + } + n_decode += (uint32_t)p - (uint32_t)s; + + val *= neg; + + nassigned += StrFormatScanFillInteger(flag, &args_ptr, val); + } +#if SCANF_FLOAT_ENABLE + else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestFloat) + { + n_decode += ScanIgnoreWhiteSpace(&p); + fnum = 0.0; + errno = 0; + + fnum = strtod(p, (char **)&s_temp); + s = s_temp; /* MISRA C-2012 Rule 11.3 */ + + /* MISRA C-2012 Rule 22.9 */ + if (0 != errno) + { + break; + } + + if ((fnum < HUGE_VAL) && (fnum > -HUGE_VAL)) + { + n_decode = (uint32_t)n_decode + (uint32_t)s - (uint32_t)p; + p = s; + nassigned += StrFormatScanFillFloat(flag, &args_ptr, fnum); + } + } +#endif /* SCANF_FLOAT_ENABLE */ + else + { + break; + } + } + } + return (int)nassigned; +} diff --git a/devices/MIMX8MQ6/utilities/str/fsl_str.h b/devices/MIMX8MQ6/utilities/str/fsl_str.h new file mode 100644 index 000000000..bf7adcc52 --- /dev/null +++ b/devices/MIMX8MQ6/utilities/str/fsl_str.h @@ -0,0 +1,66 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FSL_STR_H +#define _FSL_STR_H + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief A function pointer which is used when format printf log. + */ +typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len); + +/*! + * @brief This function outputs its parameters according to a formatted string. + * + * @note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * @param[in] fmt Format string for printf. + * @param[in] ap Arguments to printf. + * @param[in] buf pointer to the buffer + * @param cb print callbck function pointer + * + * @return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb); + +/*! + * @brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * @param[in] line_ptr The input line of ASCII data. + * @param[in] format Format first points to the format string. + * @param[in] args_ptr The list of parameters. + * + * @return Number of input items converted and assigned. + * @retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_STR_H */ diff --git a/devices/MIMX8MQ6/utilities/utilities_misc_utilities_MIMX8MQ6.cmake b/devices/MIMX8MQ6/utilities/utilities_misc_utilities_MIMX8MQ6.cmake new file mode 100644 index 000000000..1defb773a --- /dev/null +++ b/devices/MIMX8MQ6/utilities/utilities_misc_utilities_MIMX8MQ6.cmake @@ -0,0 +1,8 @@ +include_guard(GLOBAL) +message("utilities_misc_utilities component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_sbrk.c +) + + diff --git a/devices/MIMX8MQ6/utilities/utility_assert_MIMX8MQ6.cmake b/devices/MIMX8MQ6/utilities/utility_assert_MIMX8MQ6.cmake new file mode 100644 index 000000000..b2b9ca641 --- /dev/null +++ b/devices/MIMX8MQ6/utilities/utility_assert_MIMX8MQ6.cmake @@ -0,0 +1,10 @@ +include_guard(GLOBAL) +message("utility_assert component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_assert.c +) + + +include(utility_debug_console_MIMX8MQ6) + diff --git a/devices/MIMX8MQ6/utilities/utility_debug_console_MIMX8MQ6.cmake b/devices/MIMX8MQ6/utilities/utility_debug_console_MIMX8MQ6.cmake new file mode 100644 index 000000000..1dd484fd2 --- /dev/null +++ b/devices/MIMX8MQ6/utilities/utility_debug_console_MIMX8MQ6.cmake @@ -0,0 +1,19 @@ +include_guard(GLOBAL) +message("utility_debug_console component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/str/fsl_str.c + ${CMAKE_CURRENT_LIST_DIR}/debug_console/fsl_debug_console.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/str + ${CMAKE_CURRENT_LIST_DIR}/debug_console +) + + +include(component_serial_manager_MIMX8MQ6) + +include(driver_common_MIMX8MQ6) + diff --git a/docs/Getting Started with MCUXpresso SDK for EVK-MIMX8MQ.pdf b/docs/Getting Started with MCUXpresso SDK for EVK-MIMX8MQ.pdf new file mode 100644 index 000000000..d073c1bbd Binary files /dev/null and b/docs/Getting Started with MCUXpresso SDK for EVK-MIMX8MQ.pdf differ diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6.pdf b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6.pdf new file mode 100644 index 000000000..e586e7bc5 Binary files /dev/null and b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6.pdf differ diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/Kinetis_SDK_Block_Diagram.jpg b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/Kinetis_SDK_Block_Diagram.jpg new file mode 100644 index 000000000..ac7abd7b2 Binary files /dev/null and b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/Kinetis_SDK_Block_Diagram.jpg differ diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00002.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00002.html new file mode 100644 index 000000000..cd646408f --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00002.html @@ -0,0 +1,130 @@ + + + + + + +MCUXpresso SDK API Reference Manual: Trademarks + + + + + + + + + + + + + + +
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+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00004.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00004.html new file mode 100644 index 000000000..233c42869 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00004.html @@ -0,0 +1,159 @@ + + + + + + +MCUXpresso SDK API Reference Manual: Architectural Overview + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Architectural Overview
+
+
+

This chapter provides the architectural overview for the MCUXpresso Software Development Kit (MCUXpresso SDK). It describes each layer within the architecture and its associated components.

+

Overview

+

The MCUXpresso SDK architecture consists of five key components listed below.

+
    +
  1. +The Arm Cortex Microcontroller Software Interface Standard (CMSIS) CORE compliance device-specific header files, SOC Header, and CMSIS math/DSP libraries.
    2. +
  2. +Peripheral Drivers
    3. +
  3. +Real-time Operating Systems (RTOS)
    4. +
  4. +Stacks and Middleware that integrate with the MCUXpresso SDK
    5. +
  5. +Demo Applications based on the MCUXpresso SDK
    6. +
+
+Kinetis_SDK_Block_Diagram.jpg +
+MCUXpresso SDK Block Diagram
+

MCU header files

+

Each supported MCU device in the MCUXpresso SDK has an overall System-on Chip (SoC) memory-mapped header file. This header file contains the memory map and register base address for each peripheral and the IRQ vector table with associated vector numbers. The overall SoC header file provides access to the peripheral registers through pointers and predefined bit masks. In addition to the overall SoC memory-mapped header file, the MCUXpresso SDK includes a feature header file for each device. The feature header file allows NXP to deliver a single software driver for a given peripheral. The feature file ensures that the driver is properly compiled for the target SOC.

+

CMSIS Support

+

Along with the SoC header files and peripheral extension header files, the MCUXpresso SDK also includes common CMSIS header files for the Arm Cortex-M core and the math and DSP libraries from the latest CMSIS release. The CMSIS DSP library source code is also included for reference.

+

MCUXpresso SDK Peripheral Drivers

+

The MCUXpresso SDK peripheral drivers mainly consist of low-level functional APIs for the MCU product family on-chip peripherals and also of high-level transactional APIs for some bus drivers/DMA driver/eDMA driver to quickly enable the peripherals and perform transfers.

+

All MCUXpresso SDK peripheral drivers only depend on the CMSIS headers, device feature files, fsl_common.h, and fsl_clock.h files so that users can easily pull selected drivers and their dependencies into projects. With the exception of the clock/power-relevant peripherals, each peripheral has its own driver. Peripheral drivers handle the peripheral clock gating/ungating inside the drivers during initialization and deinitialization respectively.

+

Low-level functional APIs provide common peripheral functionality, abstracting the hardware peripheral register accesses into a set of stateless basic functional operations. These APIs primarily focus on the control, configuration, and function of basic peripheral operations. The APIs hide the register access details and various MCU peripheral instantiation differences so that the application can be abstracted from the low-level hardware details. The API prototypes are intentionally similar to help ensure easy portability across supported MCUXpresso SDK devices.

+

Transactional APIs provide a quick method for customers to utilize higher-level functionality of the peripherals. The transactional APIs utilize interrupts and perform asynchronous operations without user intervention. Transactional APIs operate on high-level logic that requires data storage for internal operation context handling. However, the Peripheral Drivers do not allocate this memory space. Rather, the user passes in the memory to the driver for internal driver operation. Transactional APIs ensure the NVIC is enabled properly inside the drivers. The transactional APIs do not meet all customer needs, but provide a baseline for development of custom user APIs.

+

Note that the transactional drivers never disable an NVIC after use. This is due to the shared nature of interrupt vectors on devices. It is up to the user to ensure that NVIC interrupts are properly disabled after usage is complete.

+

Interrupt handling for transactional APIs

+

A double weak mechanism is introduced for drivers with transactional API. The double weak indicates two levels of weak vector entries. See the examples below:

+
PUBWEAK SPI0_IRQHandler
+
PUBWEAK SPI0_DriverIRQHandler
+
SPI0_IRQHandler
+
LDR R0, =SPI0_DriverIRQHandler
+
BX R0
+

The first level of the weak implementation are the functions defined in the vector table. In the devices/<DEVICE_NAME>/<TOOLCHAIN>/startup_<DEVICE_NAME>.s/.S file, the implementation of the first layer weak function calls the second layer of weak function. The implementation of the second layer weak function (ex. SPI0_DriverIRQHandler) jumps to itself (B). The MCUXpresso SDK drivers with transactional APIs provide the reimplementation of the second layer function inside of the peripheral driver. If the MCUXpresso SDK drivers with transactional APIs are linked into the image, the SPI0_DriverIRQHandler is replaced with the function implemented in the MCUXpresso SDK SPI driver.

+

The reason for implementing the double weak functions is to provide a better user experience when using the transactional APIs. For drivers with a transactional function, call the transactional APIs and the drivers complete the interrupt-driven flow. Users are not required to redefine the vector entries out of the box. At the same time, if users are not satisfied by the second layer weak function implemented in the MCUXpresso SDK drivers, users can redefine the first layer weak function and implement their own interrupt handler functions to suit their implementation.

+

The limitation of the double weak mechanism is that it cannot be used for peripherals that share the same vector entry. For this use case, redefine the first layer weak function to enable the desired peripheral interrupt functionality. For example, if the MCU’s UART0 and UART1 share the same vector entry, redefine the UART0_UART1_IRQHandler according to the use case requirements.

+

Feature Header Files

+

The peripheral drivers are designed to be reusable regardless of the peripheral functional differences from one MCU device to another. An overall Peripheral Feature Header File is provided for the MCUXpresso SDK-supported MCU device to define the features or configuration differences for each sub-family device.

+

Application

+

See the Getting Started with MCUXpresso SDK document (MCUXSDKGSUG).

+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00006.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00006.html new file mode 100644 index 000000000..bda4da44b --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00006.html @@ -0,0 +1,153 @@ + + + + + + +MCUXpresso SDK API Reference Manual: Driver errors status + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Driver errors status
+
+
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00008.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00008.html new file mode 100644 index 000000000..281e218f3 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00008.html @@ -0,0 +1,4092 @@ + + + + + + +MCUXpresso SDK API Reference Manual: Clock Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Macros | +Enumerations
+
+
Clock Driver
+
+
+

Overview

+

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

+

The clock driver supports:

+
    +
  • Clock generator (PLL, FLL, and so on) configuration
    • +
  • Clock mux and divider configuration
    • +
  • Getting clock frequency
    • +
+ + + + + + + + + + + +

+Data Structures

struct  osc_config_t
 OSC configuration structure. More...
 
struct  ccm_analog_frac_pll_config_t
 Fractional-N PLL configuration. More...
 
struct  ccm_analog_sscg_pll_config_t
 SSCG PLL configuration. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define OSC25M_CLK_FREQ   25000000U
 XTAL 25M clock frequency.
 
+#define OSC27M_CLK_FREQ   27000000U
 XTAL 27M clock frequency.
 
+#define HDMI_PHY_27M_FREQ   27000000U
 HDMI PHY 27M clock frequency.
 
+#define CLKPN_FREQ   0U
 clock1PN frequency.
 
#define ECSPI_CLOCKS
 Clock ip name array for ECSPI. More...
 
#define GPIO_CLOCKS
 Clock ip name array for GPIO. More...
 
#define GPT_CLOCKS
 Clock ip name array for GPT. More...
 
#define I2C_CLOCKS
 Clock ip name array for I2C. More...
 
#define IOMUX_CLOCKS
 Clock ip name array for IOMUX. More...
 
#define IPMUX_CLOCKS
 Clock ip name array for IPMUX. More...
 
#define PWM_CLOCKS
 Clock ip name array for PWM. More...
 
#define RDC_CLOCKS
 Clock ip name array for RDC. More...
 
#define SAI_CLOCKS
 Clock ip name array for SAI. More...
 
#define RDC_SEMA42_CLOCKS
 Clock ip name array for RDC SEMA42. More...
 
#define UART_CLOCKS
 Clock ip name array for UART. More...
 
#define USDHC_CLOCKS
 Clock ip name array for USDHC. More...
 
#define WDOG_CLOCKS
 Clock ip name array for WDOG. More...
 
#define TMU_CLOCKS
 Clock ip name array for TEMPSENSOR. More...
 
#define SDMA_CLOCKS
 Clock ip name array for SDMA. More...
 
#define MU_CLOCKS
 Clock ip name array for MU. More...
 
#define QSPI_CLOCKS
 Clock ip name array for QSPI. More...
 
+#define CCM_BIT_FIELD_EXTRACTION(val, mask, shift)   (((val) & (mask)) >> (shift))
 CCM reg macros to extract corresponding registers bit field.
 
+#define CCM_REG_OFF(root, off)   (*((volatile uint32_t *)((uint32_t)(root) + (off))))
 CCM reg macros to map corresponding registers.
 
+#define AUDIO_PLL1_CFG0_OFFSET   0x00
 CCM Analog registers offset.
 
+#define CCM_ANALOG_TUPLE(reg, shift)   ((((reg)&0xFFFFU) << 16U) | (shift))
 CCM ANALOG tuple macros to map corresponding registers and bit fields.
 
+#define CCM_TUPLE(ccgr, root)   ((ccgr) << 16U | (root))
 CCM CCGR and root tuple.
 
#define kCLOCK_CoreSysClk   kCLOCK_CoreM4Clk
 For compatible with other platforms without CCM. More...
 
#define CLOCK_GetCoreSysClkFreq   CLOCK_GetCoreM4Freq
 For compatible with other platforms without CCM. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Enumerations

enum  clock_name_t {
+  kCLOCK_CoreM4Clk, +
+  kCLOCK_AxiClk, +
+  kCLOCK_AhbClk, +
+  kCLOCK_IpgClk +
+ }
 Clock name used to get clock frequency. More...
 
enum  clock_ip_name_t { ,
+  kCLOCK_Debug = CCM_TUPLE(4U, 32U), +
+  kCLOCK_Dram = CCM_TUPLE(5U, 64U), +
+  kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), +
+  kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), +
+  kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), +
+  kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), +
+  kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), +
+  kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), +
+  kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), +
+  kCLOCK_Gpio5 = CCM_TUPLE(15U, 33U), +
+  kCLOCK_Gpt1 = CCM_TUPLE(16U, 107U), +
+  kCLOCK_Gpt2 = CCM_TUPLE(17U, 108U), +
+  kCLOCK_Gpt3 = CCM_TUPLE(18U, 109U), +
+  kCLOCK_Gpt4 = CCM_TUPLE(19U, 110U), +
+  kCLOCK_Gpt5 = CCM_TUPLE(20U, 111U), +
+  kCLOCK_Gpt6 = CCM_TUPLE(21U, 112U), +
+  kCLOCK_I2c1 = CCM_TUPLE(23U, 90U), +
+  kCLOCK_I2c2 = CCM_TUPLE(24U, 91U), +
+  kCLOCK_I2c3 = CCM_TUPLE(25U, 92U), +
+  kCLOCK_I2c4 = CCM_TUPLE(26U, 93U), +
+  kCLOCK_Iomux = CCM_TUPLE(27U, 33U), +
+  kCLOCK_Ipmux1 = CCM_TUPLE(28U, 33U), +
+  kCLOCK_Ipmux2 = CCM_TUPLE(29U, 33U), +
+  kCLOCK_Ipmux3 = CCM_TUPLE(30U, 33U), +
+  kCLOCK_Ipmux4 = CCM_TUPLE(31U, 33U), +
+  kCLOCK_M4 = CCM_TUPLE(32U, 1U), +
+  kCLOCK_Mu = CCM_TUPLE(33U, 33U), +
+  kCLOCK_Ocram = CCM_TUPLE(35U, 16U), +
+  kCLOCK_OcramS = CCM_TUPLE(36U, 32U), +
+  kCLOCK_Pwm1 = CCM_TUPLE(40U, 103U), +
+  kCLOCK_Pwm2 = CCM_TUPLE(41U, 104U), +
+  kCLOCK_Pwm3 = CCM_TUPLE(42U, 105U), +
+  kCLOCK_Pwm4 = CCM_TUPLE(43U, 106U), +
+  kCLOCK_Qspi = CCM_TUPLE(47U, 87U), +
+  kCLOCK_Rdc = CCM_TUPLE(49U, 33U), +
+  kCLOCK_Sai1 = CCM_TUPLE(51U, 75U), +
+  kCLOCK_Sai2 = CCM_TUPLE(52U, 76U), +
+  kCLOCK_Sai3 = CCM_TUPLE(53U, 77U), +
+  kCLOCK_Sai4 = CCM_TUPLE(54U, 78U), +
+  kCLOCK_Sai5 = CCM_TUPLE(55U, 79U), +
+  kCLOCK_Sai6 = CCM_TUPLE(56U, 80U), +
+  kCLOCK_Sdma1 = CCM_TUPLE(58U, 33U), +
+  kCLOCK_Sdma2 = CCM_TUPLE(59U, 35U), +
+  kCLOCK_Sec_Debug = CCM_TUPLE(60U, 33U), +
+  kCLOCK_Sema42_1 = CCM_TUPLE(61U, 33U), +
+  kCLOCK_Sema42_2 = CCM_TUPLE(62U, 33U), +
+  kCLOCK_Sim_display = CCM_TUPLE(63U, 16U), +
+  kCLOCK_Sim_m = CCM_TUPLE(65U, 32U), +
+  kCLOCK_Sim_main = CCM_TUPLE(66U, 16U), +
+  kCLOCK_Sim_s = CCM_TUPLE(67U, 32U), +
+  kCLOCK_Sim_wakeup = CCM_TUPLE(68U, 32U), +
+  kCLOCK_Uart1 = CCM_TUPLE(73U, 94U), +
+  kCLOCK_Uart2 = CCM_TUPLE(74U, 95U), +
+  kCLOCK_Uart3 = CCM_TUPLE(75U, 96U), +
+  kCLOCK_Uart4 = CCM_TUPLE(76U, 97U), +
+  kCLOCK_Wdog1 = CCM_TUPLE(83U, 114U), +
+  kCLOCK_Wdog2 = CCM_TUPLE(84U, 114U), +
+  kCLOCK_Wdog3 = CCM_TUPLE(85U, 114U), +
+  kCLOCK_TempSensor = CCM_TUPLE(98U, 0xFFFF) +
+ }
 CCM CCGR gate control. More...
 
enum  clock_root_control_t {
+  kCLOCK_RootM4 = (uint32_t)(&(CCM)->ROOT[1].TARGET_ROOT), +
+  kCLOCK_RootAxi = (uint32_t)(&(CCM)->ROOT[16].TARGET_ROOT), +
+  kCLOCK_RootNoc = (uint32_t)(&(CCM)->ROOT[26].TARGET_ROOT), +
+  kCLOCK_RootAhb = (uint32_t)(&(CCM)->ROOT[32].TARGET_ROOT), +
+  kCLOCK_RootIpg = (uint32_t)(&(CCM)->ROOT[33].TARGET_ROOT), +
+  kCLOCK_RootDramAlt = (uint32_t)(&(CCM)->ROOT[64].TARGET_ROOT), +
+  kCLOCK_RootSai1 = (uint32_t)(&(CCM)->ROOT[75].TARGET_ROOT), +
+  kCLOCK_RootSai2 = (uint32_t)(&(CCM)->ROOT[76].TARGET_ROOT), +
+  kCLOCK_RootSai3 = (uint32_t)(&(CCM)->ROOT[77].TARGET_ROOT), +
+  kCLOCK_RootSai4 = (uint32_t)(&(CCM)->ROOT[78].TARGET_ROOT), +
+  kCLOCK_RootSai5 = (uint32_t)(&(CCM)->ROOT[79].TARGET_ROOT), +
+  kCLOCK_RootSai6 = (uint32_t)(&(CCM)->ROOT[80].TARGET_ROOT), +
+  kCLOCK_RootQspi = (uint32_t)(&(CCM)->ROOT[87].TARGET_ROOT), +
+  kCLOCK_RootI2c1 = (uint32_t)(&(CCM)->ROOT[90].TARGET_ROOT), +
+  kCLOCK_RootI2c2 = (uint32_t)(&(CCM)->ROOT[91].TARGET_ROOT), +
+  kCLOCK_RootI2c3 = (uint32_t)(&(CCM)->ROOT[92].TARGET_ROOT), +
+  kCLOCK_RootI2c4 = (uint32_t)(&(CCM)->ROOT[93].TARGET_ROOT), +
+  kCLOCK_RootUart1 = (uint32_t)(&(CCM)->ROOT[94].TARGET_ROOT), +
+  kCLOCK_RootUart2 = (uint32_t)(&(CCM)->ROOT[95].TARGET_ROOT), +
+  kCLOCK_RootUart3 = (uint32_t)(&(CCM)->ROOT[96].TARGET_ROOT), +
+  kCLOCK_RootUart4 = (uint32_t)(&(CCM)->ROOT[97].TARGET_ROOT), +
+  kCLOCK_RootEcspi1 = (uint32_t)(&(CCM)->ROOT[101].TARGET_ROOT), +
+  kCLOCK_RootEcspi2 = (uint32_t)(&(CCM)->ROOT[102].TARGET_ROOT), +
+  kCLOCK_RootEcspi3 = (uint32_t)(&(CCM)->ROOT[131].TARGET_ROOT), +
+  kCLOCK_RootPwm1 = (uint32_t)(&(CCM)->ROOT[103].TARGET_ROOT), +
+  kCLOCK_RootPwm2 = (uint32_t)(&(CCM)->ROOT[104].TARGET_ROOT), +
+  kCLOCK_RootPwm3 = (uint32_t)(&(CCM)->ROOT[105].TARGET_ROOT), +
+  kCLOCK_RootPwm4 = (uint32_t)(&(CCM)->ROOT[106].TARGET_ROOT), +
+  kCLOCK_RootGpt1 = (uint32_t)(&(CCM)->ROOT[107].TARGET_ROOT), +
+  kCLOCK_RootGpt2 = (uint32_t)(&(CCM)->ROOT[108].TARGET_ROOT), +
+  kCLOCK_RootGpt3 = (uint32_t)(&(CCM)->ROOT[109].TARGET_ROOT), +
+  kCLOCK_RootGpt4 = (uint32_t)(&(CCM)->ROOT[110].TARGET_ROOT), +
+  kCLOCK_RootGpt5 = (uint32_t)(&(CCM)->ROOT[111].TARGET_ROOT), +
+  kCLOCK_RootGpt6 = (uint32_t)(&(CCM)->ROOT[112].TARGET_ROOT), +
+  kCLOCK_RootWdog = (uint32_t)(&(CCM)->ROOT[114].TARGET_ROOT) +
+ }
 ccm root name used to get clock frequency. More...
 
enum  clock_rootmux_m4_clk_sel_t {
+  kCLOCK_M4RootmuxOsc25m = 0U, +
+  kCLOCK_M4RootmuxSysPll2Div5 = 1U, +
+  kCLOCK_M4RootmuxSysPll2Div4 = 2U, +
+  kCLOCK_M4RootmuxSysPll1Div3 = 3U, +
+  kCLOCK_M4RootmuxSysPll1 = 4U, +
+  kCLOCK_M4RootmuxAudioPll1 = 5U, +
+  kCLOCK_M4RootmuxVideoPll1 = 6U, +
+  kCLOCK_M4RootmuxSysPll3 = 7U +
+ }
 Root clock select enumeration for ARM Cortex-M4 core. More...
 
enum  clock_rootmux_axi_clk_sel_t {
+  kCLOCK_AxiRootmuxOsc25m = 0U, +
+  kCLOCK_AxiRootmuxSysPll2Div3 = 1U, +
+  kCLOCK_AxiRootmuxSysPll1 = 2U, +
+  kCLOCK_AxiRootmuxSysPll2Div4 = 3U, +
+  kCLOCK_AxiRootmuxSysPll2 = 4U, +
+  kCLOCK_AxiRootmuxAudioPll1 = 5U, +
+  kCLOCK_AxiRootmuxVideoPll1 = 6U, +
+  kCLOCK_AxiRootmuxSysPll1Div8 = 7U +
+ }
 Root clock select enumeration for AXI bus. More...
 
enum  clock_rootmux_ahb_clk_sel_t {
+  kCLOCK_AhbRootmuxOsc25m = 0U, +
+  kCLOCK_AhbRootmuxSysPll1Div6 = 1U, +
+  kCLOCK_AhbRootmuxSysPll1 = 2U, +
+  kCLOCK_AhbRootmuxSysPll1Div2 = 3U, +
+  kCLOCK_AhbRootmuxSysPll2Div8 = 4U, +
+  kCLOCK_AhbRootmuxSysPll3 = 5U, +
+  kCLOCK_AhbRootmuxAudioPll1 = 6U, +
+  kCLOCK_AhbRootmuxVideoPll1 = 7U +
+ }
 Root clock select enumeration for AHB bus. More...
 
enum  clock_rootmux_qspi_clk_sel_t {
+  kCLOCK_QspiRootmuxOsc25m = 0U, +
+  kCLOCK_QspiRootmuxSysPll1Div2 = 1U, +
+  kCLOCK_QspiRootmuxSysPll1 = 2U, +
+  kCLOCK_QspiRootmuxSysPll2Div2 = 3U, +
+  kCLOCK_QspiRootmuxAudioPll2 = 4, +
+  kCLOCK_QspiRootmuxSysPll1Div3 = 5U, +
+  kCLOCK_QspiRootmuxSysPll3 = 6U, +
+  kCLOCK_QspiRootmuxSysPll1Div8 = 7U +
+ }
 Root clock select enumeration for QSPI peripheral. More...
 
enum  clock_rootmux_ecspi_clk_sel_t {
+  kCLOCK_EcspiRootmuxOsc25m = 0U, +
+  kCLOCK_EcspiRootmuxSysPll2Div5 = 1U, +
+  kCLOCK_EcspiRootmuxSysPll1Div20 = 2U, +
+  kCLOCK_EcspiRootmuxSysPll1Div5 = 3U, +
+  kCLOCK_EcspiRootmuxSysPll1 = 4U, +
+  kCLOCK_EcspiRootmuxSysPll3 = 5U, +
+  kCLOCK_EcspiRootmuxSysPll2Div4 = 6U, +
+  kCLOCK_EcspiRootmuxAudioPll2 = 7U +
+ }
 Root clock select enumeration for ECSPI peripheral. More...
 
enum  clock_rootmux_i2c_clk_sel_t {
+  kCLOCK_I2cRootmuxOsc25m = 0U, +
+  kCLOCK_I2cRootmuxSysPll1Div5 = 1U, +
+  kCLOCK_I2cRootmuxSysPll2Div20 = 2U, +
+  kCLOCK_I2cRootmuxSysPll3 = 3U, +
+  kCLOCK_I2cRootmuxAudioPll1 = 4U, +
+  kCLOCK_I2cRootmuxVideoPll1 = 5U, +
+  kCLOCK_I2cRootmuxAudioPll2 = 6U, +
+  kCLOCK_I2cRootmuxSysPll1Div6 = 7U +
+ }
 Root clock select enumeration for I2C peripheral. More...
 
enum  clock_rootmux_uart_clk_sel_t {
+  kCLOCK_UartRootmuxOsc25m = 0U, +
+  kCLOCK_UartRootmuxSysPll1Div10 = 1U, +
+  kCLOCK_UartRootmuxSysPll2Div5 = 2U, +
+  kCLOCK_UartRootmuxSysPll2Div10 = 3U, +
+  kCLOCK_UartRootmuxSysPll3 = 4U, +
+  kCLOCK_UartRootmuxExtClk2 = 5U, +
+  kCLOCK_UartRootmuxExtClk34 = 6U, +
+  kCLOCK_UartRootmuxAudioPll2 = 7U +
+ }
 Root clock select enumeration for UART peripheral. More...
 
enum  clock_rootmux_gpt_t {
+  kCLOCK_GptRootmuxOsc25m = 0U, +
+  kCLOCK_GptRootmuxSystemPll2Div10 = 1U, +
+  kCLOCK_GptRootmuxSysPll1Div2 = 2U, +
+  kCLOCK_GptRootmuxSysPll1Div20 = 3U, +
+  kCLOCK_GptRootmuxVideoPll1 = 4U, +
+  kCLOCK_GptRootmuxSystemPll1Div10 = 5U, +
+  kCLOCK_GptRootmuxAudioPll1 = 6U, +
+  kCLOCK_GptRootmuxExtClk123 = 7U +
+ }
 Root clock select enumeration for GPT peripheral. More...
 
enum  clock_rootmux_wdog_clk_sel_t {
+  kCLOCK_WdogRootmuxOsc25m = 0U, +
+  kCLOCK_WdogRootmuxSysPll1Div6 = 1U, +
+  kCLOCK_WdogRootmuxSysPll1Div5 = 2U, +
+  kCLOCK_WdogRootmuxVpuPll = 3U, +
+  kCLOCK_WdogRootmuxSystemPll2Div8 = 4U, +
+  kCLOCK_WdogRootmuxSystemPll3 = 5U, +
+  kCLOCK_WdogRootmuxSystemPll1Div10 = 6U, +
+  kCLOCK_WdogRootmuxSystemPll2Div6 = 7U +
+ }
 Root clock select enumeration for WDOG peripheral. More...
 
enum  clock_rootmux_Pwm_clk_sel_t {
+  kCLOCK_PwmRootmuxOsc25m = 0U, +
+  kCLOCK_PwmRootmuxSysPll2Div10 = 1U, +
+  kCLOCK_PwmRootmuxSysPll1Div5 = 2U, +
+  kCLOCK_PwmRootmuxSysPll1Div20 = 3U, +
+  kCLOCK_PwmRootmuxSystemPll3 = 4U, +
+  kCLOCK_PwmRootmuxExtClk12 = 5U, +
+  kCLOCK_PwmRootmuxSystemPll1Div10 = 6U, +
+  kCLOCK_PwmRootmuxVideoPll1 = 7U +
+ }
 Root clock select enumeration for PWM peripheral. More...
 
enum  clock_rootmux_sai_clk_sel_t {
+  kCLOCK_SaiRootmuxOsc25m = 0U, +
+  kCLOCK_SaiRootmuxAudioPll1 = 1U, +
+  kCLOCK_SaiRootmuxAudioPll2 = 2U, +
+  kCLOCK_SaiRootmuxVideoPll1 = 3U, +
+  kCLOCK_SaiRootmuxSysPll1Div6 = 4U, +
+  kCLOCK_SaiRootmuxOsc27m = 5U, +
+  kCLOCK_SaiRootmuxExtClk123 = 6U, +
+  kCLOCK_SaiRootmuxExtClk234 = 7U +
+ }
 Root clock select enumeration for SAI peripheral. More...
 
enum  clock_rootmux_noc_clk_sel_t {
+  kCLOCK_NocRootmuxOsc25m = 0U, +
+  kCLOCK_NocRootmuxSysPll1 = 1U, +
+  kCLOCK_NocRootmuxSysPll3 = 2U, +
+  kCLOCK_NocRootmuxSysPll2 = 3U, +
+  kCLOCK_NocRootmuxSysPll2Div2 = 4U, +
+  kCLOCK_NocRootmuxAudioPll1 = 5U, +
+  kCLOCK_NocRootmuxVideoPll1 = 6U, +
+  kCLOCK_NocRootmuxAudioPll2 = 7U +
+ }
 Root clock select enumeration for NOC CLK. More...
 
enum  clock_pll_gate_t {
+  kCLOCK_ArmPllGate = (uint32_t)(&(CCM)->PLL_CTRL[12].PLL_CTRL), +
+  kCLOCK_GpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[13].PLL_CTRL), +
+  kCLOCK_VpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[14].PLL_CTRL), +
+  kCLOCK_DramPllGate = (uint32_t)(&(CCM)->PLL_CTRL[15].PLL_CTRL), +
+  kCLOCK_SysPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[16].PLL_CTRL), +
+  kCLOCK_SysPll1Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[17].PLL_CTRL), +
+  kCLOCK_SysPll1Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[18].PLL_CTRL), +
+  kCLOCK_SysPll1Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[19].PLL_CTRL), +
+  kCLOCK_SysPll1Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[20].PLL_CTRL), +
+  kCLOCK_SysPll1Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[21].PLL_CTRL), +
+  kCLOCK_SysPll1Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[22].PLL_CTRL), +
+  kCLOCK_SysPll1Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[23].PLL_CTRL), +
+  kCLOCK_SysPll1Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[24].PLL_CTRL), +
+  kCLOCK_SysPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[25].PLL_CTRL), +
+  kCLOCK_SysPll2Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[26].PLL_CTRL), +
+  kCLOCK_SysPll2Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[27].PLL_CTRL), +
+  kCLOCK_SysPll2Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[28].PLL_CTRL), +
+  kCLOCK_SysPll2Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[29].PLL_CTRL), +
+  kCLOCK_SysPll2Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[30].PLL_CTRL), +
+  kCLOCK_SysPll2Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[31].PLL_CTRL), +
+  kCLOCK_SysPll2Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[32].PLL_CTRL), +
+  kCLOCK_SysPll2Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[33].PLL_CTRL), +
+  kCLOCK_SysPll3Gate = (uint32_t)(&(CCM)->PLL_CTRL[34].PLL_CTRL), +
+  kCLOCK_AudioPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[35].PLL_CTRL), +
+  kCLOCK_AudioPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[36].PLL_CTRL), +
+  kCLOCK_VideoPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[37].PLL_CTRL), +
+  kCLOCK_VideoPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[38].PLL_CTRL) +
+ }
 CCM PLL gate control. More...
 
enum  clock_gate_value_t {
+  kCLOCK_ClockNotNeeded = 0x0U, +
+  kCLOCK_ClockNeededRun = 0x1111U, +
+  kCLOCK_ClockNeededRunWait = 0x2222U, +
+  kCLOCK_ClockNeededAll = 0x3333U +
+ }
 CCM gate control value. More...
 
enum  clock_pll_bypass_ctrl_t {
+  kCLOCK_AudioPll1BypassCtrl, +
+  kCLOCK_AudioPll2BypassCtrl, +
+  kCLOCK_VideoPll1BypassCtrl, +
+  kCLOCK_GpuPLLPwrBypassCtrl, +
+  kCLOCK_VpuPllPwrBypassCtrl, +
+  kCLOCK_ArmPllPwrBypassCtrl, +
+  kCLOCK_SysPll1InternalPll1BypassCtrl, +
+  kCLOCK_SysPll1InternalPll2BypassCtrl, +
+  kCLOCK_SysPll2InternalPll1BypassCtrl, +
+  kCLOCK_SysPll2InternalPll2BypassCtrl, +
+  kCLOCK_SysPll3InternalPll1BypassCtrl, +
+  kCLOCK_SysPll3InternalPll2BypassCtrl, +
+  kCLOCK_VideoPll2InternalPll1BypassCtrl, +
+  kCLOCK_VideoPll2InternalPll2BypassCtrl, +
+  kCLOCK_DramPllInternalPll1BypassCtrl, +
+  kCLOCK_DramPllInternalPll2BypassCtrl +
+ }
 PLL control names for PLL bypass. More...
 
enum  clock_pll_clke_t {
+  kCLOCK_AudioPll1Clke, +
+  kCLOCK_AudioPll2Clke, +
+  kCLOCK_VideoPll1Clke, +
+  kCLOCK_GpuPllClke, +
+  kCLOCK_VpuPllClke, +
+  kCLOCK_ArmPllClke, +
+  kCLOCK_SystemPll1Clke, +
+  kCLOCK_SystemPll1Div2Clke, +
+  kCLOCK_SystemPll1Div3Clke, +
+  kCLOCK_SystemPll1Div4Clke, +
+  kCLOCK_SystemPll1Div5Clke, +
+  kCLOCK_SystemPll1Div6Clke, +
+  kCLOCK_SystemPll1Div8Clke, +
+  kCLOCK_SystemPll1Div10Clke, +
+  kCLOCK_SystemPll1Div20Clke, +
+  kCLOCK_SystemPll2Clke, +
+  kCLOCK_SystemPll2Div2Clke, +
+  kCLOCK_SystemPll2Div3Clke, +
+  kCLOCK_SystemPll2Div4Clke, +
+  kCLOCK_SystemPll2Div5Clke, +
+  kCLOCK_SystemPll2Div6Clke, +
+  kCLOCK_SystemPll2Div8Clke, +
+  kCLOCK_SystemPll2Div10Clke, +
+  kCLOCK_SystemPll2Div20Clke, +
+  kCLOCK_SystemPll3Clke, +
+  kCLOCK_VideoPll2Clke, +
+  kCLOCK_DramPllClke, +
+  kCLOCK_OSC25MClke, +
+  kCLOCK_OSC27MClke +
+ }
 PLL clock names for clock enable/disable settings. More...
 
enum  clock_pll_ctrl_t
 ANALOG Power down override control.
 
enum  _osc_mode {
+  kOSC_OscMode = 0U, +
+  kOSC_ExtMode = 1U +
+ }
 OSC work mode. More...
 
enum  osc32_src_t {
+  kOSC32_Src25MDiv800 = 0U, +
+  kOSC32_SrcRTC +
+ }
 OSC 32K input select. More...
 
enum  _ccm_analog_pll_ref_clk {
+  kANALOG_PllRefOsc25M = 0U, +
+  kANALOG_PllRefOsc27M = 1U, +
+  kANALOG_PllRefOscHdmiPhy27M = 2U, +
+  kANALOG_PllRefClkPN = 3U +
+ }
 PLL reference clock select. More...
 
+ + + + +

+Driver version

#define FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 3, 3))
 CLOCK driver version 2.3.3. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+CCM Root Clock Setting

static void CLOCK_SetRootMux (clock_root_control_t rootClk, uint32_t mux)
 Set clock root mux. More...
 
static uint32_t CLOCK_GetRootMux (clock_root_control_t rootClk)
 Get clock root mux. More...
 
static void CLOCK_EnableRoot (clock_root_control_t rootClk)
 Enable clock root. More...
 
static void CLOCK_DisableRoot (clock_root_control_t rootClk)
 Disable clock root. More...
 
static bool CLOCK_IsRootEnabled (clock_root_control_t rootClk)
 Check whether clock root is enabled. More...
 
void CLOCK_UpdateRoot (clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post)
 Update clock root in one step, for dynamical clock switching Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value. More...
 
void CLOCK_SetRootDivider (clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post)
 Set root clock divider Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value. More...
 
static uint32_t CLOCK_GetRootPreDivider (clock_root_control_t rootClk)
 Get clock root PRE_PODF. More...
 
static uint32_t CLOCK_GetRootPostDivider (clock_root_control_t rootClk)
 Get clock root POST_PODF. More...
 
+ + + + + + + + + + + + + + + + +

+OSC setting

void CLOCK_InitOSC25M (const osc_config_t *config)
 OSC25M init. More...
 
void CLOCK_DeinitOSC25M (void)
 OSC25M deinit. More...
 
void CLOCK_InitOSC27M (const osc_config_t *config)
 OSC27M init. More...
 
void CLOCK_DeinitOSC27M (void)
 OSC27M deinit. More...
 
static void CLOCK_SwitchOSC32Src (osc32_src_t sel)
 switch 32KHZ OSC input More...
 
+ + + + + + + + + + +

+CCM Gate Control

static void CLOCK_ControlGate (uint32_t ccmGate, clock_gate_value_t control)
 Set PLL or CCGR gate control. More...
 
void CLOCK_EnableClock (clock_ip_name_t ccmGate)
 Enable CCGR clock gate and root clock gate for each module User should set specific gate for each module according to the description of the table of system clocks, gating and override in CCM chapter of reference manual. More...
 
void CLOCK_DisableClock (clock_ip_name_t ccmGate)
 Disable CCGR clock gate for the each module User should set specific gate for each module according to the description of the table of system clocks, gating and override in CCM chapter of reference manual. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+CCM Analog PLL Operatoin Functions

static void CLOCK_PowerUpPll (CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
 Power up PLL. More...
 
static void CLOCK_PowerDownPll (CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
 Power down PLL. More...
 
static void CLOCK_SetPllBypass (CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl, bool bypass)
 PLL bypass setting. More...
 
static bool CLOCK_IsPllBypassed (CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl)
 Check if PLL is bypassed. More...
 
static bool CLOCK_IsPllLocked (CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
 Check if PLL clock is locked. More...
 
static void CLOCK_EnableAnalogClock (CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
 Enable PLL clock. More...
 
static void CLOCK_DisableAnalogClock (CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
 Disable PLL clock. More...
 
static void CLOCK_OverrideAnalogClke (CCM_ANALOG_Type *base, clock_pll_clke_t ovClock, bool override)
 Override PLL clock output enable. More...
 
static void CLOCK_OverridePllPd (CCM_ANALOG_Type *base, clock_pll_ctrl_t pdClock, bool override)
 Override PLL power down. More...
 
void CLOCK_InitArmPll (const ccm_analog_frac_pll_config_t *config)
 Initializes the ANALOG ARM PLL. More...
 
+void CLOCK_DeinitArmPll (void)
 De-initialize the ARM PLL.
 
void CLOCK_InitSysPll1 (const ccm_analog_sscg_pll_config_t *config)
 Initializes the ANALOG SYS PLL1. More...
 
+void CLOCK_DeinitSysPll1 (void)
 De-initialize the System PLL1.
 
void CLOCK_InitSysPll2 (const ccm_analog_sscg_pll_config_t *config)
 Initializes the ANALOG SYS PLL2. More...
 
+void CLOCK_DeinitSysPll2 (void)
 De-initialize the System PLL2.
 
void CLOCK_InitSysPll3 (const ccm_analog_sscg_pll_config_t *config)
 Initializes the ANALOG SYS PLL3. More...
 
+void CLOCK_DeinitSysPll3 (void)
 De-initialize the System PLL3.
 
void CLOCK_InitDramPll (const ccm_analog_sscg_pll_config_t *config)
 Initializes the ANALOG DDR PLL. More...
 
+void CLOCK_DeinitDramPll (void)
 De-initialize the Dram PLL.
 
void CLOCK_InitAudioPll1 (const ccm_analog_frac_pll_config_t *config)
 Initializes the ANALOG AUDIO PLL1. More...
 
+void CLOCK_DeinitAudioPll1 (void)
 De-initialize the Audio PLL1.
 
void CLOCK_InitAudioPll2 (const ccm_analog_frac_pll_config_t *config)
 Initializes the ANALOG AUDIO PLL2. More...
 
+void CLOCK_DeinitAudioPll2 (void)
 De-initialize the Audio PLL2.
 
void CLOCK_InitVideoPll1 (const ccm_analog_frac_pll_config_t *config)
 Initializes the ANALOG VIDEO PLL1. More...
 
+void CLOCK_DeinitVideoPll1 (void)
 De-initialize the Video PLL1.
 
void CLOCK_InitVideoPll2 (const ccm_analog_sscg_pll_config_t *config)
 Initializes the ANALOG VIDEO PLL2. More...
 
+void CLOCK_DeinitVideoPll2 (void)
 De-initialize the Video PLL2.
 
void CLOCK_InitSSCGPll (CCM_ANALOG_Type *base, const ccm_analog_sscg_pll_config_t *config, clock_pll_ctrl_t type)
 Initializes the ANALOG SSCG PLL. More...
 
uint32_t CLOCK_GetSSCGPllFreq (CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass)
 Get the ANALOG SSCG PLL clock frequency. More...
 
void CLOCK_InitFracPll (CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type)
 Initializes the ANALOG Fractional PLL. More...
 
uint32_t CLOCK_GetFracPllFreq (CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq)
 Gets the ANALOG Fractional PLL clock frequency. More...
 
uint32_t CLOCK_GetPllFreq (clock_pll_ctrl_t pll)
 Gets PLL clock frequency. More...
 
uint32_t CLOCK_GetPllRefClkFreq (clock_pll_ctrl_t ctrl)
 Gets PLL reference clock frequency. More...
 
+ + + + + + + + + + + + + +

+CCM Get frequency

uint32_t CLOCK_GetFreq (clock_name_t clockName)
 Gets the clock frequency for a specific clock name. More...
 
uint32_t CLOCK_GetCoreM4Freq (void)
 Get the CCM Cortex M4 core frequency. More...
 
uint32_t CLOCK_GetAxiFreq (void)
 Get the CCM Axi bus frequency. More...
 
uint32_t CLOCK_GetAhbFreq (void)
 Get the CCM Ahb bus frequency. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct osc_config_t
+
+
+ + + + + + + +

Data Fields

+uint8_t oscMode
 ext or osc mode
 
+uint8_t oscDiv
 osc divider
 
+ +
+
+ +
+
+ + + + +
struct ccm_analog_frac_pll_config_t
+
+

Note: all the dividers in this configuration structure are the actually divider, software will map it to register value

+
+ + + + + + + + + + + + + +

Data Fields

+uint8_t refSel
 pll reference clock sel
 
+uint8_t refDiv
 A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ.
 
+uint32_t fractionDiv
 Inlcude fraction divider(divider:1:2^24) output clock range is 2000MHZ-4000MHZ.
 
+uint8_t outDiv
 output clock divide, output clock range is 30MHZ to 2000MHZ, must be a even value
 
+ +
+
+ +
+
+ + + + +
struct ccm_analog_sscg_pll_config_t
+
+

Note: all the dividers in this configuration structure are the actually divider, software will map it to register value

+
+ + + + + + + + + + + + + + + + + + + +

Data Fields

+uint8_t refSel
 pll reference clock sel
 
+uint8_t refDiv1
 A 3bit divider to make sure the REF must be within the range 25MHZ~235MHZ ,post_divide REF must be within the range 25MHZ~54MHZ.
 
+uint8_t refDiv2
 A 6bit divider to make sure the post_divide REF must be within the range 54MHZ~75MHZ.
 
+uint32_t loopDivider1
 A 6bit internal PLL1 feedback clock divider, output clock range must be within the range 1600MHZ-2400MHZ.
 
+uint32_t loopDivider2
 A 6bit internal PLL2 feedback clock divider, output clock range must be within the range 1200MHZ-2400MHZ.
 
+uint8_t outDiv
 A 6bit output clock divide, output clock range is 20MHZ to 1200MHZ.
 
+ +
+
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 3, 3))
+
+ +
+
+ +
+
+ + + + +
#define ECSPI_CLOCKS
+
+Value:
{ \
+
kCLOCK_IpInvalid, kCLOCK_Ecspi1, kCLOCK_Ecspi2, kCLOCK_Ecspi3, \
+
}
+
kCLOCK_Ecspi2
ECSPI2 Clock Gate.
Definition: fsl_clock.h:229
+
kCLOCK_Ecspi1
ECSPI1 Clock Gate.
Definition: fsl_clock.h:228
+
kCLOCK_Ecspi3
ECSPI3 Clock Gate.
Definition: fsl_clock.h:230
+
+
+
+ +
+
+ + + + +
#define GPIO_CLOCKS
+
+Value:
{ \
+
kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, \
+
}
+
kCLOCK_Gpio2
GPIO2 Clock Gate.
Definition: fsl_clock.h:233
+
kCLOCK_Gpio3
GPIO3 Clock Gate.
Definition: fsl_clock.h:234
+
kCLOCK_Gpio5
GPIO5 Clock Gate.
Definition: fsl_clock.h:236
+
kCLOCK_Gpio4
GPIO4 Clock Gate.
Definition: fsl_clock.h:235
+
kCLOCK_Gpio1
GPIO1 Clock Gate.
Definition: fsl_clock.h:232
+
+
+
+ +
+
+ + + + +
#define GPT_CLOCKS
+
+Value:
{ \
+
kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6, \
+
}
+
kCLOCK_Gpt4
GPT4 Clock Gate.
Definition: fsl_clock.h:241
+
kCLOCK_Gpt6
GPT6 Clock Gate.
Definition: fsl_clock.h:243
+
kCLOCK_Gpt3
GPT3 Clock Gate.
Definition: fsl_clock.h:240
+
kCLOCK_Gpt1
GPT1 Clock Gate.
Definition: fsl_clock.h:238
+
kCLOCK_Gpt5
GPT5 Clock Gate.
Definition: fsl_clock.h:242
+
kCLOCK_Gpt2
GPT2 Clock Gate.
Definition: fsl_clock.h:239
+
+
+
+ +
+
+ + + + +
#define I2C_CLOCKS
+
+Value:
{ \
+
kCLOCK_IpInvalid, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, \
+
}
+
kCLOCK_I2c2
I2C2 Clock Gate.
Definition: fsl_clock.h:246
+
kCLOCK_I2c1
I2C1 Clock Gate.
Definition: fsl_clock.h:245
+
kCLOCK_I2c4
I2C4 Clock Gate.
Definition: fsl_clock.h:248
+
kCLOCK_I2c3
I2C3 Clock Gate.
Definition: fsl_clock.h:247
+
+
+
+ +
+
+ + + + +
#define IOMUX_CLOCKS
+
+Value:
{ \
+
kCLOCK_Iomux, \
+
}
+
kCLOCK_Iomux
IOMUX Clock Gate.
Definition: fsl_clock.h:250
+
+
+
+ +
+
+ + + + +
#define IPMUX_CLOCKS
+
+Value:
{ \
+
kCLOCK_Ipmux1, kCLOCK_Ipmux2, kCLOCK_Ipmux3, kCLOCK_Ipmux4, \
+
}
+
kCLOCK_Ipmux3
IPMUX3 Clock Gate.
Definition: fsl_clock.h:253
+
kCLOCK_Ipmux2
IPMUX2 Clock Gate.
Definition: fsl_clock.h:252
+
kCLOCK_Ipmux4
IPMUX4 Clock Gate.
Definition: fsl_clock.h:254
+
kCLOCK_Ipmux1
IPMUX1 Clock Gate.
Definition: fsl_clock.h:251
+
+
+
+ +
+
+ + + + +
#define PWM_CLOCKS
+
+Value:
{ \
+
kCLOCK_IpInvalid, kCLOCK_Pwm1, kCLOCK_Pwm2, kCLOCK_Pwm3, kCLOCK_Pwm4, \
+
}
+
kCLOCK_Pwm4
PWM4 Clock Gate.
Definition: fsl_clock.h:266
+
kCLOCK_Pwm3
PWM3 Clock Gate.
Definition: fsl_clock.h:265
+
kCLOCK_Pwm2
PWM2 Clock Gate.
Definition: fsl_clock.h:264
+
kCLOCK_Pwm1
PWM1 Clock Gate.
Definition: fsl_clock.h:263
+
+
+
+ +
+
+ + + + +
#define RDC_CLOCKS
+
+Value:
{ \
+
kCLOCK_Rdc, \
+
}
+
kCLOCK_Rdc
RDC Clock Gate.
Definition: fsl_clock.h:270
+
+
+
+ +
+
+ + + + +
#define SAI_CLOCKS
+
+Value:
{ \
+
kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4, kCLOCK_Sai5, kCLOCK_Sai6, \
+
}
+
kCLOCK_Sai4
SAI4 Clock Gate.
Definition: fsl_clock.h:275
+
kCLOCK_Sai2
SAI2 Clock Gate.
Definition: fsl_clock.h:273
+
kCLOCK_Sai6
SAI6 Clock Gate.
Definition: fsl_clock.h:277
+
kCLOCK_Sai5
SAI5 Clock Gate.
Definition: fsl_clock.h:276
+
kCLOCK_Sai1
SAI1 Clock Gate.
Definition: fsl_clock.h:272
+
kCLOCK_Sai3
SAI3 Clock Gate.
Definition: fsl_clock.h:274
+
+
+
+ +
+
+ + + + +
#define RDC_SEMA42_CLOCKS
+
+Value:
{ \
+
kCLOCK_IpInvalid, kCLOCK_Sema42_1, kCLOCK_Sema42_2 \
+
}
+
kCLOCK_Sema42_1
RDC SEMA42 Clock Gate.
Definition: fsl_clock.h:284
+
kCLOCK_Sema42_2
RDC SEMA42 Clock Gate.
Definition: fsl_clock.h:285
+
+
+
+ +
+
+ + + + +
#define UART_CLOCKS
+
+Value:
{ \
+
kCLOCK_IpInvalid, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \
+
}
+
kCLOCK_Uart1
UART1 Clock Gate.
Definition: fsl_clock.h:293
+
kCLOCK_Uart4
UART4 Clock Gate.
Definition: fsl_clock.h:296
+
kCLOCK_Uart2
UART2 Clock Gate.
Definition: fsl_clock.h:294
+
kCLOCK_Uart3
UART3 Clock Gate.
Definition: fsl_clock.h:295
+
+
+
+ +
+
+ + + + +
#define USDHC_CLOCKS
+
+Value:
{ \
+
kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
+
}
+
+
+
+ +
+
+ + + + +
#define WDOG_CLOCKS
+
+Value:
{ \
+
kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3 \
+
}
+
kCLOCK_Wdog3
WDOG3 Clock Gate.
Definition: fsl_clock.h:300
+
kCLOCK_Wdog2
WDOG2 Clock Gate.
Definition: fsl_clock.h:299
+
kCLOCK_Wdog1
WDOG1 Clock Gate.
Definition: fsl_clock.h:298
+
+
+
+ +
+
+ + + + +
#define TMU_CLOCKS
+
+Value:
{ \
+
kCLOCK_TempSensor, \
+
}
+
kCLOCK_TempSensor
TempSensor Clock Gate.
Definition: fsl_clock.h:302
+
+
+
+ +
+
+ + + + +
#define SDMA_CLOCKS
+
+Value:
{ \
+
kCLOCK_Sdma1, kCLOCK_Sdma2 \
+
}
+
kCLOCK_Sdma1
SDMA1 Clock Gate.
Definition: fsl_clock.h:279
+
kCLOCK_Sdma2
SDMA2 Clock Gate.
Definition: fsl_clock.h:280
+
+
+
+ +
+
+ + + + +
#define MU_CLOCKS
+
+Value:
{ \
+
kCLOCK_Mu \
+
}
+
kCLOCK_Mu
MU Clock Gate.
Definition: fsl_clock.h:258
+
+
+
+ +
+
+ + + + +
#define QSPI_CLOCKS
+
+Value:
{ \
+
kCLOCK_Qspi \
+
}
+
kCLOCK_Qspi
QSPI Clock Gate.
Definition: fsl_clock.h:268
+
+
+
+ +
+
+ + + + +
#define kCLOCK_CoreSysClk   kCLOCK_CoreM4Clk
+
+ +
+
+ +
+
+ + + + +
#define CLOCK_GetCoreSysClkFreq   CLOCK_GetCoreM4Freq
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum clock_name_t
+
+ + + + + +
Enumerator
kCLOCK_CoreM4Clk  +

ARM M4 Core clock.

+
kCLOCK_AxiClk  +

Main AXI bus clock.

+
kCLOCK_AhbClk  +

AHB bus clock.

+
kCLOCK_IpgClk  +

IPG bus clock.

+
+ +
+
+ +
+
+ + + + +
enum clock_ip_name_t
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enumerator
kCLOCK_Debug  +

DEBUG Clock Gate.

+
kCLOCK_Dram  +

DRAM Clock Gate.

+
kCLOCK_Ecspi1  +

ECSPI1 Clock Gate.

+
kCLOCK_Ecspi2  +

ECSPI2 Clock Gate.

+
kCLOCK_Ecspi3  +

ECSPI3 Clock Gate.

+
kCLOCK_Gpio1  +

GPIO1 Clock Gate.

+
kCLOCK_Gpio2  +

GPIO2 Clock Gate.

+
kCLOCK_Gpio3  +

GPIO3 Clock Gate.

+
kCLOCK_Gpio4  +

GPIO4 Clock Gate.

+
kCLOCK_Gpio5  +

GPIO5 Clock Gate.

+
kCLOCK_Gpt1  +

GPT1 Clock Gate.

+
kCLOCK_Gpt2  +

GPT2 Clock Gate.

+
kCLOCK_Gpt3  +

GPT3 Clock Gate.

+
kCLOCK_Gpt4  +

GPT4 Clock Gate.

+
kCLOCK_Gpt5  +

GPT5 Clock Gate.

+
kCLOCK_Gpt6  +

GPT6 Clock Gate.

+
kCLOCK_I2c1  +

I2C1 Clock Gate.

+
kCLOCK_I2c2  +

I2C2 Clock Gate.

+
kCLOCK_I2c3  +

I2C3 Clock Gate.

+
kCLOCK_I2c4  +

I2C4 Clock Gate.

+
kCLOCK_Iomux  +

IOMUX Clock Gate.

+
kCLOCK_Ipmux1  +

IPMUX1 Clock Gate.

+
kCLOCK_Ipmux2  +

IPMUX2 Clock Gate.

+
kCLOCK_Ipmux3  +

IPMUX3 Clock Gate.

+
kCLOCK_Ipmux4  +

IPMUX4 Clock Gate.

+
kCLOCK_M4  +

M4 Clock Gate.

+
kCLOCK_Mu  +

MU Clock Gate.

+
kCLOCK_Ocram  +

OCRAM Clock Gate.

+
kCLOCK_OcramS  +

OCRAM S Clock Gate.

+
kCLOCK_Pwm1  +

PWM1 Clock Gate.

+
kCLOCK_Pwm2  +

PWM2 Clock Gate.

+
kCLOCK_Pwm3  +

PWM3 Clock Gate.

+
kCLOCK_Pwm4  +

PWM4 Clock Gate.

+
kCLOCK_Qspi  +

QSPI Clock Gate.

+
kCLOCK_Rdc  +

RDC Clock Gate.

+
kCLOCK_Sai1  +

SAI1 Clock Gate.

+
kCLOCK_Sai2  +

SAI2 Clock Gate.

+
kCLOCK_Sai3  +

SAI3 Clock Gate.

+
kCLOCK_Sai4  +

SAI4 Clock Gate.

+
kCLOCK_Sai5  +

SAI5 Clock Gate.

+
kCLOCK_Sai6  +

SAI6 Clock Gate.

+
kCLOCK_Sdma1  +

SDMA1 Clock Gate.

+
kCLOCK_Sdma2  +

SDMA2 Clock Gate.

+
kCLOCK_Sec_Debug  +

SEC_DEBUG Clock Gate.

+
kCLOCK_Sema42_1  +

RDC SEMA42 Clock Gate.

+
kCLOCK_Sema42_2  +

RDC SEMA42 Clock Gate.

+
kCLOCK_Sim_display  +

SIM_Display Clock Gate.

+
kCLOCK_Sim_m  +

SIM_M Clock Gate.

+
kCLOCK_Sim_main  +

SIM_MAIN Clock Gate.

+
kCLOCK_Sim_s  +

SIM_S Clock Gate.

+
kCLOCK_Sim_wakeup  +

SIM_WAKEUP Clock Gate.

+
kCLOCK_Uart1  +

UART1 Clock Gate.

+
kCLOCK_Uart2  +

UART2 Clock Gate.

+
kCLOCK_Uart3  +

UART3 Clock Gate.

+
kCLOCK_Uart4  +

UART4 Clock Gate.

+
kCLOCK_Wdog1  +

WDOG1 Clock Gate.

+
kCLOCK_Wdog2  +

WDOG2 Clock Gate.

+
kCLOCK_Wdog3  +

WDOG3 Clock Gate.

+
kCLOCK_TempSensor  +

TempSensor Clock Gate.

+
+ +
+
+ +
+
+ + + + +
enum clock_root_control_t
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enumerator
kCLOCK_RootM4  +

ARM Cortex-M4 Clock control name.

+
kCLOCK_RootAxi  +

AXI Clock control name.

+
kCLOCK_RootNoc  +

NOC Clock control name.

+
kCLOCK_RootAhb  +

AHB Clock control name.

+
kCLOCK_RootIpg  +

IPG Clock control name.

+
kCLOCK_RootDramAlt  +

DRAM ALT Clock control name.

+
kCLOCK_RootSai1  +

SAI1 Clock control name.

+
kCLOCK_RootSai2  +

SAI2 Clock control name.

+
kCLOCK_RootSai3  +

SAI3 Clock control name.

+
kCLOCK_RootSai4  +

SAI4 Clock control name.

+
kCLOCK_RootSai5  +

SAI5 Clock control name.

+
kCLOCK_RootSai6  +

SAI6 Clock control name.

+
kCLOCK_RootQspi  +

QSPI Clock control name.

+
kCLOCK_RootI2c1  +

I2C1 Clock control name.

+
kCLOCK_RootI2c2  +

I2C2 Clock control name.

+
kCLOCK_RootI2c3  +

I2C3 Clock control name.

+
kCLOCK_RootI2c4  +

I2C4 Clock control name.

+
kCLOCK_RootUart1  +

UART1 Clock control name.

+
kCLOCK_RootUart2  +

UART2 Clock control name.

+
kCLOCK_RootUart3  +

UART3 Clock control name.

+
kCLOCK_RootUart4  +

UART4 Clock control name.

+
kCLOCK_RootEcspi1  +

ECSPI1 Clock control name.

+
kCLOCK_RootEcspi2  +

ECSPI2 Clock control name.

+
kCLOCK_RootEcspi3  +

ECSPI3 Clock control name.

+
kCLOCK_RootPwm1  +

PWM1 Clock control name.

+
kCLOCK_RootPwm2  +

PWM2 Clock control name.

+
kCLOCK_RootPwm3  +

PWM3 Clock control name.

+
kCLOCK_RootPwm4  +

PWM4 Clock control name.

+
kCLOCK_RootGpt1  +

GPT1 Clock control name.

+
kCLOCK_RootGpt2  +

GPT2 Clock control name.

+
kCLOCK_RootGpt3  +

GPT3 Clock control name.

+
kCLOCK_RootGpt4  +

GPT4 Clock control name.

+
kCLOCK_RootGpt5  +

GPT5 Clock control name.

+
kCLOCK_RootGpt6  +

GPT6 Clock control name.

+
kCLOCK_RootWdog  +

WDOG Clock control name.

+
+ +
+
+ +
+
+ + + + +
enum clock_rootmux_m4_clk_sel_t
+
+ + + + + + + + + +
Enumerator
kCLOCK_M4RootmuxOsc25m  +

ARM Cortex-M4 Clock from OSC 25M.

+
kCLOCK_M4RootmuxSysPll2Div5  +

ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 5.

+
kCLOCK_M4RootmuxSysPll2Div4  +

ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 4.

+
kCLOCK_M4RootmuxSysPll1Div3  +

ARM Cortex-M4 Clock from SYSTEM PLL1 divided by 3.

+
kCLOCK_M4RootmuxSysPll1  +

ARM Cortex-M4 Clock from SYSTEM PLL1.

+
kCLOCK_M4RootmuxAudioPll1  +

ARM Cortex-M4 Clock from AUDIO PLL1.

+
kCLOCK_M4RootmuxVideoPll1  +

ARM Cortex-M4 Clock from VIDEO PLL1.

+
kCLOCK_M4RootmuxSysPll3  +

ARM Cortex-M4 Clock from SYSTEM PLL3.

+
+ +
+
+ +
+
+ + + + +
enum clock_rootmux_axi_clk_sel_t
+
+ + + + + + + + + +
Enumerator
kCLOCK_AxiRootmuxOsc25m  +

ARM AXI Clock from OSC 25M.

+
kCLOCK_AxiRootmuxSysPll2Div3  +

ARM AXI Clock from SYSTEM PLL2 divided by 3.

+
kCLOCK_AxiRootmuxSysPll1  +

ARM AXI Clock from SYSTEM PLL1.

+
kCLOCK_AxiRootmuxSysPll2Div4  +

ARM AXI Clock from SYSTEM PLL2 divided by 4.

+
kCLOCK_AxiRootmuxSysPll2  +

ARM AXI Clock from SYSTEM PLL2.

+
kCLOCK_AxiRootmuxAudioPll1  +

ARM AXI Clock from AUDIO PLL1.

+
kCLOCK_AxiRootmuxVideoPll1  +

ARM AXI Clock from VIDEO PLL1.

+
kCLOCK_AxiRootmuxSysPll1Div8  +

ARM AXI Clock from SYSTEM PLL1 divided by 8.

+
+ +
+
+ +
+
+ + + + +
enum clock_rootmux_ahb_clk_sel_t
+
+ + + + + + + + + +
Enumerator
kCLOCK_AhbRootmuxOsc25m  +

ARM AHB Clock from OSC 25M.

+
kCLOCK_AhbRootmuxSysPll1Div6  +

ARM AHB Clock from SYSTEM PLL1 divided by 6.

+
kCLOCK_AhbRootmuxSysPll1  +

ARM AHB Clock from SYSTEM PLL1.

+
kCLOCK_AhbRootmuxSysPll1Div2  +

ARM AHB Clock from SYSTEM PLL1 divided by 2.

+
kCLOCK_AhbRootmuxSysPll2Div8  +

ARM AHB Clock from SYSTEM PLL2 divided by 8.

+
kCLOCK_AhbRootmuxSysPll3  +

ARM AHB Clock from SYSTEM PLL3.

+
kCLOCK_AhbRootmuxAudioPll1  +

ARM AHB Clock from AUDIO PLL1.

+
kCLOCK_AhbRootmuxVideoPll1  +

ARM AHB Clock from VIDEO PLL1.

+
+ +
+
+ +
+
+ + + + +
enum clock_rootmux_qspi_clk_sel_t
+
+ + + + + + + + + +
Enumerator
kCLOCK_QspiRootmuxOsc25m  +

ARM QSPI Clock from OSC 25M.

+
kCLOCK_QspiRootmuxSysPll1Div2  +

ARM QSPI Clock from SYSTEM PLL1 divided by 2.

+
kCLOCK_QspiRootmuxSysPll1  +

ARM QSPI Clock from SYSTEM PLL1.

+
kCLOCK_QspiRootmuxSysPll2Div2  +

ARM QSPI Clock from SYSTEM PLL2 divided by 2.

+
kCLOCK_QspiRootmuxAudioPll2  +

ARM QSPI Clock from AUDIO PLL2.

+
kCLOCK_QspiRootmuxSysPll1Div3  +

ARM QSPI Clock from SYSTEM PLL1 divided by 3.

+
kCLOCK_QspiRootmuxSysPll3  +

ARM QSPI Clock from SYSTEM PLL3.

+
kCLOCK_QspiRootmuxSysPll1Div8  +

ARM QSPI Clock from SYSTEM PLL1 divided by 8.

+
+ +
+
+ +
+
+ + + + +
enum clock_rootmux_ecspi_clk_sel_t
+
+ + + + + + + + + +
Enumerator
kCLOCK_EcspiRootmuxOsc25m  +

ECSPI Clock from OSC 25M.

+
kCLOCK_EcspiRootmuxSysPll2Div5  +

ECSPI Clock from SYSTEM PLL2 divided by 5.

+
kCLOCK_EcspiRootmuxSysPll1Div20  +

ECSPI Clock from SYSTEM PLL1 divided by 20.

+
kCLOCK_EcspiRootmuxSysPll1Div5  +

ECSPI Clock from SYSTEM PLL1 divided by 5.

+
kCLOCK_EcspiRootmuxSysPll1  +

ECSPI Clock from SYSTEM PLL1.

+
kCLOCK_EcspiRootmuxSysPll3  +

ECSPI Clock from SYSTEM PLL3.

+
kCLOCK_EcspiRootmuxSysPll2Div4  +

ECSPI Clock from SYSTEM PLL2 divided by 4.

+
kCLOCK_EcspiRootmuxAudioPll2  +

ECSPI Clock from AUDIO PLL2.

+
+ +
+
+ +
+
+ + + + +
enum clock_rootmux_i2c_clk_sel_t
+
+ + + + + + + + + +
Enumerator
kCLOCK_I2cRootmuxOsc25m  +

I2C Clock from OSC 25M.

+
kCLOCK_I2cRootmuxSysPll1Div5  +

I2C Clock from SYSTEM PLL1 divided by 5.

+
kCLOCK_I2cRootmuxSysPll2Div20  +

I2C Clock from SYSTEM PLL2 divided by 20.

+
kCLOCK_I2cRootmuxSysPll3  +

I2C Clock from SYSTEM PLL3 .

+
kCLOCK_I2cRootmuxAudioPll1  +

I2C Clock from AUDIO PLL1.

+
kCLOCK_I2cRootmuxVideoPll1  +

I2C Clock from VIDEO PLL1.

+
kCLOCK_I2cRootmuxAudioPll2  +

I2C Clock from AUDIO PLL2.

+
kCLOCK_I2cRootmuxSysPll1Div6  +

I2C Clock from SYSTEM PLL1 divided by 6.

+
+ +
+
+ +
+
+ + + + +
enum clock_rootmux_uart_clk_sel_t
+
+ + + + + + + + + +
Enumerator
kCLOCK_UartRootmuxOsc25m  +

UART Clock from OSC 25M.

+
kCLOCK_UartRootmuxSysPll1Div10  +

UART Clock from SYSTEM PLL1 divided by 10.

+
kCLOCK_UartRootmuxSysPll2Div5  +

UART Clock from SYSTEM PLL2 divided by 5.

+
kCLOCK_UartRootmuxSysPll2Div10  +

UART Clock from SYSTEM PLL2 divided by 10.

+
kCLOCK_UartRootmuxSysPll3  +

UART Clock from SYSTEM PLL3.

+
kCLOCK_UartRootmuxExtClk2  +

UART Clock from External Clock 2.

+
kCLOCK_UartRootmuxExtClk34  +

UART Clock from External Clock 3, External Clock 4.

+
kCLOCK_UartRootmuxAudioPll2  +

UART Clock from Audio PLL2.

+
+ +
+
+ +
+
+ + + + +
enum clock_rootmux_gpt_t
+
+ + + + + + + + + +
Enumerator
kCLOCK_GptRootmuxOsc25m  +

GPT Clock from OSC 25M.

+
kCLOCK_GptRootmuxSystemPll2Div10  +

GPT Clock from SYSTEM PLL2 divided by 10.

+
kCLOCK_GptRootmuxSysPll1Div2  +

GPT Clock from SYSTEM PLL1 divided by 2.

+
kCLOCK_GptRootmuxSysPll1Div20  +

GPT Clock from SYSTEM PLL1 divided by 20.

+
kCLOCK_GptRootmuxVideoPll1  +

GPT Clock from VIDEO PLL1.

+
kCLOCK_GptRootmuxSystemPll1Div10  +

GPT Clock from SYSTEM PLL1 divided by 10.

+
kCLOCK_GptRootmuxAudioPll1  +

GPT Clock from AUDIO PLL1.

+
kCLOCK_GptRootmuxExtClk123  +

GPT Clock from External Clock1, External Clock2, External Clock3.

+
+ +
+
+ +
+
+ + + + +
enum clock_rootmux_wdog_clk_sel_t
+
+ + + + + + + + + +
Enumerator
kCLOCK_WdogRootmuxOsc25m  +

WDOG Clock from OSC 25M.

+
kCLOCK_WdogRootmuxSysPll1Div6  +

WDOG Clock from SYSTEM PLL1 divided by 6.

+
kCLOCK_WdogRootmuxSysPll1Div5  +

WDOG Clock from SYSTEM PLL1 divided by 5.

+
kCLOCK_WdogRootmuxVpuPll  +

WDOG Clock from VPU DLL.

+
kCLOCK_WdogRootmuxSystemPll2Div8  +

WDOG Clock from SYSTEM PLL2 divided by 8.

+
kCLOCK_WdogRootmuxSystemPll3  +

WDOG Clock from SYSTEM PLL3.

+
kCLOCK_WdogRootmuxSystemPll1Div10  +

WDOG Clock from SYSTEM PLL1 divided by 10.

+
kCLOCK_WdogRootmuxSystemPll2Div6  +

WDOG Clock from SYSTEM PLL2 divided by 6.

+
+ +
+
+ +
+
+ + + + +
enum clock_rootmux_Pwm_clk_sel_t
+
+ + + + + + + + + +
Enumerator
kCLOCK_PwmRootmuxOsc25m  +

PWM Clock from OSC 25M.

+
kCLOCK_PwmRootmuxSysPll2Div10  +

PWM Clock from SYSTEM PLL2 divided by 10.

+
kCLOCK_PwmRootmuxSysPll1Div5  +

PWM Clock from SYSTEM PLL1 divided by 5.

+
kCLOCK_PwmRootmuxSysPll1Div20  +

PWM Clock from SYSTEM PLL1 divided by 20.

+
kCLOCK_PwmRootmuxSystemPll3  +

PWM Clock from SYSTEM PLL3.

+
kCLOCK_PwmRootmuxExtClk12  +

PWM Clock from External Clock1, External Clock2.

+
kCLOCK_PwmRootmuxSystemPll1Div10  +

PWM Clock from SYSTEM PLL1 divided by 10.

+
kCLOCK_PwmRootmuxVideoPll1  +

PWM Clock from VIDEO PLL1.

+
+ +
+
+ +
+
+ + + + +
enum clock_rootmux_sai_clk_sel_t
+
+ + + + + + + + + +
Enumerator
kCLOCK_SaiRootmuxOsc25m  +

SAI Clock from OSC 25M.

+
kCLOCK_SaiRootmuxAudioPll1  +

SAI Clock from AUDIO PLL1.

+
kCLOCK_SaiRootmuxAudioPll2  +

SAI Clock from AUDIO PLL2.

+
kCLOCK_SaiRootmuxVideoPll1  +

SAI Clock from VIDEO PLL1.

+
kCLOCK_SaiRootmuxSysPll1Div6  +

SAI Clock from SYSTEM PLL1 divided by 6.

+
kCLOCK_SaiRootmuxOsc27m  +

SAI Clock from OSC 27M.

+
kCLOCK_SaiRootmuxExtClk123  +

SAI Clock from External Clock1, External Clock2, External Clock3.

+
kCLOCK_SaiRootmuxExtClk234  +

SAI Clock from External Clock2, External Clock3, External Clock4.

+
+ +
+
+ +
+
+ + + + +
enum clock_rootmux_noc_clk_sel_t
+
+ + + + + + + + + +
Enumerator
kCLOCK_NocRootmuxOsc25m  +

NOC Clock from OSC 25M.

+
kCLOCK_NocRootmuxSysPll1  +

NOC Clock from SYSTEM PLL1.

+
kCLOCK_NocRootmuxSysPll3  +

NOC Clock from SYSTEM PLL3.

+
kCLOCK_NocRootmuxSysPll2  +

NOC Clock from SYSTEM PLL2.

+
kCLOCK_NocRootmuxSysPll2Div2  +

NOC Clock from SYSTEM PLL2 divided by 2.

+
kCLOCK_NocRootmuxAudioPll1  +

NOC Clock from AUDIO PLL1.

+
kCLOCK_NocRootmuxVideoPll1  +

NOC Clock from VIDEO PLL1.

+
kCLOCK_NocRootmuxAudioPll2  +

NOC Clock from AUDIO PLL2.

+
+ +
+
+ +
+
+ + + + +
enum clock_pll_gate_t
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enumerator
kCLOCK_ArmPllGate  +

ARM PLL Gate.

+
kCLOCK_GpuPllGate  +

GPU PLL Gate.

+
kCLOCK_VpuPllGate  +

VPU PLL Gate.

+
kCLOCK_DramPllGate  +

DRAM PLL1 Gate.

+
kCLOCK_SysPll1Gate  +

SYSTEM PLL1 Gate.

+
kCLOCK_SysPll1Div2Gate  +

SYSTEM PLL1 Div2 Gate.

+
kCLOCK_SysPll1Div3Gate  +

SYSTEM PLL1 Div3 Gate.

+
kCLOCK_SysPll1Div4Gate  +

SYSTEM PLL1 Div4 Gate.

+
kCLOCK_SysPll1Div5Gate  +

SYSTEM PLL1 Div5 Gate.

+
kCLOCK_SysPll1Div6Gate  +

SYSTEM PLL1 Div6 Gate.

+
kCLOCK_SysPll1Div8Gate  +

SYSTEM PLL1 Div8 Gate.

+
kCLOCK_SysPll1Div10Gate  +

SYSTEM PLL1 Div10 Gate.

+
kCLOCK_SysPll1Div20Gate  +

SYSTEM PLL1 Div20 Gate.

+
kCLOCK_SysPll2Gate  +

SYSTEM PLL2 Gate.

+
kCLOCK_SysPll2Div2Gate  +

SYSTEM PLL2 Div2 Gate.

+
kCLOCK_SysPll2Div3Gate  +

SYSTEM PLL2 Div3 Gate.

+
kCLOCK_SysPll2Div4Gate  +

SYSTEM PLL2 Div4 Gate.

+
kCLOCK_SysPll2Div5Gate  +

SYSTEM PLL2 Div5 Gate.

+
kCLOCK_SysPll2Div6Gate  +

SYSTEM PLL2 Div6 Gate.

+
kCLOCK_SysPll2Div8Gate  +

SYSTEM PLL2 Div8 Gate.

+
kCLOCK_SysPll2Div10Gate  +

SYSTEM PLL2 Div10 Gate.

+
kCLOCK_SysPll2Div20Gate  +

SYSTEM PLL2 Div20 Gate.

+
kCLOCK_SysPll3Gate  +

SYSTEM PLL3 Gate.

+
kCLOCK_AudioPll1Gate  +

AUDIO PLL1 Gate.

+
kCLOCK_AudioPll2Gate  +

AUDIO PLL2 Gate.

+
kCLOCK_VideoPll1Gate  +

VIDEO PLL1 Gate.

+
kCLOCK_VideoPll2Gate  +

VIDEO PLL2 Gate.

+
+ +
+
+ +
+
+ + + + +
enum clock_gate_value_t
+
+ + + + + +
Enumerator
kCLOCK_ClockNotNeeded  +

Clock always disabled.

+
kCLOCK_ClockNeededRun  +

Clock enabled when CPU is running.

+
kCLOCK_ClockNeededRunWait  +

Clock enabled when CPU is running or in WAIT mode.

+
kCLOCK_ClockNeededAll  +

Clock always enabled.

+
+ +
+
+ +
+
+ + + + +
enum clock_pll_bypass_ctrl_t
+
+

These constants define the PLL control names for PLL bypass.
+

+
    +
  • 0:15: REG offset to CCM_ANALOG_BASE in bytes.
    • +
  • 16:20: bypass bit shift.
    • +
+ + + + + + + + + + + + + + + + + +
Enumerator
kCLOCK_AudioPll1BypassCtrl  +

CCM Audio PLL1 bypass Control.

+
kCLOCK_AudioPll2BypassCtrl  +

CCM Audio PLL2 bypass Control.

+
kCLOCK_VideoPll1BypassCtrl  +

CCM Video Pll1 bypass Control.

+
kCLOCK_GpuPLLPwrBypassCtrl  +

CCM Gpu PLL bypass Control.

+
kCLOCK_VpuPllPwrBypassCtrl  +

CCM Vpu PLL bypass Control.

+
kCLOCK_ArmPllPwrBypassCtrl  +

CCM Arm PLL bypass Control.

+
kCLOCK_SysPll1InternalPll1BypassCtrl  +

CCM System PLL1 internal pll1 bypass Control.

+
kCLOCK_SysPll1InternalPll2BypassCtrl  +

CCM System PLL1 internal pll2 bypass Control.

+
kCLOCK_SysPll2InternalPll1BypassCtrl  +

CCM Analog System PLL1 internal pll1 bypass Control.

+
kCLOCK_SysPll2InternalPll2BypassCtrl  +

CCM Analog VIDEO System PLL1 internal pll1 bypass Control.

+
kCLOCK_SysPll3InternalPll1BypassCtrl  +

CCM Analog VIDEO PLL bypass Control.

+
kCLOCK_SysPll3InternalPll2BypassCtrl  +

CCM Analog VIDEO PLL bypass Control.

+
kCLOCK_VideoPll2InternalPll1BypassCtrl  +

CCM Analog 480M PLL bypass Control.

+
kCLOCK_VideoPll2InternalPll2BypassCtrl  +

CCM Analog 480M PLL bypass Control.

+
kCLOCK_DramPllInternalPll1BypassCtrl  +

CCM Analog 480M PLL bypass Control.

+
kCLOCK_DramPllInternalPll2BypassCtrl  +

CCM Analog 480M PLL bypass Control.

+
+ +
+
+ +
+
+ + + + +
enum clock_pll_clke_t
+
+

These constants define the PLL clock names for PLL clock enable/disable operations.
+

+
    +
  • 0:15: REG offset to CCM_ANALOG_BASE in bytes.
    • +
  • 16:20: Clock enable bit shift.
    • +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enumerator
kCLOCK_AudioPll1Clke  +

Audio pll1 clke.

+
kCLOCK_AudioPll2Clke  +

Audio pll2 clke.

+
kCLOCK_VideoPll1Clke  +

Video pll1 clke.

+
kCLOCK_GpuPllClke  +

Gpu pll clke.

+
kCLOCK_VpuPllClke  +

Vpu pll clke.

+
kCLOCK_ArmPllClke  +

Arm pll clke.

+
kCLOCK_SystemPll1Clke  +

System pll1 clke.

+
kCLOCK_SystemPll1Div2Clke  +

System pll1 Div2 clke.

+
kCLOCK_SystemPll1Div3Clke  +

System pll1 Div3 clke.

+
kCLOCK_SystemPll1Div4Clke  +

System pll1 Div4 clke.

+
kCLOCK_SystemPll1Div5Clke  +

System pll1 Div5 clke.

+
kCLOCK_SystemPll1Div6Clke  +

System pll1 Div6 clke.

+
kCLOCK_SystemPll1Div8Clke  +

System pll1 Div8 clke.

+
kCLOCK_SystemPll1Div10Clke  +

System pll1 Div10 clke.

+
kCLOCK_SystemPll1Div20Clke  +

System pll1 Div20 clke.

+
kCLOCK_SystemPll2Clke  +

System pll2 clke.

+
kCLOCK_SystemPll2Div2Clke  +

System pll2 Div2 clke.

+
kCLOCK_SystemPll2Div3Clke  +

System pll2 Div3 clke.

+
kCLOCK_SystemPll2Div4Clke  +

System pll2 Div4 clke.

+
kCLOCK_SystemPll2Div5Clke  +

System pll2 Div5 clke.

+
kCLOCK_SystemPll2Div6Clke  +

System pll2 Div6 clke.

+
kCLOCK_SystemPll2Div8Clke  +

System pll2 Div8 clke.

+
kCLOCK_SystemPll2Div10Clke  +

System pll2 Div10 clke.

+
kCLOCK_SystemPll2Div20Clke  +

System pll2 Div20 clke.

+
kCLOCK_SystemPll3Clke  +

System pll3 clke.

+
kCLOCK_VideoPll2Clke  +

Video pll2 clke.

+
kCLOCK_DramPllClke  +

Dram pll clke.

+
kCLOCK_OSC25MClke  +

OSC25M clke.

+
kCLOCK_OSC27MClke  +

OSC27M clke.

+
+ +
+
+ +
+
+ + + + +
enum _osc_mode
+
+ + + +
Enumerator
kOSC_OscMode  +

OSC oscillator mode.

+
kOSC_ExtMode  +

OSC external mode.

+
+ +
+
+ +
+
+ + + + +
enum osc32_src_t
+
+ + + +
Enumerator
kOSC32_Src25MDiv800  +

source from 25M divide 800

+
kOSC32_SrcRTC  +

source from RTC

+
+ +
+
+ +
+
+ + + + +
enum _ccm_analog_pll_ref_clk
+
+ + + + + +
Enumerator
kANALOG_PllRefOsc25M  +

reference OSC 25M

+
kANALOG_PllRefOsc27M  +

reference OSC 27M

+
kANALOG_PllRefOscHdmiPhy27M  +

reference HDMI PHY 27M

+
kANALOG_PllRefClkPN  +

reference CLK_P_N

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void CLOCK_SetRootMux (clock_root_control_t rootClk,
uint32_t mux 
)
+ 		+inlinestatic
+
+

User maybe need to set more than one mux ROOT according to the clock tree description in the reference manual.

+
Parameters
+ + + +
rootClkRoot clock control (see clock_root_control_t enumeration).
muxRoot mux value (see _ccm_rootmux_xxx enumeration).
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t CLOCK_GetRootMux (clock_root_control_t rootClk)
+ 		+inlinestatic
+
+

In order to get the clock source of root, user maybe need to get more than one ROOT's mux value to obtain the final clock source of root.

+
Parameters
+ + +
rootClkRoot clock control (see clock_root_control_t enumeration).
+
+
+
Returns
Root mux value (see _ccm_rootmux_xxx enumeration).
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void CLOCK_EnableRoot (clock_root_control_t rootClk)
+ 		+inlinestatic
+
+
Parameters
+ + +
rootClkRoot clock control (see clock_root_control_t enumeration)
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void CLOCK_DisableRoot (clock_root_control_t rootClk)
+ 		+inlinestatic
+
+
Parameters
+ + +
rootClkRoot control (see clock_root_control_t enumeration)
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static bool CLOCK_IsRootEnabled (clock_root_control_t rootClk)
+ 		+inlinestatic
+
+
Parameters
+ + +
rootClkRoot control (see clock_root_control_t enumeration)
+
+
+
Returns
CCM root enabled or not.
    +
  • true: Clock root is enabled.
    • +
  • false: Clock root is disabled.
    • +
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void CLOCK_UpdateRoot (clock_root_control_t ccmRootClk,
uint32_t mux,
uint32_t pre,
uint32_t post 
)
+
+
Parameters
+ + + + + +
ccmRootClkRoot control (see clock_root_control_t enumeration)
muxroot mux value (see _ccm_rootmux_xxx enumeration)
prePre divider value (0-7, divider=n+1)
postPost divider value (0-63, divider=n+1)
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void CLOCK_SetRootDivider (clock_root_control_t ccmRootClk,
uint32_t pre,
uint32_t post 
)
+
+
Parameters
+ + + + +
ccmRootClkRoot control (see clock_root_control_t enumeration)
prePre divider value (1-8)
postPost divider value (1-64)
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t CLOCK_GetRootPreDivider (clock_root_control_t rootClk)
+ 		+inlinestatic
+
+

In order to get the clock source of root, user maybe need to get more than one ROOT's mux value to obtain the final clock source of root.

+
Parameters
+ + +
rootClkRoot clock name (see clock_root_control_t enumeration).
+
+
+
Returns
Root Pre divider value.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t CLOCK_GetRootPostDivider (clock_root_control_t rootClk)
+ 		+inlinestatic
+
+

In order to get the clock source of root, user maybe need to get more than one ROOT's mux value to obtain the final clock source of root.

+
Parameters
+ + +
rootClkRoot clock name (see clock_root_control_t enumeration).
+
+
+
Returns
Root Post divider value.
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_InitOSC25M (const osc_config_t * config)
+
+
Parameters
+ + +
configosc configuration.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_DeinitOSC25M (void )
+
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_InitOSC27M (const osc_config_t * config)
+
+
Parameters
+ + +
configosc configuration.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_DeinitOSC27M (void )
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void CLOCK_SwitchOSC32Src (osc32_src_t sel)
+ 		+inlinestatic
+
+
Parameters
+ + +
selOSC32 input clock select
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void CLOCK_ControlGate (uint32_t ccmGate,
clock_gate_value_t control 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
ccmGateGate control (see clock_pll_gate_t and clock_ip_name_t enumeration)
controlGate control value (see clock_gate_value_t)
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_EnableClock (clock_ip_name_t ccmGate)
+
+

Take care of that one module may need to set more than one clock gate.

+
Parameters
+ + +
ccmGateGate control for each module (see clock_ip_name_t enumeration).
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_DisableClock (clock_ip_name_t ccmGate)
+
+

Take care of that one module may need to set more than one clock gate.

+
Parameters
+ + +
ccmGateGate control for each module (see clock_ip_name_t enumeration).
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void CLOCK_PowerUpPll (CCM_ANALOG_Type * base,
clock_pll_ctrl_t pllControl 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseCCM_ANALOG base pointer.
pllControlPLL control name (see clock_pll_ctrl_t enumeration)
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void CLOCK_PowerDownPll (CCM_ANALOG_Type * base,
clock_pll_ctrl_t pllControl 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseCCM_ANALOG base pointer.
pllControlPLL control name (see clock_pll_ctrl_t enumeration)
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void CLOCK_SetPllBypass (CCM_ANALOG_Type * base,
clock_pll_bypass_ctrl_t pllControl,
bool bypass 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseCCM_ANALOG base pointer.
pllControlPLL control name (see ccm_analog_pll_control_t enumeration)
bypassBypass the PLL.
    +
  • true: Bypass the PLL.
    • +
  • false: Do not bypass the PLL.
    • +
+
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static bool CLOCK_IsPllBypassed (CCM_ANALOG_Type * base,
clock_pll_bypass_ctrl_t pllControl 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseCCM_ANALOG base pointer.
pllControlPLL control name (see ccm_analog_pll_control_t enumeration)
+
+
+
Returns
PLL bypass status.
    +
  • true: The PLL is bypassed.
    • +
  • false: The PLL is not bypassed.
    • +
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static bool CLOCK_IsPllLocked (CCM_ANALOG_Type * base,
clock_pll_ctrl_t pllControl 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseCCM_ANALOG base pointer.
pllControlPLL control name (see clock_pll_ctrl_t enumeration)
+
+
+
Returns
PLL lock status.
    +
  • true: The PLL clock is locked.
    • +
  • false: The PLL clock is not locked.
    • +
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void CLOCK_EnableAnalogClock (CCM_ANALOG_Type * base,
clock_pll_clke_t pllClock 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseCCM_ANALOG base pointer.
pllClockPLL clock name (see ccm_analog_pll_clock_t enumeration)
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void CLOCK_DisableAnalogClock (CCM_ANALOG_Type * base,
clock_pll_clke_t pllClock 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseCCM_ANALOG base pointer.
pllClockPLL clock name (see ccm_analog_pll_clock_t enumeration)
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void CLOCK_OverrideAnalogClke (CCM_ANALOG_Type * base,
clock_pll_clke_t ovClock,
bool override 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseCCM_ANALOG base pointer.
ovClockPLL clock name (see clock_pll_clke_t enumeration)
overrideOverride the PLL.
    +
  • true: Override the PLL clke, CCM will handle it.
    • +
  • false: Do not override the PLL clke.
    • +
+
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void CLOCK_OverridePllPd (CCM_ANALOG_Type * base,
clock_pll_ctrl_t pdClock,
bool override 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseCCM_ANALOG base pointer.
pdClockPLL clock name (see clock_pll_ctrl_t enumeration)
overrideOverride the PLL.
    +
  • true: Override the PLL clke, CCM will handle it.
    • +
  • false: Do not override the PLL clke.
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_InitArmPll (const ccm_analog_frac_pll_config_t * config)
+
+
Parameters
+ + +
configPointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).
+
+
+
Note
This function can't detect whether the Arm PLL has been enabled and used by some IPs.
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_InitSysPll1 (const ccm_analog_sscg_pll_config_t * config)
+
+
Parameters
+ + +
configPointer to the configuration structure(see ccm_analog_sscg_pll_config_t enumeration).
+
+
+
Note
This function can't detect whether the SYS PLL has been enabled and used by some IPs.
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_InitSysPll2 (const ccm_analog_sscg_pll_config_t * config)
+
+
Parameters
+ + +
configPointer to the configuration structure(see ccm_analog_sscg_pll_config_t enumeration).
+
+
+
Note
This function can't detect whether the SYS PLL has been enabled and used by some IPs.
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_InitSysPll3 (const ccm_analog_sscg_pll_config_t * config)
+
+
Parameters
+ + +
configPointer to the configuration structure(see ccm_analog_sscg_pll_config_t enumeration).
+
+
+
Note
This function can't detect whether the SYS PLL has been enabled and used by some IPs.
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_InitDramPll (const ccm_analog_sscg_pll_config_t * config)
+
+
Parameters
+ + +
configPointer to the configuration structure(see ccm_analog_sscg_pll_config_t enumeration).
+
+
+
Note
This function can't detect whether the DDR PLL has been enabled and used by some IPs.
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_InitAudioPll1 (const ccm_analog_frac_pll_config_t * config)
+
+
Parameters
+ + +
configPointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).
+
+
+
Note
This function can't detect whether the AUDIO PLL has been enabled and used by some IPs.
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_InitAudioPll2 (const ccm_analog_frac_pll_config_t * config)
+
+
Parameters
+ + +
configPointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).
+
+
+
Note
This function can't detect whether the AUDIO PLL has been enabled and used by some IPs.
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_InitVideoPll1 (const ccm_analog_frac_pll_config_t * config)
+
+
Parameters
+ + +
configPointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CLOCK_InitVideoPll2 (const ccm_analog_sscg_pll_config_t * config)
+
+
Parameters
+ + +
configPointer to the configuration structure(see ccm_analog_sscg_pll_config_t enumeration).
+
+
+
Note
This function can't detect whether the VIDEO PLL has been enabled and used by some IPs.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void CLOCK_InitSSCGPll (CCM_ANALOG_Type * base,
const ccm_analog_sscg_pll_config_t * config,
clock_pll_ctrl_t type 
)
+
+
Parameters
+ + + + +
baseCCM ANALOG base address
configPointer to the configuration structure(see ccm_analog_sscg_pll_config_t enumeration).
typesscg pll type
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t CLOCK_GetSSCGPllFreq (CCM_ANALOG_Type * base,
clock_pll_ctrl_t type,
uint32_t refClkFreq,
bool pll1Bypass 
)
+
+
Parameters
+ + + + + +
baseCCM ANALOG base address.
typesscg pll type
refClkFreqreference clock frequency
pll1Bypasspll1 bypass flag
+
+
+
Returns
Clock frequency
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void CLOCK_InitFracPll (CCM_ANALOG_Type * base,
const ccm_analog_frac_pll_config_t * config,
clock_pll_ctrl_t type 
)
+
+
Parameters
+ + + + +
baseCCM ANALOG base address.
configPointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).
typefractional pll type.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t CLOCK_GetFracPllFreq (CCM_ANALOG_Type * base,
clock_pll_ctrl_t type,
uint32_t refClkFreq 
)
+
+
Parameters
+ + + + +
baseCCM_ANALOG base pointer.
typefractional pll type.
refClkFreqreference clock frequency
+
+
+
Returns
Clock frequency
+ +
+
+ +
+
+ + + + + + + + +
uint32_t CLOCK_GetPllFreq (clock_pll_ctrl_t pll)
+
+
Parameters
+ + +
pllfractional pll type.
+
+
+
Returns
Clock frequency
+ +
+
+ +
+
+ + + + + + + + +
uint32_t CLOCK_GetPllRefClkFreq (clock_pll_ctrl_t ctrl)
+
+
Parameters
+ + +
ctrlfractional pll type.
+
+
+
Returns
Clock frequency
+ +
+
+ +
+
+ + + + + + + + +
uint32_t CLOCK_GetFreq (clock_name_t clockName)
+
+

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

+
Parameters
+ + +
clockNameClock names defined in clock_name_t
+
+
+
Returns
Clock frequency value in hertz
+ +
+
+ +
+
+ + + + + + + + +
uint32_t CLOCK_GetCoreM4Freq (void )
+
+
Returns
Clock frequency; If the clock is invalid, returns 0.
+ +
+
+ +
+
+ + + + + + + + +
uint32_t CLOCK_GetAxiFreq (void )
+
+
Returns
Clock frequency; If the clock is invalid, returns 0.
+ +
+
+ +
+
+ + + + + + + + +
uint32_t CLOCK_GetAhbFreq (void )
+
+
Returns
Clock frequency; If the clock is invalid, returns 0.
+ +
+
+
+
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b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00009.html new file mode 100644 index 000000000..899a1b8d1 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00009.html @@ -0,0 +1,1492 @@ + + + + + + +MCUXpresso SDK API Reference Manual: CODEC Common Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Modules | +Data Structures | +Macros | +Enumerations | +Functions
+
+
CODEC Common Driver
CODEC Driver
+
+
+

Overview

+

The codec common driver provides a codec control abstraction interface.

+ + + + + + +

+Modules

 CODEC Adapter
 
 WM8524 Adapter
 
+ + + + + + + + + + +

+Data Structures

struct  codec_config_t
 Initialize structure of the codec. More...
 
struct  codec_capability_t
 codec capability More...
 
struct  codec_handle_t
 Codec handle definition. More...
 
+ + + + +

+Macros

+#define CODEC_VOLUME_MAX_VALUE   (100U)
 codec maximum volume range
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Enumerations

enum  {
+  kStatus_CODEC_NotSupport = MAKE_STATUS(kStatusGroup_CODEC, 0U), +
+  kStatus_CODEC_DeviceNotRegistered = MAKE_STATUS(kStatusGroup_CODEC, 1U), +
+  kStatus_CODEC_I2CBusInitialFailed, +
+  kStatus_CODEC_I2CCommandTransferFailed +
+ }
 CODEC status. More...
 
enum  codec_audio_protocol_t {
+  kCODEC_BusI2S = 0U, +
+  kCODEC_BusLeftJustified = 1U, +
+  kCODEC_BusRightJustified = 2U, +
+  kCODEC_BusPCMA = 3U, +
+  kCODEC_BusPCMB = 4U, +
+  kCODEC_BusTDM = 5U +
+ }
 AUDIO format definition. More...
 
enum  {
+  kCODEC_AudioSampleRate8KHz = 8000U, +
+  kCODEC_AudioSampleRate11025Hz = 11025U, +
+  kCODEC_AudioSampleRate12KHz = 12000U, +
+  kCODEC_AudioSampleRate16KHz = 16000U, +
+  kCODEC_AudioSampleRate22050Hz = 22050U, +
+  kCODEC_AudioSampleRate24KHz = 24000U, +
+  kCODEC_AudioSampleRate32KHz = 32000U, +
+  kCODEC_AudioSampleRate44100Hz = 44100U, +
+  kCODEC_AudioSampleRate48KHz = 48000U, +
+  kCODEC_AudioSampleRate96KHz = 96000U, +
+  kCODEC_AudioSampleRate192KHz = 192000U, +
+  kCODEC_AudioSampleRate384KHz = 384000U +
+ }
 audio sample rate definition More...
 
enum  {
+  kCODEC_AudioBitWidth16bit = 16U, +
+  kCODEC_AudioBitWidth20bit = 20U, +
+  kCODEC_AudioBitWidth24bit = 24U, +
+  kCODEC_AudioBitWidth32bit = 32U +
+ }
 audio bit width More...
 
enum  codec_module_t {
+  kCODEC_ModuleADC = 0U, +
+  kCODEC_ModuleDAC = 1U, +
+  kCODEC_ModulePGA = 2U, +
+  kCODEC_ModuleHeadphone = 3U, +
+  kCODEC_ModuleSpeaker = 4U, +
+  kCODEC_ModuleLinein = 5U, +
+  kCODEC_ModuleLineout = 6U, +
+  kCODEC_ModuleVref = 7U, +
+  kCODEC_ModuleMicbias = 8U, +
+  kCODEC_ModuleMic = 9U, +
+  kCODEC_ModuleI2SIn = 10U, +
+  kCODEC_ModuleI2SOut = 11U, +
+  kCODEC_ModuleMixer = 12U +
+ }
 audio codec module More...
 
enum  codec_module_ctrl_cmd_t { kCODEC_ModuleSwitchI2SInInterface = 0U + }
 audio codec module control cmd More...
 
enum  {
+  kCODEC_ModuleI2SInInterfacePCM = 0U, +
+  kCODEC_ModuleI2SInInterfaceDSD = 1U +
+ }
 audio codec module digital interface More...
 
enum  {
+  kCODEC_RecordSourceDifferentialLine = 1U, +
+  kCODEC_RecordSourceLineInput = 2U, +
+  kCODEC_RecordSourceDifferentialMic = 4U, +
+  kCODEC_RecordSourceDigitalMic = 8U, +
+  kCODEC_RecordSourceSingleEndMic = 16U +
+ }
 audio codec module record source value More...
 
enum  {
+  kCODEC_RecordChannelLeft1 = 1U, +
+  kCODEC_RecordChannelLeft2 = 2U, +
+  kCODEC_RecordChannelLeft3 = 4U, +
+  kCODEC_RecordChannelRight1 = 1U, +
+  kCODEC_RecordChannelRight2 = 2U, +
+  kCODEC_RecordChannelRight3 = 4U, +
+  kCODEC_RecordChannelDifferentialPositive1 = 1U, +
+  kCODEC_RecordChannelDifferentialPositive2 = 2U, +
+  kCODEC_RecordChannelDifferentialPositive3 = 4U, +
+  kCODEC_RecordChannelDifferentialNegative1 = 8U, +
+  kCODEC_RecordChannelDifferentialNegative2 = 16U, +
+  kCODEC_RecordChannelDifferentialNegative3 = 32U +
+ }
 audio codec record channel More...
 
enum  {
+  kCODEC_PlaySourcePGA = 1U, +
+  kCODEC_PlaySourceInput = 2U, +
+  kCODEC_PlaySourceDAC = 4U, +
+  kCODEC_PlaySourceMixerIn = 1U, +
+  kCODEC_PlaySourceMixerInLeft = 2U, +
+  kCODEC_PlaySourceMixerInRight = 4U, +
+  kCODEC_PlaySourceAux = 8U +
+ }
 audio codec module play source value More...
 
enum  {
+  kCODEC_PlayChannelHeadphoneLeft = 1U, +
+  kCODEC_PlayChannelHeadphoneRight = 2U, +
+  kCODEC_PlayChannelSpeakerLeft = 4U, +
+  kCODEC_PlayChannelSpeakerRight = 8U, +
+  kCODEC_PlayChannelLineOutLeft = 16U, +
+  kCODEC_PlayChannelLineOutRight = 32U, +
+  kCODEC_PlayChannelLeft0 = 1U, +
+  kCODEC_PlayChannelRight0 = 2U, +
+  kCODEC_PlayChannelLeft1 = 4U, +
+  kCODEC_PlayChannelRight1 = 8U, +
+  kCODEC_PlayChannelLeft2 = 16U, +
+  kCODEC_PlayChannelRight2 = 32U, +
+  kCODEC_PlayChannelLeft3 = 64U, +
+  kCODEC_PlayChannelRight3 = 128U +
+ }
 codec play channel More...
 
enum  {
+  kCODEC_SupportModuleADC = 1U << 0U, +
+  kCODEC_SupportModuleDAC = 1U << 1U, +
+  kCODEC_SupportModulePGA = 1U << 2U, +
+  kCODEC_SupportModuleHeadphone = 1U << 3U, +
+  kCODEC_SupportModuleSpeaker = 1U << 4U, +
+  kCODEC_SupportModuleLinein = 1U << 5U, +
+  kCODEC_SupportModuleLineout = 1U << 6U, +
+  kCODEC_SupportModuleVref = 1U << 7U, +
+  kCODEC_SupportModuleMicbias = 1U << 8U, +
+  kCODEC_SupportModuleMic = 1U << 9U, +
+  kCODEC_SupportModuleI2SIn = 1U << 10U, +
+  kCODEC_SupportModuleI2SOut = 1U << 11U, +
+  kCODEC_SupportModuleMixer = 1U << 12U, +
+  kCODEC_SupportModuleI2SInSwitchInterface = 1U << 13U, +
+  kCODEC_SupportPlayChannelLeft0 = 1U << 0U, +
+  kCODEC_SupportPlayChannelRight0 = 1U << 1U, +
+  kCODEC_SupportPlayChannelLeft1 = 1U << 2U, +
+  kCODEC_SupportPlayChannelRight1 = 1U << 3U, +
+  kCODEC_SupportPlayChannelLeft2 = 1U << 4U, +
+  kCODEC_SupportPlayChannelRight2 = 1U << 5U, +
+  kCODEC_SupportPlayChannelLeft3 = 1U << 6U, +
+  kCODEC_SupportPlayChannelRight3 = 1U << 7U, +
+  kCODEC_SupportPlaySourcePGA = 1U << 8U, +
+  kCODEC_SupportPlaySourceInput = 1U << 9U, +
+  kCODEC_SupportPlaySourceDAC = 1U << 10U, +
+  kCODEC_SupportPlaySourceMixerIn = 1U << 11U, +
+  kCODEC_SupportPlaySourceMixerInLeft = 1U << 12U, +
+  kCODEC_SupportPlaySourceMixerInRight = 1U << 13U, +
+  kCODEC_SupportPlaySourceAux = 1U << 14U, +
+  kCODEC_SupportRecordSourceDifferentialLine = 1U << 0U, +
+  kCODEC_SupportRecordSourceLineInput = 1U << 1U, +
+  kCODEC_SupportRecordSourceDifferentialMic = 1U << 2U, +
+  kCODEC_SupportRecordSourceDigitalMic = 1U << 3U, +
+  kCODEC_SupportRecordSourceSingleEndMic = 1U << 4U, +
+  kCODEC_SupportRecordChannelLeft1 = 1U << 6U, +
+  kCODEC_SupportRecordChannelLeft2 = 1U << 7U, +
+  kCODEC_SupportRecordChannelLeft3 = 1U << 8U, +
+  kCODEC_SupportRecordChannelRight1 = 1U << 9U, +
+  kCODEC_SupportRecordChannelRight2 = 1U << 10U, +
+  kCODEC_SupportRecordChannelRight3 = 1U << 11U +
+ }
 audio codec capability More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

status_t CODEC_Init (codec_handle_t *handle, codec_config_t *config)
 Codec initilization. More...
 
status_t CODEC_Deinit (codec_handle_t *handle)
 Codec de-initilization. More...
 
status_t CODEC_SetFormat (codec_handle_t *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth)
 set audio data format. More...
 
status_t CODEC_ModuleControl (codec_handle_t *handle, codec_module_ctrl_cmd_t cmd, uint32_t data)
 codec module control. More...
 
status_t CODEC_SetVolume (codec_handle_t *handle, uint32_t channel, uint32_t volume)
 set audio codec pl volume. More...
 
status_t CODEC_SetMute (codec_handle_t *handle, uint32_t channel, bool mute)
 set audio codec module mute. More...
 
status_t CODEC_SetPower (codec_handle_t *handle, codec_module_t module, bool powerOn)
 set audio codec power. More...
 
status_t CODEC_SetRecord (codec_handle_t *handle, uint32_t recordSource)
 codec set record source. More...
 
status_t CODEC_SetRecordChannel (codec_handle_t *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel)
 codec set record channel. More...
 
status_t CODEC_SetPlay (codec_handle_t *handle, uint32_t playSource)
 codec set play source. More...
 
+ + + + +

+Driver version

#define FSL_CODEC_DRIVER_VERSION   (MAKE_VERSION(2, 2, 2))
 CLOCK driver version 2.2.2. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct codec_config_t
+
+
+ + + + + + + +

Data Fields

+uint32_t codecDevType
 codec type
 
+void * codecDevConfig
 Codec device specific configuration.
 
+ +
+
+ +
+
+ + + + +
struct codec_capability_t
+
+
+ + + + + + + + + + +

Data Fields

+uint32_t codecModuleCapability
 codec module capability
 
+uint32_t codecPlayCapability
 codec play capability
 
+uint32_t codecRecordCapability
 codec record capability
 
+ +
+
+ +
+
+ + + + +
struct _codec_handle
+
+

codec handle declaration

+
    +
  • Application should allocate a buffer with CODEC_HANDLE_SIZE for handle definition, such as uint8_t codecHandleBuffer[CODEC_HANDLE_SIZE]; codec_handle_t *codecHandle = codecHandleBuffer;
    • +
+
+ + + + + + + + + + +

Data Fields

+codec_config_t * codecConfig
 codec configuration function pointer
 
+const codec_capability_t * codecCapability
 codec capability
 
+uint8_t codecDevHandle [HAL_CODEC_HANDLER_SIZE]
 codec device handle
 
+ +
+
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_CODEC_DRIVER_VERSION   (MAKE_VERSION(2, 2, 2))
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
anonymous enum
+
+

+ + + + + +
Enumerator
kStatus_CODEC_NotSupport  +

CODEC not support status.

+
kStatus_CODEC_DeviceNotRegistered  +

CODEC device register failed status.

+
kStatus_CODEC_I2CBusInitialFailed  +

CODEC i2c bus initialization failed status.

+
kStatus_CODEC_I2CCommandTransferFailed  +

CODEC i2c bus command transfer failed status.

+
+ +
+
+ +
+
+ + + + +
enum codec_audio_protocol_t
+
+ + + + + + + +
Enumerator
kCODEC_BusI2S  +

I2S type.

+
kCODEC_BusLeftJustified  +

Left justified mode.

+
kCODEC_BusRightJustified  +

Right justified mode.

+
kCODEC_BusPCMA  +

DSP/PCM A mode.

+
kCODEC_BusPCMB  +

DSP/PCM B mode.

+
kCODEC_BusTDM  +

TDM mode.

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+

+ + + + + + + + + + + + + +
Enumerator
kCODEC_AudioSampleRate8KHz  +

Sample rate 8000 Hz.

+
kCODEC_AudioSampleRate11025Hz  +

Sample rate 11025 Hz.

+
kCODEC_AudioSampleRate12KHz  +

Sample rate 12000 Hz.

+
kCODEC_AudioSampleRate16KHz  +

Sample rate 16000 Hz.

+
kCODEC_AudioSampleRate22050Hz  +

Sample rate 22050 Hz.

+
kCODEC_AudioSampleRate24KHz  +

Sample rate 24000 Hz.

+
kCODEC_AudioSampleRate32KHz  +

Sample rate 32000 Hz.

+
kCODEC_AudioSampleRate44100Hz  +

Sample rate 44100 Hz.

+
kCODEC_AudioSampleRate48KHz  +

Sample rate 48000 Hz.

+
kCODEC_AudioSampleRate96KHz  +

Sample rate 96000 Hz.

+
kCODEC_AudioSampleRate192KHz  +

Sample rate 192000 Hz.

+
kCODEC_AudioSampleRate384KHz  +

Sample rate 384000 Hz.

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+

+ + + + + +
Enumerator
kCODEC_AudioBitWidth16bit  +

audio bit width 16

+
kCODEC_AudioBitWidth20bit  +

audio bit width 20

+
kCODEC_AudioBitWidth24bit  +

audio bit width 24

+
kCODEC_AudioBitWidth32bit  +

audio bit width 32

+
+ +
+
+ +
+
+ + + + +
enum codec_module_t
+
+ + + + + + + + + + + + + + +
Enumerator
kCODEC_ModuleADC  +

codec module ADC

+
kCODEC_ModuleDAC  +

codec module DAC

+
kCODEC_ModulePGA  +

codec module PGA

+
kCODEC_ModuleHeadphone  +

codec module headphone

+
kCODEC_ModuleSpeaker  +

codec module speaker

+
kCODEC_ModuleLinein  +

codec module linein

+
kCODEC_ModuleLineout  +

codec module lineout

+
kCODEC_ModuleVref  +

codec module VREF

+
kCODEC_ModuleMicbias  +

codec module MIC BIAS

+
kCODEC_ModuleMic  +

codec module MIC

+
kCODEC_ModuleI2SIn  +

codec module I2S in

+
kCODEC_ModuleI2SOut  +

codec module I2S out

+
kCODEC_ModuleMixer  +

codec module mixer

+
+ +
+
+ +
+
+ + + + +
enum codec_module_ctrl_cmd_t
+
+ + +
Enumerator
kCODEC_ModuleSwitchI2SInInterface  +

module digital interface siwtch.

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+

+ + + +
Enumerator
kCODEC_ModuleI2SInInterfacePCM  +

Pcm interface.

+
kCODEC_ModuleI2SInInterfaceDSD  +

DSD interface.

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+

+ + + + + + +
Enumerator
kCODEC_RecordSourceDifferentialLine  +

record source from differential line

+
kCODEC_RecordSourceLineInput  +

record source from line input

+
kCODEC_RecordSourceDifferentialMic  +

record source from differential mic

+
kCODEC_RecordSourceDigitalMic  +

record source from digital microphone

+
kCODEC_RecordSourceSingleEndMic  +

record source from single microphone

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+

+ + + + + + + + + + + + + +
Enumerator
kCODEC_RecordChannelLeft1  +

left record channel 1

+
kCODEC_RecordChannelLeft2  +

left record channel 2

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kCODEC_RecordChannelLeft3  +

left record channel 3

+
kCODEC_RecordChannelRight1  +

right record channel 1

+
kCODEC_RecordChannelRight2  +

right record channel 2

+
kCODEC_RecordChannelRight3  +

right record channel 3

+
kCODEC_RecordChannelDifferentialPositive1  +

differential positive record channel 1

+
kCODEC_RecordChannelDifferentialPositive2  +

differential positive record channel 2

+
kCODEC_RecordChannelDifferentialPositive3  +

differential positive record channel 3

+
kCODEC_RecordChannelDifferentialNegative1  +

differential negative record channel 1

+
kCODEC_RecordChannelDifferentialNegative2  +

differential negative record channel 2

+
kCODEC_RecordChannelDifferentialNegative3  +

differential negative record channel 3

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+

+ + + + + + + + +
Enumerator
kCODEC_PlaySourcePGA  +

play source PGA, bypass ADC

+
kCODEC_PlaySourceInput  +

play source Input3

+
kCODEC_PlaySourceDAC  +

play source DAC

+
kCODEC_PlaySourceMixerIn  +

play source mixer in

+
kCODEC_PlaySourceMixerInLeft  +

play source mixer in left

+
kCODEC_PlaySourceMixerInRight  +

play source mixer in right

+
kCODEC_PlaySourceAux  +

play source mixer in AUx

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+

+ + + + + + + + + + + + + + + +
Enumerator
kCODEC_PlayChannelHeadphoneLeft  +

play channel headphone left

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kCODEC_PlayChannelHeadphoneRight  +

play channel headphone right

+
kCODEC_PlayChannelSpeakerLeft  +

play channel speaker left

+
kCODEC_PlayChannelSpeakerRight  +

play channel speaker right

+
kCODEC_PlayChannelLineOutLeft  +

play channel lineout left

+
kCODEC_PlayChannelLineOutRight  +

play channel lineout right

+
kCODEC_PlayChannelLeft0  +

play channel left0

+
kCODEC_PlayChannelRight0  +

play channel right0

+
kCODEC_PlayChannelLeft1  +

play channel left1

+
kCODEC_PlayChannelRight1  +

play channel right1

+
kCODEC_PlayChannelLeft2  +

play channel left2

+
kCODEC_PlayChannelRight2  +

play channel right2

+
kCODEC_PlayChannelLeft3  +

play channel left3

+
kCODEC_PlayChannelRight3  +

play channel right3

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enumerator
kCODEC_SupportModuleADC  +

codec capability of module ADC

+
kCODEC_SupportModuleDAC  +

codec capability of module DAC

+
kCODEC_SupportModulePGA  +

codec capability of module PGA

+
kCODEC_SupportModuleHeadphone  +

codec capability of module headphone

+
kCODEC_SupportModuleSpeaker  +

codec capability of module speaker

+
kCODEC_SupportModuleLinein  +

codec capability of module linein

+
kCODEC_SupportModuleLineout  +

codec capability of module lineout

+
kCODEC_SupportModuleVref  +

codec capability of module vref

+
kCODEC_SupportModuleMicbias  +

codec capability of module mic bias

+
kCODEC_SupportModuleMic  +

codec capability of module mic bias

+
kCODEC_SupportModuleI2SIn  +

codec capability of module I2S in

+
kCODEC_SupportModuleI2SOut  +

codec capability of module I2S out

+
kCODEC_SupportModuleMixer  +

codec capability of module mixer

+
kCODEC_SupportModuleI2SInSwitchInterface  +

codec capability of module I2S in switch interface

+
kCODEC_SupportPlayChannelLeft0  +

codec capability of play channel left 0

+
kCODEC_SupportPlayChannelRight0  +

codec capability of play channel right 0

+
kCODEC_SupportPlayChannelLeft1  +

codec capability of play channel left 1

+
kCODEC_SupportPlayChannelRight1  +

codec capability of play channel right 1

+
kCODEC_SupportPlayChannelLeft2  +

codec capability of play channel left 2

+
kCODEC_SupportPlayChannelRight2  +

codec capability of play channel right 2

+
kCODEC_SupportPlayChannelLeft3  +

codec capability of play channel left 3

+
kCODEC_SupportPlayChannelRight3  +

codec capability of play channel right 3

+
kCODEC_SupportPlaySourcePGA  +

codec capability of set playback source PGA

+
kCODEC_SupportPlaySourceInput  +

codec capability of set playback source INPUT

+
kCODEC_SupportPlaySourceDAC  +

codec capability of set playback source DAC

+
kCODEC_SupportPlaySourceMixerIn  +

codec capability of set play source Mixer in

+
kCODEC_SupportPlaySourceMixerInLeft  +

codec capability of set play source Mixer in left

+
kCODEC_SupportPlaySourceMixerInRight  +

codec capability of set play source Mixer in right

+
kCODEC_SupportPlaySourceAux  +

codec capability of set play source aux

+
kCODEC_SupportRecordSourceDifferentialLine  +

codec capability of record source differential line

+
kCODEC_SupportRecordSourceLineInput  +

codec capability of record source line input

+
kCODEC_SupportRecordSourceDifferentialMic  +

codec capability of record source differential mic

+
kCODEC_SupportRecordSourceDigitalMic  +

codec capability of record digital mic

+
kCODEC_SupportRecordSourceSingleEndMic  +

codec capability of single end mic

+
kCODEC_SupportRecordChannelLeft1  +

left record channel 1

+
kCODEC_SupportRecordChannelLeft2  +

left record channel 2

+
kCODEC_SupportRecordChannelLeft3  +

left record channel 3

+
kCODEC_SupportRecordChannelRight1  +

right record channel 1

+
kCODEC_SupportRecordChannelRight2  +

right record channel 2

+
kCODEC_SupportRecordChannelRight3  +

right record channel 3

+
+ +
+
+

Function Documentation

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status_t CODEC_Init (codec_handle_t * handle,
codec_config_t * config 
)
+
+
Parameters
+ + + +
handlecodec handle.
configcodec configurations.
+
+
+
Returns
kStatus_Success is success, else de-initial failed.
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+
+ +
+
+ + + + + + + + +
status_t CODEC_Deinit (codec_handle_t * handle)
+
+
Parameters
+ + +
handlecodec handle.
+
+
+
Returns
kStatus_Success is success, else de-initial failed.
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status_t CODEC_SetFormat (codec_handle_t * handle,
uint32_t mclk,
uint32_t sampleRate,
uint32_t bitWidth 
)
+
+
Parameters
+ + + + + +
handlecodec handle.
mclkmaster clock frequency in HZ.
sampleRatesample rate in HZ.
bitWidthbit width.
+
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+
Returns
kStatus_Success is success, else configure failed.
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status_t CODEC_ModuleControl (codec_handle_t * handle,
codec_module_ctrl_cmd_t cmd,
uint32_t data 
)
+
+

This function is used for codec module control, support switch digital interface cmd, can be expand to support codec module specific feature.

+
Parameters
+ + + + +
handlecodec handle.
cmdmodule control cmd, reference _codec_module_ctrl_cmd.
datavalue to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference codec specific driver for detail configurations.
+
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Returns
kStatus_Success is success, else configure failed.
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status_t CODEC_SetVolume (codec_handle_t * handle,
uint32_t channel,
uint32_t volume 
)
+
+
Parameters
+ + + + +
handlecodec handle.
channelaudio codec play channel, can be a value or combine value of _codec_play_channel.
volumevolume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value.
+
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Returns
kStatus_Success is success, else configure failed.
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status_t CODEC_SetMute (codec_handle_t * handle,
uint32_t channel,
bool mute 
)
+
+
Parameters
+ + + + +
handlecodec handle.
channelaudio codec play channel, can be a value or combine value of _codec_play_channel.
mutetrue is mute, false is unmute.
+
+
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Returns
kStatus_Success is success, else configure failed.
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status_t CODEC_SetPower (codec_handle_t * handle,
codec_module_t module,
bool powerOn 
)
+
+
Parameters
+ + + + +
handlecodec handle.
moduleaudio codec module.
powerOntrue is power on, false is power down.
+
+
+
Returns
kStatus_Success is success, else configure failed.
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status_t CODEC_SetRecord (codec_handle_t * handle,
uint32_t recordSource 
)
+
+
Parameters
+ + + +
handlecodec handle.
recordSourceaudio codec record source, can be a value or combine value of _codec_record_source.
+
+
+
Returns
kStatus_Success is success, else configure failed.
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status_t CODEC_SetRecordChannel (codec_handle_t * handle,
uint32_t leftRecordChannel,
uint32_t rightRecordChannel 
)
+
+
Parameters
+ + + + +
handlecodec handle.
leftRecordChannelaudio codec record channel, reference _codec_record_channel, can be a value combine of member in _codec_record_channel.
rightRecordChannelaudio codec record channel, reference _codec_record_channel, can be a value combine of member in _codec_record_channel.
+
+
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Returns
kStatus_Success is success, else configure failed.
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status_t CODEC_SetPlay (codec_handle_t * handle,
uint32_t playSource 
)
+
+
Parameters
+ + + +
handlecodec handle.
playSourceaudio codec play source, can be a value or combine value of _codec_play_source.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00009.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00009.js new file mode 100644 index 000000000..3d544bb9b --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00009.js @@ -0,0 +1,158 @@ +var a00009 = +[ + [ "CODEC Adapter", "a00109.html", null ], + [ "WM8524 Adapter", "a00107.html", "a00107" ], + [ "codec_config_t", "a00009.html#a00121", [ + [ "codecDevType", "a00009.html#a0f68e054507c31a257a298cc9839729e", null ], + [ "codecDevConfig", "a00009.html#a6b9cc87b16b5275a006f34477a04f96e", null ] + ] ], + [ "codec_capability_t", "a00009.html#a00120", [ + [ "codecModuleCapability", "a00009.html#a3309e0df5a46d24b5bf533f792276169", null ], + [ "codecPlayCapability", "a00009.html#acda24c6b9b8efe9624996cee729ccecb", null ], + [ "codecRecordCapability", "a00009.html#a5df326e2f2b2e3c02e74f4ca53302176", null ] + ] ], + [ "codec_handle_t", "a00009.html#a00112", [ + [ "codecConfig", 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"a00009.html#gaa1cf75fe8598db6a6a9e33b56421a725", null ], + [ "CODEC_SetRecord", "a00009.html#ga6f348297e309b371c512b1c025f7aba7", null ], + [ "CODEC_SetRecordChannel", "a00009.html#ga22e45cee1bd24d656f16311bfa8bc7d7", null ], + [ "CODEC_SetPlay", "a00009.html#ga691cf0f3517139c6ad8f43918de8ea86", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00010.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00010.html new file mode 100644 index 000000000..aad3bde29 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00010.html @@ -0,0 +1,2353 @@ + + + + + + +MCUXpresso SDK API Reference Manual: ECSPI Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Macros | +Typedefs | +Enumerations | +Functions
+
+
ECSPI Driver
ECSPI: Enhanced Configurable Serial Peripheral Interface Driver
+
+
+

Overview

+

ECSPI driver includes functional APIs and transactional APIs.

+

Functional APIs are feature/property target low level APIs. Functional APIs can be used for ECSPI initialization/configuration/operation for optimization/customization purpose. Using the functional API requires the knowledge of the SPI peripheral and how to organize functional APIs to meet the application requirements. All functional API use the peripheral base address as the first parameter. ECSPI functional operation groups provide the functional API set.

+

Transactional APIs are transaction target high level APIs. Transactional APIs can be used to enable the peripheral and in the application if the code size and performance of transactional APIs satisfy the requirements. If the code size and performance are a critical requirement, see the transactional API implementation and write a custom code. All transactional APIs use the spi_handle_t as the first parameter. Initialize the handle by calling the SPI_MasterTransferCreateHandle() or SPI_SlaveTransferCreateHandle() API.

+

Transactional APIs support asynchronous transfer. This means that the functions SPI_MasterTransferNonBlocking() and SPI_SlaveTransferNonBlocking() set up the interrupt for data transfer. When the transfer completes, the upper layer is notified through a callback function with the kStatus_SPI_Idle status.

+

+Typical use case

+

+SPI master transfer using polling method

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/ecspi

+

+SPI master transfer using an interrupt method

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/ecspi

+ + + + + + + + + + + + + + + + + +

+Data Structures

struct  ecspi_channel_config_t
 ECSPI user channel configure structure. More...
 
struct  ecspi_master_config_t
 ECSPI master configure structure. More...
 
struct  ecspi_slave_config_t
 ECSPI slave configure structure. More...
 
struct  ecspi_transfer_t
 ECSPI transfer structure. More...
 
struct  ecspi_master_handle_t
 ECSPI master handle structure. More...
 
+ + + + + + + +

+Macros

#define ECSPI_DUMMYDATA   (0xFFFFFFFFU)
 ECSPI dummy transfer data, the data is sent while txBuff is NULL. More...
 
#define SPI_RETRY_TIMES   0U /* Define to zero means keep waiting until the flag is assert/deassert. */
 Retry times for waiting flag. More...
 
+ + + + + + + + + + +

+Typedefs

+typedef ecspi_master_handle_t ecspi_slave_handle_t
 Slave handle is the same with master handle.
 
+typedef void(* ecspi_master_callback_t )(ECSPI_Type *base, ecspi_master_handle_t *handle, status_t status, void *userData)
 ECSPI master callback for finished transmit.
 
+typedef void(* ecspi_slave_callback_t )(ECSPI_Type *base, ecspi_slave_handle_t *handle, status_t status, void *userData)
 ECSPI slave callback for finished transmit.
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Enumerations

enum  {
+  kStatus_ECSPI_Busy = MAKE_STATUS(kStatusGroup_ECSPI, 0), +
+  kStatus_ECSPI_Idle = MAKE_STATUS(kStatusGroup_ECSPI, 1), +
+  kStatus_ECSPI_Error = MAKE_STATUS(kStatusGroup_ECSPI, 2), +
+  kStatus_ECSPI_HardwareOverFlow = MAKE_STATUS(kStatusGroup_ECSPI, 3), +
+  kStatus_ECSPI_Timeout = MAKE_STATUS(kStatusGroup_ECSPI, 4) +
+ }
 Return status for the ECSPI driver. More...
 
enum  ecspi_clock_polarity_t {
+  kECSPI_PolarityActiveHigh = 0x0U, +
+  kECSPI_PolarityActiveLow +
+ }
 ECSPI clock polarity configuration. More...
 
enum  ecspi_clock_phase_t {
+  kECSPI_ClockPhaseFirstEdge, +
+  kECSPI_ClockPhaseSecondEdge +
+ }
 ECSPI clock phase configuration. More...
 
enum  {
+  kECSPI_TxfifoEmptyInterruptEnable = ECSPI_INTREG_TEEN_MASK, +
+  kECSPI_TxFifoDataRequstInterruptEnable = ECSPI_INTREG_TDREN_MASK, +
+  kECSPI_TxFifoFullInterruptEnable = ECSPI_INTREG_TFEN_MASK, +
+  kECSPI_RxFifoReadyInterruptEnable = ECSPI_INTREG_RREN_MASK, +
+  kECSPI_RxFifoDataRequstInterruptEnable = ECSPI_INTREG_RDREN_MASK, +
+  kECSPI_RxFifoFullInterruptEnable = ECSPI_INTREG_RFEN_MASK, +
+  kECSPI_RxFifoOverFlowInterruptEnable = ECSPI_INTREG_ROEN_MASK, +
+  kECSPI_TransferCompleteInterruptEnable = ECSPI_INTREG_TCEN_MASK, +
+  kECSPI_AllInterruptEnable +
+ }
 ECSPI interrupt sources. More...
 
enum  {
+  kECSPI_TxfifoEmptyFlag = ECSPI_STATREG_TE_MASK, +
+  kECSPI_TxFifoDataRequstFlag = ECSPI_STATREG_TDR_MASK, +
+  kECSPI_TxFifoFullFlag = ECSPI_STATREG_TF_MASK, +
+  kECSPI_RxFifoReadyFlag = ECSPI_STATREG_RR_MASK, +
+  kECSPI_RxFifoDataRequstFlag = ECSPI_STATREG_RDR_MASK, +
+  kECSPI_RxFifoFullFlag = ECSPI_STATREG_RF_MASK, +
+  kECSPI_RxFifoOverFlowFlag = ECSPI_STATREG_RO_MASK, +
+  kECSPI_TransferCompleteFlag = ECSPI_STATREG_TC_MASK +
+ }
 ECSPI status flags. More...
 
enum  {
+  kECSPI_TxDmaEnable = ECSPI_DMAREG_TEDEN_MASK, +
+  kECSPI_RxDmaEnable = ECSPI_DMAREG_RXDEN_MASK, +
+  kECSPI_DmaAllEnable = (ECSPI_DMAREG_TEDEN_MASK | ECSPI_DMAREG_RXDEN_MASK) +
+ }
 ECSPI DMA enable. More...
 
enum  ecspi_Data_ready_t {
+  kECSPI_DataReadyIgnore = 0x0U, +
+  kECSPI_DataReadyFallingEdge, +
+  kECSPI_DataReadyLowLevel +
+ }
 ECSPI SPI_RDY signal configuration. More...
 
enum  ecspi_channel_source_t {
+  kECSPI_Channel0 = 0x0U, +
+  kECSPI_Channel1, +
+  kECSPI_Channel2, +
+  kECSPI_Channel3 +
+ }
 ECSPI channel select source. More...
 
enum  ecspi_master_slave_mode_t {
+  kECSPI_Slave = 0U, +
+  kECSPI_Master +
+ }
 ECSPI master or slave mode configuration. More...
 
enum  ecspi_data_line_inactive_state_t {
+  kECSPI_DataLineInactiveStateHigh = 0x0U, +
+  kECSPI_DataLineInactiveStateLow +
+ }
 ECSPI data line inactive state configuration. More...
 
enum  ecspi_clock_inactive_state_t {
+  kECSPI_ClockInactiveStateLow = 0x0U, +
+  kECSPI_ClockInactiveStateHigh +
+ }
 ECSPI clock inactive state configuration. More...
 
enum  ecspi_chip_select_active_state_t {
+  kECSPI_ChipSelectActiveStateLow = 0x0U, +
+  kECSPI_ChipSelectActiveStateHigh +
+ }
 ECSPI active state configuration. More...
 
enum  ecspi_sample_period_clock_source_t {
+  kECSPI_spiClock = 0x0U, +
+  kECSPI_lowFreqClock +
+ }
 ECSPI sample period clock configuration. More...
 
+ + + + +

+Functions

uint32_t ECSPI_GetInstance (ECSPI_Type *base)
 Get the instance for ECSPI module. More...
 
+ + + + +

+Driver version

#define FSL_ECSPI_DRIVER_VERSION   (MAKE_VERSION(2, 2, 0))
 ECSPI driver version. More...
 
+ + + + + + + + + + + + + + + + + + + +

+Initialization and deinitialization

void ECSPI_MasterGetDefaultConfig (ecspi_master_config_t *config)
 Sets the ECSPI configuration structure to default values. More...
 
void ECSPI_MasterInit (ECSPI_Type *base, const ecspi_master_config_t *config, uint32_t srcClock_Hz)
 Initializes the ECSPI with configuration. More...
 
void ECSPI_SlaveGetDefaultConfig (ecspi_slave_config_t *config)
 Sets the ECSPI configuration structure to default values. More...
 
void ECSPI_SlaveInit (ECSPI_Type *base, const ecspi_slave_config_t *config)
 Initializes the ECSPI with configuration. More...
 
void ECSPI_Deinit (ECSPI_Type *base)
 De-initializes the ECSPI. More...
 
static void ECSPI_Enable (ECSPI_Type *base, bool enable)
 Enables or disables the ECSPI. More...
 
+ + + + + + + +

+Status

static uint32_t ECSPI_GetStatusFlags (ECSPI_Type *base)
 Gets the status flag. More...
 
static void ECSPI_ClearStatusFlags (ECSPI_Type *base, uint32_t mask)
 Clear the status flag. More...
 
+ + + + + + + +

+Interrupts

static void ECSPI_EnableInterrupts (ECSPI_Type *base, uint32_t mask)
 Enables the interrupt for the ECSPI. More...
 
static void ECSPI_DisableInterrupts (ECSPI_Type *base, uint32_t mask)
 Disables the interrupt for the ECSPI. More...
 
+ + + + +

+Software Reset

static void ECSPI_SoftwareReset (ECSPI_Type *base)
 Software reset. More...
 
+ + + + +

+Channel mode check

static bool ECSPI_IsMaster (ECSPI_Type *base, ecspi_channel_source_t channel)
 Mode check. More...
 
+ + + + +

+DMA Control

static void ECSPI_EnableDMA (ECSPI_Type *base, uint32_t mask, bool enable)
 Enables the DMA source for ECSPI. More...
 
+ + + + + + + +

+FIFO Operation

static uint8_t ECSPI_GetTxFifoCount (ECSPI_Type *base)
 Get the Tx FIFO data count. More...
 
static uint8_t ECSPI_GetRxFifoCount (ECSPI_Type *base)
 Get the Rx FIFO data count. More...
 
+ + + + + + + + + + + + + + + + + + + +

+Bus Operations

static void ECSPI_SetChannelSelect (ECSPI_Type *base, ecspi_channel_source_t channel)
 Set channel select for transfer. More...
 
void ECSPI_SetChannelConfig (ECSPI_Type *base, ecspi_channel_source_t channel, const ecspi_channel_config_t *config)
 Set channel select configuration for transfer. More...
 
void ECSPI_SetBaudRate (ECSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
 Sets the baud rate for ECSPI transfer. More...
 
status_t ECSPI_WriteBlocking (ECSPI_Type *base, uint32_t *buffer, size_t size)
 Sends a buffer of data bytes using a blocking method. More...
 
static void ECSPI_WriteData (ECSPI_Type *base, uint32_t data)
 Writes a data into the ECSPI data register. More...
 
static uint32_t ECSPI_ReadData (ECSPI_Type *base)
 Gets a data from the ECSPI data register. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Transactional

void ECSPI_MasterTransferCreateHandle (ECSPI_Type *base, ecspi_master_handle_t *handle, ecspi_master_callback_t callback, void *userData)
 Initializes the ECSPI master handle. More...
 
status_t ECSPI_MasterTransferBlocking (ECSPI_Type *base, ecspi_transfer_t *xfer)
 Transfers a block of data using a polling method. More...
 
status_t ECSPI_MasterTransferNonBlocking (ECSPI_Type *base, ecspi_master_handle_t *handle, ecspi_transfer_t *xfer)
 Performs a non-blocking ECSPI interrupt transfer. More...
 
status_t ECSPI_MasterTransferGetCount (ECSPI_Type *base, ecspi_master_handle_t *handle, size_t *count)
 Gets the bytes of the ECSPI interrupt transferred. More...
 
void ECSPI_MasterTransferAbort (ECSPI_Type *base, ecspi_master_handle_t *handle)
 Aborts an ECSPI transfer using interrupt. More...
 
void ECSPI_MasterTransferHandleIRQ (ECSPI_Type *base, ecspi_master_handle_t *handle)
 Interrupts the handler for the ECSPI. More...
 
void ECSPI_SlaveTransferCreateHandle (ECSPI_Type *base, ecspi_slave_handle_t *handle, ecspi_slave_callback_t callback, void *userData)
 Initializes the ECSPI slave handle. More...
 
static status_t ECSPI_SlaveTransferNonBlocking (ECSPI_Type *base, ecspi_slave_handle_t *handle, ecspi_transfer_t *xfer)
 Performs a non-blocking ECSPI slave interrupt transfer. More...
 
static status_t ECSPI_SlaveTransferGetCount (ECSPI_Type *base, ecspi_slave_handle_t *handle, size_t *count)
 Gets the bytes of the ECSPI interrupt transferred. More...
 
static void ECSPI_SlaveTransferAbort (ECSPI_Type *base, ecspi_slave_handle_t *handle)
 Aborts an ECSPI slave transfer using interrupt. More...
 
void ECSPI_SlaveTransferHandleIRQ (ECSPI_Type *base, ecspi_slave_handle_t *handle)
 Interrupts a handler for the ECSPI slave. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct ecspi_channel_config_t
+
+
+ + + + + + + + + + + + + + + + + + + +

Data Fields

+ecspi_master_slave_mode_t channelMode
 Channel mode.
 
+ecspi_clock_inactive_state_t clockInactiveState
 Clock line (SCLK) inactive state.
 
+ecspi_data_line_inactive_state_t dataLineInactiveState
 Data line (MOSI&MISO) inactive state.
 
+ecspi_chip_select_active_state_t chipSlectActiveState
 Chip select(SS) line active state.
 
+ecspi_clock_polarity_t polarity
 Clock polarity.
 
+ecspi_clock_phase_t phase
 Clock phase.
 
+ +
+
+ +
+
+ + + + +
struct ecspi_master_config_t
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

+ecspi_channel_source_t channel
 Channel number.
 
+ecspi_channel_config_t channelConfig
 Channel configuration.
 
+ecspi_sample_period_clock_source_t samplePeriodClock
 Sample period clock source.
 
+uint8_t burstLength
 Burst length.
 
+uint8_t chipSelectDelay
 SS delay time.
 
+uint16_t samplePeriod
 Sample period.
 
+uint8_t txFifoThreshold
 TX Threshold.
 
+uint8_t rxFifoThreshold
 RX Threshold.
 
+uint32_t baudRate_Bps
 ECSPI baud rate for master mode.
 
bool enableLoopback
 Enable the ECSPI loopback test. More...
 
+

Field Documentation

+ +
+
+ + + + +
bool ecspi_master_config_t::enableLoopback
+
+ +
+
+ +
+
+ +
+
+ + + + +
struct ecspi_slave_config_t
+
+
+ + + + + + + + + + + + + +

Data Fields

+uint8_t burstLength
 Burst length.
 
+uint8_t txFifoThreshold
 TX Threshold.
 
+uint8_t rxFifoThreshold
 RX Threshold.
 
+ecspi_channel_config_t channelConfig
 Channel configuration.
 
+ +
+
+ +
+
+ + + + +
struct ecspi_transfer_t
+
+
+ + + + + + + + + + + + + +

Data Fields

+uint32_t * txData
 Send buffer.
 
+uint32_t * rxData
 Receive buffer.
 
+size_t dataSize
 Transfer bytes.
 
+ecspi_channel_source_t channel
 ECSPI channel select.
 
+ +
+
+ +
+
+ + + + +
struct _ecspi_master_handle
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

+ecspi_channel_source_t channel
 Channel number.
 
+uint32_t *volatile txData
 Transfer buffer.
 
+uint32_t *volatile rxData
 Receive buffer.
 
+volatile size_t txRemainingBytes
 Send data remaining in bytes.
 
+volatile size_t rxRemainingBytes
 Receive data remaining in bytes.
 
+volatile uint32_t state
 ECSPI internal state.
 
+size_t transferSize
 Bytes to be transferred.
 
+ecspi_master_callback_t callback
 ECSPI callback.
 
+void * userData
 Callback parameter.
 
+ +
+
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_ECSPI_DRIVER_VERSION   (MAKE_VERSION(2, 2, 0))
+
+ +
+
+ +
+
+ + + + +
#define ECSPI_DUMMYDATA   (0xFFFFFFFFU)
+
+ +
+
+ +
+
+ + + + +
#define SPI_RETRY_TIMES   0U /* Define to zero means keep waiting until the flag is assert/deassert. */
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
anonymous enum
+
+ + + + + + +
Enumerator
kStatus_ECSPI_Busy  +

ECSPI bus is busy.

+
kStatus_ECSPI_Idle  +

ECSPI is idle.

+
kStatus_ECSPI_Error  +

ECSPI error.

+
kStatus_ECSPI_HardwareOverFlow  +

ECSPI hardware overflow.

+
kStatus_ECSPI_Timeout  +

ECSPI timeout polling status flags.

+
+ +
+
+ +
+
+ + + + +
enum ecspi_clock_polarity_t
+
+ + + +
Enumerator
kECSPI_PolarityActiveHigh  +

Active-high ECSPI polarity high (idles low).

+
kECSPI_PolarityActiveLow  +

Active-low ECSPI polarity low (idles high).

+
+ +
+
+ +
+
+ + + + +
enum ecspi_clock_phase_t
+
+ + + +
Enumerator
kECSPI_ClockPhaseFirstEdge  +

First edge on SPSCK occurs at the middle of the first cycle of a data transfer.

+
kECSPI_ClockPhaseSecondEdge  +

First edge on SPSCK occurs at the start of the first cycle of a data transfer.

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+ + + + + + + + + + +
Enumerator
kECSPI_TxfifoEmptyInterruptEnable  +

Transmit FIFO buffer empty interrupt.

+
kECSPI_TxFifoDataRequstInterruptEnable  +

Transmit FIFO data requst interrupt.

+
kECSPI_TxFifoFullInterruptEnable  +

Transmit FIFO full interrupt.

+
kECSPI_RxFifoReadyInterruptEnable  +

Receiver FIFO ready interrupt.

+
kECSPI_RxFifoDataRequstInterruptEnable  +

Receiver FIFO data requst interrupt.

+
kECSPI_RxFifoFullInterruptEnable  +

Receiver FIFO full interrupt.

+
kECSPI_RxFifoOverFlowInterruptEnable  +

Receiver FIFO buffer overflow interrupt.

+
kECSPI_TransferCompleteInterruptEnable  +

Transfer complete interrupt.

+
kECSPI_AllInterruptEnable  +

All interrupt.

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+ + + + + + + + + +
Enumerator
kECSPI_TxfifoEmptyFlag  +

Transmit FIFO buffer empty flag.

+
kECSPI_TxFifoDataRequstFlag  +

Transmit FIFO data requst flag.

+
kECSPI_TxFifoFullFlag  +

Transmit FIFO full flag.

+
kECSPI_RxFifoReadyFlag  +

Receiver FIFO ready flag.

+
kECSPI_RxFifoDataRequstFlag  +

Receiver FIFO data requst flag.

+
kECSPI_RxFifoFullFlag  +

Receiver FIFO full flag.

+
kECSPI_RxFifoOverFlowFlag  +

Receiver FIFO buffer overflow flag.

+
kECSPI_TransferCompleteFlag  +

Transfer complete flag.

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+ + + + +
Enumerator
kECSPI_TxDmaEnable  +

Tx DMA request source.

+
kECSPI_RxDmaEnable  +

Rx DMA request source.

+
kECSPI_DmaAllEnable  +

All DMA request source.

+
+ +
+
+ +
+
+ + + + +
enum ecspi_Data_ready_t
+
+ + + + +
Enumerator
kECSPI_DataReadyIgnore  +

SPI_RDY signal is ignored.

+
kECSPI_DataReadyFallingEdge  +

SPI_RDY signal will be triggerd by the falling edge.

+
kECSPI_DataReadyLowLevel  +

SPI_RDY signal will be triggerd by a low level.

+
+ +
+
+ +
+
+ + + + +
enum ecspi_channel_source_t
+
+ + + + + +
Enumerator
kECSPI_Channel0  +

Channel 0 is selectd.

+
kECSPI_Channel1  +

Channel 1 is selectd.

+
kECSPI_Channel2  +

Channel 2 is selectd.

+
kECSPI_Channel3  +

Channel 3 is selectd.

+
+ +
+
+ +
+
+ + + + +
enum ecspi_master_slave_mode_t
+
+ + + +
Enumerator
kECSPI_Slave  +

ECSPI peripheral operates in slave mode.

+
kECSPI_Master  +

ECSPI peripheral operates in master mode.

+
+ +
+
+ +
+
+ + + + +
enum ecspi_data_line_inactive_state_t
+
+ + + +
Enumerator
kECSPI_DataLineInactiveStateHigh  +

The data line inactive state stays high.

+
kECSPI_DataLineInactiveStateLow  +

The data line inactive state stays low.

+
+ +
+
+ +
+
+ + + + +
enum ecspi_clock_inactive_state_t
+
+ + + +
Enumerator
kECSPI_ClockInactiveStateLow  +

The SCLK inactive state stays low.

+
kECSPI_ClockInactiveStateHigh  +

The SCLK inactive state stays high.

+
+ +
+
+ +
+
+ + + + +
enum ecspi_chip_select_active_state_t
+
+ + + +
Enumerator
kECSPI_ChipSelectActiveStateLow  +

The SS signal line active stays low.

+
kECSPI_ChipSelectActiveStateHigh  +

The SS signal line active stays high.

+
+ +
+
+ +
+
+ + + + +
enum ecspi_sample_period_clock_source_t
+
+ + + +
Enumerator
kECSPI_spiClock  +

The sample period clock source is SCLK.

+
kECSPI_lowFreqClock  +

The sample seriod clock source is low_frequency reference clock(32.768 kHz).

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t ECSPI_GetInstance (ECSPI_Type * base)
+
+
Parameters
+ + +
baseECSPI base address
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ECSPI_MasterGetDefaultConfig (ecspi_master_config_t * config)
+
+

The purpose of this API is to get the configuration structure initialized for use in ECSPI_MasterInit(). User may use the initialized structure unchanged in ECSPI_MasterInit, or modify some fields of the structure before calling ECSPI_MasterInit. After calling this API, the master is ready to transfer. Example:

+
ecspi_master_config_t config;
+
ECSPI_MasterGetDefaultConfig(&config);
+
Parameters
+ + +
configpointer to config structure
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void ECSPI_MasterInit (ECSPI_Type * base,
const ecspi_master_config_t * config,
uint32_t srcClock_Hz 
)
+
+

The configuration structure can be filled by user from scratch, or be set with default values by ECSPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. Example

+
ecspi_master_config_t config = {
+
.baudRate_Bps = 400000,
+
...
+
};
+
ECSPI_MasterInit(ECSPI0, &config);
+
Parameters
+ + + + +
baseECSPI base pointer
configpointer to master configuration structure
srcClock_HzSource clock frequency.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ECSPI_SlaveGetDefaultConfig (ecspi_slave_config_t * config)
+
+

The purpose of this API is to get the configuration structure initialized for use in ECSPI_SlaveInit(). User may use the initialized structure unchanged in ECSPI_SlaveInit(), or modify some fields of the structure before calling ECSPI_SlaveInit(). After calling this API, the master is ready to transfer. Example:

+
ecspi_Slaveconfig_t config;
+
ECSPI_SlaveGetDefaultConfig(&config);
+
Parameters
+ + +
configpointer to config structure
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ECSPI_SlaveInit (ECSPI_Type * base,
const ecspi_slave_config_t * config 
)
+
+

The configuration structure can be filled by user from scratch, or be set with default values by ECSPI_SlaveGetDefaultConfig(). After calling this API, the slave is ready to transfer. Example

+
ecspi_Salveconfig_t config = {
+
.baudRate_Bps = 400000,
+
...
+
};
+
ECSPI_SlaveInit(ECSPI1, &config);
+
Parameters
+ + + +
baseECSPI base pointer
configpointer to master configuration structure
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ECSPI_Deinit (ECSPI_Type * base)
+
+

Calling this API resets the ECSPI module, gates the ECSPI clock. The ECSPI module can't work unless calling the ECSPI_MasterInit/ECSPI_SlaveInit to initialize module.

+
Parameters
+ + +
baseECSPI base pointer
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void ECSPI_Enable (ECSPI_Type * base,
bool enable 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseECSPI base pointer
enablepass true to enable module, false to disable module
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t ECSPI_GetStatusFlags (ECSPI_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseECSPI base pointer
+
+
+
Returns
ECSPI Status, use status flag to AND _ecspi_flags could get the related status.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void ECSPI_ClearStatusFlags (ECSPI_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseECSPI base pointer
maskECSPI Status, use status flag to AND _ecspi_flags could get the related status.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void ECSPI_EnableInterrupts (ECSPI_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseECSPI base pointer
maskECSPI interrupt source. The parameter can be any combination of the following values:
    +
  • kECSPI_TxfifoEmptyInterruptEnable
    • +
  • kECSPI_TxFifoDataRequstInterruptEnable
    • +
  • kECSPI_TxFifoFullInterruptEnable
    • +
  • kECSPI_RxFifoReadyInterruptEnable
    • +
  • kECSPI_RxFifoDataRequstInterruptEnable
    • +
  • kECSPI_RxFifoFullInterruptEnable
    • +
  • kECSPI_RxFifoOverFlowInterruptEnable
    • +
  • kECSPI_TransferCompleteInterruptEnable
    • +
  • kECSPI_AllInterruptEnable
    • +
+
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void ECSPI_DisableInterrupts (ECSPI_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseECSPI base pointer
maskECSPI interrupt source. The parameter can be any combination of the following values:
    +
  • kECSPI_TxfifoEmptyInterruptEnable
    • +
  • kECSPI_TxFifoDataRequstInterruptEnable
    • +
  • kECSPI_TxFifoFullInterruptEnable
    • +
  • kECSPI_RxFifoReadyInterruptEnable
    • +
  • kECSPI_RxFifoDataRequstInterruptEnable
    • +
  • kECSPI_RxFifoFullInterruptEnable
    • +
  • kECSPI_RxFifoOverFlowInterruptEnable
    • +
  • kECSPI_TransferCompleteInterruptEnable
    • +
  • kECSPI_AllInterruptEnable
    • +
+
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void ECSPI_SoftwareReset (ECSPI_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseECSPI base pointer
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static bool ECSPI_IsMaster (ECSPI_Type * base,
ecspi_channel_source_t channel 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseECSPI base pointer
channelECSPI channel source
+
+
+
Returns
mode of channel
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void ECSPI_EnableDMA (ECSPI_Type * base,
uint32_t mask,
bool enable 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseECSPI base pointer
maskECSPI DMA source. The parameter can be any of the following values:
    +
  • kECSPI_TxDmaEnable
    • +
  • kECSPI_RxDmaEnable
    • +
  • kECSPI_DmaAllEnable
    • +
+
enableTrue means enable DMA, false means disable DMA
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint8_t ECSPI_GetTxFifoCount (ECSPI_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseECSPI base pointer.
+
+
+
Returns
the number of words in Tx FIFO buffer.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint8_t ECSPI_GetRxFifoCount (ECSPI_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseECSPI base pointer.
+
+
+
Returns
the number of words in Rx FIFO buffer.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void ECSPI_SetChannelSelect (ECSPI_Type * base,
ecspi_channel_source_t channel 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseECSPI base pointer
channelChannel source.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void ECSPI_SetChannelConfig (ECSPI_Type * base,
ecspi_channel_source_t channel,
const ecspi_channel_config_t * config 
)
+
+

The purpose of this API is to set the channel will be use to transfer. User may use this API after instance has been initialized or before transfer start. The configuration structure ecspi_channel_config can be filled by user from scratch. After calling this API, user can select this channel as transfer channel.

+
Parameters
+ + + + +
baseECSPI base pointer
channelChannel source.
configConfiguration struct of channel
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void ECSPI_SetBaudRate (ECSPI_Type * base,
uint32_t baudRate_Bps,
uint32_t srcClock_Hz 
)
+
+

This is only used in master.

+
Parameters
+ + + + +
baseECSPI base pointer
baudRate_Bpsbaud rate needed in Hz.
srcClock_HzECSPI source clock frequency in Hz.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t ECSPI_WriteBlocking (ECSPI_Type * base,
uint32_t * buffer,
size_t size 
)
+
+
Note
This function blocks via polling until all bytes have been sent.
+
Parameters
+ + + + +
baseECSPI base pointer
bufferThe data bytes to send
sizeThe number of data bytes to send
+
+
+
Return values
+ + + +
kStatus_SuccessSuccessfully start a transfer.
kStatus_ECSPI_TimeoutThe transfer timed out and was aborted.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void ECSPI_WriteData (ECSPI_Type * base,
uint32_t data 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseECSPI base pointer
dataData needs to be write.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t ECSPI_ReadData (ECSPI_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseECSPI base pointer
+
+
+
Returns
Data in the register.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void ECSPI_MasterTransferCreateHandle (ECSPI_Type * base,
ecspi_master_handle_t * handle,
ecspi_master_callback_t callback,
void * userData 
)
+
+

This function initializes the ECSPI master handle which can be used for other ECSPI master transactional APIs. Usually, for a specified ECSPI instance, call this API once to get the initialized handle.

+
Parameters
+ + + + + +
baseECSPI peripheral base address.
handleECSPI handle pointer.
callbackCallback function.
userDataUser data.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t ECSPI_MasterTransferBlocking (ECSPI_Type * base,
ecspi_transfer_t * xfer 
)
+
+
Parameters
+ + + +
baseSPI base pointer
xferpointer to spi_xfer_config_t structure
+
+
+
Return values
+ + + + +
kStatus_SuccessSuccessfully start a transfer.
kStatus_InvalidArgumentInput argument is invalid.
kStatus_ECSPI_TimeoutThe transfer timed out and was aborted.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t ECSPI_MasterTransferNonBlocking (ECSPI_Type * base,
ecspi_master_handle_t * handle,
ecspi_transfer_t * xfer 
)
+
+
Note
The API immediately returns after transfer initialization is finished.
+
+If ECSPI transfer data frame size is 16 bits, the transfer size cannot be an odd number.
+
Parameters
+ + + + +
baseECSPI peripheral base address.
handlepointer to ecspi_master_handle_t structure which stores the transfer state
xferpointer to ecspi_transfer_t structure
+
+
+
Return values
+ + + + +
kStatus_SuccessSuccessfully start a transfer.
kStatus_InvalidArgumentInput argument is invalid.
kStatus_ECSPI_BusyECSPI is not idle, is running another transfer.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t ECSPI_MasterTransferGetCount (ECSPI_Type * base,
ecspi_master_handle_t * handle,
size_t * count 
)
+
+
Parameters
+ + + + +
baseECSPI peripheral base address.
handlePointer to ECSPI transfer handle, this should be a static variable.
countTransferred bytes of ECSPI master.
+
+
+
Return values
+ + + +
kStatus_ECSPI_SuccessSucceed get the transfer count.
kStatus_NoTransferInProgressThere is not a non-blocking transaction currently in progress.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ECSPI_MasterTransferAbort (ECSPI_Type * base,
ecspi_master_handle_t * handle 
)
+
+
Parameters
+ + + +
baseECSPI peripheral base address.
handlePointer to ECSPI transfer handle, this should be a static variable.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ECSPI_MasterTransferHandleIRQ (ECSPI_Type * base,
ecspi_master_handle_t * handle 
)
+
+
Parameters
+ + + +
baseECSPI peripheral base address.
handlepointer to ecspi_master_handle_t structure which stores the transfer state.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void ECSPI_SlaveTransferCreateHandle (ECSPI_Type * base,
ecspi_slave_handle_t * handle,
ecspi_slave_callback_t callback,
void * userData 
)
+
+

This function initializes the ECSPI slave handle which can be used for other ECSPI slave transactional APIs. Usually, for a specified ECSPI instance, call this API once to get the initialized handle.

+
Parameters
+ + + + + +
baseECSPI peripheral base address.
handleECSPI handle pointer.
callbackCallback function.
userDataUser data.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static status_t ECSPI_SlaveTransferNonBlocking (ECSPI_Type * base,
ecspi_slave_handle_t * handle,
ecspi_transfer_t * xfer 
)
+ 		+inlinestatic
+
+
Note
The API returns immediately after the transfer initialization is finished.
+
Parameters
+ + + + +
baseECSPI peripheral base address.
handlepointer to ecspi_master_handle_t structure which stores the transfer state
xferpointer to ecspi_transfer_t structure
+
+
+
Return values
+ + + + +
kStatus_SuccessSuccessfully start a transfer.
kStatus_InvalidArgumentInput argument is invalid.
kStatus_ECSPI_BusyECSPI is not idle, is running another transfer.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static status_t ECSPI_SlaveTransferGetCount (ECSPI_Type * base,
ecspi_slave_handle_t * handle,
size_t * count 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseECSPI peripheral base address.
handlePointer to ECSPI transfer handle, this should be a static variable.
countTransferred bytes of ECSPI slave.
+
+
+
Return values
+ + + +
kStatus_ECSPI_SuccessSucceed get the transfer count.
kStatus_NoTransferInProgressThere is not a non-blocking transaction currently in progress.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void ECSPI_SlaveTransferAbort (ECSPI_Type * base,
ecspi_slave_handle_t * handle 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseECSPI peripheral base address.
handlePointer to ECSPI transfer handle, this should be a static variable.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ECSPI_SlaveTransferHandleIRQ (ECSPI_Type * base,
ecspi_slave_handle_t * handle 
)
+
+
Parameters
+ + + +
baseECSPI peripheral base address.
handlepointer to ecspi_slave_handle_t structure which stores the transfer state
+
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00010.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00010.js new file mode 100644 index 000000000..a11451bdf --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00010.js @@ -0,0 +1,150 @@ +var a00010 = +[ + [ "ecspi_channel_config_t", "a00010.html#a00122", [ + [ "channelMode", "a00010.html#ae4b6b855f5d5202d69995657f6b495f9", null ], + [ "clockInactiveState", "a00010.html#aa08cd8243e60e65e43e5425c8a560a07", null ], + [ "dataLineInactiveState", "a00010.html#a9ad22b79de30e56cb705c239c7bb62fd", null ], + [ "chipSlectActiveState", "a00010.html#a373701fa6b25844c20404dbda4b08612", null ], + [ "polarity", "a00010.html#aa6327b0a05d54c85c01ca246e86b50c4", null ], + [ "phase", "a00010.html#aad4e0d3e01790b01e7c0ca7c6c5920af", null ] + ] ], + [ "ecspi_master_config_t", "a00010.html#a00123", [ + [ "channel", "a00010.html#ab7f80a7f7b11d5c4d3d08a39199dacfd", null ], + [ "channelConfig", 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"ECSPI_Deinit", "a00010.html#ga684087107b71beeb41401d78f4983685", null ], + [ "ECSPI_Enable", "a00010.html#ga2e4d1cabe92e6f4b35c540ba3c8b0308", null ], + [ "ECSPI_GetStatusFlags", "a00010.html#gacebe36e1f278e18350d4bf971af2fc7e", null ], + [ "ECSPI_ClearStatusFlags", "a00010.html#gaa437a7c7a740dfabb3f2296b0e989adf", null ], + [ "ECSPI_EnableInterrupts", "a00010.html#gad3f9f4d11b99c104503aa4b7dda53833", null ], + [ "ECSPI_DisableInterrupts", "a00010.html#gac9bac11d5dcd977a97a0607d77791ba1", null ], + [ "ECSPI_SoftwareReset", "a00010.html#gadc13d57141df32cefbb4b0040e6404f6", null ], + [ "ECSPI_IsMaster", "a00010.html#ga92268573eb4bcbb82d4cc2417ac4933a", null ], + [ "ECSPI_EnableDMA", "a00010.html#gab2f7c2269309fd273f8e41f11833e313", null ], + [ "ECSPI_GetTxFifoCount", "a00010.html#ga88e66c4f5f15754fb7ba7fc016f6dc41", null ], + [ "ECSPI_GetRxFifoCount", "a00010.html#gaded76e7db6b46c3a53922a528d755c57", null ], + [ "ECSPI_SetChannelSelect", "a00010.html#ga3175e7552062e74bffa3538195b8df6a", null ], + [ "ECSPI_SetChannelConfig", "a00010.html#gaa4a223ca2612f4e73fae0982afcff226", null ], + [ "ECSPI_SetBaudRate", "a00010.html#ga4b5b00f89c45cb1164af2a4685e984d5", null ], + [ "ECSPI_WriteBlocking", "a00010.html#gab0233870c51a5096af0b247ec99014d0", null ], + [ "ECSPI_WriteData", "a00010.html#ga99b6a9e30ad735c3634d60b81c500c2e", null ], + [ "ECSPI_ReadData", "a00010.html#ga3c50b084acf2fe74f19575cc10069bbe", null ], + [ "ECSPI_MasterTransferCreateHandle", "a00010.html#ga1ab5918361a605a7f0467bcb3d1760ac", null ], + [ "ECSPI_MasterTransferBlocking", "a00010.html#ga20f68343a19b3772e814a8ee61d7be7f", null ], + [ "ECSPI_MasterTransferNonBlocking", "a00010.html#gad77408a45d6982958068a49149ac60b6", null ], + [ "ECSPI_MasterTransferGetCount", "a00010.html#ga85aef57f678a64cbe3e718ec59043841", null ], + [ "ECSPI_MasterTransferAbort", "a00010.html#gacda4c03d5c4b1c2ba78578ff5213a2f5", null ], + [ "ECSPI_MasterTransferHandleIRQ", "a00010.html#gada190053bf71b9ce53a619b7d6c7c245", null ], + [ "ECSPI_SlaveTransferCreateHandle", "a00010.html#ga63b3bb057b97b1115ad082e9e056632b", null ], + [ "ECSPI_SlaveTransferNonBlocking", "a00010.html#gad4a51681f1b62b0f26be844a209e6e10", null ], + [ "ECSPI_SlaveTransferGetCount", "a00010.html#gacea2421bc4aaee6e9cc19f7d4f48e3e5", null ], + [ "ECSPI_SlaveTransferAbort", "a00010.html#ga2512b5ae1d6591e8ba1d70f15221c689", null ], + [ "ECSPI_SlaveTransferHandleIRQ", "a00010.html#ga8bc32a537b99b7e988228650957f25d8", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00011.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00011.html new file mode 100644 index 000000000..f30c5d513 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00011.html @@ -0,0 +1,1239 @@ + + + + + + +MCUXpresso SDK API Reference Manual: GPIO: General-Purpose Input/Output Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Enumerations
+
+
GPIO: General-Purpose Input/Output Driver
+
+
+

Overview

+

The MCUXpresso SDK provides a peripheral driver for the General-Purpose Input/Output (GPIO) module of MCUXpresso SDK devices.

+

+Typical use case

+

+Input Operation

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/gpio

+ + + + + +

+Data Structures

struct  gpio_pin_config_t
 GPIO Init structure definition. More...
 
+ + + + + + + +

+Enumerations

enum  gpio_pin_direction_t {
+  kGPIO_DigitalInput = 0U, +
+  kGPIO_DigitalOutput = 1U +
+ }
 GPIO direction definition. More...
 
enum  gpio_interrupt_mode_t {
+  kGPIO_NoIntmode = 0U, +
+  kGPIO_IntLowLevel = 1U, +
+  kGPIO_IntHighLevel = 2U, +
+  kGPIO_IntRisingEdge = 3U, +
+  kGPIO_IntFallingEdge = 4U, +
+  kGPIO_IntRisingOrFallingEdge = 5U +
+ }
 GPIO interrupt mode definition. More...
 
+ + + + +

+Driver version

#define FSL_GPIO_DRIVER_VERSION   (MAKE_VERSION(2, 0, 5))
 GPIO driver version. More...
 
+ + + + +

+GPIO Initialization and Configuration functions

void GPIO_PinInit (GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config)
 Initializes the GPIO peripheral according to the specified parameters in the initConfig. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+GPIO Reads and Write Functions

void GPIO_PinWrite (GPIO_Type *base, uint32_t pin, uint8_t output)
 Sets the output level of the individual GPIO pin to logic 1 or 0. More...
 
static void GPIO_WritePinOutput (GPIO_Type *base, uint32_t pin, uint8_t output)
 Sets the output level of the individual GPIO pin to logic 1 or 0. More...
 
static void GPIO_PortSet (GPIO_Type *base, uint32_t mask)
 Sets the output level of the multiple GPIO pins to the logic 1. More...
 
static void GPIO_SetPinsOutput (GPIO_Type *base, uint32_t mask)
 Sets the output level of the multiple GPIO pins to the logic 1. More...
 
static void GPIO_PortClear (GPIO_Type *base, uint32_t mask)
 Sets the output level of the multiple GPIO pins to the logic 0. More...
 
static void GPIO_ClearPinsOutput (GPIO_Type *base, uint32_t mask)
 Sets the output level of the multiple GPIO pins to the logic 0. More...
 
static void GPIO_PortToggle (GPIO_Type *base, uint32_t mask)
 Reverses the current output logic of the multiple GPIO pins. More...
 
static uint32_t GPIO_PinRead (GPIO_Type *base, uint32_t pin)
 Reads the current input value of the GPIO port. More...
 
static uint32_t GPIO_ReadPinInput (GPIO_Type *base, uint32_t pin)
 Reads the current input value of the GPIO port. More...
 
+ + + + + + + +

+GPIO Reads Pad Status Functions

static uint8_t GPIO_PinReadPadStatus (GPIO_Type *base, uint32_t pin)
 Reads the current GPIO pin pad status. More...
 
static uint8_t GPIO_ReadPadStatus (GPIO_Type *base, uint32_t pin)
 Reads the current GPIO pin pad status. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Interrupts and flags management functions

void GPIO_PinSetInterruptConfig (GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
 Sets the current pin interrupt mode. More...
 
static void GPIO_SetPinInterruptConfig (GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
 Sets the current pin interrupt mode. More...
 
static void GPIO_PortEnableInterrupts (GPIO_Type *base, uint32_t mask)
 Enables the specific pin interrupt. More...
 
static void GPIO_EnableInterrupts (GPIO_Type *base, uint32_t mask)
 Enables the specific pin interrupt. More...
 
static void GPIO_PortDisableInterrupts (GPIO_Type *base, uint32_t mask)
 Disables the specific pin interrupt. More...
 
static void GPIO_DisableInterrupts (GPIO_Type *base, uint32_t mask)
 Disables the specific pin interrupt. More...
 
static uint32_t GPIO_PortGetInterruptFlags (GPIO_Type *base)
 Reads individual pin interrupt status. More...
 
static uint32_t GPIO_GetPinsInterruptFlags (GPIO_Type *base)
 Reads individual pin interrupt status. More...
 
static void GPIO_PortClearInterruptFlags (GPIO_Type *base, uint32_t mask)
 Clears pin interrupt flag. More...
 
static void GPIO_ClearPinsInterruptFlags (GPIO_Type *base, uint32_t mask)
 Clears pin interrupt flag. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct gpio_pin_config_t
+
+
+ + + + + + + + + + +

Data Fields

gpio_pin_direction_t direction
 Specifies the pin direction. More...
 
+uint8_t outputLogic
 Set a default output logic, which has no use in input.
 
gpio_interrupt_mode_t interruptMode
 Specifies the pin interrupt mode, a value of gpio_interrupt_mode_t. More...
 
+

Field Documentation

+ +
+
+ + + + +
gpio_pin_direction_t gpio_pin_config_t::direction
+
+ +
+
+ +
+
+ + + + +
gpio_interrupt_mode_t gpio_pin_config_t::interruptMode
+
+ +
+
+ +
+
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_GPIO_DRIVER_VERSION   (MAKE_VERSION(2, 0, 5))
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum gpio_pin_direction_t
+
+ + + +
Enumerator
kGPIO_DigitalInput  +

Set current pin as digital input.

+
kGPIO_DigitalOutput  +

Set current pin as digital output.

+
+ +
+
+ +
+
+ + + + +
enum gpio_interrupt_mode_t
+
+ + + + + + + +
Enumerator
kGPIO_NoIntmode  +

Set current pin general IO functionality.

+
kGPIO_IntLowLevel  +

Set current pin interrupt is low-level sensitive.

+
kGPIO_IntHighLevel  +

Set current pin interrupt is high-level sensitive.

+
kGPIO_IntRisingEdge  +

Set current pin interrupt is rising-edge sensitive.

+
kGPIO_IntFallingEdge  +

Set current pin interrupt is falling-edge sensitive.

+
kGPIO_IntRisingOrFallingEdge  +

Enable the edge select bit to override the ICR register's configuration.

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void GPIO_PinInit (GPIO_Type * base,
uint32_t pin,
const gpio_pin_config_t * Config 
)
+
+
Parameters
+ + + + +
baseGPIO base pointer.
pinSpecifies the pin number
Configpointer to a gpio_pin_config_t structure that contains the configuration information.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void GPIO_PinWrite (GPIO_Type * base,
uint32_t pin,
uint8_t output 
)
+
+
Parameters
+ + + + +
baseGPIO base pointer.
pinGPIO port pin number.
outputGPIOpin output logic level.
    +
  • 0: corresponding pin output low-logic level.
    • +
  • 1: corresponding pin output high-logic level.
    • +
+
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void GPIO_WritePinOutput (GPIO_Type * base,
uint32_t pin,
uint8_t output 
)
+ 		+inlinestatic
+
+
Deprecated:
Do not use this function. It has been superceded by GPIO_PinWrite.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPIO_PortSet (GPIO_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
maskGPIO pin number macro
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPIO_SetPinsOutput (GPIO_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Deprecated:
Do not use this function. It has been superceded by GPIO_PortSet.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPIO_PortClear (GPIO_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
maskGPIO pin number macro
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPIO_ClearPinsOutput (GPIO_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Deprecated:
Do not use this function. It has been superceded by GPIO_PortClear.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPIO_PortToggle (GPIO_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
maskGPIO pin number macro
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static uint32_t GPIO_PinRead (GPIO_Type * base,
uint32_t pin 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPIO base pointer.
pinGPIO port pin number.
+
+
+
Return values
+ + +
GPIOport input value.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static uint32_t GPIO_ReadPinInput (GPIO_Type * base,
uint32_t pin 
)
+ 		+inlinestatic
+
+
Deprecated:
Do not use this function. It has been superceded by GPIO_PinRead.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static uint8_t GPIO_PinReadPadStatus (GPIO_Type * base,
uint32_t pin 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPIO base pointer.
pinGPIO port pin number.
+
+
+
Return values
+ + +
GPIOpin pad status value.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static uint8_t GPIO_ReadPadStatus (GPIO_Type * base,
uint32_t pin 
)
+ 		+inlinestatic
+
+
Deprecated:
Do not use this function. It has been superceded by GPIO_PinReadPadStatus.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void GPIO_PinSetInterruptConfig (GPIO_Type * base,
uint32_t pin,
gpio_interrupt_mode_t pinInterruptMode 
)
+
+
Parameters
+ + + + +
baseGPIO base pointer.
pinGPIO port pin number.
pinInterruptModepointer to a gpio_interrupt_mode_t structure that contains the interrupt mode information.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void GPIO_SetPinInterruptConfig (GPIO_Type * base,
uint32_t pin,
gpio_interrupt_mode_t pinInterruptMode 
)
+ 		+inlinestatic
+
+
Deprecated:
Do not use this function. It has been superceded by GPIO_PinSetInterruptConfig.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPIO_PortEnableInterrupts (GPIO_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPIO base pointer.
maskGPIO pin number macro.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPIO_EnableInterrupts (GPIO_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPIO base pointer.
maskGPIO pin number macro.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPIO_PortDisableInterrupts (GPIO_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPIO base pointer.
maskGPIO pin number macro.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPIO_DisableInterrupts (GPIO_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Deprecated:
Do not use this function. It has been superceded by GPIO_PortDisableInterrupts.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t GPIO_PortGetInterruptFlags (GPIO_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseGPIO base pointer.
+
+
+
Return values
+ + +
currentpin interrupt status flag.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t GPIO_GetPinsInterruptFlags (GPIO_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseGPIO base pointer.
+
+
+
Return values
+ + +
currentpin interrupt status flag.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPIO_PortClearInterruptFlags (GPIO_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+

Status flags are cleared by writing a 1 to the corresponding bit position.

+
Parameters
+ + + +
baseGPIO base pointer.
maskGPIO pin number macro.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPIO_ClearPinsInterruptFlags (GPIO_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+

Status flags are cleared by writing a 1 to the corresponding bit position.

+
Parameters
+ + + +
baseGPIO base pointer.
maskGPIO pin number macro.
+
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00011.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00011.js new file mode 100644 index 000000000..c76d933ed --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00011.js @@ -0,0 +1,43 @@ +var a00011 = +[ + [ "gpio_pin_config_t", "a00011.html#a00126", [ + [ "direction", "a00011.html#a5eae83ead0519707b896cfa9082c4e82", null ], + [ "outputLogic", "a00011.html#a9d37ffd9a2943f10a91095759bd52da5", null ], + [ "interruptMode", "a00011.html#a2aaf4ec1e85d3fcea653b422c673441e", null ] + ] ], + [ "FSL_GPIO_DRIVER_VERSION", "a00011.html#ga5aa5229cbd041b11bcf8417ba12896b2", null ], + [ "gpio_pin_direction_t", "a00011.html#gada41ca0a2ce239fe125ee96833e715c0", [ + [ "kGPIO_DigitalInput", "a00011.html#ggada41ca0a2ce239fe125ee96833e715c0abacf19933be1940ab40c83535e6a46d4", null ], + [ "kGPIO_DigitalOutput", "a00011.html#ggada41ca0a2ce239fe125ee96833e715c0a509ebcd228fc813cf4afcacd258680f9", null ] + ] ], + [ "gpio_interrupt_mode_t", "a00011.html#ga1b9ad57f43a7be04e31c2e43e92aca39", [ + [ "kGPIO_NoIntmode", "a00011.html#gga1b9ad57f43a7be04e31c2e43e92aca39a69d618dcf6fc01e5c8315ef1dd4aa66d", null ], + [ "kGPIO_IntLowLevel", "a00011.html#gga1b9ad57f43a7be04e31c2e43e92aca39af6c9ba431378e6290d7033b643e554da", null ], + [ "kGPIO_IntHighLevel", "a00011.html#gga1b9ad57f43a7be04e31c2e43e92aca39aa445f82a63c5aa94a1e53cdcf52b71d3", null ], + [ "kGPIO_IntRisingEdge", "a00011.html#gga1b9ad57f43a7be04e31c2e43e92aca39ab874f7d31c4bf2f964bf52466d5c40f4", null ], + [ "kGPIO_IntFallingEdge", "a00011.html#gga1b9ad57f43a7be04e31c2e43e92aca39a369cc36a7fda0eb55c4f509070c2d887", null ], + [ "kGPIO_IntRisingOrFallingEdge", "a00011.html#gga1b9ad57f43a7be04e31c2e43e92aca39ac1d74f985cbebbe8441f6053b8074a50", null ] + ] ], + [ "GPIO_PinInit", "a00011.html#ga8d3aa26ad7e88ef1427e51242a70c259", null ], + [ "GPIO_PinWrite", "a00011.html#ga41c1b70e3ee7825359e0891812c88e85", null ], + [ "GPIO_WritePinOutput", "a00011.html#ga5677a2c3b14f5e9f034edbbd5b429c1d", null ], + [ "GPIO_PortSet", "a00011.html#ga2de9f41517bfde0920a5dea5db6e56d6", null ], + [ "GPIO_SetPinsOutput", "a00011.html#ga2f8a8be69355039abd8b1ddf2a236f4c", null ], + [ "GPIO_PortClear", "a00011.html#gaff8a89d83ce5fdaea9db88317eece33c", null ], + [ "GPIO_ClearPinsOutput", "a00011.html#ga3ac4a7dccb5285b2926f152c3ff12af9", null ], + [ "GPIO_PortToggle", "a00011.html#gaedff8c598cb084323f2aa6c324c2c0cb", null ], + [ "GPIO_PinRead", "a00011.html#gac999c0dd229595fe2b651e796da560be", null ], + [ "GPIO_ReadPinInput", "a00011.html#gaf8d77b6a1daf18087dbc6c0814b2ed97", null ], + [ "GPIO_PinReadPadStatus", "a00011.html#ga1841e0c18fa0792e1fa1b5f812dcdbfa", null ], + [ "GPIO_ReadPadStatus", "a00011.html#ga064aa69c0dbb70a4a7344124df9943b1", null ], + [ "GPIO_PinSetInterruptConfig", "a00011.html#gac704735fb3cf3a56676f2fb90e67b10f", null ], + [ "GPIO_SetPinInterruptConfig", "a00011.html#ga364fe6d19b98557e44282f95ccc5e63d", null ], + [ "GPIO_PortEnableInterrupts", "a00011.html#ga2a62aa9cd2aeacf2a81dc4d644f9b0b1", null ], + [ "GPIO_EnableInterrupts", "a00011.html#ga7c45f4ed2a5ec769e0e4cd2e32f62ad5", null ], + [ "GPIO_PortDisableInterrupts", "a00011.html#gaf9613d5714d047051b09f86592d9cdc4", null ], + [ "GPIO_DisableInterrupts", "a00011.html#gaa1deaff6764df2649453fa5502ee0fcc", null ], + [ "GPIO_PortGetInterruptFlags", "a00011.html#gaee4bc796792470cf80e8f0aa6d8c0d32", null ], + [ "GPIO_GetPinsInterruptFlags", "a00011.html#ga6efe712710a08ee6e9f89a47a507339f", null ], + [ "GPIO_PortClearInterruptFlags", "a00011.html#gabc9cd5e2b520359406cf4b45c5761011", null ], + [ "GPIO_ClearPinsInterruptFlags", "a00011.html#ga0b1ad50f4212dfb839fd059503f03bed", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00012.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00012.html new file mode 100644 index 000000000..0e2b2e9d4 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00012.html @@ -0,0 +1,1651 @@ + + + + + + +MCUXpresso SDK API Reference Manual: GPT: General Purpose Timer + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Enumerations
+
+
GPT: General Purpose Timer
+
+
+

Overview

+

The MCUXpresso SDK provides a driver for the General Purpose Timer (GPT) of MCUXpresso SDK devices.

+

+Function groups

+

The gpt driver supports the generation of PWM signals, input capture, and setting up the timer match conditions.

+

+Initialization and deinitialization

+

The function GPT_Init() initializes the gpt with specified configurations. The function GPT_GetDefaultConfig() gets the default configurations. The initialization function configures the restart/free-run mode and input selection when running.

+

The function GPT_Deinit() stops the timer and turns off the module clock.

+

+Typical use case

+

+GPT interrupt example

+

Set up a channel to trigger a periodic interrupt after every 1 second. Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/gpt

+ + + + + +

+Data Structures

struct  gpt_config_t
 Structure to configure the running mode. More...
 
+ + + + + + + + + + + + + + + + + + + + + + +

+Enumerations

enum  gpt_clock_source_t {
+  kGPT_ClockSource_Off = 0U, +
+  kGPT_ClockSource_Periph = 1U, +
+  kGPT_ClockSource_HighFreq = 2U, +
+  kGPT_ClockSource_Ext = 3U, +
+  kGPT_ClockSource_LowFreq = 4U, +
+  kGPT_ClockSource_Osc = 5U +
+ }
 List of clock sources. More...
 
enum  gpt_input_capture_channel_t {
+  kGPT_InputCapture_Channel1 = 0U, +
+  kGPT_InputCapture_Channel2 = 1U +
+ }
 List of input capture channel number. More...
 
enum  gpt_input_operation_mode_t {
+  kGPT_InputOperation_Disabled = 0U, +
+  kGPT_InputOperation_RiseEdge = 1U, +
+  kGPT_InputOperation_FallEdge = 2U, +
+  kGPT_InputOperation_BothEdge = 3U +
+ }
 List of input capture operation mode. More...
 
enum  gpt_output_compare_channel_t {
+  kGPT_OutputCompare_Channel1 = 0U, +
+  kGPT_OutputCompare_Channel2 = 1U, +
+  kGPT_OutputCompare_Channel3 = 2U +
+ }
 List of output compare channel number. More...
 
enum  gpt_output_operation_mode_t {
+  kGPT_OutputOperation_Disconnected = 0U, +
+  kGPT_OutputOperation_Toggle = 1U, +
+  kGPT_OutputOperation_Clear = 2U, +
+  kGPT_OutputOperation_Set = 3U, +
+  kGPT_OutputOperation_Activelow = 4U +
+ }
 List of output compare operation mode. More...
 
enum  gpt_interrupt_enable_t {
+  kGPT_OutputCompare1InterruptEnable = GPT_IR_OF1IE_MASK, +
+  kGPT_OutputCompare2InterruptEnable = GPT_IR_OF2IE_MASK, +
+  kGPT_OutputCompare3InterruptEnable = GPT_IR_OF3IE_MASK, +
+  kGPT_InputCapture1InterruptEnable = GPT_IR_IF1IE_MASK, +
+  kGPT_InputCapture2InterruptEnable = GPT_IR_IF2IE_MASK, +
+  kGPT_RollOverFlagInterruptEnable = GPT_IR_ROVIE_MASK +
+ }
 List of GPT interrupts. More...
 
enum  gpt_status_flag_t {
+  kGPT_OutputCompare1Flag = GPT_SR_OF1_MASK, +
+  kGPT_OutputCompare2Flag = GPT_SR_OF2_MASK, +
+  kGPT_OutputCompare3Flag = GPT_SR_OF3_MASK, +
+  kGPT_InputCapture1Flag = GPT_SR_IF1_MASK, +
+  kGPT_InputCapture2Flag = GPT_SR_IF2_MASK, +
+  kGPT_RollOverFlag = GPT_SR_ROV_MASK +
+ }
 Status flag. More...
 
+ + + +

+Driver version

+#define FSL_GPT_DRIVER_VERSION   (MAKE_VERSION(2, 0, 3))
 
+ + + + + + + + + + +

+Initialization and deinitialization

void GPT_Init (GPT_Type *base, const gpt_config_t *initConfig)
 Initialize GPT to reset state and initialize running mode. More...
 
void GPT_Deinit (GPT_Type *base)
 Disables the module and gates the GPT clock. More...
 
void GPT_GetDefaultConfig (gpt_config_t *config)
 Fills in the GPT configuration structure with default settings. More...
 
+ + + + +

+Software Reset

static void GPT_SoftwareReset (GPT_Type *base)
 Software reset of GPT module. More...
 
+ + + + + + + + + + + + + + + + + + + +

+Clock source and frequency control

static void GPT_SetClockSource (GPT_Type *base, gpt_clock_source_t gptClkSource)
 Set clock source of GPT. More...
 
static gpt_clock_source_t GPT_GetClockSource (GPT_Type *base)
 Get clock source of GPT. More...
 
static void GPT_SetClockDivider (GPT_Type *base, uint32_t divider)
 Set pre scaler of GPT. More...
 
static uint32_t GPT_GetClockDivider (GPT_Type *base)
 Get clock divider in GPT module. More...
 
static void GPT_SetOscClockDivider (GPT_Type *base, uint32_t divider)
 OSC 24M pre-scaler before selected by clock source. More...
 
static uint32_t GPT_GetOscClockDivider (GPT_Type *base)
 Get OSC 24M clock divider in GPT module. More...
 
+ + + + + + + +

+Timer Start and Stop

static void GPT_StartTimer (GPT_Type *base)
 Start GPT timer. More...
 
static void GPT_StopTimer (GPT_Type *base)
 Stop GPT timer. More...
 
+ + + + +

+Read the timer period

static uint32_t GPT_GetCurrentTimerCount (GPT_Type *base)
 Reads the current GPT counting value. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+GPT Input/Output Signal Control

static void GPT_SetInputOperationMode (GPT_Type *base, gpt_input_capture_channel_t channel, gpt_input_operation_mode_t mode)
 Set GPT operation mode of input capture channel. More...
 
static gpt_input_operation_mode_t GPT_GetInputOperationMode (GPT_Type *base, gpt_input_capture_channel_t channel)
 Get GPT operation mode of input capture channel. More...
 
static uint32_t GPT_GetInputCaptureValue (GPT_Type *base, gpt_input_capture_channel_t channel)
 Get GPT input capture value of certain channel. More...
 
static void GPT_SetOutputOperationMode (GPT_Type *base, gpt_output_compare_channel_t channel, gpt_output_operation_mode_t mode)
 Set GPT operation mode of output compare channel. More...
 
static gpt_output_operation_mode_t GPT_GetOutputOperationMode (GPT_Type *base, gpt_output_compare_channel_t channel)
 Get GPT operation mode of output compare channel. More...
 
static void GPT_SetOutputCompareValue (GPT_Type *base, gpt_output_compare_channel_t channel, uint32_t value)
 Set GPT output compare value of output compare channel. More...
 
static uint32_t GPT_GetOutputCompareValue (GPT_Type *base, gpt_output_compare_channel_t channel)
 Get GPT output compare value of output compare channel. More...
 
static void GPT_ForceOutput (GPT_Type *base, gpt_output_compare_channel_t channel)
 Force GPT output action on output compare channel, ignoring comparator. More...
 
+ + + + + + + + + + +

+GPT Interrupt and Status Interface

static void GPT_EnableInterrupts (GPT_Type *base, uint32_t mask)
 Enables the selected GPT interrupts. More...
 
static void GPT_DisableInterrupts (GPT_Type *base, uint32_t mask)
 Disables the selected GPT interrupts. More...
 
static uint32_t GPT_GetEnabledInterrupts (GPT_Type *base)
 Gets the enabled GPT interrupts. More...
 
+ + + + + + + +

+Status Interface

static uint32_t GPT_GetStatusFlags (GPT_Type *base, gpt_status_flag_t flags)
 Get GPT status flags. More...
 
static void GPT_ClearStatusFlags (GPT_Type *base, gpt_status_flag_t flags)
 Clears the GPT status flags. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct gpt_config_t
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

gpt_clock_source_t clockSource
 clock source for GPT module. More...
 
uint32_t divider
 clock divider (prescaler+1) from clock source to counter. More...
 
bool enableFreeRun
 true: FreeRun mode, false: Restart mode. More...
 
bool enableRunInWait
 GPT enabled in wait mode. More...
 
bool enableRunInStop
 GPT enabled in stop mode. More...
 
bool enableRunInDoze
 GPT enabled in doze mode. More...
 
bool enableRunInDbg
 GPT enabled in debug mode. More...
 
bool enableMode
 
 true:  counter reset to 0 when enabled;
+

false: counter retain its value when enabled. More...

 
+

Field Documentation

+ +
+
+ + + + +
gpt_clock_source_t gpt_config_t::clockSource
+
+ +
+
+ +
+
+ + + + +
uint32_t gpt_config_t::divider
+
+ +
+
+ +
+
+ + + + +
bool gpt_config_t::enableFreeRun
+
+ +
+
+ +
+
+ + + + +
bool gpt_config_t::enableRunInWait
+
+ +
+
+ +
+
+ + + + +
bool gpt_config_t::enableRunInStop
+
+ +
+
+ +
+
+ + + + +
bool gpt_config_t::enableRunInDoze
+
+ +
+
+ +
+
+ + + + +
bool gpt_config_t::enableRunInDbg
+
+ +
+
+ +
+
+ + + + +
bool gpt_config_t::enableMode
+
+ +
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum gpt_clock_source_t
+
+
Note
Actual number of clock sources is SoC dependent
+ + + + + + + +
Enumerator
kGPT_ClockSource_Off  +

GPT Clock Source Off.

+
kGPT_ClockSource_Periph  +

GPT Clock Source from Peripheral Clock.

+
kGPT_ClockSource_HighFreq  +

GPT Clock Source from High Frequency Reference Clock.

+
kGPT_ClockSource_Ext  +

GPT Clock Source from external pin.

+
kGPT_ClockSource_LowFreq  +

GPT Clock Source from Low Frequency Reference Clock.

+
kGPT_ClockSource_Osc  +

GPT Clock Source from Crystal oscillator.

+
+ +
+
+ +
+
+ + + + +
enum gpt_input_capture_channel_t
+
+ + + +
Enumerator
kGPT_InputCapture_Channel1  +

GPT Input Capture Channel1.

+
kGPT_InputCapture_Channel2  +

GPT Input Capture Channel2.

+
+ +
+
+ +
+
+ + + + +
enum gpt_input_operation_mode_t
+
+ + + + + +
Enumerator
kGPT_InputOperation_Disabled  +

Don't capture.

+
kGPT_InputOperation_RiseEdge  +

Capture on rising edge of input pin.

+
kGPT_InputOperation_FallEdge  +

Capture on falling edge of input pin.

+
kGPT_InputOperation_BothEdge  +

Capture on both edges of input pin.

+
+ +
+
+ +
+
+ + + + +
enum gpt_output_compare_channel_t
+
+ + + + +
Enumerator
kGPT_OutputCompare_Channel1  +

Output Compare Channel1.

+
kGPT_OutputCompare_Channel2  +

Output Compare Channel2.

+
kGPT_OutputCompare_Channel3  +

Output Compare Channel3.

+
+ +
+
+ +
+
+ + + + +
enum gpt_output_operation_mode_t
+
+ + + + + + +
Enumerator
kGPT_OutputOperation_Disconnected  +

Don't change output pin.

+
kGPT_OutputOperation_Toggle  +

Toggle output pin.

+
kGPT_OutputOperation_Clear  +

Set output pin low.

+
kGPT_OutputOperation_Set  +

Set output pin high.

+
kGPT_OutputOperation_Activelow  +

Generate a active low pulse on output pin.

+
+ +
+
+ +
+
+ + + + +
enum gpt_interrupt_enable_t
+
+ + + + + + + +
Enumerator
kGPT_OutputCompare1InterruptEnable  +

Output Compare Channel1 interrupt enable.

+
kGPT_OutputCompare2InterruptEnable  +

Output Compare Channel2 interrupt enable.

+
kGPT_OutputCompare3InterruptEnable  +

Output Compare Channel3 interrupt enable.

+
kGPT_InputCapture1InterruptEnable  +

Input Capture Channel1 interrupt enable.

+
kGPT_InputCapture2InterruptEnable  +

Input Capture Channel1 interrupt enable.

+
kGPT_RollOverFlagInterruptEnable  +

Counter rolled over interrupt enable.

+
+ +
+
+ +
+
+ + + + +
enum gpt_status_flag_t
+
+ + + + + + + +
Enumerator
kGPT_OutputCompare1Flag  +

Output compare channel 1 event.

+
kGPT_OutputCompare2Flag  +

Output compare channel 2 event.

+
kGPT_OutputCompare3Flag  +

Output compare channel 3 event.

+
kGPT_InputCapture1Flag  +

Input Capture channel 1 event.

+
kGPT_InputCapture2Flag  +

Input Capture channel 2 event.

+
kGPT_RollOverFlag  +

Counter reaches maximum value and rolled over to 0 event.

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void GPT_Init (GPT_Type * base,
const gpt_config_t * initConfig 
)
+
+
Parameters
+ + + +
baseGPT peripheral base address.
initConfigGPT mode setting configuration.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void GPT_Deinit (GPT_Type * base)
+
+
Parameters
+ + +
baseGPT peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void GPT_GetDefaultConfig (gpt_config_t * config)
+
+

The default values are:

+
* config->clockSource = kGPT_ClockSource_Periph;
+
* config->divider = 1U;
+
* config->enableRunInStop = true;
+
* config->enableRunInWait = true;
+
* config->enableRunInDoze = false;
+
* config->enableRunInDbg = false;
+
* config->enableFreeRun = false;
+
* config->enableMode = true;
+
*
+
Parameters
+ + +
configPointer to the user configuration structure.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void GPT_SoftwareReset (GPT_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseGPT peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPT_SetClockSource (GPT_Type * base,
gpt_clock_source_t gptClkSource 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPT peripheral base address.
gptClkSourceClock source (see gpt_clock_source_t typedef enumeration).
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static gpt_clock_source_t GPT_GetClockSource (GPT_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseGPT peripheral base address.
+
+
+
Returns
clock source (see gpt_clock_source_t typedef enumeration).
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPT_SetClockDivider (GPT_Type * base,
uint32_t divider 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPT peripheral base address.
dividerDivider of GPT (1-4096).
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t GPT_GetClockDivider (GPT_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseGPT peripheral base address.
+
+
+
Returns
clock divider in GPT module (1-4096).
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPT_SetOscClockDivider (GPT_Type * base,
uint32_t divider 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPT peripheral base address.
dividerOSC Divider(1-16).
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t GPT_GetOscClockDivider (GPT_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseGPT peripheral base address.
+
+
+
Returns
OSC clock divider in GPT module (1-16).
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void GPT_StartTimer (GPT_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseGPT peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void GPT_StopTimer (GPT_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseGPT peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t GPT_GetCurrentTimerCount (GPT_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseGPT peripheral base address.
+
+
+
Returns
Current GPT counter value.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void GPT_SetInputOperationMode (GPT_Type * base,
gpt_input_capture_channel_t channel,
gpt_input_operation_mode_t mode 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseGPT peripheral base address.
channelGPT capture channel (see gpt_input_capture_channel_t typedef enumeration).
modeGPT input capture operation mode (see gpt_input_operation_mode_t typedef enumeration).
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static gpt_input_operation_mode_t GPT_GetInputOperationMode (GPT_Type * base,
gpt_input_capture_channel_t channel 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPT peripheral base address.
channelGPT capture channel (see gpt_input_capture_channel_t typedef enumeration).
+
+
+
Returns
GPT input capture operation mode (see gpt_input_operation_mode_t typedef enumeration).
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static uint32_t GPT_GetInputCaptureValue (GPT_Type * base,
gpt_input_capture_channel_t channel 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPT peripheral base address.
channelGPT capture channel (see gpt_input_capture_channel_t typedef enumeration).
+
+
+
Returns
GPT input capture value.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void GPT_SetOutputOperationMode (GPT_Type * base,
gpt_output_compare_channel_t channel,
gpt_output_operation_mode_t mode 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseGPT peripheral base address.
channelGPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
modeGPT output operation mode (see gpt_output_operation_mode_t typedef enumeration).
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static gpt_output_operation_mode_t GPT_GetOutputOperationMode (GPT_Type * base,
gpt_output_compare_channel_t channel 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPT peripheral base address.
channelGPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
+
+
+
Returns
GPT output operation mode (see gpt_output_operation_mode_t typedef enumeration).
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void GPT_SetOutputCompareValue (GPT_Type * base,
gpt_output_compare_channel_t channel,
uint32_t value 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseGPT peripheral base address.
channelGPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
valueGPT output compare value.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static uint32_t GPT_GetOutputCompareValue (GPT_Type * base,
gpt_output_compare_channel_t channel 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPT peripheral base address.
channelGPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
+
+
+
Returns
GPT output compare value.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPT_ForceOutput (GPT_Type * base,
gpt_output_compare_channel_t channel 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPT peripheral base address.
channelGPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPT_EnableInterrupts (GPT_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPT peripheral base address.
maskThe interrupts to enable. This is a logical OR of members of the enumeration gpt_interrupt_enable_t
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPT_DisableInterrupts (GPT_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPT peripheral base address
maskThe interrupts to disable. This is a logical OR of members of the enumeration gpt_interrupt_enable_t
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t GPT_GetEnabledInterrupts (GPT_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseGPT peripheral base address
+
+
+
Returns
The enabled interrupts. This is the logical OR of members of the enumeration gpt_interrupt_enable_t
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static uint32_t GPT_GetStatusFlags (GPT_Type * base,
gpt_status_flag_t flags 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPT peripheral base address.
flagsGPT status flag mask (see gpt_status_flag_t for bit definition).
+
+
+
Returns
GPT status, each bit represents one status flag.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void GPT_ClearStatusFlags (GPT_Type * base,
gpt_status_flag_t flags 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseGPT peripheral base address.
flagsGPT status flag mask (see gpt_status_flag_t for bit definition).
+
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00012.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00012.js new file mode 100644 index 000000000..a00057ddd --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00012.js @@ -0,0 +1,85 @@ +var a00012 = +[ + [ "gpt_config_t", "a00012.html#a00127", [ + [ "clockSource", "a00012.html#a25f268bc5fecec8069a572c4c3b58fc7", null ], + [ "divider", "a00012.html#a2407ae05cf065f7670679b3e1c2c2b50", null ], + [ "enableFreeRun", "a00012.html#aae502b9cc970005480f6ff1658972d53", null ], + [ "enableRunInWait", "a00012.html#a4ddfd1bd9f2f22b721a2bff60673fac5", null ], + [ "enableRunInStop", "a00012.html#a10b8bb88a27214987d3e877a6c0371db", null ], + [ "enableRunInDoze", "a00012.html#a0cfe8142bf85397f51921301055b1bb8", null ], + [ "enableRunInDbg", "a00012.html#a5c3a30242ed5d7d2675be2d300eed4d1", null ], + [ "enableMode", "a00012.html#a0c9bf1a239e33da721076aabd0c2b079", null ] + ] ], + [ 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"GPT_GetInputOperationMode", "a00012.html#ga075a62145685b5e150392b5bf0162af7", null ], + [ "GPT_GetInputCaptureValue", "a00012.html#ga613c750bc61498e596cc34bf3d7c8705", null ], + [ "GPT_SetOutputOperationMode", "a00012.html#ga2b4b3962e3f263e53d83ccabf2f3b489", null ], + [ "GPT_GetOutputOperationMode", "a00012.html#gaa4ed0958938a4a9c3c58050e26511026", null ], + [ "GPT_SetOutputCompareValue", "a00012.html#gab4482de4377738cf0ee065f6ad7d3547", null ], + [ "GPT_GetOutputCompareValue", "a00012.html#gaf152c66a815fd38352742ed4ba01d507", null ], + [ "GPT_ForceOutput", "a00012.html#ga82938d7d324ba16a8462f1b68284b6ba", null ], + [ "GPT_EnableInterrupts", "a00012.html#gaf441b1f196d31f08319db26487bbe496", null ], + [ "GPT_DisableInterrupts", "a00012.html#gaa4fd7eccba69c67e4facf6e9a5e9c62e", null ], + [ "GPT_GetEnabledInterrupts", "a00012.html#ga471739441f35a3f65707e40e8d5f0649", null ], + [ "GPT_GetStatusFlags", "a00012.html#ga9e19600458e9121125a370720b4f6f6d", null ], + [ "GPT_ClearStatusFlags", "a00012.html#gad0cdd59a23d43441a5a160bf01351754", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00013.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00013.html new file mode 100644 index 000000000..2e0866841 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00013.html @@ -0,0 +1,2369 @@ + + + + + + +MCUXpresso SDK API Reference Manual: I2C Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Macros | +Typedefs | +Enumerations
+
+
I2C Driver
I2C: Inter-Integrated Circuit Driver
+
+
+

Overview

+

The MCUXpresso SDK provides a peripheral driver for the Inter-Integrated Circuit (I2C) module of MCUXpresso SDK devices.

+

The I2C driver includes functional APIs and transactional APIs.

+

Functional APIs target the low-level APIs. Functional APIs can be used for the I2C master/slave initialization/configuration/operation for optimization/customization purpose. Using the functional APIs requires knowing the I2C master peripheral and how to organize functional APIs to meet the application requirements. The I2C functional operation groups provide the functional APIs set.

+

Transactional APIs target the high-level APIs. The transactional APIs can be used to enable the peripheral quickly and also in the application if the code size and performance of transactional APIs satisfy the requirements. If the code size and performance are critical requirements, see the transactional API implementation and write custom code using the functional APIs or accessing the hardware registers.

+

Transactional APIs support asynchronous transfer. This means that the functions I2C_MasterTransferNonBlocking() set up the interrupt non-blocking transfer. When the transfer completes, the upper layer is notified through a callback function with the status.

+

+Typical use case

+

+Master Operation in functional method

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/i2c

+

+Master Operation in interrupt transactional method

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/i2c

+

+Slave Operation in functional method

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/i2c

+

+Slave Operation in interrupt transactional method

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/i2c

+ + + + + + + + + + + + + + + + + + + + +

+Data Structures

struct  i2c_master_config_t
 I2C master user configuration. More...
 
struct  i2c_master_transfer_t
 I2C master transfer structure. More...
 
struct  i2c_master_handle_t
 I2C master handle structure. More...
 
struct  i2c_slave_config_t
 I2C slave user configuration. More...
 
struct  i2c_slave_transfer_t
 I2C slave transfer structure. More...
 
struct  i2c_slave_handle_t
 I2C slave handle structure. More...
 
+ + + + +

+Macros

#define I2C_RETRY_TIMES   0U /* Define to zero means keep waiting until the flag is assert/deassert. */
 Retry times for waiting flag. More...
 
+ + + + + + + +

+Typedefs

typedef void(* i2c_master_transfer_callback_t )(I2C_Type *base, i2c_master_handle_t *handle, status_t status, void *userData)
 I2C master transfer callback typedef. More...
 
typedef void(* i2c_slave_transfer_callback_t )(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData)
 I2C slave transfer callback typedef. More...
 
+ + + + + + + + + + + + + + + + + + + +

+Enumerations

enum  {
+  kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0), +
+  kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), +
+  kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), +
+  kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), +
+  kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), +
+  kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_I2C, 5) +
+ }
 I2C status return codes. More...
 
enum  _i2c_flags {
+  kI2C_ReceiveNakFlag = I2C_I2SR_RXAK_MASK, +
+  kI2C_IntPendingFlag = I2C_I2SR_IIF_MASK, +
+  kI2C_TransferDirectionFlag = I2C_I2SR_SRW_MASK, +
+  kI2C_ArbitrationLostFlag = I2C_I2SR_IAL_MASK, +
+  kI2C_BusBusyFlag = I2C_I2SR_IBB_MASK, +
+  kI2C_AddressMatchFlag = I2C_I2SR_IAAS_MASK, +
+  kI2C_TransferCompleteFlag = I2C_I2SR_ICF_MASK +
+ }
 I2C peripheral flags. More...
 
enum  _i2c_interrupt_enable { kI2C_GlobalInterruptEnable = I2C_I2CR_IIEN_MASK + }
 I2C feature interrupt source. More...
 
enum  i2c_direction_t {
+  kI2C_Write = 0x0U, +
+  kI2C_Read = 0x1U +
+ }
 The direction of master and slave transfers. More...
 
enum  _i2c_master_transfer_flags {
+  kI2C_TransferDefaultFlag = 0x0U, +
+  kI2C_TransferNoStartFlag = 0x1U, +
+  kI2C_TransferRepeatedStartFlag = 0x2U, +
+  kI2C_TransferNoStopFlag = 0x4U +
+ }
 I2C transfer control flag. More...
 
enum  i2c_slave_transfer_event_t {
+  kI2C_SlaveAddressMatchEvent = 0x01U, +
+  kI2C_SlaveTransmitEvent = 0x02U, +
+  kI2C_SlaveReceiveEvent = 0x04U, +
+  kI2C_SlaveTransmitAckEvent = 0x08U, +
+  kI2C_SlaveCompletionEvent = 0x20U, +
+  kI2C_SlaveAllEvents +
+ }
 Set of events sent to the callback for nonblocking slave transfers. More...
 
+ + + + +

+Driver version

#define FSL_I2C_DRIVER_VERSION   (MAKE_VERSION(2, 0, 7))
 I2C driver version. More...
 
+ + + + + + + + + + + + + + + + + + + + + + +

+Initialization and deinitialization

void I2C_MasterInit (I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
 Initializes the I2C peripheral. More...
 
void I2C_MasterDeinit (I2C_Type *base)
 De-initializes the I2C master peripheral. More...
 
void I2C_MasterGetDefaultConfig (i2c_master_config_t *masterConfig)
 Sets the I2C master configuration structure to default values. More...
 
void I2C_SlaveInit (I2C_Type *base, const i2c_slave_config_t *slaveConfig)
 Initializes the I2C peripheral. More...
 
void I2C_SlaveDeinit (I2C_Type *base)
 De-initializes the I2C slave peripheral. More...
 
void I2C_SlaveGetDefaultConfig (i2c_slave_config_t *slaveConfig)
 Sets the I2C slave configuration structure to default values. More...
 
static void I2C_Enable (I2C_Type *base, bool enable)
 Enables or disables the I2C peripheral operation. More...
 
+ + + + + + + + + + + + + +

+Status

static uint32_t I2C_MasterGetStatusFlags (I2C_Type *base)
 Gets the I2C status flags. More...
 
static void I2C_MasterClearStatusFlags (I2C_Type *base, uint32_t statusMask)
 Clears the I2C status flag state. More...
 
static uint32_t I2C_SlaveGetStatusFlags (I2C_Type *base)
 Gets the I2C status flags. More...
 
static void I2C_SlaveClearStatusFlags (I2C_Type *base, uint32_t statusMask)
 Clears the I2C status flag state. More...
 
+ + + + + + + +

+Interrupts

void I2C_EnableInterrupts (I2C_Type *base, uint32_t mask)
 Enables I2C interrupt requests. More...
 
void I2C_DisableInterrupts (I2C_Type *base, uint32_t mask)
 Disables I2C interrupt requests. More...
 
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+Bus Operations

void I2C_MasterSetBaudRate (I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
 Sets the I2C master transfer baud rate. More...
 
status_t I2C_MasterStart (I2C_Type *base, uint8_t address, i2c_direction_t direction)
 Sends a START on the I2C bus. More...
 
status_t I2C_MasterStop (I2C_Type *base)
 Sends a STOP signal on the I2C bus. More...
 
status_t I2C_MasterRepeatedStart (I2C_Type *base, uint8_t address, i2c_direction_t direction)
 Sends a REPEATED START on the I2C bus. More...
 
status_t I2C_MasterWriteBlocking (I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags)
 Performs a polling send transaction on the I2C bus. More...
 
status_t I2C_MasterReadBlocking (I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags)
 Performs a polling receive transaction on the I2C bus. More...
 
status_t I2C_SlaveWriteBlocking (I2C_Type *base, const uint8_t *txBuff, size_t txSize)
 Performs a polling send transaction on the I2C bus. More...
 
status_t I2C_SlaveReadBlocking (I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
 Performs a polling receive transaction on the I2C bus. More...
 
status_t I2C_MasterTransferBlocking (I2C_Type *base, i2c_master_transfer_t *xfer)
 Performs a master polling transfer on the I2C bus. More...
 
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+Transactional

void I2C_MasterTransferCreateHandle (I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_callback_t callback, void *userData)
 Initializes the I2C handle which is used in transactional functions. More...
 
status_t I2C_MasterTransferNonBlocking (I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
 Performs a master interrupt non-blocking transfer on the I2C bus. More...
 
status_t I2C_MasterTransferGetCount (I2C_Type *base, i2c_master_handle_t *handle, size_t *count)
 Gets the master transfer status during a interrupt non-blocking transfer. More...
 
status_t I2C_MasterTransferAbort (I2C_Type *base, i2c_master_handle_t *handle)
 Aborts an interrupt non-blocking transfer early. More...
 
void I2C_MasterTransferHandleIRQ (I2C_Type *base, void *i2cHandle)
 Master interrupt handler. More...
 
void I2C_SlaveTransferCreateHandle (I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_callback_t callback, void *userData)
 Initializes the I2C handle which is used in transactional functions. More...
 
status_t I2C_SlaveTransferNonBlocking (I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask)
 Starts accepting slave transfers. More...
 
void I2C_SlaveTransferAbort (I2C_Type *base, i2c_slave_handle_t *handle)
 Aborts the slave transfer. More...
 
status_t I2C_SlaveTransferGetCount (I2C_Type *base, i2c_slave_handle_t *handle, size_t *count)
 Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. More...
 
void I2C_SlaveTransferHandleIRQ (I2C_Type *base, void *i2cHandle)
 Slave interrupt handler. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct i2c_master_config_t
+
+
+ + + + + + + +

Data Fields

bool enableMaster
 Enables the I2C peripheral at initialization time. More...
 
uint32_t baudRate_Bps
 Baud rate configuration of I2C peripheral. More...
 
+

Field Documentation

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+
+ + + + +
bool i2c_master_config_t::enableMaster
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uint32_t i2c_master_config_t::baudRate_Bps
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struct i2c_master_transfer_t
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+
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Data Fields

uint32_t flags
 A transfer flag which controls the transfer. More...
 
uint8_t slaveAddress
 7-bit slave address. More...
 
i2c_direction_t direction
 A transfer direction, read or write. More...
 
uint32_t subaddress
 A sub address. More...
 
uint8_t subaddressSize
 A size of the command buffer. More...
 
uint8_t *volatile data
 A transfer buffer. More...
 
volatile size_t dataSize
 A transfer size. More...
 
+

Field Documentation

+ +
+
+ + + + +
uint32_t i2c_master_transfer_t::flags
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uint8_t i2c_master_transfer_t::slaveAddress
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i2c_direction_t i2c_master_transfer_t::direction
+
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uint32_t i2c_master_transfer_t::subaddress
+
+

Transferred MSB first.

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uint8_t i2c_master_transfer_t::subaddressSize
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uint8_t* volatile i2c_master_transfer_t::data
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volatile size_t i2c_master_transfer_t::dataSize
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+ + + + +
struct _i2c_master_handle
+
+

I2C master handle typedef.

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+ + + + + + + + + + + + + + + + +

Data Fields

i2c_master_transfer_t transfer
 I2C master transfer copy. More...
 
size_t transferSize
 Total bytes to be transferred. More...
 
uint8_t state
 A transfer state maintained during transfer. More...
 
i2c_master_transfer_callback_t completionCallback
 A callback function called when the transfer is finished. More...
 
void * userData
 A callback parameter passed to the callback function. More...
 
+

Field Documentation

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+
+ + + + +
i2c_master_transfer_t i2c_master_handle_t::transfer
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size_t i2c_master_handle_t::transferSize
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uint8_t i2c_master_handle_t::state
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i2c_master_transfer_callback_t i2c_master_handle_t::completionCallback
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void* i2c_master_handle_t::userData
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struct i2c_slave_config_t
+
+
+ + + + + + + +

Data Fields

bool enableSlave
 Enables the I2C peripheral at initialization time. More...
 
uint16_t slaveAddress
 A slave address configuration. More...
 
+

Field Documentation

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+
+ + + + +
bool i2c_slave_config_t::enableSlave
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uint16_t i2c_slave_config_t::slaveAddress
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struct i2c_slave_transfer_t
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Data Fields

i2c_slave_transfer_event_t event
 A reason that the callback is invoked. More...
 
uint8_t *volatile data
 A transfer buffer. More...
 
volatile size_t dataSize
 A transfer size. More...
 
status_t completionStatus
 Success or error code describing how the transfer completed. More...
 
size_t transferredCount
 A number of bytes actually transferred since the start or since the last repeated start. More...
 
+

Field Documentation

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+
+ + + + +
i2c_slave_transfer_event_t i2c_slave_transfer_t::event
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uint8_t* volatile i2c_slave_transfer_t::data
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volatile size_t i2c_slave_transfer_t::dataSize
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status_t i2c_slave_transfer_t::completionStatus
+
+

Only applies for kI2C_SlaveCompletionEvent.

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size_t i2c_slave_transfer_t::transferredCount
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+ + + + +
struct _i2c_slave_handle
+
+

I2C slave handle typedef.

+
+ + + + + + + + + + + + + + + + +

Data Fields

volatile uint8_t state
 A transfer state maintained during transfer. More...
 
i2c_slave_transfer_t transfer
 I2C slave transfer copy. More...
 
uint32_t eventMask
 A mask of enabled events. More...
 
i2c_slave_transfer_callback_t callback
 A callback function called at the transfer event. More...
 
void * userData
 A callback parameter passed to the callback. More...
 
+

Field Documentation

+ +
+
+ + + + +
volatile uint8_t i2c_slave_handle_t::state
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+ + + + +
i2c_slave_transfer_t i2c_slave_handle_t::transfer
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uint32_t i2c_slave_handle_t::eventMask
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i2c_slave_transfer_callback_t i2c_slave_handle_t::callback
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void* i2c_slave_handle_t::userData
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+ +
+
+

Macro Definition Documentation

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+
+ + + + +
#define FSL_I2C_DRIVER_VERSION   (MAKE_VERSION(2, 0, 7))
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#define I2C_RETRY_TIMES   0U /* Define to zero means keep waiting until the flag is assert/deassert. */
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+ +
+
+

Typedef Documentation

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+
+ + + + +
typedef void(* i2c_master_transfer_callback_t)(I2C_Type *base, i2c_master_handle_t *handle, status_t status, void *userData)
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+ + + + +
typedef void(* i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData)
+
+ +
+
+

Enumeration Type Documentation

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+
+ + + + +
anonymous enum
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+ + + + + + + +
Enumerator
kStatus_I2C_Busy  +

I2C is busy with current transfer.

+
kStatus_I2C_Idle  +

Bus is Idle.

+
kStatus_I2C_Nak  +

NAK received during transfer.

+
kStatus_I2C_ArbitrationLost  +

Arbitration lost during transfer.

+
kStatus_I2C_Timeout  +

Timeout polling status flags.

+
kStatus_I2C_Addr_Nak  +

NAK received during the address probe.

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+ +
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+ + + + +
enum _i2c_flags
+
+

The following status register flags can be cleared:

+ +
Note
These enumerations are meant to be OR'd together to form a bit mask.
+ + + + + + + + +
Enumerator
kI2C_ReceiveNakFlag  +

I2C receive NAK flag.

+
kI2C_IntPendingFlag  +

I2C interrupt pending flag.

+
kI2C_TransferDirectionFlag  +

I2C transfer direction flag.

+
kI2C_ArbitrationLostFlag  +

I2C arbitration lost flag.

+
kI2C_BusBusyFlag  +

I2C bus busy flag.

+
kI2C_AddressMatchFlag  +

I2C address match flag.

+
kI2C_TransferCompleteFlag  +

I2C transfer complete flag.

+
+ +
+
+ +
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+ + + + +
enum _i2c_interrupt_enable
+
+ + +
Enumerator
kI2C_GlobalInterruptEnable  +

I2C global interrupt.

+
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+ + + + +
enum i2c_direction_t
+
+ + + +
Enumerator
kI2C_Write  +

Master transmits to the slave.

+
kI2C_Read  +

Master receives from the slave.

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+
+ + + + +
enum _i2c_master_transfer_flags
+
+ + + + + +
Enumerator
kI2C_TransferDefaultFlag  +

A transfer starts with a start signal, stops with a stop signal.

+
kI2C_TransferNoStartFlag  +

A transfer starts without a start signal, only support write only or write+read with no start flag, do not support read only with no start flag.

+
kI2C_TransferRepeatedStartFlag  +

A transfer starts with a repeated start signal.

+
kI2C_TransferNoStopFlag  +

A transfer ends without a stop signal.

+
+ +
+
+ +
+
+ + + + +
enum i2c_slave_transfer_event_t
+
+

These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together events is passed to I2C_SlaveTransferNonBlocking() to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

+
Note
These enumerations are meant to be OR'd together to form a bit mask of events.
+ + + + + + + +
Enumerator
kI2C_SlaveAddressMatchEvent  +

Received the slave address after a start or repeated start.

+
kI2C_SlaveTransmitEvent  +

A callback is requested to provide data to transmit (slave-transmitter role).

+
kI2C_SlaveReceiveEvent  +

A callback is requested to provide a buffer in which to place received data (slave-receiver role).

+
kI2C_SlaveTransmitAckEvent  +

A callback needs to either transmit an ACK or NACK.

+
kI2C_SlaveCompletionEvent  +

A stop was detected or finished transfer, completing the transfer.

+
kI2C_SlaveAllEvents  +

A bit mask of all available events.

+
+ +
+
+

Function Documentation

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void I2C_MasterInit (I2C_Type * base,
const i2c_master_config_t * masterConfig,
uint32_t srcClock_Hz 
)
+
+

Call this API to ungate the I2C clock and configure the I2C with master configuration.

+
Note
This API should be called at the beginning of the application. Otherwise, any operation to the I2C module can cause a hard fault because the clock is not enabled. The configuration structure can be custom filled or it can be set with default values by using the I2C_MasterGetDefaultConfig(). After calling this API, the master is ready to transfer. This is an example.
* i2c_master_config_t config = {
+
* .enableMaster = true,
+
* .baudRate_Bps = 100000
+
* };
+
* I2C_MasterInit(I2C0, &config, 12000000U);
+
*
+
+
Parameters
+ + + + +
baseI2C base pointer
masterConfigA pointer to the master configuration structure
srcClock_HzI2C peripheral clock frequency in Hz
+
+
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+ +
+
+ + + + + + + + +
void I2C_MasterDeinit (I2C_Type * base)
+
+

Call this API to gate the I2C clock. The I2C master module can't work unless the I2C_MasterInit is called.

+
Parameters
+ + +
baseI2C base pointer
+
+
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+
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void I2C_MasterGetDefaultConfig (i2c_master_config_t * masterConfig)
+
+

The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterInit(). Use the initialized structure unchanged in the I2C_MasterInit() or modify the structure before calling the I2C_MasterInit(). This is an example.

+
* i2c_master_config_t config;
+
* I2C_MasterGetDefaultConfig(&config);
+
*
+
Parameters
+ + +
masterConfigA pointer to the master configuration structure.
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void I2C_SlaveInit (I2C_Type * base,
const i2c_slave_config_t * slaveConfig 
)
+
+

Call this API to ungate the I2C clock and initialize the I2C with the slave configuration.

+
Note
This API should be called at the beginning of the application. Otherwise, any operation to the I2C module can cause a hard fault because the clock is not enabled. The configuration structure can partly be set with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user. This is an example.
* i2c_slave_config_t config = {
+
* .enableSlave = true,
+
* .slaveAddress = 0x1DU,
+
* };
+
* I2C_SlaveInit(I2C0, &config);
+
*
+
+
Parameters
+ + + +
baseI2C base pointer
slaveConfigA pointer to the slave configuration structure
+
+
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+ + + + + + + + +
void I2C_SlaveDeinit (I2C_Type * base)
+
+

Calling this API gates the I2C clock. The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock.

+
Parameters
+ + +
baseI2C base pointer
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void I2C_SlaveGetDefaultConfig (i2c_slave_config_t * slaveConfig)
+
+

The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveInit(). Modify fields of the structure before calling the I2C_SlaveInit(). This is an example.

+
* i2c_slave_config_t config;
+
* I2C_SlaveGetDefaultConfig(&config);
+
*
+
Parameters
+ + +
slaveConfigA pointer to the slave configuration structure.
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static void I2C_Enable (I2C_Type * base,
bool enable 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseI2C base pointer
enablePass true to enable and false to disable the module.
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static uint32_t I2C_MasterGetStatusFlags (I2C_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseI2C base pointer
+
+
+
Returns
status flag, use status flag to AND _i2c_flags to get the related status.
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static void I2C_MasterClearStatusFlags (I2C_Type * base,
uint32_t statusMask 
)
+ 		+inlinestatic
+
+

The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag.

+
Parameters
+ + + +
baseI2C base pointer
statusMaskThe status flag mask, defined in type i2c_status_flag_t. The parameter can be any combination of the following values:
    +
  • kI2C_ArbitrationLostFlag
    • +
  • kI2C_IntPendingFlag
    • +
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static uint32_t I2C_SlaveGetStatusFlags (I2C_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseI2C base pointer
+
+
+
Returns
status flag, use status flag to AND _i2c_flags to get the related status.
+ +
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static void I2C_SlaveClearStatusFlags (I2C_Type * base,
uint32_t statusMask 
)
+ 		+inlinestatic
+
+

The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag

+
Parameters
+ + + +
baseI2C base pointer
statusMaskThe status flag mask, defined in type i2c_status_flag_t. The parameter can be any combination of the following values:
    +
  • kI2C_IntPendingFlagFlag
    • +
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void I2C_EnableInterrupts (I2C_Type * base,
uint32_t mask 
)
+
+
Parameters
+ + + +
baseI2C base pointer
maskinterrupt source The parameter can be combination of the following source if defined:
    +
  • kI2C_GlobalInterruptEnable
    • +
  • kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
    • +
  • kI2C_SdaTimeoutInterruptEnable
    • +
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void I2C_DisableInterrupts (I2C_Type * base,
uint32_t mask 
)
+
+
Parameters
+ + + +
baseI2C base pointer
maskinterrupt source The parameter can be combination of the following source if defined:
    +
  • kI2C_GlobalInterruptEnable
    • +
  • kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
    • +
  • kI2C_SdaTimeoutInterruptEnable
    • +
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void I2C_MasterSetBaudRate (I2C_Type * base,
uint32_t baudRate_Bps,
uint32_t srcClock_Hz 
)
+
+
Parameters
+ + + + +
baseI2C base pointer
baudRate_Bpsthe baud rate value in bps
srcClock_HzSource clock
+
+
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+
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+
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status_t I2C_MasterStart (I2C_Type * base,
uint8_t address,
i2c_direction_t direction 
)
+
+

This function is used to initiate a new master mode transfer by sending the START signal. The slave address is sent following the I2C START signal.

+
Parameters
+ + + + +
baseI2C peripheral base pointer
address7-bit slave device address.
directionMaster transfer directions(transmit/receive).
+
+
+
Return values
+ + + +
kStatus_SuccessSuccessfully send the start signal.
kStatus_I2C_BusyCurrent bus is busy.
+
+
+ +
+
+ +
+
+ + + + + + + + +
status_t I2C_MasterStop (I2C_Type * base)
+
+
Return values
+ + + +
kStatus_SuccessSuccessfully send the stop signal.
kStatus_I2C_TimeoutSend stop signal failed, timeout.
+
+
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+
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+
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status_t I2C_MasterRepeatedStart (I2C_Type * base,
uint8_t address,
i2c_direction_t direction 
)
+
+
Parameters
+ + + + +
baseI2C peripheral base pointer
address7-bit slave device address.
directionMaster transfer directions(transmit/receive).
+
+
+
Return values
+ + + +
kStatus_SuccessSuccessfully send the start signal.
kStatus_I2C_BusyCurrent bus is busy but not occupied by current I2C master.
+
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status_t I2C_MasterWriteBlocking (I2C_Type * base,
const uint8_t * txBuff,
size_t txSize,
uint32_t flags 
)
+
+
Parameters
+ + + + + +
baseThe I2C peripheral base pointer.
txBuffThe pointer to the data to be transferred.
txSizeThe length in bytes of the data to be transferred.
flagsTransfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag to issue a stop and kI2C_TransferNoStop to not send a stop.
+
+
+
Return values
+ + + + +
kStatus_SuccessSuccessfully complete the data transmission.
kStatus_I2C_ArbitrationLostTransfer error, arbitration lost.
kStataus_I2C_NakTransfer error, receive NAK during transfer.
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status_t I2C_MasterReadBlocking (I2C_Type * base,
uint8_t * rxBuff,
size_t rxSize,
uint32_t flags 
)
+
+
Note
The I2C_MasterReadBlocking function stops the bus before reading the final byte. Without stopping the bus prior for the final read, the bus issues another read, resulting in garbage data being read into the data register.
+
Parameters
+ + + + + +
baseI2C peripheral base pointer.
rxBuffThe pointer to the data to store the received data.
rxSizeThe length in bytes of the data to be received.
flagsTransfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag to issue a stop and kI2C_TransferNoStop to not send a stop.
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Return values
+ + + +
kStatus_SuccessSuccessfully complete the data transmission.
kStatus_I2C_TimeoutSend stop signal failed, timeout.
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status_t I2C_SlaveWriteBlocking (I2C_Type * base,
const uint8_t * txBuff,
size_t txSize 
)
+
+
Parameters
+ + + + +
baseThe I2C peripheral base pointer.
txBuffThe pointer to the data to be transferred.
txSizeThe length in bytes of the data to be transferred.
+
+
+
Return values
+ + + + +
kStatus_SuccessSuccessfully complete the data transmission.
kStatus_I2C_ArbitrationLostTransfer error, arbitration lost.
kStataus_I2C_NakTransfer error, receive NAK during transfer.
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status_t I2C_SlaveReadBlocking (I2C_Type * base,
uint8_t * rxBuff,
size_t rxSize 
)
+
+
Parameters
+ + + + +
baseI2C peripheral base pointer.
rxBuffThe pointer to the data to store the received data.
rxSizeThe length in bytes of the data to be received.
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status_t I2C_MasterTransferBlocking (I2C_Type * base,
i2c_master_transfer_t * xfer 
)
+
+
Note
The API does not return until the transfer succeeds or fails due to arbitration lost or receiving a NAK.
+
Parameters
+ + + +
baseI2C peripheral base address.
xferPointer to the transfer structure.
+
+
+
Return values
+ + + + + + +
kStatus_SuccessSuccessfully complete the data transmission.
kStatus_I2C_BusyPrevious transmission still not finished.
kStatus_I2C_TimeoutTransfer error, wait signal timeout.
kStatus_I2C_ArbitrationLostTransfer error, arbitration lost.
kStataus_I2C_NakTransfer error, receive NAK during transfer.
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void I2C_MasterTransferCreateHandle (I2C_Type * base,
i2c_master_handle_t * handle,
i2c_master_transfer_callback_t callback,
void * userData 
)
+
+
Parameters
+ + + + + +
baseI2C base pointer.
handlepointer to i2c_master_handle_t structure to store the transfer state.
callbackpointer to user callback function.
userDatauser parameter passed to the callback function.
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status_t I2C_MasterTransferNonBlocking (I2C_Type * base,
i2c_master_handle_t * handle,
i2c_master_transfer_t * xfer 
)
+
+
Note
Calling the API returns immediately after transfer initiates. The user needs to call I2C_MasterGetTransferCount to poll the transfer status to check whether the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer is finished.
+
Parameters
+ + + + +
baseI2C base pointer.
handlepointer to i2c_master_handle_t structure which stores the transfer state.
xferpointer to i2c_master_transfer_t structure.
+
+
+
Return values
+ + + + +
kStatus_SuccessSuccessfully start the data transmission.
kStatus_I2C_BusyPrevious transmission still not finished.
kStatus_I2C_TimeoutTransfer error, wait signal timeout.
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status_t I2C_MasterTransferGetCount (I2C_Type * base,
i2c_master_handle_t * handle,
size_t * count 
)
+
+
Parameters
+ + + + +
baseI2C base pointer.
handlepointer to i2c_master_handle_t structure which stores the transfer state.
countNumber of bytes transferred so far by the non-blocking transaction.
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Return values
+ + + +
kStatus_InvalidArgumentcount is Invalid.
kStatus_SuccessSuccessfully return the count.
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status_t I2C_MasterTransferAbort (I2C_Type * base,
i2c_master_handle_t * handle 
)
+
+
Note
This API can be called at any time when an interrupt non-blocking transfer initiates to abort the transfer early.
+
Parameters
+ + + +
baseI2C base pointer.
handlepointer to i2c_master_handle_t structure which stores the transfer state
+
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Return values
+ + + +
kStatus_I2C_TimeoutTimeout during polling flag.
kStatus_SuccessSuccessfully abort the transfer.
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void I2C_MasterTransferHandleIRQ (I2C_Type * base,
void * i2cHandle 
)
+
+
Parameters
+ + + +
baseI2C base pointer.
i2cHandlepointer to i2c_master_handle_t structure.
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void I2C_SlaveTransferCreateHandle (I2C_Type * base,
i2c_slave_handle_t * handle,
i2c_slave_transfer_callback_t callback,
void * userData 
)
+
+
Parameters
+ + + + + +
baseI2C base pointer.
handlepointer to i2c_slave_handle_t structure to store the transfer state.
callbackpointer to user callback function.
userDatauser parameter passed to the callback function.
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status_t I2C_SlaveTransferNonBlocking (I2C_Type * base,
i2c_slave_handle_t * handle,
uint32_t eventMask 
)
+
+

Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.

+

The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR'd combination of i2c_slave_transfer_event_t enumerators for the events you wish to receive. The kI2C_SlaveTransmitEvent and kLPI2C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kI2C_SlaveAllEvents constant is provided as a convenient way to enable all events.

+
Parameters
+ + + + +
baseThe I2C peripheral base address.
handlePointer to i2c_slave_handle_t structure which stores the transfer state.
eventMaskBit mask formed by OR'ing together i2c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kI2C_SlaveAllEvents to enable all events.
+
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Return values
+ + + +
kStatus_SuccessSlave transfers were successfully started.
kStatus_I2C_BusySlave transfers have already been started on this handle.
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void I2C_SlaveTransferAbort (I2C_Type * base,
i2c_slave_handle_t * handle 
)
+
+
Note
This API can be called at any time to stop slave for handling the bus events.
+
Parameters
+ + + +
baseI2C base pointer.
handlepointer to i2c_slave_handle_t structure which stores the transfer state.
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status_t I2C_SlaveTransferGetCount (I2C_Type * base,
i2c_slave_handle_t * handle,
size_t * count 
)
+
+
Parameters
+ + + + +
baseI2C base pointer.
handlepointer to i2c_slave_handle_t structure.
countNumber of bytes transferred so far by the non-blocking transaction.
+
+
+
Return values
+ + + +
kStatus_InvalidArgumentcount is Invalid.
kStatus_SuccessSuccessfully return the count.
+
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+
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void I2C_SlaveTransferHandleIRQ (I2C_Type * base,
void * i2cHandle 
)
+
+
Parameters
+ + + +
baseI2C base pointer.
i2cHandlepointer to i2c_slave_handle_t structure which stores the transfer state
+
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+ +
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+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00013.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00013.js new file mode 100644 index 000000000..95c928825 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00013.js @@ -0,0 +1,114 @@ +var a00013 = +[ + [ "i2c_master_config_t", "a00013.html#a00128", [ + [ "enableMaster", "a00013.html#a2419131a10906475fd31950f17ac8895", null ], + [ "baudRate_Bps", "a00013.html#a2186844dc87bcde999fc12005f4c550a", null ] + ] ], + [ "i2c_master_transfer_t", "a00013.html#a00129", [ + [ "flags", "a00013.html#a8835787e1b0f9a4b8868e7cbe53e45d5", null ], + [ "slaveAddress", "a00013.html#a3b9c4ae818b1194955db51de0f67795f", null ], + [ "direction", "a00013.html#ac5b89dc9115b7760431c981e0c1fd443", null ], + [ "subaddress", "a00013.html#ae7facb612714785d4e143e57d47a5af3", null ], + [ "subaddressSize", "a00013.html#a9c08797f65f0faac78f44ac038c45c38", null ], + [ "data", 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+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
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+Data Structures | +Macros | +Enumerations
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+
Quad Serial Peripheral Interface Driver
QSPI: Quad Serial Peripheral Interface
+
+
+

Overview

+ + + + + + + + + + + + + + + + + + + + +

+Data Structures

struct  qspi_dqs_config_t
 DQS configure features. More...
 
struct  qspi_flash_timing_t
 Flash timing configuration. More...
 
struct  qspi_config_t
 QSPI configuration structure. More...
 
struct  qspi_flash_config_t
 External flash configuration items. More...
 
struct  qspi_transfer_t
 Transfer structure for QSPI. More...
 
struct  ip_command_config_t
 16-bit access reg for IPCR register More...
 
+ + + + + + + + + + +

+Macros

+#define QSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
 Macro functions for LUT table.
 
+#define QSPI_CMD   (0x1U)
 Macro for QSPI LUT command.
 
+#define QSPI_PAD_1   (0x0U)
 Macro for QSPI PAD.
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Enumerations

enum  {
+  kStatus_QSPI_Idle = MAKE_STATUS(kStatusGroup_QSPI, 0), +
+  kStatus_QSPI_Busy = MAKE_STATUS(kStatusGroup_QSPI, 1), +
+  kStatus_QSPI_Error = MAKE_STATUS(kStatusGroup_QSPI, 2) +
+ }
 Status structure of QSPI. More...
 
enum  qspi_read_area_t {
+  kQSPI_ReadAHB = 0x0U, +
+  kQSPI_ReadIP +
+ }
 QSPI read data area, from IP FIFO or AHB buffer. More...
 
enum  qspi_command_seq_t {
+  kQSPI_IPSeq = QuadSPI_SPTRCLR_IPPTRC_MASK, +
+  kQSPI_BufferSeq = QuadSPI_SPTRCLR_BFPTRC_MASK +
+ }
 QSPI command sequence type. More...
 
enum  qspi_fifo_t {
+  kQSPI_TxFifo = QuadSPI_MCR_CLR_TXF_MASK, +
+  kQSPI_RxFifo = QuadSPI_MCR_CLR_RXF_MASK, +
+  kQSPI_AllFifo = QuadSPI_MCR_CLR_TXF_MASK | QuadSPI_MCR_CLR_RXF_MASK +
+ }
 QSPI buffer type. More...
 
enum  qspi_endianness_t {
+  kQSPI_64BigEndian = 0x0U, +
+  kQSPI_32LittleEndian, +
+  kQSPI_32BigEndian, +
+  kQSPI_64LittleEndian +
+ }
 QSPI transfer endianess. More...
 
enum  _qspi_error_flags {
+  kQSPI_DataLearningFail = (int)QuadSPI_FR_DLPFF_MASK, +
+  kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, +
+  kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, +
+  kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, +
+  kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, +
+  kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, +
+  kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, +
+  kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, +
+  kQSPI_IPCommandUsageError = QuadSPI_FR_IUEF_MASK, +
+  kQSPI_IPCommandTriggerDuringAHBAccess = QuadSPI_FR_IPAEF_MASK, +
+  kQSPI_IPCommandTriggerDuringIPAccess = QuadSPI_FR_IPIEF_MASK, +
+  kQSPI_IPCommandTriggerDuringAHBGrant = QuadSPI_FR_IPGEF_MASK, +
+  kQSPI_IPCommandTransactionFinished = QuadSPI_FR_TFF_MASK, +
+  kQSPI_FlagAll = (int)0x8C83F8D1U +
+ }
 QSPI error flags. More...
 
enum  _qspi_flags {
+  kQSPI_DataLearningSamplePoint = (int)QuadSPI_SR_DLPSMP_MASK, +
+  kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK, +
+  kQSPI_TxBufferEnoughData = QuadSPI_SR_TXEDA_MASK, +
+  kQSPI_RxDMA = QuadSPI_SR_RXDMA_MASK, +
+  kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK, +
+  kQSPI_RxWatermark = QuadSPI_SR_RXWE_MASK, +
+  kQSPI_AHB3BufferFull = QuadSPI_SR_AHB3FUL_MASK, +
+  kQSPI_AHB2BufferFull = QuadSPI_SR_AHB2FUL_MASK, +
+  kQSPI_AHB1BufferFull = QuadSPI_SR_AHB1FUL_MASK, +
+  kQSPI_AHB0BufferFull = QuadSPI_SR_AHB0FUL_MASK, +
+  kQSPI_AHB3BufferNotEmpty = QuadSPI_SR_AHB3NE_MASK, +
+  kQSPI_AHB2BufferNotEmpty = QuadSPI_SR_AHB2NE_MASK, +
+  kQSPI_AHB1BufferNotEmpty = QuadSPI_SR_AHB1NE_MASK, +
+  kQSPI_AHB0BufferNotEmpty = QuadSPI_SR_AHB0NE_MASK, +
+  kQSPI_AHBTransactionPending = QuadSPI_SR_AHBTRN_MASK, +
+  kQSPI_AHBCommandPriorityGranted = QuadSPI_SR_AHBGNT_MASK, +
+  kQSPI_AHBAccess = QuadSPI_SR_AHB_ACC_MASK, +
+  kQSPI_IPAccess = QuadSPI_SR_IP_ACC_MASK, +
+  kQSPI_Busy = QuadSPI_SR_BUSY_MASK, +
+  kQSPI_StateAll = (int)0xEF897FE7U +
+ }
 QSPI state bit. More...
 
enum  _qspi_interrupt_enable {
+  kQSPI_DataLearningFailInterruptEnable, +
+  kQSPI_TxBufferFillInterruptEnable = QuadSPI_RSER_TBFIE_MASK, +
+  kQSPI_TxBufferUnderrunInterruptEnable = QuadSPI_RSER_TBUIE_MASK, +
+  kQSPI_IllegalInstructionInterruptEnable, +
+  kQSPI_RxBufferOverflowInterruptEnable = QuadSPI_RSER_RBOIE_MASK, +
+  kQSPI_RxBufferDrainInterruptEnable = QuadSPI_RSER_RBDIE_MASK, +
+  kQSPI_AHBSequenceErrorInterruptEnable = QuadSPI_RSER_ABSEIE_MASK, +
+  kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, +
+  kQSPI_IPCommandUsageErrorInterruptEnable = QuadSPI_RSER_IUEIE_MASK, +
+  kQSPI_IPCommandTriggerDuringAHBAccessInterruptEnable, +
+  kQSPI_IPCommandTriggerDuringIPAccessInterruptEnable, +
+  kQSPI_IPCommandTriggerDuringAHBGrantInterruptEnable, +
+  kQSPI_IPCommandTransactionFinishedInterruptEnable, +
+  kQSPI_AllInterruptEnable = (int)0x8C83F8D1U +
+ }
 QSPI interrupt enable. More...
 
enum  _qspi_dma_enable { kQSPI_RxBufferDrainDMAEnable = QuadSPI_RSER_RBDDE_MASK + }
 QSPI DMA request flag. More...
 
enum  qspi_dqs_phrase_shift_t {
+  kQSPI_DQSNoPhraseShift = 0x0U, +
+  kQSPI_DQSPhraseShift45Degree, +
+  kQSPI_DQSPhraseShift90Degree, +
+  kQSPI_DQSPhraseShift135Degree +
+ }
 Phrase shift number for DQS mode. More...
 
enum  qspi_dqs_read_sample_clock_t {
+  kQSPI_ReadSampleClkInternalLoopback = 0x0U, +
+  kQSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, +
+  kQSPI_ReadSampleClkExternalInputFromDqsPad = 0x2U +
+ }
 Qspi read sampling option. More...
 
+ + + + +

+Driver version

#define FSL_QSPI_DRIVER_VERSION   (MAKE_VERSION(2, 2, 3))
 QSPI driver version 2.2.3. More...
 
+ + + + + + + + + + + + + + + + + + + + + + +

+Initialization and deinitialization

uint32_t QSPI_GetInstance (QuadSPI_Type *base)
 Get the instance number for QSPI. More...
 
void QSPI_Init (QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz)
 Initializes the QSPI module and internal state. More...
 
void QSPI_GetDefaultQspiConfig (qspi_config_t *config)
 Gets default settings for QSPI. More...
 
void QSPI_Deinit (QuadSPI_Type *base)
 Deinitializes the QSPI module. More...
 
void QSPI_SetFlashConfig (QuadSPI_Type *base, qspi_flash_config_t *config)
 Configures the serial flash parameter. More...
 
void QSPI_SoftwareReset (QuadSPI_Type *base)
 Software reset for the QSPI logic. More...
 
static void QSPI_Enable (QuadSPI_Type *base, bool enable)
 Enables or disables the QSPI module. More...
 
+ + + + + + + + + + +

+Status

static uint32_t QSPI_GetStatusFlags (QuadSPI_Type *base)
 Gets the state value of QSPI. More...
 
static uint32_t QSPI_GetErrorStatusFlags (QuadSPI_Type *base)
 Gets QSPI error status flags. More...
 
static void QSPI_ClearErrorFlag (QuadSPI_Type *base, uint32_t mask)
 Clears the QSPI error flags. More...
 
+ + + + + + + +

+Interrupts

static void QSPI_EnableInterrupts (QuadSPI_Type *base, uint32_t mask)
 Enables the QSPI interrupts. More...
 
static void QSPI_DisableInterrupts (QuadSPI_Type *base, uint32_t mask)
 Disables the QSPI interrupts. More...
 
+ + + + + + + + + + +

+DMA Control

static void QSPI_EnableDMA (QuadSPI_Type *base, uint32_t mask, bool enable)
 Enables the QSPI DMA source. More...
 
static uint32_t QSPI_GetTxDataRegisterAddress (QuadSPI_Type *base)
 Gets the Tx data register address. More...
 
uint32_t QSPI_GetRxDataRegisterAddress (QuadSPI_Type *base)
 Gets the Rx data register address used for DMA operation. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Bus Operations

static void QSPI_SetIPCommandAddress (QuadSPI_Type *base, uint32_t addr)
 Sets the IP command address. More...
 
static void QSPI_SetIPCommandSize (QuadSPI_Type *base, uint32_t size)
 Sets the IP command size. More...
 
void QSPI_ExecuteIPCommand (QuadSPI_Type *base, uint32_t index)
 Executes IP commands located in LUT table. More...
 
void QSPI_ExecuteAHBCommand (QuadSPI_Type *base, uint32_t index)
 Executes AHB commands located in LUT table. More...
 
static void QSPI_EnableIPParallelMode (QuadSPI_Type *base, bool enable)
 Enables/disables the QSPI IP command parallel mode. More...
 
static void QSPI_EnableAHBParallelMode (QuadSPI_Type *base, bool enable)
 Enables/disables the QSPI AHB command parallel mode. More...
 
void QSPI_UpdateLUT (QuadSPI_Type *base, uint32_t index, uint32_t *cmd)
 Updates the LUT table. More...
 
static void QSPI_ClearFifo (QuadSPI_Type *base, uint32_t mask)
 Clears the QSPI FIFO logic. More...
 
static void QSPI_ClearCommandSequence (QuadSPI_Type *base, qspi_command_seq_t seq)
 @ brief Clears the command sequence for the IP/buffer command. More...
 
static void QSPI_EnableDDRMode (QuadSPI_Type *base, bool enable)
 Enable or disable DDR mode. More...
 
void QSPI_SetReadDataArea (QuadSPI_Type *base, qspi_read_area_t area)
 @ brief Set the RX buffer readout area. More...
 
void QSPI_WriteBlocking (QuadSPI_Type *base, uint32_t *buffer, size_t size)
 Sends a buffer of data bytes using a blocking method. More...
 
static void QSPI_WriteData (QuadSPI_Type *base, uint32_t data)
 Writes data into FIFO. More...
 
void QSPI_ReadBlocking (QuadSPI_Type *base, uint32_t *buffer, size_t size)
 Receives a buffer of data bytes using a blocking method. More...
 
uint32_t QSPI_ReadData (QuadSPI_Type *base)
 Receives data from data FIFO. More...
 
+ + + + + + + +

+Transactional

static void QSPI_TransferSendBlocking (QuadSPI_Type *base, qspi_transfer_t *xfer)
 Writes data to the QSPI transmit buffer. More...
 
static void QSPI_TransferReceiveBlocking (QuadSPI_Type *base, qspi_transfer_t *xfer)
 Reads data from the QSPI receive buffer in polling way. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct qspi_dqs_config_t
+
+
+ + + + + + + + + + + + + +

Data Fields

+uint32_t portADelayTapNum
 Delay chain tap number selection for QSPI port A DQS.
 
+qspi_dqs_phrase_shift_t shift
 Phase shift for internal DQS generation.
 
qspi_dqs_read_sample_clock_t rxSampleClock
 Read sample clock for Dqs. More...
 
+bool enableDQSClkInverse
 Enable inverse clock for internal DQS generation.
 
+

Field Documentation

+ +
+
+ + + + +
qspi_dqs_read_sample_clock_t qspi_dqs_config_t::rxSampleClock
+
+ +
+
+ +
+
+ +
+
+ + + + +
struct qspi_flash_timing_t
+
+
+ + + + + + + + + + +

Data Fields

+uint32_t dataHoldTime
 Serial flash data in hold time.
 
+uint32_t CSHoldTime
 Serial flash CS hold time in terms of serial flash clock cycles.
 
+uint32_t CSSetupTime
 Serial flash CS setup time in terms of serial flash clock cycles.
 
+ +
+
+ +
+
+ + + + +
struct qspi_config_t
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

+uint32_t clockSource
 Clock source for QSPI module.
 
+uint32_t baudRate
 Serial flash clock baud rate.
 
+uint8_t txWatermark
 QSPI transmit watermark value.
 
uint8_t rxWatermark
 QSPI receive watermark value. More...
 
uint32_t AHBbufferSize [FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]
 AHB buffer size. More...
 
uint8_t AHBbufferMaster [FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]
 AHB buffer master. More...
 
bool enableAHBbuffer3AllMaster
 Is AHB buffer3 for all master. More...
 
+qspi_read_area_t area
 Which area Rx data readout.
 
+bool enableQspi
 Enable QSPI after initialization.
 
+

Field Documentation

+ +
+
+ + + + +
uint8_t qspi_config_t::rxWatermark
+
+ +
+
+ +
+
+ + + + +
uint32_t qspi_config_t::AHBbufferSize[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]
+
+ +
+
+ +
+
+ + + + +
uint8_t qspi_config_t::AHBbufferMaster[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]
+
+ +
+
+ +
+
+ + + + +
bool qspi_config_t::enableAHBbuffer3AllMaster
+
+ +
+
+ +
+
+ +
+
+ + + + +
struct qspi_flash_config_t
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

+uint32_t flashA1Size
 Flash A1 size.
 
+uint32_t flashA2Size
 Flash A2 size.
 
+uint32_t flashB1Size
 Flash B1 size.
 
+uint32_t flashB2Size
 Flash B2 size.
 
+uint32_t lookuptable [FSL_FEATURE_QSPI_LUT_DEPTH]
 Flash command in LUT.
 
uint32_t dataHoldTime
 Data line hold time. More...
 
+uint32_t CSHoldTime
 CS line hold time.
 
+uint32_t CSSetupTime
 CS line setup time.
 
+uint32_t cloumnspace
 Column space size.
 
+uint32_t dataLearnValue
 Data Learn value if enable data learn.
 
qspi_endianness_t endian
 Flash data endianess. More...
 
bool enableWordAddress
 If enable word address. More...
 
+

Field Documentation

+ +
+
+ + + + +
uint32_t qspi_flash_config_t::dataHoldTime
+
+ +
+
+ +
+
+ + + + +
qspi_endianness_t qspi_flash_config_t::endian
+
+ +
+
+ +
+
+ + + + +
bool qspi_flash_config_t::enableWordAddress
+
+ +
+
+ +
+
+ +
+
+ + + + +
struct qspi_transfer_t
+
+
+ + + + + + + +

Data Fields

+uint32_t * data
 Pointer to data to transmit.
 
+size_t dataSize
 Bytes to be transmit.
 
+ +
+
+ +
+
+ + + + +
struct ip_command_config_t
+
+
+
+
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_QSPI_DRIVER_VERSION   (MAKE_VERSION(2, 2, 3))
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
anonymous enum
+
+ + + + +
Enumerator
kStatus_QSPI_Idle  +

QSPI is in idle state.

+
kStatus_QSPI_Busy  +

QSPI is busy.

+
kStatus_QSPI_Error  +

Error occurred during QSPI transfer.

+
+ +
+
+ +
+
+ + + + +
enum qspi_read_area_t
+
+ + + +
Enumerator
kQSPI_ReadAHB  +

QSPI read from AHB buffer.

+
kQSPI_ReadIP  +

QSPI read from IP FIFO.

+
+ +
+
+ +
+
+ + + + +
enum qspi_command_seq_t
+
+ + + +
Enumerator
kQSPI_IPSeq  +

IP command sequence.

+
kQSPI_BufferSeq  +

Buffer command sequence.

+
+ +
+
+ +
+
+ + + + +
enum qspi_fifo_t
+
+ + + + +
Enumerator
kQSPI_TxFifo  +

QSPI Tx FIFO.

+
kQSPI_RxFifo  +

QSPI Rx FIFO.

+
kQSPI_AllFifo  +

QSPI all FIFO, including Tx and Rx.

+
+ +
+
+ +
+
+ + + + +
enum qspi_endianness_t
+
+ + + + + +
Enumerator
kQSPI_64BigEndian  +

64 bits big endian

+
kQSPI_32LittleEndian  +

32 bit little endian

+
kQSPI_32BigEndian  +

32 bit big endian

+
kQSPI_64LittleEndian  +

64 bit little endian

+
+ +
+
+ +
+
+ + + + +
enum _qspi_error_flags
+
+ + + + + + + + + + + + + + + +
Enumerator
kQSPI_DataLearningFail  +

Data learning pattern failure flag.

+
kQSPI_TxBufferFill  +

Tx buffer fill flag.

+
kQSPI_TxBufferUnderrun  +

Tx buffer underrun flag.

+
kQSPI_IllegalInstruction  +

Illegal instruction error flag.

+
kQSPI_RxBufferOverflow  +

Rx buffer overflow flag.

+
kQSPI_RxBufferDrain  +

Rx buffer drain flag.

+
kQSPI_AHBSequenceError  +

AHB sequence error flag.

+
kQSPI_AHBBufferOverflow  +

AHB buffer overflow flag.

+
kQSPI_IPCommandUsageError  +

IP command usage error flag.

+
kQSPI_IPCommandTriggerDuringAHBAccess  +

IP command trigger during AHB access error.

+
kQSPI_IPCommandTriggerDuringIPAccess  +

IP command trigger cannot be executed.

+
kQSPI_IPCommandTriggerDuringAHBGrant  +

IP command trigger during AHB grant error.

+
kQSPI_IPCommandTransactionFinished  +

IP command transaction finished flag.

+
kQSPI_FlagAll  +

All error flag.

+
+ +
+
+ +
+
+ + + + +
enum _qspi_flags
+
+ + + + + + + + + + + + + + + + + + + + + +
Enumerator
kQSPI_DataLearningSamplePoint  +

Data learning sample point.

+
kQSPI_TxBufferFull  +

Tx buffer full flag.

+
kQSPI_TxBufferEnoughData  +

Tx buffer enough data available.

+
kQSPI_RxDMA  +

Rx DMA is requesting or running.

+
kQSPI_RxBufferFull  +

Rx buffer full.

+
kQSPI_RxWatermark  +

Rx buffer watermark exceeded.

+
kQSPI_AHB3BufferFull  +

AHB buffer 3 full.

+
kQSPI_AHB2BufferFull  +

AHB buffer 2 full.

+
kQSPI_AHB1BufferFull  +

AHB buffer 1 full.

+
kQSPI_AHB0BufferFull  +

AHB buffer 0 full.

+
kQSPI_AHB3BufferNotEmpty  +

AHB buffer 3 not empty.

+
kQSPI_AHB2BufferNotEmpty  +

AHB buffer 2 not empty.

+
kQSPI_AHB1BufferNotEmpty  +

AHB buffer 1 not empty.

+
kQSPI_AHB0BufferNotEmpty  +

AHB buffer 0 not empty.

+
kQSPI_AHBTransactionPending  +

AHB access transaction pending.

+
kQSPI_AHBCommandPriorityGranted  +

AHB command priority granted.

+
kQSPI_AHBAccess  +

AHB access.

+
kQSPI_IPAccess  +

IP access.

+
kQSPI_Busy  +

Module busy.

+
kQSPI_StateAll  +

All flags.

+
+ +
+
+ +
+
+ + + + +
enum _qspi_interrupt_enable
+
+ + + + + + + + + + + + + + + +
Enumerator
kQSPI_DataLearningFailInterruptEnable  +

Data learning pattern failure interrupt enable.

+
kQSPI_TxBufferFillInterruptEnable  +

Tx buffer fill interrupt enable.

+
kQSPI_TxBufferUnderrunInterruptEnable  +

Tx buffer underrun interrupt enable.

+
kQSPI_IllegalInstructionInterruptEnable  +

Illegal instruction error interrupt enable.

+
kQSPI_RxBufferOverflowInterruptEnable  +

Rx buffer overflow interrupt enable.

+
kQSPI_RxBufferDrainInterruptEnable  +

Rx buffer drain interrupt enable.

+
kQSPI_AHBSequenceErrorInterruptEnable  +

AHB sequence error interrupt enable.

+
kQSPI_AHBBufferOverflowInterruptEnable  +

AHB buffer overflow interrupt enable.

+
kQSPI_IPCommandUsageErrorInterruptEnable  +

IP command usage error interrupt enable.

+
kQSPI_IPCommandTriggerDuringAHBAccessInterruptEnable  +

IP command trigger during AHB access error.

+
kQSPI_IPCommandTriggerDuringIPAccessInterruptEnable  +

IP command trigger cannot be executed.

+
kQSPI_IPCommandTriggerDuringAHBGrantInterruptEnable  +

IP command trigger during AHB grant error.

+
kQSPI_IPCommandTransactionFinishedInterruptEnable  +

IP command transaction finished interrupt enable.

+
kQSPI_AllInterruptEnable  +

All error interrupt enable.

+
+ +
+
+ +
+
+ + + + +
enum _qspi_dma_enable
+
+ + +
Enumerator
kQSPI_RxBufferDrainDMAEnable  +

Rx buffer drain DMA.

+
+ +
+
+ +
+
+ + + + +
enum qspi_dqs_phrase_shift_t
+
+ + + + + +
Enumerator
kQSPI_DQSNoPhraseShift  +

No phase shift.

+
kQSPI_DQSPhraseShift45Degree  +

Select 45 degree phase shift.

+
kQSPI_DQSPhraseShift90Degree  +

Select 90 degree phase shift.

+
kQSPI_DQSPhraseShift135Degree  +

Select 135 degree phase shift.

+
+ +
+
+ +
+
+ + + + +
enum qspi_dqs_read_sample_clock_t
+
+ + + + +
Enumerator
kQSPI_ReadSampleClkInternalLoopback  +

Read sample clock adopts internal loopback mode.

+
kQSPI_ReadSampleClkLoopbackFromDqsPad  +

Dummy Read strobe generated by QSPI Controller and loopback from DQS pad.

+
kQSPI_ReadSampleClkExternalInputFromDqsPad  +

Flash provided Read strobe and input from DQS pad.

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t QSPI_GetInstance (QuadSPI_Type * base)
+
+
Parameters
+ + +
baseQSPI base pointer.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void QSPI_Init (QuadSPI_Type * base,
qspi_config_t * config,
uint32_t srcClock_Hz 
)
+
+

This function enables the clock for QSPI and also configures the QSPI with the input configure parameters. Users should call this function before any QSPI operations.

+
Parameters
+ + + + +
basePointer to QuadSPI Type.
configQSPI configure structure.
srcClock_HzQSPI source clock frequency in Hz.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void QSPI_GetDefaultQspiConfig (qspi_config_t * config)
+
+
Parameters
+ + +
configQSPI configuration structure.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void QSPI_Deinit (QuadSPI_Type * base)
+
+

Clears the QSPI state and QSPI module registers.

+
Parameters
+ + +
basePointer to QuadSPI Type.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void QSPI_SetFlashConfig (QuadSPI_Type * base,
qspi_flash_config_t * config 
)
+
+

This function configures the serial flash relevant parameters, such as the size, command, and so on. The flash configuration value cannot have a default value. The user needs to configure it according to the QSPI features.

+
Parameters
+ + + +
basePointer to QuadSPI Type.
configFlash configuration parameters.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void QSPI_SoftwareReset (QuadSPI_Type * base)
+
+

This function sets the software reset flags for both AHB and buffer domain and resets both AHB buffer and also IP FIFOs.

+
Parameters
+ + +
basePointer to QuadSPI Type.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_Enable (QuadSPI_Type * base,
bool enable 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePointer to QuadSPI Type.
enableTrue means enable QSPI, false means disable.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t QSPI_GetStatusFlags (QuadSPI_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
basePointer to QuadSPI Type.
+
+
+
Returns
status flag, use status flag to AND _qspi_flags could get the related status.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t QSPI_GetErrorStatusFlags (QuadSPI_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
basePointer to QuadSPI Type.
+
+
+
Returns
status flag, use status flag to AND _qspi_error_flags could get the related status.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_ClearErrorFlag (QuadSPI_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePointer to QuadSPI Type.
maskWhich kind of QSPI flags to be cleared, a combination of _qspi_error_flags.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_EnableInterrupts (QuadSPI_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePointer to QuadSPI Type.
maskQSPI interrupt source.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_DisableInterrupts (QuadSPI_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePointer to QuadSPI Type.
maskQSPI interrupt source.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void QSPI_EnableDMA (QuadSPI_Type * base,
uint32_t mask,
bool enable 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
basePointer to QuadSPI Type.
maskQSPI DMA source.
enableTrue means enable DMA, false means disable.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t QSPI_GetTxDataRegisterAddress (QuadSPI_Type * base)
+ 		+inlinestatic
+
+

It is used for DMA operation.

+
Parameters
+ + +
basePointer to QuadSPI Type.
+
+
+
Returns
QSPI Tx data register address.
+ +
+
+ +
+
+ + + + + + + + +
uint32_t QSPI_GetRxDataRegisterAddress (QuadSPI_Type * base)
+
+

This function returns the Rx data register address or Rx buffer address according to the Rx read area settings.

+
Parameters
+ + +
basePointer to QuadSPI Type.
+
+
+
Returns
QSPI Rx data register address.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_SetIPCommandAddress (QuadSPI_Type * base,
uint32_t addr 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePointer to QuadSPI Type.
addrIP command address.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_SetIPCommandSize (QuadSPI_Type * base,
uint32_t size 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePointer to QuadSPI Type.
sizeIP command size.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void QSPI_ExecuteIPCommand (QuadSPI_Type * base,
uint32_t index 
)
+
+
Parameters
+ + + +
basePointer to QuadSPI Type.
indexIP command located in which LUT table index.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void QSPI_ExecuteAHBCommand (QuadSPI_Type * base,
uint32_t index 
)
+
+
Parameters
+ + + +
basePointer to QuadSPI Type.
indexAHB command located in which LUT table index.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_EnableIPParallelMode (QuadSPI_Type * base,
bool enable 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePointer to QuadSPI Type.
enableTrue means enable parallel mode, false means disable parallel mode.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_EnableAHBParallelMode (QuadSPI_Type * base,
bool enable 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePointer to QuadSPI Type.
enableTrue means enable parallel mode, false means disable parallel mode.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void QSPI_UpdateLUT (QuadSPI_Type * base,
uint32_t index,
uint32_t * cmd 
)
+
+
Parameters
+ + + + +
basePointer to QuadSPI Type.
indexWhich LUT index needs to be located. It should be an integer divided by 4.
cmdCommand sequence array.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_ClearFifo (QuadSPI_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePointer to QuadSPI Type.
maskWhich kind of QSPI FIFO to be cleared.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_ClearCommandSequence (QuadSPI_Type * base,
qspi_command_seq_t seq 
)
+ 		+inlinestatic
+
+

This function can reset the command sequence.

+
Parameters
+ + + +
baseQSPI base address.
seqWhich command sequence need to reset, IP command, buffer command or both.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_EnableDDRMode (QuadSPI_Type * base,
bool enable 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseQSPI base pointer
enableTrue means enable DDR mode, false means disable DDR mode.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void QSPI_SetReadDataArea (QuadSPI_Type * base,
qspi_read_area_t area 
)
+
+

This function can set the RX buffer readout, from AHB bus or IP Bus.

+
Parameters
+ + + +
baseQSPI base address.
areaQSPI Rx buffer readout area. AHB bus buffer or IP bus buffer.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void QSPI_WriteBlocking (QuadSPI_Type * base,
uint32_t * buffer,
size_t size 
)
+
+
Note
This function blocks via polling until all bytes have been sent.
+
Parameters
+ + + + +
baseQSPI base pointer
bufferThe data bytes to send
sizeThe number of data bytes to send
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_WriteData (QuadSPI_Type * base,
uint32_t data 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseQSPI base pointer
dataThe data bytes to send
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void QSPI_ReadBlocking (QuadSPI_Type * base,
uint32_t * buffer,
size_t size 
)
+
+
Note
This function blocks via polling until all bytes have been sent. Users shall notice that this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers. For flash contents read, please use AHB bus read, this is much more efficiency.
+
Parameters
+ + + + +
baseQSPI base pointer
bufferThe data bytes to send
sizeThe number of data bytes to receive
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t QSPI_ReadData (QuadSPI_Type * base)
+
+
Parameters
+ + +
baseQSPI base pointer
+
+
+
Returns
The data in the FIFO.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_TransferSendBlocking (QuadSPI_Type * base,
qspi_transfer_t * xfer 
)
+ 		+inlinestatic
+
+

This function writes a continuous data to the QSPI transmit FIFO. This function is a block function and can return only when finished. This function uses polling methods.

+
Parameters
+ + + +
basePointer to QuadSPI Type.
xferQSPI transfer structure.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void QSPI_TransferReceiveBlocking (QuadSPI_Type * base,
qspi_transfer_t * xfer 
)
+ 		+inlinestatic
+
+

This function reads continuous data from the QSPI receive buffer/FIFO. This function is a blocking function and can return only when finished. This function uses polling methods. Users shall notice that this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers. For flash contents read, please use AHB bus read, this is much more efficiency.

+
Parameters
+ + + +
basePointer to QuadSPI Type.
xferQSPI transfer structure.
+
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00014.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00014.js new file mode 100644 index 000000000..91f1db586 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00014.js @@ -0,0 +1,176 @@ +var a00014 = +[ + [ "qspi_dqs_config_t", "a00014.html#a00135", [ + [ "portADelayTapNum", "a00014.html#ab166711d9c9ea0accacffbd9463ba91a", null ], + [ "shift", "a00014.html#a41a08deef01859490a87688da1a2f166", null ], + [ "rxSampleClock", "a00014.html#ad1f0bd234f0c3fb83147c25819949729", null ], + [ "enableDQSClkInverse", "a00014.html#a501b65137e9c19834a56df7812708328", null ] + ] ], + [ "qspi_flash_timing_t", "a00014.html#a00137", [ + [ "dataHoldTime", "a00014.html#a1c4812527eaebb35bab982a6635b4106", null ], + [ "CSHoldTime", "a00014.html#a46b400bc95b18888574e5d20ae4c2c1e", null ], + [ "CSSetupTime", "a00014.html#a94b7c0ea1ba1f3dbf06b11062d0e8e85", null ] + ] ], + [ "qspi_config_t", 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null ], + [ "QSPI_WriteData", "a00014.html#gaf6225414bf13955c55471779308d531c", null ], + [ "QSPI_ReadBlocking", "a00014.html#ga4aab7113f914858544075e60dc3b6c4f", null ], + [ "QSPI_ReadData", "a00014.html#ga673d32dc8663771f44cdda19b091a5d3", null ], + [ "QSPI_TransferSendBlocking", "a00014.html#gaba3ec60feea5813ae34fc7fb75f6d2db", null ], + [ "QSPI_TransferReceiveBlocking", "a00014.html#ga2734478dd21ba237b925e1e86e147580", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00015.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00015.html new file mode 100644 index 000000000..a325c1806 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00015.html @@ -0,0 +1,1553 @@ + + + + + + +MCUXpresso SDK API Reference Manual: RDC: Resource Domain Controller + + + + + + + + + + + + + + +
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+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
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+Data Structures | +Enumerations | +Functions
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+
RDC: Resource Domain Controller
+
+
+

Overview

+

The MCUXpresso SDK provides a driver for the RDC module of MCUXpresso SDK devices.

+

The Resource Domain Controller (RDC) provides robust support for the isolation of destination memory mapped locations such as peripherals and memory to a single core, a bus master, or set of cores and bus masters.
+ The RDC driver should be used together with the RDC_SEMA42 driver.

+ + + + + + + + + + + + + + + + + +

+Data Structures

struct  rdc_hardware_config_t
 RDC hardware configuration. More...
 
struct  rdc_domain_assignment_t
 Master domain assignment. More...
 
struct  rdc_periph_access_config_t
 Peripheral domain access permission configuration. More...
 
struct  rdc_mem_access_config_t
 Memory region domain access control configuration. More...
 
struct  rdc_mem_status_t
 Memory region access violation status. More...
 
+ + + + + + + + + + +

+Enumerations

enum  _rdc_interrupts { kRDC_RestoreCompleteInterrupt = RDC_INTCTRL_RCI_EN_MASK + }
 RDC interrupts. More...
 
enum  _rdc_flags { kRDC_PowerDownDomainOn = RDC_STAT_PDS_MASK + }
 RDC status. More...
 
enum  _rdc_access_policy {
+  kRDC_NoAccess = 0, +
+  kRDC_WriteOnly = 1, +
+  kRDC_ReadOnly = 2, +
+  kRDC_ReadWrite = 3 +
+ }
 Access permission policy. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void RDC_Init (RDC_Type *base)
 Initializes the RDC module. More...
 
void RDC_Deinit (RDC_Type *base)
 De-initializes the RDC module. More...
 
void RDC_GetHardwareConfig (RDC_Type *base, rdc_hardware_config_t *config)
 Gets the RDC hardware configuration. More...
 
static void RDC_EnableInterrupts (RDC_Type *base, uint32_t mask)
 Enable interrupts. More...
 
static void RDC_DisableInterrupts (RDC_Type *base, uint32_t mask)
 Disable interrupts. More...
 
static uint32_t RDC_GetInterruptStatus (RDC_Type *base)
 Get the interrupt pending status. More...
 
static void RDC_ClearInterruptStatus (RDC_Type *base, uint32_t mask)
 Clear interrupt pending status. More...
 
static uint32_t RDC_GetStatus (RDC_Type *base)
 Get RDC status. More...
 
static void RDC_ClearStatus (RDC_Type *base, uint32_t mask)
 Clear RDC status. More...
 
void RDC_SetMasterDomainAssignment (RDC_Type *base, rdc_master_t master, const rdc_domain_assignment_t *domainAssignment)
 Set master domain assignment. More...
 
void RDC_GetDefaultMasterDomainAssignment (rdc_domain_assignment_t *domainAssignment)
 Get default master domain assignment. More...
 
static void RDC_LockMasterDomainAssignment (RDC_Type *base, rdc_master_t master)
 Lock master domain assignment. More...
 
void RDC_SetPeriphAccessConfig (RDC_Type *base, const rdc_periph_access_config_t *config)
 Set peripheral access policy. More...
 
void RDC_GetDefaultPeriphAccessConfig (rdc_periph_access_config_t *config)
 Get default peripheral access policy. More...
 
static void RDC_LockPeriphAccessConfig (RDC_Type *base, rdc_periph_t periph)
 Lock peripheral access policy configuration. More...
 
static uint8_t RDC_GetPeriphAccessPolicy (RDC_Type *base, rdc_periph_t periph, uint8_t domainId)
 Get the peripheral access policy for specific domain. More...
 
void RDC_SetMemAccessConfig (RDC_Type *base, const rdc_mem_access_config_t *config)
 Set memory region access policy. More...
 
void RDC_GetDefaultMemAccessConfig (rdc_mem_access_config_t *config)
 Get default memory region access policy. More...
 
static void RDC_LockMemAccessConfig (RDC_Type *base, rdc_mem_t mem)
 Lock memory access policy configuration. More...
 
static void RDC_SetMemAccessValid (RDC_Type *base, rdc_mem_t mem, bool valid)
 Enable or disable memory access policy configuration. More...
 
void RDC_GetMemViolationStatus (RDC_Type *base, rdc_mem_t mem, rdc_mem_status_t *status)
 Get the memory region violation status. More...
 
static void RDC_ClearMemViolationFlag (RDC_Type *base, rdc_mem_t mem)
 Clear the memory region violation flag. More...
 
static uint8_t RDC_GetMemAccessPolicy (RDC_Type *base, rdc_mem_t mem, uint8_t domainId)
 Get the memory region access policy for specific domain. More...
 
static uint8_t RDC_GetCurrentMasterDomainId (RDC_Type *base)
 Gets the domain ID of the current bus master. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct rdc_hardware_config_t
+
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+ + + + + + + + + + + + + +

Data Fields

uint32_t domainNumber: 4
 Number of domains. More...
 
uint32_t masterNumber: 8
 Number of bus masters. More...
 
uint32_t periphNumber: 8
 Number of peripherals. More...
 
uint32_t memNumber: 8
 Number of memory regions. More...
 
+

Field Documentation

+ +
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uint32_t rdc_hardware_config_t::domainNumber
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uint32_t rdc_hardware_config_t::masterNumber
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uint32_t rdc_hardware_config_t::periphNumber
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uint32_t rdc_hardware_config_t::memNumber
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struct rdc_domain_assignment_t
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Data Fields

uint32_t domainId: 2U
 Domain ID. More...
 
uint32_t __pad0__: 29U
 Reserved. More...
 
uint32_t lock: 1U
 Lock the domain assignment. More...
 
+

Field Documentation

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uint32_t rdc_domain_assignment_t::domainId
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uint32_t rdc_domain_assignment_t::__pad0__
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uint32_t rdc_domain_assignment_t::lock
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struct rdc_periph_access_config_t
+
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Data Fields

rdc_periph_t periph
 Peripheral name. More...
 
bool lock
 Lock the permission until reset. More...
 
bool enableSema
 Enable semaphore or not, when enabled, master should call RDC_SEMA42_Lock to lock the semaphore gate accordingly before access the peripheral. More...
 
uint16_t policy
 Access policy. More...
 
+

Field Documentation

+ +
+
+ + + + +
rdc_periph_t rdc_periph_access_config_t::periph
+
+ +
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+ +
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bool rdc_periph_access_config_t::lock
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bool rdc_periph_access_config_t::enableSema
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uint16_t rdc_periph_access_config_t::policy
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struct rdc_mem_access_config_t
+
+

Note that when setting the baseAddress and endAddress, should be aligned to the region resolution, see rdc_mem_t definitions.

+
+ + + + + + + + + + + + + + + + +

Data Fields

rdc_mem_t mem
 Memory region descriptor name. More...
 
bool lock
 Lock the configuration. More...
 
uint64_t baseAddress
 Start address of the memory region. More...
 
uint64_t endAddress
 End address of the memory region. More...
 
uint16_t policy
 Access policy. More...
 
+

Field Documentation

+ +
+
+ + + + +
rdc_mem_t rdc_mem_access_config_t::mem
+
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bool rdc_mem_access_config_t::lock
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uint64_t rdc_mem_access_config_t::baseAddress
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uint64_t rdc_mem_access_config_t::endAddress
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uint16_t rdc_mem_access_config_t::policy
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struct rdc_mem_status_t
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Data Fields

bool hasViolation
 Violating happens or not. More...
 
uint8_t domainID
 Violating Domain ID. More...
 
uint64_t address
 Violating Address. More...
 
+

Field Documentation

+ +
+
+ + + + +
bool rdc_mem_status_t::hasViolation
+
+ +
+
+ +
+
+ + + + +
uint8_t rdc_mem_status_t::domainID
+
+ +
+
+ +
+
+ + + + +
uint64_t rdc_mem_status_t::address
+
+ +
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum _rdc_interrupts
+
+ + +
Enumerator
kRDC_RestoreCompleteInterrupt  +

Interrupt generated when the RDC has completed restoring state to a recently re-powered memory regions.

+
+ +
+
+ +
+
+ + + + +
enum _rdc_flags
+
+ + +
Enumerator
kRDC_PowerDownDomainOn  +

Power down domain is ON.

+
+ +
+
+ +
+
+ + + + +
enum _rdc_access_policy
+
+ + + + + +
Enumerator
kRDC_NoAccess  +

Could not read or write.

+
kRDC_WriteOnly  +

Write only.

+
kRDC_ReadOnly  +

Read only.

+
kRDC_ReadWrite  +

Read and write.

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
void RDC_Init (RDC_Type * base)
+
+

This function enables the RDC clock.

+
Parameters
+ + +
baseRDC peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RDC_Deinit (RDC_Type * base)
+
+

This function disables the RDC clock.

+
Parameters
+ + +
baseRDC peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RDC_GetHardwareConfig (RDC_Type * base,
rdc_hardware_config_t * config 
)
+
+

This function gets the RDC hardware configurations, including number of bus masters, number of domains, number of memory regions and number of peripherals.

+
Parameters
+ + + +
baseRDC peripheral base address.
configPointer to the structure to get the configuration.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void RDC_EnableInterrupts (RDC_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseRDC peripheral base address.
maskInterrupts to enable, it is OR'ed value of enum _rdc_interrupts.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void RDC_DisableInterrupts (RDC_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseRDC peripheral base address.
maskInterrupts to disable, it is OR'ed value of enum _rdc_interrupts.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t RDC_GetInterruptStatus (RDC_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseRDC peripheral base address.
+
+
+
Returns
Interrupts pending status, it is OR'ed value of enum _rdc_interrupts.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void RDC_ClearInterruptStatus (RDC_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseRDC peripheral base address.
maskStatus to clear, it is OR'ed value of enum _rdc_interrupts.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t RDC_GetStatus (RDC_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseRDC peripheral base address.
+
+
+
Returns
mask RDC status, it is OR'ed value of enum _rdc_flags.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void RDC_ClearStatus (RDC_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseRDC peripheral base address.
maskRDC status to clear, it is OR'ed value of enum _rdc_flags.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void RDC_SetMasterDomainAssignment (RDC_Type * base,
rdc_master_t master,
const rdc_domain_assignment_t * domainAssignment 
)
+
+
Parameters
+ + + + +
baseRDC peripheral base address.
masterWhich master to set.
domainAssignmentPointer to the assignment.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RDC_GetDefaultMasterDomainAssignment (rdc_domain_assignment_t * domainAssignment)
+
+

The default configuration is:

+
assignment->domainId = 0U;
+
assignment->lock = 0U;
+
Parameters
+ + +
domainAssignmentPointer to the assignment.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void RDC_LockMasterDomainAssignment (RDC_Type * base,
rdc_master_t master 
)
+ 		+inlinestatic
+
+

Once locked, it could not be unlocked until next reset.

+
Parameters
+ + + +
baseRDC peripheral base address.
masterWhich master to lock.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RDC_SetPeriphAccessConfig (RDC_Type * base,
const rdc_periph_access_config_t * config 
)
+
+
Parameters
+ + + +
baseRDC peripheral base address.
configPointer to the policy configuration.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RDC_GetDefaultPeriphAccessConfig (rdc_periph_access_config_t * config)
+
+

The default configuration is:

+
config->lock = false;
+
config->enableSema = false;
+
config->policy = RDC_ACCESS_POLICY(0, kRDC_ReadWrite) |
+
RDC_ACCESS_POLICY(1, kRDC_ReadWrite) |
+
RDC_ACCESS_POLICY(2, kRDC_ReadWrite) |
+
RDC_ACCESS_POLICY(3, kRDC_ReadWrite);
+
Parameters
+ + +
configPointer to the policy configuration.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void RDC_LockPeriphAccessConfig (RDC_Type * base,
rdc_periph_t periph 
)
+ 		+inlinestatic
+
+

Once locked, it could not be unlocked until reset.

+
Parameters
+ + + +
baseRDC peripheral base address.
periphWhich peripheral to lock.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static uint8_t RDC_GetPeriphAccessPolicy (RDC_Type * base,
rdc_periph_t periph,
uint8_t domainId 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseRDC peripheral base address.
periphWhich peripheral to get.
domainIdGet policy for which domain.
+
+
+
Returns
Access policy, see _rdc_access_policy.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RDC_SetMemAccessConfig (RDC_Type * base,
const rdc_mem_access_config_t * config 
)
+
+

Note that when setting the baseAddress and endAddress in config, should be aligned to the region resolution, see rdc_mem_t definitions.

+
Parameters
+ + + +
baseRDC peripheral base address.
configPointer to the policy configuration.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RDC_GetDefaultMemAccessConfig (rdc_mem_access_config_t * config)
+
+

The default configuration is:

+
config->lock = false;
+
config->baseAddress = 0;
+
config->endAddress = 0;
+
config->policy = RDC_ACCESS_POLICY(0, kRDC_ReadWrite) |
+
RDC_ACCESS_POLICY(1, kRDC_ReadWrite) |
+
RDC_ACCESS_POLICY(2, kRDC_ReadWrite) |
+
RDC_ACCESS_POLICY(3, kRDC_ReadWrite);
+
Parameters
+ + +
configPointer to the policy configuration.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void RDC_LockMemAccessConfig (RDC_Type * base,
rdc_mem_t mem 
)
+ 		+inlinestatic
+
+

Once locked, it could not be unlocked until reset. After locked, you can only call RDC_SetMemAccessValid to enable the configuration, but can not disable it or change other settings.

+
Parameters
+ + + +
baseRDC peripheral base address.
memWhich memory region to lock.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void RDC_SetMemAccessValid (RDC_Type * base,
rdc_mem_t mem,
bool valid 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseRDC peripheral base address.
memWhich memory region to operate.
validPass in true to valid, false to invalid.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void RDC_GetMemViolationStatus (RDC_Type * base,
rdc_mem_t mem,
rdc_mem_status_t * status 
)
+
+

The first access violation is captured. Subsequent violations are ignored until the status register is cleared. Contents are cleared upon reading the register. Clearing of contents occurs only when the status is read by the memory region's associated domain ID(s).

+
Parameters
+ + + + +
baseRDC peripheral base address.
memWhich memory region to get.
statusThe returned status.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void RDC_ClearMemViolationFlag (RDC_Type * base,
rdc_mem_t mem 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseRDC peripheral base address.
memWhich memory region to clear.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static uint8_t RDC_GetMemAccessPolicy (RDC_Type * base,
rdc_mem_t mem,
uint8_t domainId 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseRDC peripheral base address.
memWhich memory region to get.
domainIdGet policy for which domain.
+
+
+
Returns
Access policy, see _rdc_access_policy.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint8_t RDC_GetCurrentMasterDomainId (RDC_Type * base)
+ 		+inlinestatic
+
+

This function returns the domain ID of the current bus master.

+
Parameters
+ + +
baseRDC peripheral base address.
+
+
+
Returns
Domain ID of current bus master.
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00015.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00015.js new file mode 100644 index 000000000..f8b65aea9 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00015.js @@ -0,0 +1,68 @@ +var a00015 = +[ + [ "rdc_hardware_config_t", "a00015.html#a00140", [ + [ "domainNumber", "a00015.html#a739ea4a24186ac54d3d97ec1bcda5631", null ], + [ "masterNumber", "a00015.html#a81842ff8d313ca38916e3226efdd3bde", null ], + [ "periphNumber", "a00015.html#ac02b7c759b76aac047c8dfd86fd93a59", null ], + [ "memNumber", "a00015.html#afb605761a847c152ab23a5790b44dee9", null ] + ] ], + [ "rdc_domain_assignment_t", "a00015.html#a00139", [ + [ "domainId", "a00015.html#a6e918db4f50ef773621e9f90a8dd0aa1", null ], + [ "__pad0__", "a00015.html#a8d76c2ce9f3ab1bd748c21c409e14b08", null ], + [ "lock", "a00015.html#add7373049bb837ae009d9d6f54d6c042", null ] + ] ], + [ "rdc_periph_access_config_t", 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null ] + ] ], + [ "_rdc_interrupts", "a00015.html#ga43f5d8d1ed667a8c73ab204a74925892", [ + [ "kRDC_RestoreCompleteInterrupt", "a00015.html#gga43f5d8d1ed667a8c73ab204a74925892a5088cfe20c6ef9e259657e6f6ecc7387", null ] + ] ], + [ "_rdc_flags", "a00015.html#ga30afa024532b0207bdeeee3344af9ebd", [ + [ "kRDC_PowerDownDomainOn", "a00015.html#gga30afa024532b0207bdeeee3344af9ebda5e58c4dabb46b1f4a47b7ae8cd0f61e3", null ] + ] ], + [ "_rdc_access_policy", "a00015.html#gad1f726221167c740e1500317ea80beb2", [ + [ "kRDC_NoAccess", "a00015.html#ggad1f726221167c740e1500317ea80beb2a3abbfd7f6818ca32df8d30300aba7f1a", null ], + [ "kRDC_WriteOnly", "a00015.html#ggad1f726221167c740e1500317ea80beb2af704f2f758ba0d96ddea53e686325efe", null ], + [ "kRDC_ReadOnly", "a00015.html#ggad1f726221167c740e1500317ea80beb2acad6ad0fa9f2d31d48ec9e7b2898cdb6", null ], + [ "kRDC_ReadWrite", "a00015.html#ggad1f726221167c740e1500317ea80beb2a45a95e9ad49ab28807dc57a67e770ebd", null ] + ] ], + [ "RDC_Init", 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"a00015.html#gab4b8ce2df7a0ccd22d90d897a80616fb", null ], + [ "RDC_GetCurrentMasterDomainId", "a00015.html#gacf0861a99d3a45d022fef5dd35f158c5", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00016.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00016.html new file mode 100644 index 000000000..04d982adf --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00016.html @@ -0,0 +1,4923 @@ + + + + + + +MCUXpresso SDK API Reference Manual: SAI Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Macros | +Typedefs | +Enumerations
+
+
SAI Driver
SAI: Serial Audio Interface
+
+
+

Overview

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Structures

struct  sai_config_t
 SAI user configuration structure. More...
 
struct  sai_transfer_format_t
 sai transfer format More...
 
struct  sai_fifo_t
 sai fifo configurations More...
 
struct  sai_bit_clock_t
 sai bit clock configurations More...
 
struct  sai_frame_sync_t
 sai frame sync configurations More...
 
struct  sai_serial_data_t
 sai serial data configurations More...
 
struct  sai_transceiver_t
 sai transceiver configurations More...
 
struct  sai_transfer_t
 SAI transfer structure. More...
 
struct  sai_handle_t
 SAI handle structure. More...
 
+ + + + + + + +

+Macros

#define SAI_XFER_QUEUE_SIZE   (4U)
 SAI transfer queue size, user can refine it according to use case. More...
 
+#define FSL_SAI_HAS_FIFO_EXTEND_FEATURE   1
 sai fifo feature
 
+ + + + +

+Typedefs

+typedef void(* sai_transfer_callback_t )(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData)
 SAI transfer callback prototype.
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Enumerations

enum  {
+  kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0), +
+  kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1), +
+  kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2), +
+  kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3), +
+  kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), +
+  kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5), +
+  kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) +
+ }
 _sai_status_t, SAI return status. More...
 
enum  {
+  kSAI_Channel0Mask = 1 << 0U, +
+  kSAI_Channel1Mask = 1 << 1U, +
+  kSAI_Channel2Mask = 1 << 2U, +
+  kSAI_Channel3Mask = 1 << 3U, +
+  kSAI_Channel4Mask = 1 << 4U, +
+  kSAI_Channel5Mask = 1 << 5U, +
+  kSAI_Channel6Mask = 1 << 6U, +
+  kSAI_Channel7Mask = 1 << 7U +
+ }
 _sai_channel_mask,.sai channel mask value, actual channel numbers is depend soc specific More...
 
enum  sai_protocol_t {
+  kSAI_BusLeftJustified = 0x0U, +
+  kSAI_BusRightJustified, +
+  kSAI_BusI2S, +
+  kSAI_BusPCMA, +
+  kSAI_BusPCMB +
+ }
 Define the SAI bus type. More...
 
enum  sai_master_slave_t {
+  kSAI_Master = 0x0U, +
+  kSAI_Slave = 0x1U, +
+  kSAI_Bclk_Master_FrameSync_Slave = 0x2U, +
+  kSAI_Bclk_Slave_FrameSync_Master = 0x3U +
+ }
 Master or slave mode. More...
 
enum  sai_mono_stereo_t {
+  kSAI_Stereo = 0x0U, +
+  kSAI_MonoRight, +
+  kSAI_MonoLeft +
+ }
 Mono or stereo audio format. More...
 
enum  sai_data_order_t {
+  kSAI_DataLSB = 0x0U, +
+  kSAI_DataMSB +
+ }
 SAI data order, MSB or LSB. More...
 
enum  sai_clock_polarity_t {
+  kSAI_PolarityActiveHigh = 0x0U, +
+  kSAI_PolarityActiveLow = 0x1U, +
+  kSAI_SampleOnFallingEdge = 0x0U, +
+  kSAI_SampleOnRisingEdge = 0x1U +
+ }
 SAI clock polarity, active high or low. More...
 
enum  sai_sync_mode_t {
+  kSAI_ModeAsync = 0x0U, +
+  kSAI_ModeSync +
+ }
 Synchronous or asynchronous mode. More...
 
enum  sai_bclk_source_t {
+  kSAI_BclkSourceBusclk = 0x0U, +
+  kSAI_BclkSourceMclkOption1 = 0x1U, +
+  kSAI_BclkSourceMclkOption2 = 0x2U, +
+  kSAI_BclkSourceMclkOption3 = 0x3U, +
+  kSAI_BclkSourceMclkDiv = 0x1U, +
+  kSAI_BclkSourceOtherSai0 = 0x2U, +
+  kSAI_BclkSourceOtherSai1 = 0x3U +
+ }
 Bit clock source. More...
 
enum  {
+  kSAI_WordStartInterruptEnable, +
+  kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK, +
+  kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, +
+  kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK, +
+  kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK +
+ }
 _sai_interrupt_enable_t, The SAI interrupt enable flag More...
 
enum  {
+  kSAI_FIFOWarningDMAEnable = I2S_TCSR_FWDE_MASK, +
+  kSAI_FIFORequestDMAEnable = I2S_TCSR_FRDE_MASK +
+ }
 _sai_dma_enable_t, The DMA request sources More...
 
enum  {
+  kSAI_WordStartFlag = I2S_TCSR_WSF_MASK, +
+  kSAI_SyncErrorFlag = I2S_TCSR_SEF_MASK, +
+  kSAI_FIFOErrorFlag = I2S_TCSR_FEF_MASK, +
+  kSAI_FIFORequestFlag = I2S_TCSR_FRF_MASK, +
+  kSAI_FIFOWarningFlag = I2S_TCSR_FWF_MASK +
+ }
 _sai_flags, The SAI status flag More...
 
enum  sai_reset_type_t {
+  kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, +
+  kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK, +
+  kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK +
+ }
 The reset type. More...
 
enum  sai_fifo_packing_t {
+  kSAI_FifoPackingDisabled = 0x0U, +
+  kSAI_FifoPacking8bit = 0x2U, +
+  kSAI_FifoPacking16bit = 0x3U +
+ }
 The SAI packing mode The mode includes 8 bit and 16 bit packing. More...
 
enum  sai_sample_rate_t {
+  kSAI_SampleRate8KHz = 8000U, +
+  kSAI_SampleRate11025Hz = 11025U, +
+  kSAI_SampleRate12KHz = 12000U, +
+  kSAI_SampleRate16KHz = 16000U, +
+  kSAI_SampleRate22050Hz = 22050U, +
+  kSAI_SampleRate24KHz = 24000U, +
+  kSAI_SampleRate32KHz = 32000U, +
+  kSAI_SampleRate44100Hz = 44100U, +
+  kSAI_SampleRate48KHz = 48000U, +
+  kSAI_SampleRate96KHz = 96000U, +
+  kSAI_SampleRate192KHz = 192000U, +
+  kSAI_SampleRate384KHz = 384000U +
+ }
 Audio sample rate. More...
 
enum  sai_word_width_t {
+  kSAI_WordWidth8bits = 8U, +
+  kSAI_WordWidth16bits = 16U, +
+  kSAI_WordWidth24bits = 24U, +
+  kSAI_WordWidth32bits = 32U +
+ }
 Audio word width. More...
 
enum  sai_data_pin_state_t {
+  kSAI_DataPinStateTriState, +
+  kSAI_DataPinStateOutputZero = 1U +
+ }
 sai data pin state definition More...
 
enum  sai_transceiver_type_t {
+  kSAI_Transmitter = 0U, +
+  kSAI_Receiver = 1U +
+ }
 sai transceiver type More...
 
enum  sai_frame_sync_len_t {
+  kSAI_FrameSyncLenOneBitClk = 0U, +
+  kSAI_FrameSyncLenPerWordWidth = 1U +
+ }
 sai frame sync len More...
 
+ + + + +

+Driver version

+#define FSL_SAI_DRIVER_VERSION   (MAKE_VERSION(2, 3, 3))
 Version 2.3.3.
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Initialization and deinitialization

void SAI_TxInit (I2S_Type *base, const sai_config_t *config)
 Initializes the SAI Tx peripheral. More...
 
void SAI_RxInit (I2S_Type *base, const sai_config_t *config)
 Initializes the SAI Rx peripheral. More...
 
void SAI_TxGetDefaultConfig (sai_config_t *config)
 Sets the SAI Tx configuration structure to default values. More...
 
void SAI_RxGetDefaultConfig (sai_config_t *config)
 Sets the SAI Rx configuration structure to default values. More...
 
void SAI_Init (I2S_Type *base)
 Initializes the SAI peripheral. More...
 
void SAI_Deinit (I2S_Type *base)
 De-initializes the SAI peripheral. More...
 
void SAI_TxReset (I2S_Type *base)
 Resets the SAI Tx. More...
 
void SAI_RxReset (I2S_Type *base)
 Resets the SAI Rx. More...
 
void SAI_TxEnable (I2S_Type *base, bool enable)
 Enables/disables the SAI Tx. More...
 
void SAI_RxEnable (I2S_Type *base, bool enable)
 Enables/disables the SAI Rx. More...
 
static void SAI_TxSetBitClockDirection (I2S_Type *base, sai_master_slave_t masterSlave)
 Set Rx bit clock direction. More...
 
static void SAI_RxSetBitClockDirection (I2S_Type *base, sai_master_slave_t masterSlave)
 Set Rx bit clock direction. More...
 
static void SAI_RxSetFrameSyncDirection (I2S_Type *base, sai_master_slave_t masterSlave)
 Set Rx frame sync direction. More...
 
static void SAI_TxSetFrameSyncDirection (I2S_Type *base, sai_master_slave_t masterSlave)
 Set Tx frame sync direction. More...
 
void SAI_TxSetBitClockRate (I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)
 Transmitter bit clock rate configurations. More...
 
void SAI_RxSetBitClockRate (I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)
 Receiver bit clock rate configurations. More...
 
void SAI_TxSetBitclockConfig (I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)
 Transmitter Bit clock configurations. More...
 
void SAI_RxSetBitclockConfig (I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)
 Receiver Bit clock configurations. More...
 
void SAI_TxSetFifoConfig (I2S_Type *base, sai_fifo_t *config)
 SAI transmitter fifo configurations. More...
 
void SAI_RxSetFifoConfig (I2S_Type *base, sai_fifo_t *config)
 SAI receiver fifo configurations. More...
 
void SAI_TxSetFrameSyncConfig (I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)
 SAI transmitter Frame sync configurations. More...
 
void SAI_RxSetFrameSyncConfig (I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)
 SAI receiver Frame sync configurations. More...
 
void SAI_TxSetSerialDataConfig (I2S_Type *base, sai_serial_data_t *config)
 SAI transmitter Serial data configurations. More...
 
void SAI_RxSetSerialDataConfig (I2S_Type *base, sai_serial_data_t *config)
 SAI receiver Serial data configurations. More...
 
void SAI_TxSetConfig (I2S_Type *base, sai_transceiver_t *config)
 SAI transmitter configurations. More...
 
void SAI_RxSetConfig (I2S_Type *base, sai_transceiver_t *config)
 SAI receiver configurations. More...
 
void SAI_GetClassicI2SConfig (sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)
 Get classic I2S mode configurations. More...
 
void SAI_GetLeftJustifiedConfig (sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)
 Get left justified mode configurations. More...
 
void SAI_GetRightJustifiedConfig (sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)
 Get right justified mode configurations. More...
 
void SAI_GetTDMConfig (sai_transceiver_t *config, sai_frame_sync_len_t frameSyncWidth, sai_word_width_t bitWidth, uint32_t dataWordNum, uint32_t saiChannelMask)
 Get TDM mode configurations. More...
 
void SAI_GetDSPConfig (sai_transceiver_t *config, sai_frame_sync_len_t frameSyncWidth, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)
 Get DSP mode configurations. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Status

static uint32_t SAI_TxGetStatusFlag (I2S_Type *base)
 Gets the SAI Tx status flag state. More...
 
static void SAI_TxClearStatusFlags (I2S_Type *base, uint32_t mask)
 Clears the SAI Tx status flag state. More...
 
static uint32_t SAI_RxGetStatusFlag (I2S_Type *base)
 Gets the SAI Tx status flag state. More...
 
static void SAI_RxClearStatusFlags (I2S_Type *base, uint32_t mask)
 Clears the SAI Rx status flag state. More...
 
void SAI_TxSoftwareReset (I2S_Type *base, sai_reset_type_t type)
 Do software reset or FIFO reset . More...
 
void SAI_RxSoftwareReset (I2S_Type *base, sai_reset_type_t type)
 Do software reset or FIFO reset . More...
 
void SAI_TxSetChannelFIFOMask (I2S_Type *base, uint8_t mask)
 Set the Tx channel FIFO enable mask. More...
 
void SAI_RxSetChannelFIFOMask (I2S_Type *base, uint8_t mask)
 Set the Rx channel FIFO enable mask. More...
 
void SAI_TxSetDataOrder (I2S_Type *base, sai_data_order_t order)
 Set the Tx data order. More...
 
void SAI_RxSetDataOrder (I2S_Type *base, sai_data_order_t order)
 Set the Rx data order. More...
 
void SAI_TxSetBitClockPolarity (I2S_Type *base, sai_clock_polarity_t polarity)
 Set the Tx data order. More...
 
void SAI_RxSetBitClockPolarity (I2S_Type *base, sai_clock_polarity_t polarity)
 Set the Rx data order. More...
 
void SAI_TxSetFrameSyncPolarity (I2S_Type *base, sai_clock_polarity_t polarity)
 Set the Tx data order. More...
 
void SAI_RxSetFrameSyncPolarity (I2S_Type *base, sai_clock_polarity_t polarity)
 Set the Rx data order. More...
 
void SAI_TxSetFIFOPacking (I2S_Type *base, sai_fifo_packing_t pack)
 Set Tx FIFO packing feature. More...
 
void SAI_RxSetFIFOPacking (I2S_Type *base, sai_fifo_packing_t pack)
 Set Rx FIFO packing feature. More...
 
static void SAI_TxSetFIFOErrorContinue (I2S_Type *base, bool isEnabled)
 Set Tx FIFO error continue. More...
 
static void SAI_RxSetFIFOErrorContinue (I2S_Type *base, bool isEnabled)
 Set Rx FIFO error continue. More...
 
+ + + + + + + + + + + + + +

+Interrupts

static void SAI_TxEnableInterrupts (I2S_Type *base, uint32_t mask)
 Enables the SAI Tx interrupt requests. More...
 
static void SAI_RxEnableInterrupts (I2S_Type *base, uint32_t mask)
 Enables the SAI Rx interrupt requests. More...
 
static void SAI_TxDisableInterrupts (I2S_Type *base, uint32_t mask)
 Disables the SAI Tx interrupt requests. More...
 
static void SAI_RxDisableInterrupts (I2S_Type *base, uint32_t mask)
 Disables the SAI Rx interrupt requests. More...
 
+ + + + + + + + + + + + + +

+DMA Control

static void SAI_TxEnableDMA (I2S_Type *base, uint32_t mask, bool enable)
 Enables/disables the SAI Tx DMA requests. More...
 
static void SAI_RxEnableDMA (I2S_Type *base, uint32_t mask, bool enable)
 Enables/disables the SAI Rx DMA requests. More...
 
static uint32_t SAI_TxGetDataRegisterAddress (I2S_Type *base, uint32_t channel)
 Gets the SAI Tx data register address. More...
 
static uint32_t SAI_RxGetDataRegisterAddress (I2S_Type *base, uint32_t channel)
 Gets the SAI Rx data register address. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Bus Operations

void SAI_TxSetFormat (I2S_Type *base, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, uint32_t bclkSourceClockHz)
 Configures the SAI Tx audio format. More...
 
void SAI_RxSetFormat (I2S_Type *base, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, uint32_t bclkSourceClockHz)
 Configures the SAI Rx audio format. More...
 
void SAI_WriteBlocking (I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
 Sends data using a blocking method. More...
 
void SAI_WriteMultiChannelBlocking (I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
 Sends data to multi channel using a blocking method. More...
 
static void SAI_WriteData (I2S_Type *base, uint32_t channel, uint32_t data)
 Writes data into SAI FIFO. More...
 
void SAI_ReadBlocking (I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
 Receives data using a blocking method. More...
 
void SAI_ReadMultiChannelBlocking (I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
 Receives multi channel data using a blocking method. More...
 
static uint32_t SAI_ReadData (I2S_Type *base, uint32_t channel)
 Reads data from the SAI FIFO. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Transactional

void SAI_TransferTxCreateHandle (I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)
 Initializes the SAI Tx handle. More...
 
void SAI_TransferRxCreateHandle (I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)
 Initializes the SAI Rx handle. More...
 
void SAI_TransferTxSetConfig (I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)
 SAI transmitter transfer configurations. More...
 
void SAI_TransferRxSetConfig (I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)
 SAI receiver transfer configurations. More...
 
status_t SAI_TransferTxSetFormat (I2S_Type *base, sai_handle_t *handle, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, uint32_t bclkSourceClockHz)
 Configures the SAI Tx audio format. More...
 
status_t SAI_TransferRxSetFormat (I2S_Type *base, sai_handle_t *handle, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, uint32_t bclkSourceClockHz)
 Configures the SAI Rx audio format. More...
 
status_t SAI_TransferSendNonBlocking (I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)
 Performs an interrupt non-blocking send transfer on SAI. More...
 
status_t SAI_TransferReceiveNonBlocking (I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)
 Performs an interrupt non-blocking receive transfer on SAI. More...
 
status_t SAI_TransferGetSendCount (I2S_Type *base, sai_handle_t *handle, size_t *count)
 Gets a set byte count. More...
 
status_t SAI_TransferGetReceiveCount (I2S_Type *base, sai_handle_t *handle, size_t *count)
 Gets a received byte count. More...
 
void SAI_TransferAbortSend (I2S_Type *base, sai_handle_t *handle)
 Aborts the current send. More...
 
void SAI_TransferAbortReceive (I2S_Type *base, sai_handle_t *handle)
 Aborts the current IRQ receive. More...
 
void SAI_TransferTerminateSend (I2S_Type *base, sai_handle_t *handle)
 Terminate all SAI send. More...
 
void SAI_TransferTerminateReceive (I2S_Type *base, sai_handle_t *handle)
 Terminate all SAI receive. More...
 
void SAI_TransferTxHandleIRQ (I2S_Type *base, sai_handle_t *handle)
 Tx interrupt handler. More...
 
void SAI_TransferRxHandleIRQ (I2S_Type *base, sai_handle_t *handle)
 Tx interrupt handler. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct sai_config_t
+
+
+ + + + + + + + + + + + + +

Data Fields

+sai_protocol_t protocol
 Audio bus protocol in SAI.
 
+sai_sync_mode_t syncMode
 SAI sync mode, control Tx/Rx clock sync.
 
+sai_bclk_source_t bclkSource
 Bit Clock source.
 
+sai_master_slave_t masterSlave
 Master or slave.
 
+ +
+
+ +
+
+ + + + +
struct sai_transfer_format_t
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

+uint32_t sampleRate_Hz
 Sample rate of audio data.
 
+uint32_t bitWidth
 Data length of audio data, usually 8/16/24/32 bits.
 
+sai_mono_stereo_t stereo
 Mono or stereo.
 
+uint8_t watermark
 Watermark value.
 
+uint8_t channel
 Transfer start channel.
 
+uint8_t channelMask
 enabled channel mask value, reference _sai_channel_mask
 
+uint8_t endChannel
 end channel number
 
+uint8_t channelNums
 Total enabled channel numbers.
 
+sai_protocol_t protocol
 Which audio protocol used.
 
bool isFrameSyncCompact
 True means Frame sync length is configurable according to bitWidth, false means frame sync length is 64 times of bit clock. More...
 
+

Field Documentation

+ +
+
+ + + + +
bool sai_transfer_format_t::isFrameSyncCompact
+
+ +
+
+ +
+
+ +
+
+ + + + +
struct sai_fifo_t
+
+
+ + + + + + + + + + +

Data Fields

+bool fifoContinueOneError
 fifo continues when error occur
 
+sai_fifo_packing_t fifoPacking
 fifo packing mode
 
+uint8_t fifoWatermark
 fifo watermark
 
+ +
+
+ +
+
+ + + + +
struct sai_bit_clock_t
+
+
+ + + + + + + + + + + + + +

Data Fields

+bool bclkSrcSwap
 bit clock source swap
 
bool bclkInputDelay
 bit clock actually used by the transmitter is delayed by the pad output delay, this has effect of decreasing the data input setup time, but increasing the data output valid time . More...
 
+sai_clock_polarity_t bclkPolarity
 bit clock polarity
 
+sai_bclk_source_t bclkSource
 bit Clock source
 
+

Field Documentation

+ +
+
+ + + + +
bool sai_bit_clock_t::bclkInputDelay
+
+ +
+
+ +
+
+ +
+
+ + + + +
struct sai_frame_sync_t
+
+
+ + + + + + + + + + +

Data Fields

+uint8_t frameSyncWidth
 frame sync width in number of bit clocks
 
+bool frameSyncEarly
 TRUE is frame sync assert one bit before the first bit of frame FALSE is frame sync assert with the first bit of the frame.
 
+sai_clock_polarity_t frameSyncPolarity
 frame sync polarity
 
+ +
+
+ +
+
+ + + + +
struct sai_serial_data_t
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

+sai_data_pin_state_t dataMode
 sai data pin state when slots masked or channel disabled
 
+sai_data_order_t dataOrder
 configure whether the LSB or MSB is transmitted first
 
+uint8_t dataWord0Length
 configure the number of bits in the first word in each frame
 
+uint8_t dataWordNLength
 configure the number of bits in the each word in each frame, except the first word
 
+uint8_t dataWordLength
 used to record the data length for dma transfer
 
+uint8_t dataFirstBitShifted
 Configure the bit index for the first bit transmitted for each word in the frame.
 
+uint8_t dataWordNum
 configure the number of words in each frame
 
+uint32_t dataMaskedWord
 configure whether the transmit word is masked
 
+ +
+
+ +
+
+ + + + +
struct sai_transceiver_t
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

+sai_serial_data_t serialData
 serial data configurations
 
+sai_frame_sync_t frameSync
 ws configurations
 
+sai_bit_clock_t bitClock
 bit clock configurations
 
+sai_fifo_t fifo
 fifo configurations
 
+sai_master_slave_t masterSlave
 transceiver is master or slave
 
+sai_sync_mode_t syncMode
 transceiver sync mode
 
+uint8_t startChannel
 Transfer start channel.
 
+uint8_t channelMask
 enabled channel mask value, reference _sai_channel_mask
 
+uint8_t endChannel
 end channel number
 
+uint8_t channelNums
 Total enabled channel numbers.
 
+ +
+
+ +
+
+ + + + +
struct sai_transfer_t
+
+
+ + + + + + + +

Data Fields

uint8_t * data
 Data start address to transfer. More...
 
size_t dataSize
 Transfer size. More...
 
+

Field Documentation

+ +
+
+ + + + +
uint8_t* sai_transfer_t::data
+
+ +
+
+ +
+
+ + + + +
size_t sai_transfer_t::dataSize
+
+ +
+
+ +
+
+ +
+
+ + + + +
struct _sai_handle
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

+I2S_Type * base
 base address
 
+uint32_t state
 Transfer status.
 
+sai_transfer_callback_t callback
 Callback function called at transfer event.
 
+void * userData
 Callback parameter passed to callback function.
 
+uint8_t bitWidth
 Bit width for transfer, 8/16/24/32 bits.
 
+uint8_t channel
 Transfer start channel.
 
+uint8_t channelMask
 enabled channel mask value, refernece _sai_channel_mask
 
+uint8_t endChannel
 end channel number
 
+uint8_t channelNums
 Total enabled channel numbers.
 
+sai_transfer_t saiQueue [SAI_XFER_QUEUE_SIZE]
 Transfer queue storing queued transfer.
 
+size_t transferSize [SAI_XFER_QUEUE_SIZE]
 Data bytes need to transfer.
 
+volatile uint8_t queueUser
 Index for user to queue transfer.
 
+volatile uint8_t queueDriver
 Index for driver to get the transfer data and size.
 
+uint8_t watermark
 Watermark value.
 
+ +
+
+

Macro Definition Documentation

+ +
+
+ + + + +
#define SAI_XFER_QUEUE_SIZE   (4U)
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
anonymous enum
+
+ + + + + + + + +
Enumerator
kStatus_SAI_TxBusy  +

SAI Tx is busy.

+
kStatus_SAI_RxBusy  +

SAI Rx is busy.

+
kStatus_SAI_TxError  +

SAI Tx FIFO error.

+
kStatus_SAI_RxError  +

SAI Rx FIFO error.

+
kStatus_SAI_QueueFull  +

SAI transfer queue is full.

+
kStatus_SAI_TxIdle  +

SAI Tx is idle.

+
kStatus_SAI_RxIdle  +

SAI Rx is idle.

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+ + + + + + + + + +
Enumerator
kSAI_Channel0Mask  +

channel 0 mask value

+
kSAI_Channel1Mask  +

channel 1 mask value

+
kSAI_Channel2Mask  +

channel 2 mask value

+
kSAI_Channel3Mask  +

channel 3 mask value

+
kSAI_Channel4Mask  +

channel 4 mask value

+
kSAI_Channel5Mask  +

channel 5 mask value

+
kSAI_Channel6Mask  +

channel 6 mask value

+
kSAI_Channel7Mask  +

channel 7 mask value

+
+ +
+
+ +
+
+ + + + +
enum sai_protocol_t
+
+ + + + + + +
Enumerator
kSAI_BusLeftJustified  +

Uses left justified format.

+
kSAI_BusRightJustified  +

Uses right justified format.

+
kSAI_BusI2S  +

Uses I2S format.

+
kSAI_BusPCMA  +

Uses I2S PCM A format.

+
kSAI_BusPCMB  +

Uses I2S PCM B format.

+
+ +
+
+ +
+
+ + + + +
enum sai_master_slave_t
+
+ + + + + +
Enumerator
kSAI_Master  +

Master mode include bclk and frame sync.

+
kSAI_Slave  +

Slave mode include bclk and frame sync.

+
kSAI_Bclk_Master_FrameSync_Slave  +

bclk in master mode, frame sync in slave mode

+
kSAI_Bclk_Slave_FrameSync_Master  +

bclk in slave mode, frame sync in master mode

+
+ +
+
+ +
+
+ + + + +
enum sai_mono_stereo_t
+
+ + + + +
Enumerator
kSAI_Stereo  +

Stereo sound.

+
kSAI_MonoRight  +

Only Right channel have sound.

+
kSAI_MonoLeft  +

Only left channel have sound.

+
+ +
+
+ +
+
+ + + + +
enum sai_data_order_t
+
+ + + +
Enumerator
kSAI_DataLSB  +

LSB bit transferred first.

+
kSAI_DataMSB  +

MSB bit transferred first.

+
+ +
+
+ +
+
+ + + + +
enum sai_clock_polarity_t
+
+ + + + + +
Enumerator
kSAI_PolarityActiveHigh  +

Drive outputs on rising edge.

+
kSAI_PolarityActiveLow  +

Drive outputs on falling edge.

+
kSAI_SampleOnFallingEdge  +

Sample inputs on falling edge.

+
kSAI_SampleOnRisingEdge  +

Sample inputs on rising edge.

+
+ +
+
+ +
+
+ + + + +
enum sai_sync_mode_t
+
+ + + +
Enumerator
kSAI_ModeAsync  +

Asynchronous mode.

+
kSAI_ModeSync  +

Synchronous mode (with receiver or transmit)

+
+ +
+
+ +
+
+ + + + +
enum sai_bclk_source_t
+
+ + + + + + + + +
Enumerator
kSAI_BclkSourceBusclk  +

Bit clock using bus clock.

+
kSAI_BclkSourceMclkOption1  +

Bit clock MCLK option 1.

+
kSAI_BclkSourceMclkOption2  +

Bit clock MCLK option2.

+
kSAI_BclkSourceMclkOption3  +

Bit clock MCLK option3.

+
kSAI_BclkSourceMclkDiv  +

Bit clock using master clock divider.

+
kSAI_BclkSourceOtherSai0  +

Bit clock from other SAI device.

+
kSAI_BclkSourceOtherSai1  +

Bit clock from other SAI device.

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+ + + + + + +
Enumerator
kSAI_WordStartInterruptEnable  +

Word start flag, means the first word in a frame detected.

+
kSAI_SyncErrorInterruptEnable  +

Sync error flag, means the sync error is detected.

+
kSAI_FIFOWarningInterruptEnable  +

FIFO warning flag, means the FIFO is empty.

+
kSAI_FIFOErrorInterruptEnable  +

FIFO error flag.

+
kSAI_FIFORequestInterruptEnable  +

FIFO request, means reached watermark.

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+ + + +
Enumerator
kSAI_FIFOWarningDMAEnable  +

FIFO warning caused by the DMA request.

+
kSAI_FIFORequestDMAEnable  +

FIFO request caused by the DMA request.

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+ + + + + + +
Enumerator
kSAI_WordStartFlag  +

Word start flag, means the first word in a frame detected.

+
kSAI_SyncErrorFlag  +

Sync error flag, means the sync error is detected.

+
kSAI_FIFOErrorFlag  +

FIFO error flag.

+
kSAI_FIFORequestFlag  +

FIFO request flag.

+
kSAI_FIFOWarningFlag  +

FIFO warning flag.

+
+ +
+
+ +
+
+ + + + +
enum sai_reset_type_t
+
+ + + + +
Enumerator
kSAI_ResetTypeSoftware  +

Software reset, reset the logic state.

+
kSAI_ResetTypeFIFO  +

FIFO reset, reset the FIFO read and write pointer.

+
kSAI_ResetAll  +

All reset.

+
+ +
+
+ +
+
+ + + + +
enum sai_fifo_packing_t
+
+ + + + +
Enumerator
kSAI_FifoPackingDisabled  +

Packing disabled.

+
kSAI_FifoPacking8bit  +

8 bit packing enabled

+
kSAI_FifoPacking16bit  +

16bit packing enabled

+
+ +
+
+ +
+
+ + + + +
enum sai_sample_rate_t
+
+ + + + + + + + + + + + + +
Enumerator
kSAI_SampleRate8KHz  +

Sample rate 8000 Hz.

+
kSAI_SampleRate11025Hz  +

Sample rate 11025 Hz.

+
kSAI_SampleRate12KHz  +

Sample rate 12000 Hz.

+
kSAI_SampleRate16KHz  +

Sample rate 16000 Hz.

+
kSAI_SampleRate22050Hz  +

Sample rate 22050 Hz.

+
kSAI_SampleRate24KHz  +

Sample rate 24000 Hz.

+
kSAI_SampleRate32KHz  +

Sample rate 32000 Hz.

+
kSAI_SampleRate44100Hz  +

Sample rate 44100 Hz.

+
kSAI_SampleRate48KHz  +

Sample rate 48000 Hz.

+
kSAI_SampleRate96KHz  +

Sample rate 96000 Hz.

+
kSAI_SampleRate192KHz  +

Sample rate 192000 Hz.

+
kSAI_SampleRate384KHz  +

Sample rate 384000 Hz.

+
+ +
+
+ +
+
+ + + + +
enum sai_word_width_t
+
+ + + + + +
Enumerator
kSAI_WordWidth8bits  +

Audio data width 8 bits.

+
kSAI_WordWidth16bits  +

Audio data width 16 bits.

+
kSAI_WordWidth24bits  +

Audio data width 24 bits.

+
kSAI_WordWidth32bits  +

Audio data width 32 bits.

+
+ +
+
+ +
+
+ + + + +
enum sai_data_pin_state_t
+
+ + + +
Enumerator
kSAI_DataPinStateTriState  +

transmit data pins are tri-stated when slots are masked or channels are disabled

+
kSAI_DataPinStateOutputZero  +

transmit data pins are never tri-stated and will output zero when slots are masked or channel disabled

+
+ +
+
+ +
+
+ + + + +
enum sai_transceiver_type_t
+
+ + + +
Enumerator
kSAI_Transmitter  +

sai transmitter

+
kSAI_Receiver  +

sai receiver

+
+ +
+
+ +
+
+ + + + +
enum sai_frame_sync_len_t
+
+ + + +
Enumerator
kSAI_FrameSyncLenOneBitClk  +

1 bit clock frame sync len for DSP mode

+
kSAI_FrameSyncLenPerWordWidth  +

Frame sync length decided by word width.

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TxInit (I2S_Type * base,
const sai_config_t * config 
)
+
+
Deprecated:
Do not use this function. It has been superceded by SAI_Init
+

Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. The configuration structure can be custom filled or set with default values by SAI_TxGetDefaultConfig().

+
Note
This API should be called at the beginning of the application to use the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault because the clock is not enabled.
+
Parameters
+ + + +
baseSAI base pointer
configSAI configuration structure.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_RxInit (I2S_Type * base,
const sai_config_t * config 
)
+
+
Deprecated:
Do not use this function. It has been superceded by SAI_Init
+

Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. The configuration structure can be custom filled or set with default values by SAI_RxGetDefaultConfig().

+
Note
This API should be called at the beginning of the application to use the SAI driver. Otherwise, accessing the SAI module can cause a hard fault because the clock is not enabled.
+
Parameters
+ + + +
baseSAI base pointer
configSAI configuration structure.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SAI_TxGetDefaultConfig (sai_config_t * config)
+
+
Deprecated:
Do not use this function. It has been superceded by SAI_GetClassicI2SConfig, SAI_GetLeftJustifiedConfig , SAI_GetRightJustifiedConfig, SAI_GetDSPConfig, SAI_GetTDMConfig
+

This API initializes the configuration structure for use in SAI_TxConfig(). The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified before calling SAI_TxConfig(). This is an example.

+
sai_config_t config;
+
SAI_TxGetDefaultConfig(&config);
+
Parameters
+ + +
configpointer to master configuration structure
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SAI_RxGetDefaultConfig (sai_config_t * config)
+
+
Deprecated:
Do not use this function. It has been superceded by SAI_GetClassicI2SConfig, SAI_GetLeftJustifiedConfig , SAI_GetRightJustifiedConfig, SAI_GetDSPConfig, SAI_GetTDMConfig
+

This API initializes the configuration structure for use in SAI_RxConfig(). The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified before calling SAI_RxConfig(). This is an example.

+
sai_config_t config;
+
SAI_RxGetDefaultConfig(&config);
+
Parameters
+ + +
configpointer to master configuration structure
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SAI_Init (I2S_Type * base)
+
+

This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock.

+
Parameters
+ + +
baseSAI base pointer.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SAI_Deinit (I2S_Type * base)
+
+

This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit or SAI_RxInit is called to enable the clock.

+
Parameters
+ + +
baseSAI base pointer.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SAI_TxReset (I2S_Type * base)
+
+

This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit.

+
Parameters
+ + +
baseSAI base pointer
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SAI_RxReset (I2S_Type * base)
+
+

This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit.

+
Parameters
+ + +
baseSAI base pointer
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TxEnable (I2S_Type * base,
bool enable 
)
+
+
Parameters
+ + + +
baseSAI base pointer.
enableTrue means enable SAI Tx, false means disable.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_RxEnable (I2S_Type * base,
bool enable 
)
+
+
Parameters
+ + + +
baseSAI base pointer.
enableTrue means enable SAI Rx, false means disable.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void SAI_TxSetBitClockDirection (I2S_Type * base,
sai_master_slave_t masterSlave 
)
+ 		+inlinestatic
+
+

Select bit clock direction, master or slave.

+
Parameters
+ + + +
baseSAI base pointer.
masterSlavereference sai_master_slave_t.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void SAI_RxSetBitClockDirection (I2S_Type * base,
sai_master_slave_t masterSlave 
)
+ 		+inlinestatic
+
+

Select bit clock direction, master or slave.

+
Parameters
+ + + +
baseSAI base pointer.
masterSlavereference sai_master_slave_t.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void SAI_RxSetFrameSyncDirection (I2S_Type * base,
sai_master_slave_t masterSlave 
)
+ 		+inlinestatic
+
+

Select frame sync direction, master or slave.

+
Parameters
+ + + +
baseSAI base pointer.
masterSlavereference sai_master_slave_t.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void SAI_TxSetFrameSyncDirection (I2S_Type * base,
sai_master_slave_t masterSlave 
)
+ 		+inlinestatic
+
+

Select frame sync direction, master or slave.

+
Parameters
+ + + +
baseSAI base pointer.
masterSlavereference sai_master_slave_t.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_TxSetBitClockRate (I2S_Type * base,
uint32_t sourceClockHz,
uint32_t sampleRate,
uint32_t bitWidth,
uint32_t channelNumbers 
)
+
+
Parameters
+ + + + + + +
baseSAI base pointer.
sourceClockHzBit clock source frequency.
sampleRateAudio data sample rate.
bitWidthAudio data bitWidth.
channelNumbersAudio channel numbers.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_RxSetBitClockRate (I2S_Type * base,
uint32_t sourceClockHz,
uint32_t sampleRate,
uint32_t bitWidth,
uint32_t channelNumbers 
)
+
+
Parameters
+ + + + + + +
baseSAI base pointer.
sourceClockHzBit clock source frequency.
sampleRateAudio data sample rate.
bitWidthAudio data bitWidth.
channelNumbersAudio channel numbers.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_TxSetBitclockConfig (I2S_Type * base,
sai_master_slave_t masterSlave,
sai_bit_clock_t * config 
)
+
+
Parameters
+ + + + +
baseSAI base pointer.
masterSlavemaster or slave.
configbit clock other configurations, can be NULL in slave mode.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_RxSetBitclockConfig (I2S_Type * base,
sai_master_slave_t masterSlave,
sai_bit_clock_t * config 
)
+
+
Parameters
+ + + + +
baseSAI base pointer.
masterSlavemaster or slave.
configbit clock other configurations, can be NULL in slave mode.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TxSetFifoConfig (I2S_Type * base,
sai_fifo_t * config 
)
+
+
Parameters
+ + + +
baseSAI base pointer.
configfifo configurations.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_RxSetFifoConfig (I2S_Type * base,
sai_fifo_t * config 
)
+
+
Parameters
+ + + +
baseSAI base pointer.
configfifo configurations.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_TxSetFrameSyncConfig (I2S_Type * base,
sai_master_slave_t masterSlave,
sai_frame_sync_t * config 
)
+
+
Parameters
+ + + + +
baseSAI base pointer.
masterSlavemaster or slave.
configframe sync configurations, can be NULL in slave mode.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_RxSetFrameSyncConfig (I2S_Type * base,
sai_master_slave_t masterSlave,
sai_frame_sync_t * config 
)
+
+
Parameters
+ + + + +
baseSAI base pointer.
masterSlavemaster or slave.
configframe sync configurations, can be NULL in slave mode.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TxSetSerialDataConfig (I2S_Type * base,
sai_serial_data_t * config 
)
+
+
Parameters
+ + + +
baseSAI base pointer.
configserial data configurations.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_RxSetSerialDataConfig (I2S_Type * base,
sai_serial_data_t * config 
)
+
+
Parameters
+ + + +
baseSAI base pointer.
configserial data configurations.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TxSetConfig (I2S_Type * base,
sai_transceiver_t * config 
)
+
+
Parameters
+ + + +
baseSAI base pointer.
configtransmitter configurations.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_RxSetConfig (I2S_Type * base,
sai_transceiver_t * config 
)
+
+
Parameters
+ + + +
baseSAI base pointer.
configreceiver configurations.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_GetClassicI2SConfig (sai_transceiver_t * config,
sai_word_width_t bitWidth,
sai_mono_stereo_t mode,
uint32_t saiChannelMask 
)
+
+
Parameters
+ + + + + +
configtransceiver configurations.
bitWidthaudio data bitWidth.
modeaudio data channel.
saiChannelMaskmask value of the channel to be enable.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_GetLeftJustifiedConfig (sai_transceiver_t * config,
sai_word_width_t bitWidth,
sai_mono_stereo_t mode,
uint32_t saiChannelMask 
)
+
+
Parameters
+ + + + + +
configtransceiver configurations.
bitWidthaudio data bitWidth.
modeaudio data channel.
saiChannelMaskmask value of the channel to be enable.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_GetRightJustifiedConfig (sai_transceiver_t * config,
sai_word_width_t bitWidth,
sai_mono_stereo_t mode,
uint32_t saiChannelMask 
)
+
+
Parameters
+ + + + + +
configtransceiver configurations.
bitWidthaudio data bitWidth.
modeaudio data channel.
saiChannelMaskmask value of the channel to be enable.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_GetTDMConfig (sai_transceiver_t * config,
sai_frame_sync_len_t frameSyncWidth,
sai_word_width_t bitWidth,
uint32_t dataWordNum,
uint32_t saiChannelMask 
)
+
+
Parameters
+ + + + + + +
configtransceiver configurations.
frameSyncWidthlength of frame sync.
bitWidthaudio data word width.
dataWordNumword number in one frame.
saiChannelMaskmask value of the channel to be enable.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_GetDSPConfig (sai_transceiver_t * config,
sai_frame_sync_len_t frameSyncWidth,
sai_word_width_t bitWidth,
sai_mono_stereo_t mode,
uint32_t saiChannelMask 
)
+
+
Note
DSP mode is also called PCM mode which support MODE A and MODE B, DSP/PCM MODE A configuration flow. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:
* SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
+
* config->frameSync.frameSyncEarly = true;
+
* SAI_TxSetConfig(base, config)
+
*
+
+

DSP/PCM MODE B configuration flow for TX. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:

+
* SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
+
* SAI_TxSetConfig(base, config)
+
*
+
Parameters
+ + + + + + +
configtransceiver configurations.
frameSyncWidthlength of frame sync.
bitWidthaudio data bitWidth.
modeaudio data channel.
saiChannelMaskmask value of the channel to enable.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t SAI_TxGetStatusFlag (I2S_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseSAI base pointer
+
+
+
Returns
SAI Tx status flag value. Use the Status Mask to get the status value needed.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void SAI_TxClearStatusFlags (I2S_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseSAI base pointer
maskState mask. It can be a combination of the following source if defined:
    +
  • kSAI_WordStartFlag
    • +
  • kSAI_SyncErrorFlag
    • +
  • kSAI_FIFOErrorFlag
    • +
+
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t SAI_RxGetStatusFlag (I2S_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseSAI base pointer
+
+
+
Returns
SAI Rx status flag value. Use the Status Mask to get the status value needed.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void SAI_RxClearStatusFlags (I2S_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseSAI base pointer
maskState mask. It can be a combination of the following sources if defined.
    +
  • kSAI_WordStartFlag
    • +
  • kSAI_SyncErrorFlag
    • +
  • kSAI_FIFOErrorFlag
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TxSoftwareReset (I2S_Type * base,
sai_reset_type_t type 
)
+
+

FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software reset will not clear any configuration registers like TCR1~TCR5. This function will also clear all the error flags such as FIFO error, sync error etc.

+
Parameters
+ + + +
baseSAI base pointer
typeReset type, FIFO reset or software reset
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_RxSoftwareReset (I2S_Type * base,
sai_reset_type_t type 
)
+
+

FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software reset will not clear any configuration registers like RCR1~RCR5. This function will also clear all the error flags such as FIFO error, sync error etc.

+
Parameters
+ + + +
baseSAI base pointer
typeReset type, FIFO reset or software reset
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TxSetChannelFIFOMask (I2S_Type * base,
uint8_t mask 
)
+
+
Parameters
+ + + +
baseSAI base pointer
maskChannel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, 3 means both channel 0 and channel 1 enabled.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_RxSetChannelFIFOMask (I2S_Type * base,
uint8_t mask 
)
+
+
Parameters
+ + + +
baseSAI base pointer
maskChannel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, 3 means both channel 0 and channel 1 enabled.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TxSetDataOrder (I2S_Type * base,
sai_data_order_t order 
)
+
+
Parameters
+ + + +
baseSAI base pointer
orderData order MSB or LSB
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_RxSetDataOrder (I2S_Type * base,
sai_data_order_t order 
)
+
+
Parameters
+ + + +
baseSAI base pointer
orderData order MSB or LSB
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TxSetBitClockPolarity (I2S_Type * base,
sai_clock_polarity_t polarity 
)
+
+
Parameters
+ + + +
baseSAI base pointer
polarity
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_RxSetBitClockPolarity (I2S_Type * base,
sai_clock_polarity_t polarity 
)
+
+
Parameters
+ + + +
baseSAI base pointer
polarity
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TxSetFrameSyncPolarity (I2S_Type * base,
sai_clock_polarity_t polarity 
)
+
+
Parameters
+ + + +
baseSAI base pointer
polarity
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_RxSetFrameSyncPolarity (I2S_Type * base,
sai_clock_polarity_t polarity 
)
+
+
Parameters
+ + + +
baseSAI base pointer
polarity
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TxSetFIFOPacking (I2S_Type * base,
sai_fifo_packing_t pack 
)
+
+
Parameters
+ + + +
baseSAI base pointer.
packFIFO pack type. It is element of sai_fifo_packing_t.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_RxSetFIFOPacking (I2S_Type * base,
sai_fifo_packing_t pack 
)
+
+
Parameters
+ + + +
baseSAI base pointer.
packFIFO pack type. It is element of sai_fifo_packing_t.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void SAI_TxSetFIFOErrorContinue (I2S_Type * base,
bool isEnabled 
)
+ 		+inlinestatic
+
+

FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature not enabled, SAI will hang and users need to clear FEF flag in TCSR register.

+
Parameters
+ + + +
baseSAI base pointer.
isEnabledIs FIFO error continue enabled, true means enable, false means disable.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void SAI_RxSetFIFOErrorContinue (I2S_Type * base,
bool isEnabled 
)
+ 		+inlinestatic
+
+

FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature not enabled, SAI will hang and users need to clear FEF flag in RCSR register.

+
Parameters
+ + + +
baseSAI base pointer.
isEnabledIs FIFO error continue enabled, true means enable, false means disable.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void SAI_TxEnableInterrupts (I2S_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseSAI base pointer
maskinterrupt source The parameter can be a combination of the following sources if defined.
    +
  • kSAI_WordStartInterruptEnable
    • +
  • kSAI_SyncErrorInterruptEnable
    • +
  • kSAI_FIFOWarningInterruptEnable
    • +
  • kSAI_FIFORequestInterruptEnable
    • +
  • kSAI_FIFOErrorInterruptEnable
    • +
+
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void SAI_RxEnableInterrupts (I2S_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseSAI base pointer
maskinterrupt source The parameter can be a combination of the following sources if defined.
    +
  • kSAI_WordStartInterruptEnable
    • +
  • kSAI_SyncErrorInterruptEnable
    • +
  • kSAI_FIFOWarningInterruptEnable
    • +
  • kSAI_FIFORequestInterruptEnable
    • +
  • kSAI_FIFOErrorInterruptEnable
    • +
+
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void SAI_TxDisableInterrupts (I2S_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseSAI base pointer
maskinterrupt source The parameter can be a combination of the following sources if defined.
    +
  • kSAI_WordStartInterruptEnable
    • +
  • kSAI_SyncErrorInterruptEnable
    • +
  • kSAI_FIFOWarningInterruptEnable
    • +
  • kSAI_FIFORequestInterruptEnable
    • +
  • kSAI_FIFOErrorInterruptEnable
    • +
+
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void SAI_RxDisableInterrupts (I2S_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseSAI base pointer
maskinterrupt source The parameter can be a combination of the following sources if defined.
    +
  • kSAI_WordStartInterruptEnable
    • +
  • kSAI_SyncErrorInterruptEnable
    • +
  • kSAI_FIFOWarningInterruptEnable
    • +
  • kSAI_FIFORequestInterruptEnable
    • +
  • kSAI_FIFOErrorInterruptEnable
    • +
+
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void SAI_TxEnableDMA (I2S_Type * base,
uint32_t mask,
bool enable 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseSAI base pointer
maskDMA source The parameter can be combination of the following sources if defined.
    +
  • kSAI_FIFOWarningDMAEnable
    • +
  • kSAI_FIFORequestDMAEnable
    • +
+
enableTrue means enable DMA, false means disable DMA.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void SAI_RxEnableDMA (I2S_Type * base,
uint32_t mask,
bool enable 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseSAI base pointer
maskDMA source The parameter can be a combination of the following sources if defined.
    +
  • kSAI_FIFOWarningDMAEnable
    • +
  • kSAI_FIFORequestDMAEnable
    • +
+
enableTrue means enable DMA, false means disable DMA.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static uint32_t SAI_TxGetDataRegisterAddress (I2S_Type * base,
uint32_t channel 
)
+ 		+inlinestatic
+
+

This API is used to provide a transfer address for the SAI DMA transfer configuration.

+
Parameters
+ + + +
baseSAI base pointer.
channelWhich data channel used.
+
+
+
Returns
data register address.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static uint32_t SAI_RxGetDataRegisterAddress (I2S_Type * base,
uint32_t channel 
)
+ 		+inlinestatic
+
+

This API is used to provide a transfer address for the SAI DMA transfer configuration.

+
Parameters
+ + + +
baseSAI base pointer.
channelWhich data channel used.
+
+
+
Returns
data register address.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_TxSetFormat (I2S_Type * base,
sai_transfer_format_t * format,
uint32_t mclkSourceClockHz,
uint32_t bclkSourceClockHz 
)
+
+
Deprecated:
Do not use this function. It has been superceded by SAI_TxSetConfig
+

The audio format can be changed at run-time. This function configures the sample rate and audio data format to be transferred.

+
Parameters
+ + + + + +
baseSAI base pointer.
formatPointer to the SAI audio data format structure.
mclkSourceClockHzSAI master clock source frequency in Hz.
bclkSourceClockHzSAI bit clock source frequency in Hz. If the bit clock source is a master clock, this value should equal the masterClockHz.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_RxSetFormat (I2S_Type * base,
sai_transfer_format_t * format,
uint32_t mclkSourceClockHz,
uint32_t bclkSourceClockHz 
)
+
+
Deprecated:
Do not use this function. It has been superceded by SAI_RxSetConfig
+

The audio format can be changed at run-time. This function configures the sample rate and audio data format to be transferred.

+
Parameters
+ + + + + +
baseSAI base pointer.
formatPointer to the SAI audio data format structure.
mclkSourceClockHzSAI master clock source frequency in Hz.
bclkSourceClockHzSAI bit clock source frequency in Hz. If the bit clock source is a master clock, this value should equal the masterClockHz.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_WriteBlocking (I2S_Type * base,
uint32_t channel,
uint32_t bitWidth,
uint8_t * buffer,
uint32_t size 
)
+
+
Note
This function blocks by polling until data is ready to be sent.
+
Parameters
+ + + + + + +
baseSAI base pointer.
channelData channel used.
bitWidthHow many bits in an audio word; usually 8/16/24/32 bits.
bufferPointer to the data to be written.
sizeBytes to be written.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_WriteMultiChannelBlocking (I2S_Type * base,
uint32_t channel,
uint32_t channelMask,
uint32_t bitWidth,
uint8_t * buffer,
uint32_t size 
)
+
+
Note
This function blocks by polling until data is ready to be sent.
+
Parameters
+ + + + + + + +
baseSAI base pointer.
channelData channel used.
channelMaskchannel mask.
bitWidthHow many bits in an audio word; usually 8/16/24/32 bits.
bufferPointer to the data to be written.
sizeBytes to be written.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void SAI_WriteData (I2S_Type * base,
uint32_t channel,
uint32_t data 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
baseSAI base pointer.
channelData channel used.
dataData needs to be written.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_ReadBlocking (I2S_Type * base,
uint32_t channel,
uint32_t bitWidth,
uint8_t * buffer,
uint32_t size 
)
+
+
Note
This function blocks by polling until data is ready to be sent.
+
Parameters
+ + + + + + +
baseSAI base pointer.
channelData channel used.
bitWidthHow many bits in an audio word; usually 8/16/24/32 bits.
bufferPointer to the data to be read.
sizeBytes to be read.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_ReadMultiChannelBlocking (I2S_Type * base,
uint32_t channel,
uint32_t channelMask,
uint32_t bitWidth,
uint8_t * buffer,
uint32_t size 
)
+
+
Note
This function blocks by polling until data is ready to be sent.
+
Parameters
+ + + + + + + +
baseSAI base pointer.
channelData channel used.
channelMaskchannel mask.
bitWidthHow many bits in an audio word; usually 8/16/24/32 bits.
bufferPointer to the data to be read.
sizeBytes to be read.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static uint32_t SAI_ReadData (I2S_Type * base,
uint32_t channel 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseSAI base pointer.
channelData channel used.
+
+
+
Returns
Data in SAI FIFO.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_TransferTxCreateHandle (I2S_Type * base,
sai_handle_t * handle,
sai_transfer_callback_t callback,
void * userData 
)
+
+

This function initializes the Tx handle for the SAI Tx transactional APIs. Call this function once to get the handle initialized.

+
Parameters
+ + + + + +
baseSAI base pointer
handleSAI handle pointer.
callbackPointer to the user callback function.
userDataUser parameter passed to the callback function
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_TransferRxCreateHandle (I2S_Type * base,
sai_handle_t * handle,
sai_transfer_callback_t callback,
void * userData 
)
+
+

This function initializes the Rx handle for the SAI Rx transactional APIs. Call this function once to get the handle initialized.

+
Parameters
+ + + + + +
baseSAI base pointer.
handleSAI handle pointer.
callbackPointer to the user callback function.
userDataUser parameter passed to the callback function.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_TransferTxSetConfig (I2S_Type * base,
sai_handle_t * handle,
sai_transceiver_t * config 
)
+
+

This function initializes the Tx, include bit clock, frame sync, master clock, serial data and fifo configurations.

+
Parameters
+ + + + +
baseSAI base pointer.
handleSAI handle pointer.
configtranmitter configurations.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_TransferRxSetConfig (I2S_Type * base,
sai_handle_t * handle,
sai_transceiver_t * config 
)
+
+

This function initializes the Rx, include bit clock, frame sync, master clock, serial data and fifo configurations.

+
Parameters
+ + + + +
baseSAI base pointer.
handleSAI handle pointer.
configreceiver configurations.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
status_t SAI_TransferTxSetFormat (I2S_Type * base,
sai_handle_t * handle,
sai_transfer_format_t * format,
uint32_t mclkSourceClockHz,
uint32_t bclkSourceClockHz 
)
+
+
Deprecated:
Do not use this function. It has been superceded by SAI_TransferTxSetConfig
+

The audio format can be changed at run-time. This function configures the sample rate and audio data format to be transferred.

+
Parameters
+ + + + + + +
baseSAI base pointer.
handleSAI handle pointer.
formatPointer to the SAI audio data format structure.
mclkSourceClockHzSAI master clock source frequency in Hz.
bclkSourceClockHzSAI bit clock source frequency in Hz. If a bit clock source is a master clock, this value should equal the masterClockHz in format.
+
+
+
Returns
Status of this function. Return value is the status_t.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
status_t SAI_TransferRxSetFormat (I2S_Type * base,
sai_handle_t * handle,
sai_transfer_format_t * format,
uint32_t mclkSourceClockHz,
uint32_t bclkSourceClockHz 
)
+
+
Deprecated:
Do not use this function. It has been superceded by SAI_TransferRxSetConfig
+

The audio format can be changed at run-time. This function configures the sample rate and audio data format to be transferred.

+
Parameters
+ + + + + + +
baseSAI base pointer.
handleSAI handle pointer.
formatPointer to the SAI audio data format structure.
mclkSourceClockHzSAI master clock source frequency in Hz.
bclkSourceClockHzSAI bit clock source frequency in Hz. If a bit clock source is a master clock, this value should equal the masterClockHz in format.
+
+
+
Returns
Status of this function. Return value is one of status_t.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t SAI_TransferSendNonBlocking (I2S_Type * base,
sai_handle_t * handle,
sai_transfer_t * xfer 
)
+
+
Note
This API returns immediately after the transfer initiates. Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer is finished.
+
Parameters
+ + + + +
baseSAI base pointer.
handlePointer to the sai_handle_t structure which stores the transfer state.
xferPointer to the sai_transfer_t structure.
+
+
+
Return values
+ + + + +
kStatus_SuccessSuccessfully started the data receive.
kStatus_SAI_TxBusyPrevious receive still not finished.
kStatus_InvalidArgumentThe input parameter is invalid.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t SAI_TransferReceiveNonBlocking (I2S_Type * base,
sai_handle_t * handle,
sai_transfer_t * xfer 
)
+
+
Note
This API returns immediately after the transfer initiates. Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer is finished.
+
Parameters
+ + + + +
baseSAI base pointer
handlePointer to the sai_handle_t structure which stores the transfer state.
xferPointer to the sai_transfer_t structure.
+
+
+
Return values
+ + + + +
kStatus_SuccessSuccessfully started the data receive.
kStatus_SAI_RxBusyPrevious receive still not finished.
kStatus_InvalidArgumentThe input parameter is invalid.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t SAI_TransferGetSendCount (I2S_Type * base,
sai_handle_t * handle,
size_t * count 
)
+
+
Parameters
+ + + + +
baseSAI base pointer.
handlePointer to the sai_handle_t structure which stores the transfer state.
countBytes count sent.
+
+
+
Return values
+ + + +
kStatus_SuccessSucceed get the transfer count.
kStatus_NoTransferInProgressThere is not a non-blocking transaction currently in progress.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t SAI_TransferGetReceiveCount (I2S_Type * base,
sai_handle_t * handle,
size_t * count 
)
+
+
Parameters
+ + + + +
baseSAI base pointer.
handlePointer to the sai_handle_t structure which stores the transfer state.
countBytes count received.
+
+
+
Return values
+ + + +
kStatus_SuccessSucceed get the transfer count.
kStatus_NoTransferInProgressThere is not a non-blocking transaction currently in progress.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TransferAbortSend (I2S_Type * base,
sai_handle_t * handle 
)
+
+
Note
This API can be called any time when an interrupt non-blocking transfer initiates to abort the transfer early.
+
Parameters
+ + + +
baseSAI base pointer.
handlePointer to the sai_handle_t structure which stores the transfer state.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TransferAbortReceive (I2S_Type * base,
sai_handle_t * handle 
)
+
+
Note
This API can be called when an interrupt non-blocking transfer initiates to abort the transfer early.
+
Parameters
+ + + +
baseSAI base pointer
handlePointer to the sai_handle_t structure which stores the transfer state.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TransferTerminateSend (I2S_Type * base,
sai_handle_t * handle 
)
+
+

This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortSend.

+
Parameters
+ + + +
baseSAI base pointer.
handleSAI eDMA handle pointer.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TransferTerminateReceive (I2S_Type * base,
sai_handle_t * handle 
)
+
+

This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortReceive.

+
Parameters
+ + + +
baseSAI base pointer.
handleSAI eDMA handle pointer.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TransferTxHandleIRQ (I2S_Type * base,
sai_handle_t * handle 
)
+
+
Parameters
+ + + +
baseSAI base pointer.
handlePointer to the sai_handle_t structure.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TransferRxHandleIRQ (I2S_Type * base,
sai_handle_t * handle 
)
+
+
Parameters
+ + + +
baseSAI base pointer.
handlePointer to the sai_handle_t structure.
+
+
+ +
+
+
+
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"a00016.html#gab66ff18cc17137d132a3b5c8accbdb34", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00017.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00017.html new file mode 100644 index 000000000..bda828d0f --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00017.html @@ -0,0 +1,1063 @@ + + + + + + +MCUXpresso SDK API Reference Manual: Serial Manager + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Modules | +Data Structures | +Macros | +Typedefs | +Enumerations | +Functions
+
+
Serial Manager
+
+
+

Overview

+

This chapter describes the programming interface of the serial manager component.

+

The serial manager component provides a series of APIs to operate different serial port types. The port types it supports are UART, USB CDC and SWO.

+ + + + + + +

+Modules

 Serial Port SWO
 
 Serial Port Uart
 
+ + + + + + + +

+Data Structures

struct  serial_manager_config_t
 serial manager config structure More...
 
struct  serial_manager_callback_message_t
 Callback message structure. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SERIAL_MANAGER_NON_BLOCKING_MODE   (0U)
 Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable)
 
+#define SERIAL_PORT_TYPE_UART   (0U)
 Enable or disable uart port (1 - enable, 0 - disable)
 
+#define SERIAL_PORT_TYPE_USBCDC   (0U)
 Enable or disable USB CDC port (1 - enable, 0 - disable)
 
+#define SERIAL_PORT_TYPE_SWO   (0U)
 Enable or disable SWO port (1 - enable, 0 - disable)
 
+#define SERIAL_PORT_TYPE_VIRTUAL   (0U)
 Enable or disable USB CDC virtual port (1 - enable, 0 - disable)
 
+#define SERIAL_PORT_TYPE_RPMSG   (0U)
 Enable or disable rPMSG port (1 - enable, 0 - disable)
 
+#define SERIAL_MANAGER_TASK_HANDLE_TX   (0U)
 Enable or disable SerialManager_Task() handle TX to prevent recursive calling.
 
#define SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE   (1U)
 Set the default delay time in ms used by SerialManager_WriteTimeDelay(). More...
 
#define SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE   (1U)
 Set the default delay time in ms used by SerialManager_ReadTimeDelay(). More...
 
+#define SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY   (0U)
 Enable or disable SerialManager_Task() handle RX data available notify.
 
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE   (4U)
 Set serial manager write handle size.
 
#define SERIAL_MANAGER_USE_COMMON_TASK   (0U)
 SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size. More...
 
#define SERIAL_MANAGER_HANDLE_SIZE   (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
 Macro to determine whether use common task. More...
 
#define SERIAL_MANAGER_HANDLE_DEFINE(name)   uint32_t name[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
 Defines the serial manager handle. More...
 
#define SERIAL_MANAGER_WRITE_HANDLE_DEFINE(name)   uint32_t name[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
 Defines the serial manager write handle. More...
 
#define SERIAL_MANAGER_READ_HANDLE_DEFINE(name)   uint32_t name[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
 Defines the serial manager read handle. More...
 
#define SERIAL_MANAGER_TASK_PRIORITY   (2U)
 Macro to set serial manager task priority. More...
 
#define SERIAL_MANAGER_TASK_STACK_SIZE   (1000U)
 Macro to set serial manager task stack size. More...
 
+ + + + + + + + + + + + + +

+Typedefs

+typedef void * serial_handle_t
 The handle of the serial manager module.
 
+typedef void * serial_write_handle_t
 The write handle of the serial manager module.
 
+typedef void * serial_read_handle_t
 The read handle of the serial manager module.
 
+typedef void(* serial_manager_callback_t )(void *callbackParam, serial_manager_callback_message_t *message, serial_manager_status_t status)
 callback function
 
+ + + + + + + + + + +

+Enumerations

enum  serial_port_type_t {
+  kSerialPort_Uart = 1U, +
+  kSerialPort_UsbCdc, +
+  kSerialPort_Swo, +
+  kSerialPort_Virtual, +
+  kSerialPort_Rpmsg +
+ }
 serial port type More...
 
enum  serial_manager_type_t {
+  kSerialManager_NonBlocking = 0x0U, +
+  kSerialManager_Blocking = 0x8F41U +
+ }
 serial manager type More...
 
enum  serial_manager_status_t {
+  kStatus_SerialManager_Success = kStatus_Success, +
+  kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), +
+  kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), +
+  kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), +
+  kStatus_SerialManager_Canceled, +
+  kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), +
+  kStatus_SerialManager_RingBufferOverflow, +
+  kStatus_SerialManager_NotConnected = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 7) +
+ }
 serial manager error code More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

serial_manager_status_t SerialManager_Init (serial_handle_t serialHandle, const serial_manager_config_t *config)
 Initializes a serial manager module with the serial manager handle and the user configuration structure. More...
 
serial_manager_status_t SerialManager_Deinit (serial_handle_t serialHandle)
 De-initializes the serial manager module instance. More...
 
serial_manager_status_t SerialManager_OpenWriteHandle (serial_handle_t serialHandle, serial_write_handle_t writeHandle)
 Opens a writing handle for the serial manager module. More...
 
serial_manager_status_t SerialManager_CloseWriteHandle (serial_write_handle_t writeHandle)
 Closes a writing handle for the serial manager module. More...
 
serial_manager_status_t SerialManager_OpenReadHandle (serial_handle_t serialHandle, serial_read_handle_t readHandle)
 Opens a reading handle for the serial manager module. More...
 
serial_manager_status_t SerialManager_CloseReadHandle (serial_read_handle_t readHandle)
 Closes a reading for the serial manager module. More...
 
serial_manager_status_t SerialManager_WriteBlocking (serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)
 Transmits data with the blocking mode. More...
 
serial_manager_status_t SerialManager_ReadBlocking (serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
 Reads data with the blocking mode. More...
 
serial_manager_status_t SerialManager_EnterLowpower (serial_handle_t serialHandle)
 Prepares to enter low power consumption. More...
 
serial_manager_status_t SerialManager_ExitLowpower (serial_handle_t serialHandle)
 Restores from low power consumption. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct serial_manager_config_t
+
+
+ + + + + + + + + + + + + + + + +

Data Fields

uint8_t * ringBuffer
 Ring buffer address, it is used to buffer data received by the hardware. More...
 
+uint32_t ringBufferSize
 The size of the ring buffer.
 
+serial_port_type_t type
 Serial port type.
 
+serial_manager_type_t blockType
 Serial manager port type.
 
+void * portConfig
 Serial port configuration.
 
+

Field Documentation

+ +
+
+ + + + +
uint8_t* serial_manager_config_t::ringBuffer
+
+

Besides, the memory space cannot be free during the lifetime of the serial manager module.

+ +
+
+ +
+
+ +
+
+ + + + +
struct serial_manager_callback_message_t
+
+
+ + + + + + + +

Data Fields

+uint8_t * buffer
 Transferred buffer.
 
+uint32_t length
 Transferred data length.
 
+ +
+
+

Macro Definition Documentation

+ +
+
+ + + + +
#define SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE   (1U)
+
+ +
+
+ +
+
+ + + + +
#define SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE   (1U)
+
+ +
+
+ +
+
+ + + + +
#define SERIAL_MANAGER_USE_COMMON_TASK   (0U)
+
+

Macro to determine whether use common task.

+ +
+
+ +
+
+ + + + +
#define SERIAL_MANAGER_HANDLE_SIZE   (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
+
+

Definition of serial manager handle size.

+ +
+
+ +
+
+ + + + + + + + +
#define SERIAL_MANAGER_HANDLE_DEFINE( name)   uint32_t name[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+
+

This macro is used to define a 4 byte aligned serial manager handle. Then use "(serial_handle_t)name" to get the serial manager handle.

+

The macro should be global and could be optional. You could also define serial manager handle by yourself.

+

This is an example,

+
* SERIAL_MANAGER_HANDLE_DEFINE(serialManagerHandle);
+
*
+
Parameters
+ + +
nameThe name string of the serial manager handle.
+
+
+ +
+
+ +
+
+ + + + + + + + +
#define SERIAL_MANAGER_WRITE_HANDLE_DEFINE( name)   uint32_t name[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+
+

This macro is used to define a 4 byte aligned serial manager write handle. Then use "(serial_write_handle_t)name" to get the serial manager write handle.

+

The macro should be global and could be optional. You could also define serial manager write handle by yourself.

+

This is an example,

+
* SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialManagerwriteHandle);
+
*
+
Parameters
+ + +
nameThe name string of the serial manager write handle.
+
+
+ +
+
+ +
+
+ + + + + + + + +
#define SERIAL_MANAGER_READ_HANDLE_DEFINE( name)   uint32_t name[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+
+

This macro is used to define a 4 byte aligned serial manager read handle. Then use "(serial_read_handle_t)name" to get the serial manager read handle.

+

The macro should be global and could be optional. You could also define serial manager read handle by yourself.

+

This is an example,

+
* SERIAL_MANAGER_READ_HANDLE_DEFINE(serialManagerReadHandle);
+
*
+
Parameters
+ + +
nameThe name string of the serial manager read handle.
+
+
+ +
+
+ +
+
+ + + + +
#define SERIAL_MANAGER_TASK_PRIORITY   (2U)
+
+ +
+
+ +
+
+ + + + +
#define SERIAL_MANAGER_TASK_STACK_SIZE   (1000U)
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum serial_port_type_t
+
+ + + + + + +
Enumerator
kSerialPort_Uart  +

Serial port UART.

+
kSerialPort_UsbCdc  +

Serial port USB CDC.

+
kSerialPort_Swo  +

Serial port SWO.

+
kSerialPort_Virtual  +

Serial port Virtual.

+
kSerialPort_Rpmsg  +

Serial port RPMSG.

+
+ +
+
+ +
+
+ + + + +
enum serial_manager_type_t
+
+ + + +
Enumerator
kSerialManager_NonBlocking  +

None blocking handle.

+
kSerialManager_Blocking  +

Blocking handle.

+
+ +
+
+ +
+
+ + + + +
enum serial_manager_status_t
+
+ + + + + + + + + +
Enumerator
kStatus_SerialManager_Success  +

Success.

+
kStatus_SerialManager_Error  +

Failed.

+
kStatus_SerialManager_Busy  +

Busy.

+
kStatus_SerialManager_Notify  +

Ring buffer is not empty.

+
kStatus_SerialManager_Canceled  +

the non-blocking request is canceled

+
kStatus_SerialManager_HandleConflict  +

The handle is opened.

+
kStatus_SerialManager_RingBufferOverflow  +

The ring buffer is overflowed.

+
kStatus_SerialManager_NotConnected  +

The host is not connected.

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
serial_manager_status_t SerialManager_Init (serial_handle_t serialHandle,
const serial_manager_config_t * config 
)
+
+

This function configures the Serial Manager module with user-defined settings. The user can configure the configuration structure. The parameter serialHandle is a pointer to point to a memory space of size SERIAL_MANAGER_HANDLE_SIZE allocated by the caller. The Serial Manager module supports three types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc), USB CDC and swo. Please refer to serial_port_type_t for serial port setting. These three types can be set by using serial_manager_config_t.

+

Example below shows how to use this API to configure the Serial Manager. For UART,

+
* #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
+
* static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle);
+
* static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
+
*
+
* serial_manager_config_t config;
+
* serial_port_uart_config_t uartConfig;
+
* config.type = kSerialPort_Uart;
+
* config.ringBuffer = &s_ringBuffer[0];
+
* config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
+
* uartConfig.instance = 0;
+
* uartConfig.clockRate = 24000000;
+
* uartConfig.baudRate = 115200;
+
* uartConfig.parityMode = kSerialManager_UartParityDisabled;
+
* uartConfig.stopBitCount = kSerialManager_UartOneStopBit;
+
* uartConfig.enableRx = 1;
+
* uartConfig.enableTx = 1;
+
* uartConfig.enableRxRTS = 0;
+
* uartConfig.enableTxCTS = 0;
+
* config.portConfig = &uartConfig;
+
* SerialManager_Init((serial_handle_t)s_serialHandle, &config);
+
*
+

For USB CDC,

+
* #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
+
* static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle);
+
* static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
+
*
+
* serial_manager_config_t config;
+
* serial_port_usb_cdc_config_t usbCdcConfig;
+
* config.type = kSerialPort_UsbCdc;
+
* config.ringBuffer = &s_ringBuffer[0];
+
* config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
+
* usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;
+
* config.portConfig = &usbCdcConfig;
+
* SerialManager_Init((serial_handle_t)s_serialHandle, &config);
+
*
+
Parameters
+ + + +
serialHandlePointer to point to a memory space of size SERIAL_MANAGER_HANDLE_SIZE allocated by the caller. The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. You can define the handle in the following two ways: SERIAL_MANAGER_HANDLE_DEFINE(serialHandle); or uint32_t serialHandle[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
configPointer to user-defined configuration structure.
+
+
+
Return values
+ + + +
kStatus_SerialManager_ErrorAn error occurred.
kStatus_SerialManager_SuccessThe Serial Manager module initialization succeed.
+
+
+ +
+
+ +
+
+ + + + + + + + +
serial_manager_status_t SerialManager_Deinit (serial_handle_t serialHandle)
+
+

This function de-initializes the serial manager module instance. If the opened writing or reading handle is not closed, the function will return kStatus_SerialManager_Busy.

+
Parameters
+ + +
serialHandleThe serial manager module handle pointer.
+
+
+
Return values
+ + + +
kStatus_SerialManager_SuccessThe serial manager de-initialization succeed.
kStatus_SerialManager_BusyOpened reading or writing handle is not closed.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
serial_manager_status_t SerialManager_OpenWriteHandle (serial_handle_t serialHandle,
serial_write_handle_t writeHandle 
)
+
+

This function Opens a writing handle for the serial manager module. If the serial manager needs to be used in different tasks, the task should open a dedicated write handle for itself by calling SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing handle at the same time, multiple writing handles need to be opened when the multiple transmission is needed for a task.

+
Parameters
+ + + +
serialHandleThe serial manager module handle pointer. The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
writeHandleThe serial manager module writing handle pointer. The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. You can define the handle in the following two ways: SERIAL_MANAGER_WRITE_HANDLE_DEFINE(writeHandle); or uint32_t writeHandle[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+
+
+
Return values
+ + + + +
kStatus_SerialManager_ErrorAn error occurred.
kStatus_SerialManager_HandleConflictThe writing handle was opened.
kStatus_SerialManager_SuccessThe writing handle is opened.
+
+
+

Example below shows how to use this API to write data. For task 1,

+
* static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle1);
+
* static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n";
+
* SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle1);
+
* SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle1,
+
* Task1_SerialManagerTxCallback,
+
* s_serialWriteHandle1);
+
* SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle1,
+
* s_nonBlockingWelcome1,
+
* sizeof(s_nonBlockingWelcome1) - 1U);
+
*
+

For task 2,

+
* static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle2);
+
* static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n";
+
* SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle2);
+
* SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle2,
+
* Task2_SerialManagerTxCallback,
+
* s_serialWriteHandle2);
+
* SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle2,
+
* s_nonBlockingWelcome2,
+
* sizeof(s_nonBlockingWelcome2) - 1U);
+
*
+
+
+
+ +
+
+ + + + + + + + +
serial_manager_status_t SerialManager_CloseWriteHandle (serial_write_handle_t writeHandle)
+
+

This function Closes a writing handle for the serial manager module.

+
Parameters
+ + +
writeHandleThe serial manager module writing handle pointer.
+
+
+
Return values
+ + +
kStatus_SerialManager_SuccessThe writing handle is closed.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
serial_manager_status_t SerialManager_OpenReadHandle (serial_handle_t serialHandle,
serial_read_handle_t readHandle 
)
+
+

This function Opens a reading handle for the serial manager module. The reading handle can not be opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when the previous reading handle is not closed. And there can only be one buffer for receiving for the reading handle at the same time.

+
Parameters
+ + + +
serialHandleThe serial manager module handle pointer. The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
readHandleThe serial manager module reading handle pointer. The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. You can define the handle in the following two ways: SERIAL_MANAGER_READ_HANDLE_DEFINE(readHandle); or uint32_t readHandle[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+
+
+
Return values
+ + + + +
kStatus_SerialManager_ErrorAn error occurred.
kStatus_SerialManager_SuccessThe reading handle is opened.
kStatus_SerialManager_BusyPrevious reading handle is not closed.
+
+
+

Example below shows how to use this API to read data.

+
* static SERIAL_MANAGER_READ_HANDLE_DEFINE(s_serialReadHandle);
+
* SerialManager_OpenReadHandle((serial_handle_t)serialHandle, (serial_read_handle_t)s_serialReadHandle);
+
* static uint8_t s_nonBlockingBuffer[64];
+
* SerialManager_InstallRxCallback((serial_read_handle_t)s_serialReadHandle,
+
* APP_SerialManagerRxCallback,
+
* s_serialReadHandle);
+
* SerialManager_ReadNonBlocking((serial_read_handle_t)s_serialReadHandle,
+
* s_nonBlockingBuffer,
+
* sizeof(s_nonBlockingBuffer));
+
*
+
+
+
+ +
+
+ + + + + + + + +
serial_manager_status_t SerialManager_CloseReadHandle (serial_read_handle_t readHandle)
+
+

This function Closes a reading for the serial manager module.

+
Parameters
+ + +
readHandleThe serial manager module reading handle pointer.
+
+
+
Return values
+ + +
kStatus_SerialManager_SuccessThe reading handle is closed.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
serial_manager_status_t SerialManager_WriteBlocking (serial_write_handle_t writeHandle,
uint8_t * buffer,
uint32_t length 
)
+
+

This is a blocking function, which polls the sending queue, waits for the sending queue to be empty. This function sends data using an interrupt method. The interrupt of the hardware could not be disabled. And There can only one buffer for transmission for the writing handle at the same time.

+
Note
The function SerialManager_WriteBlocking and the function SerialManager_WriteNonBlocking cannot be used at the same time. And, the function SerialManager_CancelWriting cannot be used to abort the transmission of this function.
+
Parameters
+ + + + +
writeHandleThe serial manager module handle pointer.
bufferStart address of the data to write.
lengthLength of the data to write.
+
+
+
Return values
+ + + + +
kStatus_SerialManager_SuccessSuccessfully sent all data.
kStatus_SerialManager_BusyPrevious transmission still not finished; data not all sent yet.
kStatus_SerialManager_ErrorAn error occurred.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
serial_manager_status_t SerialManager_ReadBlocking (serial_read_handle_t readHandle,
uint8_t * buffer,
uint32_t length 
)
+
+

This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full. This function receives data using an interrupt method. The interrupt of the hardware could not be disabled. And There can only one buffer for receiving for the reading handle at the same time.

+
Note
The function SerialManager_ReadBlocking and the function SerialManager_ReadNonBlocking cannot be used at the same time. And, the function SerialManager_CancelReading cannot be used to abort the transmission of this function.
+
Parameters
+ + + + +
readHandleThe serial manager module handle pointer.
bufferStart address of the data to store the received data.
lengthThe length of the data to be received.
+
+
+
Return values
+ + + + +
kStatus_SerialManager_SuccessSuccessfully received all data.
kStatus_SerialManager_BusyPrevious transmission still not finished; data not all received yet.
kStatus_SerialManager_ErrorAn error occurred.
+
+
+ +
+
+ +
+
+ + + + + + + + +
serial_manager_status_t SerialManager_EnterLowpower (serial_handle_t serialHandle)
+
+

This function is used to prepare to enter low power consumption.

+
Parameters
+ + +
serialHandleThe serial manager module handle pointer.
+
+
+
Return values
+ + +
kStatus_SerialManager_SuccessSuccessful operation.
+
+
+ +
+
+ +
+
+ + + + + + + + +
serial_manager_status_t SerialManager_ExitLowpower (serial_handle_t serialHandle)
+
+

This function is used to restore from low power consumption.

+
Parameters
+ + +
serialHandleThe serial manager module handle pointer.
+
+
+
Return values
+ + +
kStatus_SerialManager_SuccessSuccessful operation.
+
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00017.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00017.js new file mode 100644 index 000000000..6884b9777 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00017.js @@ -0,0 +1,69 @@ +var a00017 = +[ + [ "Serial Port SWO", "a00018.html", "a00018" ], + [ "Serial Port Uart", "a00108.html", "a00108" ], + [ "serial_manager_config_t", "a00017.html#a00153", [ + [ "ringBuffer", "a00017.html#a73403169ff2d3c8d8897059435fe7e01", null ], + [ "ringBufferSize", "a00017.html#a3cdd8d8501bb64e720345207310de89b", null ], + [ "type", "a00017.html#a19422220843683406b8487dd40fc2cee", null ], + [ "blockType", "a00017.html#ae1f413cf0928c0efdf89ce584adf8007", null ], + [ "portConfig", "a00017.html#ac91431f403f82ce50784274deab7e640", null ] + ] ], + [ "serial_manager_callback_message_t", "a00017.html#a00152", [ + [ "buffer", "a00017.html#a80694c056b447b821f7e146122040e0f", null ], + [ "length", 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"a00017.html#ggae9a330e1f3a81509399832c7b2c2872fa9f087536c7a9930159682ed03d8d71ea", null ], + [ "kStatus_SerialManager_RingBufferOverflow", "a00017.html#ggae9a330e1f3a81509399832c7b2c2872fa41631953d2191b631fbe8443bfa856c8", null ], + [ "kStatus_SerialManager_NotConnected", "a00017.html#ggae9a330e1f3a81509399832c7b2c2872fa1e09ebaf03a4d8599170987750b17ce6", null ] + ] ], + [ "SerialManager_Init", "a00017.html#gac9ad820108a6713516ff44ef109fadf4", null ], + [ "SerialManager_Deinit", "a00017.html#ga467c8a817003eacd48f86aaef1ce8306", null ], + [ "SerialManager_OpenWriteHandle", "a00017.html#ga3d26249a8331e6ca17e9c60838b56d20", null ], + [ "SerialManager_CloseWriteHandle", "a00017.html#gadb8df1d54da32e6de17680264ca4106a", null ], + [ "SerialManager_OpenReadHandle", "a00017.html#ga66915bf8f50a417620ef94951d1df4b8", null ], + [ "SerialManager_CloseReadHandle", "a00017.html#ga09c8831eb6ca6e544881dcbf18dcb4a7", null ], + [ "SerialManager_WriteBlocking", "a00017.html#ga3fab1d6bffd89459be9f23d40874248e", null ], + [ "SerialManager_ReadBlocking", "a00017.html#ga03b1bb5c3dbaa5ea2f0a6e7003f0b4eb", null ], + [ "SerialManager_EnterLowpower", "a00017.html#ga32cdccd6df5d87f17037f34cf9f1e416", null ], + [ "SerialManager_ExitLowpower", "a00017.html#gaef5c404d43871f6d8f761b27dbf183fa", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00018.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00018.html new file mode 100644 index 000000000..da457fed6 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00018.html @@ -0,0 +1,199 @@ + + + + + + +MCUXpresso SDK API Reference Manual: Serial Port SWO + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Macros | +Enumerations
+
+
Serial Port SWO
Serial Manager
+
+
+

Overview

+ + + + + +

+Data Structures

struct  serial_port_swo_config_t
 serial port swo config struct More...
 
+ + + + +

+Macros

+#define SERIAL_PORT_SWO_HANDLE_SIZE   (12U)
 serial port swo handle size
 
+ + + + +

+Enumerations

enum  serial_port_swo_protocol_t {
+  kSerialManager_SwoProtocolManchester = 1U, +
+  kSerialManager_SwoProtocolNrz = 2U +
+ }
 serial port swo protocol More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct serial_port_swo_config_t
+
+
+ + + + + + + + + + + + + +

Data Fields

+uint32_t clockRate
 clock rate
 
+uint32_t baudRate
 baud rate
 
+uint32_t port
 Port used to transfer data.
 
+serial_port_swo_protocol_t protocol
 SWO protocol.
 
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum serial_port_swo_protocol_t
+
+ + + +
Enumerator
kSerialManager_SwoProtocolManchester  +

SWO Manchester protocol.

+
kSerialManager_SwoProtocolNrz  +

SWO UART/NRZ protocol.

+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00018.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00018.js new file mode 100644 index 000000000..80d653fc1 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00018.js @@ -0,0 +1,14 @@ +var a00018 = +[ + [ "serial_port_swo_config_t", "a00018.html#a00154", [ + [ "clockRate", "a00018.html#a515e2f5ca8778fd65e10a0ac7f77d309", null ], + [ "baudRate", "a00018.html#af06ab1ceb2156bba95ee5b125ef77e40", null ], + [ "port", "a00018.html#aeab85500212c4b7945515d3acdf24aee", null ], + [ "protocol", "a00018.html#a1fee1b1db63edc021f9b1d2e5808ecc0", null ] + ] ], + [ "SERIAL_PORT_SWO_HANDLE_SIZE", "a00018.html#ga65f815f28e5af3d42712ebefdd8662dc", null ], + [ "serial_port_swo_protocol_t", "a00018.html#gab72244db50e88efd6d079d157558932d", [ + [ "kSerialManager_SwoProtocolManchester", "a00018.html#ggab72244db50e88efd6d079d157558932da57feeffbb98d786af19111f49bd6d733", null ], + [ "kSerialManager_SwoProtocolNrz", "a00018.html#ggab72244db50e88efd6d079d157558932da1178f82728f1b7f27f28af46f8550d95", null ] + ] ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00019.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00019.html new file mode 100644 index 000000000..4f36b6d12 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00019.html @@ -0,0 +1,1122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: TMU: Thermal Management Unit Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Macros | +Enumerations | +Functions
+
+
TMU: Thermal Management Unit Driver
+
+
+

Overview

+

The MCUXpresso SDK provides a peripheral driver for the thermal management unit (TMU) module of MCUXpresso SDK devices.

+

+Typical use case

+

+Monitor and report Configuration

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/tmu

+ + + + + + + + + + + +

+Data Structures

struct  tmu_thresold_config_t
 configuration for TMU thresold. More...
 
struct  tmu_interrupt_status_t
 TMU interrupt status. More...
 
struct  tmu_config_t
 Configuration for TMU module. More...
 
+ + + + +

+Macros

#define FSL_TMU_DRIVER_VERSION   (MAKE_VERSION(2, 0, 3))
 TMU driver version. More...
 
+ + + + + + + + + + + + + +

+Enumerations

enum  _tmu_interrupt_enable {
+  kTMU_ImmediateTemperatureInterruptEnable, +
+  kTMU_AverageTemperatureInterruptEnable, +
+  kTMU_AverageTemperatureCriticalInterruptEnable +
+ }
 TMU interrupt enable. More...
 
enum  _tmu_interrupt_status_flags {
+  kTMU_ImmediateTemperatureStatusFlags = TMU_TIDR_ITTE_MASK, +
+  kTMU_AverageTemperatureStatusFlags = TMU_TIDR_ATTE_MASK, +
+  kTMU_AverageTemperatureCriticalStatusFlags +
+ }
 TMU interrupt status flags. More...
 
enum  _tmu_status_flags {
+  kTMU_IntervalExceededStatusFlags = TMU_TSR_MIE_MASK, +
+  kTMU_OutOfLowRangeStatusFlags = TMU_TSR_ORL_MASK, +
+  kTMU_OutOfHighRangeStatusFlags +
+ }
 TMU status flags. More...
 
enum  tmu_average_low_pass_filter_t {
+  kTMU_AverageLowPassFilter1_0 = 0U, +
+  kTMU_AverageLowPassFilter0_5 = 1U, +
+  kTMU_AverageLowPassFilter0_25 = 2U, +
+  kTMU_AverageLowPassFilter0_125 = 3U +
+ }
 Average low pass filter setting. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void TMU_Init (TMU_Type *base, const tmu_config_t *config)
 Enable the access to TMU registers and Initialize TMU module. More...
 
void TMU_Deinit (TMU_Type *base)
 De-initialize TMU module and Disable the access to DCDC registers. More...
 
void TMU_GetDefaultConfig (tmu_config_t *config)
 Gets the default configuration for TMU. More...
 
static void TMU_Enable (TMU_Type *base, bool enable)
 Enable/Disable the TMU module. More...
 
static void TMU_EnableInterrupts (TMU_Type *base, uint32_t mask)
 Enable the TMU interrupts. More...
 
static void TMU_DisableInterrupts (TMU_Type *base, uint32_t mask)
 Disable the TMU interrupts. More...
 
void TMU_GetInterruptStatusFlags (TMU_Type *base, tmu_interrupt_status_t *status)
 Get interrupt status flags. More...
 
void TMU_ClearInterruptStatusFlags (TMU_Type *base, uint32_t mask)
 Clear interrupt status flags and corresponding interrupt critical site capture register. More...
 
static uint32_t TMU_GetStatusFlags (TMU_Type *base)
 Get TMU status flags. More...
 
status_t TMU_GetHighestTemperature (TMU_Type *base, uint32_t *temperature)
 Get the highest temperature reached for any enabled monitored site within the temperature sensor range. More...
 
status_t TMU_GetLowestTemperature (TMU_Type *base, uint32_t *temperature)
 Get the lowest temperature reached for any enabled monitored site within the temperature sensor range. More...
 
status_t TMU_GetImmediateTemperature (TMU_Type *base, uint32_t siteIndex, uint32_t *temperature)
 Get the last immediate temperature at site n. More...
 
status_t TMU_GetAverageTemperature (TMU_Type *base, uint32_t siteIndex, uint32_t *temperature)
 Get the last average temperature at site n. More...
 
void TMU_SetHighTemperatureThresold (TMU_Type *base, const tmu_thresold_config_t *config)
 Configure the high temperature thresold value and enable/disable relevant thresold. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct tmu_thresold_config_t
+
+
+ + + + + + + + + + + + + + + + + + + +

Data Fields

bool immediateThresoldEnable
 Enable high temperature immediate threshold. More...
 
bool AverageThresoldEnable
 Enable high temperature average threshold. More...
 
bool AverageCriticalThresoldEnable
 Enable high temperature average critical threshold. More...
 
uint8_t immediateThresoldValue
 Range:0U-125U. More...
 
uint8_t averageThresoldValue
 Range:0U-125U. More...
 
uint8_t averageCriticalThresoldValue
 Range:0U-125U. More...
 
+

Field Documentation

+ +
+
+ + + + +
bool tmu_thresold_config_t::immediateThresoldEnable
+
+ +
+
+ +
+
+ + + + +
bool tmu_thresold_config_t::AverageThresoldEnable
+
+ +
+
+ +
+
+ + + + +
bool tmu_thresold_config_t::AverageCriticalThresoldEnable
+
+ +
+
+ +
+
+ + + + +
uint8_t tmu_thresold_config_t::immediateThresoldValue
+
+

Valid when corresponding thresold is enabled. High temperature immediate threshold value. Determines the current upper temperature threshold, for anyenabled monitored site.

+ +
+
+ +
+
+ + + + +
uint8_t tmu_thresold_config_t::averageThresoldValue
+
+

Valid when corresponding thresold is enabled. High temperature average threshold value. Determines the average upper temperature threshold, for any enabled monitored site.

+ +
+
+ +
+
+ + + + +
uint8_t tmu_thresold_config_t::averageCriticalThresoldValue
+
+

Valid when corresponding thresold is enabled. High temperature average critical threshold value. Determines the average upper critical temperature threshold, for any enabled monitored site.

+ +
+
+ +
+
+ +
+
+ + + + +
struct tmu_interrupt_status_t
+
+
+ + + + + + + + + + + + + +

Data Fields

uint32_t interruptDetectMask
 The mask of interrupt status flags. More...
 
uint16_t immediateInterruptsSiteMask
 The mask of the temperature sensor site associated with a detected ITTE event. More...
 
uint16_t AverageInterruptsSiteMask
 The mask of the temperature sensor site associated with a detected ATTE event. More...
 
uint16_t AverageCriticalInterruptsSiteMask
 The mask of the temperature sensor site associated with a detected ATCTE event. More...
 
+

Field Documentation

+ +
+
+ + + + +
uint32_t tmu_interrupt_status_t::interruptDetectMask
+
+

Refer to "_tmu_interrupt_status_flags" enumeration.

+ +
+
+ +
+
+ + + + +
uint16_t tmu_interrupt_status_t::immediateInterruptsSiteMask
+
+

Please refer to "_tmu_monitor_site" enumeration.

+ +
+
+ +
+
+ + + + +
uint16_t tmu_interrupt_status_t::AverageInterruptsSiteMask
+
+

Please refer to "_tmu_monitor_site" enumeration.

+ +
+
+ +
+
+ + + + +
uint16_t tmu_interrupt_status_t::AverageCriticalInterruptsSiteMask
+
+

Please refer to "_tmu_monitor_site" enumeration.

+ +
+
+ +
+
+ +
+
+ + + + +
struct tmu_config_t
+
+
+ + + + + + + + + + +

Data Fields

uint8_t monitorInterval
 Temperature monitoring interval in seconds. More...
 
uint16_t monitorSiteSelection
 By setting the select bit for a temperature sensor site, it is enabled and included in all monitoring functions. More...
 
tmu_average_low_pass_filter_t averageLPF
 The average temperature is calculated as: ALPF x Current_Temp + (1 - ALPF) x Average_Temp. More...
 
+

Field Documentation

+ +
+
+ + + + +
uint8_t tmu_config_t::monitorInterval
+
+

Please refer to specific table in RM.

+ +
+
+ +
+
+ + + + +
uint16_t tmu_config_t::monitorSiteSelection
+
+

If no site is selected, site 0 is monitored by default. Refer to "_tmu_monitor_site" enumeration. Please look up relevant table in reference manual.

+ +
+
+ +
+
+ + + + +
tmu_average_low_pass_filter_t tmu_config_t::averageLPF
+
+

For proper operation, this field should only change when monitoring is disabled.

+ +
+
+ +
+
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_TMU_DRIVER_VERSION   (MAKE_VERSION(2, 0, 3))
+
+

Version 2.0.3.

+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum _tmu_interrupt_enable
+
+ + + + +
Enumerator
kTMU_ImmediateTemperatureInterruptEnable  +

Immediate temperature threshold exceeded interrupt enable.

+
kTMU_AverageTemperatureInterruptEnable  +

Average temperature threshold exceeded interrupt enable.

+
kTMU_AverageTemperatureCriticalInterruptEnable  +

Average temperature critical threshold exceeded interrupt enable.

+

>

+
+ +
+
+ +
+
+ + + + +
enum _tmu_interrupt_status_flags
+
+ + + + +
Enumerator
kTMU_ImmediateTemperatureStatusFlags  +

Immediate temperature threshold exceeded(ITTE).

+
kTMU_AverageTemperatureStatusFlags  +

Average temperature threshold exceeded(ATTE).

+
kTMU_AverageTemperatureCriticalStatusFlags  +

Average temperature critical threshold exceeded.

+

(ATCTE)

+
+ +
+
+ +
+
+ + + + +
enum _tmu_status_flags
+
+ + + + +
Enumerator
kTMU_IntervalExceededStatusFlags  +

Monitoring interval exceeded.

+

The time required to perform measurement of all monitored sites has exceeded the monitoring interval as defined by TMTMIR.

+
kTMU_OutOfLowRangeStatusFlags  +

Out-of-range low temperature measurement detected.

+

A temperature sensor detected a temperature reading below the lowest measurable temperature of 0 °C.

+
kTMU_OutOfHighRangeStatusFlags  +

Out-of-range high temperature measurement detected.

+

A temperature sensor detected a temperature reading above the highest measurable temperature of 125 °C.

+
+ +
+
+ +
+
+ + + + +
enum tmu_average_low_pass_filter_t
+
+ + + + + +
Enumerator
kTMU_AverageLowPassFilter1_0  +

Average low pass filter = 1.

+
kTMU_AverageLowPassFilter0_5  +

Average low pass filter = 0.5.

+
kTMU_AverageLowPassFilter0_25  +

Average low pass filter = 0.25.

+
kTMU_AverageLowPassFilter0_125  +

Average low pass filter = 0.125.

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void TMU_Init (TMU_Type * base,
const tmu_config_t * config 
)
+
+
Parameters
+ + + +
baseTMU peripheral base address.
configPointer to configuration structure. Refer to "tmu_config_t" structure.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void TMU_Deinit (TMU_Type * base)
+
+
Parameters
+ + +
baseTMU peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void TMU_GetDefaultConfig (tmu_config_t * config)
+
+

This function initializes the user configuration structure to default value. The default value are:

+

Example:

+
config->monitorInterval = 0U;
+
config->monitorSiteSelection = 0U;
+
config->averageLPF = kTMU_AverageLowPassFilter1_0;
+
Parameters
+ + +
configPointer to TMU configuration structure.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void TMU_Enable (TMU_Type * base,
bool enable 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseTMU peripheral base address.
enableSwitcher to enable/disable TMU.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void TMU_EnableInterrupts (TMU_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseTMU peripheral base address.
maskThe interrupt mask. Refer to "_tmu_interrupt_enable" enumeration.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void TMU_DisableInterrupts (TMU_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseTMU peripheral base address.
maskThe interrupt mask. Refer to "_tmu_interrupt_enable" enumeration.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TMU_GetInterruptStatusFlags (TMU_Type * base,
tmu_interrupt_status_t * status 
)
+
+
Parameters
+ + + +
baseTMU peripheral base address.
statusThe pointer to interrupt status structure. Record the current interrupt status. Please refer to "tmu_interrupt_status_t" structure.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TMU_ClearInterruptStatusFlags (TMU_Type * base,
uint32_t mask 
)
+
+
Parameters
+ + + +
baseTMU peripheral base address.
maskThe mask of interrupt status flags. Refer to "_tmu_interrupt_status_flags" enumeration.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t TMU_GetStatusFlags (TMU_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseTMU peripheral base address.
+
+
+
Returns
The mask of status flags. Refer to "_tmu_status_flags" enumeration.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t TMU_GetHighestTemperature (TMU_Type * base,
uint32_t * temperature 
)
+
+
Parameters
+ + + +
baseTMU peripheral base address.
temperatureHighest temperature recorded in degrees Celsius by any enabled monitored site.
+
+
+
Returns
Execution status.
+
Return values
+ + + +
kStatus_SuccessTemperature reading is valid.
kStatus_FailTemperature reading is not valid due to no measured temperature within the sensor range of 0-125 °C for an enabled monitored site.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t TMU_GetLowestTemperature (TMU_Type * base,
uint32_t * temperature 
)
+
+
Parameters
+ + + +
baseTMU peripheral base address.
temperatureLowest temperature recorded in degrees Celsius by any enabled monitored site.
+
+
+
Returns
Execution status.
+
Return values
+ + + +
kStatus_SuccessTemperature reading is valid.
kStatus_FailTemperature reading is not valid due to no measured temperature within the sensor range of 0-125 °C for an enabled monitored site.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t TMU_GetImmediateTemperature (TMU_Type * base,
uint32_t siteIndex,
uint32_t * temperature 
)
+
+

The site must be part of the list of enabled monitored sites as defined by monitorSiteSelection in "tmu_config_t" structure.

+
Parameters
+ + + + +
baseTMU peripheral base address.
siteIndexThe index of the site user want to read. 0U: site0 ~ 15U: site15.
temperatureLast immediate temperature reading at site n .
+
+
+
Returns
Execution status.
+
Return values
+ + + +
kStatus_SuccessTemperature reading is valid.
kStatus_FailTemperature reading is not valid because temperature out of sensor range or first measurement still pending.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t TMU_GetAverageTemperature (TMU_Type * base,
uint32_t siteIndex,
uint32_t * temperature 
)
+
+

The site must be part of the list of enabled monitored sites as defined by monitorSiteSelection in "tmu_config_t" structure.

+
Parameters
+ + + + +
baseTMU peripheral base address.
siteIndexThe index of the site user want to read. 0U: site0 ~ 15U: site15.
temperatureLast average temperature reading at site n .
+
+
+
Returns
Execution status.
+
Return values
+ + + +
kStatus_SuccessTemperature reading is valid.
kStatus_FailTemperature reading is not valid because temperature out of sensor range or first measurement still pending.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TMU_SetHighTemperatureThresold (TMU_Type * base,
const tmu_thresold_config_t * config 
)
+
+
Parameters
+ + + +
baseTMU peripheral base address.
configPointer to configuration structure. Refer to "tmu_thresold_config_t" structure.
+
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00019.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00019.js new file mode 100644 index 000000000..0db9eb181 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00019.js @@ -0,0 +1,58 @@ +var a00019 = +[ + [ "tmu_thresold_config_t", "a00019.html#a00157", [ + [ "immediateThresoldEnable", "a00019.html#a26dcfbd2e1b2358536423c97a932b220", null ], + [ "AverageThresoldEnable", "a00019.html#a269f4768530d6a95fd23ad2bce651cde", null ], + [ "AverageCriticalThresoldEnable", "a00019.html#ae3422784818643c5e78ab9b2b545204b", null ], + [ "immediateThresoldValue", "a00019.html#a86a0ce2dd78e46a1b842a4c86afeee11", null ], + [ "averageThresoldValue", "a00019.html#aee4703600e7bae9134b7fb717071a3d0", null ], + [ "averageCriticalThresoldValue", "a00019.html#a36c49c9978a39decb657e72026189754", null ] + ] ], + [ "tmu_interrupt_status_t", "a00019.html#a00156", [ + [ "interruptDetectMask", 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"TMU_SetHighTemperatureThresold", "a00019.html#gae0fe58362113f09ec233fb83f4c1cc01", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00020.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00020.html new file mode 100644 index 000000000..16217ac69 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00020.html @@ -0,0 +1,2706 @@ + + + + + + +MCUXpresso SDK API Reference Manual: UART Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Macros | +Typedefs | +Enumerations | +Functions | +Variables
+
+
UART Driver
UART: Universal Asynchronous Receiver/Transmitter Driver
+
+
+

Overview

+

The MCUXpresso SDK provides a peripheral driver for the Universal Asynchronous Receiver/Transmitter (UART) module of MCUXpresso SDK devices.

+

The UART driver includes functional APIs and transactional APIs.

+

Functional APIs are used for UART initialization/configuration/operation for the purpose of optimization/customization. Using the functional API requires the knowledge of the UART peripheral and how to organize functional APIs to meet the application requirements. All functional APIs use the peripheral base address as the first parameter. UART functional operation groups provide the functional API set.

+

Transactional APIs can be used to enable the peripheral quickly and in the application if the code size and performance of transactional APIs can satisfy the requirements. If the code size and performance are critical requirements, see the transactional API implementation and write custom code. All transactional APIs use the uart_handle_t as the second parameter. Initialize the handle by calling the UART_TransferCreateHandle() API.

+

Transactional APIs support asynchronous transfer, which means that the functions UART_TransferSendNonBlocking() and UART_TransferReceiveNonBlocking() set up an interrupt for data transfer. When the transfer completes, the upper layer is notified through a callback function with the kStatus_UART_TxIdle and kStatus_UART_RxIdle.

+

Transactional receive APIs support the ring buffer. Prepare the memory for the ring buffer and pass in the start address and size while calling the UART_TransferCreateHandle(). If passing NULL, the ring buffer feature is disabled. When the ring buffer is enabled, the received data is saved to the ring buffer in the background. The UART_TransferReceiveNonBlocking() function first gets data from the ring buffer. If the ring buffer does not have enough data, the function first returns the data in the ring buffer and then saves the received data to user memory. When all data is received, the upper layer is informed through a callback with the kStatus_UART_RxIdle.

+

If the receive ring buffer is full, the upper layer is informed through a callback with the kStatus_UART_RxRingBufferOverrun. In the callback function, the upper layer reads data out from the ring buffer. If not, existing data is overwritten by the new data.

+

The ring buffer size is specified when creating the handle. Note that one byte is reserved for the ring buffer maintenance. When creating handle using the following code.

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/uart In this example, the buffer size is 32, but only 31 bytes are used for saving data.

+

+Typical use case

+

+UART Send/receive using a polling method

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/uart

+

+UART Send/receive using an interrupt method

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/uart

+

+UART Receive using the ringbuffer feature

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/uart

+

+UART automatic baud rate detect feature

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/uart

+ + + + + + + + + + + +

+Data Structures

struct  uart_config_t
 UART configuration structure. More...
 
struct  uart_transfer_t
 UART transfer structure. More...
 
struct  uart_handle_t
 UART handle structure. More...
 
+ + + + +

+Macros

#define UART_RETRY_TIMES   0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */
 Retry times for waiting flag. More...
 
+ + + + +

+Typedefs

typedef void(* uart_transfer_callback_t )(UART_Type *base, uart_handle_t *handle, status_t status, void *userData)
 UART transfer callback function. More...
 
+ + + + + + + + + + + + + + + + + + + + + + +

+Enumerations

enum  {
+  kStatus_UART_TxBusy = MAKE_STATUS(kStatusGroup_IUART, 0), +
+  kStatus_UART_RxBusy = MAKE_STATUS(kStatusGroup_IUART, 1), +
+  kStatus_UART_TxIdle = MAKE_STATUS(kStatusGroup_IUART, 2), +
+  kStatus_UART_RxIdle = MAKE_STATUS(kStatusGroup_IUART, 3), +
+  kStatus_UART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_IUART, 4), +
+  kStatus_UART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_IUART, 5), +
+  kStatus_UART_FlagCannotClearManually, +
+  kStatus_UART_Error = MAKE_STATUS(kStatusGroup_IUART, 7), +
+  kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_IUART, 8), +
+  kStatus_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_IUART, 9), +
+  kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_IUART, 10), +
+  kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_IUART, 11), +
+  kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_IUART, 12), +
+  kStatus_UART_BaudrateNotSupport, +
+  kStatus_UART_BreakDetect = MAKE_STATUS(kStatusGroup_IUART, 14), +
+  kStatus_UART_Timeout = MAKE_STATUS(kStatusGroup_IUART, 15) +
+ }
 Error codes for the UART driver. More...
 
enum  uart_data_bits_t {
+  kUART_SevenDataBits = 0x0U, +
+  kUART_EightDataBits = 0x1U +
+ }
 UART data bits count. More...
 
enum  uart_parity_mode_t {
+  kUART_ParityDisabled = 0x0U, +
+  kUART_ParityEven = 0x2U, +
+  kUART_ParityOdd = 0x3U +
+ }
 UART parity mode. More...
 
enum  uart_stop_bit_count_t {
+  kUART_OneStopBit = 0x0U, +
+  kUART_TwoStopBit = 0x1U +
+ }
 UART stop bit count. More...
 
enum  uart_idle_condition_t {
+  kUART_IdleFor4Frames = 0x0U, +
+  kUART_IdleFor8Frames = 0x1U, +
+  kUART_IdleFor16Frames = 0x2U, +
+  kUART_IdleFor32Frames = 0x3U +
+ }
 UART idle condition detect. More...
 
enum  _uart_interrupt_enable
 This structure contains the settings for all of the UART interrupt configurations. More...
 
enum  {
+  kUART_RxCharReadyFlag = 0x0000000FU, +
+  kUART_RxErrorFlag = 0x0000000EU, +
+  kUART_RxOverrunErrorFlag = 0x0000000DU, +
+  kUART_RxFrameErrorFlag = 0x0000000CU, +
+  kUART_RxBreakDetectFlag = 0x0000000BU, +
+  kUART_RxParityErrorFlag = 0x0000000AU, +
+  kUART_ParityErrorFlag = 0x0094000FU, +
+  kUART_RtsStatusFlag = 0x0094000EU, +
+  kUART_TxReadyFlag = 0x0094000DU, +
+  kUART_RtsDeltaFlag = 0x0094000CU, +
+  kUART_EscapeFlag = 0x0094000BU, +
+  kUART_FrameErrorFlag = 0x0094000AU, +
+  kUART_RxReadyFlag = 0x00940009U, +
+  kUART_AgingTimerFlag = 0x00940008U, +
+  kUART_DtrDeltaFlag = 0x00940007U, +
+  kUART_RxDsFlag = 0x00940006U, +
+  kUART_tAirWakeFlag = 0x00940005U, +
+  kUART_AwakeFlag = 0x00940004U, +
+  kUART_Rs485SlaveAddrMatchFlag = 0x00940003U, +
+  kUART_AutoBaudFlag = 0x0098000FU, +
+  kUART_TxEmptyFlag = 0x0098000EU, +
+  kUART_DtrFlag = 0x0098000DU, +
+  kUART_IdleFlag = 0x0098000CU, +
+  kUART_AutoBaudCntStopFlag = 0x0098000BU, +
+  kUART_RiDeltaFlag = 0x0098000AU, +
+  kUART_RiFlag = 0x00980009U, +
+  kUART_IrFlag = 0x00980008U, +
+  kUART_WakeFlag = 0x00980007U, +
+  kUART_DcdDeltaFlag = 0x00980006U, +
+  kUART_DcdFlag = 0x00980005U, +
+  kUART_RtsFlag = 0x00980004U, +
+  kUART_TxCompleteFlag = 0x00980003U, +
+  kUART_BreakDetectFlag = 0x00980002U, +
+  kUART_RxOverrunFlag = 0x00980001U, +
+  kUART_RxDataReadyFlag = 0x00980000U +
+ }
 UART status flags. More...
 
+ + + + +

+Functions

uint32_t UART_GetInstance (UART_Type *base)
 Get the UART instance from peripheral base address. More...
 
+ + + + +

+Variables

void * s_uartHandle []
 Pointers to uart handles for each instance. More...
 
+ + + + +

+Driver version

#define FSL_UART_DRIVER_VERSION   (MAKE_VERSION(2, 3, 1))
 UART driver version. More...
 
+ + + + +

+Software Reset

static void UART_SoftwareReset (UART_Type *base)
 Resets the UART using software. More...
 
+ + + + + + + + + + + + + + + + + + + + + + +

+Initialization and deinitialization

status_t UART_Init (UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz)
 Initializes an UART instance with the user configuration structure and the peripheral clock. More...
 
void UART_Deinit (UART_Type *base)
 Deinitializes a UART instance. More...
 
void UART_GetDefaultConfig (uart_config_t *config)
 l More...
 
status_t UART_SetBaudRate (UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
 Sets the UART instance baud rate. More...
 
static void UART_Enable (UART_Type *base)
 This function is used to Enable the UART Module. More...
 
static void UART_SetIdleCondition (UART_Type *base, uart_idle_condition_t condition)
 This function is used to configure the IDLE line condition. More...
 
static void UART_Disable (UART_Type *base)
 This function is used to Disable the UART Module. More...
 
+ + + + + + + +

+Status

bool UART_GetStatusFlag (UART_Type *base, uint32_t flag)
 This function is used to get the current status of specific UART status flag(including interrupt flag). More...
 
void UART_ClearStatusFlag (UART_Type *base, uint32_t flag)
 This function is used to clear the current status of specific UART status flag. More...
 
+ + + + + + + + + + +

+Interrupts

void UART_EnableInterrupts (UART_Type *base, uint32_t mask)
 Enables UART interrupts according to the provided mask. More...
 
void UART_DisableInterrupts (UART_Type *base, uint32_t mask)
 Disables the UART interrupts according to the provided mask. More...
 
uint32_t UART_GetEnabledInterrupts (UART_Type *base)
 Gets enabled UART interrupts. More...
 
+ + + + + + + + + + + + + + + + + + + +

+Bus Operations

static void UART_EnableTx (UART_Type *base, bool enable)
 Enables or disables the UART transmitter. More...
 
static void UART_EnableRx (UART_Type *base, bool enable)
 Enables or disables the UART receiver. More...
 
static void UART_WriteByte (UART_Type *base, uint8_t data)
 Writes to the transmitter register. More...
 
static uint8_t UART_ReadByte (UART_Type *base)
 Reads the receiver register. More...
 
status_t UART_WriteBlocking (UART_Type *base, const uint8_t *data, size_t length)
 Writes to the TX register using a blocking method. More...
 
status_t UART_ReadBlocking (UART_Type *base, uint8_t *data, size_t length)
 Read RX data register using a blocking method. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Transactional

void UART_TransferCreateHandle (UART_Type *base, uart_handle_t *handle, uart_transfer_callback_t callback, void *userData)
 Initializes the UART handle. More...
 
void UART_TransferStartRingBuffer (UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
 Sets up the RX ring buffer. More...
 
void UART_TransferStopRingBuffer (UART_Type *base, uart_handle_t *handle)
 Aborts the background transfer and uninstalls the ring buffer. More...
 
size_t UART_TransferGetRxRingBufferLength (uart_handle_t *handle)
 Get the length of received data in RX ring buffer. More...
 
status_t UART_TransferSendNonBlocking (UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer)
 Transmits a buffer of data using the interrupt method. More...
 
void UART_TransferAbortSend (UART_Type *base, uart_handle_t *handle)
 Aborts the interrupt-driven data transmit. More...
 
status_t UART_TransferGetSendCount (UART_Type *base, uart_handle_t *handle, uint32_t *count)
 Gets the number of bytes written to the UART TX register. More...
 
status_t UART_TransferReceiveNonBlocking (UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer, size_t *receivedBytes)
 Receives a buffer of data using an interrupt method. More...
 
void UART_TransferAbortReceive (UART_Type *base, uart_handle_t *handle)
 Aborts the interrupt-driven data receiving. More...
 
status_t UART_TransferGetReceiveCount (UART_Type *base, uart_handle_t *handle, uint32_t *count)
 Gets the number of bytes that have been received. More...
 
void UART_TransferHandleIRQ (UART_Type *base, void *irqHandle)
 UART IRQ handle function. More...
 
+ + + + + + + +

+DMA control functions.

static void UART_EnableTxDMA (UART_Type *base, bool enable)
 Enables or disables the UART transmitter DMA request. More...
 
static void UART_EnableRxDMA (UART_Type *base, bool enable)
 Enables or disables the UART receiver DMA request. More...
 
+ + + + + + + + + + +

+FIFO control functions.

static void UART_SetTxFifoWatermark (UART_Type *base, uint8_t watermark)
 This function is used to set the watermark of UART Tx FIFO. More...
 
static void UART_SetRxRTSWatermark (UART_Type *base, uint8_t watermark)
 This function is used to set the watermark of UART RTS deassertion. More...
 
static void UART_SetRxFifoWatermark (UART_Type *base, uint8_t watermark)
 This function is used to set the watermark of UART Rx FIFO. More...
 
+ + + + + + + +

+Auto baud rate detection.

static void UART_EnableAutoBaudRate (UART_Type *base, bool enable)
 This function is used to set the enable condition of Automatic Baud Rate Detection feature. More...
 
static bool UART_IsAutoBaudRateComplete (UART_Type *base)
 This function is used to read if the automatic baud rate detection has finished. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct uart_config_t
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

uint32_t baudRate_Bps
 UART baud rate. More...
 
uart_parity_mode_t parityMode
 Parity error check mode of this module. More...
 
+uart_data_bits_t dataBitsCount
 Data bits count, eight (default), seven.
 
uart_stop_bit_count_t stopBitCount
 Number of stop bits in one frame. More...
 
+uint8_t txFifoWatermark
 TX FIFO watermark.
 
+uint8_t rxFifoWatermark
 RX FIFO watermark.
 
+uint8_t rxRTSWatermark
 RX RTS watermark, RX FIFO data count being larger than this triggers RTS deassertion.
 
+bool enableAutoBaudRate
 Enable automatic baud rate detection.
 
+bool enableTx
 Enable TX.
 
+bool enableRx
 Enable RX.
 
+bool enableRxRTS
 RX RTS enable.
 
+bool enableTxCTS
 TX CTS enable.
 
+

Field Documentation

+ +
+
+ + + + +
uint32_t uart_config_t::baudRate_Bps
+
+ +
+
+ +
+
+ + + + +
uart_parity_mode_t uart_config_t::parityMode
+
+ +
+
+ +
+
+ + + + +
uart_stop_bit_count_t uart_config_t::stopBitCount
+
+ +
+
+ +
+
+ +
+
+ + + + +
struct uart_transfer_t
+
+
+ + + + + + + + + + + + + +

Data Fields

size_t dataSize
 The byte count to be transfer. More...
 
uint8_t * data
 The buffer of data to be transfer. More...
 
uint8_t * rxData
 The buffer to receive data. More...
 
const uint8_t * txData
 The buffer of data to be sent. More...
 
+

Field Documentation

+ +
+
+ + + + +
uint8_t* uart_transfer_t::data
+
+ +
+
+ +
+
+ + + + +
uint8_t* uart_transfer_t::rxData
+
+ +
+
+ +
+
+ + + + +
const uint8_t* uart_transfer_t::txData
+
+ +
+
+ +
+
+ + + + +
size_t uart_transfer_t::dataSize
+
+ +
+
+ +
+
+ +
+
+ + + + +
struct _uart_handle
+
+

Forward declaration of the handle typedef.

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

const uint8_t *volatile txData
 Address of remaining data to send. More...
 
volatile size_t txDataSize
 Size of the remaining data to send. More...
 
size_t txDataSizeAll
 Size of the data to send out. More...
 
uint8_t *volatile rxData
 Address of remaining data to receive. More...
 
volatile size_t rxDataSize
 Size of the remaining data to receive. More...
 
size_t rxDataSizeAll
 Size of the data to receive. More...
 
uint8_t * rxRingBuffer
 Start address of the receiver ring buffer. More...
 
size_t rxRingBufferSize
 Size of the ring buffer. More...
 
volatile uint16_t rxRingBufferHead
 Index for the driver to store received data into ring buffer. More...
 
volatile uint16_t rxRingBufferTail
 Index for the user to get data from the ring buffer. More...
 
uart_transfer_callback_t callback
 Callback function. More...
 
void * userData
 UART callback function parameter. More...
 
volatile uint8_t txState
 TX transfer state. More...
 
+volatile uint8_t rxState
 RX transfer state.
 
+

Field Documentation

+ +
+
+ + + + +
const uint8_t* volatile uart_handle_t::txData
+
+ +
+
+ +
+
+ + + + +
volatile size_t uart_handle_t::txDataSize
+
+ +
+
+ +
+
+ + + + +
size_t uart_handle_t::txDataSizeAll
+
+ +
+
+ +
+
+ + + + +
uint8_t* volatile uart_handle_t::rxData
+
+ +
+
+ +
+
+ + + + +
volatile size_t uart_handle_t::rxDataSize
+
+ +
+
+ +
+
+ + + + +
size_t uart_handle_t::rxDataSizeAll
+
+ +
+
+ +
+
+ + + + +
uint8_t* uart_handle_t::rxRingBuffer
+
+ +
+
+ +
+
+ + + + +
size_t uart_handle_t::rxRingBufferSize
+
+ +
+
+ +
+
+ + + + +
volatile uint16_t uart_handle_t::rxRingBufferHead
+
+ +
+
+ +
+
+ + + + +
volatile uint16_t uart_handle_t::rxRingBufferTail
+
+ +
+
+ +
+
+ + + + +
uart_transfer_callback_t uart_handle_t::callback
+
+ +
+
+ +
+
+ + + + +
void* uart_handle_t::userData
+
+ +
+
+ +
+
+ + + + +
volatile uint8_t uart_handle_t::txState
+
+ +
+
+ +
+
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_UART_DRIVER_VERSION   (MAKE_VERSION(2, 3, 1))
+
+ +
+
+ +
+
+ + + + +
#define UART_RETRY_TIMES   0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */
+
+ +
+
+

Typedef Documentation

+ +
+
+ + + + +
typedef void(* uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData)
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
anonymous enum
+
+ + + + + + + + + + + + + + + + + +
Enumerator
kStatus_UART_TxBusy  +

Transmitter is busy.

+
kStatus_UART_RxBusy  +

Receiver is busy.

+
kStatus_UART_TxIdle  +

UART transmitter is idle.

+
kStatus_UART_RxIdle  +

UART receiver is idle.

+
kStatus_UART_TxWatermarkTooLarge  +

TX FIFO watermark too large.

+
kStatus_UART_RxWatermarkTooLarge  +

RX FIFO watermark too large.

+
kStatus_UART_FlagCannotClearManually  +

UART flag can't be manually cleared.

+
kStatus_UART_Error  +

Error happens on UART.

+
kStatus_UART_RxRingBufferOverrun  +

UART RX software ring buffer overrun.

+
kStatus_UART_RxHardwareOverrun  +

UART RX receiver overrun.

+
kStatus_UART_NoiseError  +

UART noise error.

+
kStatus_UART_FramingError  +

UART framing error.

+
kStatus_UART_ParityError  +

UART parity error.

+
kStatus_UART_BaudrateNotSupport  +

Baudrate is not support in current clock source.

+
kStatus_UART_BreakDetect  +

Receiver detect BREAK signal.

+
kStatus_UART_Timeout  +

UART times out.

+
+ +
+
+ +
+
+ + + + +
enum uart_data_bits_t
+
+ + + +
Enumerator
kUART_SevenDataBits  +

Seven data bit.

+
kUART_EightDataBits  +

Eight data bit.

+
+ +
+
+ +
+
+ + + + +
enum uart_parity_mode_t
+
+ + + + +
Enumerator
kUART_ParityDisabled  +

Parity disabled.

+
kUART_ParityEven  +

Even error check is selected.

+
kUART_ParityOdd  +

Odd error check is selected.

+
+ +
+
+ +
+
+ + + + +
enum uart_stop_bit_count_t
+
+ + + +
Enumerator
kUART_OneStopBit  +

One stop bit.

+
kUART_TwoStopBit  +

Two stop bits.

+
+ +
+
+ +
+
+ + + + +
enum uart_idle_condition_t
+
+ + + + + +
Enumerator
kUART_IdleFor4Frames  +

Idle for more than 4 frames.

+
kUART_IdleFor8Frames  +

Idle for more than 8 frames.

+
kUART_IdleFor16Frames  +

Idle for more than 16 frames.

+
kUART_IdleFor32Frames  +

Idle for more than 32 frames.

+
+ +
+
+ +
+
+ + + + +
enum _uart_interrupt_enable
+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+

This provides constants for the UART status flags for use in the UART functions.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enumerator
kUART_RxCharReadyFlag  +

Rx Character Ready Flag.

+
kUART_RxErrorFlag  +

Rx Error Detect Flag.

+
kUART_RxOverrunErrorFlag  +

Rx Overrun Flag.

+
kUART_RxFrameErrorFlag  +

Rx Frame Error Flag.

+
kUART_RxBreakDetectFlag  +

Rx Break Detect Flag.

+
kUART_RxParityErrorFlag  +

Rx Parity Error Flag.

+
kUART_ParityErrorFlag  +

Parity Error Interrupt Flag.

+
kUART_RtsStatusFlag  +

RTS_B Pin Status Flag.

+
kUART_TxReadyFlag  +

Transmitter Ready Interrupt/DMA Flag.

+
kUART_RtsDeltaFlag  +

RTS Delta Flag.

+
kUART_EscapeFlag  +

Escape Sequence Interrupt Flag.

+
kUART_FrameErrorFlag  +

Frame Error Interrupt Flag.

+
kUART_RxReadyFlag  +

Receiver Ready Interrupt/DMA Flag.

+
kUART_AgingTimerFlag  +

Aging Timer Interrupt Flag.

+
kUART_DtrDeltaFlag  +

DTR Delta Flag.

+
kUART_RxDsFlag  +

Receiver IDLE Interrupt Flag.

+
kUART_tAirWakeFlag  +

Asynchronous IR WAKE Interrupt Flag.

+
kUART_AwakeFlag  +

Asynchronous WAKE Interrupt Flag.

+
kUART_Rs485SlaveAddrMatchFlag  +

RS-485 Slave Address Detected Interrupt Flag.

+
kUART_AutoBaudFlag  +

Automatic Baud Rate Detect Complete Flag.

+
kUART_TxEmptyFlag  +

Transmit Buffer FIFO Empty.

+
kUART_DtrFlag  +

DTR edge triggered interrupt flag.

+
kUART_IdleFlag  +

Idle Condition Flag.

+
kUART_AutoBaudCntStopFlag  +

Auto-baud Counter Stopped Flag.

+
kUART_RiDeltaFlag  +

Ring Indicator Delta Flag.

+
kUART_RiFlag  +

Ring Indicator Input Flag.

+
kUART_IrFlag  +

Serial Infrared Interrupt Flag.

+
kUART_WakeFlag  +

Wake Flag.

+
kUART_DcdDeltaFlag  +

Data Carrier Detect Delta Flag.

+
kUART_DcdFlag  +

Data Carrier Detect Input Flag.

+
kUART_RtsFlag  +

RTS Edge Triggered Interrupt Flag.

+
kUART_TxCompleteFlag  +

Transmitter Complete Flag.

+
kUART_BreakDetectFlag  +

BREAK Condition Detected Flag.

+
kUART_RxOverrunFlag  +

Overrun Error Flag.

+
kUART_RxDataReadyFlag  +

Receive Data Ready Flag.

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t UART_GetInstance (UART_Type * base)
+
+
Parameters
+ + +
baseUART peripheral base address.
+
+
+
Returns
UART instance.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void UART_SoftwareReset (UART_Type * base)
+ 		+inlinestatic
+
+

This function resets the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3]

+
Parameters
+ + +
baseUART peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t UART_Init (UART_Type * base,
const uart_config_t * config,
uint32_t srcClock_Hz 
)
+
+

This function configures the UART module with user-defined settings. Call the UART_GetDefaultConfig() function to configure the configuration structure and get the default configuration. The example below shows how to use this API to configure the UART.

+
* uart_config_t uartConfig;
+
* uartConfig.baudRate_Bps = 115200U;
+
* uartConfig.parityMode = kUART_ParityDisabled;
+
* uartConfig.dataBitsCount = kUART_EightDataBits;
+
* uartConfig.stopBitCount = kUART_OneStopBit;
+
* uartConfig.txFifoWatermark = 2;
+
* uartConfig.rxFifoWatermark = 1;
+
* uartConfig.enableAutoBaudrate = false;
+
* uartConfig.enableTx = true;
+
* uartConfig.enableRx = true;
+
* UART_Init(UART1, &uartConfig, 24000000U);
+
*
+
Parameters
+ + + + +
baseUART peripheral base address.
configPointer to a user-defined configuration structure.
srcClock_HzUART clock source frequency in HZ.
+
+
+
Return values
+ + +
kStatus_SuccessUART initialize succeed
+
+
+ +
+
+ +
+
+ + + + + + + + +
void UART_Deinit (UART_Type * base)
+
+

This function waits for transmit to complete, disables TX and RX, and disables the UART clock.

+
Parameters
+ + +
baseUART peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void UART_GetDefaultConfig (uart_config_t * config)
+
+

Gets the default configuration structure.

+

This function initializes the UART configuration structure to a default value. The default values are: uartConfig->baudRate_Bps = 115200U; uartConfig->parityMode = kUART_ParityDisabled; uartConfig->dataBitsCount = kUART_EightDataBits; uartConfig->stopBitCount = kUART_OneStopBit; uartConfig->txFifoWatermark = 2; uartConfig->rxFifoWatermark = 1; uartConfig->enableAutoBaudrate = flase; uartConfig->enableTx = false; uartConfig->enableRx = false;

+
Parameters
+ + +
configPointer to a configuration structure.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t UART_SetBaudRate (UART_Type * base,
uint32_t baudRate_Bps,
uint32_t srcClock_Hz 
)
+
+

This function configures the UART module baud rate. This function is used to update the UART module baud rate after the UART module is initialized by the UART_Init.

+
* UART_SetBaudRate(UART1, 115200U, 20000000U);
+
*
+
Parameters
+ + + + +
baseUART peripheral base address.
baudRate_BpsUART baudrate to be set.
srcClock_HzUART clock source frequency in Hz.
+
+
+
Return values
+ + + +
kStatus_UART_BaudrateNotSupportBaudrate is not support in the current clock source.
kStatus_SuccessSet baudrate succeeded.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void UART_Enable (UART_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseUART base pointer.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void UART_SetIdleCondition (UART_Type * base,
uart_idle_condition_t condition 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseUART base pointer.
conditionIDLE line detect condition of the enumerators in uart_idle_condition_t.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void UART_Disable (UART_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseUART base pointer.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
bool UART_GetStatusFlag (UART_Type * base,
uint32_t flag 
)
+
+

The available status flag can be select from uart_status_flag_t enumeration.

+
Parameters
+ + + +
baseUART base pointer.
flagStatus flag to check.
+
+
+
Return values
+ + +
currentstate of corresponding status flag.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void UART_ClearStatusFlag (UART_Type * base,
uint32_t flag 
)
+
+

The available status flag can be select from uart_status_flag_t enumeration.

+
Parameters
+ + + +
baseUART base pointer.
flagStatus flag to clear.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void UART_EnableInterrupts (UART_Type * base,
uint32_t mask 
)
+
+

This function enables the UART interrupts according to the provided mask. The mask is a logical OR of enumeration members. See _uart_interrupt_enable. For example, to enable TX empty interrupt and RX data ready interrupt, do the following.

+
* UART_EnableInterrupts(UART1,kUART_TxEmptyEnable | kUART_RxDataReadyEnable);
+
*
+
Parameters
+ + + +
baseUART peripheral base address.
maskThe interrupts to enable. Logical OR of _uart_interrupt_enable.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void UART_DisableInterrupts (UART_Type * base,
uint32_t mask 
)
+
+

This function disables the UART interrupts according to the provided mask. The mask is a logical OR of enumeration members. See _uart_interrupt_enable. For example, to disable TX empty interrupt and RX data ready interrupt do the following.

+
* UART_EnableInterrupts(UART1,kUART_TxEmptyEnable | kUART_RxDataReadyEnable);
+
*
+
Parameters
+ + + +
baseUART peripheral base address.
maskThe interrupts to disable. Logical OR of _uart_interrupt_enable.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t UART_GetEnabledInterrupts (UART_Type * base)
+
+

This function gets the enabled UART interrupts. The enabled interrupts are returned as the logical OR value of the enumerators _uart_interrupt_enable. To check a specific interrupt enable status, compare the return value with enumerators in _uart_interrupt_enable. For example, to check whether the TX empty interrupt is enabled:

+
* uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1);
+
*
+
* if (kUART_TxEmptyEnable & enabledInterrupts)
+
* {
+
* ...
+
* }
+
*
+
Parameters
+ + +
baseUART peripheral base address.
+
+
+
Returns
UART interrupt flags which are logical OR of the enumerators in _uart_interrupt_enable.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void UART_EnableTx (UART_Type * base,
bool enable 
)
+ 		+inlinestatic
+
+

This function enables or disables the UART transmitter.

+
Parameters
+ + + +
baseUART peripheral base address.
enableTrue to enable, false to disable.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void UART_EnableRx (UART_Type * base,
bool enable 
)
+ 		+inlinestatic
+
+

This function enables or disables the UART receiver.

+
Parameters
+ + + +
baseUART peripheral base address.
enableTrue to enable, false to disable.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void UART_WriteByte (UART_Type * base,
uint8_t data 
)
+ 		+inlinestatic
+
+

This function is used to write data to transmitter register. The upper layer must ensure that the TX register is empty or that the TX FIFO has room before calling this function.

+
Parameters
+ + + +
baseUART peripheral base address.
dataData write to the TX register.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint8_t UART_ReadByte (UART_Type * base)
+ 		+inlinestatic
+
+

This function is used to read data from receiver register. The upper layer must ensure that the receiver register is full or that the RX FIFO has data before calling this function.

+
Parameters
+ + +
baseUART peripheral base address.
+
+
+
Returns
Data read from data register.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t UART_WriteBlocking (UART_Type * base,
const uint8_t * data,
size_t length 
)
+
+

This function polls the TX register, waits for the TX register to be empty or for the TX FIFO to have room and writes data to the TX buffer.

+
Parameters
+ + + + +
baseUART peripheral base address.
dataStart address of the data to write.
lengthSize of the data to write.
+
+
+
Return values
+ + + +
kStatus_UART_TimeoutTransmission timed out and was aborted.
kStatus_SuccessSuccessfully wrote all data.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t UART_ReadBlocking (UART_Type * base,
uint8_t * data,
size_t length 
)
+
+

This function polls the RX register, waits for the RX register to be full or for RX FIFO to have data, and reads data from the TX register.

+
Parameters
+ + + + +
baseUART peripheral base address.
dataStart address of the buffer to store the received data.
lengthSize of the buffer.
+
+
+
Return values
+ + + + + + + +
kStatus_UART_RxHardwareOverrunReceiver overrun occurred while receiving data.
kStatus_UART_NoiseErrorA noise error occurred while receiving data.
kStatus_UART_FramingErrorA framing error occurred while receiving data.
kStatus_UART_ParityErrorA parity error occurred while receiving data.
kStatus_UART_TimeoutTransmission timed out and was aborted.
kStatus_SuccessSuccessfully received all data.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void UART_TransferCreateHandle (UART_Type * base,
uart_handle_t * handle,
uart_transfer_callback_t callback,
void * userData 
)
+
+

This function initializes the UART handle which can be used for other UART transactional APIs. Usually, for a specified UART instance, call this API once to get the initialized handle.

+
Parameters
+ + + + + +
baseUART peripheral base address.
handleUART handle pointer.
callbackThe callback function.
userDataThe parameter of the callback function.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void UART_TransferStartRingBuffer (UART_Type * base,
uart_handle_t * handle,
uint8_t * ringBuffer,
size_t ringBufferSize 
)
+
+

This function sets up the RX ring buffer to a specific UART handle.

+

When the RX ring buffer is used, data received are stored into the ring buffer even when the user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received in the ring buffer, the user can get the received data from the ring buffer directly.

+
Note
When using the RX ring buffer, one byte is reserved for internal use. In other words, if ringBufferSize is 32, only 31 bytes are used for saving data.
+
Parameters
+ + + + + +
baseUART peripheral base address.
handleUART handle pointer.
ringBufferStart address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
ringBufferSizeSize of the ring buffer.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void UART_TransferStopRingBuffer (UART_Type * base,
uart_handle_t * handle 
)
+
+

This function aborts the background transfer and uninstalls the ring buffer.

+
Parameters
+ + + +
baseUART peripheral base address.
handleUART handle pointer.
+
+
+ +
+
+ +
+
+ + + + + + + + +
size_t UART_TransferGetRxRingBufferLength (uart_handle_t * handle)
+
+
Parameters
+ + +
handleUART handle pointer.
+
+
+
Returns
Length of received data in RX ring buffer.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t UART_TransferSendNonBlocking (UART_Type * base,
uart_handle_t * handle,
uart_transfer_t * xfer 
)
+
+

This function sends data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data to be written to the TX register. When all data is written to the TX register in the ISR, the UART driver calls the callback function and passes the kStatus_UART_TxIdle as status parameter.

+
Note
The kStatus_UART_TxIdle is passed to the upper layer when all data is written to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX, check the kUART_TransmissionCompleteFlag to ensure that the TX is finished.
+
Parameters
+ + + + +
baseUART peripheral base address.
handleUART handle pointer.
xferUART transfer structure. See uart_transfer_t.
+
+
+
Return values
+ + + + +
kStatus_SuccessSuccessfully start the data transmission.
kStatus_UART_TxBusyPrevious transmission still not finished; data not all written to TX register yet.
kStatus_InvalidArgumentInvalid argument.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void UART_TransferAbortSend (UART_Type * base,
uart_handle_t * handle 
)
+
+

This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out how many bytes are not sent out.

+
Parameters
+ + + +
baseUART peripheral base address.
handleUART handle pointer.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t UART_TransferGetSendCount (UART_Type * base,
uart_handle_t * handle,
uint32_t * count 
)
+
+

This function gets the number of bytes written to the UART TX register by using the interrupt method.

+
Parameters
+ + + + +
baseUART peripheral base address.
handleUART handle pointer.
countSend bytes count.
+
+
+
Return values
+ + + + +
kStatus_NoTransferInProgressNo send in progress.
kStatus_InvalidArgumentThe parameter is invalid.
kStatus_SuccessGet successfully through the parameter count;
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
status_t UART_TransferReceiveNonBlocking (UART_Type * base,
uart_handle_t * handle,
uart_transfer_t * xfer,
size_t * receivedBytes 
)
+
+

This function receives data using an interrupt method. This is a non-blocking function, which returns without waiting for all data to be received. If the RX ring buffer is used and not empty, the data in the ring buffer is copied and the parameter receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in the ring buffer is not enough to read, the receive request is saved by the UART driver. When the new data arrives, the receive request is serviced first. When all data is received, the UART driver notifies the upper layer through a callback function and passes the status parameter kStatus_UART_RxIdle. For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. The 5 bytes are copied to the xfer->data and this function returns with the parameter receivedBytes set to 5. For the left 5 bytes, newly arrived data is saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to the xfer->data. When all data is received, the upper layer is notified.

+
Parameters
+ + + + + +
baseUART peripheral base address.
handleUART handle pointer.
xferUART transfer structure, see uart_transfer_t.
receivedBytesBytes received from the ring buffer directly.
+
+
+
Return values
+ + + + +
kStatus_SuccessSuccessfully queue the transfer into transmit queue.
kStatus_UART_RxBusyPrevious receive request is not finished.
kStatus_InvalidArgumentInvalid argument.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void UART_TransferAbortReceive (UART_Type * base,
uart_handle_t * handle 
)
+
+

This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know how many bytes are not received yet.

+
Parameters
+ + + +
baseUART peripheral base address.
handleUART handle pointer.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t UART_TransferGetReceiveCount (UART_Type * base,
uart_handle_t * handle,
uint32_t * count 
)
+
+

This function gets the number of bytes that have been received.

+
Parameters
+ + + + +
baseUART peripheral base address.
handleUART handle pointer.
countReceive bytes count.
+
+
+
Return values
+ + + + +
kStatus_NoTransferInProgressNo receive in progress.
kStatus_InvalidArgumentParameter is invalid.
kStatus_SuccessGet successfully through the parameter count;
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void UART_TransferHandleIRQ (UART_Type * base,
void * irqHandle 
)
+
+

This function handles the UART transmit and receive IRQ request.

+
Parameters
+ + + +
baseUART peripheral base address.
irqHandleUART handle pointer.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void UART_EnableTxDMA (UART_Type * base,
bool enable 
)
+ 		+inlinestatic
+
+

This function enables or disables the transmit request when the transmitter has one or more slots available in the TxFIFO. The fill level in the TxFIFO that generates the DMA request is controlled by the TXTL bits.

+
Parameters
+ + + +
baseUART peripheral base address.
enableTrue to enable, false to disable.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void UART_EnableRxDMA (UART_Type * base,
bool enable 
)
+ 		+inlinestatic
+
+

This function enables or disables the receive request when the receiver has data in the RxFIFO. The fill level in the RxFIFO at which a DMA request is generated is controlled by the RXTL bits .

+
Parameters
+ + + +
baseUART peripheral base address.
enableTrue to enable, false to disable.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void UART_SetTxFifoWatermark (UART_Type * base,
uint8_t watermark 
)
+ 		+inlinestatic
+
+
   A maskable interrupt is generated whenever the data level in
+   the TxFIFO falls below the Tx FIFO watermark.
+
Parameters
+ + + +
baseUART base pointer.
watermarkThe Tx FIFO watermark.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void UART_SetRxRTSWatermark (UART_Type * base,
uint8_t watermark 
)
+ 		+inlinestatic
+
+

The RTS signal deasserts whenever the data count in RxFIFO reaches the Rx RTS watermark.

+
Parameters
+ + + +
baseUART base pointer.
watermarkThe Rx RTS watermark.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void UART_SetRxFifoWatermark (UART_Type * base,
uint8_t watermark 
)
+ 		+inlinestatic
+
+
   A maskable interrupt is generated whenever the data level in
+   the RxFIFO reaches the Rx FIFO watermark.
+
Parameters
+ + + +
baseUART base pointer.
watermarkThe Rx FIFO watermark.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void UART_EnableAutoBaudRate (UART_Type * base,
bool enable 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseUART base pointer.
enableEnable/Disable Automatic Baud Rate Detection feature.
    +
  • true: Enable Automatic Baud Rate Detection feature.
    • +
  • false: Disable Automatic Baud Rate Detection feature.
    • +
+
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static bool UART_IsAutoBaudRateComplete (UART_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
baseUART base pointer.
+
+
+
Returns
- true: Automatic baud rate detection has finished.
    +
  • false: Automatic baud rate detection has not finished.
    • +
+
+ +
+
+

Variable Documentation

+ +
+
+ + + + +
void* s_uartHandle[]
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00020.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00020.js new file mode 100644 index 000000000..38943f41e --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00020.js @@ -0,0 +1,154 @@ +var a00020 = +[ + [ "uart_config_t", "a00020.html#a00158", [ + [ "baudRate_Bps", "a00020.html#acc123668836f3432c54ee6a2f6f318f1", null ], + [ "parityMode", "a00020.html#a1a3abcf4f0f5d0a3893df14f2991aa39", null ], + [ "dataBitsCount", "a00020.html#aa026642db643d8cae1a64869acd9baf5", null ], + [ "stopBitCount", "a00020.html#adf6e33c13910e9ec7c2688f83a462be0", null ], + [ "txFifoWatermark", "a00020.html#a5eb9ab81752080bc726b8d625d2b6b21", null ], + [ "rxFifoWatermark", "a00020.html#a1bb7b2f0f7df79977d33be264fb5163a", null ], + [ "rxRTSWatermark", "a00020.html#a4c7cdd2e54c98166de5148ffe637ce8c", null ], + [ "enableAutoBaudRate", "a00020.html#ac595435b68632c2dbaece764c54cd41d", null ], + [ "enableTx", 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"a00020.html#ga5a6ca92e153c2a2c1323c5dc2fae6ab4", null ], + [ "UART_ClearStatusFlag", "a00020.html#gaf547a539e6d7540010ef688e51bc2eeb", null ], + [ "UART_EnableInterrupts", "a00020.html#ga49ecd761481a22956e3f46285038719c", null ], + [ "UART_DisableInterrupts", "a00020.html#ga3f24b6b9b730046a9a81918f9abe7d99", null ], + [ "UART_GetEnabledInterrupts", "a00020.html#ga79bc0b880286ec0dc0543606fc772912", null ], + [ "UART_EnableTx", "a00020.html#gaf2ed68f3dd6ee8a272e9afd8ebd84f93", null ], + [ "UART_EnableRx", "a00020.html#gaa503e36c8ce82f1042ce186b9863871f", null ], + [ "UART_WriteByte", "a00020.html#ga371d2ceda535de3a74beba5a3465fab0", null ], + [ "UART_ReadByte", "a00020.html#ga3728011ac7906f3e03bb677b0f9cf7b4", null ], + [ "UART_WriteBlocking", "a00020.html#gabedf96691af44a8fafec58d5cf6e4dd2", null ], + [ "UART_ReadBlocking", "a00020.html#ga39d59e8a94f1af451a0db81888596639", null ], + [ "UART_TransferCreateHandle", "a00020.html#ga63db308c32019b7dd6c0647d618e5247", null ], + [ "UART_TransferStartRingBuffer", "a00020.html#ga223fba584bfabd599629d5ce92f929ac", null ], + [ "UART_TransferStopRingBuffer", "a00020.html#ga0c0bc73df49cb31dff0e903630314f5b", null ], + [ "UART_TransferGetRxRingBufferLength", "a00020.html#ga3921aa660977ca77dadf95fa35f1c3a9", null ], + [ "UART_TransferSendNonBlocking", "a00020.html#gad89afd7db1656c5aef404bb285d0dc05", null ], + [ "UART_TransferAbortSend", "a00020.html#gaa64f9f89d8286fd3ef0736a8c40be2c2", null ], + [ "UART_TransferGetSendCount", "a00020.html#ga071727ba05b2937ef5ad641ca7faf9c7", null ], + [ "UART_TransferReceiveNonBlocking", "a00020.html#gaf804acde5d73ce0a5bf54b06195e1218", null ], + [ "UART_TransferAbortReceive", "a00020.html#gacc35671622b2401545cc55cc6ae572d4", null ], + [ "UART_TransferGetReceiveCount", "a00020.html#ga05df10f570cdca4ac2dff63b069d254e", null ], + [ "UART_TransferHandleIRQ", "a00020.html#ga9b9c99f73429317bfce6065c82b0db3c", null ], + [ "UART_EnableTxDMA", "a00020.html#ga93a5d80d9f8ec9e61eb54db18efa5c63", null ], + [ "UART_EnableRxDMA", "a00020.html#ga32e14856ac77e50800e733ba8ab9c448", null ], + [ "UART_SetTxFifoWatermark", "a00020.html#ga5ed56b76143c42e6e712d1a4d6a1fbdd", null ], + [ "UART_SetRxRTSWatermark", "a00020.html#ga987939442aa7baa6fa043a0fbfa4ea03", null ], + [ "UART_SetRxFifoWatermark", "a00020.html#ga9fc461e2d9a906a2b5aa1363ab06044c", null ], + [ "UART_EnableAutoBaudRate", "a00020.html#gac88019d2b8abe60bd6ee8cf2c1e8dfb0", null ], + [ "UART_IsAutoBaudRateComplete", "a00020.html#ga28850ab8c31bd095fde407992b937035", null ], + [ "s_uartHandle", "a00020.html#ga5795f92ab50688d9700481929e79c014", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00021.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00021.html new file mode 100644 index 000000000..93ba8204b --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00021.html @@ -0,0 +1,361 @@ + + + + + + +MCUXpresso SDK API Reference Manual: UART FreeRTOS Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures
+
+
UART FreeRTOS Driver
UART: Universal Asynchronous Receiver/Transmitter Driver
+
+
+

Overview

+ + + + + +

+Data Structures

struct  uart_rtos_config_t
 UART configuration structure. More...
 
+ + + + +

+Driver version

#define FSL_UART_FREERTOS_DRIVER_VERSION   (MAKE_VERSION(2, 1, 1))
 UART FreeRTOS driver version 2.1.1. More...
 
+ + + + + + + +

+UART RTOS Operation

int UART_RTOS_Init (uart_rtos_handle_t *handle, uart_handle_t *t_handle, const uart_rtos_config_t *cfg)
 Initializes a UART instance for operation in RTOS. More...
 
int UART_RTOS_Deinit (uart_rtos_handle_t *handle)
 Deinitializes a UART instance for operation. More...
 
+ + + + + + + +

+UART transactional Operation

int UART_RTOS_Send (uart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length)
 Sends data in the background. More...
 
int UART_RTOS_Receive (uart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received)
 Receives data. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct uart_rtos_config_t
+
+
+ + + + + + + + + + + + + + + + + + + + + + +

Data Fields

+UART_Type * base
 UART base address.
 
+uint32_t srcclk
 UART source clock in Hz.
 
+uint32_t baudrate
 Desired communication speed.
 
+uart_parity_mode_t parity
 Parity setting.
 
+uart_stop_bit_count_t stopbits
 Number of stop bits to use.
 
+uint8_t * buffer
 Buffer for background reception.
 
+uint32_t buffer_size
 Size of buffer for background reception.
 
+ +
+
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_UART_FREERTOS_DRIVER_VERSION   (MAKE_VERSION(2, 1, 1))
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
int UART_RTOS_Init (uart_rtos_handle_t * handle,
uart_handle_t * t_handle,
const uart_rtos_config_t * cfg 
)
+
+
Parameters
+ + + + +
handleThe RTOS UART handle, the pointer to an allocated space for RTOS context.
t_handleThe pointer to the allocated space to store the transactional layer internal state.
cfgThe pointer to the parameters required to configure the UART after initialization.
+
+
+
Returns
0 succeed; otherwise fail.
+ +
+
+ +
+
+ + + + + + + + +
int UART_RTOS_Deinit (uart_rtos_handle_t * handle)
+
+

This function deinitializes the UART module, sets all register values to reset value, and frees the resources.

+
Parameters
+ + +
handleThe RTOS UART handle.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
int UART_RTOS_Send (uart_rtos_handle_t * handle,
uint8_t * buffer,
uint32_t length 
)
+
+

This function sends data. It is a synchronous API. If the hardware buffer is full, the task is in the blocked state.

+
Parameters
+ + + + +
handleThe RTOS UART handle.
bufferThe pointer to the buffer to send.
lengthThe number of bytes to send.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
int UART_RTOS_Receive (uart_rtos_handle_t * handle,
uint8_t * buffer,
uint32_t length,
size_t * received 
)
+
+

This function receives data from UART. It is a synchronous API. If data is immediately available, it is returned immediately and the number of bytes received.

+
Parameters
+ + + + + +
handleThe RTOS UART handle.
bufferThe pointer to the buffer to write received data.
lengthThe number of bytes to receive.
receivedThe pointer to a variable of size_t where the number of received data is filled.
+
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00021.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00021.js new file mode 100644 index 000000000..900ee9eb1 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00021.js @@ -0,0 +1,17 @@ +var a00021 = +[ + [ "uart_rtos_config_t", "a00021.html#a00159", [ + [ "base", "a00021.html#af93759d3503ab560aef347c02e5f42dd", null ], + [ "srcclk", "a00021.html#aaa9ea3cb62d50a49b907b1baddbeeaa0", null ], + [ "baudrate", "a00021.html#a3a516fb385a59c89720a3dead326df78", null ], + [ "parity", "a00021.html#a8d8809aff183104892d30cc0734679bd", null ], + [ "stopbits", "a00021.html#a2afb208100058edfc05aa161e555483f", null ], + [ "buffer", "a00021.html#ad05b4abce6a95baa7ba35eaa57569cfe", null ], + [ "buffer_size", "a00021.html#a7b7d6d667f6e06c720f506a07869e14d", null ] + ] ], + [ "FSL_UART_FREERTOS_DRIVER_VERSION", "a00021.html#ga0023d77491809dff862358266574febb", null ], + [ "UART_RTOS_Init", "a00021.html#ga1ca9d0f6b8d4d5fc3e64c9a57d7ada7d", null ], + [ "UART_RTOS_Deinit", "a00021.html#gab7ac281cb85e1d290c8f25c83a6facfc", null ], + [ "UART_RTOS_Send", "a00021.html#gac14fc0e6c6cac6818958e92d2f8950bb", null ], + [ "UART_RTOS_Receive", "a00021.html#gaa8adcb11232b565985f3f5961815a00c", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00022.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00022.html new file mode 100644 index 000000000..08044b868 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00022.html @@ -0,0 +1,818 @@ + + + + + + +MCUXpresso SDK API Reference Manual: WDOG: Watchdog Timer Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Enumerations
+
+
WDOG: Watchdog Timer Driver
+
+
+

Overview

+

The MCUXpresso SDK provides a peripheral driver for the Watchdog module (WDOG) of MCUXpresso SDK devices.

+

+Typical use case

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/wdog

+ + + + + + + + +

+Data Structures

struct  wdog_work_mode_t
 Defines WDOG work mode. More...
 
struct  wdog_config_t
 Describes WDOG configuration structure. More...
 
+ + + + + + + +

+Enumerations

enum  _wdog_interrupt_enable { kWDOG_InterruptEnable = WDOG_WICR_WIE_MASK + }
 WDOG interrupt configuration structure, default settings all disabled. More...
 
enum  _wdog_status_flags {
+  kWDOG_RunningFlag = WDOG_WCR_WDE_MASK, +
+  kWDOG_PowerOnResetFlag = WDOG_WRSR_POR_MASK, +
+  kWDOG_TimeoutResetFlag = WDOG_WRSR_TOUT_MASK, +
+  kWDOG_SoftwareResetFlag = WDOG_WRSR_SFTW_MASK, +
+  kWDOG_InterruptFlag = WDOG_WICR_WTIS_MASK +
+ }
 WDOG status flags. More...
 
+ + + + +

+Driver version

+#define FSL_WDOG_DRIVER_VERSION   (MAKE_VERSION(2, 1, 1))
 Defines WDOG driver version.
 
+ + + +

+Refresh sequence

+#define WDOG_REFRESH_KEY   (0xAAAA5555U)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+WDOG Initialization and De-initialization.

void WDOG_GetDefaultConfig (wdog_config_t *config)
 Initializes the WDOG configuration structure. More...
 
void WDOG_Init (WDOG_Type *base, const wdog_config_t *config)
 Initializes the WDOG. More...
 
void WDOG_Deinit (WDOG_Type *base)
 Shuts down the WDOG. More...
 
static void WDOG_Enable (WDOG_Type *base)
 Enables the WDOG module. More...
 
static void WDOG_Disable (WDOG_Type *base)
 Disables the WDOG module. More...
 
static void WDOG_TriggerSystemSoftwareReset (WDOG_Type *base)
 Trigger the system software reset. More...
 
static void WDOG_TriggerSoftwareSignal (WDOG_Type *base)
 Trigger an output assertion. More...
 
static void WDOG_EnableInterrupts (WDOG_Type *base, uint16_t mask)
 Enables the WDOG interrupt. More...
 
uint16_t WDOG_GetStatusFlags (WDOG_Type *base)
 Gets the WDOG all reset status flags. More...
 
void WDOG_ClearInterruptStatus (WDOG_Type *base, uint16_t mask)
 Clears the WDOG flag. More...
 
static void WDOG_SetTimeoutValue (WDOG_Type *base, uint16_t timeoutCount)
 Sets the WDOG timeout value. More...
 
static void WDOG_SetInterrputTimeoutValue (WDOG_Type *base, uint16_t timeoutCount)
 Sets the WDOG interrupt count timeout value. More...
 
static void WDOG_DisablePowerDownEnable (WDOG_Type *base)
 Disable the WDOG power down enable bit. More...
 
void WDOG_Refresh (WDOG_Type *base)
 Refreshes the WDOG timer. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct wdog_work_mode_t
+
+
+ + + + + + + + + + +

Data Fields

+bool enableWait
 continue or suspend WDOG in wait mode
 
+bool enableStop
 continue or suspend WDOG in stop mode
 
+bool enableDebug
 continue or suspend WDOG in debug mode
 
+ +
+
+ +
+
+ + + + +
struct wdog_config_t
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

+bool enableWdog
 Enables or disables WDOG.
 
+wdog_work_mode_t workMode
 Configures WDOG work mode in debug stop and wait mode.
 
+bool enableInterrupt
 Enables or disables WDOG interrupt.
 
+uint16_t timeoutValue
 Timeout value.
 
+uint16_t interruptTimeValue
 Interrupt count timeout value.
 
+bool softwareResetExtension
 software reset extension
 
+bool enablePowerDown
 power down enable bit
 
bool enableTimeOutAssert
 Enable WDOG_B timeout assertion. More...
 
+

Field Documentation

+ +
+
+ + + + +
bool wdog_config_t::enableTimeOutAssert
+
+ +
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum _wdog_interrupt_enable
+
+

This structure contains the settings for all of the WDOG interrupt configurations.

+ + +
Enumerator
kWDOG_InterruptEnable  +

WDOG timeout generates an interrupt before reset.

+
+ +
+
+ +
+
+ + + + +
enum _wdog_status_flags
+
+

This structure contains the WDOG status flags for use in the WDOG functions.

+ + + + + + +
Enumerator
kWDOG_RunningFlag  +

Running flag, set when WDOG is enabled.

+
kWDOG_PowerOnResetFlag  +

Power On flag, set when reset is the result of a powerOnReset.

+
kWDOG_TimeoutResetFlag  +

Timeout flag, set when reset is the result of a timeout.

+
kWDOG_SoftwareResetFlag  +

Software flag, set when reset is the result of a software.

+
kWDOG_InterruptFlag  +

interrupt flag,whether interrupt has occurred or not

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
void WDOG_GetDefaultConfig (wdog_config_t * config)
+
+

This function initializes the WDOG configuration structure to default values. The default values are as follows.

+
* wdogConfig->enableWdog = true;
+
* wdogConfig->workMode.enableWait = true;
+
* wdogConfig->workMode.enableStop = false;
+
* wdogConfig->workMode.enableDebug = false;
+
* wdogConfig->enableInterrupt = false;
+
* wdogConfig->enablePowerdown = false;
+
* wdogConfig->resetExtension = flase;
+
* wdogConfig->timeoutValue = 0xFFU;
+
* wdogConfig->interruptTimeValue = 0x04u;
+
*
+
Parameters
+ + +
configPointer to the WDOG configuration structure.
+
+
+
See Also
wdog_config_t
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void WDOG_Init (WDOG_Type * base,
const wdog_config_t * config 
)
+
+

This function initializes the WDOG. When called, the WDOG runs according to the configuration.

+

This is an example.

+
* wdog_config_t config;
+
* WDOG_GetDefaultConfig(&config);
+
* config.timeoutValue = 0xffU;
+
* config->interruptTimeValue = 0x04u;
+
* WDOG_Init(wdog_base,&config);
+
*
+
Parameters
+ + + +
baseWDOG peripheral base address
configThe configuration of WDOG
+
+
+ +
+
+ +
+
+ + + + + + + + +
void WDOG_Deinit (WDOG_Type * base)
+
+

This function shuts down the WDOG. Watchdog Enable bit is a write one once only bit. It is not possible to clear this bit by a software write, once the bit is set. This bit(WDE) can be set/reset only in debug mode(exception).

+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void WDOG_Enable (WDOG_Type * base)
+ 		+inlinestatic
+
+

This function writes a value into the WDOG_WCR register to enable the WDOG. This is a write one once only bit. It is not possible to clear this bit by a software write, once the bit is set. only debug mode exception.

+
Parameters
+ + +
baseWDOG peripheral base address
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void WDOG_Disable (WDOG_Type * base)
+ 		+inlinestatic
+
+

This function writes a value into the WDOG_WCR register to disable the WDOG. This is a write one once only bit. It is not possible to clear this bit by a software write,once the bit is set. only debug mode exception

+
Parameters
+ + +
baseWDOG peripheral base address
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void WDOG_TriggerSystemSoftwareReset (WDOG_Type * base)
+ 		+inlinestatic
+
+

This function will write to the WCR[SRS] bit to trigger a software system reset. This bit will automatically resets to "1" after it has been asserted to "0". Note: Calling this API will reset the system right now, please using it with more attention.

+
Parameters
+ + +
baseWDOG peripheral base address
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void WDOG_TriggerSoftwareSignal (WDOG_Type * base)
+ 		+inlinestatic
+
+

This function will write to the WCR[WDA] bit to trigger WDOG_B signal assertion. The WDOG_B signal can be routed to external pin of the chip, the output pin will turn to assertion along with WDOG_B signal. Note: The WDOG_B signal will remain assert until a power on reset occurred, so, please take more attention while calling it.

+
Parameters
+ + +
baseWDOG peripheral base address
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void WDOG_EnableInterrupts (WDOG_Type * base,
uint16_t mask 
)
+ 		+inlinestatic
+
+

This bit is a write once only bit. Once the software does a write access to this bit, it will get locked and cannot be reprogrammed until the next system reset assertion

+
Parameters
+ + + +
baseWDOG peripheral base address
maskThe interrupts to enable The parameter can be combination of the following source if defined.
    +
  • kWDOG_InterruptEnable
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t WDOG_GetStatusFlags (WDOG_Type * base)
+
+

This function gets all reset status flags.

+
* uint16_t status;
+
* status = WDOG_GetStatusFlags (wdog_base);
+
*
+
Parameters
+ + +
baseWDOG peripheral base address
+
+
+
Returns
State of the status flag: asserted (true) or not-asserted (false).
+
See Also
_wdog_status_flags
    +
  • true: a related status flag has been set.
    • +
  • false: a related status flag is not set.
    • +
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void WDOG_ClearInterruptStatus (WDOG_Type * base,
uint16_t mask 
)
+
+

This function clears the WDOG status flag.

+

This is an example for clearing the interrupt flag.

+
* WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag);
+
*
+
Parameters
+ + + +
baseWDOG peripheral base address
maskThe status flags to clear. The parameter could be any combination of the following values. kWDOG_TimeoutFlag
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void WDOG_SetTimeoutValue (WDOG_Type * base,
uint16_t timeoutCount 
)
+ 		+inlinestatic
+
+

This function sets the timeout value. This function writes a value into WCR registers. The time-out value can be written at any point of time but it is loaded to the counter at the time when WDOG is enabled or after the service routine has been performed.

+
Parameters
+ + + +
baseWDOG peripheral base address
timeoutCountWDOG timeout value; count of WDOG clock tick.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void WDOG_SetInterrputTimeoutValue (WDOG_Type * base,
uint16_t timeoutCount 
)
+ 		+inlinestatic
+
+

This function sets the interrupt count timeout value. This function writes a value into WIC registers which are wirte-once. This field is write once only. Once the software does a write access to this field, it will get locked and cannot be reprogrammed until the next system reset assertion.

+
Parameters
+ + + +
baseWDOG peripheral base address
timeoutCountWDOG timeout value; count of WDOG clock tick.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void WDOG_DisablePowerDownEnable (WDOG_Type * base)
+ 		+inlinestatic
+
+

This function disable the WDOG power down enable(PDE). This function writes a value into WMCR registers which are wirte-once. This field is write once only. Once software sets this bit it cannot be reset until the next system reset.

+
Parameters
+ + +
baseWDOG peripheral base address
+
+
+ +
+
+ +
+
+ + + + + + + + +
void WDOG_Refresh (WDOG_Type * base)
+
+

This function feeds the WDOG. This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted.

+
Parameters
+ + +
baseWDOG peripheral base address
+
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00022.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00022.js new file mode 100644 index 000000000..3ffafd7a7 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00022.js @@ -0,0 +1,43 @@ +var a00022 = +[ + [ "wdog_work_mode_t", "a00022.html#a00162", [ + [ "enableWait", "a00022.html#ac4c03e680f6c2070c50e9cbb7eae64fc", null ], + [ "enableStop", "a00022.html#a26f09db30cdfe918931fb6e2ea0545ad", null ], + [ "enableDebug", "a00022.html#ac46160e5425428c3f6b2bd7a9103539e", null ] + ] ], + [ "wdog_config_t", "a00022.html#a00161", [ + [ "enableWdog", "a00022.html#a871dc017463d6cc5d31121b40affa1a4", null ], + [ "workMode", "a00022.html#a52dd1d98958c48e0a342e3ffe9a1c351", null ], + [ "enableInterrupt", "a00022.html#aa749ba919bb8ddf9b52fda7781afa6b5", null ], + [ "timeoutValue", "a00022.html#a867555736162830ec456cb98b37431bf", null ], + [ "interruptTimeValue", "a00022.html#aac4e0165a8a5674bbd4ac8e7c32d7217", null ], + [ "softwareResetExtension", "a00022.html#aa698ca620c05feee0946ee91e1b3374f", null ], + [ "enablePowerDown", "a00022.html#a8596d41dfdb0d29a55dfee5e9d707d68", null ], + [ "enableTimeOutAssert", "a00022.html#a5e3f1a4dd09bde15aac1ca0e9ad16640", null ] + ] ], + [ "FSL_WDOG_DRIVER_VERSION", "a00022.html#ga5baa4ad349ae3c543938d4ee773df43e", null ], + [ "_wdog_interrupt_enable", "a00022.html#ga568a59a02c40c87ed791f569c68e3617", [ + [ "kWDOG_InterruptEnable", "a00022.html#gga568a59a02c40c87ed791f569c68e3617a8c358d55c0101eaa0a580d867572ec8d", null ] + ] ], + [ "_wdog_status_flags", "a00022.html#ga0b88468681d9540ae2932b8863df21da", [ + [ "kWDOG_RunningFlag", "a00022.html#gga0b88468681d9540ae2932b8863df21daa36d15132390c05315cadcd7531d16235", null ], + [ "kWDOG_PowerOnResetFlag", "a00022.html#gga0b88468681d9540ae2932b8863df21daac5e2f745cea700526fddf869bead3e7f", null ], + [ "kWDOG_TimeoutResetFlag", "a00022.html#gga0b88468681d9540ae2932b8863df21daa3e7218cabdb8b98afb859e5e5bb10c2b", null ], + [ "kWDOG_SoftwareResetFlag", "a00022.html#gga0b88468681d9540ae2932b8863df21daab8d3e9351b38a6c2070e168e794cbe04", null ], + [ "kWDOG_InterruptFlag", "a00022.html#gga0b88468681d9540ae2932b8863df21daac1277a2936555249acf7a516e6af1f78", null ] + ] ], + [ "WDOG_GetDefaultConfig", "a00022.html#gaad5ad72d4eaf90ade6be3c976e8bc3f7", null ], + [ "WDOG_Init", "a00022.html#ga50d46daf10ab46c6c696e8807c8e913b", null ], + [ "WDOG_Deinit", "a00022.html#gaa6667780dc3dcd9579f0689178c3b0d9", null ], + [ "WDOG_Enable", "a00022.html#gab4deee569751728b2bd3a74f3c51e51e", null ], + [ "WDOG_Disable", "a00022.html#gac50451a963f16a891a365df27305dcca", null ], + [ "WDOG_TriggerSystemSoftwareReset", "a00022.html#ga148420ea7de00bc3c60c40abffcdf1cb", null ], + [ "WDOG_TriggerSoftwareSignal", "a00022.html#gaedd7386f165e4750bc1aa72544122995", null ], + [ "WDOG_EnableInterrupts", "a00022.html#gac10aa3550c0824493f112a02ffd955b1", null ], + [ "WDOG_GetStatusFlags", "a00022.html#ga420a7d120956521faf8a40993014d6fa", null ], + [ "WDOG_ClearInterruptStatus", "a00022.html#ga45d1ddf1d8f4aeb8a87657f275050594", null ], + [ "WDOG_SetTimeoutValue", "a00022.html#ga7744339b66fc64cf4088f0a413e53b08", null ], + [ "WDOG_SetInterrputTimeoutValue", "a00022.html#ga18bcb8843c59834b6ae275c58fcf2cd3", null ], + [ "WDOG_DisablePowerDownEnable", "a00022.html#ga9c50304e7d819199df178ae26e12f1a8", null ], + [ "WDOG_Refresh", "a00022.html#ga1d307a7df8f2b926c306dc8714dda3f5", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00023.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00023.html new file mode 100644 index 000000000..2bbb0b846 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00023.html @@ -0,0 +1,367 @@ + + + + + + +MCUXpresso SDK API Reference Manual: WM8524 Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Typedefs | +Enumerations | +Functions
+
+
WM8524 Driver
CODEC Driver
+
+
+

Overview

+

The wm8524 driver provides a codec control interface.

+ + + + + +

+Data Structures

struct  wm8524_handle_t
 WM8524 handler. More...
 
+ + + + +

+Typedefs

typedef void(* wm8524_setMuteIO )(uint32_t output)
 < mute control io function pointer More...
 
+ + + + + + + +

+Enumerations

enum  wm8524_protocol_t {
+  kWM8524_ProtocolLeftJustified = 0x0, +
+  kWM8524_ProtocolI2S = 0x1, +
+  kWM8524_ProtocolRightJustified = 0x2 +
+ }
 The audio data transfer protocol. More...
 
enum  _wm8524_mute_control {
+  kWM8524_Mute = 0U, +
+  kWM8524_Unmute = 1U +
+ }
 wm8524 mute operation More...
 
+ + + + + + + + + + +

+Functions

status_t WM8524_Init (wm8524_handle_t *handle, wm8524_config_t *config)
 Initializes WM8524. More...
 
void WM8524_ConfigFormat (wm8524_handle_t *handle, wm8524_protocol_t protocol)
 Configure WM8524 audio protocol. More...
 
void WM8524_SetMute (wm8524_handle_t *handle, bool isMute)
 Sets the codec mute state. More...
 
+ + + + +

+Driver version

#define FSL_WM8524_DRIVER_VERSION   (MAKE_VERSION(2, 1, 1))
 WM8524 driver version 2.1.1. More...
 
+

Data Structure Documentation

+ +
+
+ + + + +
struct wm8524_handle_t
+
+
+ + + + +

Data Fields

+wm8524_config_t * config
 wm8524 config pointer
 
+ +
+
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_WM8524_DRIVER_VERSION   (MAKE_VERSION(2, 1, 1))
+
+ +
+
+

Typedef Documentation

+ +
+
+ + + + +
typedef void(* wm8524_setMuteIO)(uint32_t output)
+
+

format control io function pointer

+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum wm8524_protocol_t
+
+ + + + +
Enumerator
kWM8524_ProtocolLeftJustified  +

Left justified mode.

+
kWM8524_ProtocolI2S  +

I2S mode.

+
kWM8524_ProtocolRightJustified  +

Right justified mode.

+
+ +
+
+ +
+
+ + + + +
enum _wm8524_mute_control
+
+ + + +
Enumerator
kWM8524_Mute  +

mute left and right channel DAC

+
kWM8524_Unmute  +

unmute left and right channel DAC

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t WM8524_Init (wm8524_handle_t * handle,
wm8524_config_t * config 
)
+
+
Parameters
+ + + +
handleWM8524 handle structure.
configWM8524 configure structure.
+
+
+
Returns
kStatus_Success.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void WM8524_ConfigFormat (wm8524_handle_t * handle,
wm8524_protocol_t protocol 
)
+
+
Parameters
+ + + +
handleWM8524 handle structure.
protocolWM8524 configuration structure.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void WM8524_SetMute (wm8524_handle_t * handle,
bool isMute 
)
+
+
Parameters
+ + + +
handleWM8524 handle structure.
isMutetrue means mute, false means normal.
+
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00023.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00023.js new file mode 100644 index 000000000..b06ced4b9 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00023.js @@ -0,0 +1,20 @@ +var a00023 = +[ + [ "wm8524_handle_t", "a00023.html#a00163", [ + [ "config", "a00023.html#ab7cc533307c3f5d10e7d93efb80eb22e", null ] + ] ], + [ "FSL_WM8524_DRIVER_VERSION", "a00023.html#ga35fc5ea7698d930571d7917506e5afb0", null ], + [ "wm8524_setMuteIO", "a00023.html#gae893f953d0412d5fb817b5e83f08e369", null ], + [ "wm8524_protocol_t", "a00023.html#ga4d492c0ba01547cc26de876974a2dc52", [ + [ "kWM8524_ProtocolLeftJustified", "a00023.html#gga4d492c0ba01547cc26de876974a2dc52a152777862674dfd67279b569b4da746c", null ], + [ "kWM8524_ProtocolI2S", "a00023.html#gga4d492c0ba01547cc26de876974a2dc52a94e3c4c9585cdf8884371bd02bd543a3", null ], + [ "kWM8524_ProtocolRightJustified", "a00023.html#gga4d492c0ba01547cc26de876974a2dc52aacc3ffe41a38570ab30d73b809fc1612", null ] + ] ], + [ "_wm8524_mute_control", "a00023.html#gab747af4c7ae7ffd5cf60a8ffb7bdf60f", [ + [ "kWM8524_Mute", "a00023.html#ggab747af4c7ae7ffd5cf60a8ffb7bdf60fa57c1726acdf918943422558305cfd0d9", null ], + [ "kWM8524_Unmute", "a00023.html#ggab747af4c7ae7ffd5cf60a8ffb7bdf60fa9fcbc98f070eaeb7c99b037fa926ce59", null ] + ] ], + [ "WM8524_Init", "a00023.html#gafd9277c5ea97104ae693098801a31242", null ], + [ "WM8524_ConfigFormat", "a00023.html#ga27adb51025eae2b414cddd9cb45f87ce", null ], + [ "WM8524_SetMute", "a00023.html#gadafdeda642a54614ea97ef179623ecd3", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00085.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00085.html new file mode 100644 index 000000000..c221c2b5d --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00085.html @@ -0,0 +1,1770 @@ + + + + + + +MCUXpresso SDK API Reference Manual: IOMUXC: IOMUX Controller + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Files
+
+
IOMUXC: IOMUX Controller
+
+
+

Overview

+

IOMUXC driver provides APIs for pin configuration. It also supports the miscellaneous functions integrated in IOMUXC.

+ + + + +

+Files

file  fsl_iomuxc.h
 
+ + + + +

+Driver version

#define FSL_IOMUXC_DRIVER_VERSION   (MAKE_VERSION(2, 0, 1))
 IOMUXC driver version 2.0.1. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Pin function ID

The pin function ID is a tuple of <muxRegister muxMode inputRegister inputDaisy configRegister>

+
+#define IOMUXC_PMIC_STBY_REQ   0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
 
+#define IOMUXC_PMIC_ON_REQ   0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
 
+#define IOMUXC_ONOFF   0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
 
+#define IOMUXC_POR_B   0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
 
+#define IOMUXC_RTC_RESET_B   0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
 
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00   0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
 
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT   0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
 
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K   0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
 
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1   0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
 
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01   0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
 
+#define IOMUXC_GPIO1_IO01_PWM1_OUT   0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
 
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M   0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
 
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2   0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
 
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02   0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
 
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B   0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
 
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY   0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
 
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03   0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
 
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT   0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
 
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0   0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
 
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04   0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
 
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT   0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
 
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1   0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
 
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05   0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
 
+#define IOMUXC_GPIO1_IO05_M4_NMI   0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
 
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY   0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
 
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06   0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
 
+#define IOMUXC_GPIO1_IO06_ENET1_MDC   0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
 
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B   0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
 
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3   0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
 
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07   0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
 
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO   0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
 
+#define IOMUXC_GPIO1_IO07_USDHC1_WP   0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
 
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4   0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
 
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08   0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
 
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN   0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
 
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B   0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
 
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09   0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
 
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT   0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
 
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0   0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
 
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10   0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
 
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID   0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
 
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11   0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
 
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID   0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
 
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY   0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
 
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12   0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
 
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR   0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
 
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1   0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
 
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13   0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
 
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC   0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
 
+#define IOMUXC_GPIO1_IO13_PWM2_OUT   0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
 
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14   0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
 
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR   0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
 
+#define IOMUXC_GPIO1_IO14_PWM3_OUT   0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
 
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1   0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
 
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15   0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
 
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC   0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
 
+#define IOMUXC_GPIO1_IO15_PWM4_OUT   0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
 
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2   0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
 
+#define IOMUXC_ENET_MDC_ENET1_MDC   0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
 
+#define IOMUXC_ENET_MDC_GPIO1_IO16   0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
 
+#define IOMUXC_ENET_MDIO_ENET1_MDIO   0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
 
+#define IOMUXC_ENET_MDIO_GPIO1_IO17   0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
 
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
 
+#define IOMUXC_ENET_TD3_GPIO1_IO18   0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
 
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
 
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK   0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
 
+#define IOMUXC_ENET_TD2_GPIO1_IO19   0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
 
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
 
+#define IOMUXC_ENET_TD1_GPIO1_IO20   0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
 
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
 
+#define IOMUXC_ENET_TD0_GPIO1_IO21   0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
 
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL   0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
 
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22   0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
 
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
 
+#define IOMUXC_ENET_TXC_ENET1_TX_ER   0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
 
+#define IOMUXC_ENET_TXC_GPIO1_IO23   0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
 
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL   0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
 
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24   0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
 
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
 
+#define IOMUXC_ENET_RXC_ENET1_RX_ER   0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
 
+#define IOMUXC_ENET_RXC_GPIO1_IO25   0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
 
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
 
+#define IOMUXC_ENET_RD0_GPIO1_IO26   0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
 
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
 
+#define IOMUXC_ENET_RD1_GPIO1_IO27   0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
 
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
 
+#define IOMUXC_ENET_RD2_GPIO1_IO28   0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
 
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
 
+#define IOMUXC_ENET_RD3_GPIO1_IO29   0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
 
+#define IOMUXC_SD1_CLK_USDHC1_CLK   0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
 
+#define IOMUXC_SD1_CLK_GPIO2_IO00   0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
 
+#define IOMUXC_SD1_CMD_USDHC1_CMD   0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
 
+#define IOMUXC_SD1_CMD_GPIO2_IO01   0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
 
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0   0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
 
+#define IOMUXC_SD1_DATA0_GPIO2_IO02   0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
 
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1   0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
 
+#define IOMUXC_SD1_DATA1_GPIO2_IO03   0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
 
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2   0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
 
+#define IOMUXC_SD1_DATA2_GPIO2_IO04   0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
 
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3   0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
 
+#define IOMUXC_SD1_DATA3_GPIO2_IO05   0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
 
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4   0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
 
+#define IOMUXC_SD1_DATA4_GPIO2_IO06   0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
 
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5   0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
 
+#define IOMUXC_SD1_DATA5_GPIO2_IO07   0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
 
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6   0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
 
+#define IOMUXC_SD1_DATA6_GPIO2_IO08   0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
 
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7   0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
 
+#define IOMUXC_SD1_DATA7_GPIO2_IO09   0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
 
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B   0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
 
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10   0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
 
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE   0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
 
+#define IOMUXC_SD1_STROBE_GPIO2_IO11   0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
 
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B   0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
 
+#define IOMUXC_SD2_CD_B_GPIO2_IO12   0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
 
+#define IOMUXC_SD2_CLK_USDHC2_CLK   0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
 
+#define IOMUXC_SD2_CLK_GPIO2_IO13   0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
 
+#define IOMUXC_SD2_CMD_USDHC2_CMD   0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
 
+#define IOMUXC_SD2_CMD_GPIO2_IO14   0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
 
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0   0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
 
+#define IOMUXC_SD2_DATA0_GPIO2_IO15   0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
 
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1   0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
 
+#define IOMUXC_SD2_DATA1_GPIO2_IO16   0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
 
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2   0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
 
+#define IOMUXC_SD2_DATA2_GPIO2_IO17   0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
 
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3   0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
 
+#define IOMUXC_SD2_DATA3_GPIO2_IO18   0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
 
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B   0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
 
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19   0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
 
+#define IOMUXC_SD2_WP_USDHC2_WP   0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
 
+#define IOMUXC_SD2_WP_GPIO2_IO20   0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
 
+#define IOMUXC_NAND_ALE_RAWNAND_ALE   0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
 
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK   0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
 
+#define IOMUXC_NAND_ALE_GPIO3_IO00   0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
 
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B   0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
 
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B   0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
 
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01   0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
 
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B   0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
 
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B   0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
 
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02   0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
 
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B   0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
 
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B   0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
 
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03   0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
 
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B   0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
 
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B   0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
 
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04   0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
 
+#define IOMUXC_NAND_CLE_RAWNAND_CLE   0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
 
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK   0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
 
+#define IOMUXC_NAND_CLE_GPIO3_IO05   0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
 
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00   0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
 
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0   0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
 
+#define IOMUXC_NAND_DATA00_GPIO3_IO06   0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
 
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01   0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
 
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1   0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
 
+#define IOMUXC_NAND_DATA01_GPIO3_IO07   0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
 
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02   0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
 
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2   0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
 
+#define IOMUXC_NAND_DATA02_GPIO3_IO08   0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
 
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03   0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
 
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3   0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
 
+#define IOMUXC_NAND_DATA03_GPIO3_IO09   0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
 
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04   0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
 
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0   0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
 
+#define IOMUXC_NAND_DATA04_GPIO3_IO10   0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
 
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05   0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
 
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1   0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
 
+#define IOMUXC_NAND_DATA05_GPIO3_IO11   0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
 
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06   0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
 
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2   0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
 
+#define IOMUXC_NAND_DATA06_GPIO3_IO12   0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
 
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07   0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
 
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3   0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
 
+#define IOMUXC_NAND_DATA07_GPIO3_IO13   0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
 
+#define IOMUXC_NAND_DQS_RAWNAND_DQS   0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
 
+#define IOMUXC_NAND_DQS_QSPI_A_DQS   0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
 
+#define IOMUXC_NAND_DQS_GPIO3_IO14   0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
 
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B   0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
 
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS   0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
 
+#define IOMUXC_NAND_RE_B_GPIO3_IO15   0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
 
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B   0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
 
+#define IOMUXC_NAND_READY_B_GPIO3_IO16   0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
 
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B   0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
 
+#define IOMUXC_NAND_WE_B_GPIO3_IO17   0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
 
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B   0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
 
+#define IOMUXC_NAND_WP_B_GPIO3_IO18   0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
 
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC   0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
 
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0   0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
 
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19   0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
 
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK   0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
 
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1   0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
 
+#define IOMUXC_SAI5_RXC_GPIO3_IO20   0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
 
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0   0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
 
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2   0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
 
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21   0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
 
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1   0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
 
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3   0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
 
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC   0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
 
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC   0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
 
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22   0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
 
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2   0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
 
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4   0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
 
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC   0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
 
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK   0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
 
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23   0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
 
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3   0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
 
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5   0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
 
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC   0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
 
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0   0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
 
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24   0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
 
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK   0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
 
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK   0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
 
+#define IOMUXC_SAI5_MCLK_SAI4_MCLK   0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0
 
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25   0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
 
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC   0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
 
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC   0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
 
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK   0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
 
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00   0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
 
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK   0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
 
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK   0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
 
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL   0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
 
+#define IOMUXC_SAI1_RXC_GPIO4_IO01   0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
 
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0   0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
 
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0   0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
 
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0   0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
 
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02   0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
 
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0   0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
 
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1   0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
 
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1   0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
 
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1   0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
 
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03   0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
 
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1   0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
 
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2   0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
 
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2   0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
 
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2   0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
 
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04   0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
 
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2   0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
 
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3   0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
 
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3   0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
 
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3   0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
 
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05   0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
 
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3   0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
 
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4   0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
 
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK   0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
 
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK   0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
 
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4   0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
 
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06   0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
 
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4   0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
 
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5   0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
 
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0   0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
 
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0   0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
 
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC   0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
 
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5   0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
 
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07   0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
 
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5   0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
 
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6   0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
 
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC   0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
 
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC   0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
 
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6   0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
 
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08   0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
 
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6   0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
 
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7   0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
 
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK   0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
 
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC   0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
 
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4   0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
 
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7   0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
 
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09   0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
 
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7   0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
 
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC   0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
 
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC   0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
 
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO   0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
 
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10   0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
 
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK   0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
 
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK   0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
 
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI   0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
 
+#define IOMUXC_SAI1_TXC_GPIO4_IO11   0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
 
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0   0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
 
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0   0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
 
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8   0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
 
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12   0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
 
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8   0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
 
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1   0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
 
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1   0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
 
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9   0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
 
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13   0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
 
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9   0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
 
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2   0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
 
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2   0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
 
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10   0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
 
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14   0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
 
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10   0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
 
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3   0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
 
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3   0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
 
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11   0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
 
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15   0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
 
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11   0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
 
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4   0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
 
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK   0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
 
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK   0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
 
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12   0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
 
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16   0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
 
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12   0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
 
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5   0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
 
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0   0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
 
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0   0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
 
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13   0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
 
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17   0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
 
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13   0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
 
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6   0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
 
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC   0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
 
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC   0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
 
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14   0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
 
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18   0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
 
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14   0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
 
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7   0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
 
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK   0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
 
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15   0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
 
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19   0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
 
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15   0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
 
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK   0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
 
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK   0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
 
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK   0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
 
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20   0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
 
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC   0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
 
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC   0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
 
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21   0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
 
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK   0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
 
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK   0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
 
+#define IOMUXC_SAI2_RXC_GPIO4_IO22   0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
 
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0   0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
 
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0   0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
 
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23   0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
 
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC   0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
 
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1   0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
 
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24   0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
 
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK   0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
 
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2   0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
 
+#define IOMUXC_SAI2_TXC_GPIO4_IO25   0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
 
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0   0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
 
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3   0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
 
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26   0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
 
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK   0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
 
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK   0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
 
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27   0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
 
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC   0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
 
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1   0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
 
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC   0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
 
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28   0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
 
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK   0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
 
+#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2   0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
 
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK   0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
 
+#define IOMUXC_SAI3_RXC_GPIO4_IO29   0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
 
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0   0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
 
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1   0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
 
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0   0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
 
+#define IOMUXC_SAI3_RXD_GPIO4_IO30   0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
 
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC   0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
 
+#define IOMUXC_SAI3_TXFS_GPT1_CLK   0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
 
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1   0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
 
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31   0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
 
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK   0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
 
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2   0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
 
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2   0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
 
+#define IOMUXC_SAI3_TXC_GPIO5_IO00   0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
 
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0   0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
 
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3   0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
 
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3   0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
 
+#define IOMUXC_SAI3_TXD_GPIO5_IO01   0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
 
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK   0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
 
+#define IOMUXC_SAI3_MCLK_PWM4_OUT   0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
 
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK   0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
 
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02   0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
 
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT   0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
 
+#define IOMUXC_SPDIF_TX_PWM3_OUT   0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
 
+#define IOMUXC_SPDIF_TX_GPIO5_IO03   0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
 
+#define IOMUXC_SPDIF_RX_SPDIF1_IN   0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
 
+#define IOMUXC_SPDIF_RX_PWM2_OUT   0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
 
+#define IOMUXC_SPDIF_RX_GPIO5_IO04   0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
 
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK   0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
 
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT   0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
 
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05   0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
 
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK   0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
 
+#define IOMUXC_ECSPI1_SCLK_UART3_RX   0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
 
+#define IOMUXC_ECSPI1_SCLK_UART3_TX   0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
 
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06   0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
 
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI   0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
 
+#define IOMUXC_ECSPI1_MOSI_UART3_TX   0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
 
+#define IOMUXC_ECSPI1_MOSI_UART3_RX   0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
 
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07   0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
 
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO   0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
 
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B   0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
 
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B   0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
 
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08   0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
 
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0   0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
 
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B   0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
 
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B   0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
 
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09   0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
 
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK   0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
 
+#define IOMUXC_ECSPI2_SCLK_UART4_RX   0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
 
+#define IOMUXC_ECSPI2_SCLK_UART4_TX   0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
 
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10   0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
 
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI   0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
 
+#define IOMUXC_ECSPI2_MOSI_UART4_TX   0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
 
+#define IOMUXC_ECSPI2_MOSI_UART4_RX   0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
 
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11   0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
 
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO   0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
 
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B   0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
 
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B   0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
 
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12   0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
 
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0   0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
 
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B   0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
 
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B   0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
 
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13   0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
 
+#define IOMUXC_I2C1_SCL_I2C1_SCL   0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
 
+#define IOMUXC_I2C1_SCL_ENET1_MDC   0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
 
+#define IOMUXC_I2C1_SCL_GPIO5_IO14   0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
 
+#define IOMUXC_I2C1_SDA_I2C1_SDA   0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
 
+#define IOMUXC_I2C1_SDA_ENET1_MDIO   0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
 
+#define IOMUXC_I2C1_SDA_GPIO5_IO15   0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
 
+#define IOMUXC_I2C2_SCL_I2C2_SCL   0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
 
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN   0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
 
+#define IOMUXC_I2C2_SCL_GPIO5_IO16   0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
 
+#define IOMUXC_I2C2_SDA_I2C2_SDA   0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
 
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT   0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
 
+#define IOMUXC_I2C2_SDA_GPIO5_IO17   0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
 
+#define IOMUXC_I2C3_SCL_I2C3_SCL   0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
 
+#define IOMUXC_I2C3_SCL_PWM4_OUT   0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
 
+#define IOMUXC_I2C3_SCL_GPT2_CLK   0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
 
+#define IOMUXC_I2C3_SCL_GPIO5_IO18   0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
 
+#define IOMUXC_I2C3_SDA_I2C3_SDA   0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
 
+#define IOMUXC_I2C3_SDA_PWM3_OUT   0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
 
+#define IOMUXC_I2C3_SDA_GPT3_CLK   0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
 
+#define IOMUXC_I2C3_SDA_GPIO5_IO19   0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
 
+#define IOMUXC_I2C4_SCL_I2C4_SCL   0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
 
+#define IOMUXC_I2C4_SCL_PWM2_OUT   0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
 
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B   0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
 
+#define IOMUXC_I2C4_SCL_GPIO5_IO20   0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
 
+#define IOMUXC_I2C4_SDA_I2C4_SDA   0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
 
+#define IOMUXC_I2C4_SDA_PWM1_OUT   0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
 
+#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B   0x30330230, 0x2, 0x30330528, 0x0, 0x30330498
 
+#define IOMUXC_I2C4_SDA_GPIO5_IO21   0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
 
+#define IOMUXC_UART1_RXD_UART1_RX   0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
 
+#define IOMUXC_UART1_RXD_UART1_TX   0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
 
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK   0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
 
+#define IOMUXC_UART1_RXD_GPIO5_IO22   0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
 
+#define IOMUXC_UART1_TXD_UART1_TX   0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
 
+#define IOMUXC_UART1_TXD_UART1_RX   0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
 
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI   0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
 
+#define IOMUXC_UART1_TXD_GPIO5_IO23   0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
 
+#define IOMUXC_UART2_RXD_UART2_RX   0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
 
+#define IOMUXC_UART2_RXD_UART2_TX   0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
 
+#define IOMUXC_UART2_RXD_ECSPI3_MISO   0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
 
+#define IOMUXC_UART2_RXD_GPIO5_IO24   0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
 
+#define IOMUXC_UART2_TXD_UART2_TX   0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
 
+#define IOMUXC_UART2_TXD_UART2_RX   0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
 
+#define IOMUXC_UART2_TXD_ECSPI3_SS0   0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
 
+#define IOMUXC_UART2_TXD_GPIO5_IO25   0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
 
+#define IOMUXC_UART3_RXD_UART3_RX   0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
 
+#define IOMUXC_UART3_RXD_UART3_TX   0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
 
+#define IOMUXC_UART3_RXD_UART1_CTS_B   0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
 
+#define IOMUXC_UART3_RXD_UART1_RTS_B   0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
 
+#define IOMUXC_UART3_RXD_GPIO5_IO26   0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
 
+#define IOMUXC_UART3_TXD_UART3_TX   0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
 
+#define IOMUXC_UART3_TXD_UART3_RX   0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
 
+#define IOMUXC_UART3_TXD_UART1_RTS_B   0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
 
+#define IOMUXC_UART3_TXD_UART1_CTS_B   0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
 
+#define IOMUXC_UART3_TXD_GPIO5_IO27   0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
 
+#define IOMUXC_UART4_RXD_UART4_RX   0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
 
+#define IOMUXC_UART4_RXD_UART4_TX   0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
 
+#define IOMUXC_UART4_RXD_UART2_CTS_B   0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
 
+#define IOMUXC_UART4_RXD_UART2_RTS_B   0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
 
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B   0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
 
+#define IOMUXC_UART4_RXD_GPIO5_IO28   0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
 
+#define IOMUXC_UART4_TXD_UART4_TX   0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
 
+#define IOMUXC_UART4_TXD_UART4_RX   0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
 
+#define IOMUXC_UART4_TXD_UART2_RTS_B   0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
 
+#define IOMUXC_UART4_TXD_UART2_CTS_B   0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
 
+#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B   0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8
 
+#define IOMUXC_UART4_TXD_GPIO5_IO29   0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
 
+#define IOMUXC_TEST_MODE   0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
 
+#define IOMUXC_BOOT_MODE0   0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
 
+#define IOMUXC_BOOT_MODE1   0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
 
+#define IOMUXC_JTAG_MOD   0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
 
+#define IOMUXC_JTAG_TRST_B   0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
 
+#define IOMUXC_JTAG_TDI   0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
 
+#define IOMUXC_JTAG_TMS   0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
 
+#define IOMUXC_JTAG_TCK   0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
 
+#define IOMUXC_JTAG_TDO   0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
 
+#define IOMUXC_RTC   0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
 
+ + + + + + + +

+Configuration

static void IOMUXC_SetPinMux (uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t inputOnfield)
 Sets the IOMUXC pin mux mode. More...
 
static void IOMUXC_SetPinConfig (uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t configValue)
 Sets the IOMUXC pin configuration. More...
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_IOMUXC_DRIVER_VERSION   (MAKE_VERSION(2, 0, 1))
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
static void IOMUXC_SetPinMux (uint32_t muxRegister,
uint32_t muxMode,
uint32_t inputRegister,
uint32_t inputDaisy,
uint32_t configRegister,
uint32_t inputOnfield 
)
+ 		+inlinestatic
+
+
Note
The first five parameters can be filled with the pin function ID macros.
+

This is an example to set the I2C4_SDA as the pwm1_OUT:

+
* IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+
*
+
Parameters
+ + + + + + + +
muxRegisterThe pin mux register_
muxModeThe pin mux mode_
inputRegisterThe select input register_
inputDaisyThe input daisy_
configRegisterThe config register_
inputOnfieldThe pad->module input inversion_
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
static void IOMUXC_SetPinConfig (uint32_t muxRegister,
uint32_t muxMode,
uint32_t inputRegister,
uint32_t inputDaisy,
uint32_t configRegister,
uint32_t configValue 
)
+ 		+inlinestatic
+
+
Note
The previous five parameters can be filled with the pin function ID macros.
+

This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:

+
* IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+
*
+
Parameters
+ + + + + + + +
muxRegisterThe pin mux register_
muxModeThe pin mux mode_
inputRegisterThe select input register_
inputDaisyThe input daisy_
configRegisterThe config register_
configValueThe pin config value_
+
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00085.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00085.js new file mode 100644 index 000000000..624a47a78 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00085.js @@ -0,0 +1,6 @@ +var a00085 = +[ + [ "FSL_IOMUXC_DRIVER_VERSION", "a00085.html#gaa82996f29b9fa7947fdc478b7a874757", null ], + [ "IOMUXC_SetPinMux", "a00085.html#gaff65bf655b0d541b868b4a9d15415ce8", null ], + [ "IOMUXC_SetPinConfig", "a00085.html#gab7a6f9e42bd00d9e80457b53712748de", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00086.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00086.html new file mode 100644 index 000000000..4fa1b24ba --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00086.html @@ -0,0 +1,1181 @@ + + + + + + +MCUXpresso SDK API Reference Manual: Common Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Typedefs | +Enumerations | +Functions
+
+
Common Driver
+
+
+

Overview

+

The MCUXpresso SDK provides a driver for the common module of MCUXpresso SDK devices.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ   1
 Macro to use the default weak IRQ handler in drivers. More...
 
#define MAKE_STATUS(group, code)   ((((group)*100) + (code)))
 Construct a status code value from a group and code number. More...
 
#define MAKE_VERSION(major, minor, bugfix)   (((major) << 16) | ((minor) << 8) | (bugfix))
 Construct the version number for drivers. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE   0U
 No debug console. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_UART   1U
 Debug console based on UART. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART   2U
 Debug console based on LPUART. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI   3U
 Debug console based on LPSCI. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC   4U
 Debug console based on USBCDC. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM   5U
 Debug console based on FLEXCOMM. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART   6U
 Debug console based on i.MX UART. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART   7U
 Debug console based on LPC_VUSART. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART   8U
 Debug console based on LPC_USART. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO   9U
 Debug console based on SWO. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI   10U
 Debug console based on QSCI. More...
 
#define ARRAY_SIZE(x)   (sizeof(x) / sizeof((x)[0]))
 Computes the number of elements in an array. More...
 
+ + + + +

+Typedefs

typedef int32_t status_t
 Type used for all status and error return values. More...
 
+ + + + + + + +

+Enumerations

enum  _status_groups {
+  kStatusGroup_Generic = 0, +
+  kStatusGroup_FLASH = 1, +
+  kStatusGroup_LPSPI = 4, +
+  kStatusGroup_FLEXIO_SPI = 5, +
+  kStatusGroup_DSPI = 6, +
+  kStatusGroup_FLEXIO_UART = 7, +
+  kStatusGroup_FLEXIO_I2C = 8, +
+  kStatusGroup_LPI2C = 9, +
+  kStatusGroup_UART = 10, +
+  kStatusGroup_I2C = 11, +
+  kStatusGroup_LPSCI = 12, +
+  kStatusGroup_LPUART = 13, +
+  kStatusGroup_SPI = 14, +
+  kStatusGroup_XRDC = 15, +
+  kStatusGroup_SEMA42 = 16, +
+  kStatusGroup_SDHC = 17, +
+  kStatusGroup_SDMMC = 18, +
+  kStatusGroup_SAI = 19, +
+  kStatusGroup_MCG = 20, +
+  kStatusGroup_SCG = 21, +
+  kStatusGroup_SDSPI = 22, +
+  kStatusGroup_FLEXIO_I2S = 23, +
+  kStatusGroup_FLEXIO_MCULCD = 24, +
+  kStatusGroup_FLASHIAP = 25, +
+  kStatusGroup_FLEXCOMM_I2C = 26, +
+  kStatusGroup_I2S = 27, +
+  kStatusGroup_IUART = 28, +
+  kStatusGroup_CSI = 29, +
+  kStatusGroup_MIPI_DSI = 30, +
+  kStatusGroup_SDRAMC = 35, +
+  kStatusGroup_POWER = 39, +
+  kStatusGroup_ENET = 40, +
+  kStatusGroup_PHY = 41, +
+  kStatusGroup_TRGMUX = 42, +
+  kStatusGroup_SMARTCARD = 43, +
+  kStatusGroup_LMEM = 44, +
+  kStatusGroup_QSPI = 45, +
+  kStatusGroup_DMA = 50, +
+  kStatusGroup_EDMA = 51, +
+  kStatusGroup_DMAMGR = 52, +
+  kStatusGroup_FLEXCAN = 53, +
+  kStatusGroup_LTC = 54, +
+  kStatusGroup_FLEXIO_CAMERA = 55, +
+  kStatusGroup_LPC_SPI = 56, +
+  kStatusGroup_LPC_USART = 57, +
+  kStatusGroup_DMIC = 58, +
+  kStatusGroup_SDIF = 59, +
+  kStatusGroup_SPIFI = 60, +
+  kStatusGroup_OTP = 61, +
+  kStatusGroup_MCAN = 62, +
+  kStatusGroup_CAAM = 63, +
+  kStatusGroup_ECSPI = 64, +
+  kStatusGroup_USDHC = 65, +
+  kStatusGroup_LPC_I2C = 66, +
+  kStatusGroup_DCP = 67, +
+  kStatusGroup_MSCAN = 68, +
+  kStatusGroup_ESAI = 69, +
+  kStatusGroup_FLEXSPI = 70, +
+  kStatusGroup_MMDC = 71, +
+  kStatusGroup_PDM = 72, +
+  kStatusGroup_SDMA = 73, +
+  kStatusGroup_ICS = 74, +
+  kStatusGroup_SPDIF = 75, +
+  kStatusGroup_LPC_MINISPI = 76, +
+  kStatusGroup_HASHCRYPT = 77, +
+  kStatusGroup_LPC_SPI_SSP = 78, +
+  kStatusGroup_I3C = 79, +
+  kStatusGroup_LPC_I2C_1 = 97, +
+  kStatusGroup_NOTIFIER = 98, +
+  kStatusGroup_DebugConsole = 99, +
+  kStatusGroup_SEMC = 100, +
+  kStatusGroup_ApplicationRangeStart = 101, +
+  kStatusGroup_IAP = 102, +
+  kStatusGroup_SFA = 103, +
+  kStatusGroup_SPC = 104, +
+  kStatusGroup_PUF = 105, +
+  kStatusGroup_TOUCH_PANEL = 106, +
+  kStatusGroup_HAL_GPIO = 121, +
+  kStatusGroup_HAL_UART = 122, +
+  kStatusGroup_HAL_TIMER = 123, +
+  kStatusGroup_HAL_SPI = 124, +
+  kStatusGroup_HAL_I2C = 125, +
+  kStatusGroup_HAL_FLASH = 126, +
+  kStatusGroup_HAL_PWM = 127, +
+  kStatusGroup_HAL_RNG = 128, +
+  kStatusGroup_TIMERMANAGER = 135, +
+  kStatusGroup_SERIALMANAGER = 136, +
+  kStatusGroup_LED = 137, +
+  kStatusGroup_BUTTON = 138, +
+  kStatusGroup_EXTERN_EEPROM = 139, +
+  kStatusGroup_SHELL = 140, +
+  kStatusGroup_MEM_MANAGER = 141, +
+  kStatusGroup_LIST = 142, +
+  kStatusGroup_OSA = 143, +
+  kStatusGroup_COMMON_TASK = 144, +
+  kStatusGroup_MSG = 145, +
+  kStatusGroup_SDK_OCOTP = 146, +
+  kStatusGroup_SDK_FLEXSPINOR = 147, +
+  kStatusGroup_CODEC = 148, +
+  kStatusGroup_ASRC = 149, +
+  kStatusGroup_OTFAD = 150, +
+  kStatusGroup_SDIOSLV = 151, +
+  kStatusGroup_MECC = 152, +
+  kStatusGroup_ENET_QOS = 153, +
+  kStatusGroup_LOG = 154, +
+  kStatusGroup_I3CBUS = 155, +
+  kStatusGroup_QSCI = 156, +
+  kStatusGroup_SNT = 157 +
+ }
 Status group numbers. More...
 
enum  {
+  kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), +
+  kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), +
+  kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), +
+  kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), +
+  kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), +
+  kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), +
+  kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +
+  kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7) +
+ }
 Generic status return codes. More...
 
+ + + + + + + + + + +

+Functions

void * SDK_Malloc (size_t size, size_t alignbytes)
 Allocate memory with given alignment and aligned size. More...
 
void SDK_Free (void *ptr)
 Free memory. More...
 
void SDK_DelayAtLeastUs (uint32_t delayTime_us, uint32_t coreClock_Hz)
 Delay at least for some time. More...
 
+ + + + +

+Driver version

#define FSL_COMMON_DRIVER_VERSION   (MAKE_VERSION(2, 3, 0))
 common driver version. More...
 
+ + + + + +

+Min/max macros

+#define MIN(a, b)   (((a) < (b)) ? (a) : (b))
 
+#define MAX(a, b)   (((a) > (b)) ? (a) : (b))
 
+ + + + + +

+UINT16_MAX/UINT32_MAX value

+#define UINT16_MAX   ((uint16_t)-1)
 
+#define UINT32_MAX   ((uint32_t)-1)
 
+ + + +

+Suppress fallthrough warning macro

+#define SUPPRESS_FALL_THROUGH_WARNING()
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ   1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MAKE_STATUS( group,
 code 
)   ((((group)*100) + (code)))
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MAKE_VERSION( major,
 minor,
 bugfix 
)   (((major) << 16) | ((minor) << 8) | (bugfix))
+
+ +
+
+ +
+
+ + + + +
#define FSL_COMMON_DRIVER_VERSION   (MAKE_VERSION(2, 3, 0))
+
+ +
+
+ +
+
+ + + + +
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE   0U
+
+ +
+
+ +
+
+ + + + +
#define DEBUG_CONSOLE_DEVICE_TYPE_UART   1U
+
+ +
+
+ +
+
+ + + + +
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART   2U
+
+ +
+
+ +
+
+ + + + +
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI   3U
+
+ +
+
+ +
+
+ + + + +
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC   4U
+
+ +
+
+ +
+
+ + + + +
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM   5U
+
+ +
+
+ +
+
+ + + + +
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART   6U
+
+ +
+
+ +
+
+ + + + +
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART   7U
+
+ +
+
+ +
+
+ + + + +
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART   8U
+
+ +
+
+ +
+
+ + + + +
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO   9U
+
+ +
+
+ +
+
+ + + + +
#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI   10U
+
+ +
+
+ +
+
+ + + + + + + + +
#define ARRAY_SIZE( x)   (sizeof(x) / sizeof((x)[0]))
+
+ +
+
+

Typedef Documentation

+ +
+
+ + + + +
typedef int32_t status_t
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum _status_groups
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enumerator
kStatusGroup_Generic  +

Group number for generic status codes.

+
kStatusGroup_FLASH  +

Group number for FLASH status codes.

+
kStatusGroup_LPSPI  +

Group number for LPSPI status codes.

+
kStatusGroup_FLEXIO_SPI  +

Group number for FLEXIO SPI status codes.

+
kStatusGroup_DSPI  +

Group number for DSPI status codes.

+
kStatusGroup_FLEXIO_UART  +

Group number for FLEXIO UART status codes.

+
kStatusGroup_FLEXIO_I2C  +

Group number for FLEXIO I2C status codes.

+
kStatusGroup_LPI2C  +

Group number for LPI2C status codes.

+
kStatusGroup_UART  +

Group number for UART status codes.

+
kStatusGroup_I2C  +

Group number for UART status codes.

+
kStatusGroup_LPSCI  +

Group number for LPSCI status codes.

+
kStatusGroup_LPUART  +

Group number for LPUART status codes.

+
kStatusGroup_SPI  +

Group number for SPI status code.

+
kStatusGroup_XRDC  +

Group number for XRDC status code.

+
kStatusGroup_SEMA42  +

Group number for SEMA42 status code.

+
kStatusGroup_SDHC  +

Group number for SDHC status code.

+
kStatusGroup_SDMMC  +

Group number for SDMMC status code.

+
kStatusGroup_SAI  +

Group number for SAI status code.

+
kStatusGroup_MCG  +

Group number for MCG status codes.

+
kStatusGroup_SCG  +

Group number for SCG status codes.

+
kStatusGroup_SDSPI  +

Group number for SDSPI status codes.

+
kStatusGroup_FLEXIO_I2S  +

Group number for FLEXIO I2S status codes.

+
kStatusGroup_FLEXIO_MCULCD  +

Group number for FLEXIO LCD status codes.

+
kStatusGroup_FLASHIAP  +

Group number for FLASHIAP status codes.

+
kStatusGroup_FLEXCOMM_I2C  +

Group number for FLEXCOMM I2C status codes.

+
kStatusGroup_I2S  +

Group number for I2S status codes.

+
kStatusGroup_IUART  +

Group number for IUART status codes.

+
kStatusGroup_CSI  +

Group number for CSI status codes.

+
kStatusGroup_MIPI_DSI  +

Group number for MIPI DSI status codes.

+
kStatusGroup_SDRAMC  +

Group number for SDRAMC status codes.

+
kStatusGroup_POWER  +

Group number for POWER status codes.

+
kStatusGroup_ENET  +

Group number for ENET status codes.

+
kStatusGroup_PHY  +

Group number for PHY status codes.

+
kStatusGroup_TRGMUX  +

Group number for TRGMUX status codes.

+
kStatusGroup_SMARTCARD  +

Group number for SMARTCARD status codes.

+
kStatusGroup_LMEM  +

Group number for LMEM status codes.

+
kStatusGroup_QSPI  +

Group number for QSPI status codes.

+
kStatusGroup_DMA  +

Group number for DMA status codes.

+
kStatusGroup_EDMA  +

Group number for EDMA status codes.

+
kStatusGroup_DMAMGR  +

Group number for DMAMGR status codes.

+
kStatusGroup_FLEXCAN  +

Group number for FlexCAN status codes.

+
kStatusGroup_LTC  +

Group number for LTC status codes.

+
kStatusGroup_FLEXIO_CAMERA  +

Group number for FLEXIO CAMERA status codes.

+
kStatusGroup_LPC_SPI  +

Group number for LPC_SPI status codes.

+
kStatusGroup_LPC_USART  +

Group number for LPC_USART status codes.

+
kStatusGroup_DMIC  +

Group number for DMIC status codes.

+
kStatusGroup_SDIF  +

Group number for SDIF status codes.

+
kStatusGroup_SPIFI  +

Group number for SPIFI status codes.

+
kStatusGroup_OTP  +

Group number for OTP status codes.

+
kStatusGroup_MCAN  +

Group number for MCAN status codes.

+
kStatusGroup_CAAM  +

Group number for CAAM status codes.

+
kStatusGroup_ECSPI  +

Group number for ECSPI status codes.

+
kStatusGroup_USDHC  +

Group number for USDHC status codes.

+
kStatusGroup_LPC_I2C  +

Group number for LPC_I2C status codes.

+
kStatusGroup_DCP  +

Group number for DCP status codes.

+
kStatusGroup_MSCAN  +

Group number for MSCAN status codes.

+
kStatusGroup_ESAI  +

Group number for ESAI status codes.

+
kStatusGroup_FLEXSPI  +

Group number for FLEXSPI status codes.

+
kStatusGroup_MMDC  +

Group number for MMDC status codes.

+
kStatusGroup_PDM  +

Group number for MIC status codes.

+
kStatusGroup_SDMA  +

Group number for SDMA status codes.

+
kStatusGroup_ICS  +

Group number for ICS status codes.

+
kStatusGroup_SPDIF  +

Group number for SPDIF status codes.

+
kStatusGroup_LPC_MINISPI  +

Group number for LPC_MINISPI status codes.

+
kStatusGroup_HASHCRYPT  +

Group number for Hashcrypt status codes.

+
kStatusGroup_LPC_SPI_SSP  +

Group number for LPC_SPI_SSP status codes.

+
kStatusGroup_I3C  +

Group number for I3C status codes.

+
kStatusGroup_LPC_I2C_1  +

Group number for LPC_I2C_1 status codes.

+
kStatusGroup_NOTIFIER  +

Group number for NOTIFIER status codes.

+
kStatusGroup_DebugConsole  +

Group number for debug console status codes.

+
kStatusGroup_SEMC  +

Group number for SEMC status codes.

+
kStatusGroup_ApplicationRangeStart  +

Starting number for application groups.

+
kStatusGroup_IAP  +

Group number for IAP status codes.

+
kStatusGroup_SFA  +

Group number for SFA status codes.

+
kStatusGroup_SPC  +

Group number for SPC status codes.

+
kStatusGroup_PUF  +

Group number for PUF status codes.

+
kStatusGroup_TOUCH_PANEL  +

Group number for touch panel status codes.

+
kStatusGroup_HAL_GPIO  +

Group number for HAL GPIO status codes.

+
kStatusGroup_HAL_UART  +

Group number for HAL UART status codes.

+
kStatusGroup_HAL_TIMER  +

Group number for HAL TIMER status codes.

+
kStatusGroup_HAL_SPI  +

Group number for HAL SPI status codes.

+
kStatusGroup_HAL_I2C  +

Group number for HAL I2C status codes.

+
kStatusGroup_HAL_FLASH  +

Group number for HAL FLASH status codes.

+
kStatusGroup_HAL_PWM  +

Group number for HAL PWM status codes.

+
kStatusGroup_HAL_RNG  +

Group number for HAL RNG status codes.

+
kStatusGroup_TIMERMANAGER  +

Group number for TiMER MANAGER status codes.

+
kStatusGroup_SERIALMANAGER  +

Group number for SERIAL MANAGER status codes.

+
kStatusGroup_LED  +

Group number for LED status codes.

+
kStatusGroup_BUTTON  +

Group number for BUTTON status codes.

+
kStatusGroup_EXTERN_EEPROM  +

Group number for EXTERN EEPROM status codes.

+
kStatusGroup_SHELL  +

Group number for SHELL status codes.

+
kStatusGroup_MEM_MANAGER  +

Group number for MEM MANAGER status codes.

+
kStatusGroup_LIST  +

Group number for List status codes.

+
kStatusGroup_OSA  +

Group number for OSA status codes.

+
kStatusGroup_COMMON_TASK  +

Group number for Common task status codes.

+
kStatusGroup_MSG  +

Group number for messaging status codes.

+
kStatusGroup_SDK_OCOTP  +

Group number for OCOTP status codes.

+
kStatusGroup_SDK_FLEXSPINOR  +

Group number for FLEXSPINOR status codes.

+
kStatusGroup_CODEC  +

Group number for codec status codes.

+
kStatusGroup_ASRC  +

Group number for codec status ASRC.

+
kStatusGroup_OTFAD  +

Group number for codec status codes.

+
kStatusGroup_SDIOSLV  +

Group number for SDIOSLV status codes.

+
kStatusGroup_MECC  +

Group number for MECC status codes.

+
kStatusGroup_ENET_QOS  +

Group number for ENET_QOS status codes.

+
kStatusGroup_LOG  +

Group number for LOG status codes.

+
kStatusGroup_I3CBUS  +

Group number for I3CBUS status codes.

+
kStatusGroup_QSCI  +

Group number for QSCI status codes.

+
kStatusGroup_SNT  +

Group number for SNT status codes.

+
+ +
+
+ +
+
+ + + + +
anonymous enum
+
+ + + + + + + + + +
Enumerator
kStatus_Success  +

Generic status for Success.

+
kStatus_Fail  +

Generic status for Fail.

+
kStatus_ReadOnly  +

Generic status for read only failure.

+
kStatus_OutOfRange  +

Generic status for out of range access.

+
kStatus_InvalidArgument  +

Generic status for invalid argument check.

+
kStatus_Timeout  +

Generic status for timeout.

+
kStatus_NoTransferInProgress  +

Generic status for no transfer in progress.

+
kStatus_Busy  +

Generic status for module is busy.

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void* SDK_Malloc (size_t size,
size_t alignbytes 
)
+
+

This is provided to support the dynamically allocated memory used in cache-able region.

+
Parameters
+ + + +
sizeThe length required to malloc.
alignbytesThe alignment size.
+
+
+
Return values
+ + +
Theallocated memory.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDK_Free (void * ptr)
+
+
Parameters
+ + +
ptrThe memory to be release.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SDK_DelayAtLeastUs (uint32_t delayTime_us,
uint32_t coreClock_Hz 
)
+
+

Please note that, this API uses while loop for delay, different run-time environments make the time not precise, if precise delay count was needed, please implement a new delay function with hardware timer.

+
Parameters
+ + + +
delayTime_usDelay time in unit of microsecond.
coreClock_HzCore clock frequency with Hz.
+
+
+ +
+
+
+
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"a00086.html#gga06fc87d81c62e9abb8790b6e5713c55ba9743ab3bec5065667c0b12510317e76c", null ], + [ "kStatus_Timeout", "a00086.html#gga06fc87d81c62e9abb8790b6e5713c55badf7f172a5d4f1a44d5cb8a1121dcafcb", null ], + [ "kStatus_NoTransferInProgress", "a00086.html#gga06fc87d81c62e9abb8790b6e5713c55ba82fc7f2a425a9c3cfcf6636b8c05c06c", null ], + [ "kStatus_Busy", "a00086.html#gga06fc87d81c62e9abb8790b6e5713c55ba31e314ec45f0b673257687c06b6fe764", null ] + ] ], + [ "SDK_Malloc", "a00086.html#ga4e1420d9e817ebe0e8973420411de015", null ], + [ "SDK_Free", "a00086.html#ga0be5caec9b8493d87cc849714bd47865", null ], + [ "SDK_DelayAtLeastUs", "a00086.html#ga4f9121590e5b8fe025d706ff2fe5da36", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00087.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00087.html new file mode 100644 index 000000000..e2eae813b --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00087.html @@ -0,0 +1,129 @@ + + + + + + +MCUXpresso SDK API Reference Manual: ECSPI: Enhanced Configurable Serial Peripheral Interface Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Modules
+
+
ECSPI: Enhanced Configurable Serial Peripheral Interface Driver
+
+
+

Overview

+ + + + + + + + +

+Modules

 ECSPI CMSIS Driver
 
 ECSPI Driver
 
 ECSPI FreeRTOS Driver
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00087.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00087.js new file mode 100644 index 000000000..d2274b327 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00087.js @@ -0,0 +1,6 @@ +var a00087 = +[ + [ "ECSPI CMSIS Driver", "a00089.html", null ], + [ "ECSPI Driver", "a00010.html", "a00010" ], + [ "ECSPI FreeRTOS Driver", "a00088.html", "a00088" ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00088.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00088.html new file mode 100644 index 000000000..4daee44c4 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00088.html @@ -0,0 +1,257 @@ + + + + + + +MCUXpresso SDK API Reference Manual: ECSPI FreeRTOS Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
ECSPI FreeRTOS Driver
ECSPI: Enhanced Configurable Serial Peripheral Interface Driver
+
+
+

Overview

+ + + + + +

+Driver version

#define FSL_ECSPI_FREERTOS_DRIVER_VERSION   (MAKE_VERSION(2, 2, 0))
 ECSPI FreeRTOS driver version. More...
 
+ + + + + + + + + + +

+ECSPI RTOS Operation

status_t ECSPI_RTOS_Init (ecspi_rtos_handle_t *handle, ECSPI_Type *base, const ecspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
 Initializes ECSPI. More...
 
status_t ECSPI_RTOS_Deinit (ecspi_rtos_handle_t *handle)
 Deinitializes the ECSPI. More...
 
status_t ECSPI_RTOS_Transfer (ecspi_rtos_handle_t *handle, ecspi_transfer_t *transfer)
 Performs ECSPI transfer. More...
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_ECSPI_FREERTOS_DRIVER_VERSION   (MAKE_VERSION(2, 2, 0))
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
status_t ECSPI_RTOS_Init (ecspi_rtos_handle_t * handle,
ECSPI_Type * base,
const ecspi_master_config_t * masterConfig,
uint32_t srcClock_Hz 
)
+
+

This function initializes the ECSPI module and related RTOS context.

+
Parameters
+ + + + + +
handleThe RTOS ECSPI handle, the pointer to an allocated space for RTOS context.
baseThe pointer base address of the ECSPI instance to initialize.
masterConfigConfiguration structure to set-up ECSPI in master mode.
srcClock_HzFrequency of input clock of the ECSPI module.
+
+
+
Returns
status of the operation.
+ +
+
+ +
+
+ + + + + + + + +
status_t ECSPI_RTOS_Deinit (ecspi_rtos_handle_t * handle)
+
+

This function deinitializes the ECSPI module and related RTOS context.

+
Parameters
+ + +
handleThe RTOS ECSPI handle.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t ECSPI_RTOS_Transfer (ecspi_rtos_handle_t * handle,
ecspi_transfer_t * transfer 
)
+
+

This function performs an ECSPI transfer according to data given in the transfer structure.

+
Parameters
+ + + +
handleThe RTOS ECSPI handle.
transferStructure specifying the transfer parameters.
+
+
+
Returns
status of the operation.
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00088.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00088.js new file mode 100644 index 000000000..dd25c4d31 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00088.js @@ -0,0 +1,7 @@ +var a00088 = +[ + [ "FSL_ECSPI_FREERTOS_DRIVER_VERSION", "a00088.html#ga10a34b5d38a5ff9822fc444148195799", null ], + [ "ECSPI_RTOS_Init", "a00088.html#ga7918b90668b02f4d4e996f8176168451", null ], + [ "ECSPI_RTOS_Deinit", "a00088.html#ga901f7e93af2ee61c81d4ee0ff4801724", null ], + [ "ECSPI_RTOS_Transfer", "a00088.html#gabeedc3019d9f8ba9a20dcee2f9e14d1e", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00089.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00089.html new file mode 100644 index 000000000..55a7fe81a --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00089.html @@ -0,0 +1,177 @@ + + + + + + +MCUXpresso SDK API Reference Manual: ECSPI CMSIS Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
ECSPI CMSIS Driver
ECSPI: Enhanced Configurable Serial Peripheral Interface Driver
+
+
+

This section describes the programming interface of the ecspi Cortex Microcontroller Software Interface Standard (CMSIS) driver. And this driver defines generic peripheral driver interfaces for middleware making it reusable across a wide range of supported microcontroller devices. The API connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces. More information and usage methord please refer to http://www.keil.com/pack/doc/cmsis/Driver/html/index.html.

+

+Function groups

+

+ECSPI CMSIS GetVersion Operation

+

This function group will return the ECSPI CMSIS Driver version to user.

+

+ECSPI CMSIS GetCapabilities Operation

+

This function group will return the capabilities of this driver.

+

+ECSPI CMSIS Initialize and Uninitialize Operation

+

This function will initialize and uninitialize the instance in master mode or slave mode. And this API must be called before you configure an instance or after you Deinit an instance.The right steps to start an instance is that you must initialize the instance which been slected firstly,then you can power on the instance.After these all have been done,you can configure the instance by using control operation.If you want to Uninitialize the instance, you must power off the instance first.

+

+ECSPI CMSIS Transfer Operation

+

This function group controls the transfer, master send/receive data, and slave send/receive data.

+

+ECSPI CMSIS Status Operation

+

This function group gets the ecspi transfer status.

+

+ECSPI CMSIS Control Operation

+

This function can select instance as master mode or slave mode, set baudrate for master mode transfer, get current baudrate of master mode transfer,set transfer data bits and set other control command.

+

+Typical use case

+

+Master Operation

+
/* Variables */
+
uint8_t masterRxData[TRANSFER_SIZE] = {0U};
+
uint8_t masterTxData[TRANSFER_SIZE] = {0U};
+
+
/*ECSPI master init*/
+
Driver_SPI0.Initialize(ECSPI_MasterSignalEvent_t);
+
Driver_SPI0.PowerControl(ARM_POWER_FULL);
+
Driver_SPI0.Control(ARM_SPI_MODE_MASTER, TRANSFER_BAUDRATE);
+
+
/* Start master transfer */
+
Driver_SPI0.Transfer(masterTxData, masterRxData, TRANSFER_SIZE);
+
+
/* Master power off */
+
Driver_SPI0.PowerControl(ARM_POWER_OFF);
+
+
/* Master uninitialize */
+
Driver_SPI0.Uninitialize();
+

+Slave Operation

+
/* Variables */
+
uint8_t slaveRxData[TRANSFER_SIZE] = {0U};
+
uint8_t slaveTxData[TRANSFER_SIZE] = {0U};
+
+
/*DSPI slave init*/
+
Driver_SPI2.Initialize(ECSPI_SlaveSignalEvent_t);
+
Driver_SPI2.PowerControl(ARM_POWER_FULL);
+
Driver_SPI2.Control(ARM_SPI_MODE_SLAVE, false);
+
+
/* Start slave transfer */
+
Driver_SPI2.Transfer(slaveTxData, slaveRxData, TRANSFER_SIZE);
+
+
/* slave power off */
+
Driver_SPI2.PowerControl(ARM_POWER_OFF);
+
+
/* slave uninitialize */
+
Driver_SPI2.Uninitialize();
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00090.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00090.html new file mode 100644 index 000000000..94f05dc8e --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00090.html @@ -0,0 +1,129 @@ + + + + + + +MCUXpresso SDK API Reference Manual: I2C: Inter-Integrated Circuit Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Modules
+
+
I2C: Inter-Integrated Circuit Driver
+
+
+

Overview

+ + + + + + + + +

+Modules

 I2C CMSIS Driver
 
 I2C Driver
 
 I2C FreeRTOS Driver
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00090.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00090.js new file mode 100644 index 000000000..ad201ab5c --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00090.js @@ -0,0 +1,6 @@ +var a00090 = +[ + [ "I2C CMSIS Driver", "a00092.html", null ], + [ "I2C Driver", "a00013.html", "a00013" ], + [ "I2C FreeRTOS Driver", "a00091.html", "a00091" ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00091.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00091.html new file mode 100644 index 000000000..daa430f32 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00091.html @@ -0,0 +1,257 @@ + + + + + + +MCUXpresso SDK API Reference Manual: I2C FreeRTOS Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
I2C FreeRTOS Driver
I2C: Inter-Integrated Circuit Driver
+
+
+

Overview

+ + + + + +

+Driver version

#define FSL_I2C_FREERTOS_DRIVER_VERSION   (MAKE_VERSION(2, 0, 7))
 I2C FreeRTOS driver version. More...
 
+ + + + + + + + + + +

+I2C RTOS Operation

status_t I2C_RTOS_Init (i2c_rtos_handle_t *handle, I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
 Initializes I2C. More...
 
status_t I2C_RTOS_Deinit (i2c_rtos_handle_t *handle)
 Deinitializes the I2C. More...
 
status_t I2C_RTOS_Transfer (i2c_rtos_handle_t *handle, i2c_master_transfer_t *transfer)
 Performs the I2C transfer. More...
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_I2C_FREERTOS_DRIVER_VERSION   (MAKE_VERSION(2, 0, 7))
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
status_t I2C_RTOS_Init (i2c_rtos_handle_t * handle,
I2C_Type * base,
const i2c_master_config_t * masterConfig,
uint32_t srcClock_Hz 
)
+
+

This function initializes the I2C module and the related RTOS context.

+
Parameters
+ + + + + +
handleThe RTOS I2C handle, the pointer to an allocated space for RTOS context.
baseThe pointer base address of the I2C instance to initialize.
masterConfigThe configuration structure to set-up I2C in master mode.
srcClock_HzThe frequency of an input clock of the I2C module.
+
+
+
Returns
status of the operation.
+ +
+
+ +
+
+ + + + + + + + +
status_t I2C_RTOS_Deinit (i2c_rtos_handle_t * handle)
+
+

This function deinitializes the I2C module and the related RTOS context.

+
Parameters
+ + +
handleThe RTOS I2C handle.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t I2C_RTOS_Transfer (i2c_rtos_handle_t * handle,
i2c_master_transfer_t * transfer 
)
+
+

This function performs the I2C transfer according to the data given in the transfer structure.

+
Parameters
+ + + +
handleThe RTOS I2C handle.
transferA structure specifying the transfer parameters.
+
+
+
Returns
status of the operation.
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00091.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00091.js new file mode 100644 index 000000000..ccfec3c00 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00091.js @@ -0,0 +1,7 @@ +var a00091 = +[ + [ "FSL_I2C_FREERTOS_DRIVER_VERSION", "a00091.html#ga8a57a810d1c6632d3bf7dd2ea4e76ae5", null ], + [ "I2C_RTOS_Init", "a00091.html#ga2d8b0de9d5d807257ac91df157233cae", null ], + [ "I2C_RTOS_Deinit", "a00091.html#gabe3dc27604637a77cba04967097defb2", null ], + [ "I2C_RTOS_Transfer", "a00091.html#ga0b090779ab62f02149066a2325feb868", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00092.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00092.html new file mode 100644 index 000000000..d9bc154a7 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00092.html @@ -0,0 +1,173 @@ + + + + + + +MCUXpresso SDK API Reference Manual: I2C CMSIS Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
I2C CMSIS Driver
I2C: Inter-Integrated Circuit Driver
+
+
+

This section describes the programming interface of the I2C Cortex Microcontroller Software Interface Standard (CMSIS) driver. This driver defines generic peripheral driver interfaces for middleware making it reusable across a wide range of supported microcontroller devices. The API connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces. More information and usage methord see http://www.keil.com/pack/doc/cmsis/Driver/html/index.html.

+

The I2C CMSIS driver includes transactional APIs.

+

Transactional APIs are transaction target high-level APIs. The transactional APIs can be used to enable the peripheral quickly and also in the application if the code size and performance of transactional APIs satisfy the requirements. If the code size and performance are critical requirements, see the transactional API implementation and write custom code accessing the hardware registers.

+

+I2C CMSIS Driver

+

+Master Operation in interrupt transactional method

+
void I2C_MasterSignalEvent_t(uint32_t event)
+
{
+
if (event == ARM_I2C_EVENT_TRANSFER_DONE)
+
{
+
g_MasterCompletionFlag = true;
+
}
+
}
+
/*Init I2C1*/
+
Driver_I2C1.Initialize(I2C_MasterSignalEvent_t);
+
+
Driver_I2C1.PowerControl(ARM_POWER_FULL);
+
+
/*config transmit speed*/
+
Driver_I2C1.Control(ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_STANDARD);
+
+
/*start transmit*/
+
Driver_I2C1.MasterTransmit(I2C_MASTER_SLAVE_ADDR, g_master_buff, I2C_DATA_LENGTH, false);
+
+
/* Wait for transfer completed. */
+
while (!g_MasterCompletionFlag)
+
{
+
}
+
g_MasterCompletionFlag = false;
+

+Slave Operation in interrupt transactional method

+
void I2C_SlaveSignalEvent_t(uint32_t event)
+
{
+
/* Transfer done */
+
if (event == ARM_I2C_EVENT_TRANSFER_DONE)
+
{
+
g_SlaveCompletionFlag = true;
+
}
+
}
+
+
/*Init I2C1*/
+
Driver_I2C1.Initialize(I2C_SlaveSignalEvent_t);
+
+
Driver_I2C1.PowerControl(ARM_POWER_FULL);
+
+
/*config slave addr*/
+
Driver_I2C1.Control(ARM_I2C_OWN_ADDRESS, I2C_MASTER_SLAVE_ADDR);
+
+
/*start transfer*/
+
Driver_I2C1.SlaveReceive(g_slave_buff, I2C_DATA_LENGTH);
+
+
/* Wait for transfer completed. */
+
while (!g_SlaveCompletionFlag)
+
{
+
}
+
g_SlaveCompletionFlag = false;
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00093.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00093.html new file mode 100644 index 000000000..868ab0a17 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00093.html @@ -0,0 +1,1103 @@ + + + + + + +MCUXpresso SDK API Reference Manual: PWM: Pulse Width Modulation Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Enumerations | +Functions
+
+
PWM: Pulse Width Modulation Driver
+
+
+

Overview

+

The MCUXpresso SDK provides a peripheral driver for the Pulse Width Modulation (PWM) module of MCUXpresso SDK devices.

+

+PWM Driver

+

+Initialization and deinitialization

+

The function PWM_Init() initializes the PWM with a specified configurations. The function PWM_GetDefaultConfig() gets the default configurations.The initialization function configures the PWM for the requested register update mode for registers with buffers.

+

The function PWM_Deinit() disables the PWM counter and turns off the module clock.

+

+Typical use case

+

+PWM output

+

Output PWM signal on PWM3 module with different dutycycles. Periodically update the PWM signal duty cycle. Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/pwm

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Enumerations

enum  pwm_clock_source_t {
+  kPWM_PeripheralClock = 1U, +
+  kPWM_HighFrequencyClock, +
+  kPWM_LowFrequencyClock +
+ }
 PWM clock source select. More...
 
enum  pwm_fifo_water_mark_t {
+  kPWM_FIFOWaterMark_1 = 0U, +
+  kPWM_FIFOWaterMark_2, +
+  kPWM_FIFOWaterMark_3, +
+  kPWM_FIFOWaterMark_4 +
+ }
 PWM FIFO water mark select. More...
 
enum  pwm_byte_data_swap_t {
+  kPWM_ByteNoSwap = 0U, +
+  kPWM_ByteSwap +
+ }
 PWM byte data swap select. More...
 
enum  pwm_half_word_data_swap_t {
+  kPWM_HalfWordNoSwap = 0U, +
+  kPWM_HalfWordSwap +
+ }
 PWM half-word data swap select. More...
 
enum  pwm_output_configuration_t {
+  kPWM_SetAtRolloverAndClearAtcomparison = 0U, +
+  kPWM_ClearAtRolloverAndSetAtcomparison, +
+  kPWM_NoConfigure +
+ }
 PWM Output Configuration. More...
 
enum  pwm_sample_repeat_t {
+  kPWM_EachSampleOnce = 0u, +
+  kPWM_EachSampletwice, +
+  kPWM_EachSampleFourTimes, +
+  kPWM_EachSampleEightTimes +
+ }
 PWM FIFO sample repeat It determines the number of times each sample from the FIFO is to be used. More...
 
enum  pwm_interrupt_enable_t {
+  kPWM_FIFOEmptyInterruptEnable = (1U << 0), +
+  kPWM_RolloverInterruptEnable = (1U << 1), +
+  kPWM_CompareInterruptEnable = (1U << 2) +
+ }
 List of PWM interrupt options. More...
 
enum  pwm_status_flags_t {
+  kPWM_FIFOEmptyFlag = (1U << 3), +
+  kPWM_RolloverFlag = (1U << 4), +
+  kPWM_CompareFlag = (1U << 5), +
+  kPWM_FIFOWriteErrorFlag +
+ }
 List of PWM status flags. More...
 
enum  pwm_fifo_available_t {
+  kPWM_NoDataInFIFOFlag = 0U, +
+  kPWM_OneWordInFIFOFlag, +
+  kPWM_TwoWordsInFIFOFlag, +
+  kPWM_ThreeWordsInFIFOFlag, +
+  kPWM_FourWordsInFIFOFlag +
+ }
 List of PWM FIFO available. More...
 
+ + + + + + + + + + + + + +

+Functions

static void PWM_SoftwareReset (PWM_Type *base)
 Sofrware reset. More...
 
static void PWM_SetPeriodValue (PWM_Type *base, uint32_t value)
 Sets the PWM period value. More...
 
static uint32_t PWM_GetPeriodValue (PWM_Type *base)
 Gets the PWM period value. More...
 
static uint32_t PWM_GetCounterValue (PWM_Type *base)
 Gets the PWM counter value. More...
 
+ + + + +

+Driver version

+#define FSL_PWM_DRIVER_VERSION   (MAKE_VERSION(2, 0, 0))
 Version 2.0.0.
 
+ + + + + + + + + + +

+Initialization and deinitialization

status_t PWM_Init (PWM_Type *base, const pwm_config_t *config)
 Ungates the PWM clock and configures the peripheral for basic operation. More...
 
void PWM_Deinit (PWM_Type *base)
 Gate the PWM submodule clock. More...
 
void PWM_GetDefaultConfig (pwm_config_t *config)
 Fill in the PWM config struct with the default settings. More...
 
+ + + + + + + +

+PWM start and stop.

static void PWM_StartTimer (PWM_Type *base)
 Starts the PWM counter when the PWM is enabled. More...
 
static void PWM_StopTimer (PWM_Type *base)
 Stops the PWM counter when the pwm is disabled. More...
 
+ + + + + + + + + + +

+Interrupt Interface

static void PWM_EnableInterrupts (PWM_Type *base, uint32_t mask)
 Enables the selected PWM interrupts. More...
 
static void PWM_DisableInterrupts (PWM_Type *base, uint32_t mask)
 Disables the selected PWM interrupts. More...
 
static uint32_t PWM_GetEnabledInterrupts (PWM_Type *base)
 Gets the enabled PWM interrupts. More...
 
+ + + + + + + + + + +

+Status Interface

static uint32_t PWM_GetStatusFlags (PWM_Type *base)
 Gets the PWM status flags. More...
 
static void PWM_clearStatusFlags (PWM_Type *base, uint32_t mask)
 Clears the PWM status flags. More...
 
static uint32_t PWM_GetFIFOAvailable (PWM_Type *base)
 Gets the PWM FIFO available. More...
 
+ + + + + + + +

+Sample Interface

static void PWM_SetSampleValue (PWM_Type *base, uint32_t value)
 Sets the PWM sample value. More...
 
static uint32_t PWM_GetSampleValue (PWM_Type *base)
 Gets the PWM sample value. More...
 
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum pwm_clock_source_t
+
+ + + + +
Enumerator
kPWM_PeripheralClock  +

The Peripheral clock is used as the clock.

+
kPWM_HighFrequencyClock  +

High-frequency reference clock is used as the clock.

+
kPWM_LowFrequencyClock  +

Low-frequency reference clock(32KHz) is used as the clock.

+
+ +
+
+ +
+
+ + + + +
enum pwm_fifo_water_mark_t
+
+

Sets the data level at which the FIFO empty flag will be set

+ + + + + +
Enumerator
kPWM_FIFOWaterMark_1  +

FIFO empty flag is set when there are more than or equal to 1 empty slots.

+
kPWM_FIFOWaterMark_2  +

FIFO empty flag is set when there are more than or equal to 2 empty slots.

+
kPWM_FIFOWaterMark_3  +

FIFO empty flag is set when there are more than or equal to 3 empty slots.

+
kPWM_FIFOWaterMark_4  +

FIFO empty flag is set when there are more than or equal to 4 empty slots.

+
+ +
+
+ +
+
+ + + + +
enum pwm_byte_data_swap_t
+
+

It determines the byte ordering of the 16-bit data when it goes into the FIFO from the sample register.

+ + + +
Enumerator
kPWM_ByteNoSwap  +

byte ordering remains the same

+
kPWM_ByteSwap  +

byte ordering is reversed

+
+ +
+
+ +
+
+ + + + +
enum pwm_half_word_data_swap_t
+
+ + + +
Enumerator
kPWM_HalfWordNoSwap  +

Half word swapping does not take place.

+
kPWM_HalfWordSwap  +

Half word from write data bus are swapped.

+
+ +
+
+ +
+
+ + + + +
enum pwm_output_configuration_t
+
+ + + + +
Enumerator
kPWM_SetAtRolloverAndClearAtcomparison  +

Output pin is set at rollover and cleared at comparison.

+
kPWM_ClearAtRolloverAndSetAtcomparison  +

Output pin is cleared at rollover and set at comparison.

+
kPWM_NoConfigure  +

PWM output is disconnected.

+
+ +
+
+ +
+
+ + + + +
enum pwm_sample_repeat_t
+
+ + + + + +
Enumerator
kPWM_EachSampleOnce  +

Use each sample once.

+
kPWM_EachSampletwice  +

Use each sample twice.

+
kPWM_EachSampleFourTimes  +

Use each sample four times.

+
kPWM_EachSampleEightTimes  +

Use each sample eight times.

+
+ +
+
+ +
+
+ + + + +
enum pwm_interrupt_enable_t
+
+ + + + +
Enumerator
kPWM_FIFOEmptyInterruptEnable  +

This bit controls the generation of the FIFO Empty interrupt.

+
kPWM_RolloverInterruptEnable  +

This bit controls the generation of the Rollover interrupt.

+
kPWM_CompareInterruptEnable  +

This bit controls the generation of the Compare interrupt.

+
+ +
+
+ +
+
+ + + + +
enum pwm_status_flags_t
+
+ + + + + +
Enumerator
kPWM_FIFOEmptyFlag  +

This bit indicates the FIFO data level in comparison to the water level set by FWM field in the control register.

+
kPWM_RolloverFlag  +

This bit shows that a roll-over event has occurred.

+
kPWM_CompareFlag  +

This bit shows that a compare event has occurred.

+
kPWM_FIFOWriteErrorFlag  +

This bit shows that an attempt has been made to write FIFO when it is full.

+
+ +
+
+ +
+
+ + + + +
enum pwm_fifo_available_t
+
+ + + + + + +
Enumerator
kPWM_NoDataInFIFOFlag  +

No data available.

+
kPWM_OneWordInFIFOFlag  +

1 word of data in FIFO

+
kPWM_TwoWordsInFIFOFlag  +

2 word of data in FIFO

+
kPWM_ThreeWordsInFIFOFlag  +

3 word of data in FIFO

+
kPWM_FourWordsInFIFOFlag  +

4 word of data in FIFO

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t PWM_Init (PWM_Type * base,
const pwm_config_t * config 
)
+
+
Note
This API should be called at the beginning of the application using the PWM driver.
+
Parameters
+ + + +
basePWM peripheral base address
configPointer to user's PWM config structure.
+
+
+
Returns
kStatus_Success means success; else failed.
+ +
+
+ +
+
+ + + + + + + + +
void PWM_Deinit (PWM_Type * base)
+
+
Parameters
+ + +
basePWM peripheral base address
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWM_GetDefaultConfig (pwm_config_t * config)
+
+

The default values are:

+
* config->enableStopMode = false;
+
* config->enableDozeMode = false;
+
* config->enableWaitMode = false;
+
* config->enableDozeMode = false;
+
* config->clockSource = kPWM_LowFrequencyClock;
+
* config->prescale = 0U;
+
* config->outputConfig = kPWM_SetAtRolloverAndClearAtcomparison;
+
* config->fifoWater = kPWM_FIFOWaterMark_2;
+
* config->sampleRepeat = kPWM_EachSampleOnce;
+
* config->byteSwap = kPWM_ByteNoSwap;
+
* config->halfWordSwap = kPWM_HalfWordNoSwap;
+
*
+
Parameters
+ + +
configPointer to user's PWM config structure.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void PWM_StartTimer (PWM_Type * base)
+ 		+inlinestatic
+
+

When the PWM is enabled, it begins a new period, the output pin is set to start a new period while the prescaler and counter are released and counting begins.

+
Parameters
+ + +
basePWM peripheral base address
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void PWM_StopTimer (PWM_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
basePWM peripheral base address
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void PWM_SoftwareReset (PWM_Type * base)
+ 		+inlinestatic
+
+

PWM is reset when this bit is set to 1. It is a self clearing bit. Setting this bit resets all the registers to their reset values except for the STOPEN, DOZEN, WAITEN, and DBGEN bits in this control register.

+
Parameters
+ + +
basePWM peripheral base address
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void PWM_EnableInterrupts (PWM_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePWM peripheral base address
maskThe interrupts to enable. This is a logical OR of members of the enumeration pwm_interrupt_enable_t
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void PWM_DisableInterrupts (PWM_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePWM peripheral base address
maskThe interrupts to disable. This is a logical OR of members of the enumeration pwm_interrupt_enable_t
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t PWM_GetEnabledInterrupts (PWM_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
basePWM peripheral base address
+
+
+
Returns
The enabled interrupts. This is the logical OR of members of the enumeration pwm_interrupt_enable_t
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t PWM_GetStatusFlags (PWM_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
basePWM peripheral base address
+
+
+
Returns
The status flags. This is the logical OR of members of the enumeration pwm_status_flags_t
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void PWM_clearStatusFlags (PWM_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePWM peripheral base address
maskThe status flags to clear. This is a logical OR of members of the enumeration pwm_status_flags_t
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t PWM_GetFIFOAvailable (PWM_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
basePWM peripheral base address
+
+
+
Returns
The status flags. This is the logical OR of members of the enumeration pwm_fifo_available_t
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void PWM_SetSampleValue (PWM_Type * base,
uint32_t value 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePWM peripheral base address
valueThe sample value. This is the input to the 4x16 FIFO. The value in this register denotes the value of the sample being currently used.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t PWM_GetSampleValue (PWM_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
basePWM peripheral base address
+
+
+
Returns
The sample value. It can be read only when the PWM is enable.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void PWM_SetPeriodValue (PWM_Type * base,
uint32_t value 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
basePWM peripheral base address
valueThe period value. The PWM period register (PWM_PWMPR) determines the period of the PWM output signal. Writing 0xFFFF to this register will achieve the same result as writing 0xFFFE. PWMO (Hz) = PCLK(Hz) / (period +2)
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t PWM_GetPeriodValue (PWM_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
basePWM peripheral base address
+
+
+
Returns
The period value. The PWM period register (PWM_PWMPR) determines the period of the PWM output signal.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t PWM_GetCounterValue (PWM_Type * base)
+ 		+inlinestatic
+
+
Parameters
+ + +
basePWM peripheral base address
+
+
+
Returns
The counter value. The current count value.
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00093.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00093.js new file mode 100644 index 000000000..bca67c493 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00093.js @@ -0,0 +1,69 @@ +var a00093 = +[ + [ "FSL_PWM_DRIVER_VERSION", "a00093.html#ga8bda5d1da1f6b7150e002c109a62d083", null ], + [ "pwm_clock_source_t", "a00093.html#ga54dcbb5e3e5c8ceebef5f46a9ec73a2f", [ + [ "kPWM_PeripheralClock", "a00093.html#gga54dcbb5e3e5c8ceebef5f46a9ec73a2fa720ad082de555ca2262db6704c2a48a3", null ], + [ "kPWM_HighFrequencyClock", "a00093.html#gga54dcbb5e3e5c8ceebef5f46a9ec73a2fa085a1f3b7337dbbba37cc92b63c456a9", null ], + [ "kPWM_LowFrequencyClock", "a00093.html#gga54dcbb5e3e5c8ceebef5f46a9ec73a2faba2ffadbe1b173e93305c188117a76c2", null ] + ] ], + [ "pwm_fifo_water_mark_t", "a00093.html#ga6e28d42a5d0c43c2afd4a360868b67c1", [ + [ "kPWM_FIFOWaterMark_1", "a00093.html#gga6e28d42a5d0c43c2afd4a360868b67c1a46bc12cdcd748f75352dda927d12469a", null ], + [ "kPWM_FIFOWaterMark_2", "a00093.html#gga6e28d42a5d0c43c2afd4a360868b67c1aa33f62954c9e10d85e4a13412090913f", null ], + [ "kPWM_FIFOWaterMark_3", "a00093.html#gga6e28d42a5d0c43c2afd4a360868b67c1ada5ef9ecf09d93451bf57b8a4b618ba4", null ], + [ "kPWM_FIFOWaterMark_4", "a00093.html#gga6e28d42a5d0c43c2afd4a360868b67c1af5401079de9ca6b7e62439d9a984ae03", null ] + ] ], + [ "pwm_byte_data_swap_t", "a00093.html#gacc83f5df6efd279b96ec7736d4259134", [ + [ "kPWM_ByteNoSwap", "a00093.html#ggacc83f5df6efd279b96ec7736d4259134ae3fa9d0120efe5505d2af8e97930289d", null ], + [ "kPWM_ByteSwap", "a00093.html#ggacc83f5df6efd279b96ec7736d4259134a4c7de4fcc7f74c751dad87d905dc1898", null ] + ] ], + [ "pwm_half_word_data_swap_t", "a00093.html#ga9717526c69f90be4577677b784a95c99", [ + [ "kPWM_HalfWordNoSwap", "a00093.html#gga9717526c69f90be4577677b784a95c99a7fa6ec0c14835ef884bf21948ab9bcf1", null ], + [ "kPWM_HalfWordSwap", "a00093.html#gga9717526c69f90be4577677b784a95c99a6a9922129c4d784d1c2a7b488ef5f9fc", null ] + ] ], + [ "pwm_output_configuration_t", "a00093.html#ga0adacb1aa800a63efc5284aad1c99e94", [ + [ "kPWM_SetAtRolloverAndClearAtcomparison", "a00093.html#gga0adacb1aa800a63efc5284aad1c99e94ae7aa751cf0d4e6cc037bcb759a2da38a", null ], + [ "kPWM_ClearAtRolloverAndSetAtcomparison", "a00093.html#gga0adacb1aa800a63efc5284aad1c99e94ab0fc28ed8325295cc72f3dd186b92d89", null ], + [ "kPWM_NoConfigure", "a00093.html#gga0adacb1aa800a63efc5284aad1c99e94a2defe10613012528de8c7cb282af6534", null ] + ] ], + [ "pwm_sample_repeat_t", "a00093.html#ga0fa976f45603849cad601ab4db4d15b7", [ + [ "kPWM_EachSampleOnce", "a00093.html#gga0fa976f45603849cad601ab4db4d15b7a602b673889a9b270cec181f67df0b693", null ], + [ "kPWM_EachSampletwice", "a00093.html#gga0fa976f45603849cad601ab4db4d15b7aa76ac77e7df80d685a539609a2f3989d", null ], + [ "kPWM_EachSampleFourTimes", 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null ], + [ "kPWM_CompareFlag", "a00093.html#ggabc3ee1e46578039b2dbe795d60a69b2fa5c09799112bef469896b400acfa81c47", null ], + [ "kPWM_FIFOWriteErrorFlag", "a00093.html#ggabc3ee1e46578039b2dbe795d60a69b2faea97a51c1742c4b203c9d43efabf773e", null ] + ] ], + [ "pwm_fifo_available_t", "a00093.html#ga44d23f62b51e6ff9cfb59c0de70854e0", [ + [ "kPWM_NoDataInFIFOFlag", "a00093.html#gga44d23f62b51e6ff9cfb59c0de70854e0abc972d0365de9da7939b7b2303843ae7", null ], + [ "kPWM_OneWordInFIFOFlag", "a00093.html#gga44d23f62b51e6ff9cfb59c0de70854e0a7ad9f69d768a8db9d06451bd10570f45", null ], + [ "kPWM_TwoWordsInFIFOFlag", "a00093.html#gga44d23f62b51e6ff9cfb59c0de70854e0a9f29c4ee5edf483e38b8cfd8ae17d5fe", null ], + [ "kPWM_ThreeWordsInFIFOFlag", "a00093.html#gga44d23f62b51e6ff9cfb59c0de70854e0a562337a037bdefed6658dbc098d28ba8", null ], + [ "kPWM_FourWordsInFIFOFlag", "a00093.html#gga44d23f62b51e6ff9cfb59c0de70854e0a8c49eedceff1f99bd9908fcaf652278d", null ] + ] ], + [ "PWM_Init", "a00093.html#ga6359b8a4cd00c794549ed9441e50ba3c", null ], + [ "PWM_Deinit", "a00093.html#gaf93b767ea243d633bb00e3c7b4a217c6", null ], + [ "PWM_GetDefaultConfig", "a00093.html#gaead09677ab28bfd57dce26c6c161b18d", null ], + [ "PWM_StartTimer", "a00093.html#ga6d94af58afb186f19c075cf0cc8a4670", null ], + [ "PWM_StopTimer", "a00093.html#ga863fd4143eab8fba91be2a80c300ee5f", null ], + [ "PWM_SoftwareReset", "a00093.html#ga46cd9b9c3c3409649667d816b37dfe93", null ], + [ "PWM_EnableInterrupts", "a00093.html#gaa8ddb3dddd8f5a9451cf286da691572e", null ], + [ "PWM_DisableInterrupts", "a00093.html#gaf8ef908a32a5b7c11890119680533efb", null ], + [ "PWM_GetEnabledInterrupts", "a00093.html#gaf5aeac9d17361d41ebd4fd35cf8c844b", null ], + [ "PWM_GetStatusFlags", "a00093.html#ga1e16638fb84c7881722c7d370824bb34", null ], + [ "PWM_clearStatusFlags", "a00093.html#ga5554b41a1262201466f831085fa0a0e3", null ], + [ "PWM_GetFIFOAvailable", "a00093.html#ga68f31c637445e375d6429db0f265a0ff", null ], + [ "PWM_SetSampleValue", "a00093.html#gaf30e59afefa5214fdb951a41508c39d2", null ], + [ "PWM_GetSampleValue", "a00093.html#ga6e3329e7f50fc923b26003a988366860", null ], + [ "PWM_SetPeriodValue", "a00093.html#gaeca8cd9af1aacdca96c91f60482a54d4", null ], + [ "PWM_GetPeriodValue", "a00093.html#ga67304227c86e6a15ec78f339f9fe00e3", null ], + [ "PWM_GetCounterValue", "a00093.html#gac77ad7b4cbb1658df73b8d50f10978b5", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00094.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00094.html new file mode 100644 index 000000000..ed5035404 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00094.html @@ -0,0 +1,129 @@ + + + + + + +MCUXpresso SDK API Reference Manual: UART: Universal Asynchronous Receiver/Transmitter Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Modules
+
+
UART: Universal Asynchronous Receiver/Transmitter Driver
+
+
+

Overview

+ + + + + + + + +

+Modules

 UART CMSIS Driver
 
 UART Driver
 
 UART FreeRTOS Driver
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00094.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00094.js new file mode 100644 index 000000000..c6fffa8b9 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00094.js @@ -0,0 +1,6 @@ +var a00094 = +[ + [ "UART CMSIS Driver", "a00095.html", null ], + [ "UART Driver", "a00020.html", "a00020" ], + [ "UART FreeRTOS Driver", "a00021.html", "a00021" ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00095.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00095.html new file mode 100644 index 000000000..ea93fd2bc --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00095.html @@ -0,0 +1,139 @@ + + + + + + +MCUXpresso SDK API Reference Manual: UART CMSIS Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
UART CMSIS Driver
UART: Universal Asynchronous Receiver/Transmitter Driver
+
+
+

This section describes the programming interface of the UART Cortex Microcontroller Software Interface Standard (CMSIS) driver. And this driver defines generic peripheral driver interfaces for middleware making it reusable across a wide range of supported microcontroller devices. The API connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces. More information and usage methord please refer to http://www.keil.com/pack/doc/cmsis/Driver/html/index.html.

+

The UART driver includes transactional APIs.

+

Transactional APIs can be used to enable the peripheral quickly and in the application if the code size and performance of transactional APIs can satisfy the requirements. If the code size and performance are critical requirements please write custom code.

+

+Function groups

+

+UART CMSIS GetVersion Operation

+

This function group will return the UART CMSIS Driver version to user.

+

+UART CMSIS GetCapabilities Operation

+

This function group will return the capabilities of this driver.

+

+UART CMSIS Initialize and Uninitialize Operation

+

This function will initialize and uninitialize the uart instance . And this API must be called before you configure an uart instance or after you Deinit an uart instance.The right steps to start an instance is that you must initialize the instance which been slected firstly,then you can power on the instance.After these all have been done,you can configure the instance by using control operation.If you want to Uninitialize the instance, you must power off the instance first.

+

+UART CMSIS Transfer Operation

+

This function group controls the transfer, send/receive data.

+

+UART CMSIS Status Operation

+

This function group gets the UART transfer status.

+

+UART CMSIS Control Operation

+

This function can configure an instance ,set baudrate for uart, get current baudrate ,set transfer data bits and other control command.

+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00096.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00096.html new file mode 100644 index 000000000..d815e6f2b --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00096.html @@ -0,0 +1,1142 @@ + + + + + + +MCUXpresso SDK API Reference Manual: MU: Messaging Unit + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Enumerations
+
+
MU: Messaging Unit
+
+
+

Overview

+

The MCUXpresso SDK provides a driver for the MU module of MCUXpresso SDK devices.

+

+Function description

+

The MU driver provides these functions:

+
    +
  • Functions to initialize the MU module.
    • +
  • Functions to send and receive messages.
    • +
  • Functions for MU flags for both MU sides.
    • +
  • Functions for status flags and interrupts.
    • +
  • Other miscellaneous functions.
    • +
+

+MU initialization

+

The function MU_Init() initializes the MU module and enables the MU clock. It should be called before any other MU functions.
+ The function MU_Deinit() deinitializes the MU module and disables the MU clock. No MU functions can be called after this function.
+

+

+MU message

+

The MU message must be sent when the transmit register is empty. The MU driver provides blocking API and non-blocking API to send message.
+ The MU_SendMsgNonBlocking() function writes a message to the MU transmit register without checking the transmit register status. The upper layer should check that the transmit register is empty before calling this function. This function can be used in the ISR for better performance.
+ The MU_SendMsg() function is a blocking function. It waits until the transmit register is empty and sends the message.
+ Correspondingly, there are blocking and non-blocking APIs for receiving a message. The MU_ReadMsgNonBlocking() function is a non-blocking API. The MU_ReadMsg() function is the blocking API.

+

+MU flags

+

The MU driver provides 3-bit general purpose flags. When the flags are set on one side, they are reflected on the other side.
+ The MU flags must be set when the previous flags have been updated to the other side. The MU driver provides a non-blocking function and a blocking function. The blocking function MU_SetFlags() waits until previous flags have been updated to the other side and then sets flags. The non-blocking function sets the flags directly. Ensure that the kMU_FlagsUpdatingFlag is not pending before calling this function.
+ The function MU_GetFlags() gets the MU flags on the current side.

+

+Status and interrupt

+

The function MU_GetStatusFlags() returns all MU status flags. Use the _mu_status_flags to check for specific flags, for example, to check RX0 and RX1 register full, use the following code:

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/mu The receive full flags are cleared automatically after messages are read out. The transmit empty flags are cleared automatically after new messages are written to the transmit register. The general purpose interrupt flags must be cleared manually using the function MU_ClearStatusFlags().
+ Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/mu To enable or disable a specific interrupt, use MU_EnableInterrupts() and MU_DisableInterrupts() functions. The interrupts to enable or disable should be passed in as a bit mask of the _mu_interrupt_enable.
+ The MU_TriggerInterrupts() function triggers general purpose interrupts and NMI to the other core. The interrupts to trigger are passed in as a bit mask of the _mu_interrupt_trigger. If previously triggered interrupts have not been processed by the other side, this function returns an error.

+

+MU misc functions

+

The MU_BootCoreB() and MU_HoldCoreBReset() functions should only be used from A side. They are used to boot the core B or to hold core B in reset.
+ The MU_ResetBothSides() function resets MU at both A and B sides. However, only the A side can call this function.
+ If a core enters stop mode, the platform clock of this core is disabled by default. The function MU_SetClockOnOtherCoreEnable() forces the other core's platform clock to remain enabled even after that core has entered a stop mode. In this case, the other core's platform clock keeps running until the current core enters stop mode too.
+ Function MU_GetOtherCorePowerMode() gets the power mode of the other core.

+ + + + + + + + + + + +

+Enumerations

enum  _mu_status_flags {
+  kMU_Tx0EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 3U)), +
+  kMU_Tx1EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 2U)), +
+  kMU_Tx2EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 1U)), +
+  kMU_Tx3EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 0U)), +
+  kMU_Rx0FullFlag = (1U << (MU_SR_RFn_SHIFT + 3U)), +
+  kMU_Rx1FullFlag = (1U << (MU_SR_RFn_SHIFT + 2U)), +
+  kMU_Rx2FullFlag = (1U << (MU_SR_RFn_SHIFT + 1U)), +
+  kMU_Rx3FullFlag = (1U << (MU_SR_RFn_SHIFT + 0U)), +
+  kMU_GenInt0Flag = (1U << (MU_SR_GIPn_SHIFT + 3U)), +
+  kMU_GenInt1Flag = (1U << (MU_SR_GIPn_SHIFT + 2U)), +
+  kMU_GenInt2Flag = (1U << (MU_SR_GIPn_SHIFT + 1U)), +
+  kMU_GenInt3Flag = (1U << (MU_SR_GIPn_SHIFT + 0U)), +
+  kMU_EventPendingFlag = MU_SR_EP_MASK, +
+  kMU_FlagsUpdatingFlag = MU_SR_FUP_MASK, +
+  kMU_OtherSideInResetFlag = MU_SR_RS_MASK +
+ }
 MU status flags. More...
 
enum  _mu_interrupt_enable {
+  kMU_Tx0EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 3U)), +
+  kMU_Tx1EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 2U)), +
+  kMU_Tx2EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 1U)), +
+  kMU_Tx3EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 0U)), +
+  kMU_Rx0FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 3U)), +
+  kMU_Rx1FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 2U)), +
+  kMU_Rx2FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 1U)), +
+  kMU_Rx3FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 0U)), +
+  kMU_GenInt0InterruptEnable = (int)(1U << (MU_CR_GIEn_SHIFT + 3U)), +
+  kMU_GenInt1InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 2U)), +
+  kMU_GenInt2InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 1U)), +
+  kMU_GenInt3InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 0U)) +
+ }
 MU interrupt source to enable. More...
 
enum  _mu_interrupt_trigger {
+  kMU_GenInt0InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 3U)), +
+  kMU_GenInt1InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 2U)), +
+  kMU_GenInt2InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 1U)), +
+  kMU_GenInt3InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 0U)) +
+ }
 MU interrupt that could be triggered to the other core. More...
 
+ + + + +

+Driver version

#define FSL_MU_DRIVER_VERSION   (MAKE_VERSION(2, 0, 6))
 MU driver version. More...
 
+ + + + + + + +

+MU initialization.

void MU_Init (MU_Type *base)
 Initializes the MU module. More...
 
void MU_Deinit (MU_Type *base)
 De-initializes the MU module. More...
 
+ + + + + + + + + + + + + +

+MU Message

static void MU_SendMsgNonBlocking (MU_Type *base, uint32_t regIndex, uint32_t msg)
 Writes a message to the TX register. More...
 
void MU_SendMsg (MU_Type *base, uint32_t regIndex, uint32_t msg)
 Blocks to send a message. More...
 
static uint32_t MU_ReceiveMsgNonBlocking (MU_Type *base, uint32_t regIndex)
 Reads a message from the RX register. More...
 
uint32_t MU_ReceiveMsg (MU_Type *base, uint32_t regIndex)
 Blocks to receive a message. More...
 
+ + + + + + + + + + +

+MU Flags

static void MU_SetFlagsNonBlocking (MU_Type *base, uint32_t flags)
 Sets the 3-bit MU flags reflect on the other MU side. More...
 
void MU_SetFlags (MU_Type *base, uint32_t flags)
 Blocks setting the 3-bit MU flags reflect on the other MU side. More...
 
static uint32_t MU_GetFlags (MU_Type *base)
 Gets the current value of the 3-bit MU flags set by the other side. More...
 
+ + + + + + + + + + + + + + + + + + + +

+Status and Interrupt.

static uint32_t MU_GetStatusFlags (MU_Type *base)
 Gets the MU status flags. More...
 
static uint32_t MU_GetInterruptsPending (MU_Type *base)
 Gets the MU IRQ pending status. More...
 
static void MU_ClearStatusFlags (MU_Type *base, uint32_t mask)
 Clears the specific MU status flags. More...
 
static void MU_EnableInterrupts (MU_Type *base, uint32_t mask)
 Enables the specific MU interrupts. More...
 
static void MU_DisableInterrupts (MU_Type *base, uint32_t mask)
 Disables the specific MU interrupts. More...
 
status_t MU_TriggerInterrupts (MU_Type *base, uint32_t mask)
 Triggers interrupts to the other core. More...
 
+ + + + + + + +

+MU misc functions

static void MU_MaskHardwareReset (MU_Type *base, bool mask)
 Mask hardware reset by the other core. More...
 
static mu_power_mode_t MU_GetOtherCorePowerMode (MU_Type *base)
 Gets the power mode of the other core. More...
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define FSL_MU_DRIVER_VERSION   (MAKE_VERSION(2, 0, 6))
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum _mu_status_flags
+
+ + + + + + + + + + + + + + + + +
Enumerator
kMU_Tx0EmptyFlag  +

TX0 empty.

+
kMU_Tx1EmptyFlag  +

TX1 empty.

+
kMU_Tx2EmptyFlag  +

TX2 empty.

+
kMU_Tx3EmptyFlag  +

TX3 empty.

+
kMU_Rx0FullFlag  +

RX0 full.

+
kMU_Rx1FullFlag  +

RX1 full.

+
kMU_Rx2FullFlag  +

RX2 full.

+
kMU_Rx3FullFlag  +

RX3 full.

+
kMU_GenInt0Flag  +

General purpose interrupt 0 pending.

+
kMU_GenInt1Flag  +

General purpose interrupt 0 pending.

+
kMU_GenInt2Flag  +

General purpose interrupt 0 pending.

+
kMU_GenInt3Flag  +

General purpose interrupt 0 pending.

+
kMU_EventPendingFlag  +

MU event pending.

+
kMU_FlagsUpdatingFlag  +

MU flags update is on-going.

+
kMU_OtherSideInResetFlag  +

The other side is in reset.

+
+ +
+
+ +
+
+ + + + +
enum _mu_interrupt_enable
+
+ + + + + + + + + + + + + +
Enumerator
kMU_Tx0EmptyInterruptEnable  +

TX0 empty.

+
kMU_Tx1EmptyInterruptEnable  +

TX1 empty.

+
kMU_Tx2EmptyInterruptEnable  +

TX2 empty.

+
kMU_Tx3EmptyInterruptEnable  +

TX3 empty.

+
kMU_Rx0FullInterruptEnable  +

RX0 full.

+
kMU_Rx1FullInterruptEnable  +

RX1 full.

+
kMU_Rx2FullInterruptEnable  +

RX2 full.

+
kMU_Rx3FullInterruptEnable  +

RX3 full.

+
kMU_GenInt0InterruptEnable  +

General purpose interrupt 0.

+
kMU_GenInt1InterruptEnable  +

General purpose interrupt 1.

+
kMU_GenInt2InterruptEnable  +

General purpose interrupt 2.

+
kMU_GenInt3InterruptEnable  +

General purpose interrupt 3.

+
+ +
+
+ +
+
+ + + + +
enum _mu_interrupt_trigger
+
+ + + + + +
Enumerator
kMU_GenInt0InterruptTrigger  +

General purpose interrupt 0.

+
kMU_GenInt1InterruptTrigger  +

General purpose interrupt 1.

+
kMU_GenInt2InterruptTrigger  +

General purpose interrupt 2.

+
kMU_GenInt3InterruptTrigger  +

General purpose interrupt 3.

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
void MU_Init (MU_Type * base)
+
+

This function enables the MU clock only.

+
Parameters
+ + +
baseMU peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void MU_Deinit (MU_Type * base)
+
+

This function disables the MU clock only.

+
Parameters
+ + +
baseMU peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void MU_SendMsgNonBlocking (MU_Type * base,
uint32_t regIndex,
uint32_t msg 
)
+ 		+inlinestatic
+
+

This function writes a message to the specific TX register. It does not check whether the TX register is empty or not. The upper layer should make sure the TX register is empty before calling this function. This function can be used in ISR for better performance.

+
* while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { } Wait for TX0 register empty.
+
* MU_SendMsgNonBlocking(base, 0U, MSG_VAL); Write message to the TX0 register.
+
*
+
Parameters
+ + + + +
baseMU peripheral base address.
regIndexTX register index.
msgMessage to send.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void MU_SendMsg (MU_Type * base,
uint32_t regIndex,
uint32_t msg 
)
+
+

This function waits until the TX register is empty and sends the message.

+
Parameters
+ + + + +
baseMU peripheral base address.
regIndexTX register index.
msgMessage to send.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static uint32_t MU_ReceiveMsgNonBlocking (MU_Type * base,
uint32_t regIndex 
)
+ 		+inlinestatic
+
+

This function reads a message from the specific RX register. It does not check whether the RX register is full or not. The upper layer should make sure the RX register is full before calling this function. This function can be used in ISR for better performance.

+
* uint32_t msg;
+
* while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base)))
+
* {
+
* } Wait for the RX0 register full.
+
*
+
* msg = MU_ReceiveMsgNonBlocking(base, 0U); Read message from RX0 register.
+
*
+
Parameters
+ + + +
baseMU peripheral base address.
regIndexTX register index.
+
+
+
Returns
The received message.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t MU_ReceiveMsg (MU_Type * base,
uint32_t regIndex 
)
+
+

This function waits until the RX register is full and receives the message.

+
Parameters
+ + + +
baseMU peripheral base address.
regIndexRX register index.
+
+
+
Returns
The received message.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void MU_SetFlagsNonBlocking (MU_Type * base,
uint32_t flags 
)
+ 		+inlinestatic
+
+

This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. The upper layer should make sure the status flag kMU_FlagsUpdatingFlag is cleared before calling this function.

+
* while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base))
+
* {
+
* } Wait for previous MU flags updating.
+
*
+
* MU_SetFlagsNonBlocking(base, 0U); Set the mU flags.
+
*
+
Parameters
+ + + +
baseMU peripheral base address.
flagsThe 3-bit MU flags to set.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void MU_SetFlags (MU_Type * base,
uint32_t flags 
)
+
+

This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. This function waits for the MU status flag kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags.

+
Parameters
+ + + +
baseMU peripheral base address.
flagsThe 3-bit MU flags to set.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t MU_GetFlags (MU_Type * base)
+ 		+inlinestatic
+
+

This function gets the current 3-bit MU flags on the current side.

+
Parameters
+ + +
baseMU peripheral base address.
+
+
+
Returns
flags Current value of the 3-bit flags.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t MU_GetStatusFlags (MU_Type * base)
+ 		+inlinestatic
+
+

This function returns the bit mask of the MU status flags. See _mu_status_flags.

+
* uint32_t flags;
+
* flags = MU_GetStatusFlags(base); Get all status flags.
+
* if (kMU_Tx0EmptyFlag & flags)
+
* {
+
* The TX0 register is empty. Message can be sent.
+
* MU_SendMsgNonBlocking(base, 0U, MSG0_VAL);
+
* }
+
* if (kMU_Tx1EmptyFlag & flags)
+
* {
+
* The TX1 register is empty. Message can be sent.
+
* MU_SendMsgNonBlocking(base, 1U, MSG1_VAL);
+
* }
+
*
+
Parameters
+ + +
baseMU peripheral base address.
+
+
+
Returns
Bit mask of the MU status flags, see _mu_status_flags.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static uint32_t MU_GetInterruptsPending (MU_Type * base)
+ 		+inlinestatic
+
+

This function returns the bit mask of the pending MU IRQs.

+
Parameters
+ + +
baseMU peripheral base address.
+
+
+
Returns
Bit mask of the MU IRQs pending.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void MU_ClearStatusFlags (MU_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+

This function clears the specific MU status flags. The flags to clear should be passed in as bit mask. See _mu_status_flags.

+
* Clear general interrupt 0 and general interrupt 1 pending flags.
+
* MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag);
+
*
+
Parameters
+ + + +
baseMU peripheral base address.
maskBit mask of the MU status flags. See _mu_status_flags. The following flags are cleared by hardware, this function could not clear them.
    +
  • kMU_Tx0EmptyFlag
    • +
  • kMU_Tx1EmptyFlag
    • +
  • kMU_Tx2EmptyFlag
    • +
  • kMU_Tx3EmptyFlag
    • +
  • kMU_Rx0FullFlag
    • +
  • kMU_Rx1FullFlag
    • +
  • kMU_Rx2FullFlag
    • +
  • kMU_Rx3FullFlag
    • +
  • kMU_EventPendingFlag
    • +
  • kMU_FlagsUpdatingFlag
    • +
  • kMU_OtherSideInResetFlag
    • +
+
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void MU_EnableInterrupts (MU_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+

This function enables the specific MU interrupts. The interrupts to enable should be passed in as bit mask. See _mu_interrupt_enable.

+
* Enable general interrupt 0 and TX0 empty interrupt.
+
* MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);
+
*
+
Parameters
+ + + +
baseMU peripheral base address.
maskBit mask of the MU interrupts. See _mu_interrupt_enable.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void MU_DisableInterrupts (MU_Type * base,
uint32_t mask 
)
+ 		+inlinestatic
+
+

This function disables the specific MU interrupts. The interrupts to disable should be passed in as bit mask. See _mu_interrupt_enable.

+
* Disable general interrupt 0 and TX0 empty interrupt.
+
* MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);
+
*
+
Parameters
+ + + +
baseMU peripheral base address.
maskBit mask of the MU interrupts. See _mu_interrupt_enable.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t MU_TriggerInterrupts (MU_Type * base,
uint32_t mask 
)
+
+

This function triggers the specific interrupts to the other core. The interrupts to trigger are passed in as bit mask. See _mu_interrupt_trigger. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.

+
* if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger))
+
* {
+
* Previous general purpose interrupt 0 or general purpose interrupt 2
+
* has not been processed by the other core.
+
* }
+
*
+
Parameters
+ + + +
baseMU peripheral base address.
maskBit mask of the interrupts to trigger. See _mu_interrupt_trigger.
+
+
+
Return values
+ + + +
kStatus_SuccessInterrupts have been triggered successfully.
kStatus_FailPrevious interrupts have not been accepted.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void MU_MaskHardwareReset (MU_Type * base,
bool mask 
)
+ 		+inlinestatic
+
+

The other core could call MU_HardwareResetOtherCore() to reset current core. To mask the reset, call this function and pass in true.

+
Parameters
+ + + +
baseMU peripheral base address.
maskPass true to mask the hardware reset, pass false to unmask it.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static mu_power_mode_t MU_GetOtherCorePowerMode (MU_Type * base)
+ 		+inlinestatic
+
+

This function gets the power mode of the other core.

+
Parameters
+ + +
baseMU peripheral base address.
+
+
+
Returns
Power mode of the other core.
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00096.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00096.js new file mode 100644 index 000000000..6a1958abb --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00096.js @@ -0,0 +1,58 @@ +var a00096 = +[ + [ "FSL_MU_DRIVER_VERSION", "a00096.html#gac08525378e7d8aaa3e0e6b16e9f76ad3", null ], + [ "_mu_status_flags", "a00096.html#gae0771a3d173c2b3bf358aff30664f8bf", [ + [ "kMU_Tx0EmptyFlag", "a00096.html#ggae0771a3d173c2b3bf358aff30664f8bfa8c78ea862685cbf3168dd556137f481b", null ], + [ "kMU_Tx1EmptyFlag", "a00096.html#ggae0771a3d173c2b3bf358aff30664f8bfa02c68cfbe97c75fcc1a84d931f5d2e3d", null ], + [ "kMU_Tx2EmptyFlag", "a00096.html#ggae0771a3d173c2b3bf358aff30664f8bfa767f1b8e0e39543921f1a140efb9e154", null ], + [ "kMU_Tx3EmptyFlag", "a00096.html#ggae0771a3d173c2b3bf358aff30664f8bfa8f0e3eeb71299fce34d2fb31524d223f", null ], + [ "kMU_Rx0FullFlag", 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"a00096.html#ggae0771a3d173c2b3bf358aff30664f8bfad2f4fdc37e185dd77f42ae824a334197", null ], + [ "kMU_FlagsUpdatingFlag", "a00096.html#ggae0771a3d173c2b3bf358aff30664f8bfa2c98f3deffd6aeb55701cf98bbe2936a", null ], + [ "kMU_OtherSideInResetFlag", "a00096.html#ggae0771a3d173c2b3bf358aff30664f8bfa7ee78bc085c8be00c5997fe1a7b5f3d2", null ] + ] ], + [ "_mu_interrupt_enable", "a00096.html#gabd070b1725280439337373fcd5934931", [ + [ "kMU_Tx0EmptyInterruptEnable", "a00096.html#ggabd070b1725280439337373fcd5934931a168101d14f235b5601e4d87b426338ac", null ], + [ "kMU_Tx1EmptyInterruptEnable", "a00096.html#ggabd070b1725280439337373fcd5934931a818770dd5a82087b90347dc8822e03f8", null ], + [ "kMU_Tx2EmptyInterruptEnable", "a00096.html#ggabd070b1725280439337373fcd5934931a7a4a0c0d7df99a19b2c09ece2458a83f", null ], + [ "kMU_Tx3EmptyInterruptEnable", "a00096.html#ggabd070b1725280439337373fcd5934931a7e01176f783c0895365517dedad4e66e", null ], + [ "kMU_Rx0FullInterruptEnable", "a00096.html#ggabd070b1725280439337373fcd5934931a4b7915f891336860a5288404c040627d", null ], + [ "kMU_Rx1FullInterruptEnable", "a00096.html#ggabd070b1725280439337373fcd5934931ab2a2f081c353728fb56f3895e4615670", null ], + [ "kMU_Rx2FullInterruptEnable", "a00096.html#ggabd070b1725280439337373fcd5934931a1e73d223a485610347f2ab818a95c0b7", null ], + [ "kMU_Rx3FullInterruptEnable", "a00096.html#ggabd070b1725280439337373fcd5934931a493732db72b70452f893a1bdbe9b4c10", null ], + [ "kMU_GenInt0InterruptEnable", "a00096.html#ggabd070b1725280439337373fcd5934931ab695880fd49642db0667884453ce0de5", null ], + [ "kMU_GenInt1InterruptEnable", "a00096.html#ggabd070b1725280439337373fcd5934931a0f9b9c7651fa7770aef0bff12726ea23", null ], + [ "kMU_GenInt2InterruptEnable", "a00096.html#ggabd070b1725280439337373fcd5934931a99744e6b9c80212cee08887bdb8c7e16", null ], + [ "kMU_GenInt3InterruptEnable", "a00096.html#ggabd070b1725280439337373fcd5934931aa961c2b4ea26a5de52d61f819356a37b", null ] + ] ], + [ "_mu_interrupt_trigger", "a00096.html#ga41108bad4d5d228e3832b2739e982084", [ + [ "kMU_GenInt0InterruptTrigger", "a00096.html#gga41108bad4d5d228e3832b2739e982084a55c2d4c3d2065504f7edb30553c86a53", null ], + [ "kMU_GenInt1InterruptTrigger", "a00096.html#gga41108bad4d5d228e3832b2739e982084af8c229732fcaef64ad86d0111a37e349", null ], + [ "kMU_GenInt2InterruptTrigger", "a00096.html#gga41108bad4d5d228e3832b2739e982084a3e107a42c4bb962e9736c46dc8fb4c20", null ], + [ "kMU_GenInt3InterruptTrigger", "a00096.html#gga41108bad4d5d228e3832b2739e982084a9307f291207c5f5e83bd6baff07234f2", null ] + ] ], + [ "MU_Init", "a00096.html#ga59dde6d6ef6bd1016eafe1e6faf7a6d9", null ], + [ "MU_Deinit", "a00096.html#ga956ac92cddf9794a9155b346f4db2044", null ], + [ "MU_SendMsgNonBlocking", "a00096.html#gae4e41714bd6cf6e3de866e1aaf5b85a2", null ], + [ "MU_SendMsg", "a00096.html#gaedd7d1f0418441a61a2587a8db322ecd", null ], + [ "MU_ReceiveMsgNonBlocking", "a00096.html#gabeb32b60cedae555c659126d75bda806", null ], + [ "MU_ReceiveMsg", "a00096.html#ga36b003e10632eed908184ddbfc48df25", null ], + [ "MU_SetFlagsNonBlocking", "a00096.html#ga180ad60fda7f03cbcd98543bdb808a43", null ], + [ "MU_SetFlags", "a00096.html#ga392ac71819def4a3e9d34fd1daf3fff0", null ], + [ "MU_GetFlags", "a00096.html#ga4fbbf69b6157a909bcf6bb9523419834", null ], + [ "MU_GetStatusFlags", "a00096.html#ga90e31d91ebb2a97c4b8ac449bb4e2a4e", null ], + [ "MU_GetInterruptsPending", "a00096.html#ga1a04c3768d3a4b611a3b2a5c4e8799eb", null ], + [ "MU_ClearStatusFlags", "a00096.html#gae9097788e142b8cb891eddfcbfc60c26", null ], + [ "MU_EnableInterrupts", "a00096.html#ga5ea7e2b8b70b2f7a44013e9a8dded335", null ], + [ "MU_DisableInterrupts", "a00096.html#gaecadc0cf75fd66e80737b33c0971cbca", null ], + [ "MU_TriggerInterrupts", "a00096.html#ga1c78b4336b2f9ef4a4ca8ff22be7116c", null ], + [ "MU_MaskHardwareReset", "a00096.html#gac6dd57592c5d5fa10e7354adc1cad37d", null ], + [ "MU_GetOtherCorePowerMode", "a00096.html#ga4c9449aca64b03c381ae1b7e1720c61b", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00097.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00097.html new file mode 100644 index 000000000..fea315940 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00097.html @@ -0,0 +1,129 @@ + + + + + + +MCUXpresso SDK API Reference Manual: QSPI: Quad Serial Peripheral Interface + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Modules
+
+
QSPI: Quad Serial Peripheral Interface
+
+
+

Overview

+

The MCUXpresso SDK provides a peripheral driver for the Quad Serial Peripheral Interface (QSPI) module of MCUXpresso SDK devices.

+

QSPI driver includes functional APIs and EDMA transactional APIs.

+

Functional APIs are feature/property target low level APIs. Functional APIs can be used for QSPI initialization/configuration/operation for optimization/customization purpose. Using the functional API requires the knowledge of the QSPI peripheral and how to organize functional APIs to meet the application requirements. All functional API use the peripheral base address as the first parameter. QSPI functional operation groups provide the functional API set.

+

Transactional APIs are transaction target high level APIs. Transactional APIs can be used to enable the peripheral and in the application if the code size and performance of transactional APIs satisfy the requirements. If the code size and performance are a critical requirement, see the transactional API implementation and write a custom code. All transactional APIs use the qspi_handle_t as the first parameter. Initialize the handle by calling the QSPI_TransferTxCreateHandleEDMA() or QSPI_TransferRxCreateHandleEDMA() API.

+ + + + +

+Modules

 Quad Serial Peripheral Interface Driver
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00097.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00097.js new file mode 100644 index 000000000..61eb850cf --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00097.js @@ -0,0 +1,4 @@ +var a00097 = +[ + [ "Quad Serial Peripheral Interface Driver", "a00014.html", "a00014" ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00098.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00098.html new file mode 100644 index 000000000..9b64df4ef --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00098.html @@ -0,0 +1,574 @@ + + + + + + +MCUXpresso SDK API Reference Manual: RDC_SEMA42: Hardware Semaphores Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
RDC_SEMA42: Hardware Semaphores Driver
+
+
+

Overview

+

The MCUXpresso SDK provides a driver for the RDC_SEMA42 module of MCUXpresso SDK devices.

+

The RDC_SEMA42 driver should be used together with RDC driver.
+ Before using the RDC_SEMA42, call the RDC_SEMA42_Init() function to initialize the module. Note that this function only enables the clock but does not reset the gates because the module might be used by other processors at the same time. To reset the gates, call either the RDC_SEMA42_ResetGate() or RDC_SEMA42_ResetAllGates() functions. The function RDC_SEMA42_Deinit() deinitializes the RDC_SEMA42.
+ The RDC_SEMA42 provides two functions to lock the RDC_SEMA42 gate. The function RDC_SEMA42_TryLock() tries to lock the gate. If the gate has been locked by another processor, this function returns an error immediately. The function RDC_SEMA42_Lock() is a blocking method, which waits until the gate is free and locks it.
+ The RDC_SEMA42_Unlock() unlocks the RDC_SEMA42 gate. The gate can only be unlocked by the processor which locked it. If the gate is not locked by the current processor, this function takes no effect. The function RDC_SEMA42_GetGateStatus() returns a status whether the gate is unlocked and which processor locks the gate. The function RDC_SEMA42_GetLockDomainID() returns the ID of the domain which has locked the gate.
+ The RDC_SEMA42 gate can be reset to unlock forcefully. The function RDC_SEMA42_ResetGate() resets a specific gate. The function RDC_SEMA42_ResetAllGates() resets all gates.

+ + + + + + + + + + + +

+Macros

#define RDC_SEMA42_GATE_NUM_RESET_ALL   (64U)
 The number to reset all RDC_SEMA42 gates. More...
 
#define RDC_SEMA42_GATEn(base, n)   (((volatile uint8_t *)(&((base)->GATE0)))[(n)])
 RDC_SEMA42 gate n register address. More...
 
#define RDC_SEMA42_GATE_COUNT   (64U)
 RDC_SEMA42 gate count. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void RDC_SEMA42_Init (RDC_SEMAPHORE_Type *base)
 Initializes the RDC_SEMA42 module. More...
 
void RDC_SEMA42_Deinit (RDC_SEMAPHORE_Type *base)
 De-initializes the RDC_SEMA42 module. More...
 
status_t RDC_SEMA42_TryLock (RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId)
 Tries to lock the RDC_SEMA42 gate. More...
 
void RDC_SEMA42_Lock (RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId)
 Locks the RDC_SEMA42 gate. More...
 
static void RDC_SEMA42_Unlock (RDC_SEMAPHORE_Type *base, uint8_t gateNum)
 Unlocks the RDC_SEMA42 gate. More...
 
static int32_t RDC_SEMA42_GetLockMasterIndex (RDC_SEMAPHORE_Type *base, uint8_t gateNum)
 Gets which master has currently locked the gate. More...
 
int32_t RDC_SEMA42_GetLockDomainID (RDC_SEMAPHORE_Type *base, uint8_t gateNum)
 Gets which domain has currently locked the gate. More...
 
status_t RDC_SEMA42_ResetGate (RDC_SEMAPHORE_Type *base, uint8_t gateNum)
 Resets the RDC_SEMA42 gate to an unlocked status. More...
 
static status_t RDC_SEMA42_ResetAllGates (RDC_SEMAPHORE_Type *base)
 Resets all RDC_SEMA42 gates to an unlocked status. More...
 
+ + + + +

+Driver version

+#define FSL_RDC_SEMA42_DRIVER_VERSION   (MAKE_VERSION(2, 0, 3))
 RDC_SEMA42 driver version.
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define RDC_SEMA42_GATE_NUM_RESET_ALL   (64U)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define RDC_SEMA42_GATEn( base,
 n 
)   (((volatile uint8_t *)(&((base)->GATE0)))[(n)])
+
+ +
+
+ +
+
+ + + + +
#define RDC_SEMA42_GATE_COUNT   (64U)
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
void RDC_SEMA42_Init (RDC_SEMAPHORE_Type * base)
+
+

This function initializes the RDC_SEMA42 module. It only enables the clock but does not reset the gates because the module might be used by other processors at the same time. To reset the gates, call either RDC_SEMA42_ResetGate or RDC_SEMA42_ResetAllGates function.

+
Parameters
+ + +
baseRDC_SEMA42 peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RDC_SEMA42_Deinit (RDC_SEMAPHORE_Type * base)
+
+

This function de-initializes the RDC_SEMA42 module. It only disables the clock.

+
Parameters
+ + +
baseRDC_SEMA42 peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
status_t RDC_SEMA42_TryLock (RDC_SEMAPHORE_Type * base,
uint8_t gateNum,
uint8_t masterIndex,
uint8_t domainId 
)
+
+

This function tries to lock the specific RDC_SEMA42 gate. If the gate has been locked by another processor, this function returns an error code.

+
Parameters
+ + + + + +
baseRDC_SEMA42 peripheral base address.
gateNumGate number to lock.
masterIndexCurrent processor master index.
domainIdCurrent processor domain ID.
+
+
+
Return values
+ + + +
kStatus_SuccessLock the sema42 gate successfully.
kStatus_FailedSema42 gate has been locked by another processor.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void RDC_SEMA42_Lock (RDC_SEMAPHORE_Type * base,
uint8_t gateNum,
uint8_t masterIndex,
uint8_t domainId 
)
+
+

This function locks the specific RDC_SEMA42 gate. If the gate has been locked by other processors, this function waits until it is unlocked and then lock it.

+
Parameters
+ + + + + +
baseRDC_SEMA42 peripheral base address.
gateNumGate number to lock.
masterIndexCurrent processor master index.
domainIdCurrent processor domain ID.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void RDC_SEMA42_Unlock (RDC_SEMAPHORE_Type * base,
uint8_t gateNum 
)
+ 		+inlinestatic
+
+

This function unlocks the specific RDC_SEMA42 gate. It only writes unlock value to the RDC_SEMA42 gate register. However, it does not check whether the RDC_SEMA42 gate is locked by the current processor or not. As a result, if the RDC_SEMA42 gate is not locked by the current processor, this function has no effect.

+
Parameters
+ + + +
baseRDC_SEMA42 peripheral base address.
gateNumGate number to unlock.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static int32_t RDC_SEMA42_GetLockMasterIndex (RDC_SEMAPHORE_Type * base,
uint8_t gateNum 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
baseRDC_SEMA42 peripheral base address.
gateNumGate number.
+
+
+
Returns
Return -1 if the gate is not locked by any master, otherwise return the master index.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int32_t RDC_SEMA42_GetLockDomainID (RDC_SEMAPHORE_Type * base,
uint8_t gateNum 
)
+
+
Parameters
+ + + +
baseRDC_SEMA42 peripheral base address.
gateNumGate number.
+
+
+
Returns
Return -1 if the gate is not locked by any domain, otherwise return the domain ID.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t RDC_SEMA42_ResetGate (RDC_SEMAPHORE_Type * base,
uint8_t gateNum 
)
+
+

This function resets a RDC_SEMA42 gate to an unlocked status.

+
Parameters
+ + + +
baseRDC_SEMA42 peripheral base address.
gateNumGate number.
+
+
+
Return values
+ + + +
kStatus_SuccessRDC_SEMA42 gate is reset successfully.
kStatus_FailedSome other reset process is ongoing.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static status_t RDC_SEMA42_ResetAllGates (RDC_SEMAPHORE_Type * base)
+ 		+inlinestatic
+
+

This function resets all RDC_SEMA42 gate to an unlocked status.

+
Parameters
+ + +
baseRDC_SEMA42 peripheral base address.
+
+
+
Return values
+ + + +
kStatus_SuccessRDC_SEMA42 is reset successfully.
kStatus_RDC_SEMA42_ResetingSome other reset process is ongoing.
+
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00098.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00098.js new file mode 100644 index 000000000..907ead686 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00098.js @@ -0,0 +1,16 @@ +var a00098 = +[ + [ "FSL_RDC_SEMA42_DRIVER_VERSION", "a00098.html#gaa6cac37b3ebec11ac45076d374d6a93e", null ], + [ "RDC_SEMA42_GATE_NUM_RESET_ALL", "a00098.html#ga2e1384ab2be0f1a97f5e4eda2d12ceaf", null ], + [ "RDC_SEMA42_GATEn", "a00098.html#ga857f01bed307b5d333bd793429b59037", null ], + [ "RDC_SEMA42_GATE_COUNT", "a00098.html#ga09a33a01fde064c69b0ee9eec91b0c1a", null ], + [ "RDC_SEMA42_Init", "a00098.html#ga5b8154d8b24ac1dfd1b1d2bb10158ec0", null ], + [ "RDC_SEMA42_Deinit", "a00098.html#ga1a2c1f1889cdd9c2d4410a9fffe226d9", null ], + [ "RDC_SEMA42_TryLock", "a00098.html#ga85fb981fbe35995485b419091c06583c", null ], + [ "RDC_SEMA42_Lock", "a00098.html#ga55f710fde1530472af83d2192a1003d6", null ], + [ "RDC_SEMA42_Unlock", "a00098.html#ga24343ed74b1ac14f1ef6ee2bf9981787", null ], + [ "RDC_SEMA42_GetLockMasterIndex", "a00098.html#ga0335914d7ba08830da16f7110d2e2ddc", null ], + [ "RDC_SEMA42_GetLockDomainID", "a00098.html#gac2bc50ca8bb908c88f0eedba0bc2f3f2", null ], + [ "RDC_SEMA42_ResetGate", "a00098.html#ga756f7f9c12750a30c2ab26271371108d", null ], + [ "RDC_SEMA42_ResetAllGates", "a00098.html#gae72a0e282cf4c612ff7f2e55954cd2fd", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00099.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00099.html new file mode 100644 index 000000000..dae35ac91 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00099.html @@ -0,0 +1,144 @@ + + + + + + +MCUXpresso SDK API Reference Manual: SAI: Serial Audio Interface + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Modules
+
+
SAI: Serial Audio Interface
+
+
+

Overview

+

The MCUXpresso SDK provides a peripheral driver for the Serial Audio Interface (SAI) module of MCUXpresso SDK devices.

+

SAI driver includes functional APIs and transactional APIs.

+

Functional APIs target low-level APIs. Functional APIs can be used for SAI initialization, configuration and operation, and for optimization and customization purposes. Using the functional API requires the knowledge of the SAI peripheral and how to organize functional APIs to meet the application requirements. All functional API use the peripheral base address as the first parameter. SAI functional operation groups provide the functional API set.

+

Transactional APIs target high-level APIs. Transactional APIs can be used to enable the peripheral and in the application if the code size and performance of transactional APIs satisfy the requirements. If the code size and performance are a critical requirement, see the transactional API implementation and write a custom code. All transactional APIs use the sai_handle_t as the first parameter. Initialize the handle by calling the SAI_TransferTxCreateHandle() or SAI_TransferRxCreateHandle() API.

+

Transactional APIs support asynchronous transfer. This means that the functions SAI_TransferSendNonBlocking() and SAI_TransferReceiveNonBlocking() set up the interrupt for data transfer. When the transfer completes, the upper layer is notified through a callback function with the kStatus_SAI_TxIdle and kStatus_SAI_RxIdle status.

+

+Typical configurations

+

Bit width configuration

+

SAI driver support 8/16/24/32bits stereo/mono raw audio data transfer. SAI EDMA driver support 8/16/32bits stereo/mono raw audio data transfer, since the EDMA doesn't support 24bit data width, so application should pre-convert the 24bit data to 32bit. SAI DMA driver support 8/16/32bits stereo/mono raw audio data transfer, since the EDMA doesn't support 24bit data width, so application should pre-convert the 24bit data to 32bit. SAI SDMA driver support 8/16/24/32bits stereo/mono raw audio data transfer.

+

Frame configuration

+

SAI driver support I2S, DSP, Left justified, Right justified, TDM mode. Application can call the api directly: SAI_GetClassicI2SConfig SAI_GetLeftJustifiedConfig SAI_GetRightJustifiedConfig SAI_GetTDMConfig SAI_GetDSPConfig

+

+Typical use case

+

+SAI Send/receive using an interrupt method

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/sai

+

+SAI Send/receive using a DMA method

+

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/sai

+ + + + +

+Modules

 SAI Driver
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00099.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00099.js new file mode 100644 index 000000000..24ac5d83f --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00099.js @@ -0,0 +1,4 @@ +var a00099 = +[ + [ "SAI Driver", "a00016.html", "a00016" ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00100.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00100.html new file mode 100644 index 000000000..3a564536c --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00100.html @@ -0,0 +1,116 @@ + + + + + + +MCUXpresso SDK API Reference Manual: SAI EDMA Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
SAI EDMA Driver
+
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00101.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00101.html new file mode 100644 index 000000000..d924c3ea8 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00101.html @@ -0,0 +1,714 @@ + + + + + + +MCUXpresso SDK API Reference Manual: SEMA4: Hardware Semaphores Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
SEMA4: Hardware Semaphores Driver
+
+
+

Overview

+

The MCUXpresso SDK provides a driver for the SEMA4 module of MCUXpresso SDK devices.

+ + + + + + + + +

+Macros

#define SEMA4_GATE_NUM_RESET_ALL   (64U)
 The number to reset all SEMA4 gates. More...
 
+#define SEMA4_GATEn(base, n)   (((volatile uint8_t *)(&((base)->Gate00)))[(n)])
 SEMA4 gate n register address.
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SEMA4_Init (SEMA4_Type *base)
 Initializes the SEMA4 module. More...
 
void SEMA4_Deinit (SEMA4_Type *base)
 De-initializes the SEMA4 module. More...
 
status_t SEMA4_TryLock (SEMA4_Type *base, uint8_t gateNum, uint8_t procNum)
 Tries to lock the SEMA4 gate. More...
 
void SEMA4_Lock (SEMA4_Type *base, uint8_t gateNum, uint8_t procNum)
 Locks the SEMA4 gate. More...
 
static void SEMA4_Unlock (SEMA4_Type *base, uint8_t gateNum)
 Unlocks the SEMA4 gate. More...
 
static int32_t SEMA4_GetLockProc (SEMA4_Type *base, uint8_t gateNum)
 Gets the status of the SEMA4 gate. More...
 
status_t SEMA4_ResetGate (SEMA4_Type *base, uint8_t gateNum)
 Resets the SEMA4 gate to an unlocked status. More...
 
static status_t SEMA4_ResetAllGates (SEMA4_Type *base)
 Resets all SEMA4 gates to an unlocked status. More...
 
static void SEMA4_EnableGateNotifyInterrupt (SEMA4_Type *base, uint8_t procNum, uint32_t mask)
 Enable the gate notification interrupt. More...
 
static void SEMA4_DisableGateNotifyInterrupt (SEMA4_Type *base, uint8_t procNum, uint32_t mask)
 Disable the gate notification interrupt. More...
 
static uint32_t SEMA4_GetGateNotifyStatus (SEMA4_Type *base, uint8_t procNum)
 Get the gate notification flags. More...
 
status_t SEMA4_ResetGateNotify (SEMA4_Type *base, uint8_t gateNum)
 Resets the SEMA4 gate IRQ notification. More...
 
static status_t SEMA4_ResetAllGateNotify (SEMA4_Type *base)
 Resets all SEMA4 gates IRQ notification. More...
 
+ + + + +

+Driver version

+#define FSL_SEMA4_DRIVER_VERSION   (MAKE_VERSION(2, 0, 2))
 SEMA4 driver version.
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define SEMA4_GATE_NUM_RESET_ALL   (64U)
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
void SEMA4_Init (SEMA4_Type * base)
+
+

This function initializes the SEMA4 module. It only enables the clock but does not reset the gates because the module might be used by other processors at the same time. To reset the gates, call either SEMA4_ResetGate or SEMA4_ResetAllGates function.

+
Parameters
+ + +
baseSEMA4 peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SEMA4_Deinit (SEMA4_Type * base)
+
+

This function de-initializes the SEMA4 module. It only disables the clock.

+
Parameters
+ + +
baseSEMA4 peripheral base address.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t SEMA4_TryLock (SEMA4_Type * base,
uint8_t gateNum,
uint8_t procNum 
)
+
+

This function tries to lock the specific SEMA4 gate. If the gate has been locked by another processor, this function returns an error code.

+
Parameters
+ + + + +
baseSEMA4 peripheral base address.
gateNumGate number to lock.
procNumCurrent processor number.
+
+
+
Return values
+ + + +
kStatus_SuccessLock the sema4 gate successfully.
kStatus_FailSema4 gate has been locked by another processor.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void SEMA4_Lock (SEMA4_Type * base,
uint8_t gateNum,
uint8_t procNum 
)
+
+

This function locks the specific SEMA4 gate. If the gate has been locked by other processors, this function waits until it is unlocked and then lock it.

+
Parameters
+ + + + +
baseSEMA4 peripheral base address.
gateNumGate number to lock.
procNumCurrent processor number.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void SEMA4_Unlock (SEMA4_Type * base,
uint8_t gateNum 
)
+ 		+inlinestatic
+
+

This function unlocks the specific SEMA4 gate. It only writes unlock value to the SEMA4 gate register. However, it does not check whether the SEMA4 gate is locked by the current processor or not. As a result, if the SEMA4 gate is not locked by the current processor, this function has no effect.

+
Parameters
+ + + +
baseSEMA4 peripheral base address.
gateNumGate number to unlock.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static int32_t SEMA4_GetLockProc (SEMA4_Type * base,
uint8_t gateNum 
)
+ 		+inlinestatic
+
+

This function checks the lock status of a specific SEMA4 gate.

+
Parameters
+ + + +
baseSEMA4 peripheral base address.
gateNumGate number.
+
+
+
Returns
Return -1 if the gate is unlocked, otherwise return the processor number which has locked the gate.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t SEMA4_ResetGate (SEMA4_Type * base,
uint8_t gateNum 
)
+
+

This function resets a SEMA4 gate to an unlocked status.

+
Parameters
+ + + +
baseSEMA4 peripheral base address.
gateNumGate number.
+
+
+
Return values
+ + + +
kStatus_SuccessSEMA4 gate is reset successfully.
kStatus_FailSome other reset process is ongoing.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static status_t SEMA4_ResetAllGates (SEMA4_Type * base)
+ 		+inlinestatic
+
+

This function resets all SEMA4 gate to an unlocked status.

+
Parameters
+ + +
baseSEMA4 peripheral base address.
+
+
+
Return values
+ + + +
kStatus_SuccessSEMA4 is reset successfully.
kStatus_FailSome other reset process is ongoing.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void SEMA4_EnableGateNotifyInterrupt (SEMA4_Type * base,
uint8_t procNum,
uint32_t mask 
)
+ 		+inlinestatic
+
+

Gate notification provides such feature, when core tried to lock the gate and failed, it could get notification when the gate is idle.

+
Parameters
+ + + + +
baseSEMA4 peripheral base address.
procNumCurrent processor number.
maskOR'ed value of the gate index, for example: (1<<0) | (1<<1) means gate 0 and gate 1.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static void SEMA4_DisableGateNotifyInterrupt (SEMA4_Type * base,
uint8_t procNum,
uint32_t mask 
)
+ 		+inlinestatic
+
+

Gate notification provides such feature, when core tried to lock the gate and failed, it could get notification when the gate is idle.

+
Parameters
+ + + + +
baseSEMA4 peripheral base address.
procNumCurrent processor number.
maskOR'ed value of the gate index, for example: (1<<0) | (1<<1) means gate 0 and gate 1.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static uint32_t SEMA4_GetGateNotifyStatus (SEMA4_Type * base,
uint8_t procNum 
)
+ 		+inlinestatic
+
+

Gate notification provides such feature, when core tried to lock the gate and failed, it could get notification when the gate is idle. The status flags are cleared automatically when the gate is locked by current core or locked again before the other core.

+
Parameters
+ + + +
baseSEMA4 peripheral base address.
procNumCurrent processor number.
+
+
+
Returns
OR'ed value of the gate index, for example: (1<<0) | (1<<1) means gate 0 and gate 1 flags are pending.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t SEMA4_ResetGateNotify (SEMA4_Type * base,
uint8_t gateNum 
)
+
+

This function resets a SEMA4 gate IRQ notification.

+
Parameters
+ + + +
baseSEMA4 peripheral base address.
gateNumGate number.
+
+
+
Return values
+ + + +
kStatus_SuccessReset successfully.
kStatus_FailSome other reset process is ongoing.
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static status_t SEMA4_ResetAllGateNotify (SEMA4_Type * base)
+ 		+inlinestatic
+
+

This function resets all SEMA4 gate IRQ notifications.

+
Parameters
+ + +
baseSEMA4 peripheral base address.
+
+
+
Return values
+ + + +
kStatus_SuccessReset successfully.
kStatus_FailSome other reset process is ongoing.
+
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00101.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00101.js new file mode 100644 index 000000000..48b16091d --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00101.js @@ -0,0 +1,19 @@ +var a00101 = +[ + [ "FSL_SEMA4_DRIVER_VERSION", "a00101.html#ga1bb7148a101cd7925e5271374862802e", null ], + [ "SEMA4_GATE_NUM_RESET_ALL", "a00101.html#gacb7a70c49148b0186f0eaa3fe910ba79", null ], + [ "SEMA4_GATEn", "a00101.html#gaf1811869c70952983fa9cbd5aef3e933", null ], + [ "SEMA4_Init", "a00101.html#gac6380ed053744f451c5175db29f9f3d9", null ], + [ "SEMA4_Deinit", "a00101.html#gafc7188cb89c7522813d6be66f97c7e35", null ], + [ "SEMA4_TryLock", "a00101.html#ga30d848a2ce959c29af0f13bf8f0ee1dc", null ], + [ "SEMA4_Lock", "a00101.html#gae5ca0fa4f34ac84b2c3df0abeeadd9c0", null ], + [ "SEMA4_Unlock", "a00101.html#ga1c34c4b2eca52767539b73647e866e7f", null ], + [ "SEMA4_GetLockProc", "a00101.html#ga9869fbc634dce9bd292f85bd09661d37", null ], + [ "SEMA4_ResetGate", "a00101.html#gae5c7bc935b02303f51a8254886acff76", null ], + [ "SEMA4_ResetAllGates", "a00101.html#ga4d466ad087825369aeaa611140dccf55", null ], + [ "SEMA4_EnableGateNotifyInterrupt", "a00101.html#ga06ad2e8a81e220aefac8c9a2b49ce1cb", null ], + [ "SEMA4_DisableGateNotifyInterrupt", "a00101.html#gac3168fbde7570fc0ce56a92a8eb335fb", null ], + [ "SEMA4_GetGateNotifyStatus", "a00101.html#ga0ed4770fa9e88d5abb4b94a775e7db2b", null ], + [ "SEMA4_ResetGateNotify", "a00101.html#gab648c6d8479df0890ba2d654f0193f7a", null ], + [ "SEMA4_ResetAllGateNotify", "a00101.html#gaef68d23981bfc1c2fbbb823b28976353", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00102.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00102.html new file mode 100644 index 000000000..128da892a --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00102.html @@ -0,0 +1,860 @@ + + + + + + +MCUXpresso SDK API Reference Manual: Debug Console + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Modules | +Macros | +Typedefs | +Functions | +Variables
+
+
Debug Console
+
+
+

Overview

+

This chapter describes the programming interface of the debug console driver.

+

The debug console enables debug log messages to be output via the specified peripheral with frequency of the peripheral source clock and base address at the specified baud rate. Additionally, it provides input and output functions to scan and print formatted data. The below picture shows the laylout of debug console.

+
+debug_console_overview.jpg +
+

+Function groups

+

+Initialization

+

To initialize the debug console, call the DbgConsole_Init() function with these parameters. This function automatically enables the module and the clock.

+
+
status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);
+

Select the supported debug console hardware device type, such as

+
typedef enum _serial_port_type
+
{
+
kSerialPort_Uart = 1U,
+
kSerialPort_UsbCdc,
+
kSerialPort_Swo,
+
} serial_port_type_t;
+

After the initialization is successful, stdout and stdin are connected to the selected peripheral.

+

This example shows how to call the DbgConsole_Init() given the user configuration structure.

+
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE,
+
BOARD_DEBUG_UART_CLK_FREQ);
+

+Advanced Feature

+

The debug console provides input and output functions to scan and print formatted data.

+
    +
  • Support a format specifier for PRINTF following this prototype " %[flags][width][.precision][length]specifier", which is explained below
    • +
+
+ + + + + + + + + + + + +
flags Description
- Left-justified within the given field width. Right-justified is the default.
+ Forces to precede the result with a plus or minus sign (+ or -) even for positive numbers. By default, only negative numbers are preceded with a - sign.
(space) If no sign is written, a blank space is inserted before the value.
# Used with o, x, or X specifiers the value is preceded with 0, 0x, or 0X respectively for values other than zero. Used with e, E and f, it forces the written output to contain a decimal point even if no digits would follow. By default, if no digits follow, no decimal point is written. Used with g or G the result is the same as with e or E but trailing zeros are not removed.
0 Left-pads the number with zeroes (0) instead of spaces, where padding is specified (see width sub-specifier).
+
+ + + + + + +
Width Description
(number) A minimum number of characters to be printed. If the value to be printed is shorter than this number, the result is padded with blank spaces. The value is not truncated even if the result is larger.
* The width is not specified in the format string, but as an additional integer value argument preceding the argument that has to be formatted.
+
+ + + + + + +
.precision Description
.number For integer specifiers (d, i, o, u, x, X) − precision specifies the minimum number of digits to be written. If the value to be written is shorter than this number, the result is padded with leading zeros. The value is not truncated even if the result is longer. A precision of 0 means that no character is written for the value 0. For e, E, and f specifiers − this is the number of digits to be printed after the decimal point. For g and G specifiers − This is the maximum number of significant digits to be printed. For s − this is the maximum number of characters to be printed. By default, all characters are printed until the ending null character is encountered. For c type − it has no effect. When no precision is specified, the default is 1. If the period is specified without an explicit value for precision, 0 is assumed.
.* The precision is not specified in the format string, but as an additional integer value argument preceding the argument that has to be formatted.
+
+ + + + +
length Description
Do not support
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
specifier Description
d or i Signed decimal integer
f Decimal floating point
F Decimal floating point capital letters
x Unsigned hexadecimal integer
X Unsigned hexadecimal integer capital letters
o Signed octal
b Binary value
p Pointer address
u Unsigned decimal integer
c Character
s String of characters
n Nothing printed
+
    +
  • Support a format specifier for SCANF following this prototype " %[*][width][length]specifier", which is explained below
    • +
+
+ + + + +
* Description
An optional starting asterisk indicates that the data is to be read from the stream but ignored. In other words, it is not stored in the corresponding argument.
+
+ + + + +
width Description
This specifies the maximum number of characters to be read in the current reading operation.
+
+ + + + + + + + + + + + + + +
length Description
hh The argument is interpreted as a signed character or unsigned character (only applies to integer specifiers: i, d, o, u, x, and X).
h The argument is interpreted as a short integer or unsigned short integer (only applies to integer specifiers: i, d, o, u, x, and X).
l The argument is interpreted as a long integer or unsigned long integer for integer specifiers (i, d, o, u, x, and X) and as a wide character or wide character string for specifiers c and s.
ll The argument is interpreted as a long long integer or unsigned long long integer for integer specifiers (i, d, o, u, x, and X) and as a wide character or wide character string for specifiers c and s.
L The argument is interpreted as a long double (only applies to floating point specifiers: e, E, f, g, and G).
j or z or t Not supported
+
+ + + + + + + + + + + + + + + + +
specifier Qualifying Input Type of argument
c Single character: Reads the next character. If a width different from 1 is specified, the function reads width characters and stores them in the successive locations of the array passed as argument. No null character is appended at the end. char *
i Integer: : Number optionally preceded with a + or - sign int *
d Decimal integer: Number optionally preceded with a + or - sign int *
a, A, e, E, f, F, g, G Floating point: Decimal number containing a decimal point, optionally preceded by a + or - sign and optionally followed by the e or E character and a decimal number. Two examples of valid entries are -732.103 and 7.12e4 float *
o Octal Integer: int *
s String of characters. This reads subsequent characters until a white space is found (white space characters are considered to be blank, newline, and tab). char *
u Unsigned decimal integer. unsigned int *
+

The debug console has its own printf/scanf/putchar/getchar functions which are defined in the header file.

+
int DbgConsole_Printf(const char *fmt_s, ...);
+
int DbgConsole_Putchar(int ch);
+
int DbgConsole_Scanf(char *fmt_ptr, ...);
+
int DbgConsole_Getchar(void);
+

This utility supports selecting toolchain's printf/scanf or the MCUXpresso SDK printf/scanf.

+
#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */
+
#define PRINTF
+
#define SCANF
+
#define PUTCHAR
+
#define GETCHAR
+
#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */
+
#define PRINTF DbgConsole_Printf
+
#define SCANF DbgConsole_Scanf
+
#define PUTCHAR DbgConsole_Putchar
+
#define GETCHAR DbgConsole_Getchar
+
#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. */
+
#define PRINTF printf
+
#define SCANF scanf
+
#define PUTCHAR putchar
+
#define GETCHAR getchar
+
#endif /* SDK_DEBUGCONSOLE */
+

+SDK_DEBUGCONSOLE and SDK_DEBUGCONSOLE_UART

+

There are two macros SDK_DEBUGCONSOLE and SDK_DEBUGCONSOLE_UART added to configure PRINTF and low level output perihperal.

+
    +
  • The macro SDK_DEBUGCONSOLE is used for forntend. Whether debug console redirect to toolchain or SDK or disabled, it decides which is the frontend of the debug console, Tool chain or SDK. The fucntion can be set by the macro SDK_DEBUGCONSOLE.
    • +
  • The macro SDK_DEBUGCONSOLE_UART is used for backend. It is use to decide whether provide low level IO implementation to toolchain printf and scanf. For example, within MCUXpresso, if the macro SDK_DEBUGCONSOLE_UART is defined, __sys_write and __sys_readc will be used when __REDLIB__ is defined; _write and _read will be used in other cases.The macro does not specifically refer to the perihpheral "UART". It refers to the external perihperal similar to UART, like as USB CDC, UART, SWO, etc. So if the macro SDK_DEBUGCONSOLE_UART is not defined when tool-chain printf is calling, the semihosting will be used.
    • +
+

The following the matrix show the effects of SDK_DEBUGCONSOLE and SDK_DEBUGCONSOLE_UART on PRINTF and printf. The green mark is the default setting of the debug console.

+
+ + + + + + + + + + + + + + +
SDK_DEBUGCONSOLE SDK_DEBUGCONSOLE_UART PRINTF printf
DEBUGCONSOLE_REDIRECT_TO_SDK defined Low level peripheral* Low level peripheral*
DEBUGCONSOLE_REDIRECT_TO_SDK undefined Low level peripheral* semihost
DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN defined Low level peripheral* Low level peripheral*
DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN undefined semihost semihost
DEBUGCONSOLE_DISABLE defined No ouput Low level peripheral*
DEBUGCONSOLE_DISABLE undefined No ouput semihost
+

* the low level peripheral could be USB CDC, UART, or SWO, and so on.

+

+Typical use case

+

Some examples use the PUTCHAR & GETCHAR function

+
ch = GETCHAR();
+
PUTCHAR(ch);
+

Some examples use the PRINTF function

+

Statement prints the string format.

+
PRINTF("%s %s\r\n", "Hello", "world!");
+

Statement prints the hexadecimal format/

+
PRINTF("0x%02X hexadecimal number equivalents 255", 255);
+

Statement prints the decimal floating point and unsigned decimal.

+
PRINTF("Execution timer: %s\n\rTime: %u ticks %2.5f milliseconds\n\rDONE\n\r", "1 day", 86400, 86.4);
+

Some examples use the SCANF function

+
PRINTF("Enter a decimal number: ");
+
SCANF("%d", &i);
+
PRINTF("\r\nYou have entered %d.\r\n", i, i);
+
PRINTF("Enter a hexadecimal number: ");
+
SCANF("%x", &i);
+
PRINTF("\r\nYou have entered 0x%X (%d).\r\n", i, i);
+

Print out failure messages using MCUXpresso SDK __assert_func:

+
void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+
{
+
PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file , line, func);
+
for (;;)
+
{}
+
}
+

Note:

+

To use 'printf' and 'scanf' for GNUC Base, add file 'fsl_sbrk.c' in path: ..\{package}\devices\{subset}\utilities\fsl_sbrk.c to your project.

+ + + + + + +

+Modules

 SWO
 
 Semihosting
 
+ + + + + + + + + + + + + + + + +

+Macros

#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN   0U
 Definition select redirect toolchain printf, scanf to uart or not. More...
 
#define DEBUGCONSOLE_REDIRECT_TO_SDK   1U
 Select SDK version printf, scanf. More...
 
#define DEBUGCONSOLE_DISABLE   2U
 Disable debugconsole function. More...
 
#define SDK_DEBUGCONSOLE   DEBUGCONSOLE_REDIRECT_TO_SDK
 Definition to select sdk or toolchain printf, scanf. More...
 
#define PRINTF   DbgConsole_Printf
 Definition to select redirect toolchain printf, scanf to uart or not. More...
 
+ + + + +

+Typedefs

+typedef void(* printfCb )(char *buf, int32_t *indicator, char val, int len)
 A function pointer which is used when format printf log.
 
+ + + + + + + +

+Functions

int StrFormatPrintf (const char *fmt, va_list ap, char *buf, printfCb cb)
 This function outputs its parameters according to a formatted string. More...
 
int StrFormatScanf (const char *line_ptr, char *format, va_list args_ptr)
 Converts an input line of ASCII characters based upon a provided string format. More...
 
+ + + + +

+Variables

+serial_handle_t g_serialHandle
 serial manager handle
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Initialization

status_t DbgConsole_Init (uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq)
 Initializes the peripheral used for debug messages. More...
 
status_t DbgConsole_Deinit (void)
 De-initializes the peripheral used for debug messages. More...
 
status_t DbgConsole_EnterLowpower (void)
 Prepares to enter low power consumption. More...
 
status_t DbgConsole_ExitLowpower (void)
 Restores from low power consumption. More...
 
int DbgConsole_Printf (const char *fmt_s,...)
 Writes formatted output to the standard output stream. More...
 
int DbgConsole_Putchar (int ch)
 Writes a character to stdout. More...
 
int DbgConsole_Scanf (char *formatString,...)
 Reads formatted data from the standard input stream. More...
 
int DbgConsole_Getchar (void)
 Reads a character from standard input. More...
 
int DbgConsole_BlockingPrintf (const char *formatString,...)
 Writes formatted output to the standard output stream with the blocking mode. More...
 
status_t DbgConsole_Flush (void)
 Debug console flush. More...
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN   0U
+
+

Select toolchain printf and scanf.

+ +
+
+ +
+
+ + + + +
#define DEBUGCONSOLE_REDIRECT_TO_SDK   1U
+
+ +
+
+ +
+
+ + + + +
#define DEBUGCONSOLE_DISABLE   2U
+
+ +
+
+ +
+
+ + + + +
#define SDK_DEBUGCONSOLE   DEBUGCONSOLE_REDIRECT_TO_SDK
+
+

The macro only support to be redefined in project setting.

+ +
+
+ +
+
+ + + + +
#define PRINTF   DbgConsole_Printf
+
+

if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf. if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf. if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.

+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
status_t DbgConsole_Init (uint8_t instance,
uint32_t baudRate,
serial_port_type_t device,
uint32_t clkSrcFreq 
)
+
+

Call this function to enable debug log messages to be output via the specified peripheral initialized by the serial manager module. After this function has returned, stdout and stdin are connected to the selected peripheral.

+
Parameters
+ + + + + +
instanceThe instance of the module.If the device is kSerialPort_Uart, the instance is UART peripheral instance. The UART hardware peripheral type is determined by UART adapter. For example, if the instance is 1, if the lpuart_adapter.c is added to the current project, the UART periheral is LPUART1. If the uart_adapter.c is added to the current project, the UART periheral is UART1.
baudRateThe desired baud rate in bits per second.
deviceLow level device type for the debug console, can be one of the following.
    +
  • kSerialPort_Uart,
    • +
  • kSerialPort_UsbCdc
    • +
+
clkSrcFreqFrequency of peripheral source clock.
+
+
+
Returns
Indicates whether initialization was successful or not.
+
Return values
+ + +
kStatus_SuccessExecution successfully
+
+
+ +
+
+ +
+
+ + + + + + + + +
status_t DbgConsole_Deinit (void )
+
+

Call this function to disable debug log messages to be output via the specified peripheral initialized by the serial manager module.

+
Returns
Indicates whether de-initialization was successful or not.
+ +
+
+ +
+
+ + + + + + + + +
status_t DbgConsole_EnterLowpower (void )
+
+

This function is used to prepare to enter low power consumption.

+
Returns
Indicates whether de-initialization was successful or not.
+ +
+
+ +
+
+ + + + + + + + +
status_t DbgConsole_ExitLowpower (void )
+
+

This function is used to restore from low power consumption.

+
Returns
Indicates whether de-initialization was successful or not.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int DbgConsole_Printf (const char * fmt_s,
 ... 
)
+
+

Call this function to write a formatted output to the standard output stream.

+
Parameters
+ + +
fmt_sFormat control string.
+
+
+
Returns
Returns the number of characters printed or a negative value if an error occurs.
+ +
+
+ +
+
+ + + + + + + + +
int DbgConsole_Putchar (int ch)
+
+

Call this function to write a character to stdout.

+
Parameters
+ + +
chCharacter to be written.
+
+
+
Returns
Returns the character written.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int DbgConsole_Scanf (char * formatString,
 ... 
)
+
+

Call this function to read formatted data from the standard input stream.

+
Note
Due the limitation in the BM OSA environment (CPU is blocked in the function, other tasks will not be scheduled), the function cannot be used when the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. And an error is returned when the function called in this case. The suggestion is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+
Parameters
+ + +
formatStringFormat control string.
+
+
+
Returns
Returns the number of fields successfully converted and assigned.
+ +
+
+ +
+
+ + + + + + + + +
int DbgConsole_Getchar (void )
+
+

Call this function to read a character from standard input.

+
Note
Due the limitation in the BM OSA environment (CPU is blocked in the function, other tasks will not be scheduled), the function cannot be used when the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. And an error is returned when the function called in this case. The suggestion is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+
Returns
Returns the character read.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int DbgConsole_BlockingPrintf (const char * formatString,
 ... 
)
+
+

Call this function to write a formatted output to the standard output stream with the blocking mode. The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set or not. The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set.

+
Parameters
+ + +
formatStringFormat control string.
+
+
+
Returns
Returns the number of characters printed or a negative value if an error occurs.
+ +
+
+ +
+
+ + + + + + + + +
status_t DbgConsole_Flush (void )
+
+

Call this function to wait the tx buffer empty. If interrupt transfer is using, make sure the global IRQ is enable before call this function This function should be called when 1, before enter power down mode 2, log is required to print to terminal immediately

+
Returns
Indicates whether wait idle was successful or not.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
int StrFormatPrintf (const char * fmt,
va_list ap,
char * buf,
printfCb cb 
)
+
+
Note
I/O is performed by calling given function pointer using following (*func_ptr)(c);
+
Parameters
+ + + + + +
[in]fmtFormat string for printf.
[in]apArguments to printf.
[in]bufpointer to the buffer
cbprint callbck function pointer
+
+
+
Returns
Number of characters to be print
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
int StrFormatScanf (const char * line_ptr,
char * format,
va_list args_ptr 
)
+
+
Parameters
+ + + + +
[in]line_ptrThe input line of ASCII data.
[in]formatFormat first points to the format string.
[in]args_ptrThe list of parameters.
+
+
+
Returns
Number of input items converted and assigned.
+
Return values
+ + +
IO_EOFWhen line_ptr is empty string "".
+
+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00102.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00102.js new file mode 100644 index 000000000..badabcc7f --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00102.js @@ -0,0 +1,24 @@ +var a00102 = +[ + [ "SWO", "a00104.html", null ], + [ "Semihosting", "a00103.html", null ], + [ "DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN", "a00102.html#gabb8f0adbec02f143b4f84d2eb42126df", null ], + [ "DEBUGCONSOLE_REDIRECT_TO_SDK", "a00102.html#gac33031f28afa29dc8fe1718bbc86ee23", null ], + [ "DEBUGCONSOLE_DISABLE", "a00102.html#gaf8f85fd102e4aedcee3d061dc2d3e0c2", null ], + [ "SDK_DEBUGCONSOLE", "a00102.html#ga7fdd594efdc8374ecd8684ed758d6cec", null ], + [ "PRINTF", "a00102.html#gae1649fc947ca37a86917a08354f48d1a", null ], + [ "printfCb", "a00102.html#gae9d851a9da87d7f21d8dd5a19f9eec7b", null ], + [ "DbgConsole_Init", "a00102.html#ga12e50ee0450679fd8ca950a89338d366", null ], + [ "DbgConsole_Deinit", "a00102.html#gad80e7aa70bbb3fce1a9168621372833e", null ], + [ "DbgConsole_EnterLowpower", "a00102.html#ga9ce272e795c2b235265d3dfb50669bee", null ], + [ "DbgConsole_ExitLowpower", "a00102.html#ga21831f5ee970f3a1f13ff375405f3592", null ], + [ "DbgConsole_Printf", "a00102.html#ga7f9e0678f4c708ed5640b0823c07dc35", null ], + [ "DbgConsole_Putchar", "a00102.html#gada572d86a06f028b5b1a5d0440f683e3", null ], + [ "DbgConsole_Scanf", "a00102.html#ga6d87d10b03e4aaf8464206fe3829dd28", null ], + [ "DbgConsole_Getchar", "a00102.html#ga11898c5015274863741c4f3f4d9edc08", null ], + [ "DbgConsole_BlockingPrintf", "a00102.html#ga6a957577839a195b36adf2b6d9de1fd0", null ], + [ "DbgConsole_Flush", "a00102.html#ga3194467c3dae6c5015b8b29c3cc1db1e", null ], + [ "StrFormatPrintf", "a00102.html#ga50b9d66ac2ba38b23b99dac4e81f4b8c", null ], + [ "StrFormatScanf", "a00102.html#gafe318e0fd8d0f6ebad0c8a871a7a196f", null ], + [ "g_serialHandle", "a00102.html#gaad3c4240a1364156a239471ccdb9aa0b", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00103.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00103.html new file mode 100644 index 000000000..dbe148af8 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00103.html @@ -0,0 +1,234 @@ + + + + + + +MCUXpresso SDK API Reference Manual: Semihosting + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Semihosting
Debug Console
+
+
+

Semihosting is a mechanism for ARM targets to communicate input/output requests from application code to a host computer running a debugger. This mechanism can be used, for example, to enable functions in the C library, such as printf() and scanf(), to use the screen and keyboard of the host rather than having a screen and keyboard on the target system.

+

+Guide Semihosting for IAR

+

NOTE: After the setting both "printf" and "scanf" are available for debugging, if you want use PRINTF with semihosting, please make sure the SDK_DEBUGCONSOLE is DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN.

+

Step 1: Setting up the environment

+
    +
  1. To set debugger options, choose Project>Options. In the Debugger category, click the Setup tab.
    2. +
  2. Select Run to main and click OK. This ensures that the debug session starts by running the main function.
    3. +
  3. The project is now ready to be built.
    4. +
+

Step 2: Building the project

+
    +
  1. Compile and link the project by choosing Project>Make or F7.
    2. +
  2. Alternatively, click the Make button on the tool bar. The Make command compiles and links those files that have been modified.
    3. +
+

Step 3: Starting semihosting

+
    +
  1. Choose "Semihosting_IAR" project -> "Options" -> "Debugger" -> "J-Link/J-Trace".
    2. +
  2. Choose tab "J-Link/J-Trace" -> "Connection" tab -> "SWD".
    3. +
  3. Choose tab "General Options" -> "Library Configurations", select Semihosted, select Via semihosting. Please Make sure the SDK_DEBUGCONSOLE_UART is not defined in project settings.
    4. +
  4. Start the project by choosing Project>Download and Debug.
    5. +
  5. Choose View>Terminal I/O to display the output from the I/O operations.
    6. +
+

+Guide Semihosting for Keil µVision

+

NOTE: Semihosting is not support by MDK-ARM, use the retargeting functionality of MDK-ARM instead.

+

+Guide Semihosting for MCUXpresso IDE

+

Step 1: Setting up the environment

+
    +
  1. To set debugger options, choose Project>Properties. select the setting category.
    2. +
  2. Select Tool Settings, unfold MCU C Compile.
    3. +
  3. Select Preprocessor item.
    4. +
  4. Set SDK_DEBUGCONSOLE=0, if set SDK_DEBUGCONSOLE=1, the log will be redirect to the UART.
    5. +
+

Step 2: Building the project

+
    +
  1. Compile and link the project.
    2. +
+

Step 3: Starting semihosting

+
    +
  1. Download and debug the project.
    2. +
  2. When the project runs successfully, the result can be seen in the Console window.
    3. +
+

Semihosting can also be selected through the "Quick settings" menu in the left bottom window, Quick settings->SDK Debug Console->Semihost console.

+

+Guide Semihosting for ARMGCC

+

Step 1: Setting up the environment

+
    +
  1. Turn on "J-LINK GDB Server" -> Select suitable "Target device" -> "OK".
    2. +
  2. Turn on "PuTTY". Set up as follows.
      +
    • "Host Name (or IP address)" : localhost
      • +
    • "Port" :2333
      • +
    • "Connection type" : Telet.
      • +
    • Click "Open".
      • +
    +
    3. +
  3. Increase "Heap/Stack" for GCC to 0x2000:
    4. +
+

Add to "CMakeLists.txt"

+

SET(CMAKE_EXE_LINKER_FLAGS_RELEASE "${CMAKE_EXE_LINKER_FLAGS_RELEASE} --defsym=__stack_size__=0x2000")

+

SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} --defsym=__stack_size__=0x2000")

+

SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} --defsym=__heap_size__=0x2000")

+

SET(CMAKE_EXE_LINKER_FLAGS_RELEASE "${CMAKE_EXE_LINKER_FLAGS_RELEASE} --defsym=__heap_size__=0x2000")

+

Step 2: Building the project

+
    +
  1. +

    Change "CMakeLists.txt":

    +

    Change "SET(CMAKE_EXE_LINKER_FLAGS_RELEASE "${CMAKE_EXE_LINKER_FLAGS_RELEASE} –specs=nano.specs")"

    +

    to "SET(CMAKE_EXE_LINKER_FLAGS_RELEASE "${CMAKE_EXE_LINKER_FLAGS_RELEASE} –specs=rdimon.specs")"

    +

    +

    Replace paragraph

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} -fno-common")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} -ffunction-sections")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} -fdata-sections")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} -ffreestanding")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} -fno-builtin")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} -mthumb")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} -mapcs")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} -Xlinker")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} --gc-sections")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} -Xlinker")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} -static")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} -Xlinker")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} -z")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} -Xlinker")

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} muldefs")

    +

    +

    To

    +

    +

    SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} --specs=rdimon.specs ")

    +

    +

    +

    Remove

    +

    target_link_libraries(semihosting_ARMGCC.elf debug nosys)

    +

    +
    2. +
  2. +Run "build_debug.bat" to build project
    3. +
+

Step 3: Starting semihosting

+
    +
  1. Download the image and set as follows.
    cd D:\mcu-sdk-2.0-origin\boards\twrk64f120m\driver_examples\semihosting\armgcc\debug
    +
    d:
    +
    C:\PROGRA~2\GNUTOO~1\4BD65~1.920\bin\arm-none-eabi-gdb.exe
    +
    target remote localhost:2331
    +
    monitor reset
    +
    monitor semihosting enable
    +
    monitor semihosting thumbSWI 0xAB
    +
    monitor semihosting IOClient 1
    +
    monitor flash device = MK64FN1M0xxx12
    +
    load semihosting_ARMGCC.elf
    +
    monitor reg pc = (0x00000004)
    +
    monitor reg sp = (0x00000000)
    +
    continue
    +
    2. +
  2. After the setting, press "enter". The PuTTY window now shows the printf() output.
    3. +
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00104.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00104.html new file mode 100644 index 000000000..098f0df3a --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00104.html @@ -0,0 +1,182 @@ + + + + + + +MCUXpresso SDK API Reference Manual: SWO + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
SWO
Debug Console
+
+
+

Serial wire output is a mechanism for ARM targets to output signal from core through a single pin. Some IDEs also support SWO, such IAR and KEIL, both input and output are supported, see below for details.

+

+Guide SWO for SDK

+

NOTE: After the setting both "printf" and "PRINTF" are available for debugging, JlinkSWOViewer can be used to capture the output log.

+

Step 1: Setting up the environment

+
    +
  1. Define SERIAL_PORT_TYPE_SWO in your project settings.
    2. +
  2. Prepare code, the port and baudrate can be decided by application, clkSrcFreq should be mcu core clock frequency:
    DbgConsole_Init(instance, baudRate, kSerialPort_Swo, clkSrcFreq);
    +
    3. +
  3. Use PRINTF or printf to print some thing in application.

    Step 2: Building the project

    +
    4. +
+

Step 3: Download and run project

+

+Guide SWO for IAR

+

NOTE: After the setting both "printf" and "scanf" are available for debugging.

+

Step 1: Setting up the environment

+
    +
  1. Choose project -> "Options" -> "Debugger" -> "J-Link/J-Trace".
    2. +
  2. Choose tab "J-Link/J-Trace" -> "Connection" tab -> "SWD".
    3. +
  3. Choose tab "General Options" -> "Library Configurations", select Semihosted, select Via SWO.
    4. +
  4. To configure the hardware’s generation of trace data, click the SWO Configuration button available in the SWO Configuration dialog box. â—The value of the CPU clock option must reflect the frequency of the CPU clock speed at which the application executes. Note also that the settings you make are preserved between debug sessions. â—To decrease the amount of transmissions on the communication channel, you can disable the Timestamp option. Alternatively, set a lower rate for PC Sampling or use a higher SWO clock frequency.
    5. +
  5. Open the SWO Trace window from J-LINK,and click the Activate button to enable trace data collection.
    6. +
  6. There are three cases for this SDK_DEBUGCONSOLE_UART whether or not defined. a: if use uppercase PRINTF to output log,The SDK_DEBUGCONSOLE_UART defined or not defined will not effect debug function. b: if use lowercase printf to output log and defined SDK_DEBUGCONSOLE_UART to zero,then debug function ok. c: if use lowercase printf to output log and defined SDK_DEBUGCONSOLE_UART to one,then debug function ok.
    7. +
+

NOTE: Case a or c only apply at example which enable swo function,the SDK_DEBUGCONSOLE_UART definition in fsl_debug_console.h. For case a and c, Do and not do the above third step will be not affect function.

+
    +
  1. Start the project by choosing Project>Download and Debug.

    Step 2: Building the project

    +
    2. +
+

Step 3: Starting swo

+
    +
  1. Download and debug application.
    2. +
  2. Choose View -> Terminal I/O to display the output from the I/O operations.
    3. +
  3. Run application.
    4. +
+

+Guide SWO for Keil µVision

+

NOTE: After the setting both "printf" and "scanf" are available for debugging.

+

Step 1: Setting up the environment

+
    +
  1. There are three cases for this SDK_DEBUGCONSOLE_UART whether or not defined. a: if use uppercase PRINTF to output log,the SDK_DEBUGCONSOLE_UART definition does not affect the functionality and skip the second step directly. b: if use lowercase printf to output log and defined SDK_DEBUGCONSOLE_UART to zero,then start the second step. c: if use lowercase printf to output log and defined SDK_DEBUGCONSOLE_UART to one,then skip the second step directly.
    2. +
+

NOTE: Case a or c only apply at example which enable swo function,the SDK_DEBUGCONSOLE_UART definition in fsl_debug_console.h.

+
    +
  1. In menu bar, click Management Run-Time Environment icon, select Compiler, unfold I/O, enable STDERR/STDIN/STDOUT and set the variant to ITM.
    2. +
  2. Open Project>Options for target or using Alt+F7 or click.
    3. +
  3. Select “Debug†tab, select “J-Link/J-Trace Cortex†and click “Setting buttonâ€.
    4. +
  4. Select “Debug†tab and choose Port:SW, then select "Trace" tab, choose "Enable" and click OK, please make sure the Core clock is set correctly, enable autodetect max SWO clk, enable ITM Stimulus Ports 0.
    5. +
+

Step 3: Building the project

+
    +
  1. Compile and link the project by choosing Project>Build Target or using F7.
    2. +
+

Step 4: Run the project

+
    +
  1. Choose “Debug†on menu bar or Ctrl F5.
    2. +
  2. In menu bar, choose "Serial Window" and click to "Debug (printf) Viewer".
    3. +
  3. Run line by line to see result in Console Window.
    4. +
+

+Guide SWO for MCUXpresso IDE

+

NOTE: MCUX support SWO for LPC-Link2 debug probe only.

+

+Guide SWO for ARMGCC

+

NOTE: ARMGCC has no library support SWO.

+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00105.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00105.html new file mode 100644 index 000000000..1ac968bc8 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00105.html @@ -0,0 +1,130 @@ + + + + + + +MCUXpresso SDK API Reference Manual: CODEC Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Modules
+
+
CODEC Driver
+
+
+

Overview

+

The MCUXpresso SDK provides a codec abstraction driver interface to access codec register.

+ + + + + + + + +

+Modules

 CODEC Common Driver
 
 CODEC I2C Driver
 
 WM8524 Driver
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00105.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00105.js new file mode 100644 index 000000000..842f9d2bf --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00105.js @@ -0,0 +1,6 @@ +var a00105 = +[ + [ "CODEC Common Driver", "a00009.html", "a00009" ], + [ "CODEC I2C Driver", "a00106.html", null ], + [ "WM8524 Driver", "a00023.html", "a00023" ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00106.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00106.html new file mode 100644 index 000000000..70a9d9cb3 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00106.html @@ -0,0 +1,117 @@ + + + + + + +MCUXpresso SDK API Reference Manual: CODEC I2C Driver + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
CODEC I2C Driver
CODEC Driver
+
+
+

The codec common driver provides a codec control abstraction interface.

+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00107.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00107.html new file mode 100644 index 000000000..1b94e7282 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00107.html @@ -0,0 +1,1031 @@ + + + + + + +MCUXpresso SDK API Reference Manual: WM8524 Adapter + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
WM8524 Adapter
CODEC Common Driver
+
+
+

Overview

+

The wm8524 adapter provides a codec unify control interface.

+ + + + + +

+Macros

+#define HAL_CODEC_WM8524_HANDLER_SIZE   (4)
 codec handler size
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

status_t HAL_CODEC_WM8524_Init (void *handle, void *config)
 Codec initilization. More...
 
status_t HAL_CODEC_WM8524_Deinit (void *handle)
 Codec de-initilization. More...
 
status_t HAL_CODEC_WM8524_SetFormat (void *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth)
 set audio data format. More...
 
status_t HAL_CODEC_WM8524_SetVolume (void *handle, uint32_t playChannel, uint32_t volume)
 set audio codec module volume. More...
 
status_t HAL_CODEC_WM8524_SetMute (void *handle, uint32_t playChannel, bool isMute)
 set audio codec module mute. More...
 
status_t HAL_CODEC_WM8524_SetPower (void *handle, uint32_t module, bool powerOn)
 set audio codec module power. More...
 
status_t HAL_CODEC_WM8524_SetRecord (void *handle, uint32_t recordSource)
 codec set record source. More...
 
status_t HAL_CODEC_WM8524_SetRecordChannel (void *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel)
 codec set record channel. More...
 
status_t HAL_CODEC_WM8524_SetPlay (void *handle, uint32_t playSource)
 codec set play source. More...
 
status_t HAL_CODEC_WM8524_ModuleControl (void *handle, uint32_t cmd, uint32_t data)
 codec module control. More...
 
static status_t HAL_CODEC_Init (void *handle, void *config)
 Codec initilization. More...
 
static status_t HAL_CODEC_Deinit (void *handle)
 Codec de-initilization. More...
 
static status_t HAL_CODEC_SetFormat (void *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth)
 set audio data format. More...
 
static status_t HAL_CODEC_SetVolume (void *handle, uint32_t playChannel, uint32_t volume)
 set audio codec module volume. More...
 
static status_t HAL_CODEC_SetMute (void *handle, uint32_t playChannel, bool isMute)
 set audio codec module mute. More...
 
static status_t HAL_CODEC_SetPower (void *handle, uint32_t module, bool powerOn)
 set audio codec module power. More...
 
static status_t HAL_CODEC_SetRecord (void *handle, uint32_t recordSource)
 codec set record source. More...
 
static status_t HAL_CODEC_SetRecordChannel (void *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel)
 codec set record channel. More...
 
static status_t HAL_CODEC_SetPlay (void *handle, uint32_t playSource)
 codec set play source. More...
 
static status_t HAL_CODEC_ModuleControl (void *handle, uint32_t cmd, uint32_t data)
 codec module control. More...
 
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t HAL_CODEC_WM8524_Init (void * handle,
void * config 
)
+
+
Parameters
+ + + +
handlecodec handle.
configcodec configuration.
+
+
+
Returns
kStatus_Success is success, else initial failed.
+ +
+
+ +
+
+ + + + + + + + +
status_t HAL_CODEC_WM8524_Deinit (void * handle)
+
+
Parameters
+ + +
handlecodec handle.
+
+
+
Returns
kStatus_Success is success, else de-initial failed.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
status_t HAL_CODEC_WM8524_SetFormat (void * handle,
uint32_t mclk,
uint32_t sampleRate,
uint32_t bitWidth 
)
+
+
Parameters
+ + + + + +
handlecodec handle.
mclkmaster clock frequency in HZ.
sampleRatesample rate in HZ.
bitWidthbit width.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t HAL_CODEC_WM8524_SetVolume (void * handle,
uint32_t playChannel,
uint32_t volume 
)
+
+
Parameters
+ + + + +
handlecodec handle.
playChannelaudio codec play channel, can be a value or combine value of _codec_play_channel.
volumevolume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t HAL_CODEC_WM8524_SetMute (void * handle,
uint32_t playChannel,
bool isMute 
)
+
+
Parameters
+ + + + +
handlecodec handle.
playChannelaudio codec play channel, can be a value or combine value of _codec_play_channel.
isMutetrue is mute, false is unmute.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t HAL_CODEC_WM8524_SetPower (void * handle,
uint32_t module,
bool powerOn 
)
+
+
Parameters
+ + + + +
handlecodec handle.
moduleaudio codec module.
powerOntrue is power on, false is power down.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t HAL_CODEC_WM8524_SetRecord (void * handle,
uint32_t recordSource 
)
+
+
Parameters
+ + + +
handlecodec handle.
recordSourceaudio codec record source, can be a value or combine value of _codec_record_source.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t HAL_CODEC_WM8524_SetRecordChannel (void * handle,
uint32_t leftRecordChannel,
uint32_t rightRecordChannel 
)
+
+
Parameters
+ + + + +
handlecodec handle.
leftRecordChannelaudio codec record channel, reference _codec_record_channel, can be a value or combine value of member in _codec_record_channel.
rightRecordChannelaudio codec record channel, reference _codec_record_channel, can be a value combine of member in _codec_record_channel.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
status_t HAL_CODEC_WM8524_SetPlay (void * handle,
uint32_t playSource 
)
+
+
Parameters
+ + + +
handlecodec handle.
playSourceaudio codec play source, can be a value or combine value of _codec_play_source.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
status_t HAL_CODEC_WM8524_ModuleControl (void * handle,
uint32_t cmd,
uint32_t data 
)
+
+

This function is used for codec module control, support switch digital interface cmd, can be expand to support codec module specific feature

+
Parameters
+ + + + +
handlecodec handle.
cmdmodule control cmd, reference _codec_module_ctrl_cmd.
datavalue to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference codec specific driver for detail configurations.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static status_t HAL_CODEC_Init (void * handle,
void * config 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
handlecodec handle.
configcodec configuration.
+
+
+
Returns
kStatus_Success is success, else initial failed.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static status_t HAL_CODEC_Deinit (void * handle)
+ 		+inlinestatic
+
+
Parameters
+ + +
handlecodec handle.
+
+
+
Returns
kStatus_Success is success, else de-initial failed.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
static status_t HAL_CODEC_SetFormat (void * handle,
uint32_t mclk,
uint32_t sampleRate,
uint32_t bitWidth 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + + +
handlecodec handle.
mclkmaster clock frequency in HZ.
sampleRatesample rate in HZ.
bitWidthbit width.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static status_t HAL_CODEC_SetVolume (void * handle,
uint32_t playChannel,
uint32_t volume 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
handlecodec handle.
playChannelaudio codec play channel, can be a value or combine value of _codec_play_channel.
volumevolume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static status_t HAL_CODEC_SetMute (void * handle,
uint32_t playChannel,
bool isMute 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
handlecodec handle.
playChannelaudio codec play channel, can be a value or combine value of _codec_play_channel.
isMutetrue is mute, false is unmute.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static status_t HAL_CODEC_SetPower (void * handle,
uint32_t module,
bool powerOn 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
handlecodec handle.
moduleaudio codec module.
powerOntrue is power on, false is power down.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static status_t HAL_CODEC_SetRecord (void * handle,
uint32_t recordSource 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
handlecodec handle.
recordSourceaudio codec record source, can be a value or combine value of _codec_record_source.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static status_t HAL_CODEC_SetRecordChannel (void * handle,
uint32_t leftRecordChannel,
uint32_t rightRecordChannel 
)
+ 		+inlinestatic
+
+
Parameters
+ + + + +
handlecodec handle.
leftRecordChannelaudio codec record channel, reference _codec_record_channel, can be a value or combine value of member in _codec_record_channel.
rightRecordChannelaudio codec record channel, reference _codec_record_channel, can be a value combine of member in _codec_record_channel.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static status_t HAL_CODEC_SetPlay (void * handle,
uint32_t playSource 
)
+ 		+inlinestatic
+
+
Parameters
+ + + +
handlecodec handle.
playSourceaudio codec play source, can be a value or combine value of _codec_play_source.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
static status_t HAL_CODEC_ModuleControl (void * handle,
uint32_t cmd,
uint32_t data 
)
+ 		+inlinestatic
+
+

This function is used for codec module control, support switch digital interface cmd, can be expand to support codec module specific feature

+
Parameters
+ + + + +
handlecodec handle.
cmdmodule control cmd, reference _codec_module_ctrl_cmd.
datavalue to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference codec specific driver for detail configurations.
+
+
+
Returns
kStatus_Success is success, else configure failed.
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00107.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00107.js new file mode 100644 index 000000000..05b95e82c --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00107.js @@ -0,0 +1,24 @@ +var a00107 = +[ + [ "HAL_CODEC_WM8524_HANDLER_SIZE", "a00107.html#ga0da7b65852552fda1bd03ce870cce471", null ], + [ "HAL_CODEC_WM8524_Init", "a00107.html#ga586b458942b371c346e6a411a534897a", null ], + [ "HAL_CODEC_WM8524_Deinit", "a00107.html#ga0001e9afafb89b3b272bc90750ed2064", null ], + [ "HAL_CODEC_WM8524_SetFormat", "a00107.html#ga2bdbc741b7559044553ea2bbc50314a8", null ], + [ "HAL_CODEC_WM8524_SetVolume", "a00107.html#ga004bf6ddf4dfb00c2177e57f71e2d6ce", null ], + [ "HAL_CODEC_WM8524_SetMute", "a00107.html#ga6250a999fab3ad9a96163eb4e5dfc268", null ], + [ "HAL_CODEC_WM8524_SetPower", "a00107.html#gaa15c74cb0e86b3d96d9abe32764ff023", null ], + [ "HAL_CODEC_WM8524_SetRecord", "a00107.html#ga428aeff244fb88261c47f8bc38d6c1ea", null ], + [ "HAL_CODEC_WM8524_SetRecordChannel", "a00107.html#gafd3bbaf309c3437d69be8b719babd107", null ], + [ "HAL_CODEC_WM8524_SetPlay", "a00107.html#gafbb7fe5d734362dac2e2f964acfbc509", null ], + [ "HAL_CODEC_WM8524_ModuleControl", "a00107.html#ga041a79e3a0296333286a90856bd55d70", null ], + [ "HAL_CODEC_Init", "a00107.html#gafe47075da9b829e30e618a86ac2cc9c6", null ], + [ "HAL_CODEC_Deinit", "a00107.html#ga6728d97d2c909d8bff9fee477b0cd9e9", null ], + [ "HAL_CODEC_SetFormat", "a00107.html#gaaf073d16e55b2da18b4b801acd03454b", null ], + [ "HAL_CODEC_SetVolume", "a00107.html#ga17769c66cf7b5c0f01041e7f36f4c89c", null ], + [ "HAL_CODEC_SetMute", "a00107.html#ga6e3171b042e6150ac410abced6123feb", null ], + [ "HAL_CODEC_SetPower", "a00107.html#gad630677f451ca311d9f149d34da70637", null ], + [ "HAL_CODEC_SetRecord", "a00107.html#ga78612feccab62150fb8ee1ef9eb4b6ed", null ], + [ "HAL_CODEC_SetRecordChannel", "a00107.html#gad96c5638cbc67a85bfdb44aa1eee435b", null ], + [ "HAL_CODEC_SetPlay", "a00107.html#ga10228c6005d118872915a0412c466a7d", null ], + [ "HAL_CODEC_ModuleControl", "a00107.html#gab2e790a1ed09bc9a6b910d94180e5bd4", null ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00108.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00108.html new file mode 100644 index 000000000..d4eb6ea95 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00108.html @@ -0,0 +1,197 @@ + + + + + + +MCUXpresso SDK API Reference Manual: Serial Port Uart + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Enumerations
+
+
Serial Port Uart
Serial Manager
+
+
+

Overview

+ + + + + + + + +

+Macros

+#define SERIAL_PORT_UART_HANDLE_SIZE   (HAL_UART_HANDLE_SIZE)
 serial port uart handle size
 
+#define SERIAL_USE_CONFIGURE_STRUCTURE   (0U)
 Enable or disable the confgure structure pointer.
 
+ + + + + + + +

+Enumerations

enum  serial_port_uart_parity_mode_t {
+  kSerialManager_UartParityDisabled = 0x0U, +
+  kSerialManager_UartParityEven = 0x2U, +
+  kSerialManager_UartParityOdd = 0x3U +
+ }
 serial port uart parity mode More...
 
enum  serial_port_uart_stop_bit_count_t {
+  kSerialManager_UartOneStopBit = 0U, +
+  kSerialManager_UartTwoStopBit = 1U +
+ }
 serial port uart stop bit count More...
 
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum serial_port_uart_parity_mode_t
+
+ + + + +
Enumerator
kSerialManager_UartParityDisabled  +

Parity disabled.

+
kSerialManager_UartParityEven  +

Parity even enabled.

+
kSerialManager_UartParityOdd  +

Parity odd enabled.

+
+ +
+
+ +
+
+ + + + +
enum serial_port_uart_stop_bit_count_t
+
+ + + +
Enumerator
kSerialManager_UartOneStopBit  +

One stop bit.

+
kSerialManager_UartTwoStopBit  +

Two stop bits.

+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00108.js b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00108.js new file mode 100644 index 000000000..4c38b05aa --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00108.js @@ -0,0 +1,14 @@ +var a00108 = +[ + [ "SERIAL_PORT_UART_HANDLE_SIZE", "a00108.html#ga2109c092d5f72ef7729b0454b40e892f", null ], + [ "SERIAL_USE_CONFIGURE_STRUCTURE", "a00108.html#ga29c0fa5c543615a75f63bdcb7e086b16", null ], + [ "serial_port_uart_parity_mode_t", "a00108.html#ga89a4bbed0c24cfe5e085194add680ccc", [ + [ "kSerialManager_UartParityDisabled", "a00108.html#gga89a4bbed0c24cfe5e085194add680ccca208958aa923a2c50ac1192a5085ab8b1", null ], + [ "kSerialManager_UartParityEven", "a00108.html#gga89a4bbed0c24cfe5e085194add680ccca7d9d6f05fb6e1099fdfbf1f79a699356", null ], + [ "kSerialManager_UartParityOdd", "a00108.html#gga89a4bbed0c24cfe5e085194add680ccca15bc11791c1f07fac71c808d083515db", null ] + ] ], + [ "serial_port_uart_stop_bit_count_t", "a00108.html#ga8bdf0213026f54fd54c21971e07f2d56", [ + [ "kSerialManager_UartOneStopBit", "a00108.html#gga8bdf0213026f54fd54c21971e07f2d56a5caed34146b357a7061aaacfe378e039", null ], + [ "kSerialManager_UartTwoStopBit", "a00108.html#gga8bdf0213026f54fd54c21971e07f2d56a83eb7aee91f3fd8964d283c0057880dc", null ] + ] ] +]; \ No newline at end of file diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00109.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00109.html new file mode 100644 index 000000000..a577c8a43 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00109.html @@ -0,0 +1,198 @@ + + + + + + +MCUXpresso SDK API Reference Manual: CODEC Adapter + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Enumerations
+
+
CODEC Adapter
CODEC Common Driver
+
+
+

Overview

+ + + + + +

+Enumerations

enum  {
+  kCODEC_WM8904, +
+  kCODEC_WM8960, +
+  kCODEC_WM8524, +
+  kCODEC_SGTL5000, +
+  kCODEC_DA7212, +
+  kCODEC_CS42888, +
+  kCODEC_CS42448, +
+  kCODEC_AK4497, +
+  kCODEC_AK4458, +
+  kCODEC_TFA9XXX, +
+  kCODEC_TFA9896 +
+ }
 codec type More...
 
+

Enumeration Type Documentation

+ +
+
+ + + + +
anonymous enum
+
+

+ + + + + + + + + + + + +
Enumerator
kCODEC_WM8904  +

wm8904

+
kCODEC_WM8960  +

wm8960

+
kCODEC_WM8524  +

wm8524

+
kCODEC_SGTL5000  +

sgtl5000

+
kCODEC_DA7212  +

da7212

+
kCODEC_CS42888  +

CS42888.

+
kCODEC_CS42448  +

CS42448.

+
kCODEC_AK4497  +

AK4497.

+
kCODEC_AK4458  +

ak4458

+
kCODEC_TFA9XXX  +

tfa9xxx

+
kCODEC_TFA9896  +

tfa9896

+
+ +
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00111.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00111.html new file mode 100644 index 000000000..5e2f9f2cd --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/a00111.html @@ -0,0 +1,148 @@ + + + + + + +MCUXpresso SDK API Reference Manual: Deprecated List + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Deprecated List
+
+
+
+
Global GPIO_ClearPinsOutput (GPIO_Type *base, uint32_t mask)
+
Do not use this function. It has been superceded by GPIO_PortClear.
+
Global GPIO_DisableInterrupts (GPIO_Type *base, uint32_t mask)
+
Do not use this function. It has been superceded by GPIO_PortDisableInterrupts.
+
Global GPIO_ReadPadStatus (GPIO_Type *base, uint32_t pin)
+
Do not use this function. It has been superceded by GPIO_PinReadPadStatus.
+
Global GPIO_ReadPinInput (GPIO_Type *base, uint32_t pin)
+
Do not use this function. It has been superceded by GPIO_PinRead.
+
Global GPIO_SetPinInterruptConfig (GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
+
Do not use this function. It has been superceded by GPIO_PinSetInterruptConfig.
+
Global GPIO_SetPinsOutput (GPIO_Type *base, uint32_t mask)
+
Do not use this function. It has been superceded by GPIO_PortSet.
+
Global GPIO_WritePinOutput (GPIO_Type *base, uint32_t pin, uint8_t output)
+
Do not use this function. It has been superceded by GPIO_PinWrite.
+
Global SAI_RxGetDefaultConfig (sai_config_t *config)
+
Do not use this function. It has been superceded by SAI_GetClassicI2SConfig, SAI_GetLeftJustifiedConfig , SAI_GetRightJustifiedConfig, SAI_GetDSPConfig, SAI_GetTDMConfig
+
Global SAI_RxInit (I2S_Type *base, const sai_config_t *config)
+
Do not use this function. It has been superceded by SAI_Init
+
Global SAI_RxSetFormat (I2S_Type *base, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, uint32_t bclkSourceClockHz)
+
Do not use this function. It has been superceded by SAI_RxSetConfig
+
Global SAI_TransferRxSetFormat (I2S_Type *base, sai_handle_t *handle, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, uint32_t bclkSourceClockHz)
+
Do not use this function. It has been superceded by SAI_TransferRxSetConfig
+
Global SAI_TransferTxSetFormat (I2S_Type *base, sai_handle_t *handle, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, uint32_t bclkSourceClockHz)
+
Do not use this function. It has been superceded by SAI_TransferTxSetConfig
+
Global SAI_TxGetDefaultConfig (sai_config_t *config)
+
Do not use this function. It has been superceded by SAI_GetClassicI2SConfig, SAI_GetLeftJustifiedConfig , SAI_GetRightJustifiedConfig, SAI_GetDSPConfig, SAI_GetTDMConfig
+
Global SAI_TxInit (I2S_Type *base, const sai_config_t *config)
+
Do not use this function. It has been superceded by SAI_Init
+
Global SAI_TxSetFormat (I2S_Type *base, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, uint32_t bclkSourceClockHz)
+
Do not use this function. It has been superceded by SAI_TxSetConfig
+
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/arm_logo.png b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/arm_logo.png new file mode 100644 index 000000000..bdf487c12 Binary files /dev/null and b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/arm_logo.png differ diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/bc_s.png b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/bc_s.png new file mode 100644 index 000000000..224b29aa9 Binary files /dev/null and b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/bc_s.png differ diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/bdwn.png b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/bdwn.png new file mode 100644 index 000000000..940a0b950 Binary files /dev/null and b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/bdwn.png differ diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/closed.png b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/closed.png new file mode 100644 index 000000000..98cc2c909 Binary files /dev/null and b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/closed.png differ diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/customdoxygen.css b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/customdoxygen.css new file mode 100644 index 000000000..262bfa4e8 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/customdoxygen.css @@ -0,0 +1,94 @@ + +body { + color: #51626f; +} + +body, table, div, p, dl { + font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; +} + +.title { + font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; +} + +.textblock ul { + list-style: none outside url("data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAYAAAAGCAYAAADgzO9IAAAAF0lEQVQIHWP8uZXhPwMWwIRFDCxEDwkAjygCuZMRiw4AAAAASUVORK5CYII="); +} + +h1, h2.groupheader { + color: #51626f; + font-size: 21px; +} + +h1 { + font-weight: 600; +} + +h2 { + font-size: 18px; +} + +.tablist a, +.tablist a:hover { + text-shadow: none; + background-image: none; +} + +.tablist a { + color: #ffffff; +} + +.tablist a:hover { + background-color: #f2f2f5; + color: #007088; +} + +.tablist li.current a { + text-shadow: none; + background-image: none; + background-color: #ffffff; + color: #777777; +} + +.navpath ul { + background-image: none; + background-color: #e6e6e6; + color: #646464; +} + +.tabs, .tabs2, .tabs3, +.tablist li { + background: rgba(0, 0, 0, 0) linear-gradient(to bottom, #f1b635, #e4942a) repeat scroll 0 0; +} + +a { + color: #5e89c1; +} + +#nav-tree .selected { + text-shadow: none; + background-image: none; + background-color: #e6e6e6; + color: #646464; +} + +#nav-tree .selected a { + color: #646464; +} + +#titlearea { + border-bottom: 1px solid #51626f; +} + +#projectname { + font: 32px "Helvetica Neue", Helvetica, Arial; +} + +div.image img[src="Kinetis_SDK_Block_Diagram.png"]{ + width:600px; +} + +.image { + text-align: center; +} + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/debug_console_overview.jpg b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/debug_console_overview.jpg new file mode 100644 index 000000000..68b887c48 Binary files /dev/null and b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/debug_console_overview.jpg differ diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_07b86ffc266b39efa5bbdc0e9fdb330a.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_07b86ffc266b39efa5bbdc0e9fdb330a.html new file mode 100644 index 000000000..c98e5e0d7 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_07b86ffc266b39efa5bbdc0e9fdb330a.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/devices Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
devices Directory Reference
+
+
+ + + + +

+Directories

directory  MIMX8MQ6
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_1a5e79e6cde7a8f7a17b9bc6aea91d8e.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_1a5e79e6cde7a8f7a17b9bc6aea91d8e.html new file mode 100644 index 000000000..9a29968e2 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_1a5e79e6cde7a8f7a17b9bc6aea91d8e.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/drivers/sema4 Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
sema4 Directory Reference
+
+
+ + + + +

+Files

file  fsl_sema4.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_2e35e6cf5123a5e911b01bb4d64a0ba5.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_2e35e6cf5123a5e911b01bb4d64a0ba5.html new file mode 100644 index 000000000..ac6350e49 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_2e35e6cf5123a5e911b01bb4d64a0ba5.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/devices/MIMX8MQ6 Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
MIMX8MQ6 Directory Reference
+
+
+ + + + +

+Directories

directory  drivers
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_409f97388efe006bc3438b95e9edef48.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_409f97388efe006bc3438b95e9edef48.html new file mode 100644 index 000000000..ee01a1381 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_409f97388efe006bc3438b95e9edef48.html @@ -0,0 +1,124 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/components Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
components Directory Reference
+
+
+ + + + + + +

+Directories

directory  codec
 
directory  serial_manager
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_439aa49903cb854e0611cde789c2accb.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_439aa49903cb854e0611cde789c2accb.html new file mode 100644 index 000000000..7b414bc0b --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_439aa49903cb854e0611cde789c2accb.html @@ -0,0 +1,124 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/drivers/iuart Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
iuart Directory Reference
+
+
+ + + + + + +

+Files

file  fsl_uart.h
 
file  fsl_uart_freertos.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_4d587534c930721bb7699d438d28eeba.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_4d587534c930721bb7699d438d28eeba.html new file mode 100644 index 000000000..1bf5acb3b --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_4d587534c930721bb7699d438d28eeba.html @@ -0,0 +1,126 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/cmsis_drivers Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
cmsis_drivers Directory Reference
+
+
+ + + + + + + + +

+Directories

directory  ecspi
 
directory  ii2c
 
directory  iuart
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_546b01b78826fc49268112f909d12f41.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_546b01b78826fc49268112f909d12f41.html new file mode 100644 index 000000000..3ce5ddfe1 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_546b01b78826fc49268112f909d12f41.html @@ -0,0 +1,124 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/devices/MIMX8MQ6/drivers Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
drivers Directory Reference
+
+
+ + + + + + +

+Files

file  fsl_clock.h
 
file  fsl_iomuxc.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_598901b0422b62d1b877d2d0d566bac0.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_598901b0422b62d1b877d2d0d566bac0.html new file mode 100644 index 000000000..64c3d50cb --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_598901b0422b62d1b877d2d0d566bac0.html @@ -0,0 +1,124 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/drivers/ecspi Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
ecspi Directory Reference
+
+
+ + + + + + +

+Files

file  fsl_ecspi.h
 
file  fsl_ecspi_freertos.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_675f9f61ca74e4999b71747fe2b6f630.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_675f9f61ca74e4999b71747fe2b6f630.html new file mode 100644 index 000000000..7eb18c095 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_675f9f61ca74e4999b71747fe2b6f630.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/drivers/gpt Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
gpt Directory Reference
+
+
+ + + + +

+Files

file  fsl_gpt.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_695421cc36b9b5355445d751498b0174.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_695421cc36b9b5355445d751498b0174.html new file mode 100644 index 000000000..7c639f750 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_695421cc36b9b5355445d751498b0174.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/drivers/igpio Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
igpio Directory Reference
+
+
+ + + + +

+Files

file  fsl_gpio.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_72239d8cd728703b50a733950290957c.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_72239d8cd728703b50a733950290957c.html new file mode 100644 index 000000000..3642fc64d --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_72239d8cd728703b50a733950290957c.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/drivers/tmu Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
tmu Directory Reference
+
+
+ + + + +

+Files

file  fsl_tmu.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_81378354e1f131cbc78d326df98fa777.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_81378354e1f131cbc78d326df98fa777.html new file mode 100644 index 000000000..8df6a959c --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_81378354e1f131cbc78d326df98fa777.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/components/codec/port/wm8524 Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
wm8524 Directory Reference
+
+
+ + + + +

+Files

file  fsl_codec_wm8524_adapter.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_83c4f67939b2e50b6dc50fe3fc259b2d.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_83c4f67939b2e50b6dc50fe3fc259b2d.html new file mode 100644 index 000000000..88f172b69 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_83c4f67939b2e50b6dc50fe3fc259b2d.html @@ -0,0 +1,150 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/drivers Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
drivers Directory Reference
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Directories

directory  common
 
directory  ecspi
 
directory  gpt
 
directory  igpio
 
directory  ii2c
 
directory  ipwm
 
directory  iuart
 
directory  mu
 
directory  qspi
 
directory  rdc
 
directory  rdc_sema42
 
directory  sai
 
directory  sema4
 
directory  tmu
 
directory  wdog01
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_919453c527cd3b17be9d0977f49b7a97.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_919453c527cd3b17be9d0977f49b7a97.html new file mode 100644 index 000000000..429af3c57 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_919453c527cd3b17be9d0977f49b7a97.html @@ -0,0 +1,129 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/components/codec Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
codec Directory Reference
+
+
+ + + + + + +

+Directories

directory  port
 
directory  wm8524
 
+ + + +

+Files

file  fsl_codec_common.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_9808b1dbc7a3d4b3d8b414738fccb85f.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_9808b1dbc7a3d4b3d8b414738fccb85f.html new file mode 100644 index 000000000..5e14b0358 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_9808b1dbc7a3d4b3d8b414738fccb85f.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/components/codec/wm8524 Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
wm8524 Directory Reference
+
+
+ + + + +

+Files

file  fsl_wm8524.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_9d7943276f7f59eae0f94ff2d28103c6.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_9d7943276f7f59eae0f94ff2d28103c6.html new file mode 100644 index 000000000..d4fe9be97 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_9d7943276f7f59eae0f94ff2d28103c6.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/drivers/qspi Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
qspi Directory Reference
+
+
+ + + + +

+Files

file  fsl_qspi.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_a343a3e9cbb710280ccd0de2056b945d.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_a343a3e9cbb710280ccd0de2056b945d.html new file mode 100644 index 000000000..f202b7e03 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_a343a3e9cbb710280ccd0de2056b945d.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/utilities/misc_utilities Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
misc_utilities Directory Reference
+
+
+ + + + +

+Files

file  fsl_format.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_b5759f6cd324301c8d375e44421eccc5.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_b5759f6cd324301c8d375e44421eccc5.html new file mode 100644 index 000000000..8020ba115 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_b5759f6cd324301c8d375e44421eccc5.html @@ -0,0 +1,129 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/utilities/debug_console Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
debug_console Directory Reference
+
+
+ + + + +

+Directories

directory  str
 
+ + + + + +

+Files

file  fsl_debug_console.h
 
file  fsl_debug_console_conf.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_b96e454a38a6bfeaaa08570bbcdf434e.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_b96e454a38a6bfeaaa08570bbcdf434e.html new file mode 100644 index 000000000..b98343b7f --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_b96e454a38a6bfeaaa08570bbcdf434e.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/drivers/rdc_sema42 Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
rdc_sema42 Directory Reference
+
+
+ + + + +

+Files

file  fsl_rdc_sema42.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_bb3b07144e84a0cb0d108309e2ae4920.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_bb3b07144e84a0cb0d108309e2ae4920.html new file mode 100644 index 000000000..6ece26d13 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_bb3b07144e84a0cb0d108309e2ae4920.html @@ -0,0 +1,124 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/drivers/ii2c Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
ii2c Directory Reference
+
+
+ + + + + + +

+Files

file  fsl_i2c.h
 
file  fsl_i2c_freertos.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_bf71e8795d5ec3bf1a04b9a740296e07.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_bf71e8795d5ec3bf1a04b9a740296e07.html new file mode 100644 index 000000000..02b81a577 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_bf71e8795d5ec3bf1a04b9a740296e07.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/drivers/sai Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
sai Directory Reference
+
+
+ + + + +

+Files

file  fsl_sai.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_c35ca6965aa29b760300e697294724bc.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_c35ca6965aa29b760300e697294724bc.html new file mode 100644 index 000000000..3c4819ad8 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_c35ca6965aa29b760300e697294724bc.html @@ -0,0 +1,127 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/components/codec/port Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
port Directory Reference
+
+
+ + + + +

+Directories

directory  wm8524
 
+ + + +

+Files

file  fsl_codec_adapter.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_c40bbae3f5b4218bd9ec044c32f0ea1b.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_c40bbae3f5b4218bd9ec044c32f0ea1b.html new file mode 100644 index 000000000..390d303bb --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_c40bbae3f5b4218bd9ec044c32f0ea1b.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/cmsis_drivers/iuart Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
iuart Directory Reference
+
+
+ + + + +

+Files

file  fsl_uart_cmsis.h
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_c5a52a81292cf9a5167198f4f346d6d9.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_c5a52a81292cf9a5167198f4f346d6d9.html new file mode 100644 index 000000000..d2944cd61 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_c5a52a81292cf9a5167198f4f346d6d9.html @@ -0,0 +1,126 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
platform Directory Reference
+
+
+ + + + + + + + +

+Directories

directory  cmsis_drivers
 
directory  drivers
 
directory  utilities
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_d0b0cea4c1afa919405231e98537b73c.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_d0b0cea4c1afa919405231e98537b73c.html new file mode 100644 index 000000000..e992abd0f --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_d0b0cea4c1afa919405231e98537b73c.html @@ -0,0 +1,124 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/utilities Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
utilities Directory Reference
+
+
+ + + + + + +

+Directories

directory  debug_console
 
directory  misc_utilities
 
+
+
+ + + + + diff --git a/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_d2b15e30b0d01e2b67d403043b348a1c.html b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_d2b15e30b0d01e2b67d403043b348a1c.html new file mode 100644 index 000000000..8cd6bba78 --- /dev/null +++ b/docs/MCUXpresso SDK API Reference Manual_MIMX8MQ6/dir_d2b15e30b0d01e2b67d403043b348a1c.html @@ -0,0 +1,122 @@ + + + + + + +MCUXpresso SDK API Reference Manual: /home/nxf66276/jenkins_home/workspace/sdk_git/platform/cmsis_drivers/ii2c Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
ii2c Directory Reference
+
+
+ + + + +

+Files

file  fsl_i2c_cmsis.h
 
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+
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file  fsl_component_serial_manager.h
 
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+ -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3D578C; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4665A2; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9CAFD4; + color: #ffffff; + border: 1px double #869DCA; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited, a.line, a.line:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 0px; + margin: 0px; + background-color: #FBFCFD; + border: 1px solid #C4CFE5; +} + +div.line { + font-family: monospace, fixed; + font-size: 13px; + min-height: 13px; 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+} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C4CFE5; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C4CFE5; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EEF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9CAFD4; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4A6AAA; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td, .fieldtable tr { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; 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+ color: #4665A2; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; + display: table !important; + width: 100%; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 0px 6px 0px; + color: #253555; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} +.paramname code { + line-height: 14px; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #728DC1; + border-top:1px solid #5373B4; + border-left:1px solid #5373B4; + border-right:1px solid #C4CFE5; + border-bottom:1px solid #C4CFE5; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; + vertical-align: middle; +} + + + +/* @end */ + +/* these are for tree view when not used as main index */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; + padding-top: 3px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.entry a img { + border: none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + padding-top: 3px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3D578C; +} + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #2A3D61; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + /*width: 100%;*/ + margin-bottom: 10px; + border: 1px solid #A8B8D9; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + vertical-align: top; +} + +.fieldtable td.fieldname { + padding-top: 3px; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A8B8D9; + /*width: 100%;*/ +} + +.fieldtable td.fielddoc p:first-child { + margin-top: 0px; +} + +.fieldtable td.fielddoc p:last-child { + margin-bottom: 2px; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + font-size: 90%; + color: #253555; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A8B8D9; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + background-position: 0 -5px; + height:30px; + line-height:30px; + color:#8AA0CC; + border:solid 1px #C2CDE4; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#364D7C; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; + color: #283A5D; + font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; +} + +.navpath li.navelem a:hover +{ + color:#6884BD; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#364D7C; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + font-size: 8pt; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C4CFE5; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +dl +{ + padding: 0 0 0 10px; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ +dl.section +{ + margin-left: 0px; + padding-left: 0px; +} + +dl.note +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00D000; +} + +dl.deprecated +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #505050; +} + +dl.todo +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00C0E0; +} + +dl.test +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #3030E0; +} + +dl.bug +{ + margin-left:-7px; + padding-left: 3px; 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+ padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D8DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 20px 10px 10px; + width: 200px; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4665A2; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +/* tooltip related style info */ + +.ttc { + position: absolute; + display: none; +} + +#powerTip { + cursor: default; + white-space: nowrap; + background-color: white; + border: 1px solid gray; + border-radius: 4px 4px 4px 4px; + box-shadow: 1px 1px 7px gray; + display: none; + font-size: smaller; + max-width: 80%; + opacity: 0.9; + padding: 1ex 1em 1em; + position: absolute; + z-index: 2147483647; +} + +#powerTip div.ttdoc { + color: grey; + font-style: italic; +} + +#powerTip div.ttname a { + font-weight: bold; +} + +#powerTip div.ttname { + font-weight: bold; +} + +#powerTip div.ttdeci { + color: #006318; +} + +#powerTip div { + margin: 0px; + padding: 0px; + font: 12px/16px Roboto,sans-serif; +} + +#powerTip:before, #powerTip:after { + content: ""; + position: absolute; + margin: 0px; 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+ var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); +} +function toggleLevel(level) +{ + $('table.directory tr').each(function(){ + var l = this.id.split('_').length-1; + var i = $('#img'+this.id.substring(3)); + var a = $('#arr'+this.id.substring(3)); + if (l + + + + + +MCUXpresso SDK API Reference Manual: Introduction + + + + + + + + + + + + + + +
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MCUXpresso SDK API Reference Manual +  Rev. 0 +
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NXP Semiconductors
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Introduction
+
+
+

The MCUXpresso Software Development Kit (MCUXpresso SDK) is a collection of software enablement for NXP Microcontrollers that includes peripheral drivers, multicore support and integrated RTOS support for FreeRTOSTM. In addition to the base enablement, the MCUXpresso SDK is augmented with demo applications, driver example projects, and API documentation to help users quickly leverage the support provided by MCUXpresso SDK. The MCUXpresso SDK Web Builder is available to provide access to all MCUXpresso SDK packages. See the MCUXpresso Software Development Kit (SDK) Release Notes (document MCUXSDKRN) in the Supported Devices section at MCUXpresso-SDK: Software Development Kit for MCUXpresso for details.

+

The MCUXpresso SDK is built with the following runtime software components:

+
    +
  • +Arm® and DSP standard libraries, and CMSIS-compliant device header files which provide direct access to the peripheral registers.
    • +
  • +Peripheral drivers that provide stateless, high-performance, ease-of-use APIs. Communication drivers provide higher-level transactional APIs for a higher-performance option.
    • +
  • +RTOS wrapper driver built on top of MCUXpresso SDK peripheral drivers and leverage native RTOS services to better comply to the RTOS cases.
    • +
  • +Real time operation systems (RTOS) for FreeRTOS OS.
    • +
  • +

    Stacks and middleware in source or object formats including:

    +
      +
    • +CMSIS-DSP, a suite of common signal processing functions.
      • +
    • +The MCUXpresso SDK comes complete with software examples demonstrating the usage of the peripheral drivers, RTOS wrapper drivers, middleware, and RTOSes.
      • +
    +

    +

    All demo applications and driver examples are provided with projects for the following toolchains:

    +
      +
    • +IAR Embedded Workbench
      • +
    • +GNU Arm Embedded Toolchain
      • +
    +
    • +
+

The peripheral drivers and RTOS driver wrappers can be used across multiple devices within the product family without modification. The configuration items for each driver are encapsulated into C language data structures. Device-specific configuration information is provided as part of the MCUXpresso SDK and need not be modified by the user. If necessary, the user is able to modify the peripheral driver and RTOS wrapper driver configuration during runtime. The driver examples demonstrate how to configure the drivers by passing the proper configuration data to the APIs. The folder structure is organized to reduce the total number of includes required to compile a project.

+ + + + + + + + + + + + + + + + + + + + + + +
MCUXpresso SDK Folder Structure
DeliverableLocation
Demo Applications<install_dir>/boards/<board_name>/demo_apps
Driver Examples<install_dir>/boards/<board_name>/driver_examples
Documentation<install_dir>/docs
Middleware<install_dir>/middleware
Drivers<install_dir>/<device_name>/drivers/
CMSIS Standard Arm Cortex-M Headers, math and DSP Libraries<install_dir>/CMSIS
Device Startup and Linker<install_dir>/<device_name>/<toolchain>/
MCUXpresso SDK Utilities<install_dir>/devices/<device_name>/utilities
RTOS Kernel Code<install_dir>/rtos
+

The rest of this document describes the API references in detail for the peripheral drivers and RTOS wrapper drivers. For the latest version of this and other MCUXpresso SDK documents, see the mcuxpresso.nxp.com/apidoc/.

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+
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0},disableSelection:function(){return this.bind((a.support.selectstart?"selectstart":"mousedown")+".ui-disableSelection",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(".ui-disableSelection")}});a.each(["Width","Height"],function(g,e){var f=e==="Width"?["Left","Right"]:["Top","Bottom"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,"padding"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,"border"+this+"Width",true))||0}if(n){l-=parseFloat(a.curCSS(m,"margin"+this,true))||0}});return l}a.fn["inner"+e]=function(i){if(i===d){return k["inner"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+"px")})};a.fn["outer"+e]=function(i,l){if(typeof i!=="number"){return k["outer"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+"px")})}});function c(g,e){var j=g.nodeName.toLowerCase();if("area"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!=="map"){return false}f=a("img[usemap=#"+h+"]")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:"a"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,"visibility")==="hidden"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[":"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,"tabindex")))},tabbable:function(g){var e=a.attr(g,"tabindex"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement("div"));f.offsetHeight;a.extend(f.style,{minHeight:"100px",height:"auto",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart="onselectstart" in f;e.removeChild(f).style.display="none"});a.extend(a.ui,{plugin:{add:function(f,g,j){var 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http://jquery.org/license + * + * http://docs.jquery.com/UI/Mouse + * + * Depends: + * jquery.ui.widget.js + */ +(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return 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true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('
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');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var 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+
+
API Reference
+
+
+
Here is a list of all modules:
+
[detail level 123]
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
oCODEC Driver
|oCODEC Common Driver
||oCODEC Adapter
||\WM8524 Adapter
|oCODEC I2C Driver
|\WM8524 Driver
oClock Driver
oCommon Driver
oDebug Console
|oSWO
|\Semihosting
oECSPI: Enhanced Configurable Serial Peripheral Interface Driver
|oECSPI CMSIS Driver
|oECSPI Driver
|\ECSPI FreeRTOS Driver
oGPIO: General-Purpose Input/Output Driver
oGPT: General Purpose Timer
oI2C: Inter-Integrated Circuit Driver
|oI2C CMSIS Driver
|oI2C Driver
|\I2C FreeRTOS Driver
oIOMUXC: IOMUX Controller
oMU: Messaging Unit
oPWM: Pulse Width Modulation Driver
oQSPI: Quad Serial Peripheral Interface
|\Quad Serial Peripheral Interface Driver
oRDC: Resource Domain Controller
oRDC_SEMA42: Hardware Semaphores Driver
oSAI EDMA Driver
oSAI: Serial Audio Interface
|\SAI Driver
oSEMA4: Hardware Semaphores Driver
oSerial Manager
|oSerial Port SWO
|\Serial Port Uart
oTMU: Thermal Management Unit Driver
oUART: Universal Asynchronous Receiver/Transmitter Driver
|oUART CMSIS Driver
|oUART Driver
|\UART FreeRTOS Driver
\WDOG: Watchdog Timer Driver
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'inline-block'; + span.style.width = 16*(level+1)+'px'; + span.style.height = '22px'; + span.innerHTML = ' '; + domNode.appendChild(span); + } +} + +var animationInProgress = false; + +function gotoAnchor(anchor,aname,updateLocation) +{ + var pos, docContent = $('#doc-content'); + if (anchor.parent().attr('class')=='memItemLeft' || + anchor.parent().attr('class')=='fieldtype' || + anchor.parent().is(':header')) + { + pos = anchor.parent().position().top; + } else if (anchor.position()) { + pos = anchor.position().top; + } + if (pos) { + var dist = Math.abs(Math.min( + pos-docContent.offset().top, + docContent[0].scrollHeight- + docContent.height()-docContent.scrollTop())); + animationInProgress=true; + docContent.animate({ + scrollTop: pos + docContent.scrollTop() - docContent.offset().top + },Math.max(50,Math.min(500,dist)),function(){ + if (updateLocation) window.location.href=aname; + animationInProgress=false; + }); + } +} + +function newNode(o, po, text, link, childrenData, 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node.li.appendChild(node.childrenUL); + } + return node.childrenUL; + }; + + return node; +} + +function showRoot() +{ + var headerHeight = $("#top").height(); + var footerHeight = $("#nav-path").height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + (function (){ // retry until we can scroll to the selected item + try { + var navtree=$('#nav-tree'); + navtree.scrollTo('#selected',0,{offset:-windowHeight/2}); + } catch (err) { + setTimeout(arguments.callee, 0); + } + })(); +} + +function expandNode(o, node, imm, showRoot) +{ + if (node.childrenData && !node.expanded) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + expandNode(o, node, imm, showRoot); + }, showRoot); + } else { + if (!node.childrenVisited) { + getNode(o, node); + } if (imm || ($.browser.msie && $.browser.version>8)) { + // somehow slideDown jumps to the start of tree for IE9 :-( + $(node.getChildrenUL()).show(); + } else { + $(node.getChildrenUL()).slideDown("fast"); + } + if (node.isLast) { + node.plus_img.src = node.relpath+"ftv2mlastnode.png"; + } else { + node.plus_img.src = node.relpath+"ftv2mnode.png"; + } + node.expanded = true; + } + } +} + +function glowEffect(n,duration) +{ + n.addClass('glow').delay(duration).queue(function(next){ + $(this).removeClass('glow');next(); + }); +} + +function highlightAnchor() +{ + var aname = $(location).attr('hash'); + var anchor = $(aname); + if (anchor.parent().attr('class')=='memItemLeft'){ + var rows = $('.memberdecls tr[class$="'+ + window.location.hash.substring(1)+'"]'); + glowEffect(rows.children(),300); // member without details + } else if (anchor.parents().slice(2).prop('tagName')=='TR') { + glowEffect(anchor.parents('div.memitem'),1000); // enum value + } else if (anchor.parent().attr('class')=='fieldtype'){ + glowEffect(anchor.parent().parent(),1000); // struct field + } else if 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+
+ + + + + + + +
+
MCUXpresso SDK API Reference Manual +  Rev. 0 +
+
NXP Semiconductors
+
+
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+
+
+ +
+ + + + +
+ +
+ +
+
+
Related Pages
+
+
+
Here is a list of all related documentation pages:
+ + + + + +
oTrademarks
oArchitectural Overview
oDriver errors status
\Deprecated List
+
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+ +var indexSectionNames = +{ + 0: "all", + 1: "classes", + 2: "functions", + 3: "variables", + 4: "typedefs", + 5: "enums", + 6: "enumvalues", + 7: "groups", + 8: "pages" +}; + +function convertToId(search) +{ + var result = ''; + for (i=0;i do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; 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+ + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of . + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName == 'DIV' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName == 'DIV' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + var newIndex = itemIndex-1; + var focusItem = this.NavPrev(newIndex); + if (focusItem) + { + var child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') // children visible + { + var n=0; + var tmpElem; + while (1) // search for last child + { + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) + { + focusItem = tmpElem; + } + else // found it! + { + break; + } + n++; + } + } + } + if (focusItem) + { + focusItem.focus(); + } + else // return focus to search field + { + parent.document.getElementById("MSearchField").focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = itemIndex+1; + var focusItem; + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') // children visible + { + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } + else if (this.lastKey==39) // Right + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } + else if (this.lastKey==37) // Left + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + if (childIndex>0) + { + var newIndex = childIndex-1; + document.getElementById('Item'+itemIndex+'_c'+newIndex).focus(); + } + else // already at first child, jump to parent + { + document.getElementById('Item'+itemIndex).focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = childIndex+1; + var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex); + if (!elem) // last child, jump to parent next parent + { + elem = this.NavNext(itemIndex+1); + } + if (elem) + { + elem.focus(); + } + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } +} + +function setKeyActions(elem,action) +{ + elem.setAttribute('onkeydown',action); + elem.setAttribute('onkeypress',action); + elem.setAttribute('onkeyup',action); +} + +function setClassAttr(elem,attr) +{ + elem.setAttribute('class',attr); + elem.setAttribute('className',attr); +} + +function createResults() +{ + var results = document.getElementById("SRResults"); + for (var e=0; e + + + + + + + + +
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+ text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} diff --git a/docs/MCUXpresso SDK ChangeLog_MIMX8MQ6.pdf b/docs/MCUXpresso SDK ChangeLog_MIMX8MQ6.pdf new file mode 100644 index 000000000..cd7bf7366 Binary files /dev/null and b/docs/MCUXpresso SDK ChangeLog_MIMX8MQ6.pdf differ diff --git a/docs/MCUXpresso SDK Release Notes for EVK-MIMX8MQ.pdf b/docs/MCUXpresso SDK Release Notes for EVK-MIMX8MQ.pdf new file mode 100644 index 000000000..a6f9ba4fa Binary files /dev/null and b/docs/MCUXpresso SDK Release Notes for EVK-MIMX8MQ.pdf differ diff --git a/middleware/multicore/middleware_multicore_rpmsg_lite_MIMX8MQ6.cmake b/middleware/multicore/middleware_multicore_rpmsg_lite_MIMX8MQ6.cmake new file mode 100644 index 000000000..894673a69 --- /dev/null +++ b/middleware/multicore/middleware_multicore_rpmsg_lite_MIMX8MQ6.cmake @@ -0,0 +1,29 @@ +include_guard(GLOBAL) +message("middleware_multicore_rpmsg_lite component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/rpmsg_lite/lib/common/llist.c + ${CMAKE_CURRENT_LIST_DIR}/rpmsg_lite/lib/rpmsg_lite/rpmsg_lite.c + ${CMAKE_CURRENT_LIST_DIR}/rpmsg_lite/lib/rpmsg_lite/rpmsg_ns.c + ${CMAKE_CURRENT_LIST_DIR}/rpmsg_lite/lib/virtio/virtqueue.c +) + +if(CONFIG_USE_middleware_baremetal_MIMX8MQ6) +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/rpmsg_lite/lib/rpmsg_lite/porting/environment/rpmsg_env_bm.c +) +elseif(CONFIG_USE_middleware_freertos-kernel_MIMX8MQ6) +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/rpmsg_lite/lib/rpmsg_lite/porting/environment/rpmsg_env_freertos.c + ${CMAKE_CURRENT_LIST_DIR}/rpmsg_lite/lib/rpmsg_lite/rpmsg_queue.c +) +else() + message(WARNING "please config middleware.baremetal_MIMX8MQ6 or middleware.freertos-kernel_MIMX8MQ6 first.") +endif() + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/rpmsg_lite/lib/include +) + + diff --git a/middleware/multicore/middleware_multicore_rpmsg_lite_imx8mq_m4_freertos_MIMX8MQ6.cmake b/middleware/multicore/middleware_multicore_rpmsg_lite_imx8mq_m4_freertos_MIMX8MQ6.cmake new file mode 100644 index 000000000..d64fbc512 --- /dev/null +++ b/middleware/multicore/middleware_multicore_rpmsg_lite_imx8mq_m4_freertos_MIMX8MQ6.cmake @@ -0,0 +1,17 @@ +include_guard(GLOBAL) +message("middleware_multicore_rpmsg_lite_imx8mq_m4_freertos component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/rpmsg_lite/lib/rpmsg_lite/porting/platform/imx8mq_m4/rpmsg_platform.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/rpmsg_lite/lib/include/platform/imx8mq_m4 +) + + +include(middleware_multicore_rpmsg_lite_MIMX8MQ6) + +include(middleware_freertos-kernel_MIMX8MQ6) + diff --git a/middleware/multicore/rpmsg_lite/lib/include/platform/imx8mq_m4/rpmsg_platform.h b/middleware/multicore/rpmsg_lite/lib/include/platform/imx8mq_m4/rpmsg_platform.h new file mode 100644 index 000000000..9b21b2d3c --- /dev/null +++ b/middleware/multicore/rpmsg_lite/lib/include/platform/imx8mq_m4/rpmsg_platform.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef RPMSG_PLATFORM_H_ +#define RPMSG_PLATFORM_H_ + +#include + +/* RPMSG MU channel index */ +#define RPMSG_MU_CHANNEL (1) + +/* + * Linux requires the ALIGN to 0x1000(4KB) instead of 0x80 + */ +#ifndef VRING_ALIGN +#define VRING_ALIGN (0x1000U) +#endif + +/* contains pool of descriptors and two circular buffers */ +#ifndef VRING_SIZE +#define VRING_SIZE (0x8000UL) +#endif + +/* size of shared memory + 2*VRING size */ +#define RL_VRING_OVERHEAD (2UL * VRING_SIZE) + +#define RL_GET_VQ_ID(link_id, queue_id) (((queue_id)&0x1U) | (((link_id) << 1U) & 0xFFFFFFFEU)) +#define RL_GET_LINK_ID(id) (((id)&0xFFFFFFFEU) >> 1U) +#define RL_GET_Q_ID(id) ((id)&0x1U) + +#define RL_PLATFORM_IMX8MQ_M4_USER_LINK_ID (0U) +#define RL_PLATFORM_HIGHEST_LINK_ID (15U) + +/* platform interrupt related functions */ +int32_t platform_init_interrupt(uint32_t vector_id, void *isr_data); +int32_t platform_deinit_interrupt(uint32_t vector_id); +int32_t platform_interrupt_enable(uint32_t vector_id); +int32_t platform_interrupt_disable(uint32_t vector_id); +int32_t platform_in_isr(void); +void platform_notify(uint32_t vector_id); + +/* platform low-level time-delay (busy loop) */ +void platform_time_delay(uint32_t num_msec); + +/* platform memory functions */ +void platform_map_mem_region(uint32_t vrt_addr, uint32_t phy_addr, uint32_t size, uint32_t flags); +void platform_cache_all_flush_invalidate(void); +void platform_cache_disable(void); +uint32_t platform_vatopa(void *addr); +void *platform_patova(uint32_t addr); + +/* platform init/deinit */ +int32_t platform_init(void); +int32_t platform_deinit(void); + +#endif /* RPMSG_PLATFORM_H_ */ diff --git a/middleware/multicore/rpmsg_lite/lib/rpmsg_lite/porting/platform/imx8mq_m4/rpmsg_platform.c b/middleware/multicore/rpmsg_lite/lib/rpmsg_lite/porting/platform/imx8mq_m4/rpmsg_platform.c new file mode 100644 index 000000000..131d48875 --- /dev/null +++ b/middleware/multicore/rpmsg_lite/lib/rpmsg_lite/porting/platform/imx8mq_m4/rpmsg_platform.c @@ -0,0 +1,278 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include "rpmsg_platform.h" +#include "rpmsg_env.h" + +#include "fsl_device_registers.h" +#include "fsl_mu.h" + +#if defined(RL_USE_ENVIRONMENT_CONTEXT) && (RL_USE_ENVIRONMENT_CONTEXT == 1) +#error "This RPMsg-Lite port requires RL_USE_ENVIRONMENT_CONTEXT set to 0" +#endif + +#define APP_MU_IRQ_PRIORITY (3U) + +static int32_t isr_counter = 0; +static int32_t disable_counter = 0; +static void *platform_lock; + +static void platform_global_isr_disable(void) +{ + __asm volatile("cpsid i"); +} + +static void platform_global_isr_enable(void) +{ + __asm volatile("cpsie i"); +} + +int32_t platform_init_interrupt(uint32_t vector_id, void *isr_data) +{ + /* Register ISR to environment layer */ + env_register_isr(vector_id, isr_data); + + /* Prepare the MU Hardware, enable channel 1 interrupt */ + env_lock_mutex(platform_lock); + + RL_ASSERT(0 <= isr_counter); + if (isr_counter == 0) + { + MU_EnableInterrupts(MUB, (1UL << 27U) >> RPMSG_MU_CHANNEL); + } + isr_counter++; + + env_unlock_mutex(platform_lock); + + return 0; +} + +int32_t platform_deinit_interrupt(uint32_t vector_id) +{ + /* Prepare the MU Hardware */ + env_lock_mutex(platform_lock); + + RL_ASSERT(0 < isr_counter); + isr_counter--; + if (isr_counter == 0) + { + MU_DisableInterrupts(MUB, (1UL << 27U) >> RPMSG_MU_CHANNEL); + } + + /* Unregister ISR from environment layer */ + env_unregister_isr(vector_id); + + env_unlock_mutex(platform_lock); + + return 0; +} + +void platform_notify(uint32_t vector_id) +{ + /* As Linux suggests, use MU->Data Channel 1 as communication channel */ + uint32_t msg = (uint32_t)(vector_id << 16); + + env_lock_mutex(platform_lock); + MU_SendMsg(MUB, RPMSG_MU_CHANNEL, msg); + env_unlock_mutex(platform_lock); +} + +/* + * MU Interrrupt RPMsg handler + */ +int32_t MU_M4_IRQHandler(void) +{ + uint32_t channel; + + if ((((1UL << 27U) >> RPMSG_MU_CHANNEL) & MU_GetStatusFlags(MUB)) != 0UL) + { + channel = MU_ReceiveMsgNonBlocking(MUB, RPMSG_MU_CHANNEL); // Read message from RX register. + env_isr(channel >> 16); + } + + return 0; +} + +/** + * platform_time_delay + * + * @param num_msec Delay time in ms. + * + * This is not an accurate delay, it ensures at least num_msec passed when return. + */ +void platform_time_delay(uint32_t num_msec) +{ + uint32_t loop; + + /* Recalculate the CPU frequency */ + SystemCoreClockUpdate(); + + /* Calculate the CPU loops to delay, each loop has 3 cycles */ + loop = SystemCoreClock / 3U / 1000U * num_msec; + + /* There's some difference among toolchains, 3 or 4 cycles each loop */ + while (loop > 0U) + { + __NOP(); + loop--; + } +} + +/** + * platform_in_isr + * + * Return whether CPU is processing IRQ + * + * @return True for IRQ, false otherwise. + * + */ +int32_t platform_in_isr(void) +{ + return (((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0UL) ? 1 : 0); +} + +/** + * platform_interrupt_enable + * + * Enable peripheral-related interrupt + * + * @param vector_id Virtual vector ID that needs to be converted to IRQ number + * + * @return vector_id Return value is never checked. + * + */ +int32_t platform_interrupt_enable(uint32_t vector_id) +{ + RL_ASSERT(0 < disable_counter); + + platform_global_isr_disable(); + disable_counter--; + + if (disable_counter == 0) + { + NVIC_EnableIRQ(MU_M4_IRQn); + } + platform_global_isr_enable(); + return ((int32_t)vector_id); +} + +/** + * platform_interrupt_disable + * + * Disable peripheral-related interrupt. + * + * @param vector_id Virtual vector ID that needs to be converted to IRQ number + * + * @return vector_id Return value is never checked. + * + */ +int32_t platform_interrupt_disable(uint32_t vector_id) +{ + RL_ASSERT(0 <= disable_counter); + + platform_global_isr_disable(); + /* virtqueues use the same NVIC vector + if counter is set - the interrupts are disabled */ + if (disable_counter == 0) + { + NVIC_DisableIRQ(MU_M4_IRQn); + } + disable_counter++; + platform_global_isr_enable(); + return ((int32_t)vector_id); +} + +/** + * platform_map_mem_region + * + * Dummy implementation + * + */ +void platform_map_mem_region(uint32_t vrt_addr, uint32_t phy_addr, uint32_t size, uint32_t flags) +{ +} + +/** + * platform_cache_all_flush_invalidate + * + * Dummy implementation + * + */ +void platform_cache_all_flush_invalidate(void) +{ +} + +/** + * platform_cache_disable + * + * Dummy implementation + * + */ +void platform_cache_disable(void) +{ +} + +/** + * platform_vatopa + * + * Dummy implementation + * + */ +uint32_t platform_vatopa(void *addr) +{ + return ((uint32_t)(char *)addr); +} + +/** + * platform_patova + * + * Dummy implementation + * + */ +void *platform_patova(uint32_t addr) +{ + return ((void *)(char *)addr); +} + +/** + * platform_init + * + * platform/environment init + */ +int32_t platform_init(void) +{ + /* + * Prepare for the MU Interrupt + * MU must be initialized before rpmsg init is called + */ + MU_Init(MUB); + NVIC_SetPriority(MU_M4_IRQn, APP_MU_IRQ_PRIORITY); + NVIC_EnableIRQ(MU_M4_IRQn); + + /* Create lock used in multi-instanced RPMsg */ + if (0 != env_create_mutex(&platform_lock, 1)) + { + return -1; + } + + return 0; +} + +/** + * platform_deinit + * + * platform/environment deinit process + */ +int32_t platform_deinit(void) +{ + /* Delete lock used in multi-instanced RPMsg */ + env_delete_mutex(platform_lock); + platform_lock = ((void *)0); + return 0; +} diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_ACIMCtrlMTPA_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_ACIMCtrlMTPA_FLT.h new file mode 100644 index 000000000..ce7408da0 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_ACIMCtrlMTPA_FLT.h @@ -0,0 +1,101 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief ACIM flux MTPA algotitm +* +*******************************************************************************/ +#ifndef _AMCLIB_ACIMFLUXMTPA_FLT_H_ +#define _AMCLIB_ACIMFLUXMTPA_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/**************************************************************************** +* Includes +****************************************************************************/ +#include "amclib_types.h" +#include "gdflib_FP.h" +#include "gflib_FP.h" +#include "gmclib_FP.h" +#include "mlib_FP.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define AMCLIB_ACIMCtrlMTPAInit_FLT_Ci( fltIDMin, fltIDMax, psCtrl) \ + AMCLIB_ACIMCtrlMTPAInit_FLT_FCi(fltIDMin, fltIDMax, psCtrl) +#define AMCLIB_ACIMCtrlMTPA_FLT_C( fltIq, psCtrl) \ + AMCLIB_ACIMCtrlMTPA_FLT_FC(fltIq, psCtrl) + +/****************************************************************************** +* Types +******************************************************************************/ +typedef struct +{ + GDFLIB_FILTER_EXP_T_FLT fltIdExpParam; /* Exponential filter structure for Id measured */ + float_t fltLowerLim; /* Min value of Id required */ + float_t fltUpperLim; /* Max value of Id required */ +} AMCLIB_ACIM_CTRL_MTPA_T_FLT; + +/**************************************************************************** +* Exported function prototypes +****************************************************************************/ +extern float_t AMCLIB_ACIMCtrlMTPA_FLT_FC(float_t fltIq, + AMCLIB_ACIM_CTRL_MTPA_T_FLT *psCtrl); + +/**************************************************************************** +* Inline functions +****************************************************************************/ + +/***************************************************************************//*! +* @brief The function initializes the actual values of float AMCLIB_ACIMCtrlMTPA_FLT function. +* +* @params: ptr AMCLIB_ACIM_CTRL_MTPA_T_FLT *psParam - Pointer to ACIM flux MTPA +* function structure +* +* @return N/A +* +*******************************************************************************/ +static inline void AMCLIB_ACIMCtrlMTPAInit_FLT_FCi(float_t fltIDMin, float_t fltIDMax, + AMCLIB_ACIM_CTRL_MTPA_T_FLT *psCtrl) +{ + GDFLIB_FilterExpInit_FLT(0.0F, &psCtrl->fltIdExpParam); + psCtrl->fltLowerLim = fltIDMin; + psCtrl->fltUpperLim = fltIDMax; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_ACIMFLUXMTPA_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_ACIMRotFluxObsrv_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_ACIMRotFluxObsrv_FLT.h new file mode 100644 index 000000000..83eff5aa8 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_ACIMRotFluxObsrv_FLT.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief ACIM Flux Observer +* +*******************************************************************************/ +#ifndef _AMCLIB_ACIMROTFLUXOBSERVER_FLT_H_ +#define _AMCLIB_ACIMROTFLUXOBSERVER_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/**************************************************************************** +* Includes +****************************************************************************/ +#include "amclib_types.h" +#include "gflib_FP.h" +#include "gmclib_FP.h" +#include "mlib_FP.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define AMCLIB_ACIMRotFluxObsrv_FLT_C( psIsAlBe, psUSAlBe, psCtrl) \ + AMCLIB_ACIMRotFluxObsrv_FLT_FC(psIsAlBe, psUSAlBe, psCtrl) +#define AMCLIB_ACIMRotFluxObsrvInit_FLT_Ci( psCtrl) \ + AMCLIB_ACIMRotFluxObsrvInit_FLT_FCi(psCtrl) + +/****************************************************************************** +* Types +******************************************************************************/ +typedef struct +{ /* function output variables */ + GMCLIB_2COOR_DQ_T_FLT sPsiRotRDQ; /* Rotor flux estimated structure from rotor (current) model, in/out structure */ + GMCLIB_2COOR_ALBE_T_FLT sPsiRotSAlBe; /* Rotor flux estimated structure from stator (voltage) model, in/out structure */ + GMCLIB_2COOR_ALBE_T_FLT sPsiStatSAlBe; /* Stator flux estimated structure from stator (voltage) model, in/out structure */ + float_t fltTorque; /* Motor torque calculated from currents and fluxes */ + acc32_t a32RotFluxPos; /* Rotor flux estimated position (angle), in/out variable */ + + /* function state variables */ + struct + { + float_t fltCompAlphaInteg_1; /* Integral part state variable for alpha coefficient */ + float_t fltCompBetaInteg_1; /* Integral part state variable for beta coefficient */ + float_t fltCompAlphaErr_1; /* Error_1 state variable for alpha coefficient */ + float_t fltCompBetaErr_1; /* Error_1 state variable for beta coefficient */ + float_t fltPGain; /* Proportional gain Kp for PI controller */ + float_t fltIGain; /* Integration gain Ki for PI controller */ + } sCtrl; + + /* function parameters */ /* Constant Tau_r = Lr/Rr, CoeffRFO */ + float_t fltPsiRA1Gain; /* Constant determined by: Tau_r / (Tau_r+Ts) */ + float_t fltPsiRB1Gain; /* Constant determined by: Lm*Ts / (Tau_r) */ + float_t fltPsiSA1Gain; /* Constant determined by: Tau_r / (Tau_r + Ts)*/ + float_t fltPsiSA2Gain; /* Constant determined by: (1 / (2*PI*CoeffRFO))/((1/(2*PI*CoeffRFO))+Ts) */ + float_t fltKrInvGain; /* Constant determined by: Lr / Lm */ + float_t fltKrLsTotLeakGain; /* Constant determined by: fltKrInvGain * Ls * (1-Lm*Lm/(Ls*Lr) */ + float_t fltRsEst; /* Estimated stator resistance = Rs [ohm] */ + float_t fltTorqueGain; /* Torque constant given by: 3*Pp*Lm/(2*Lr) */ +} AMCLIB_ACIM_ROT_FLUX_OBSRV_T_FLT; + +/**************************************************************************** +* Exported function prototypes +****************************************************************************/ +extern void AMCLIB_ACIMRotFluxObsrv_FLT_FC(const GMCLIB_2COOR_ALBE_T_FLT *psISAlBe, + const GMCLIB_2COOR_ALBE_T_FLT *psUSAlBe, + AMCLIB_ACIM_ROT_FLUX_OBSRV_T_FLT *psCtrl); + +/**************************************************************************** +* Inline functions +****************************************************************************/ + +/***************************************************************************//*! +* @brief The function initializes the actual values of float AMCLIB_ACIMRotFluxObsrv function. +* +* @params: ptr AMCLIB_ACIM_ROT_FLUX_OBSRV_T_FLT *psParam - Pointer to flux observer structure +* +* @return N/A +* +*******************************************************************************/ +static inline void AMCLIB_ACIMRotFluxObsrvInit_FLT_FCi(AMCLIB_ACIM_ROT_FLUX_OBSRV_T_FLT *psCtrl) +{ + psCtrl->sPsiRotRDQ.fltD = (float_t) 0.0F; + psCtrl->sPsiRotRDQ.fltQ = (float_t) 0.0F; + psCtrl->sPsiRotSAlBe.fltAlpha = (float_t) 0.0F; + psCtrl->sPsiRotSAlBe.fltBeta = (float_t) 0.0F; + psCtrl->sPsiStatSAlBe.fltAlpha = (float_t) 0.0F; + psCtrl->sPsiStatSAlBe.fltBeta = (float_t) 0.0F; + psCtrl->a32RotFluxPos = (acc32_t) 0; + psCtrl->sCtrl.fltCompAlphaInteg_1 = (float_t) 0.0F; + psCtrl->sCtrl.fltCompBetaInteg_1 = (float_t) 0.0F; + psCtrl->sCtrl.fltCompAlphaErr_1 = (float_t) 0.0F; + psCtrl->sCtrl.fltCompBetaErr_1 = (float_t) 0.0F; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_ACIMROTFLUXOBSERVER_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_ACIMSpeedMRAS_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_ACIMSpeedMRAS_FLT.h new file mode 100644 index 000000000..f7f43c94e --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_ACIMSpeedMRAS_FLT.h @@ -0,0 +1,127 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief ACIM Speed Estimator based on MRAS +* +*******************************************************************************/ +#ifndef _AMCLIB_ACIMSPEEDMRAS_FLT_H_ +#define _AMCLIB_ACIMSPEEDMRAS_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/**************************************************************************** +* Includes +****************************************************************************/ +#include "amclib_types.h" +#include "gdflib_FP.h" +#include "gflib_FP.h" +#include "gmclib_FP.h" +#include "mlib_FP.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define AMCLIB_ACIMSpeedMRAS_FLT_C( psIsAlBe, psPsiRAlBe, a32RotPos, psCtrl) \ + AMCLIB_ACIMSpeedMRAS_FLT_FC(psIsAlBe, psPsiRAlBe, a32RotPos, psCtrl) +#define AMCLIB_ACIMSpeedMRASInit_FLT_Ci( psCtrl) \ + AMCLIB_ACIMSpeedMRASInit_FLT_FCi(psCtrl) + +/****************************************************************************** +* Types +******************************************************************************/ +typedef struct +{ + GDFLIB_FILTER_IIR1_T_FLT fltSpeedElIIR1Param;/* IIR1 filter structure for estimated speed */ + + /* function output variables */ + GMCLIB_2COOR_DQ_T_FLT sPsiRotRDQ; /* Rotor flux estimated structure from rotor (current) model, in/out structure */ + float_t fltSpeedEl; /* Rotor estimated electric speed, output variable */ + float_t fltSpeedElIIR1; /* Rotor estimated electric speed filtered, output variable */ + float_t fltSpeedMeIIR1; /* Rotor estimated mechanical speed filtered, output variable */ + acc32_t a32RotPos; /* Rotor estimated electric position, output variable */ + + /* function state variables */ + struct + { + float_t fltSpeedElInteg_1; /* Integral part state variable for rotor electrical estimated speed controller */ + float_t fltSpeedElErr_1; /* Error_1 state variable for rotor electrical estimated speed controller */ + float_t fltPGain; /* Proportional gain Kp for MRAS PI controller */ + float_t fltIGain; /* Integration gain Ki for MRAS PI controller */ + } sCtrl; + + /* function parameters */ + float_t fltPsiRA1Gain; /* Constant determined by: Tau_r / (Tau_r+Ts) */ + float_t fltPsiRB1Gain; /* Constant determined by: Lm*Ts / (Tau_r) */ + float_t fltTs; /* Sample time constant */ + float_t fltSpeedMeGain; /* Speed gain constant given by: 60 / (2*PI*PolePairs) */ +} AMCLIB_ACIM_SPEED_MRAS_T_FLT; + +/**************************************************************************** +* Exported function prototypes +****************************************************************************/ +extern void AMCLIB_ACIMSpeedMRAS_FLT_FC(const GMCLIB_2COOR_ALBE_T_FLT *psISAlBe, + const GMCLIB_2COOR_ALBE_T_FLT *psPsiRAlBe, + acc32_t a32RotPos, + AMCLIB_ACIM_SPEED_MRAS_T_FLT *psCtrl); + +/**************************************************************************** +* Inline functions +****************************************************************************/ + +/***************************************************************************//*! +* @brief The function initializes the actual values of float AMCLIB_ACIMSpeedMRAS function. +* +* @params: ptr AMCLIB_ACIM_SPEED_MRAS_T_FLT *psParam - Pointer to MRAS structure +* +* @return N/A +* +*******************************************************************************/ +static inline void AMCLIB_ACIMSpeedMRASInit_FLT_FCi(AMCLIB_ACIM_SPEED_MRAS_T_FLT *psCtrl) +{ + GDFLIB_FilterIIR1Init_FLT (&psCtrl->fltSpeedElIIR1Param); + psCtrl->sPsiRotRDQ.fltD = (float_t) 0.0F; + psCtrl->sPsiRotRDQ.fltQ = (float_t) 0.0F; + psCtrl->fltSpeedEl = (float_t) 0.0F; + psCtrl->fltSpeedElIIR1 = (float_t) 0.0F; + psCtrl->fltSpeedMeIIR1 = (float_t) 0.0F; + psCtrl->a32RotPos = (acc32_t) 0; + psCtrl->sCtrl.fltSpeedElInteg_1 = (float_t) 0.0F; + psCtrl->sCtrl.fltSpeedElErr_1 = (float_t) 0.0F; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_ACIMSPEEDMRAS_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_AngleTrackObsrv_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_AngleTrackObsrv_F32.h new file mode 100644 index 000000000..d52f08a79 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_AngleTrackObsrv_F32.h @@ -0,0 +1,86 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Angle tracking observer +* +*******************************************************************************/ +#ifndef _AMCLIB_ANGLE_TRACK_OBSRV_F32_H_ +#define _AMCLIB_ANGLE_TRACK_OBSRV_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif +/****************************************************************************** +* Includes +******************************************************************************/ +#include "gflib.h" +#include "gmclib.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define AMCLIB_AngleTrackObsrv_F16_C(psSinCos, psCtrl) \ + AMCLIB_AngleTrackObsrv_F16_FC(psSinCos, psCtrl) +#define AMCLIB_AngleTrackObsrvInit_F16_C(f16ThetaInit, psCtrl) \ + AMCLIB_AngleTrackObsrvInit_F16_FC(f16ThetaInit, psCtrl) + +/****************************************************************************** +* Types +******************************************************************************/ +typedef struct +{ + frac32_t f32Speed; + frac32_t f32A2; + frac16_t f16Theta; + frac16_t f16SinEstim; + frac16_t f16CosEstim; + frac16_t f16K1Gain; + int16_t i16K1GainSh; + frac16_t f16K2Gain; + int16_t i16K2GainSh; + frac16_t f16A2Gain; + int16_t i16A2GainSh; +} AMCLIB_ANGLE_TRACK_OBSRV_T_F32; + +/****************************************************************************** +* Exported function prototypes +******************************************************************************/ +extern frac16_t AMCLIB_AngleTrackObsrv_F16_FC(const GMCLIB_2COOR_SINCOS_T_F16 *psSinCos, + AMCLIB_ANGLE_TRACK_OBSRV_T_F32 *psCtrl); +extern void AMCLIB_AngleTrackObsrvInit_F16_FC(frac16_t f16ThetaInit, + AMCLIB_ANGLE_TRACK_OBSRV_T_F32 *psCtrl); + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_ANGLE_TRACK_OBSRV_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_AngleTrackObsrv_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_AngleTrackObsrv_FLT.h new file mode 100644 index 000000000..d7069e0f8 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_AngleTrackObsrv_FLT.h @@ -0,0 +1,83 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Angle tracking observer +* +*******************************************************************************/ +#ifndef _AMCLIB_ANGLE_TRACK_OBSRV_FLT_H_ +#define _AMCLIB_ANGLE_TRACK_OBSRV_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif +/****************************************************************************** +* Includes +******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_FP.h" +#include "gmclib_FP.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define AMCLIB_AngleTrackObsrvInit_A32_C(a32ThetaInit, psCtrl) \ + AMCLIB_AngleTrackObsrvInit_A32_FC(a32ThetaInit, psCtrl) +#define AMCLIB_AngleTrackObsrv_A32ff_C(psSinCos, psCtrl) \ + AMCLIB_AngleTrackObsrv_A32ff_FC(psSinCos, psCtrl) + +/****************************************************************************** +* Types +******************************************************************************/ +typedef struct +{ + float_t fltSpeed; /* Estimated speed */ + frac32_t f32A2; /* Internal integrator */ + acc32_t a32Theta; /* Estimated angle <-1;1) corresponds to <-pi;pi)*/ + float_t fltSinEstim; /* Sine of the estimated angle */ + float_t fltCosEstim; /* Cosine of the estimated angle */ + float_t fltK1Gain; /* Constant to get speed from error */ + float_t fltK2Gain; /* Prop. constant to get angle from speed */ + float_t fltA2Gain; /* Integ. constant to get angle from speed */ +} AMCLIB_ANGLE_TRACK_OBSRV_T_FLT; + +/****************************************************************************** +* Exported function prototypes +******************************************************************************/ +extern acc32_t AMCLIB_AngleTrackObsrv_A32ff_FC(const GMCLIB_2COOR_SINCOS_T_FLT *psSinCos, + AMCLIB_ANGLE_TRACK_OBSRV_T_FLT *psCtrl); +extern void AMCLIB_AngleTrackObsrvInit_A32_FC(acc32_t a32ThetaInit, + AMCLIB_ANGLE_TRACK_OBSRV_T_FLT *psCtrl); +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_ANGLE_TRACK_OBSRV_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_CtrlFluxWkng_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_CtrlFluxWkng_A32.h new file mode 100644 index 000000000..04a7eaff2 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_CtrlFluxWkng_A32.h @@ -0,0 +1,104 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Flux weakening controller +* +*******************************************************************************/ +#ifndef _AMCLIB_CTRL_FLUX_WKNG_A32_H_ +#define _AMCLIB_CTRL_FLUX_WKNG_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif +/****************************************************************************** +* Includes +******************************************************************************/ +#include "gflib.h" +#include "gdflib.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define AMCLIB_CtrlFluxWkng_F16_C(f16IQErr, f16UQReq, f16UQLim, psCtrl) \ + AMCLIB_CtrlFluxWkng_F16_FC(f16IQErr, f16UQReq, f16UQLim, psCtrl) +#define AMCLIB_CtrlFluxWkngInit_F16_Ci(f16InitVal, psCtrl) \ + AMCLIB_CtrlFluxWkngInit_F16_FCi(f16InitVal, psCtrl) + +/****************************************************************************** +* Types +******************************************************************************/ +typedef struct +{ + /* function parameters */ + GFLIB_CTRL_PI_P_AW_T_A32 sFWPiParam; /* PIp controller structure for FW controller */ + GDFLIB_FILTER_IIR1_T_F32 sIqErrIIR1Param; /* Iq error IIR filter structure for Iq measured */ + + /* function parameters */ + frac16_t f16IqErrIIR1; /* Iq filtered by IIR - calculated by algorithm */ + frac16_t f16UFWErr; /* Required voltage error - calculated by algorithm */ + frac16_t f16FWErr; /* Flux weakening error - calculated by algorithm */ + bool_t *pbStopIntegFlag; /* Flux weakening controller stop integration flag - set by application */ +} AMCLIB_CTRL_FLUX_WKNG_T_A32; + +/****************************************************************************** +* Exported function prototypes +******************************************************************************/ +extern frac16_t AMCLIB_CtrlFluxWkng_F16_FC(frac16_t f16IQErr, frac16_t f16UQReq, frac16_t f16UQLim, + AMCLIB_CTRL_FLUX_WKNG_T_A32 *psCtrl); + +/***************************************************************************//*! +* +* @brief Initialization for the Flux weakening control function +* +* @param ptr AMCLIB_CTRL_FLUX_WKNG_T_A32 *psCtrl - Pointer to controller structure +* @param in frac16_t f16InitVal - Initial state value for CtrlPIpAW integrating part +* +* @return none +* +* @remarks The function initializes Flux weakening control function by following: +* +* - PI controller with anti-wind-up protection initialization. +* - Iq IIR filter initialization +* +****************************************************************************/ +static inline void AMCLIB_CtrlFluxWkngInit_F16_FCi(frac16_t f16InitVal, + AMCLIB_CTRL_FLUX_WKNG_T_A32 *psCtrl) +{ + GFLIB_CtrlPIpAWInit_F16(f16InitVal, &psCtrl->sFWPiParam); + GDFLIB_FilterIIR1Init_F16 (&psCtrl->sIqErrIIR1Param); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_CTRL_FLUX_WKNG_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_CtrlFluxWkng_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_CtrlFluxWkng_FLT.h new file mode 100644 index 000000000..ebfad6300 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_CtrlFluxWkng_FLT.h @@ -0,0 +1,108 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Flux weakening controller +* +*******************************************************************************/ +#ifndef _AMCLIB_CTRL_FLUX_WKNG_FLT_H_ +#define _AMCLIB_CTRL_FLUX_WKNG_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif +/****************************************************************************** +* Includes +******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_FP.h" +#include "gdflib_FP.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define AMCLIB_CtrlFluxWkng_FLT_C(fltIQErr, fltUQReq, fltUQLim, psCtrl) \ + AMCLIB_CtrlFluxWkng_FLT_FC(fltIQErr, fltUQReq, fltUQLim, psCtrl) +#define AMCLIB_CtrlFluxWkngInit_FLT_Ci(fltInitVal, psCtrl) \ + AMCLIB_CtrlFluxWkngInit_FLT_FCi(fltInitVal, psCtrl) + +/****************************************************************************** +* Types +******************************************************************************/ +typedef struct +{ + /* function parameters */ + GFLIB_CTRL_PI_P_AW_T_FLT sFWPiParam; /* PIp controller structure for FW controller */ + GDFLIB_FILTER_IIR1_T_FLT sIqErrIIR1Param; /* Iq error IIR filter structure for Iq measured */ + + /* function parameters */ + float_t fltIqErrIIR1; /* Iq filtered by IIR - calculated by algorithm */ + float_t fltUFWErr; /* Required voltage error - calculated by algorithm */ + float_t fltFWErr; /* Flux weakening error - calculated by algorithm */ + float_t fltIGainUgain; /* Gain for proper float scaling: fltIGainUgain = IGain / Ugain, fltIGainUgain > 0 */ + bool_t *pbStopIntegFlag; /* Flux weakening controller stop integration input flag + Set from application when saturation occurs */ +} AMCLIB_CTRL_FLUX_WKNG_T_FLT; + +/****************************************************************************** +* Exported function prototypes +******************************************************************************/ +extern float_t AMCLIB_CtrlFluxWkng_FLT_FC(float_t fltIQErr, float_t fltUQReq, float_t fltUQLim, + AMCLIB_CTRL_FLUX_WKNG_T_FLT *psCtrl); + +/***************************************************************************//*! +* +* @brief Initialization for the Flux weakening control function +* +* @param ptr AMCLIB_CTRL_FLUX_WKNG_T_FLT *psCtrl - Pointer to controller structure +* @param in float_t fltInitVal - Initial state value for CtrlPIpAW integrating part +* +* @return none +* +* @remarks The function initializes Flux weakening control function by following: +* +* - PI controller with anti-wind-up protection initialization. +* - Iq IIR filter initialization +* +****************************************************************************/ +static inline void AMCLIB_CtrlFluxWkngInit_FLT_FCi(float_t fltInitVal, + AMCLIB_CTRL_FLUX_WKNG_T_FLT *psCtrl) +{ + GFLIB_CtrlPIpAWInit_FLT(fltInitVal, &psCtrl->sFWPiParam); + GDFLIB_FilterIIR1Init_FLT (&psCtrl->sIqErrIIR1Param); +} + + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_CTRL_FLUX_WKNG_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_PMSMBemfObsrvAB_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_PMSMBemfObsrvAB_A32.h new file mode 100644 index 000000000..522f138bc --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_PMSMBemfObsrvAB_A32.h @@ -0,0 +1,126 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Algorithm of PMSM Back Electromotive Force observer in stationary +* reference frame +* +*******************************************************************************/ +#ifndef _AMCLIB_PMSM_BEMF_OBSRV_A32_AB_H_ +#define _AMCLIB_PMSM_BEMF_OBSRV_A32_AB_H_ + +#if defined(__cplusplus) +extern "C" { +#endif +/****************************************************************************** +* Includes +******************************************************************************/ +#include "gflib.h" +#include "gmclib.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define AMCLIB_PMSMBemfObsrvAB_F16_C(psIAlBe, psUAlBe, f16Speed, psCtrl) \ + AMCLIB_PMSMBemfObsrvAB_F16_FC(psIAlBe, psUAlBe, f16Speed, psCtrl) +#define AMCLIB_PMSMBemfObsrvABInit_F16_Ci(psCtrl) \ + AMCLIB_PMSMBemfObsrvABInit_F16_FCi(psCtrl) +/****************************************************************************** +* Types +******************************************************************************/ +typedef struct +{ + GMCLIB_2COOR_ALBE_T_F32 sEObsrv; /* Estimated back-EMF voltage - alpha,beta */ + GMCLIB_2COOR_ALBE_T_F32 sIObsrv; /* Estimated current - alpha,beta */ + + /* Observer parameters for controllers */ + struct + { + frac32_t f32IAlpha_1; /* Integral part state variable for alpha coefficient */ + frac32_t f32IBeta_1; /* Integral part state variable for beta coefficient */ + acc32_t a32PGain; /* Observer proportional gain coefficient */ + acc32_t a32IGain; /* Observer integral gain coefficient */ + } sCtrl; + + /* Configuration parameters */ + acc32_t a32IGain; /* Current scaling coefficient */ + acc32_t a32UGain; /* Voltage scaling coefficient */ + acc32_t a32WIGain; /* Angular speed scaling coefficient */ + acc32_t a32EGain; /* Back-emf scaling coefficient */ + + /* Unity vector */ + GMCLIB_2COOR_SINCOS_T_F16 sUnityVctr; + +} AMCLIB_BEMF_OBSRV_AB_T_A32; + +/****************************************************************************** +* Exported function prototypes +******************************************************************************/ +extern void AMCLIB_PMSMBemfObsrvAB_F16_FC(const GMCLIB_2COOR_ALBE_T_F16 *psIAlBe, + const GMCLIB_2COOR_ALBE_T_F16 *psUAlBe, + frac16_t f16Speed, + AMCLIB_BEMF_OBSRV_AB_T_A32 *psCtrl); + +/****************************************************************************** +* Inline functions +******************************************************************************/ + +/***************************************************************************//*! +* +* @brief PMSM BEMF in AB reference frame initialization +* +* @param ptr AMCLIB_BEMF_OBSRV_AB_T_A32 *psCtrl - pointer to the parameters of the observer +* +* @param in None +* +* @return None +* +* @remarks Initializes the structure of the PMSM BEMF in AB reference frame +* +* sIObsrv_f32Alpha = 0; +* sIObsrv_f32beta = 0; +* sCtrl_f32IAlpha_1= 0; +* sCtrl_f32IBeta_1 = 0; +* +****************************************************************************/ +static inline void AMCLIB_PMSMBemfObsrvABInit_F16_FCi(AMCLIB_BEMF_OBSRV_AB_T_A32 *psCtrl) +{ + psCtrl -> sIObsrv.f32Alpha = 0; + psCtrl -> sIObsrv.f32Beta = 0; + psCtrl -> sCtrl.f32IAlpha_1= 0; + psCtrl -> sCtrl.f32IBeta_1 = 0; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_PMSM_BEMF_OBSRV_A32_AB_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_PMSMBemfObsrvAB_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_PMSMBemfObsrvAB_FLT.h new file mode 100644 index 000000000..01fd6c708 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_PMSMBemfObsrvAB_FLT.h @@ -0,0 +1,129 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Algorithm of float PMSM Back Electromotive Force observer in stationary +* reference frame +* +*******************************************************************************/ +#ifndef _AMCLIB_PMSM_BEMF_OBSRV_FLT_AB_H_ +#define _AMCLIB_PMSM_BEMF_OBSRV_FLT_AB_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "amclib_types.h" +#include "mlib_FP.h" +#include "gflib_FP.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define AMCLIB_PMSMBemfObsrvAB_FLT_C(psIAlBe, psUAlBe, fltSpeed, psCtrl) \ + AMCLIB_PMSMBemfObsrvAB_FLT_FC(psIAlBe, psUAlBe, fltSpeed, psCtrl) +#define AMCLIB_PMSMBemfObsrvABInit_FLT_Ci(psCtrl) \ + AMCLIB_PMSMBemfObsrvABInit_FLT_FCi( psCtrl) +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + GMCLIB_2COOR_ALBE_T_FLT sEObsrv; /* Estimated back-EMF voltage - alpha/beta */ + GMCLIB_2COOR_ALBE_T_FLT sIObsrv; /* Estimated current - alpha/beta */ + + /* Observer parameters for controllers */ + struct + { + float_t fltIAlpha_1; /* Integral part state variable for alpha coefficient */ + float_t fltIBeta_1; /* Integral part state variable for beta coefficient */ + float_t fltPGain; /* Observer proportional gain coefficient */ + float_t fltIGain; /* Observer integral gain coefficient */ + } sCtrl; + + /* Configuration parameters */ + float_t fltIGain; /* Current scaling coefficient */ + float_t fltUGain; /* Voltage scaling coefficient */ + float_t fltWIGain; /* Angular speed scaling coefficient */ + float_t fltEGain; /* Back-emf scaling coefficient */ + + /* Unity vector */ + GMCLIB_2COOR_SINCOS_T_FLT sUnityVctr; + +} AMCLIB_BEMF_OBSRV_AB_T_FLT; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern void AMCLIB_PMSMBemfObsrvAB_FLT_FC(const GMCLIB_2COOR_ALBE_T_FLT *psIAlBe, + const GMCLIB_2COOR_ALBE_T_FLT *psUAlBe, + float_t fltSpeed, + AMCLIB_BEMF_OBSRV_AB_T_FLT *psCtrl +); + +/****************************************************************************** +* Inline functions +******************************************************************************/ + +/***************************************************************************//*! +* +* @brief PMSM BEMF in AB reference frame initialization +* +* @param ptr AMCLIB_BEMF_OBSRV_AB_T_FLT *psCtrl - pointer to the parameters of the observer +* +* @param in None +* +* @return None +* +* @remarks Initializes the structure of the PMSM BEMF in AB reference frame +* +* sIObsrv_fltAlpha = 0; +* sIObsrv_fltbeta = 0; +* sCtrl_fltIAlpha_1= 0; +* sCtrl_fltIBeta_1 = 0; +* +****************************************************************************/ +static inline void AMCLIB_PMSMBemfObsrvABInit_FLT_FCi(AMCLIB_BEMF_OBSRV_AB_T_FLT *psCtrl) +{ + psCtrl -> sIObsrv.fltAlpha = 0.0F; + psCtrl -> sIObsrv.fltBeta = 0.0F; + psCtrl -> sCtrl.fltIAlpha_1= 0.0F; + psCtrl -> sCtrl.fltIBeta_1 = 0.0F; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_PMSM_BEMF_OBSRV_FLT_AB_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_PMSMBemfObsrvDQ_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_PMSMBemfObsrvDQ_A32.h new file mode 100644 index 000000000..d8e3b96a3 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_PMSMBemfObsrvDQ_A32.h @@ -0,0 +1,125 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Algorithm of PMSM Back Electromotive Force observer in rotating +* reference frame +* +*******************************************************************************/ +#ifndef _AMCLIB_PMSM_BEMF_OBSRV_A32_DQ_H_ +#define _AMCLIB_PMSM_BEMF_OBSRV_A32_DQ_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "amclib_types.h" +#include "gflib.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define AMCLIB_PMSMBemfObsrvDQ_F16_Asm(psIDQ, psUDQ, f16Speed, psCtrl) \ + AMCLIB_PMSMBemfObsrvDQ_F16_FAsm(psIDQ, psUDQ, f16Speed, psCtrl) +#define AMCLIB_PMSMBemfObsrvDQInit_F16_Ci(psCtrl) \ + AMCLIB_PMSMBemfObsrvDQInit_F16_FCi( psCtrl) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + GMCLIB_2COOR_DQ_T_F32 sEObsrv; /* Estimated back-EMF voltage - d/q */ + GMCLIB_2COOR_DQ_T_F32 sIObsrv; /* Estimated current - d/q */ + + /* Observer parameters for controllers */ + struct + { + frac32_t f32ID_1; /* Integral part state variable for D coefficient */ + frac32_t f32IQ_1; /* Integral part state variable for Q coefficient */ + acc32_t a32PGain; /* Observer proportional gain coefficient */ + acc32_t a32IGain; /* Observer integral gain coefficient */ + } sCtrl; + + /* Configuration parameters */ + acc32_t a32IGain; /* Current scaling coefficient */ + acc32_t a32UGain; /* Voltage scaling coefficient */ + acc32_t a32WIGain; /* Angular speed scaling coefficient */ + acc32_t a32EGain; /* Back-emf scaling coefficient */ + + /* Estimated phase error between real d/q frame system and estimated d/q + reference system */ + frac16_t f16Error; + +} AMCLIB_BEMF_OBSRV_DQ_T_A32; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t AMCLIB_PMSMBemfObsrvDQ_F16_FAsm(const GMCLIB_2COOR_DQ_T_F16 *psIDQ, + const GMCLIB_2COOR_DQ_T_F16 *psUDQ, + frac16_t f16Speed, + AMCLIB_BEMF_OBSRV_DQ_T_A32 *psCtrl); +/****************************************************************************** +* Inline functions +******************************************************************************/ + +/***************************************************************************//*! +* +* @brief PMSM BEMF in DQ reference frame initialization +* +* @param ptr - AMCLIB_BEMF_OBSRV_DQ_T_A32 *psCtrl - pointer to the parameters of the observer +* +* @return None +* +* @remarks Initializes the structure of the PMSM BEMF in DQ reference frame +* +* sIObsrv_f32D = 0; +* sIObsrv_f32Q = 0; +* sCtrl_f32ID_1 = 0; +* sCtrl_f32IQ_1 = 0; +* +****************************************************************************/ +static inline void AMCLIB_PMSMBemfObsrvDQInit_F16_FCi(AMCLIB_BEMF_OBSRV_DQ_T_A32 *psCtrl) +{ + psCtrl -> sIObsrv.f32D = 0; + psCtrl -> sIObsrv.f32Q = 0; + psCtrl -> sCtrl.f32ID_1 = 0; + psCtrl -> sCtrl.f32IQ_1 = 0; +} +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_PMSM_BEMF_OBSRV_A32_DQ_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_PMSMBemfObsrvDQ_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_PMSMBemfObsrvDQ_FLT.h new file mode 100644 index 000000000..6f2011dbb --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_PMSMBemfObsrvDQ_FLT.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Algorithm of float PMSM Back Electromotive Force observer in rotating +* reference frame +* +*******************************************************************************/ +#ifndef _AMCLIB_PMSM_BEMF_OBSRV_FLT_DQ_H_ +#define _AMCLIB_PMSM_BEMF_OBSRV_FLT_DQ_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "amclib_types.h" +#include "mlib_FP.h" +#include "gflib_FP.h" +#include "GFLIB_AtanYX_FLT.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define AMCLIB_PMSMBemfObsrvDQ_A32fff_C(psIDQ, psUDQ, fltSpeed, psCtrl) \ + AMCLIB_PMSMBemfObsrvDQ_A32fff_FC(psIDQ, psUDQ, fltSpeed, psCtrl) +#define AMCLIB_PMSMBemfObsrvDQInit_A32fff_C(psCtrl) \ + AMCLIB_PMSMBemfObsrvDQInit_A32fff_FC(psCtrl) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + GMCLIB_2COOR_DQ_T_FLT sEObsrv; /* Estimated back-EMF voltage - d/q */ + GMCLIB_2COOR_DQ_T_FLT sIObsrv; /* Estimated current - d/q */ + + /* Observer parameters for controllers */ + struct + { + float_t fltID_1; /* Integral part state variable for D coefficient */ + float_t fltIQ_1; /* Integral part state variable for Q coefficient */ + float_t fltPGain; /* Observer proportional gain coefficient */ + float_t fltIGain; /* Observer integral gain coefficient */ + } sCtrl; + + /* Configuration parameters */ + float_t fltIGain; /* Current scaling coefficient */ + float_t fltUGain; /* Voltage scaling coefficient */ + float_t fltWIGain; /* Angular speed scaling coefficient */ + float_t fltEGain; /* Back-emf scaling coefficient */ + + /* Estimated phase error between real d/q frame system and estimated d/q + reference system */ + acc32_t a32Error; + +} AMCLIB_BEMF_OBSRV_DQ_T_FLT; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern acc32_t AMCLIB_PMSMBemfObsrvDQ_A32fff_FC(const GMCLIB_2COOR_DQ_T_FLT *psIDQ, + const GMCLIB_2COOR_DQ_T_FLT *psUDQ, + float_t fltSpeed, + AMCLIB_BEMF_OBSRV_DQ_T_FLT *psCtrl); +/****************************************************************************** +* Inline functions +******************************************************************************/ + +/***************************************************************************//*! +* +* @brief PMSM BEMF in DQ reference frame initialization +* +* @param ptr - AMCLIB_BEMF_OBSRV_DQ_T_FLT *psCtrl - pointer to the observer parameters +* +* @param in - None +* +* @return None +* +* @remarks Initializes the structure of the PMSM BEMF in DQ reference frame +* +* sIObsrv_fltD = 0; +* sIObsrv_fltQ = 0; +* sCtrl_fltID_1 = 0; +* sCtrl_fltIQ_1 = 0; +* +****************************************************************************/ +static inline void AMCLIB_PMSMBemfObsrvDQInit_A32fff_FC(AMCLIB_BEMF_OBSRV_DQ_T_FLT *psCtrl) +{ + psCtrl -> sIObsrv.fltD = 0.0F; + psCtrl -> sIObsrv.fltQ = 0.0F; + psCtrl -> sCtrl.fltID_1 = 0.0F; + psCtrl -> sCtrl.fltIQ_1 = 0.0F; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_PMSM_BEMF_OBSRV_FLT_DQ_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_TrackObsrv_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_TrackObsrv_F32.h new file mode 100644 index 000000000..8aa66bc0f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_TrackObsrv_F32.h @@ -0,0 +1,120 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Tracking observer +* +*******************************************************************************/ +#ifndef _AMCLIB_TRACK_OBSRV_F32_H_ +#define _AMCLIB_TRACK_OBSRV_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "amclib_types.h" +#include "mlib.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define AMCLIB_TrackObsrv_F16_Asm(f16ThetaErr, psCtrl) \ + AMCLIB_TrackObsrv_F16_FAsm(f16ThetaErr, psCtrl) +#define AMCLIB_TrackObsrvInit_F16_Ci(f16ThetaInit, psCtrl) \ + AMCLIB_TrackObsrvInit_F16_FCi(f16ThetaInit, psCtrl) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac32_t f32Theta; /* Estimated position */ + frac32_t f32Speed; /* Estimated speed - first integrator output */ + frac32_t f32I_1; /* State variable of observer controller part */ + frac16_t f16IGain; /* Observer integral gain */ + int16_t i16IGainSh; /* Observer integral gain shift*/ + frac16_t f16PGain; /* Observer proportional gain */ + int16_t i16PGainSh; /* Observer proportional gain shift*/ + frac16_t f16ThGain; /* Observer gain for output integrator of position */ + int16_t i16ThGainSh; /* Observer gain shift for integrator of position */ +}AMCLIB_TRACK_OBSRV_T_F32; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t AMCLIB_TrackObsrv_F16_FAsm(frac16_t f16ThetaErr, + AMCLIB_TRACK_OBSRV_T_F32 *psCtrl); +/****************************************************************************** +* Inline functions +******************************************************************************/ + +/***************************************************************************//*! +* +* @brief Tracking observer initialization +* +* @param in - frac16_t f16ThetaInit - init angle <-1;1) corresponds to <-pi;pi) +* @param ptr - AMCLIB_TRACK_OBSRV_T_F32 *psCtrl +* - frac32_t f32Theta - Estimated position <-1;1) corresponds to <-pi;pi) +* - frac32_t f32Speed - Estimated speed <-1;1) +* - frac16_t f32I_1 - Internal integrator <-1;1) +* - frac16_t f16IGain - Integ. constant to get speed from error <0;1) +* - int16_t i16IGainSh - Shift for f16IGain <-15;15> +* - frac16_t f16PGain - Prop. constant to get speed from angle <0;1) +* - int16_t i16PGainSh - Shift for f16PGain <-15;15> +* - frac16_t f16ThGain - Constant to get angle from speed <0;1) +* - int16_t i16ThGainSh- Shift for f16ThGain <-15;15> +* +* @return None +* +* @remarks Initializes the structure of the tracking observer with an angle +* according to following rules: +* +* f32Theta = f16ThetaInit << 16 +* f32Speed = 0 +* f32I_1 = 0 +* +****************************************************************************/ +static inline void AMCLIB_TrackObsrvInit_F16_FCi(frac16_t f16ThetaInit, + AMCLIB_TRACK_OBSRV_T_F32 *psCtrl) +{ + psCtrl -> f32Theta = MLIB_Conv_F32s(f16ThetaInit); + psCtrl -> f32Speed = 0; + psCtrl -> f32I_1 = 0; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_TRACK_OBSRV_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_TrackObsrv_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_TrackObsrv_FLT.h new file mode 100644 index 000000000..7d4ef9297 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/AMCLIB_TrackObsrv_FLT.h @@ -0,0 +1,115 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Tracking observer +* +*******************************************************************************/ +#ifndef _AMCLIB_TRACK_OBSRV_FLT_H_ +#define _AMCLIB_TRACK_OBSRV_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "amclib_types.h" +#include "mlib_FP.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define AMCLIB_TrackObsrv_A32af_C(a32ThetaErr, psCtrl) \ + AMCLIB_TrackObsrv_A32af_FC(a32ThetaErr, psCtrl) +#define AMCLIB_TrackObsrvInit_A32af_Ci(a32ThetaInit, psCtrl) \ + AMCLIB_TrackObsrvInit_A32af_FCi(a32ThetaInit, psCtrl) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac32_t f32Theta; /* Estimated position */ + float_t fltSpeed; /* Estimated speed - first integrator output */ + float_t fltI_1; /* State variable of observer controller part */ + float_t fltIGain; /* Observer integral gain */ + float_t fltPGain; /* Observer proportional gain */ + float_t fltThGain; /* Observer gain for output integrator of position */ +}AMCLIB_TRACK_OBSRV_T_FLT; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern acc32_t AMCLIB_TrackObsrv_A32af_FC(acc32_t a32ThetaErr, + AMCLIB_TRACK_OBSRV_T_FLT *psCtrl); + +/****************************************************************************** +* Inline functions +******************************************************************************/ + +/***************************************************************************//*! +* +* @brief Tracking observer initialization +* +* @param in - acc32_t a32ThetaInit - init angle <-1;1) corresponds to <-pi;pi) +* @param ptr - AMCLIB_TRACK_OBSRV_T_FLT *psCtrl +* - frac32_t f32Theta - Estimated position +* - float_t fltSpeed - Estimated speed +* - float_t fltI_1 - Internal integrator +* - float_t fltIGain - Integ. constant to get speed from error +* - float_t fltPGain - Prop. constant to get speed from angle +* - float_t fltThGain - Constant to get angle from speed +* +* @return None +* +* @remarks Initializes the structure of the tracking observer with an angle +* according to following rules: +* +* f32Theta = a32ThetaInit << 16 +* fltSpeed = 0.0F +* fltI_1 = 0.0F +* +****************************************************************************/ +static inline void AMCLIB_TrackObsrvInit_A32af_FCi(acc32_t a32ThetaInit, + AMCLIB_TRACK_OBSRV_T_FLT *psCtrl) +{ + psCtrl -> f32Theta = MLIB_Conv_F32s((frac16_t)a32ThetaInit); + psCtrl -> fltSpeed = 0.0F; + psCtrl -> fltI_1 = 0.0F; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_TRACK_OBSRV_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/amclib.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/amclib.h new file mode 100644 index 000000000..aabba3c05 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/amclib.h @@ -0,0 +1,81 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Main AMCLIB header file for devices without FPU. +* +*******************************************************************************/ +#ifndef _AMCLIB_H_ +#define _AMCLIB_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "AMCLIB_AngleTrackObsrv_F32.h" +#include "AMCLIB_CtrlFluxWkng_A32.h" +#include "AMCLIB_PMSMBemfObsrvDQ_A32.h" +#include "AMCLIB_PMSMBemfObsrvAB_A32.h" +#include "AMCLIB_TrackObsrv_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define AMCLIB_AngleTrackObsrvInit_F16(f16ThetaInit, psCtrl) \ + AMCLIB_AngleTrackObsrvInit_F16_C(f16ThetaInit, psCtrl) +#define AMCLIB_AngleTrackObsrv_F16(f16ThetaErr, psCtrl) \ + AMCLIB_AngleTrackObsrv_F16_C(f16ThetaErr, psCtrl) +#define AMCLIB_CtrlFluxWkngInit_F16(f16InitVal, psCtrl) \ + AMCLIB_CtrlFluxWkngInit_F16_Ci(f16InitVal, psCtrl) +#define AMCLIB_CtrlFluxWkng_F16(f16IQErr, f16UQReq, f16UQLim, psCtrl) \ + AMCLIB_CtrlFluxWkng_F16_C(f16IQErr, f16UQReq, f16UQLim, psCtrl) +#define AMCLIB_PMSMBemfObsrvDQInit_F16(psCtrl) \ + AMCLIB_PMSMBemfObsrvDQInit_F16_Ci(psCtrl) +#define AMCLIB_PMSMBemfObsrvDQ_F16(psIDQ, psUDQ, f16Speed, psCtrl) \ + AMCLIB_PMSMBemfObsrvDQ_F16_Asm(psIDQ, psUDQ, f16Speed, psCtrl) +#define AMCLIB_PMSMBemfObsrvABInit_F16(psCtrl) \ + AMCLIB_PMSMBemfObsrvABInit_F16_Ci(psCtrl) +#define AMCLIB_PMSMBemfObsrvAB_F16(psIAlBe, psUAlBe, f16Speed, psCtrl) \ + AMCLIB_PMSMBemfObsrvAB_F16_C(psIAlBe, psUAlBe, f16Speed, psCtrl) +#define AMCLIB_TrackObsrvInit_F16(f16ThetaInit, psCtrl) \ + AMCLIB_TrackObsrvInit_F16_Ci(f16ThetaInit, psCtrl) +#define AMCLIB_TrackObsrv_F16(f16ThetaErr, psCtrl) \ + AMCLIB_TrackObsrv_F16_Asm(f16ThetaErr, psCtrl) + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/amclib_FP.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/amclib_FP.h new file mode 100644 index 000000000..270366426 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/amclib_FP.h @@ -0,0 +1,96 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Main AMCLIB header file for devices with FPU. +* +*******************************************************************************/ +#ifndef _AMCLIB_FP_H_ +#define _AMCLIB_FP_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "amclib.h" +#include "AMCLIB_ACIMCtrlMTPA_FLT.h" +#include "AMCLIB_ACIMRotFluxObsrv_FLT.h" +#include "AMCLIB_ACIMSpeedMRAS_FLT.h" +#include "AMCLIB_AngleTrackObsrv_FLT.h" +#include "AMCLIB_CtrlFluxWkng_FLT.h" +#include "AMCLIB_PMSMBemfObsrvAB_FLT.h" +#include "AMCLIB_PMSMBemfObsrvDQ_FLT.h" +#include "AMCLIB_TrackObsrv_FLT.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define AMCLIB_ACIMCtrlMTPAInit_FLT(fltIDMin, fltIDMax, psCtrl) \ + AMCLIB_ACIMCtrlMTPAInit_FLT_Ci(fltIDMin, fltIDMax, psCtrl) +#define AMCLIB_ACIMCtrlMTPA_FLT(fltIq, psCtrl) \ + AMCLIB_ACIMCtrlMTPA_FLT_C(fltIq, psCtrl) +#define AMCLIB_ACIMRotFluxObsrvInit_FLT(psCtrl) \ + AMCLIB_ACIMRotFluxObsrvInit_FLT_Ci(psCtrl) +#define AMCLIB_ACIMRotFluxObsrv_FLT(psIsAlBe, psUSAlBe, psCtrl) \ + AMCLIB_ACIMRotFluxObsrv_FLT_C(psIsAlBe, psUSAlBe, psCtrl ) +#define AMCLIB_ACIMSpeedMRASInit_FLT(psCtrl) \ + AMCLIB_ACIMSpeedMRASInit_FLT_Ci(psCtrl) +#define AMCLIB_ACIMSpeedMRAS_FLT(psIsAlBe, psPsiRAlBe, a32RotPos, psCtrl) \ + AMCLIB_ACIMSpeedMRAS_FLT_C(psIsAlBe, psPsiRAlBe, a32RotPos, psCtrl) +#define AMCLIB_AngleTrackObsrvInit_A32(a32ThetaInit, psCtrl) \ + AMCLIB_AngleTrackObsrvInit_A32_C(a32ThetaInit, psCtrl) +#define AMCLIB_AngleTrackObsrv_A32ff(psSinCos, psCtrl) \ + AMCLIB_AngleTrackObsrv_A32ff_C(psSinCos, psCtrl) +#define AMCLIB_CtrlFluxWkngInit_FLT(fltInitVal, psCtrl) \ + AMCLIB_CtrlFluxWkngInit_FLT_Ci(fltInitVal, psCtrl) +#define AMCLIB_CtrlFluxWkng_FLT(fltIQErr, fltUQReq, fltUQLim, psCtrl) \ + AMCLIB_CtrlFluxWkng_FLT_C(fltIQErr, fltUQReq, fltUQLim, psCtrl) +#define AMCLIB_PMSMBemfObsrvDQInit_A32fff(psCtrl) \ + AMCLIB_PMSMBemfObsrvDQInit_A32fff_C(psCtrl) +#define AMCLIB_PMSMBemfObsrvDQ_A32fff(psIDQ, psUDQ, fltSpeed, psCtrl) \ + AMCLIB_PMSMBemfObsrvDQ_A32fff_C(psIDQ, psUDQ, fltSpeed, psCtrl) +#define AMCLIB_PMSMBemfObsrvABInit_FLT(psCtrl) \ + AMCLIB_PMSMBemfObsrvABInit_FLT_Ci( psCtrl) +#define AMCLIB_PMSMBemfObsrvAB_FLT(psIAlBe, psUAlBe, fltSpeed, psCtrl) \ + AMCLIB_PMSMBemfObsrvAB_FLT_C(psIAlBe, psUAlBe, fltSpeed, psCtrl) +#define AMCLIB_TrackObsrvInit_A32af(a32ThetaInit, psCtrl) \ + AMCLIB_TrackObsrvInit_A32af_Ci(a32ThetaInit, psCtrl) +#define AMCLIB_TrackObsrv_A32af(a32ThetaErr, psCtrl) \ + AMCLIB_TrackObsrv_A32af_C(a32ThetaErr, psCtrl) + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_FP_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/amclib_types.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/amclib_types.h new file mode 100644 index 000000000..b2e85ae4f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/Include/amclib_types.h @@ -0,0 +1,61 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief AMCLIB types +* +*******************************************************************************/ +#ifndef _AMCLIB_TYPES_H_ +#define _AMCLIB_TYPES_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/****************************************************************************** +* Macros +******************************************************************************/ +#define AMCLIB_CONST + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "gmclib_types.h" + +#if defined(__cplusplus) +} +#endif + +#endif /* _AMCLIB_TYPES_H_ */ + + + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/libAMCLIB.a b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/libAMCLIB.a new file mode 100644 index 000000000..40477cdde Binary files /dev/null and b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/AMCLIB/libAMCLIB.a differ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterExp_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterExp_F32.h new file mode 100644 index 000000000..9aec7b7cc --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterExp_F32.h @@ -0,0 +1,129 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Exponential filter +* +*******************************************************************************/ +#ifndef _GDFLIB_FILTEREXP_F32_H_ +#define _GDFLIB_FILTEREXP_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterExpInit_F16_Ci(f16InitVal, psParam) \ + GDFLIB_FilterExpInit_F16_FCi(f16InitVal, psParam) +#define GDFLIB_FilterExp_F16_Ci(f16InX, psParam) \ + GDFLIB_FilterExp_F16_FCi(f16InX, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct{ + frac32_t f32A; /* is a filter constant <0; 1)assigned in form: 1-a */ + frac32_t f32AccK_1; /* filter accumulator value at step k-1 (last filter output)*/ +} GDFLIB_FILTER_EXP_T_F32; + +/***************************************************************************//*! +* @brief The function initializes the actual values of FilterExp_F16. +* +* @param in frac16_t f16InitVal - Initial value +* ptr GDFLIB_FILTER_EXP_T_F32 *psParam - pointer to filter structure +* +*******************************************************************************/ +static inline void GDFLIB_FilterExpInit_F16_FCi(frac16_t f16InitVal, + GDFLIB_FILTER_EXP_T_F32 *psParam) +{ + psParam->f32AccK_1 = MLIB_Conv_F32s(f16InitVal); +} + +/***************************************************************************//*! +* +* @brief The function calculates exponential filter +* +* @param ptr GDFLIB_FILTER_EXP_T_F32 * psParam +* - Pointer to filter structure +* +* GDFLIB_FILTER_EXP_T_F32 structure: +* - f32A - filter constant assign in form 1-a +* (where a is exp. filter constant) +* - f32AccK_1 - filter output value at step k-1 +* +* @param in f16InX - input signal +* +* @return This function returns - frac16_t value +* +* @remarks +* +* Filter Equation: +* +* Filter Equation: +* +* y(k) = y(k-1) + A * (x(k) - y(k-1)) +* +* where +* x(k) is the filter input at time step k +* y(k) is the filtered output at time step k +* A is the filter constant assign as 1-a from range (0; 1) (where a is exp. filter constant - smoothing constant). +* +****************************************************************************/ +static inline frac16_t GDFLIB_FilterExp_F16_FCi(frac16_t f16InX, + GDFLIB_FILTER_EXP_T_F32 *psParam) +{ + register frac32_t f32Temp; + register frac32_t f32AccK_1; + + /* Store frequently read quantities to register */ + f32AccK_1 = psParam->f32AccK_1; + + /* Filter calculations */ + f32Temp = MLIB_Conv_F32s(f16InX); + f32Temp = MLIB_SubSat_F32_FAsmi(f32Temp, f32AccK_1); /* calculation x(k) - y(k-1) */ + f32Temp = MLIB_MacRndSat_F32(f32AccK_1, psParam->f32A, f32Temp); /* y(k-1) + A * (x(k) - y(k-1)) */ + psParam->f32AccK_1 = f32Temp; /* store filter state value */ + + return(MLIB_RndSat_F16l(f32Temp)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FILTEREXP_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterExp_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterExp_FLT.h new file mode 100644 index 000000000..cd14ac13f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterExp_FLT.h @@ -0,0 +1,127 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Exponential filter +* +*******************************************************************************/ +#ifndef _GDFLIB_FILTEREXP_FLT_H_ +#define _GDFLIB_FILTEREXP_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gdflib_types.h" +#include "mlib_FP.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterExpInit_FLT_Ci(fltInitVal, psParam) \ + GDFLIB_FilterExpInit_FLT_FCi(fltInitVal, psParam) +#define GDFLIB_FilterExp_FLT_Ci(fltInX, psParam) \ + GDFLIB_FilterExp_FLT_FCi(fltInX, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct{ + float_t fltA; /* is a filter constant <0; 1> assigned in form: 1-a */ + float_t fltAccK_1; /* filter input value at step k-1 (last filter output)*/ +}GDFLIB_FILTER_EXP_T_FLT; + +/***************************************************************************//*! +* @brief The function initializes the actual values of FilterExp_FLT. +* +* @param in float_t fltInitVal - Initial value +* ptr GDFLIB_FILTER_EXP_T_FLT *psParam - pointer to filter structure +* +*******************************************************************************/ +static inline void GDFLIB_FilterExpInit_FLT_FCi(float_t fltInitVal, + GDFLIB_FILTER_EXP_T_FLT *psParam) +{ + psParam->fltAccK_1 = fltInitVal; +} + +/***************************************************************************//*! +* +* @brief The function calculates exponential filter +* +* @param ptr GDFLIB_FILTER_EXP_T_FLT * psParam +* - Pointer to filter structure +* +* GDFLIB_FILTER_EXP_T_FLT structure: +* - fltA - filter constant assign in form 1-a +* (where a is exp. filter constant) +* - fltAccK_1 - filter output value at step k-1 +* +* @param in fltInX - input signal +* +* @return This function returns - float_t value +* +* @remarks +* +* Filter Equation: +* +* y(k) = y(k-1) + A * (x(k) - y(k-1)) +* +* where +* x(k) is the filter input at time step k +* y(k) is the filtered output at time step k +* A is the filter constant assign as 1-a from range <0; 1) (where a is exp. filter constant - smoothing constant). +* +****************************************************************************/ +static inline float_t GDFLIB_FilterExp_FLT_FCi(float_t fltInX, + GDFLIB_FILTER_EXP_T_FLT *psParam) +{ + register float_t fltTemp; + register float_t fltAccK_1; + + /* Store frequently read quantities to register */ + fltAccK_1 = psParam->fltAccK_1; + + /* Filter calculations */ + fltTemp = MLIB_Sub_FLT(fltInX, fltAccK_1); /* calculation x(k) - y(k-1) */ + fltTemp = MLIB_Mac_FLT(fltAccK_1, psParam->fltA, fltTemp); /* y(k-1) + A * (x(k) - y(k-1)) */ + psParam->fltAccK_1 = fltTemp ; /* store filter state value */ + + return(fltTemp); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FILTEREXP_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR1_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR1_F32.h new file mode 100644 index 000000000..d206e3b2b --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR1_F32.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Digital IIR Filter, 1st order +* +*******************************************************************************/ +#ifndef _GDFLIB_FILTERIIR1_F32_H_ +#define _GDFLIB_FILTERIIR1_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gdflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterIIR1Init_F16_Ci(psParam) \ + GDFLIB_FilterIIR1Init_F16_FCi(psParam) +#define GDFLIB_FilterIIR1_F16_C(f16InX, psParam) \ + GDFLIB_FilterIIR1_F16_FC(f16InX, psParam) +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac32_t f32B0; /* B0 coefficient of an IIR1 filter */ + frac32_t f32B1; /* B1 coefficient of an IIR1 filter */ + frac32_t f32A1; /* A1 coefficient of an IIR1 filter */ +} GDFLIB_FILTER_IIR1_COEFF_T_F32; + +typedef struct +{ + GDFLIB_FILTER_IIR1_COEFF_T_F32 sFltCoeff; /* Sub-structure containing filter coefficients. */ + frac32_t f32FltBfrY[1]; /* Internal accumulator buffer */ + frac16_t f16FltBfrX[1]; /* Input buffer of an IIR1 filter */ +} GDFLIB_FILTER_IIR1_T_F32; + +/***************************************************************************//*! +* +* @brief The function clears buffer of 2nd order IIR filter pointed to by argument +* +* @param ptr GDFLIB_FILTER_IIR1_T_F16 *psParam - Pointer to filter structure +* +* @return N/A +* +*******************************************************************************/ + static inline void GDFLIB_FilterIIR1Init_F16_FCi(GDFLIB_FILTER_IIR1_T_F32 *psParam) + { + psParam->f32FltBfrY[0] = (frac32_t)0; + psParam->f16FltBfrX[0] = (frac16_t)0; + } + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FILTERIIR1_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR1_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR1_F32_Asmi.h new file mode 100644 index 000000000..e98a3d217 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR1_F32_Asmi.h @@ -0,0 +1,183 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Digital IIR Filter, 1st order +* +*******************************************************************************/ +#ifndef _GDFLIB_FILTERIIR1_F32_ASMI_H_ +#define _GDFLIB_FILTERIIR1_F32_ASMI_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gdflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterIIR1_F16_Asmi(f16InX, psParam) \ + GDFLIB_FilterIIR1_F16_FAsmi(f16InX, psParam) + +/***************************************************************************//*! +* +* @brief 16-bit input and output 1st order IIR filter +* +* @param ptr GDFLIB_FILTER_IIR1_T_F32 *psParam +* - pointer to the structure of the filter +* +* GDFLIB_FILTER_IIR1_T_F32 data structure: +* GDFLIB_FILTER_IIR1_COEFF_T_F32 sFltCoeff +* - filter coefficients in frac32_t divided by 2 +* in the following range +* -1.0 <= coef < 1.0 +* - B coefficients: +* frac32_t f32B0 +* frac32_t f32B1 +* -A coefficient, the sign is negated +* frac32_t f32A1; +* frac32_t f32FltBfrY[1]; +* - y history buffer in frac32_t +* frac16_t f16FltBfrX[1]; +* - x history buffer in frac16_t +* @param in frac16_t f16InX +* - Input signal at the step K step +* fractional value in the range <-1;1) +* +* @return This function filtered value +* - frac16_t value <-1;1) +* +* ----------- +* x(k) | | y(k) +* --------| IIR1 |--------- +* | | +* ----------- +* +* x(k) - input signal +* y(k) - filtered output signal +* +* Filter equation: +* y(n) = b0*x(n) + b1*x(n-1) - a1*y(n-1) +* +* All coefficients must be divided by 2, i.e. if the desired b1 coefficient +* is 1.756 the value is then: b1 = FRAC32(1.786 / 2.0); +* +* All A coefficients must be negated, i.e. if the desired a2 coefficient +* is 1.789, the value is then: a2 = FRAC32(-1.789 / 2.0); +* +*******************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_suppress=Pe549 /* Suppresses the Pe549 warning for IAR compiler*/ +#endif +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t GDFLIB_FilterIIR1_F16_FAsmi(frac16_t f16InX, + GDFLIB_FILTER_IIR1_T_F32 *psParam) +{ + register frac32_t f32Val1=0, f32Val2=0, f32Val3=0, f32Val4=0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16InX, f16InX /* Converts 16-bit input into 32-bit value */ + ldr f32Val1, [psParam, #0] /* f32Val1= b0 */ + ldr f32Val2, [psParam, #4] /* f32Val2= b1 */ + ldr f32Val3, [psParam, #8] /* f32Val3= a1 */ + ldrsh f32Val4, [psParam, #16] /* f32Val4 = x(n-1) */ + strh f16InX, [psParam, #16] /* Saves x(n) for next step */ + smull f32Val4, f32Val2, f32Val4, f32Val2 /* f32Val2:f32Val4 = b1*x(n-1) */ + smlal f32Val4, f32Val2, f32Val1, f16InX /* f32Val2:f32Val4 = b0*x(n) + b1*x(n-1) */ + ldr f16InX, [psParam, #12] /* f16InX = y(n-1) */ + smull f32Val3, f32Val1, f32Val3, f16InX /* f32Val1:f32Val3 = - a1*y(n-1) */ + lsr f32Val3, f32Val3, #16 /* f32Val3 >> 16 */ + add f32Val3, f32Val3, f32Val1, lsl #16 /* f32Val3 = f32Val3 + f32Val1 << 16 */ + adds f32Val4, f32Val4, f32Val3 /* f32Val4 = f32Val4 + f32Val3 */ + adc f32Val2, f32Val2, f32Val1, asr #16 /* f32Val2:f32Val4 = b0*x(n) + b1*x(n-1) - a1*y(n-1) */ + lsr f16InX, f32Val4, #14 /* f16InX = f32Val4 >> 14 */ + add f16InX, f16InX, f32Val2, lsl #18 /* f16InX = f16InX + f32Val2 << 18 */ + asr f32Val2, f32Val2, #13 /* f32Val2 >> 13 */ + cmp f32Val2, f16InX, asr #31 /* Compares f32Val2 with (f16InX >> 31)*/ + ittt ne /* If f32Val2 != (f16InX >> 18), then saturates output */ + ssatne f16InX, #1, f32Val2 /* Saturates f32Val2 as an 1 bit value */ + addne f16InX, f16InX, #1 /* f16InX + 1 */ + rsbne f16InX, f16InX, #0x80000000 /* f16InX = 0x80000000 - f16InX */ + str f16InX, [psParam, #12] /* Saves y(n) for next step */ + asrs f16InX, f16InX, #16 }; /* f16InX >> 16 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Converts 16-bit input into 32-bit value */ + "ldr %1, [%5, #0]\n" /* f32Val1= b0 */ + "ldr %2, [%5, #4]\n" /* f32Val2= b1 */ + "ldr %3, [%5, #8]\n" /* f32Val3= a1 */ + "ldrsh %4, [%5, #16] \n" /* f32Val4 = x(n-1) */ + "strh %0, [%5, #16] \n" /* Saves x(n) for next step */ + "smull %4, %2, %4, %2 \n" /* f32Val2:f32Val4 = b1*x(n-1) */ + "smlal %4, %2, %1, %0 \n" /* f32Val2:f32Val4 = b0*x(n) + b1*x(n-1) */ + "ldr %0, [%5, #12] \n" /* f16InX = y(n-1) */ + "smull %3, %1, %3, %0 \n" /* f32Val1:f32Val3 = - a1*y(n-1) */ + "lsr %3, %3, #16 \n" /* f32Val3 >> 16 */ + "add %3, %3, %1, lsl #16 \n" /* f32Val3 = f32Val3 + f32Val1 << 16 */ + "adds %4, %4, %3 \n" /* f32Val4 = f32Val4 + f32Val3 */ + "adc %2, %2, %1, asr #16 \n" /* f32Val2:f32Val4 = b0*x(n) + b1*x(n-1) - a1*y(n-1) */ + "lsr %0, %4, #14 \n" /* f16InX = f32Val4 >> 14 */ + "add %0, %0, %2, lsl #18 \n" /* f16InX = f16InX + f32Val2 << 18 */ + "asr %2, %2, #13 \n" /* f32Val2 >> 13 */ + "cmp %2, %0, asr #31 \n" /* Compares f32Val2 with (f16InX >> 31)*/ + "ittt ne \n" /* If f32Val2 != (f16InX >> 18), then saturates output */ + "ssatne %0, #1, %2 \n" /* Saturates f32Val2 as an 1 bit value */ + "addne %0, %0, #1 \n" /* f16InX + 1 */ + "rsbne %0, %0, #0x80000000 \n" /* f16InX = 0x80000000 - f16InX */ + "str %0, [%5, #12] \n" /* Saves y(n) for next step */ + "asrs %0, %0, #16 \n" /* f16InX >> 16 */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16InX), "+l"(f32Val1), "+l"(f32Val2), "+l"(f32Val3), "+l"(f32Val4): "l"(psParam)); + #endif + + return(f16InX); +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_default=Pe549 +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FILTERIIR1_F32_ASMI_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR1_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR1_FLT.h new file mode 100644 index 000000000..16275aea5 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR1_FLT.h @@ -0,0 +1,170 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Digital Float IIR Filter, 1st order +* +*******************************************************************************/ +#ifndef _GDFLIB_FILTERIIR1_FLT_H_ +#define _GDFLIB_FILTERIIR1_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gdflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterIIR1Init_FLT_Ci(psParam) \ + GDFLIB_FilterIIR1Init_FLT_FCi(psParam) +#define GDFLIB_FilterIIR1_FLT_Ci(fltInX, psParam) \ + GDFLIB_FilterIIR1_FLT_FCi(fltInX, psParam) +#define GDFLIB_FilterIIR1_FLT_C(fltInX, psParam) \ + GDFLIB_FilterIIR1_FLT_FC(fltInX, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltB0; /* B0 coefficient of an IIR1 filter */ + float_t fltB1; /* B1 coefficient of an IIR1 filter */ + float_t fltA1; /* A1 coefficient of an IIR1 filter */ +} GDFLIB_FILTER_IIR1_COEFF_T_FLT; + +typedef struct +{ + GDFLIB_FILTER_IIR1_COEFF_T_FLT sFltCoeff; /* Sub-structure containing filter coeff. */ + float_t fltFltBfrY[1]; /* Internal accumulator buffer */ + float_t fltFltBfrX[1]; /* Input buffer of an IIR1 filter */ +} GDFLIB_FILTER_IIR1_T_FLT; + +/***************************************************************************//*! +* +* @brief The function clears buffer of 2nd order float IIR filter pointed to by argument +* +* @param ptr GDFLIB_FILTER_IIR1_T_FLT *p- Pointer to filter structure +* +* @return N/A +* +****************************************************************************/ +static inline void GDFLIB_FilterIIR1Init_FLT_FCi(GDFLIB_FILTER_IIR1_T_FLT *psParam) +{ + psParam->fltFltBfrY[0] = (float_t)0.0F; + psParam->fltFltBfrX[0] = (float_t)0.0F; +} + +/***************************************************************************//*! +* +* @brief The function clears the buffer of 2nd order float IIR filter +* +* @param ptr GDFLIB_FILTER_IIR1_T_FLT *psParam +* - pointer to the structure of the filter +* +* GDFLIB_FILTER_IIR1_T_FLT data structure: +* GDFLIB_FILTER_IIR1_COEFF_T_FLT sFltCoeff +* - filter coefficients in float_t as real value +* - B coefficients: +* float_t fltB0 +* float_t fltB1 +* - A coefficient, the sign is negated +* float_t fltA1 +* float_t fltFltBfrY[1] - y history buffer in float_t +* float_t fltFltBfrX[1] - x history buffer in float_t +* @param in float_t fltInX - Input signal at the step K step +* +* @return This function filtered value - float_t value +* +* @remarks Filter algorithm: +* +* ----------- +* x(k) | | y(k) +* --------| IIR1 |--------- +* | | +* ----------- +* +* x(k) - input signal +* y(k) - filtered output signal +* +* Filter equation: +* y(n) = b0*x(n) + b1*x(n-1) - a1*y(n-1) +* +* All B coefficients are not scaled, i.e. if the desired b1 coefficient +* is 1.756 the value is then: b1 = 1.786F ; +* +* All A coefficients must be negated but are not scaled, i.e. if the desired a2 coefficient +* is 1.789, the value is then: a2 = -1.789F ; +* +*******************************************************************************/ +static inline float_t GDFLIB_FilterIIR1_FLT_FCi(float_t fltInX, + GDFLIB_FILTER_IIR1_T_FLT *psParam) +{ + register float_t fltAcc; + + /* + * Implemented equation assuming real (not devided) filter coeficients: + * y(k) = b0*x(k) + b1*x(k-1) + a1*y(k-1) + * + * Calculation steps: + * Acc = b0 * x(k) + * Acc = Acc + b1 * x(k-1) + * Acc = Acc + a1 * y(k-1) + * y(k)= Acc + */ + + /* Acc = b0 * x(k) */ + fltAcc = MLIB_Mul_FLT ( psParam->sFltCoeff.fltB0, fltInX); + + /* Acc = Acc + b1 * x(k-1) */ + fltAcc = MLIB_Mac_FLT (fltAcc, psParam->sFltCoeff.fltB1, psParam->fltFltBfrX[0]); + + /* Acc = Acc + a1 * y(k-1) */ + fltAcc = MLIB_Mac_FLT (fltAcc, psParam->sFltCoeff.fltA1, psParam->fltFltBfrY[0]); + + /* Storing filter states in the buffers */ + psParam->fltFltBfrX[0] = fltInX; + psParam->fltFltBfrY[0] = fltAcc; + + /* Returning float value of internal accumulator */ + return(fltAcc); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FILTERIIR1_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR2_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR2_F32.h new file mode 100644 index 000000000..89fddcade --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR2_F32.h @@ -0,0 +1,87 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Digital IIR Filter, 2nd order +* +*******************************************************************************/ +#ifndef _GDFLIB_FILTERIIR2_F32_H_ +#define _GDFLIB_FILTERIIR2_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gdflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterIIR2Init_F16_C(psParam) \ + GDFLIB_FilterIIR2Init_F16_FC(psParam) +#define GDFLIB_FilterIIR2_F16_Asm(f16InX, psParam) \ + GDFLIB_FilterIIR2_F16_FAsm(f16InX, psParam) +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac32_t f32B0; /* B0 coefficient of an IIR2 filter */ + frac32_t f32B1; /* B1 coefficient of an IIR2 filter */ + frac32_t f32B2; /* B2 coefficient of an IIR2 filter */ + frac32_t f32A1; /* A1 coefficient of an IIR2 filter */ + frac32_t f32A2; /* A2 coefficient of an IIR2 filter */ +} GDFLIB_FILTER_IIR2_COEFF_T_F32; + +typedef struct +{ + GDFLIB_FILTER_IIR2_COEFF_T_F32 sFltCoeff; /* Sub-structure containing filter coefficients. */ + frac32_t f32FltBfrY[2]; /* Internal accumulator buffer */ + frac16_t f16FltBfrX[2]; /* Input buffer of an IIR2 filter */ +} GDFLIB_FILTER_IIR2_T_F32; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +void GDFLIB_FilterIIR2Init_F16_FC(GDFLIB_FILTER_IIR2_T_F32 *psParam); + +frac16_t GDFLIB_FilterIIR2_F16_FAsm(frac16_t f16InX, + GDFLIB_FILTER_IIR2_T_F32 *psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FILTERIIR2_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR2_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR2_FLT.h new file mode 100644 index 000000000..9226e802e --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR2_FLT.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Digital Float IIR Filter, 2nd order +* +*******************************************************************************/ +#ifndef _GDFLIB_FILTERIIR2_FLT_H_ +#define _GDFLIB_FILTERIIR2_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gdflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterIIR2Init_FLT_C(psParam) \ + GDFLIB_FilterIIR2Init_FLT_FC(psParam) +#define GDFLIB_FilterIIR2_FLT_Ci(fltInX, psParam) \ + GDFLIB_FilterIIR2_FLT_FCi(fltInX, psParam) +#define GDFLIB_FilterIIR2_FLT_C(fltInX, psParam) \ + GDFLIB_FilterIIR2_FLT_FC(fltInX, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltB0; /* B0 coefficient of an IIR2 filter */ + float_t fltB1; /* B1 coefficient of an IIR2 filter */ + float_t fltB2; /* B2 coefficient of an IIR2 filter */ + float_t fltA1; /* A1 coefficient of an IIR2 filter */ + float_t fltA2; /* A2 coefficient of an IIR2 filter */ +} GDFLIB_FILTER_IIR2_COEFF_T_FLT; + +typedef struct +{ + GDFLIB_FILTER_IIR2_COEFF_T_FLT sFltCoeff; /* Sub-structure containing filter coefficients. */ + float_t fltFltBfrY[2]; /* Internal accumulator buffer */ + float_t fltFltBfrX[2]; /* Input buffer of an IIR2 filter */ +} GDFLIB_FILTER_IIR2_T_FLT; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +void GDFLIB_FilterIIR2Init_FLT_FC(GDFLIB_FILTER_IIR2_T_FLT *psParam); +float_t GDFLIB_FilterIIR2_FLT_FC(float_t fltInX, + GDFLIB_FILTER_IIR2_T_FLT *psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FILTERIIR2_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR3_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR3_F32.h new file mode 100644 index 000000000..8176830e9 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR3_F32.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Digital IIR Filter, 3rd order +* +*******************************************************************************/ +#ifndef _GDFLIB_FILTERIIR3_F32_H_ +#define _GDFLIB_FILTERIIR3_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gdflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterIIR3Init_F16_C(psParam) \ + GDFLIB_FilterIIR3Init_F16_FC(psParam) +#define GDFLIB_FilterIIR3_F16_C(f16InX, psParam) \ + GDFLIB_FilterIIR3_F16_FC(f16InX, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac32_t f32B0; /* B0 coefficient of an IIR3 filter */ + frac32_t f32B1; /* B1 coefficient of an IIR3 filter */ + frac32_t f32B2; /* B2 coefficient of an IIR3 filter */ + frac32_t f32B3; /* B3 coefficient of an IIR3 filter */ + frac32_t f32A1; /* A1 coefficient of an IIR3 filter */ + frac32_t f32A2; /* A2 coefficient of an IIR3 filter */ + frac32_t f32A3; /* A3 coefficient of an IIR3 filter */ +} GDFLIB_FILTER_IIR3_COEFF_T_F32; + +typedef struct +{ + GDFLIB_FILTER_IIR3_COEFF_T_F32 sFltCoeff; /* Sub-structure containing filter coefficients. */ + frac32_t f32FltBfrY[3]; /* Internal accumulator buffer */ + frac16_t f16FltBfrX[3]; /* Input buffer of an IIR3 filter */ +} GDFLIB_FILTER_IIR3_T_F32; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +void GDFLIB_FilterIIR3Init_F16_FC(GDFLIB_FILTER_IIR3_T_F32 *psParam); +frac16_t GDFLIB_FilterIIR3_F16_FC(frac16_t f16InX, + GDFLIB_FILTER_IIR3_T_F32 *psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FILTERIIR3_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR3_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR3_FLT.h new file mode 100644 index 000000000..599d500e2 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR3_FLT.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Digital Float IIR Filter, 3rd order +* +*******************************************************************************/ +#ifndef _GDFLIB_FILTERIIR3_FLT_H_ +#define _GDFLIB_FILTERIIR3_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gdflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterIIR3Init_FLT_C(psParam) \ + GDFLIB_FilterIIR3Init_FLT_FC(psParam) +#define GDFLIB_FilterIIR3_FLT_C(fltInX, psParam) \ + GDFLIB_FilterIIR3_FLT_FC(fltInX, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltB0; /* B0 coefficient of an IIR3 filter */ + float_t fltB1; /* B1 coefficient of an IIR3 filter */ + float_t fltB2; /* B2 coefficient of an IIR3 filter */ + float_t fltB3; /* B3 coefficient of an IIR3 filter */ + float_t fltA1; /* A1 coefficient of an IIR3 filter */ + float_t fltA2; /* A2 coefficient of an IIR3 filter */ + float_t fltA3; /* A3 coefficient of an IIR3 filter */ +} GDFLIB_FILTER_IIR3_COEFF_T_FLT; + +typedef struct +{ + GDFLIB_FILTER_IIR3_COEFF_T_FLT sFltCoeff; /* Sub-structure containing filter coefficients. */ + float_t fltFltBfrY[3]; /* Internal accumulator buffer */ + float_t fltFltBfrX[3]; /* Input buffer of an IIR3 filter */ +} GDFLIB_FILTER_IIR3_T_FLT; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +void GDFLIB_FilterIIR3Init_FLT_FC(GDFLIB_FILTER_IIR3_T_FLT *psParam); +float_t GDFLIB_FilterIIR3_FLT_FC(float_t fltInX, + GDFLIB_FILTER_IIR3_T_FLT *psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FILTERIIR3_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR4_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR4_F32.h new file mode 100644 index 000000000..5329fb48e --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR4_F32.h @@ -0,0 +1,90 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Digital IIR Filter, 4th order +* +*******************************************************************************/ +#ifndef _GDFLIB_FILTERIIR4_F32_H_ +#define _GDFLIB_FILTERIIR4_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gdflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterIIR4Init_F16_C(psParam) \ + GDFLIB_FilterIIR4Init_F16_FC(psParam) +#define GDFLIB_FilterIIR4_F16_C(f16InX, psParam) \ + GDFLIB_FilterIIR4_F16_FC(f16InX, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac32_t f32B0; /* B0 coefficient of an IIR4 filter */ + frac32_t f32B1; /* B1 coefficient of an IIR4 filter */ + frac32_t f32B2; /* B2 coefficient of an IIR4 filter */ + frac32_t f32B3; /* B3 coefficient of an IIR4 filter */ + frac32_t f32B4; /* B4 coefficient of an IIR4 filter */ + frac32_t f32A1; /* A1 coefficient of an IIR4 filter */ + frac32_t f32A2; /* A2 coefficient of an IIR4 filter */ + frac32_t f32A3; /* A3 coefficient of an IIR4 filter */ + frac32_t f32A4; /* A4 coefficient of an IIR4 filter */ +} GDFLIB_FILTER_IIR4_COEFF_T_F32; + +typedef struct{ + GDFLIB_FILTER_IIR4_COEFF_T_F32 sFltCoeff; /* Sub-structure containing filter coefficients. */ + frac32_t f32FltBfrY[4]; /* Internal accumulator buffer */ + frac16_t f16FltBfrX[4]; /* Input buffer of an IIR4 filter */ +} GDFLIB_FILTER_IIR4_T_F32; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +void GDFLIB_FilterIIR4Init_F16_FC(GDFLIB_FILTER_IIR4_T_F32 *psParam); +frac16_t GDFLIB_FilterIIR4_F16_FC(frac16_t f16InX, + GDFLIB_FILTER_IIR4_T_F32 *psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FILTERIIR4_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR4_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR4_FLT.h new file mode 100644 index 000000000..e9a1d210e --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterIIR4_FLT.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Digital Float IIR Filter, 4th order +* +*******************************************************************************/ +#ifndef _GDFLIB_FILTERIIR4_FLT_H_ +#define _GDFLIB_FILTERIIR4_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gdflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterIIR4Init_FLT_C(psParam) \ + GDFLIB_FilterIIR4Init_FLT_FC(psParam) +#define GDFLIB_FilterIIR4_FLT_C(fltInX, psParam) \ + GDFLIB_FilterIIR4_FLT_FC(fltInX, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct{ + float_t fltB0; /* B0 coefficient of an IIR4 filter */ + float_t fltB1; /* B1 coefficient of an IIR4 filter */ + float_t fltB2; /* B2 coefficient of an IIR4 filter */ + float_t fltB3; /* B3 coefficient of an IIR4 filter */ + float_t fltB4; /* B4 coefficient of an IIR4 filter */ + float_t fltA1; /* A1 coefficient of an IIR4 filter */ + float_t fltA2; /* A2 coefficient of an IIR4 filter */ + float_t fltA3; /* A3 coefficient of an IIR4 filter */ + float_t fltA4; /* A4 coefficient of an IIR4 filter */ +} GDFLIB_FILTER_IIR4_COEFF_T_FLT; + +typedef struct{ + GDFLIB_FILTER_IIR4_COEFF_T_FLT sFltCoeff; /* Sub-structure containing filter coefficients. */ + float_t fltFltBfrY[4]; /* Internal accumulator buffer */ + float_t fltFltBfrX[4]; /* Input buffer of an IIR4 filter */ +} GDFLIB_FILTER_IIR4_T_FLT; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +void GDFLIB_FilterIIR4Init_FLT_FC(GDFLIB_FILTER_IIR4_T_FLT *psParam); +float_t GDFLIB_FilterIIR4_FLT_FC(float_t fltInX, + GDFLIB_FILTER_IIR4_T_FLT *psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FILTERIIR4_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterMA_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterMA_A32.h new file mode 100644 index 000000000..b181440f0 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterMA_A32.h @@ -0,0 +1,123 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Moving average filter +* +*******************************************************************************/ +#ifndef _GDFLIB_FILTERMA_A32_H_ +#define _GDFLIB_FILTERMA_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gdflib_types.h" +#include "mlib.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterMAInit_F16_Ci(f16InitVal, psParam) \ + GDFLIB_FilterMAInit_F16_FCi(f16InitVal, psParam) +#define GDFLIB_FilterMA_F16_Ci(f16InX, psParam) \ + GDFLIB_FilterMA_F16_FCi(f16InX, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct{ + acc32_t a32Acc; /* Filter accumulator. */ + uint16_t u16Sh; /* Number of samples for averaging, filter sample window [0,15].*/ +}GDFLIB_FILTER_MA_T_A32; + + +/***************************************************************************//*! +* @brief The function initializes the actual values of FilterMA_F16. +* +* @param in frac16_t f16InitVal - Initial value +* ptr GDFLIB_FILTER_MA_T_A32 *psParam - pointer to filter structure +* +*******************************************************************************/ +static inline void GDFLIB_FilterMAInit_F16_FCi(frac16_t f16InitVal, + GDFLIB_FILTER_MA_T_A32 *psParam) +{ + psParam->a32Acc = (acc32_t)MLIB_ShLSat_F32(f16InitVal, psParam->u16Sh) - (acc32_t)f16InitVal; +} + +/***************************************************************************//*! +* +* @brief The function calculates recursive form of moving average filter +* +* @param ptr GDFLIB_FILTER_MA_T_A32 * psParam +* - Pointer to filter structure +* +* GDFLIB_FILTER_MA_T_A32 structure: +* - a32Acc - accumulator of the filter +* - u16Sh - 2 ^ u16Sh is the number of values +* +* @param in f16InX - input signal +* +* @return This function returns - frac16_t value +* +* @remarks +* +* Filter Equation: +* +* sum(k) = sum(k-1) + input +* out(k) = sum(k)/N +* sum(k-1) = sum(k) - out(k) +* +****************************************************************************/ +static inline frac16_t GDFLIB_FilterMA_F16_FCi(frac16_t f16InX, + GDFLIB_FILTER_MA_T_A32 *psParam) +{ + register acc32_t a32Temp; + register acc32_t a32Acc; + + /* Input scaled such as to avoid saturation of the algorithm */ + a32Acc = MLIB_AddSat_F32(psParam->a32Acc, (frac32_t)f16InX); + a32Temp = MLIB_ShR_F32(a32Acc,psParam->u16Sh); + a32Acc = MLIB_SubSat_F32(a32Acc, a32Temp); + + /* Store new accumulator state */ + psParam->a32Acc = a32Acc; + return((frac16_t)MLIB_Sat_F16a(a32Temp)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FILTERMA_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterMA_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterMA_FLT.h new file mode 100644 index 000000000..90e21eecc --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/GDFLIB_FilterMA_FLT.h @@ -0,0 +1,126 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Moving average filter +* +*******************************************************************************/ +#ifndef _GDFLIB_FILTERMA_FLT_H_ +#define _GDFLIB_FILTERMA_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gdflib_types.h" +#include "mlib.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterMAInit_FLT_Ci(fltInitVal, psParam) \ + GDFLIB_FilterMAInit_FLT_FCi(fltInitVal, psParam) +#define GDFLIB_FilterMA_FLT_Ci(fltInX, psParam) \ + GDFLIB_FilterMA_FLT_FCi(fltInX, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct{ + float_t fltAcc; /* Float filter accumulator. */ + float_t fltLambda; /* Float value of averaging, if defines filter window size.*/ +}GDFLIB_FILTER_MA_T_FLT; + + +/***************************************************************************//*! +* @brief The function initializes the actual values of FilterMA_FLT. +* +* @param in float_t fltInitVal - Initial value +* ptr GDFLIB_FILTER_MA_T_FLT *psParam - pointer to filter structure +* +*******************************************************************************/ +static inline void GDFLIB_FilterMAInit_FLT_FCi(float_t fltInitVal, + GDFLIB_FILTER_MA_T_FLT *psParam) +{ + psParam->fltAcc = (float_t)fltInitVal; +} + +/***************************************************************************//*! +* +* @brief The function calculates recursive form of moving average filter +* +* @param ptr GDFLIB_FILTER_MA_T_FLT * psParam +* - Pointer to filter structure +* +* GDFLIB_FILTER_MA_T_FLT structure: +* - fltAcc - accumulator of the filter +* - fltLambda - float value of averaging, if defines filter window size. +* +* @param in fltx - input signal +* +* @return This function returns - float_t value +* +* @remarks +* +* Function does not divide sum(k) by 2^n but multiply sum(k) by float number Coef, +* which is not determined by power of 2. For example if filter window size 4 is +* required filter coef must be set to 0.25F value. +* +* Filter Equation: +* +* sum(k) = sum(k-1) + input +* out(k) = sum(k) * Coef +* sum(k-1) = sum(k) - out(k) +* +****************************************************************************/ +static inline float_t GDFLIB_FilterMA_FLT_FCi(float_t fltInX, + GDFLIB_FILTER_MA_T_FLT *psParam) +{ + register float fltTemp; + register float fltAcc; + + fltAcc = MLIB_Add_FLT (psParam->fltAcc, fltInX); + fltTemp = MLIB_Mul_FLT (fltAcc, psParam->fltLambda); + fltAcc = MLIB_Sub_FLT (fltAcc, fltTemp); + + /* Store new accumulator state */ + psParam->fltAcc = fltAcc; + return(fltTemp); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FILTERMA_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/gdflib.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/gdflib.h new file mode 100644 index 000000000..0e617cc00 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/gdflib.h @@ -0,0 +1,85 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************//*! +* +* @brief Main GDFLIB header file for devices without FPU. +* +*******************************************************************************/ +#ifndef _GDFLIB_H_ +#define _GDFLIB_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "GDFLIB_FilterExp_F32.h" +#include "GDFLIB_FilterIIR1_F32.h" +#include "GDFLIB_FilterIIR1_F32_Asmi.h" +#include "GDFLIB_FilterIIR2_F32.h" +#include "GDFLIB_FilterIIR3_F32.h" +#include "GDFLIB_FilterIIR4_F32.h" +#include "GDFLIB_FilterMA_A32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterExpInit_F16(f16InX, psParam) \ + GDFLIB_FilterExpInit_F16_Ci(f16InX, psParam) +#define GDFLIB_FilterExp_F16(f16InX, psParam) \ + GDFLIB_FilterExp_F16_Ci(f16InX, psParam) +#define GDFLIB_FilterIIR1Init_F16(psParam) \ + GDFLIB_FilterIIR1Init_F16_Ci(psParam) +#define GDFLIB_FilterIIR1_F16(f16InX, psParam) \ + GDFLIB_FilterIIR1_F16_Asmi(f16InX, psParam) +#define GDFLIB_FilterIIR2Init_F16(psParam) \ + GDFLIB_FilterIIR2Init_F16_C(psParam) +#define GDFLIB_FilterIIR2_F16(f16InX, psParam) \ + GDFLIB_FilterIIR2_F16_Asm(f16InX, psParam) +#define GDFLIB_FilterIIR3Init_F16(psParam) \ + GDFLIB_FilterIIR3Init_F16_C(psParam) +#define GDFLIB_FilterIIR3_F16(f16InX, psParam) \ + GDFLIB_FilterIIR3_F16_C(f16InX, psParam) +#define GDFLIB_FilterIIR4Init_F16(psParam) \ + GDFLIB_FilterIIR4Init_F16_C(psParam) +#define GDFLIB_FilterIIR4_F16(f16InX, psParam) \ + GDFLIB_FilterIIR4_F16_C(f16InX, psParam) +#define GDFLIB_FilterMAInit_F16(f16InitVal, psParam) \ + GDFLIB_FilterMAInit_F16_Ci(f16InitVal, psParam) +#define GDFLIB_FilterMA_F16(f16InX, psParam) \ + GDFLIB_FilterMA_F16_Ci(f16InX, psParam) + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/gdflib_FP.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/gdflib_FP.h new file mode 100644 index 000000000..fe0b028b0 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/gdflib_FP.h @@ -0,0 +1,85 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************//*! +* +* @brief Main GDFLIB header file for devices with FPU. +* +*******************************************************************************/ +#ifndef _GDFLIB_FP_H_ +#define _GDFLIB_FP_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gdflib.h" +#include "GDFLIB_FilterExp_FLT.h" +#include "GDFLIB_FilterIIR1_FLT.h" +#include "GDFLIB_FilterIIR2_FLT.h" +#include "GDFLIB_FilterIIR3_FLT.h" +#include "GDFLIB_FilterIIR4_FLT.h" +#include "GDFLIB_FilterMA_FLT.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_FilterExpInit_FLT(fltInitVal, psParam) \ + GDFLIB_FilterExpInit_FLT_Ci(fltInitVal, psParam) +#define GDFLIB_FilterExp_FLT(fltInX, psParam) \ + GDFLIB_FilterExp_FLT_Ci(fltInX, psParam) +#define GDFLIB_FilterIIR1Init_FLT(psParam) \ + GDFLIB_FilterIIR1Init_FLT_Ci(psParam) +#define GDFLIB_FilterIIR1_FLT(fltInX, psParam) \ + GDFLIB_FilterIIR1_FLT_Ci(fltInX, psParam) +#define GDFLIB_FilterIIR2Init_FLT(psParam) \ + GDFLIB_FilterIIR2Init_FLT_C(psParam) +#define GDFLIB_FilterIIR2_FLT(fltInX, psParam) \ + GDFLIB_FilterIIR2_FLT_C(fltInX, psParam) +#define GDFLIB_FilterIIR3Init_FLT(psParam) \ + GDFLIB_FilterIIR3Init_FLT_C(psParam) +#define GDFLIB_FilterIIR3_FLT(fltInX, psParam) \ + GDFLIB_FilterIIR3_FLT_C(fltInX, psParam) +#define GDFLIB_FilterIIR4Init_FLT(psParam) \ + GDFLIB_FilterIIR4Init_FLT_C(psParam) +#define GDFLIB_FilterIIR4_FLT(fltInX, psParam) \ + GDFLIB_FilterIIR4_FLT_C(fltInX, psParam) +#define GDFLIB_FilterMAInit_FLT(fltInitVal, psParam) \ + GDFLIB_FilterMAInit_FLT_Ci(fltInitVal, psParam) +#define GDFLIB_FilterMA_FLT(fltInX, psParam) \ + GDFLIB_FilterMA_FLT_Ci(fltInX, psParam) + +#if defined(__cplusplus) +} +#endif + +#endif /* _GDFLIB_FP_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/gdflib_types.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/gdflib_types.h new file mode 100644 index 000000000..dbbd12842 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/Include/gdflib_types.h @@ -0,0 +1,55 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*******************************************************************************/ +#ifndef _GDFLIB_TYPES_H_ +#define _GDFLIB_TYPES_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GDFLIB_CONST + +#if defined(__cplusplus) +} +#endif + +#endif /*_GDFLIB_TYPES_H_*/ + + + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/libGDFLIB.a b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/libGDFLIB.a new file mode 100644 index 000000000..55f57574e Binary files /dev/null and b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GDFLIB/libGDFLIB.a differ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Acos_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Acos_F16.h new file mode 100644 index 000000000..785102bf4 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Acos_F16.h @@ -0,0 +1,83 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Arcus cosine function +* +*******************************************************************************/ +#ifndef _GFLIB_ACOS_F16_H_ +#define _GFLIB_ACOS_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Acos_F16_C(f16Val) GFLIB_Acos_F16_FC(f16Val, &f16gflibAcosCoef) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ /* Array of five 16-bit elements for storing coefficients of the piece-wise polynomial */ + const frac16_t f16A[5]; +} GFLIB_ACOS_TAYLOR_COEF_T_F16; + +typedef struct +{ /* Array of two elements for storing two sub-arrays (each sub-array + contains five 16-bit coefficients) for all sub-intervals*/ + GFLIB_ACOS_TAYLOR_COEF_T_F16 GFLIB_ACOS_SECTOR_F16[2]; + +} GFLIB_ACOS_T_F16; + +/******************************************************************************* +* Global variables +*******************************************************************************/ +extern GFLIB_CONST GFLIB_ACOS_T_F16 f16gflibAcosCoef; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t GFLIB_Acos_F16_FC(frac16_t f16Val, GFLIB_CONST GFLIB_ACOS_T_F16 *const psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_ACOS_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Acos_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Acos_FLT.h new file mode 100644 index 000000000..6d2f3ffc5 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Acos_FLT.h @@ -0,0 +1,77 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Arcus cosine function +* +*******************************************************************************/ +#ifndef _GFLIB_ACOS_FLT_H_ +#define _GFLIB_ACOS_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Acos_FLT_C(fltVal) GFLIB_Acos_FLT_FC(fltVal, &fltgflibAcosCoef) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + const float_t fltA[5]; /* Array of approximation coefficients */ +} GFLIB_ACOS_T_FLT; + +/******************************************************************************* +* Global variables +*******************************************************************************/ +extern GFLIB_CONST GFLIB_ACOS_T_FLT fltgflibAcosCoef; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern float_t GFLIB_Acos_FLT_FC(float_t fltVal,GFLIB_CONST GFLIB_ACOS_T_FLT *const psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_ACOS_FLT_H_ */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Asin_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Asin_F16.h new file mode 100644 index 000000000..f68ba5790 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Asin_F16.h @@ -0,0 +1,80 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Arcus sine function +* +*******************************************************************************/ +#ifndef _GFLIB_ASIN_F16_H_ +#define _GFLIB_ASIN_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Asin_F16_C(f16Val) GFLIB_Asin_F16_FC(f16Val, &f16gflibAsinCoef) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + const frac16_t f16A[5]; +} GFLIB_ASIN_TAYLOR_COEF_T_F16; + +typedef struct +{ + GFLIB_ASIN_TAYLOR_COEF_T_F16 GFLIB_ASIN_SECTOR_F16[2]; +} GFLIB_ASIN_T_F16; + +/******************************************************************************* +* Global variables +*******************************************************************************/ +extern GFLIB_CONST GFLIB_ASIN_T_F16 f16gflibAsinCoef; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t GFLIB_Asin_F16_FC(frac16_t f16Val, GFLIB_CONST GFLIB_ASIN_T_F16 *const psParam); + +#if defined(__cplusplus) +} +#endif +#endif /* _GFLIB_ASIN_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Asin_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Asin_FLT.h new file mode 100644 index 000000000..245bbc7f1 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Asin_FLT.h @@ -0,0 +1,76 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Arcus sine function +* +*******************************************************************************/ +#ifndef _GFLIB_ASIN_FLT_H_ +#define _GFLIB_ASIN_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Asin_FLT_C(fltVal) GFLIB_Asin_FLT_FC(fltVal, &fltgflibAsinCoef) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + const float_t fltA[8]; +} GFLIB_ASIN_T_FLT; + +/******************************************************************************* +* Global variables +*******************************************************************************/ +extern GFLIB_CONST GFLIB_ASIN_T_FLT fltgflibAsinCoef; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern float_t GFLIB_Asin_FLT_FC(float_t fltVal,GFLIB_CONST GFLIB_ASIN_T_FLT *const psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_ASIN_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_AtanYX_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_AtanYX_F16.h new file mode 100644 index 000000000..efa124c32 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_AtanYX_F16.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Arcus tangent function based on the provided x,y coordinates as arguments +* using division and piece-wise polynomial approximation +* +*******************************************************************************/ +#ifndef _GFLIB_ATANYX_F16_H_ +#define _GFLIB_ATANYX_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/****************************************************************************** +* Includes +******************************************************************************/ +#include "GFLIB_Atan_F32.h" + +/******************************************************************************* +* Global variables +*******************************************************************************/ +extern GFLIB_CONST GFLIB_ATAN_T_F32 gsAtanCoef; + +/****************************************************************************** +* Macros +******************************************************************************/ +#define GFLIB_AtanYX_F16_Asm(f16Y, f16X, pbErrFlag) \ + GFLIB_AtanYX_F16_FAsm(f16Y, f16X, pbErrFlag, &gsAtanCoef) + +/**************************************************************************** +* Exported function prototypes +****************************************************************************/ +extern frac16_t GFLIB_AtanYX_F16_FAsm(frac16_t f16Y, frac16_t f16X, + bool_t *pbErrFlag, + GFLIB_CONST GFLIB_ATAN_T_F32 *const psParam); + +#if defined(__cplusplus) +} +#endif +#endif /* _GFLIB_ATANYX_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_AtanYX_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_AtanYX_FLT.h new file mode 100644 index 000000000..f4c55cc1d --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_AtanYX_FLT.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Arcus tangent function based on the provided x,y coordinates as arguments +* using division and piece-wise polynomial approximation +* +*******************************************************************************/ +#ifndef _GFLIB_ATANYX_FLT_H_ +#define _GFLIB_ATANYX_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_FP.h" +#include "GFLIB_Atan_FLT.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_AtanYX_FLT_C(fltY, fltX, pbErrFlag) \ + GFLIB_AtanYX_FLT_FC(fltY, fltX, pbErrFlag) +#define GFLIB_AtanYX_A32f_C(fltY, fltX, pbErrFlag) \ + GFLIB_AtanYX_A32f_FC(fltY, fltX, pbErrFlag) + +/**************************************************************************** +* Exported function prototypes +****************************************************************************/ +extern float_t GFLIB_AtanYX_FLT_FC(float_t fltY, float_t fltX, + bool_t *pbErrFlag); +extern acc32_t GFLIB_AtanYX_A32f_FC(float_t fltY, float_t fltX, + bool_t *pbErrFlag); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_ATANYX_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Atan_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Atan_F32.h new file mode 100644 index 000000000..3b921b5e8 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Atan_F32.h @@ -0,0 +1,81 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Inverse tangent +* +*******************************************************************************/ +#ifndef _GFLIB_ATAN_F32_H_ +#define _GFLIB_ATAN_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_types.h" +#include "mlib.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Atan_F16_Asm(f16Val) GFLIB_Atan_F16_FAsm(f16Val, &gsAtanCoef) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac32_t f32A[3]; +}GFLIB_ATAN_COEF_T_F32; + +typedef struct +{ + GFLIB_ATAN_COEF_T_F32 GFLIB_ATAN_SECTOR_F32[8]; +}GFLIB_ATAN_T_F32; + +/******************************************************************************* +* Global variables +*******************************************************************************/ + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t GFLIB_Atan_F16_FAsm(frac16_t f16Val, GFLIB_CONST GFLIB_ATAN_T_F32 *const psParam); + + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_ATAN_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Atan_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Atan_FLT.h new file mode 100644 index 000000000..8730d92e3 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Atan_FLT.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Inverse tangent +* +*******************************************************************************/ +#ifndef _GFLIB_ATAN_FLT_H_ +#define _GFLIB_ATAN_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_types.h" +#include "mlib_FP.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Atan_FLT_C(fltVal) GFLIB_Atan_FLT_FC(fltVal, &gfltAtanCoef) +#define GFLIB_Atan_A32f_C(fltVal) GFLIB_Atan_A32f_FC(fltVal) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltA[6]; +} GFLIB_ATAN_T_FLT; + +/******************************************************************************* +* Global variables +*******************************************************************************/ +extern GFLIB_CONST GFLIB_ATAN_T_FLT gfltAtanCoef; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern float_t GFLIB_Atan_FLT_FC(float_t fltVal, GFLIB_CONST GFLIB_ATAN_T_FLT *const psParam); +extern acc32_t GFLIB_Atan_A32f_FC(float_t fltVal); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_ATAN_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlBetaIPDp_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlBetaIPDp_A32.h new file mode 100644 index 000000000..28d791cd4 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlBetaIPDp_A32.h @@ -0,0 +1,103 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Parallel beta IPD controller with and without anti-wind-up protection +* +*******************************************************************************/ +#ifndef _GFLIB_CTRLBETAIPDP_A32_H_ +#define _GFLIB_CTRLBETAIPDP_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_CtrlBetaIPDpAW_F16_C(f16InReq, f16In, f16InErrD, pbStopIntegFlag, psParam) \ + GFLIB_CtrlBetaIPDpAW_F16_FC(f16InReq, f16In, f16InErrD, pbStopIntegFlag, psParam) +#define GFLIB_CtrlBetaIPDpAWInit_F16_Ci(f16InitVal, psParam) \ + GFLIB_CtrlBetaIPDpAWInit_F16_FCi(f16InitVal, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + acc32_t a32PGain; /* Proportional Gain */ + acc32_t a32IGain; /* Integral Gain */ + acc32_t a32DGain; /* Derivative Gain */ + frac32_t f32IAccK_1; /* State variable output at step k-1 */ + frac16_t f16InErrK_1; /* State variable input error at step k-1 */ + frac16_t f16UpperLim; /* Upper Limit of the controller */ + frac16_t f16LowerLim; /* Lower Limit of the controller */ + frac16_t f16InErrDK_1; /* State variable input error at step k-1 */ + frac16_t f16BetaGain; /* Beta Gain for restricting the overshot */ + bool_t bLimFlag; /* Limitation flag, if set to 1, the controller + output has reached either the UpperLimit or LowerLimit */ +} GFLIB_CTRL_BETA_IPD_P_AW_T_A32; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t GFLIB_CtrlBetaIPDpAW_F16_FC(frac16_t f16InReq, frac16_t f16In, frac16_t f16InErrD, + const bool_t *pbStopIntegFlag, + GFLIB_CTRL_BETA_IPD_P_AW_T_A32 *psParam); + +/***************************************************************************//*! +* @brief The function initializes the actual values of CtrlBetaIPDpAWInit controller. +* +* @params in frac16_t f16InitVal - Initial state value for Integrating part +* ptr GFLIB_CTRL_BETA_IPD_P_AW_T_A32 *psParam - Pointer to controller structure +* +* @return N/A +* +*******************************************************************************/ +static inline void GFLIB_CtrlBetaIPDpAWInit_F16_FCi(frac16_t f16InitVal, + GFLIB_CTRL_BETA_IPD_P_AW_T_A32 *psParam) +{ + psParam->f32IAccK_1 = MLIB_Conv_F32s(f16InitVal); + psParam->f16InErrK_1 = (frac16_t)0; + psParam->f16InErrDK_1= (frac16_t)0; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_CTRLBETAIPDP_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlBetaIPDp_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlBetaIPDp_FLT.h new file mode 100644 index 000000000..0eca67f98 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlBetaIPDp_FLT.h @@ -0,0 +1,103 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Float parallel beta IP controller with and without anti-wind-up protection +* +*******************************************************************************/ +#ifndef _GFLIB_CTRLBETAIPDP_FLT_H_ +#define _GFLIB_CTRLBETAIPDP_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_CtrlBetaIPDpAW_FLT_C(fltInReq, fltIn, fltInErrD, pbStopIntegFlag, psParam) \ + GFLIB_CtrlBetaIPDpAW_FLT_FC(fltInReq, fltIn, fltInErrD, pbStopIntegFlag, psParam) +#define GFLIB_CtrlBetaIPDpAWInit_FLT_Ci(fltInitVal, psParam) \ + GFLIB_CtrlBetaIPDpAWInit_FLT_FCi(fltInitVal, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltPGain; /* Proportional Gain */ + float_t fltIGain; /* Integral Gain */ + float_t fltDGain; /* Derivative Gain */ + float_t fltIAccK_1; /* State variable output at step k-1 */ + float_t fltInErrK_1; /* State variable input error at step k-1 */ + float_t fltUpperLim; /* Upper Limit of the controller */ + float_t fltLowerLim; /* Lower Limit of the controller */ + float_t fltInErrDK_1; /* State variable input error at step k-1 */ + float_t fltBetaGain; /* Beta Gain for restricting the overshot */ + bool_t bLimFlag; /* Limitation flag, if set to 1, the controller output + has reached either the UpperLimit or LowerLimit */ +} GFLIB_CTRL_BETA_IPD_P_AW_T_FLT; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern float_t GFLIB_CtrlBetaIPDpAW_FLT_FC(float_t fltInReq, float_t fltIn, float_t fltInErrD, + const bool_t *pbStopIntegFlag, + GFLIB_CTRL_BETA_IPD_P_AW_T_FLT *psParam); + +/***************************************************************************//*! +* @brief The float function initializes the actual values of CtrlBetaIPDpAWInit controller. +* +* @params in float_t fltInitVal- Initial state value for Integrating part +* ptr GFLIB_CTRL_BETA_IPD_P_AW_T_FLT *psParam - Pointer to controller structure +* +* @return N/A +* +*******************************************************************************/ +static inline void GFLIB_CtrlBetaIPDpAWInit_FLT_FCi(float_t fltInitVal, + GFLIB_CTRL_BETA_IPD_P_AW_T_FLT *psParam) +{ + psParam->fltIAccK_1 = fltInitVal; + psParam->fltInErrK_1 = 0.0F; + psParam->fltInErrDK_1= 0.0F; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_CTRLBETAIPDP_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlBetaIPp_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlBetaIPp_A32.h new file mode 100644 index 000000000..0fd7d7607 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlBetaIPp_A32.h @@ -0,0 +1,101 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Parallel beta IP controller with and without anti-wind-up protection +* +*******************************************************************************/ +#ifndef _GFLIB_CTRLBETAIPP_A32_H_ +#define _GFLIB_CTRLBETAIPP_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_CtrlBetaIPpAW_F16_C(f16InReq, f16In, pbStopIntegFlag, psParam) \ + GFLIB_CtrlBetaIPpAW_F16_FC(f16InReq, f16In, pbStopIntegFlag, psParam) +#define GFLIB_CtrlBetaIPpAWInit_F16_Ci(f16InitVal, psParam) \ + GFLIB_CtrlBetaIPpAWInit_F16_FCi(f16InitVal, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + acc32_t a32PGain; /* Proportional Gain */ + acc32_t a32IGain; /* Integral Gain */ + frac32_t f32IAccK_1; /* State variable output at step k-1 */ + frac16_t f16InErrK_1; /* State variable input error at step k-1 */ + frac16_t f16UpperLim; /* Upper Limit of the controller */ + frac16_t f16LowerLim; /* Lower Limit of the controller */ + frac16_t f16BetaGain; /* Beta Gain for restricting the overshot */ + bool_t bLimFlag; /* Limitation flag, if set to 1, the controller + output has reached either the UpperLimit or LowerLimit */ +} GFLIB_CTRL_BETA_IP_P_AW_T_A32; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t GFLIB_CtrlBetaIPpAW_F16_FC(frac16_t f16InReq, frac16_t f16In, + const bool_t *pbStopIntegFlag, + GFLIB_CTRL_BETA_IP_P_AW_T_A32 *psParam); + +/***************************************************************************//*! +* @brief The function initializes the actual values of CtrlBetaIPpAWInit controller. +* +* @params in frac16_t f16InitVal - Initial state value for Integrating part +* ptr GFLIB_CTRL_BETA_IP_P_AW_T_A32 *psParam - Pointer to controller structure +* +* @return N/A +* +*******************************************************************************/ +static inline void GFLIB_CtrlBetaIPpAWInit_F16_FCi(frac16_t f16InitVal, + GFLIB_CTRL_BETA_IP_P_AW_T_A32 *psParam) +{ + psParam -> f32IAccK_1 = MLIB_Conv_F32s(f16InitVal); + psParam->f16InErrK_1 = (frac16_t)0; +} + + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_CTRLBETAIPP_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlBetaIPp_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlBetaIPp_FLT.h new file mode 100644 index 000000000..048a13acb --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlBetaIPp_FLT.h @@ -0,0 +1,100 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Float parallel beta IP controller with and without anti-wind-up protection +* +*******************************************************************************/ +#ifndef _GFLIB_CTRLBETAIPP_FLT_H_ +#define _GFLIB_CTRLBETAIPP_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_CtrlBetaIPpAW_FLT_C(fltInReq, fltIn, pbStopIntegFlag, psParam) \ + GFLIB_CtrlBetaIPpAW_FLT_FC(fltInReq, fltIn, pbStopIntegFlag, psParam) +#define GFLIB_CtrlBetaIPpAWInit_FLT_Ci(fltInitVal, psParam) \ + GFLIB_CtrlBetaIPpAWInit_FLT_FCi(fltInitVal, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltPGain; /* Proportional Gain */ + float_t fltIGain; /* Integral Gain */ + float_t fltIAccK_1; /* State variable output at step k-1 */ + float_t fltInErrK_1; /* State variable input error at step k-1 */ + float_t fltUpperLim; /* Upper Limit of the controller */ + float_t fltLowerLim; /* Lower Limit of the controller */ + float_t fltBetaGain; /* Beta Gain for restricting the overshot */ + bool_t bLimFlag; /* Limitation flag, if set to 1, the controller output + has reached either the UpperLimit or LowerLimit */ +} GFLIB_CTRL_BETA_IP_P_AW_T_FLT; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern float_t GFLIB_CtrlBetaIPpAW_FLT_FC(float_t fltInReq, float_t fltIn, + const bool_t *pbStopIntegFlag, + GFLIB_CTRL_BETA_IP_P_AW_T_FLT *psParam); + +/***************************************************************************//*! +* @brief The float function initializes the actual values of CtrlBetaIPpAWInit controller. +* +* @params in float_t fltInitVal- Initial state value for Integrating part +* ptr GFLIB_CTRL_BETA_IP_P_AW_T_FLT *psParam - Pointer to controller structure +* +* @return N/A +* +*******************************************************************************/ +static inline void GFLIB_CtrlBetaIPpAWInit_FLT_FCi(float_t fltInitVal, + GFLIB_CTRL_BETA_IP_P_AW_T_FLT *psParam) +{ + psParam->fltIAccK_1 = fltInitVal; + psParam->fltInErrK_1= 0.0F; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_CTRLBETAIPP_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlPIDp_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlPIDp_A32.h new file mode 100644 index 000000000..86412b8e6 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlPIDp_A32.h @@ -0,0 +1,103 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Parallel PID controller with and without anti-wind-up protection +* +*******************************************************************************/ +#ifndef _GFLIB_CTRLPIDP_A32_H_ +#define _GFLIB_CTRLPIDP_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_CtrlPIDpAW_F16_Asm(f16InErr, f16InErrD, pbStopIntegFlag, psParam) \ + GFLIB_CtrlPIDpAW_F16_FAsm(f16InErr, f16InErrD, pbStopIntegFlag, psParam) +#define GFLIB_CtrlPIDpAWInit_F16_Ci(f16InitVal, psParam) \ + GFLIB_CtrlPIDpAWInit_F16_FCi(f16InitVal, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + acc32_t a32PGain; /* Proportional Gain */ + acc32_t a32IGain; /* Integral Gain */ + acc32_t a32DGain; /* Derivative Gain */ + frac32_t f32IAccK_1; /* State variable output at step k-1 */ + frac16_t f16InErrK_1; /* State variable input error at step k-1 */ + frac16_t f16UpperLim; /* Upper Limit of the controller */ + frac16_t f16LowerLim; /* Lower Limit of the controller */ + frac16_t f16InErrDK_1; /* State variable input error at step k-1 */ + bool_t bLimFlag; /* Limitation flag, if set to 1, the controller output + has reached either the UpperLimit or LowerLimit */ +} GFLIB_CTRL_PID_P_AW_T_A32; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t GFLIB_CtrlPIDpAW_F16_FAsm(frac16_t f16InErr, + frac16_t f16InErrD, + const bool_t *pbStopIntegFlag, + GFLIB_CTRL_PID_P_AW_T_A32 *psParam); + +/***************************************************************************//*! +* @brief The function initializes the actual values of float CtrlPIDpInit controller. +* +* @params in frac16_t f16InitVal - Initial state value for Integrating part +* ptr GFLIB_CTRL_PID_P_AW_T_A32 *psParam - Pointer to controller structure +* +* @return N/A +* +*******************************************************************************/ +static inline void GFLIB_CtrlPIDpAWInit_F16_FCi(frac16_t f16InitVal, + GFLIB_CTRL_PID_P_AW_T_A32 *psParam) +{ + psParam->f32IAccK_1 = MLIB_Conv_F32s(f16InitVal); + psParam->f16InErrK_1 = (frac16_t)0; + psParam->f16InErrDK_1= (frac16_t)0; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_CTRLPIDP_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlPIDp_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlPIDp_FLT.h new file mode 100644 index 000000000..283af3398 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlPIDp_FLT.h @@ -0,0 +1,103 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Parallel PID controller with and without anti-wind-up protection +* +*******************************************************************************/ +#ifndef _GFLIB_CTRLPIDP_FLT_H_ +#define _GFLIB_CTRLPIDP_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_CtrlPIDpAW_FLT_C(fltInErr, fltInErrD, pbStopIntegFlag, psParam) \ + GFLIB_CtrlPIDpAW_FLT_FC(fltInErr, fltInErrD, pbStopIntegFlag, psParam) +#define GFLIB_CtrlPIDpAWInit_FLT_Ci(fltInitVal, psParam) \ + GFLIB_CtrlPIDpAWInit_FLT_FCi(fltInitVal, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltPGain; /* Proportional Gain */ + float_t fltIGain; /* Integral Gain */ + float_t fltDGain; /* Derivative Gain */ + float_t fltIAccK_1; /* State variable output at step k-1 */ + float_t fltInErrK_1; /* State variable input error at step k-1 */ + float_t fltUpperLim; /* Upper Limit of the controller */ + float_t fltLowerLim; /* Lower Limit of the controller */ + float_t fltInErrDK_1; /* State variable input error at step k-1 */ + bool_t bLimFlag; /* Limitation flag, if set to 1, the controller output + has reached either the UpperLimit or LowerLimit */ +} GFLIB_CTRL_PID_P_AW_T_FLT; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern float_t GFLIB_CtrlPIDpAW_FLT_FC(float_t fltInErr, + float_t fltInErrD, + const bool_t *pbStopIntegFlag, + GFLIB_CTRL_PID_P_AW_T_FLT *psParam); + +/***************************************************************************//*! +* @brief The function initializes the actual values of float CtrlPIDAWpInit controller. +* +* @params in float_t fltInitVal - Initial state value for Integrating part +* ptr GFLIB_CTRL_PID_P_AW_T_FLT *psParam - Pointer to controller structure +* +* @return N/A +* +*******************************************************************************/ +static inline void GFLIB_CtrlPIDpAWInit_FLT_FCi(float_t fltInitVal, + GFLIB_CTRL_PID_P_AW_T_FLT *psParam) +{ + psParam->fltIAccK_1 = fltInitVal; + psParam->fltInErrK_1 = 0.0F; + psParam->fltInErrDK_1= 0.0F; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_CTRLPIDP_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlPIp_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlPIp_A32.h new file mode 100644 index 000000000..44fd335ea --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlPIp_A32.h @@ -0,0 +1,99 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Parallel PI controller with and without anti-wind-up protection +* +*******************************************************************************/ +#ifndef _GFLIB_CTRLPIP_A32_H_ +#define _GFLIB_CTRLPIP_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_CtrlPIpAW_F16_Asm(f16InErr, pbStopIntegFlag, psParam) \ + GFLIB_CtrlPIpAW_F16_FAsm(f16InErr, pbStopIntegFlag, psParam) +#define GFLIB_CtrlPIpAWInit_F16_Ci(f16InitVal, psParam) \ + GFLIB_CtrlPIpAWInit_F16_FCi(f16InitVal, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + acc32_t a32PGain; /* Proportional Gain */ + acc32_t a32IGain; /* Integral Gain */ + frac32_t f32IAccK_1; /* State variable output at step k-1 */ + frac16_t f16InErrK_1; /* State variable input error at step k-1 */ + frac16_t f16UpperLim; /* Upper Limit of the controller */ + frac16_t f16LowerLim; /* Lower Limit of the controller */ + bool_t bLimFlag; /* Limitation flag, if set to 1, the controller + output has reached either the UpperLimit or LowerLimit */ +}GFLIB_CTRL_PI_P_AW_T_A32; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t GFLIB_CtrlPIpAW_F16_FAsm(frac16_t f16InErr, + const bool_t *pbStopIntegFlag, + GFLIB_CTRL_PI_P_AW_T_A32 *psParam); + +/***************************************************************************//*! +* @brief The function initializes the actual values of CtrlPIpAWInit controller. +* +* @params in frac16_t f16InitVal - Initial state value for Integrating part +* ptr GFLIB_CTRL_PI_P_AW_T_A32 *psParam - Pointer to controller structure +* +* @return N/A +* +*******************************************************************************/ +static inline void GFLIB_CtrlPIpAWInit_F16_FCi(frac16_t f16InitVal, + GFLIB_CTRL_PI_P_AW_T_A32 *psParam) +{ + psParam -> f32IAccK_1 = MLIB_Conv_F32s(f16InitVal); + psParam->f16InErrK_1 = (frac16_t)0; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_CTRLPIP_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlPIp_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlPIp_FLT.h new file mode 100644 index 000000000..c659dc012 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_CtrlPIp_FLT.h @@ -0,0 +1,99 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Parallel PI controller with anti-wind-up protection +* +*******************************************************************************/ +#ifndef _GFLIB_CTRLPIPAW_FLT_H_ +#define _GFLIB_CTRLPIPAW_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_CtrlPIpAW_FLT_C(fltInErr, pbStopIntegFlag, psParam) \ + GFLIB_CtrlPIpAW_FLT_FC(fltInErr, pbStopIntegFlag, psParam) +#define GFLIB_CtrlPIpAWInit_FLT_Ci(fltInitVal, psParam) \ + GFLIB_CtrlPIpAWInit_FLT_FCi(fltInitVal, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltPGain; /* Proportional Gain */ + float_t fltIGain; /* Integral Gain */ + float_t fltIAccK_1; /* State variable output at step k-1 */ + float_t fltInErrK_1; /* State variable input error at step k-1 */ + float_t fltUpperLim; /* Upper Limit of the controller */ + float_t fltLowerLim; /* Lower Limit of the controller */ + bool_t bLimFlag; /* Limitation flag, if set to 1, the controller output + has reached either the UpperLimit or LowerLimit */ +} GFLIB_CTRL_PI_P_AW_T_FLT; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern float_t GFLIB_CtrlPIpAW_FLT_FC(float_t fltInErr, + const bool_t *pbStopIntegFlag, + GFLIB_CTRL_PI_P_AW_T_FLT *psParam); + +/***************************************************************************//*! +* @brief The function initializes the actual values of float CtrlPIpAWInit controller. +* +* @params in float_t fltInitVal- Initial state value for Integrating part +* ptr GFLIB_CTRL_PI_P_AW_T_FLT *psParam - Pointer to controller structure +* +* @return N/A +* +*******************************************************************************/ +static inline void GFLIB_CtrlPIpAWInit_FLT_FCi(float_t fltInitVal, + GFLIB_CTRL_PI_P_AW_T_FLT *psParam) +{ + psParam->fltIAccK_1 = fltInitVal; + psParam->fltInErrK_1= 0.0F; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_CTRLPIPAW_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DFlexRamp_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DFlexRamp_A32.h new file mode 100644 index 000000000..3b0dd32ac --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DFlexRamp_A32.h @@ -0,0 +1,126 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Dynamic flex ramp functions with 16-bit fractional output +* +*******************************************************************************/ +#ifndef _GFLIB_DFLEXRAMP_A32_H_ +#define _GFLIB_DFLEXRAMP_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif +/****************************************************************************** +* Includes +******************************************************************************/ +#include "mlib.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define GFLIB_DFlexRampInit_F16_C(f16InitVal, psParam) \ + GFLIB_DFlexRampInit_F16_FC(f16InitVal, psParam) +#define GFLIB_DFlexRampCalcIncr_F16_C(f16Target, a32Duration, f32IncrSatMot, f32IncrSatGen, psParam) \ + GFLIB_DFlexRampCalcIncr_F16_FC(f16Target, a32Duration, f32IncrSatMot, f32IncrSatGen, psParam) +#define GFLIB_DFlexRamp_F16_C(f16Instant, pbStopFlagMot, pbStopFlagGen, psParam) \ + GFLIB_DFlexRamp_F16_FC(f16Instant, pbStopFlagMot, pbStopFlagGen, psParam) + +/****************************************************************************** +* Types +******************************************************************************/ +/* Flex dynamic ramp structure */ +typedef struct +{ + frac32_t f32State; + frac32_t f32Incr; + frac32_t f32IncrSatMot; + frac32_t f32IncrSatGen; + frac32_t f32Target; + frac32_t f32Ts; + frac32_t f32IncrMax; + bool_t bReachFlag; +} GFLIB_DFLEXRAMP_T_F32; + +/****************************************************************************** +* Exported function prototypes +******************************************************************************/ +extern void GFLIB_DFlexRampCalcIncr_F16_FC(frac16_t f16Target, + acc32_t a32Duration, + frac32_t f32IncrSatMot, + frac32_t f32IncrSatGen, + GFLIB_DFLEXRAMP_T_F32 *psParam); + +extern frac16_t GFLIB_DFlexRamp_F16_FC(frac16_t f16Instant, + const bool_t *pbStopFlagMot, + const bool_t *pbStopFlagGen, + GFLIB_DFLEXRAMP_T_F32 *psParam); + + +/****************************************************************************** +* Inline functions +******************************************************************************/ + +/***************************************************************************//*! +* +* @brief Dynamic flex ramp initialization +* +* @param in frac16_t f16InitVal - Measured instant value in <-1;1) in frac16_t +* +* @param ptr GFLIB_FLEXRAMP_T_F32 *psParam +* - f32State: State variable keeping the last state, assigned by GFLIB_DFlexRampInit_F16 +* - f32Incr: Increment - calculated by GFLIB_DFlexRampCalcIncr_F16 function +* - f32IncrSatMot: Motor mode saturation mode increment - assigned by user(positive value), +* sign can be changed by GFLIB_DFlexRampCalcIncr_F16 +* - f32IncrSatGen: Generator mode saturation mode increment - assigned by user(positive value), +* sign can be changed by GFLIB_DFlexRampCalcIncr_F16 +* - f32Target: Target value - assigned by GFLIB_DFlexRampCalcIncr_F16 function +* - f32Ts: Sample time [s] - assigned by user(positive value) +* - f32IncrMax: Maximum increment - assigned by user(positive value) +* - bReachFlag: Flag is set to TRUE if the desired value is achieved +* +* @return void +* +* @remarks The initialization value is stored into the f32State variable and the bReachFlag flag is cleared. +* +****************************************************************************/ +static inline void GFLIB_DFlexRampInit_F16_FC(register frac16_t f16InitVal, + register GFLIB_DFLEXRAMP_T_F32 *psParam) +{ + psParam -> f32State = MLIB_Conv_F32s(f16InitVal); + psParam -> bReachFlag = FALSE; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_DFLEXRAMP_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DFlexRamp_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DFlexRamp_FLT.h new file mode 100644 index 000000000..69efc20c8 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DFlexRamp_FLT.h @@ -0,0 +1,126 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Float dynamic flex ramp functions +* +*******************************************************************************/ +#ifndef _GFLIB_DFLEXRAMP_FLT_H_ +#define _GFLIB_DFLEXRAMP_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif +/****************************************************************************** +* Includes +******************************************************************************/ +#include "mlib_FP.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define GFLIB_DFlexRampInit_FLT_C(fltInitVal, psParam) \ + GFLIB_DFlexRampInit_FLT_FC(fltInitVal, psParam) +#define GFLIB_DFlexRampCalcIncr_FLT_C(fltTarget, fltDuration, fltIncrSatMot, fltIncrSatGen, psParam) \ + GFLIB_DFlexRampCalcIncr_FLT_FC(fltTarget, fltDuration, fltIncrSatMot, fltIncrSatGen, psParam) +#define GFLIB_DFlexRamp_FLT_C(fltInstant, pbStopFlagMot, pbStopFlagGen, psParam) \ + GFLIB_DFlexRamp_FLT_FC(fltInstant, pbStopFlagMot, pbStopFlagGen, psParam) + +/****************************************************************************** +* Types +******************************************************************************/ +/* Flex dynamic ramp structure */ +typedef struct +{ + float_t fltState; + float_t fltIncr; + float_t fltIncrSatMot; + float_t fltIncrSatGen; + float_t fltTarget; + float_t fltTs; + float_t fltIncrMax; + bool_t bReachFlag; +} GFLIB_DFLEXRAMP_T_FLT; + +/****************************************************************************** +* Exported function prototypes +******************************************************************************/ +extern void GFLIB_DFlexRampCalcIncr_FLT_FC(float_t fltTarget, + float_t fltDuration, + float_t fltIncrSatMot, + float_t fltIncrSatGen, + GFLIB_DFLEXRAMP_T_FLT *psParam); + +extern float_t GFLIB_DFlexRamp_FLT_FC(float_t fltInstant, + const bool_t *pbStopFlagMot, + const bool_t *pbStopFlagGen, + GFLIB_DFLEXRAMP_T_FLT *psParam); + + +/****************************************************************************** +* Inline functions +******************************************************************************/ + +/***************************************************************************//*! +* +* @brief Float dynamic flex ramp initialization +* +* @param in float_t fltInitVal - Measured instant value in float_t +* +* @param ptr GFLIB_FLEXRAMP_T_FLT *psParam +* - fltState: State variable keeping the last state, assigned by GFLIB_DFlexRampInit_FLT +* - fltIncr: Increment - calculated by GFLIB_DFlexRampCalcIncr_FLT function +* - fltIncrSatMot: Motor mode saturation mode increment - assigned by user(positive value), +* sign can be changed by GFLIB_DFlexRampCalcIncr_FLT +* - fltIncrSatGen: Generator mode saturation mode increment - assigned by user(positive value), +* sign can be changed by GFLIB_DFlexRampCalcIncr_FLT +* - fltTarget: Target value - assigned by GFLIB_DFlexRampCalcIncr_FLT function +* - fltTs: Sample time [s] - assigned by user(positive value) +* - fltIncrMax: Maximum increment - assigned by user(positive value) +* - bReachFlag: Flag is set to TRUE if the desired value is achieved +* +* @return void +* +* @remarks The initialization value is stored into the fltState variable and the bReachFlag flag is cleared. +* +****************************************************************************/ +static inline void GFLIB_DFlexRampInit_FLT_FC(register float_t fltInitVal, + register GFLIB_DFLEXRAMP_T_FLT *psParam) +{ + psParam -> fltState = fltInitVal; + psParam -> bReachFlag = FALSE; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_DFLEXRAMP_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DRamp_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DRamp_F16.h new file mode 100644 index 000000000..8e73971c6 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DRamp_F16.h @@ -0,0 +1,101 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Dynamic Ramp +* +*******************************************************************************/ +#ifndef _GFLIB_DRAMP_F16_H_ +#define _GFLIB_DRAMP_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_types.h" +#include "mlib.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_DRampInit_F16_Ci(f16InitVal, psParam) \ + GFLIB_DRampInit_F16_FCi(f16InitVal, psParam) +#define GFLIB_DRamp_F16_Asm(f16Target, f16Instant, pbStopFlag, psParam) \ + GFLIB_DRamp_F16_FAsm(f16Target, f16Instant, pbStopFlag, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac16_t f16RampUp; /* Ramp-up increment */ + frac16_t f16RampDown; /* Ramp-down increment */ + frac16_t f16RampUpSat; /* Ramp-up increment used in case of saturation */ + frac16_t f16RampDownSat; /* Ramp-down increment used in case of saturation */ + frac16_t f16State; /* Previous ramp value */ + bool_t bReachFlag; /* Flag is set to 1 if the desired value is achieved */ +} GFLIB_DRAMP_T_F16; + +/***************************************************************************//*! +* @brief The function initializes the actual value of DRamp_F16. +* +* @param ptr GFLIB_DRAMP_T_F16 *psParam +* - f16RampUp: Ramp-up increment +* - f16RampDown: Ramp-down increment +* - f16RampUpSat: Ramp-up increment used in case of saturation +* - f16RampDownSat: Ramp-down increment used in case of saturation +* - f16State: Previous ramp value +* - bReachFlag: Flag is set to 1 if the desired value is achieved +* @param in frac16_t f16InitVal - Initial value +* @remarks The initialization value is stored into the psParam->f16State and the +* bReachFlag flag is cleared. +*******************************************************************************/ +static inline void GFLIB_DRampInit_F16_FCi(frac16_t f16InitVal, GFLIB_DRAMP_T_F16 *psParam) +{ + psParam->f16State = f16InitVal; + psParam->bReachFlag = (bool_t)0; +} + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t GFLIB_DRamp_F16_FAsm(frac16_t f16Target, frac16_t f16Instant, + const bool_t *pbStopFlag, GFLIB_DRAMP_T_F16 *psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_DRAMP_F16_H_ */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DRamp_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DRamp_F32.h new file mode 100644 index 000000000..1a1ad9b2f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DRamp_F32.h @@ -0,0 +1,101 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Dynamic ramp +* +*******************************************************************************/ +#ifndef _GFLIB_DRAMP_F32_H_ +#define _GFLIB_DRAMP_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_DRampInit_F32_Ci(f32InitVal, psParam) \ + GFLIB_DRampInit_F32_FCi(f32InitVal, psParam) +#define GFLIB_DRamp_F32_Asm(f32Target, f32Instant, pbStopFlag, psParam) \ + GFLIB_DRamp_F32_FAsm(f32Target, f32Instant, pbStopFlag, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac32_t f32RampUp; /* Ramp-up increment */ + frac32_t f32RampDown; /* Ramp-down increment */ + frac32_t f32RampUpSat; /* Ramp-up increment used in case of saturation */ + frac32_t f32RampDownSat; /* Ramp-down increment used in case of saturation */ + frac32_t f32State; /* Previous ramp value */ + bool_t bReachFlag; /* Flag is set to 1 if the desired value is achieved */ +} GFLIB_DRAMP_T_F32; + +/***************************************************************************//*! +* @brief The function initializes the actual value of DRamp_F32. +* +* @param ptr GFLIB_DRAMP_T_F32 *psParam +* - f32RampUp: Ramp-up increment +* - f32RampDown: Ramp-down increment +* - f32RampUpSat: Ramp-up increment used in case of saturation +* - f32RampDownSat: Ramp-down increment used in case of saturation +* - f32State: Previous ramp value +* - bReachFlag: Flag is set to 1 if the desired value is achieved +* @param in frac32_t f32InitVal - Initial value +* @remarks The initialization value is stored into the psParam->f32State and the +* bReachFlag flag is cleared. +*******************************************************************************/ +static inline void GFLIB_DRampInit_F32_FCi(frac32_t f32InitVal, GFLIB_DRAMP_T_F32 *psParam) +{ + psParam->f32State = f32InitVal; + psParam->bReachFlag = (bool_t)0; +} + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac32_t GFLIB_DRamp_F32_FAsm(frac32_t f32Target, frac32_t f32Instant, + const bool_t *pbStopFlag, GFLIB_DRAMP_T_F32 *psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_DRAMP_F32_H_ */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DRamp_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DRamp_FLT.h new file mode 100644 index 000000000..72640ec74 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_DRamp_FLT.h @@ -0,0 +1,100 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Dynamic ramp +* +*******************************************************************************/ +#ifndef _GFLIB_DRAMP_FLT_H_ +#define _GFLIB_DRAMP_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_DRampInit_FLT_Ci(fltInitVal, psParam) \ + GFLIB_DRampInit_FLT_FCi(fltInitVal, psParam) +#define GFLIB_DRamp_FLT_C(fltTarget, fltInstant, pbStopFlag, psParam) \ + GFLIB_DRamp_FLT_FC(fltTarget, fltInstant, pbStopFlag, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltRampUp; /* Ramp-up increment */ + float_t fltRampDown; /* Ramp-down increment */ + float_t fltRampUpSat; /* Ramp-up increment used in case of saturation */ + float_t fltRampDownSat; /* Ramp-down increment used in case of saturation */ + float_t fltState; /* Previous ramp value */ + bool_t bReachFlag; /* Flag is set to 1 if the desired value is achieved */ +} GFLIB_DRAMP_T_FLT; + +/***************************************************************************//*! +* @brief The function initializes the actual value of DRamp_FLT. +* +* @param ptr GFLIB_DRAMP_T_FLT *psParam +* - fltRampUp: Ramp-up increment +* - fltRampDown: Ramp-down increment +* - fltRampUpSat: Ramp-up increment used in case of saturation +* - fltRampDownSat: Ramp-down increment used in case of saturation +* - fltState: Previous ramp value +* - bReachFlag: Flag is set to 1 if the desired value is achieved +* @param in float_t fltInitVal - Initial value +* @remarks The initialization value is stored into the psParam->fltState and the +* bReachFlag flag is cleared. +*******************************************************************************/ +static inline void GFLIB_DRampInit_FLT_FCi(float_t fltInitVal, GFLIB_DRAMP_T_FLT *psParam) +{ + psParam->fltState = fltInitVal; + psParam->bReachFlag = (bool_t)0; +} + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern float_t GFLIB_DRamp_FLT_FC(float_t fltTarget, float_t fltInstant, + const bool_t *pbStopFlag, GFLIB_DRAMP_T_FLT *psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_DRAMP_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_FlexRamp_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_FlexRamp_A32.h new file mode 100644 index 000000000..587d4702a --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_FlexRamp_A32.h @@ -0,0 +1,116 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Flex ramp functions with 16-bit fractional output +* +*******************************************************************************/ +#ifndef _GFLIB_FLEXRAMP_A32_H_ +#define _GFLIB_FLEXRAMP_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif +/****************************************************************************** +* Includes +******************************************************************************/ +#include "mlib.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define GFLIB_FlexRampInit_F16_C(f16InitVal, psParam) \ + GFLIB_FlexRampInit_F16_FC(f16InitVal, psParam) +#define GFLIB_FlexRampCalcIncr_F16_C(f16Target, a32Duration, psParam) \ + GFLIB_FlexRampCalcIncr_F16_FC(f16Target, a32Duration, psParam) +#define GFLIB_FlexRamp_F16_C(psParam) \ + GFLIB_FlexRamp_F16_FC(psParam) + +/****************************************************************************** +* Types +******************************************************************************/ +/* Flex dynamic ramp structure */ +typedef struct +{ + frac32_t f32State; + frac32_t f32Incr; + frac32_t f32Target; + frac32_t f32Ts; + frac32_t f32IncrMax; + bool_t bReachFlag; +} GFLIB_FLEXRAMP_T_F32; + +/****************************************************************************** +* Exported function prototypes +******************************************************************************/ +extern void GFLIB_FlexRampCalcIncr_F16_FC(frac16_t f16Target, + acc32_t a32Duration, + GFLIB_FLEXRAMP_T_F32 *psParam); + +extern frac16_t GFLIB_FlexRamp_F16_FC(GFLIB_FLEXRAMP_T_F32 *psParam); + +/****************************************************************************** +* Inline functions +******************************************************************************/ + +/***************************************************************************//*! +* +* @brief Flex ramp initialization +* +* @param in frac16_t f16InitVal - Measured instant value in <-1;1) in frac16_t +* +* @param ptr GFLIB_FLEXRAMP_T_F32 *psParam +* - f32State: State variable keeping the last state, assigned by +* GFLIB_FlexRampInit_F16 +* - f32Incr: Increment - calculated by GFLIB_FlexRampCalcIncr_F16 function +* - f32Target: Target value - assigned by GFLIB_FlexRampCalcIncr_F16 function +* - f32Ts: Sample time [s] - assigned by user(positive value) +* - f32IncrMax: Maximum increment - assigned by user(positive value) +* - bReachFlag: Flag is set to TRUE if the desired value is achieved +* +* @return void +* +* @remarks The initialization value is stored into the f32State variable and the +* bReachFlag flag is cleared. +* +****************************************************************************/ +static inline void GFLIB_FlexRampInit_F16_FC(register frac16_t f16InitVal, + register GFLIB_FLEXRAMP_T_F32 *psParam) +{ + psParam -> f32State = MLIB_Conv_F32s(f16InitVal); + psParam -> bReachFlag = FALSE; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_FLEXRAMP_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_FlexRamp_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_FlexRamp_FLT.h new file mode 100644 index 000000000..ff4af9cc4 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_FlexRamp_FLT.h @@ -0,0 +1,116 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Float flex ramp functions +* +*******************************************************************************/ +#ifndef _GFLIB_FLEXRAMP_FLT_H_ +#define _GFLIB_FLEXRAMP_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif +/****************************************************************************** +* Includes +******************************************************************************/ +#include "mlib_FP.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define GFLIB_FlexRampInit_FLT_C(fltInitVal, psParam) \ + GFLIB_FlexRampInit_FLT_FC(fltInitVal, psParam) +#define GFLIB_FlexRampCalcIncr_FLT_C(fltTarget, fltDuration, psParam) \ + GFLIB_FlexRampCalcIncr_FLT_FC(fltTarget, fltDuration, psParam) +#define GFLIB_FlexRamp_FLT_C(psParam) \ + GFLIB_FlexRamp_FLT_FC(psParam) + +/****************************************************************************** +* Types +******************************************************************************/ +/* Flex dynamic ramp structure */ +typedef struct +{ + float_t fltState; + float_t fltIncr; + float_t fltTarget; + float_t fltTs; + float_t fltIncrMax; + bool_t bReachFlag; +} GFLIB_FLEXRAMP_T_FLT; + +/****************************************************************************** +* Exported function prototypes +******************************************************************************/ +extern void GFLIB_FlexRampCalcIncr_FLT_FC(float_t fltTarget, + float_t fltDuration, + GFLIB_FLEXRAMP_T_FLT *psParam); + +extern float_t GFLIB_FlexRamp_FLT_FC(GFLIB_FLEXRAMP_T_FLT *psParam); + +/****************************************************************************** +* Inline functions +******************************************************************************/ + +/***************************************************************************//*! +* +* @brief Float Flex ramp initialization +* +* @param in float_t fltInitVal - Measured instant value in float_t +* +* @param ptr GFLIB_FLEXRAMP_T_FLT *psParam +* - fltState: State variable keeping the last state, assigned by +* GFLIB_FlexRampInit_FLT +* - fltIncr: Increment - calculated by GFLIB_FlexRampCalcIncr_FLT function +* - fltTarget: Target value - assigned by GFLIB_FlexRampCalcIncr_FLT function +* - fltTs: Sample time [s] - assigned by user(positive value) +* - fltIncrMax: Maximum increment - assigned by user(positive value) +* - bReachFlag: Flag is set to TRUE if the desired value is achieved +* +* @return void +* +* @remarks The initialization value is stored into the fltState variable and the +* bReachFlag flag is cleared. +* +****************************************************************************/ +static inline void GFLIB_FlexRampInit_FLT_FC(register float_t fltInitVal, + register GFLIB_FLEXRAMP_T_FLT *psParam) +{ + psParam -> fltState = fltInitVal; + psParam -> bReachFlag = FALSE; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_FLEXRAMP_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_FlexSRamp_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_FlexSRamp_A32.h new file mode 100644 index 000000000..5fcb90197 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_FlexSRamp_A32.h @@ -0,0 +1,129 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Flex s-ramp functions with 16-bit fractional output +* +*******************************************************************************/ +#ifndef _GFLIB_FLEXSRAMP_A32_H_ +#define _GFLIB_FLEXSRAMP_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif +/****************************************************************************** +* Includes +******************************************************************************/ +#include "gflib.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define GFLIB_FlexSRampInit_F16_C(f16InitVal, psParam) \ + GFLIB_FlexSRampInit_F16_FC(f16InitVal, psParam) +#define GFLIB_FlexSRampCalcIncr_F16_C(f16Target, a32Duration, psParam) \ + GFLIB_FlexSRampCalcIncr_F16_FC(f16Target, a32Duration, psParam) +#define GFLIB_FlexSRamp_F16_C(psParam) \ + GFLIB_FlexSRamp_F16_FC(psParam) + +/****************************************************************************** +* Types +******************************************************************************/ +/* Flex dynamic S ramp structure */ +typedef struct +{ + frac32_t f32State; /* state variable keeping the last state x */ + frac32_t f32Incr; /* derivative of x (dX) - acceleration */ + frac32_t f32AIncr; /* derivative of a (dA) - der. of acceleration */ + frac32_t f32ADes; /* desired acceleration - must be <= f32Incrmax */ + frac32_t f32Target; /* target value x */ + frac32_t f32Ts; /* sample time [s] */ + frac32_t f32IncrMax; /* maximum increment of x */ + frac32_t f32XT1; /* X(T1) - x at the instant where the ramp got the desired acceleration (f32Incr = const) */ + frac32_t f32XT2; /* X(T2) - x at the instant where the ramp started to decelerate */ + frac16_t f16DA; /* defined derivative of acceleration: dA = A / T */ + uint16_t u16AccState; /* state of the ramp process 0: f32Incr rising, 1: f32Incr = const, 2: f32Incr falling */ + bool_t bReachFlag; /* flag is set to TRUE if the desired value is achieved */ +} GFLIB_FLEXSRAMP_T_F32 ; + +/****************************************************************************** +* Exported function prototypes +******************************************************************************/ +extern bool_t GFLIB_FlexSRampCalcIncr_F16_C(frac16_t f16Target, acc32_t a32Duration, + GFLIB_FLEXSRAMP_T_F32 *psParam); + +extern frac16_t GFLIB_FlexSRamp_F16_FC(GFLIB_FLEXSRAMP_T_F32 *psParam); + +/****************************************************************************** +* Inline functions +******************************************************************************/ + +/***************************************************************************//*! +* +* @brief Flex s-ramp initialization +* +* @param in frac16_t f16InitVal - Measured instant value in <-1;1) in frac16_t +* +* @param ptr GFLIB_FLEXSRAMP_T_F32 *psParam +* - state variable keeping the last state x +* - derivative of x (dX) - acceleration +* - derivative of a (dA) - der. of acceleration +* - desired acceleration - must be <= f32Incrmax +* - target value x +* - sample time [s] +* - maximum increment of x +* - X(T1) - x at the instant where the ramp got the desired acceleration (f32Incr = const) +* X(T2) - x at the instant where the ramp started to decelerate +* - defined derivative of acceleration: dA = A / T +* - state of the ramp process 0: f32Incr rising, 1: f32Incr = const, 2: f32Incr falling +* - flag is set to TRUE if the desired value is achieved +* +* @return void +* +* @remarks The init value is stored into the f32State variable. The f32Incr is +* reset to 0 and the state variable u16AccState is set to 0. The +* bReachFlag flag is cleared. +* +****************************************************************************/ +static inline void GFLIB_FlexSRampInit_F16_FC(register frac16_t f16InitVal, + register GFLIB_FLEXSRAMP_T_F32 *psParam) +{ + psParam -> f32State = MLIB_Conv_F32s(f16InitVal); + psParam -> bReachFlag = FALSE; + psParam -> f32AIncr = 0; + psParam -> u16AccState = 0; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_FLEXSRAMP_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_FlexSRamp_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_FlexSRamp_FLT.h new file mode 100644 index 000000000..5239b0c54 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_FlexSRamp_FLT.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Float flex s-ramp functions +* +*******************************************************************************/ +#ifndef _GFLIB_FLEXSRAMP_FLT_H_ +#define _GFLIB_FLEXSRAMP_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif +/****************************************************************************** +* Includes +******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_FP.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define GFLIB_FlexSRampInit_FLT_C(fltInitVal, psParam) \ + GFLIB_FlexSRampInit_FLT_FC(fltInitVal, psParam) +#define GFLIB_FlexSRampCalcIncr_FLT_C(fltTarget, fltDuration, psParam) \ + GFLIB_FlexSRampCalcIncr_FLT_FC(fltTarget, fltDuration, psParam) +#define GFLIB_FlexSRamp_FLT_C(psParam) \ + GFLIB_FlexSRamp_FLT_FC(psParam) + +/****************************************************************************** +* Types +******************************************************************************/ +/* Flex dynamic ramp structure */ +typedef struct +{ + float_t fltState; /* state variable keeping the last state x */ + float_t fltIncr; /* derivative of x (dX) - acceleration */ + float_t fltAIncr; /* derivative of a (dA) - der. of acceleration */ + float_t fltADes; /* desired acceleration - must be <= f32Incrmax */ + float_t fltTarget; /* target value x */ + float_t fltTs; /* sample time [s] */ + float_t fltIncrMax; /* maximum increment of x */ + float_t fltXT1; /* X(T1) - x at the instant where the ramp got the desired acceleration (f32Incr = const) */ + float_t fltXT2; /* X(T2) - x at the instant where the ramp started to decelerate */ + float_t fltDA; /* defined derivative of acceleration: dA = A / T */ + uint16_t u16AccState;/* state of the ramp process 0: f32Incr rising, 1: f32Incr = const, 2: f32Incr falling */ + bool_t bReachFlag; /* flag is set to TRUE if the desired value is achieved */ +} GFLIB_FLEXSRAMP_T_FLT; + +/****************************************************************************** +* Exported function prototypes +******************************************************************************/ +extern bool_t GFLIB_FlexSRampCalcIncr_FLT_FC(float_t fltTarget, float_t fltDur, + GFLIB_FLEXSRAMP_T_FLT *psParam); + +extern float_t GFLIB_FlexSRamp_FLT_FC(GFLIB_FLEXSRAMP_T_FLT *psParam); + +/****************************************************************************** +* Inline functions +******************************************************************************/ + +/***************************************************************************//*! +* +* @brief Float flex s-ramp initialization +* +* @param in float_t fltInitVal - Measured instant value in float_t +* +* @param ptr GFLIB_FLEXSRAMP_T_FLT *psParam +* - State variable keeping the last state x +* - derivative of x (dX) - acceleration +* - derivative of a (dA) - der. of acceleration +* - desired acceleration - must be <= fltIncrmax +* - Target value x +* - Sample time [s] +* - Maximum increment of x +* - X(T1) - x at the instant where the ramp got the desired acceleration (fltIncr = const) +* - X(T2) - x at the instant where the ramp started to decelerate +* - Defined derivative of acceleration: dA = A / T +* - State of the ramp process 0: fltIncr rising, 1: fltIncr = const, 2: fltIncr falling +* - Flag is set to TRUE if the desired value is achieved +* +* @return void +* +* @remarks The init value is stored into the fltState variable. The fltIncr is +* reset to 0 and the state variable u16AccState is set to 0. The +* bReachFlag flag is cleared. +* +****************************************************************************/ +static inline void GFLIB_FlexSRampInit_FLT_FC(register float_t fltInitVal, + register GFLIB_FLEXSRAMP_T_FLT *psParam) +{ + psParam -> fltState = fltInitVal; + psParam -> bReachFlag = FALSE; + psParam -> fltAIncr = 0.0F; + psParam -> u16AccState = 0; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_FLEXSRAMP_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Hyst_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Hyst_F16_Asmi.h new file mode 100644 index 000000000..ee9395846 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Hyst_F16_Asmi.h @@ -0,0 +1,163 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Hysteresis function +* +*******************************************************************************/ +#ifndef _GFLIB_HYST_F16_ASMI_H_ +#define _GFLIB_HYST_F16_ASMI_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Hyst_F16_Asmi(f16Val, psParam) GFLIB_Hyst_F16_FAsmi(f16Val, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac16_t f16HystOn; /* Value determining the upper threshold */ + frac16_t f16HystOff; /* Value determining the lower threshold */ + frac16_t f16OutValOn; /* Value of the output when input is higher than the upper threshold */ + frac16_t f16OutValOff; /* Value of output when input is lower than lower threshold */ + frac16_t f16OutState; /* Actual state of the output */ +} GFLIB_HYST_T_F16; + +/***************************************************************************//*! +* +* @brief Hysteresis function +* +* @param ptr GFLIB_HYST_T_F16 *psParam +* - f16HystOn: Upper threshold +* - f16HystOff: Lower threshold +* - f16OutValOn: Output when input is above f16HystOn +* - f16OutValOff: Output when input is below f16HystOff +* - f16OutState: Output of the function +* +* @param in frac16_t f16Val +* - Argument in <-1;1) in frac16_t +* +* @return N/A +* +* @remarks The function represents a hysteresis (or relay) function. The +* function switches output between the two predefined values. When +* the input is higher than upper threshold f16HystOn, the output +* is high; when the input is below another (lower) threshold +* f16HystOff, the output is low; when the input is between the two, +* the output retains its value. +* +****************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_suppress=Pe549 /* Suppresses the Pe549 warning for IAR compiler*/ +#endif +/* inline function without any optimization (compilation issue) */ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t GFLIB_Hyst_F16_FAsmi(frac16_t f16Val, GFLIB_HYST_T_F16 *psParam) +{ + register frac16_t f16Temp=0, f16Out=0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ ldrsh f16Temp, [psParam, #2] /* f16Temp = psParam->f16HystOff */ + sxth f16Val, f16Val /* Sign extend */ + cmp f16Temp, f16Val /* Compares f16HystOff with f16Val*/ + blt Hyst_F16_HystOn /* If f16HystOff < f16Val, then goes to the Hyst_F16_HystOn */ + ldrh f16Out, [psParam, #6] /* f16Out = psParam->f16OutValOff */ + b Hyst_F16_End /* Goes to the Hyst_F16_End */ + Hyst_F16_HystOn: + ldrsh f16Temp, [psParam] /* f16Temp = psParam->f16HystOn */ + cmp f16Temp, f16Val /* Compares f16HystOn with f16Val*/ + bgt Hyst_F16_State /* If f16HystOn > f16Val, then goes to the Hyst_F16_State */ + ldrh f16Out, [psParam, #4] /* f16Out = psParam->f16OutValOn */ + b Hyst_F16_End /* Goes to the Hyst_F16_End */ + Hyst_F16_State: + ldrh f16Out, [psParam, #8] /* f16Out = psParam->f16State */ + ldrh f16Temp, [psParam, #4] /* f16Temp = psParam->f16OutValOn */ + cmp f16Out, f16Temp /* Compares f16State with f16OutValOn */ + it ne /* If f16State != f16OutValOn, then executes next command */ + ldrhne f16Out, [psParam, #6] /* f16Out = psParam->f16OutValOff */ + Hyst_F16_End: + strh f16Out, [psParam, #8] };/* psParam->f16State = f16Out */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "ldrsh %2, [%3, #2] \n" /* f16Temp = psParam->f16HystOff */ + "sxth %1, %1 \n" /* Sign extend */ + "cmp %2, %1 \n" /* Compares f16HystOff with f16Val*/ + "blt.n Hyst_F16_HystOn \n" /* If f16HystOff < f16Val, then goes to the Hyst_F16_HystOn */ + "ldrh %0, [%3, #6] \n" /* f16Out = psParam->f16OutValOff */ + "b.n Hyst_F16_End \n" /* Goes to the Hyst_F16_End */ + "Hyst_F16_HystOn: \n" + "ldrsh %2, [%3] \n" /* f16Temp = psParam->f16HystOn */ + "cmp %2, %1 \n" /* Compares f16HystOn with f16Val*/ + "bgt.n Hyst_F16_State \n" /* If f16HystOn > f16Val, then goes to the Hyst_F16_State */ + "ldrh %0, [%3, #4] \n" /* f16Out = psParam->f16OutValOn */ + "b.n Hyst_F16_End \n" /* Goes to the Hyst_F16_End */ + "Hyst_F16_State: \n" + "ldrh %0, [%3, #8] \n" /* f16Out = psParam->f16State */ + "ldrh %2, [%3, #4] \n" /* f16Temp = psParam->f16OutValOn */ + "cmp %0, %2 \n" /* Compares f16State with f16OutValOn */ + "it ne \n" /* If f16State != f16OutValOn, then executes next command */ + "ldrhne %0, [%3, #6] \n" /* f16Out = psParam->f16OutValOff */ + "Hyst_F16_End: \n" + "strh %0, [%3, #8] \n" /* psParam->f16State = f16Out */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Out), "+l"(f16Val), "+l"(f16Temp): "l"(psParam)); + #endif + + return f16Out; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_default=Pe549 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _GFLIB_HYST_F16_ASMI_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Hyst_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Hyst_FLT.h new file mode 100644 index 000000000..cb683ea49 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Hyst_FLT.h @@ -0,0 +1,111 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Hysteresis function +* +*******************************************************************************/ +#ifndef _GFLIB_HYST_FLT_H_ +#define _GFLIB_HYST_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Hyst_FLT_Ci(fltVal, psParam) GFLIB_Hyst_FLT_FCi(fltVal, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltHystOn; /* Value determining the upper threshold */ + float_t fltHystOff; /* Value determining the lower threshold */ + float_t fltOutValOn; /* Value of the output when input is higher than the upper threshold */ + float_t fltOutValOff; /* Value of output when input is lower than lower threshold */ + float_t fltOutState; /* Actual state of the output */ +} GFLIB_HYST_T_FLT; + +/***************************************************************************//*! +* +* @brief Hysteresis function +* +* @param ptr GFLIB_HYST_T_FLT *psParam +* - fltHystOn: Upper threshold +* - fltHystOff: Lower threshold +* - fltOutValOn: Output when input is above f16HystOn +* - fltOutValOff: Output when input is below f16HystOff +* - fltOutState: Output of the function +* +* @param in float_t fltVal +* +* @return N/A +* +* @remarks The function represents a hysteresis (or relay) function. The +* function switches output between the two predefined values. When +* the input is higher than upper threshold fltHystOn, the output +* is high; when the input is below another (lower) threshold +* fltHystOff, the output is low; when the input is between the two, +* the output retains its value. +* +****************************************************************************/ +static inline float_t GFLIB_Hyst_FLT_FCi(float_t fltVal, GFLIB_HYST_T_FLT *psParam) +{ + if(fltVal < psParam->fltHystOff) + { + psParam->fltOutState = psParam->fltOutValOff; + } + else if(fltVal > psParam->fltHystOn) + { + psParam->fltOutState = psParam->fltOutValOn; + } + else + { /* no command to avoid Misra issue */ + } + + return(psParam->fltOutState); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_HYST_FLT_H_ */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Integrator_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Integrator_A32.h new file mode 100644 index 000000000..b139589c6 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Integrator_A32.h @@ -0,0 +1,138 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Integrator with bilinear transformation +* +*******************************************************************************/ +#ifndef _GFLIB_INTEGRATOR_A32_H_ +#define _GFLIB_INTEGRATOR_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_types.h" +#include "mlib.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_IntegratorInit_F16_Ci(f16InitVal, psParam) \ + GFLIB_IntegratorInit_F16_FCi(f16InitVal, psParam) +#define GFLIB_Integrator_F16_Ci(f16InVal, psParam) \ + GFLIB_Integrator_F16_FCi(f16InVal, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + acc32_t a32Gain; /* Integration Gain */ + frac32_t f32IAccK_1; /* Output Value from the previous step */ + frac16_t f16InValK_1; /* Input Value from the previous step */ +} GFLIB_INTEGRATOR_T_A32; + +/***************************************************************************//*! +* @brief The function initializes the actual value of Integrator. +* +* @param ptr GFLIB_INTEGRATOR_T *psParam - Pointer to integrator structure +* GFLIB_INTEGRATOR_T data structure: +* acc32 a32Gain - gain; input parameter +* in the following range: -65536.0 <= a32Gain < 65536.0 +* frac32_t f32IAccK_1 - state variable; fractional part (lower long) +* of integral part at step k-1; +* can be modified outside of the function; +* input/output parameter +* in the following range: -1.0 <= f32IAccK_1 < 1.0 +* frac16_t f16InValK_1 - input value at the step k-1; +* input/output parameter +* in the following range: -1.0 <= f16InVal_1 < 1.0 +* @param in frac16_t f16InitVal - Initial value +* +*******************************************************************************/ +static inline void GFLIB_IntegratorInit_F16_FCi(register frac16_t f16InitVal, + register GFLIB_INTEGRATOR_T_A32 *psParam) +{ + psParam->f32IAccK_1 = MLIB_Conv_F32s(f16InitVal); /* Stores the integral portion */ + psParam->f16InValK_1 = 0; /* Resets the previous step error */ +} + +/***************************************************************************//*! +* +* @brief Scaled integrator with the bilinear transformation. +* +* @param ptr GFLIB_INTEGRATOR_T *psParam - Pointer to integrator structure +* GFLIB_INTEGRATOR_T data structure: +* acc32 a32Gain - gain; input parameter +* in the following range: -65536.0 <= a32Gain < 65536.0 +* frac32_t f32IAccK_1 - state variable; fractional part (lower long) +* of integral part at step k-1; +* can be modified outside of the function; +* input/output parameter +* in the following range: -1.0 <= f32IAccK_1 < 1.0 +* frac16_t f16InValK_1 - input value at the step k-1; +* input/output parameter +* in the following range: -1.0 <= f16InVal_1 < 1.0 +* @param in Frac16 f16InVal - input value +* +* @return out This function returns the integrated value. - frac16_t value <-1;1) +* +* @remarks Integrated input value according to equation: +* +* f32IAccK_1 = [(f16InVal + f16InValK_1) / 2] * a32Gain) + f32IAccK_1 +* f16InValK_1 = f16InVal +* output = (frac16_t)f32IAccK_1 +* +*******************************************************************************/ +static inline frac16_t GFLIB_Integrator_F16_FCi(register frac16_t f16InVal, register GFLIB_INTEGRATOR_T_A32 *psParam) +{ + register acc32_t a32Temp; + register frac32_t f32A1; + frac32_t f32Temp2; + + a32Temp = ((acc32_t)f16InVal + (acc32_t)psParam->f16InValK_1); /* input + previous input */ + f32A1 = psParam->a32Gain * a32Temp; /* multiply by 0.5 because of bilinear transformation */ + + f32Temp2 = MLIB_Add_F32(psParam->f32IAccK_1,f32A1); /* summed with previous output*/ + psParam->f32IAccK_1 = f32Temp2; + psParam->f16InValK_1 = f16InVal; /* set value of previous input for next execution */ + return(frac16_t)MLIB_Conv_F16l(f32Temp2 + 0x8000); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_INTEGRATOR_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Integrator_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Integrator_FLT.h new file mode 100644 index 000000000..3a0310592 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Integrator_FLT.h @@ -0,0 +1,155 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Integrator with bilinear transformation +* +*******************************************************************************/ +#ifndef _GFLIB_INTEGRATOR_FLT_H_ +#define _GFLIB_INTEGRATOR_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_types.h" +#include "mlib_FP.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_IntegratorInit_FLT_Ci(fltInitVal, psParam) \ + GFLIB_IntegratorInit_FLT_FCi(fltInitVal, psParam) +#define GFLIB_Integrator_FLT_Ci(fltInVal, psParam) \ + GFLIB_Integrator_FLT_FCi(fltInVal, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltGain; /* Integration Gain */ + float_t fltIAccK_1; /* Output Value from the previous step */ + float_t fltInValK_1; /* Input Value from the previous step */ + float_t fltUpperLim; /* Upper Limit */ + float_t fltLowerLim; /* Lower Limit */ +} GFLIB_INTEGRATOR_T_FLT; + +/***************************************************************************//*! +* @brief The function initializes the actual value of float Integrator. +* +* @param ptr GFLIB_INTEGRATOR_T *psParam - Pointer to integrator structure +* GFLIB_INTEGRATOR_T data structure: +* float_t gain fltGain - gain; input parameter +* in the float range +* float_t fltIAccK_1 - state variable; fractional part +* (lower long) of integral part at step k-1; +* can be modified outside of the function; +* input/output parameter +* in the float range +* float_t fltInValK_1 - input value at the step k-1; +* input/output parameter in the float range +* float_t fltUpperLim - upper limit +* float_t fltLowerLim - lower limit +* @param in float_t fltInitVal - Initial value +* +*******************************************************************************/ +static inline void GFLIB_IntegratorInit_FLT_FCi(register float_t fltInitVal, + register GFLIB_INTEGRATOR_T_FLT *psParam) +{ + psParam->fltIAccK_1 = fltInitVal; /* Stores the integral portion */ + psParam->fltInValK_1 = 0.0F; /* Resets the previous step error */ +} + +/***************************************************************************//*! +* @brief Float integrator with the bilinear transformation. +* +* @brief The function initializes the actual value of Integrator. +* +* @param ptr GFLIB_INTEGRATOR_T *psParam - Pointer to integrator structure +* GFLIB_INTEGRATOR_T data structure: +* float_t gain fltGain - gain; input parameter +* in the float range +* float_t fltIAccK_1 - state variable; fractional part +* (lower long) of integral part at step k-1; +* can be modified outside of the function; +* input/output parameter +* in the float range +* float_t fltInValK_1 - input value at the step k-1; +* input/output parameter in the float range +* float_t fltUpperLim - upper limit +* float_t fltLowerLim - lower limit +* @param in float_t fltInitVal - Initial value +* +* @return out This function returns the integrated value - float_t value +* +* @remarks Integrated input value according to equation: +* +* fltIAccK_1 = [(fltInVal + fltInValK_1) / 2] * fltGain) + fltIAccK_1 +* fltInValK_1 = fltInVal +* output = fltIAccK_1 +* +*******************************************************************************/ +static inline float_t GFLIB_Integrator_FLT_FCi(register float_t fltInVal, + register GFLIB_INTEGRATOR_T_FLT *psParam) +{ + register float_t fltTemp; + register float_t fltTemp1; + + /* Move frequently used quantities to register */ + fltTemp1 = psParam->fltIAccK_1; + + fltTemp = MLIB_Add_FLT (fltInVal, psParam->fltInValK_1); /* input + previous input */ + fltTemp = MLIB_Mul_FLT (fltTemp, 0.5F); /* multiply by 0.5 because of bilinear transformation */ + + fltTemp = MLIB_Mac_FLT (fltTemp1, psParam->fltGain, fltTemp); /* multiply a32Gain with inputs */ + psParam->fltIAccK_1 = fltTemp; /* store actual value to accumulator */ + psParam->fltInValK_1 = fltInVal; /* set value of previous input for next execution */ + if(fltTemp > psParam->fltUpperLim) + { + return(psParam->fltUpperLim); + } + if(fltTemp < psParam->fltLowerLim) + { + return(psParam->fltLowerLim); + } + + return (fltTemp); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_INTEGRATOR_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Limit_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Limit_F16.h new file mode 100644 index 000000000..4a6687f16 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Limit_F16.h @@ -0,0 +1,87 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Limit functions with 16-bit fractional output +* +*******************************************************************************/ +#ifndef _GFLIB_LIMIT_F16_H_ +#define _GFLIB_LIMIT_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Limit_F16_Ci(f16Val, f16LLim, f16ULim) \ + GFLIB_Limit_F16_FCi(f16Val, f16LLim, f16ULim) + +/***************************************************************************//*! +* +* @brief Limit function +* +* @param in frac16_t f16Val - Argument in <-1;1) in frac16_t +* frac16_t f16LLim - LowerLimit in <-1;1) in frac16_t +* frac16_t f16ULim - UpperLimit in <-1;1) in frac16_t +* +* @return This function returns - frac16_t value <-1;1) +* +* @remarks This function trims the argument according to the upper f16ULim and +* lower f16LLim limits. The upper limit must >= lower limit. +* +****************************************************************************/ +static inline frac16_t GFLIB_Limit_F16_FCi(frac16_t f16Val, + frac16_t f16LLim, frac16_t f16ULim) +{ + if(f16Val > f16ULim) + { + return(f16ULim); + } + if(f16Val < f16LLim) + { + return(f16LLim); + } + return(f16Val); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_LIMIT_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Limit_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Limit_F32.h new file mode 100644 index 000000000..180b54d1c --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Limit_F32.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Limit functions with 32-bit fractional output +* +*******************************************************************************/ +#ifndef _GFLIB_LIMIT_F32_H_ +#define _GFLIB_LIMIT_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Limit_F32_Ci(f32Val, f32LLim, f32ULim) \ + GFLIB_Limit_F32_FCi(f32Val, f32LLim, f32ULim) + +/***************************************************************************//*! +* +* @brief Limit function 32-bit version +* +* @param in frac32_t f32Val - Argument in <-1;1) in frac32_t +* frac32_t f32LLim - Lower limit in <-1;1) in frac32_t +* frac32_t f32ULim - Upper limit in <-1;1) in frac32_t +* +* @return This function returns - frac32_t value <-1;1) +* +* @remarks This function trims the argument according to the upper f32ULim and +* lower f32LLim limits. The upper limit must >= lower limit. +* +****************************************************************************/ +static inline frac32_t GFLIB_Limit_F32_FCi(frac32_t f32Val, + frac32_t f32LLim, frac32_t f32ULim) +{ + if(f32Val > f32ULim) + { + return(f32ULim); + } + if(f32Val < f32LLim) + { + return(f32LLim); + } + + return(f32Val); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_LIMIT_F32_H_ */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Limit_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Limit_FLT.h new file mode 100644 index 000000000..0a82bc8cd --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Limit_FLT.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Limit functions with float output +* +*******************************************************************************/ +#ifndef _GFLIB_LIMIT_FLT_H_ +#define _GFLIB_LIMIT_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Limit_FLT_Ci(fltVal, fltLLim, fltULim) \ + GFLIB_Limit_FLT_FCi(fltVal, fltLLim, fltULim) + +/***************************************************************************//*! +* +* @brief Limit function float version +* +* @param in float_t fltVal - Argument in float_t +* float_t fltLLim - Lower limit in float_t +* float_t fltULim - Upper limit in float_t +* +* @return This function returns - float_t value +* +* @remarks This function trims the argument according to the upper fltULim and +* lower fltLLim limits. The upper limit must >= lower limit. +* +****************************************************************************/ +static inline float_t GFLIB_Limit_FLT_FCi(float_t fltVal, + float_t fltLLim, float_t fltULim) +{ + if(fltVal > fltULim) + { + return(fltULim); + } + if(fltVal < fltLLim) + { + return(fltLLim); + } + + return(fltVal); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_LIMIT_FLT_H_ */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LowerLimit_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LowerLimit_F16.h new file mode 100644 index 000000000..e8a3c0623 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LowerLimit_F16.h @@ -0,0 +1,82 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Lower limit functions with 16-bit fractional output +* +*******************************************************************************/ +#ifndef _GFLIB_LOWERLIMIT_F16_H_ +#define _GFLIB_LOWERLIMIT_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_LowerLimit_F16_Ci(f16Val, f16LLim) \ + GFLIB_LowerLimit_F16_FCi(f16Val, f16LLim) + +/***************************************************************************//*! +* +* @brief Lower limit function +* +* @param in frac16_t f16Val - Argument in <-1;1) in frac16_t +* frac16_t f16LLim - LowerLimit in <-1;1) in frac16_t +* +* @return This function returns - frac16_t value <-1;1) +* +* @remarks This function trims the argument above or equal to lower f16LLim +* limit. +* +****************************************************************************/ +static inline frac16_t GFLIB_LowerLimit_F16_FCi(frac16_t f16Val, frac16_t f16LLim) +{ + if(f16Val < f16LLim) + { + f16Val = f16LLim; + } + return(f16Val); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_LOWERLIMIT_F16_H_ */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LowerLimit_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LowerLimit_F32.h new file mode 100644 index 000000000..fa85a42f4 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LowerLimit_F32.h @@ -0,0 +1,83 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Lower limit functions with 32-bit fractional output +* +*******************************************************************************/ +#ifndef _GFLIB_LOWERLIMIT_F32_H_ +#define _GFLIB_LOWERLIMIT_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_LowerLimit_F32_Ci(f32Val, f32LLim) \ + GFLIB_LowerLimit_F32_FCi(f32Val, f32LLim) + +/***************************************************************************//*! +* +* @brief Lower limit function +* +* @param in frac32_t f32Val - Argument in <-1;1) in frac32_t +* frac32_t f32LLim - LowerLimit in <-1;1) in frac32_t +* +* @return This function returns - frac32_t value <-1;1) +* +* @remarks This function trims the argument above or equal to lower f32LLim +* limit. +* +****************************************************************************/ +static inline frac32_t GFLIB_LowerLimit_F32_FCi(frac32_t f32Val, frac32_t f32LLim) +{ + if(f32Val < f32LLim) + { + f32Val = f32LLim; + } + return(f32Val); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_LOWERLIMIT_F32_H_ */ + + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LowerLimit_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LowerLimit_FLT.h new file mode 100644 index 000000000..9a848370f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LowerLimit_FLT.h @@ -0,0 +1,83 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Lower limit functions with float output +* +*******************************************************************************/ +#ifndef _GFLIB_LOWERLIMIT_FLT_H_ +#define _GFLIB_LOWERLIMIT_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_LowerLimit_FLT_Ci(fltVal, fltLLim) \ + GFLIB_LowerLimit_FLT_FCi(fltVal, fltLLim) + +/***************************************************************************//*! +* +* @brief Lower limit function +* +* @param in float_t fltVal - Argument in float_t +* float_t fltLLim - LowerLimit in float_t +* +* @return This function returns - float_t value +* +* @remarks This function trims the argument above or equal to lower fltLLim +* limit. +* +****************************************************************************/ +static inline float_t GFLIB_LowerLimit_FLT_FCi(float_t fltVal, float_t fltLLim) +{ + if(fltVal < fltLLim) + { + fltVal = fltLLim; + } + return(fltVal); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_LOWERLIMIT_FLT_H_ */ + + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LutPer_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LutPer_F16_Asmi.h new file mode 100644 index 000000000..209eeba8b --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LutPer_F16_Asmi.h @@ -0,0 +1,151 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Periodical look-up table algorithm using linear interpolation +* +*******************************************************************************/ +#ifndef _GFLIB_LUTPER1D_ASMI_F16_H_ +#define _GFLIB_LUTPER1D_ASMI_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_LutPer1D_F16_Asmi(f16X, pf16Table, u16TableSize) GFLIB_LutPer1D_F16_FAsmi(f16X, pf16Table, u16TableSize) + +/***************************************************************************//*! +* +* @brief Periodical look-up table algorithm using linear interpolation +* +* @param ptr *pf16Table +* - Pointer to the table values +* in f16X +* - Argument in <-1;1) in frac16_t +* u16TableSize +* - Size of the look-up table in bit shifts, 3 for 8 values +* +* @return This function returns +* - frac16_t value <-1;1) +* +* @remarks This function calculates the number from the table using interpolation +* of two values in the table. +* The table size must be based on 2^x, i.e. 256 values contains +* the size 8. +* +*******************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_suppress=Pe549 /* Suppresses the Pe549 warning for IAR compiler*/ +#endif +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +inline static frac16_t GFLIB_LutPer1D_F16_FAsmi(frac16_t f16X, const frac16_t *pf16Table, uint16_t u16TableSize) +{ + register frac32_t f32Val1=0, f32Val2=0, f32Val3=0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16X, f16X /* Transforms 16-bit input f16Val to 32-bit */ + add f32Val1, f16X, #32768 /* f32Val1 = 32768 + f16X */ + /* Calculates the number of bit shifts between the 16-bit and table resolution */ + rsb f32Val2, u16TableSize, #16 /* f32Val2 = 16 - u16TableSize */ + /* 16-bit argument is converted to the table table size bits */ + lsr f32Val1, f32Val1, f32Val2 /* f32Val1 = f32Val1 >> f32Val2 */ + /* The exact position between two table points is calculated by keeping the LSBits of the original + * argument, below the table resolution. Then it is shifted to get the frac16_t resolution */ + sub f32Val2, u16TableSize, #1 /* f32Val2 = u16TableSize - 1 */ + lsl f16X, f16X, f32Val2 /* f16X << (u16TableSize - 1) */ + bfc f16X, #15, #17 /* Clears a bit-field */ + ldrsh f32Val2, [pf16Table, f32Val1, lsl #1]/* Loads y1 */ + add f32Val1, f32Val1, #1 /* f32Val1 = f32Val1 + 1 */ + mov f32Val3, #1 /* f32Val3 = 1 */ + lsl f32Val3, f32Val3, u16TableSize /* f32Val3 = 1 << u16TableSize */ + sub f32Val3, f32Val3, #1 /* f32Val3 = (1 << u16TableSize) - 1 */ + and f32Val3, f32Val3, f32Val1 /* f32Val3 = f32Val3 & f32Val1 */ + ldrsh f32Val3, [pf16Table, f32Val3, lsl #1]/* Loads y2 */ + /* Subtracts two table values and interpolates, the next value to the previous is +1. */ + sub f32Val3, f32Val3, f32Val2 /* y2 - y1 */ + mul f16X, f32Val3, f16X /* (y2 - y1) * x */ + add f16X, f32Val2, f16X, asr # 15 }; /* result = y1 + (y2 - y1) * x */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "add %3, %0, #32768 \n" /* f32Val1 = 32768 + f16X */ + /* Calculates the number of bit shifts between the 16-bit and table resolution */ + "rsb %4, %2, #16 \n" /* f32Val2 = 16 - u16TableSize */ + /* 16-bit argument is converted to the table table size bits */ + "lsr %3, %3, %4 \n" /* f32Val1 = f32Val1 >> f32Val2 */ + /* The exact position between two table points is calculated by keeping the LSBits of the original + * argument, below the table resolution. Then it is shifted to get the frac16_t resolution */ + "sub %4, %2, #1 \n" /* f32Val2 = u16TableSize - 1 */ + "lsl %0, %0, %4 \n" /* f16X << (u16TableSize - 1) */ + "bfc %0, #15, #17 \n" /* Clears a bit-field */ + "ldrsh %4, [%1, %3, lsl #1] \n" /* Loads y1 */ + "add %3, %3, #1 \n" /* f32Val1 = f32Val1 + 1 */ + "mov %5, #1 \n" /* f32Val3 = 1 */ + "lsl %5, %5, %2 \n" /* f32Val3 = 1 << u16TableSize */ + "sub %5, %5, #1 \n" /* f32Val3 = (1 << u16TableSize) - 1 */ + "and %5, %5, %3 \n" /* f32Val3 = f32Val3 & f32Val1 */ + "ldrsh %5, [%1, %5, lsl #1] \n" /* Loads y2 */ + /* Subtracts two table values and interpolates, the next value to the previous is +1. */ + "sub %5, %5, %4 \n" /* y2 - y1 */ + "mul %0, %5, %0 \n" /* (y2 - y1) * x */ + "add %0, %4, %0, asr # 15 \n" /* result = y1 + (y2 - y1) * x */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16X), "+l"(pf16Table), "+l"(u16TableSize), "+l"(f32Val1), "+l"(f32Val2), "+l"(f32Val3):); + #endif + + return f16X; +} +RTCESL_INLINE_OPTIM_RESTORE + + +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_default=Pe549 +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_LUTPER1D_ASMI_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LutPer_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LutPer_F32.h new file mode 100644 index 000000000..e3a8ae453 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LutPer_F32.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Periodical look-up table algorithm using linear interpolation +* +*******************************************************************************/ +#ifndef _GFLIB_LUTPER_F32_H_ +#define _GFLIB_LUTPER_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_LutPer1D_F32_C(f32X, pf32Table, u16TableSize) \ + GFLIB_LutPer1D_F32_FC(f32X, pf32Table, u16TableSize) + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac32_t GFLIB_LutPer1D_F32_FC(frac32_t f32X, + const frac32_t *pf32Table, + uint16_t u16TableSize); + + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_LUTPER_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LutPer_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LutPer_FLT.h new file mode 100644 index 000000000..6ca34ef0e --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_LutPer_FLT.h @@ -0,0 +1,101 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Periodic look-up table algorithm using linear interpolation +* +*******************************************************************************/ +#ifndef _GFLIB_LUTPER1D_FLT_H_ +#define _GFLIB_LUTPER1D_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_LutPer1D_FLT_C(fltX, pfltTable, psParam) \ + GFLIB_LutPer1D_FLT_FC( fltX, pfltTable, psParam) +#define GFLIB_LutPer1DInit_FLT_Ci(fltMin, fltMax, pfltTable, psParam) \ + GFLIB_LutPer1DInit_FLT_FCi(fltMin, fltMax, pfltTable, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltMin; /* Assign the first value of X-values, set by user using Init function */ + float_t fltMax; /* Assign the last value of X-values, set by user using Init function */ + float_t fltIntInv; /* Table inverse interval in float, calculated by GFLIB_Lut1DInit_FLT*/ + uint16_t u16TableSize; /* Real table size (no shift) from interval: <2; 65535> */ +} GFLIB_LUTPER1D_T_FLT; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern float_t GFLIB_LutPer1D_FLT_FC(float_t fltX, + const float_t *pfltTable, + const GFLIB_LUTPER1D_T_FLT *psParam); + +/***************************************************************************//*! +* @brief The function initializes internal variables for constants of periodic LUT +* interpolation function +* +* @params in float_t fltMin - the first value of X-values +* in float_t fltMax - the last value of X-values +* in uint16_t ui16TabSize - Size of periodic LUT table +* ptr GFLIB_LUTPER1D_T_FLT *psParam - Pointer to parameter structure +* +* @return N/A +* +*******************************************************************************/ +static inline void GFLIB_LutPer1DInit_FLT_FCi(float_t fltMin, float_t fltMax, + uint16_t u16TableSize, + GFLIB_LUTPER1D_T_FLT *psParam) +{ + psParam->fltIntInv = MLIB_Div_FLT((float_t)(u16TableSize),MLIB_Sub_FLT(fltMax, fltMin)); + psParam->u16TableSize = u16TableSize; + psParam->fltMin = fltMin; + psParam->fltMax = fltMax; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_LUTPER1D_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Lut_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Lut_F16_Asmi.h new file mode 100644 index 000000000..cd9e98c44 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Lut_F16_Asmi.h @@ -0,0 +1,143 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Look-up table algorithm using linear interpolation +* +*******************************************************************************/ +#ifndef _GFLIB_LUT1D_ASMI_F16_H_ +#define _GFLIB_LUT1D_ASMI_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Lut1D_F16_Asmi(f16X, pf16Table, u16TableSize) \ + GFLIB_Lut1D_F16_FAsmi(f16X, pf16Table, u16TableSize) + +/***************************************************************************//*! +* +* @brief Look-up table algorithm using linear interpolation +* +* @param ptr *pf16Table +* - Pointer to the table values +* in f16X +* - Argument in <-1;1) in frac16_t +* u16TableSize +* - Size of the look-up table in bit shifts, 3 for 8 values +* +* @return This function returns +* - frac16_t value <-1;1) +* +* @remarks This function calculates the number from the table using interpolation +* of two values in the table. +* The table size must be based on 2^x+1, i.e. 257 values contains +* the size 8. +* +*******************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_suppress=Pe549 /* Suppresses the Pe549 warning for IAR compiler*/ +#endif +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +inline static frac16_t GFLIB_Lut1D_F16_FAsmi(frac16_t f16X, const frac16_t *pf16Table, uint16_t u16TableSize) +{ + register frac32_t f32Val1=0, f32Val2=0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16X, f16X /* Transforms 16-bit input f16Val to 32-bit */ + sub u16TableSize, u16TableSize, #1 /* u16TableSize = u16TableSize - 1 */ + movs f32Val1, #2 /* f32Val1 = 2 */ + lsl f32Val1, f32Val1, u16TableSize /* f32Val1 << u16TableSize */ + /* Extract the fractional part of the input abscissa */ + lsl f32Val2, f16X, u16TableSize /* f32Val2 = f16X << u16TableSize */ + bfc f32Val2, #15, #17 /* Clears a bit-field */ + add pf16Table, pf16Table, f32Val1 /* pf16Table = pf16Table + f32Val1 */ + rsb f32Val1, u16TableSize, #15 /* f32Val1 = 15 - u16TableSize */ + asr f16X, f16X, f32Val1 /* f16X >> f32Val1 */ + add pf16Table, pf16Table, f16X, lsl #1 /* pf16Table = pf16Table + f16X *2 */ + /* Read interpolated data */ + ldrsh u16TableSize, [pf16Table], #2 /* Loads y1 */ + ldrsh f32Val1, [pf16Table] /* Loads y2 */ + /* Perform the actual interpolation with 16-bit accuracy */ + sub f16X, f32Val1, u16TableSize /* y2 - y1 */ + mul f16X, f16X, f32Val2 /* (y2 - y1) * x */ + add f16X, u16TableSize, f16X, asr # 15 };/* result = y1 + (y2 - y1) * x */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "sub %2, %2, #1 \n" /* u16TableSize = u16TableSize - 1 */ + "movs %3, #2 \n" /* f32Val1 = 2 */ + "lsl %3, %3, %2 \n" /* f32Val1 << u16TableSize */ + /* Extract the fractional part of the input abscissa */ + "lsl %4, %0, %2 \n" /* f32Val2 = f16X << u16TableSize */ + "bfc %4, #15, #17 \n" /* Clears a bit-field */ + "add %1, %1, %3 \n" /* pf16Table = pf16Table + f32Val1 */ + "rsb %3, %2, #15 \n" /* f32Val1 = 15 - u16TableSize */ + "asr %0, %0, %3 \n" /* f16X >> f32Val1 */ + "add %1, %1, %0, lsl #1 \n" /* pf16Table = pf16Table + f16X *2 */ + /* Read interpolated data */ + "ldrsh %2, [%1], #2 \n" /* Loads y1 */ + "ldrsh %3, [%1] \n" /* Loads y2 */ + /* Perform the actual interpolation with 16-bit accuracy */ + "sub %0, %3, %2 \n" /* y2 - y1 */ + "mul %0, %0, %4 \n" /* (y2 - y1) * x */ + "add %0, %2, %0, asr # 15 \n"/* result = y1 + (y2 - y1) * x */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16X), "+l"(pf16Table), "+l"(u16TableSize), "+l"(f32Val1), "+l"(f32Val2):); + #endif + + return f16X; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_default=Pe549 +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_LUT1D_ASMI_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Lut_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Lut_F32.h new file mode 100644 index 000000000..3e05c9b90 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Lut_F32.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Look-up table algorithm using linear interpolation +* +*******************************************************************************/ +#ifndef _GFLIB_Lut1D_F32_H_ +#define _GFLIB_Lut1D_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Lut1D_F32_C(f32X, pf32Table, u16TableSize) \ + GFLIB_Lut1D_F32_FC(f32X, pf32Table, u16TableSize) + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac32_t GFLIB_Lut1D_F32_FC(frac32_t f32X, + const frac32_t *pf32Table, + uint16_t u16TableSize); + + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_Lut1D_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Lut_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Lut_FLT.h new file mode 100644 index 000000000..94b4b8ea9 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Lut_FLT.h @@ -0,0 +1,101 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Look-up table algorithm using linear interpolation +* +*******************************************************************************/ +#ifndef _GFLIB_LUT1D_FLT_H_ +#define _GFLIB_LUT1D_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Lut1D_FLT_C(fltX, pfltTable, psParam) \ + GFLIB_Lut1D_FLT_FC(fltX, pfltTable, psParam) +#define GFLIB_Lut1DInit_FLT_Ci(fltMin, fltMax, pfltTable, psParam) \ + GFLIB_Lut1DInit_FLT_FCi(fltMin, fltMax, pfltTable, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltMin; /* Assign the first value of X-values, set by user using Init function */ + float_t fltMax; /* Assign the last value of X-values, set by user using Init function */ + float_t fltIntInv; /* Table inverse interval in float, calculated by GFLIB_Lut1DInit_FLT*/ + uint16_t u16TableSize; /* Real table size (no shift) from interval: <2; 65535> */ +} GFLIB_LUT1D_T_FLT; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern float_t GFLIB_Lut1D_FLT_FC(float_t fltX, + const float_t *pfltTable, + const GFLIB_LUT1D_T_FLT *psParam); + +/***************************************************************************//*! +* @brief The function initializes internal variables for constants of LUT +* interpolation function +* +* @params in float_t fltMin - the first value of X-values +* in float_t fltMax - the last value of X-values +* in uint16_t ui16TabSize - Size of LUT table +* ptr GFLIB_LUT1D_T_FLT *psParam - Pointer to parameter structure +* +* @return N/A +* +*******************************************************************************/ +static inline void GFLIB_Lut1DInit_FLT_FCi(float_t fltMin, float_t fltMax, + uint16_t u16TableSize, + GFLIB_LUT1D_T_FLT *psParam) +{ + psParam->fltIntInv = MLIB_Div_FLT(((float_t)u16TableSize-1.0F),MLIB_Sub_FLT(fltMax, fltMin)); + psParam->u16TableSize = u16TableSize; + psParam->fltMin = fltMin; + psParam->fltMax = fltMax; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_LUT1D_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Ramp_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Ramp_F16.h new file mode 100644 index 000000000..a67357a9b --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Ramp_F16.h @@ -0,0 +1,135 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Ramp +* +*******************************************************************************/ +#ifndef _GFLIB_RAMP_F16_H_ +#define _GFLIB_RAMP_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_types.h" +#include "mlib.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_RampInit_F16_Ci(f16InitVal, psParam) \ + GFLIB_RampInit_F16_FCi(f16InitVal, psParam) +#define GFLIB_Ramp_F16_Ci(f16Target, psParam) \ + GFLIB_Ramp_F16_FCi(f16Target, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac16_t f16RampUp; /* Ramp-up increment */ + frac16_t f16RampDown; /* Ramp-down increment */ + frac16_t f16State; /* Previous ramp value */ +} GFLIB_RAMP_T_F16; + +/***************************************************************************//*! +* @brief The function initializes the actual value of Ramp_F16. +* +* @param ptr GFLIB_RAMP_T_F16 *psParam +* - rampUp: Ramp-up increment +* - rampDown: Ramp-down increment +* - state: Actual state +* +* @param in frac16_t f16InitVal - Initial value +*******************************************************************************/ +static inline void GFLIB_RampInit_F16_FCi(frac16_t f16InitVal, GFLIB_RAMP_T_F16 *psParam) +{ + psParam->f16State = f16InitVal; +} + +/***************************************************************************//*! +* @brief Ramp function +* +* @param ptr GFLIB_RAMP_T_F16 *psParam +* - rampUp: Ramp-up increment +* - rampDown: Ramp-down increment +* - state: Actual state +* @param in frac16_t f16Target - Desired value in <-1;1) in frac16_t +* +* @return This function returns - frac16_t value <-1;1) +* +* @remarks This function ramps the value from the f16State value up/down to +* the f16Target value using the up/down increments defined in +* the psParam structure. +*******************************************************************************/ +static inline frac16_t GFLIB_Ramp_F16_FCi(frac16_t f16Target, GFLIB_RAMP_T_F16 *psParam) +{ + register frac16_t f16Result = 0; /* Result of the ramp */ + + if (f16Target > psParam->f16State) /* If desired > actual */ + { + /* The algorithm adds the rampUp to actual */ + f16Result = (int16_t)(uint16_t)MLIB_AddSat_F16(psParam->f16State, psParam -> f16RampUp); + if (f16Result > f16Target) /* If it overshoots */ + { + f16Result = f16Target; /* it uses the desired */ + } + } + + if (f16Target < psParam->f16State) /* If desired < actual */ + { + /* The algorithm subtracts the rampDown from actual */ + f16Result = (int16_t)(uint16_t)MLIB_SubSat_F16(psParam->f16State, psParam -> f16RampDown); + if (f16Result < f16Target) /* If it undershoots */ + { + f16Result = f16Target; /* it uses the desired */ + } + } + + if (f16Target == psParam->f16State) + { + f16Result = f16Target; + } + + psParam->f16State = f16Result; + return(f16Result); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_RAMP_F16_H_*/ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Ramp_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Ramp_F32.h new file mode 100644 index 000000000..bb1ac29fc --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Ramp_F32.h @@ -0,0 +1,135 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Ramp +* +*******************************************************************************/ +#ifndef _GFLIB_RAMP_F32_H_ +#define _GFLIB_RAMP_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +******************************************************************************/ +#define GFLIB_RampInit_F32_Ci(f32InitVal, psParam) \ + GFLIB_RampInit_F32_FCi(f32InitVal, psParam) +#define GFLIB_Ramp_F32_Ci(f32Target, psParam) \ + GFLIB_Ramp_F32_FCi(f32Target, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac32_t f32RampUp; /* Ramp-up increment */ + frac32_t f32RampDown; /* Ramp-down increment */ + frac32_t f32State; /* Previous ramp value */ +} GFLIB_RAMP_T_F32; + +/***************************************************************************//*! +* @brief The function initializes the actual value of Ramp_F32. +* +* @param ptr GFLIB_RAMP_T_F32 *psParam +* - rampUp: Ramp-up increment +* - rampDown: Ramp-down increment +* - state: Actual state +* +* @param in frac32_t f32InitVal - Initial value +*******************************************************************************/ +static inline void GFLIB_RampInit_F32_FCi(frac32_t f32InitVal, GFLIB_RAMP_T_F32 *psParam) +{ + psParam->f32State = f32InitVal; +} + +/***************************************************************************//*! +* @brief Ramp function +* +* @param ptr GFLIB_RAMP_T_F32 *psParam +* - rampUp: Ramp-up increment +* - rampDown: Ramp-down increment +* - state: Actual state +* @param in frac32_t f32Target - Desired value in <-1;1) in frac32_t +* +* @return This function returns - frac32_t value <-1;1) +* +* @remarks This function ramps the value from the f32State value up/down to +* the f32Target value using the up/down increments defined in +* the psParam structure. +*******************************************************************************/ +static inline frac32_t GFLIB_Ramp_F32_FCi(frac32_t f32Target, GFLIB_RAMP_T_F32 *psParam) +{ + register frac32_t f32Result = 0; /* Result of the ramp */ + + if (f32Target > psParam->f32State) /* If desired > actual */ + { + /* The algorithm adds the rampUp to actual */ + f32Result = MLIB_AddSat_F32(psParam->f32State, psParam -> f32RampUp); + if (f32Result > f32Target) /* If it overshoots */ + { + f32Result = f32Target; /* it uses the desired */ + } + } + + if (f32Target < psParam->f32State) /* If desired < actual */ + { + /* The algorithm subtracts the rampDown from actual */ + f32Result = MLIB_SubSat_F32(psParam->f32State, psParam -> f32RampDown); + if (f32Result < f32Target) /* If it undershoots */ + { + f32Result = f32Target; /* it uses the desired */ + } + } + + if (f32Target == psParam->f32State) + { + f32Result = f32Target; + } + + psParam->f32State = f32Result; + return(f32Result); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_RAMP_F32_H */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Ramp_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Ramp_FLT.h new file mode 100644 index 000000000..0b45681e5 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Ramp_FLT.h @@ -0,0 +1,132 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Ramp +* +*******************************************************************************/ +#ifndef _GFLIB_RAMP_FLT_H_ +#define _GFLIB_RAMP_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_types.h" +#include "mlib_FP.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_RampInit_FLT_Ci(fltInitVal, psParam) \ + GFLIB_RampInit_FLT_FCi(fltInitVal, psParam) +#define GFLIB_Ramp_FLT_Ci(fltTarget, psParam) \ + GFLIB_Ramp_FLT_FCi(fltTarget, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltRampUp; /* Ramp-up increment */ + float_t fltRampDown; /* Ramp-down increment */ + float_t fltState; /* Previous ramp value */ +} GFLIB_RAMP_T_FLT; + +/***************************************************************************//*! +* @brief The function initializes the actual value of Ramp_FLT. +* +* @param ptr GFLIB_RAMP_T_FLT *psParam +* - rampUp: Ramp-up increment +* - rampDown: Ramp-down increment +* - state: Actual state +* +* @param in float_t fltInitVal - Initial value +*******************************************************************************/ +static inline void GFLIB_RampInit_FLT_FCi(float_t fltInitVal, GFLIB_RAMP_T_FLT *psParam) +{ + psParam->fltState = fltInitVal; +} + +/***************************************************************************//*! +* @brief Ramp function +* +* @param ptr GFLIB_RAMP_T_FLT *psParam +* - rampUp: Ramp-up increment +* - rampDown: Ramp-down increment +* - state: Actual state +* @param in float_t fltTarget - Desired value in float_t +* +* @return This function returns - float_t value +* +* @remarks This function ramps the value from the fltState value up/down to +* the fltTarget value using the up/down increments defined in +* the psParam structure. +*******************************************************************************/ +static inline float_t GFLIB_Ramp_FLT_FCi(float_t fltTarget, GFLIB_RAMP_T_FLT *psParam) +{ + register float_t fltResult; /* Result of the ramp */ + + if (fltTarget > psParam->fltState) /* If desired > actual */ + { + /* The algorithm adds the rampUp to actual */ + fltResult = MLIB_Add_FLT(psParam->fltState, psParam -> fltRampUp); + if (fltResult > fltTarget) /* If it overshoots */ + { + fltResult = fltTarget; /* it uses the desired */ + } + } + else if (fltTarget < psParam->fltState) /* If desired < actual */ + { + /* The algorithm subtracts the rampDown from actual */ + fltResult = MLIB_Sub_FLT(psParam->fltState, psParam -> fltRampDown); + if (fltResult < fltTarget) /* If it undershoots */ + { + fltResult = fltTarget; /* it uses the desired */ + } + } + else + { + fltResult = fltTarget; + } + psParam->fltState = fltResult; + return(fltResult); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_RAMP_FLT_H */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_SinCos_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_SinCos_F32.h new file mode 100644 index 000000000..7e695e17e --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_SinCos_F32.h @@ -0,0 +1,86 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Sine, Cosine +* +*******************************************************************************/ +#ifndef _GFLIB_SINCOS_A32_H_ +#define _GFLIB_SINCOS_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Sin_F16_Asm(f16Angle) GFLIB_Sin_F16_FAsm(f16Angle, &gsSinCoef) +#define GFLIB_Cos_F16_Asmi(f16Angle) GFLIB_Cos_F16_FAsmi(f16Angle) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac32_t f32A[5]; /* Array of fractional coefficients */ +} GFLIB_SIN_T_F32; + +/******************************************************************************* +* Global variables +*******************************************************************************/ +extern GFLIB_CONST GFLIB_SIN_T_F32 gsSinCoef; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t GFLIB_Sin_F16_FAsm(frac16_t f16Angle, GFLIB_CONST GFLIB_SIN_T_F32 *const psParam); + +/***************************************************************************//*! +* Cosine is calculated using the GFLIB_Sin_F16 function summed with FRAC(0.5) +*******************************************************************************/ +static inline frac16_t GFLIB_Cos_F16_FAsmi(register frac16_t f16Angle) +{ + return(GFLIB_Sin_F16_Asm((f16Angle +(frac16_t)16384))); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_SINCOS_A32_H_ */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_SinCos_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_SinCos_FLT.h new file mode 100644 index 000000000..d7951df59 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_SinCos_FLT.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Sine, Cosine +* +*******************************************************************************/ +#ifndef _GFLIB_SINCOS_FLT_H_ +#define _GFLIB_SINCOS_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Sin_FLT_C(fltAngle) GFLIB_Sin_FLT_FC(fltAngle, &gfltSinCoef) +#define GFLIB_Sin_FLTa_C(a32AngleExt) GFLIB_Sin_FLTa_FC(a32AngleExt) +#define GFLIB_Cos_FLT_C(fltAngle) GFLIB_Cos_FLT_FC(fltAngle, &gfltCosCoef) +#define GFLIB_Cos_FLTa_C(a32AngleExt) GFLIB_Cos_FLTa_FC(a32AngleExt) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltA[3]; /* array of coefficients */ +} GFLIB_SIN_T_FLT; + +typedef struct +{ + float_t fltA[3]; /* array of coefficients */ +} GFLIB_COS_T_FLT; + +/******************************************************************************* +* Global variables +*******************************************************************************/ +extern GFLIB_CONST GFLIB_SIN_T_FLT gfltSinCoef; +extern GFLIB_CONST GFLIB_COS_T_FLT gfltCosCoef; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern float_t GFLIB_Sin_FLT_FC(float_t fltAngle, GFLIB_CONST GFLIB_SIN_T_FLT *const psParam); +extern float_t GFLIB_Sin_FLTa_FC(acc32_t a32AngleExt); +extern float_t GFLIB_Cos_FLT_FC(float_t fltAngle, GFLIB_CONST GFLIB_COS_T_FLT *const psParam); +extern float_t GFLIB_Cos_FLTa_FC(acc32_t a32AngleExt); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_SINCOS_FLT_H_ */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Sqrt_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Sqrt_F16.h new file mode 100644 index 000000000..22280661f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Sqrt_F16.h @@ -0,0 +1,98 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Square root +* +*******************************************************************************/ + +#ifndef _GFLIB_SQRT_F16_H_ +#define _GFLIB_SQRT_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_types.h" +#include "mlib.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Sqrt_F16_C(f16Val) GFLIB_Sqrt_F16_FC(f16Val, &gsSqrtTable_F32) + +/****************************************************************************** +* Types +******************************************************************************/ + +/* Polynom table line */ +typedef struct +{ + frac16_t f16Dummy; + frac16_t f16XkOffset; + frac16_t f16PolyCoef[5]; + frac16_t f16NYScl; + frac32_t f32YkOffset; +} GFLIB_SQRT_ROW_T_F32; + +/* Polynom table line pointer */ +typedef struct +{ + GFLIB_SQRT_ROW_T_F32 *psLine; +} GFLIB_SQRT_OFFSET_T_F32; + +/* Polynom table */ +typedef struct +{ + GFLIB_SQRT_OFFSET_T_F32 sLine1; + GFLIB_SQRT_OFFSET_T_F32 sLine2; + GFLIB_SQRT_OFFSET_T_F32 sLine3; + GFLIB_SQRT_ROW_T_F32 sInterval1; + GFLIB_SQRT_ROW_T_F32 sInterval2; + GFLIB_SQRT_ROW_T_F32 sInterval3; +} GFLIB_SQRT_TABLE_T_F32; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t GFLIB_Sqrt_F16_FC(frac16_t f16Val, + const GFLIB_SQRT_TABLE_T_F32 *psParam); +extern GFLIB_SQRT_TABLE_T_F32 gsSqrtTable_F32; + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_SQRT_F16_H_ */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Sqrt_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Sqrt_F32.h new file mode 100644 index 000000000..73eaa4245 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Sqrt_F32.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Square root +* +*******************************************************************************/ + +#ifndef _GFLIB_SQRT_F32_H_ +#define _GFLIB_SQRT_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_types.h" +#include "mlib.h" +#include "GFLIB_Sqrt_F16.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Sqrt_F16l_C(f32Val) GFLIB_Sqrt_F16l_FC(f32Val, &gsSqrtTable_F32) + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t GFLIB_Sqrt_F16l_FC(frac32_t f32Val, + const GFLIB_SQRT_TABLE_T_F32 *psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_SQRT_F32_H_ */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Sqrt_FLT_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Sqrt_FLT_Asmi.h new file mode 100644 index 000000000..717149bf5 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Sqrt_FLT_Asmi.h @@ -0,0 +1,97 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Square root +* +*******************************************************************************/ +#ifndef _MLIB_SQRT_FLT_ASM_H_ +#define _MLIB_SQRT_FLT_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_types.h" +#include "mlib_FP.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Sqrt_FLT_Asmi(fltVal) GFLIB_Sqrt_FLT_FAsmi(fltVal) + +/**************************************************************************** +* Inline functions +****************************************************************************/ + + +/***************************************************************************//*! +* @brief This function returns the square root of input value. +* +* @param in fltVal - The input value. +* +* @return The function returns the square root of the input value. The +* return value is float range. If input is <= 0, then the function +* returns 0. The function uses VSQRT instruction in Cortex M FPU. +* +* @remarks The function uses VSQRT instruction in Cortex M FPU. +* +****************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline float_t GFLIB_Sqrt_FLT_FAsmi(register float_t fltVal) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ vsqrt.f32 fltVal, fltVal }; + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vsqrt.f32 %0, %0 \n" + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+t"(fltVal):); + #endif + + return fltVal; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SQRT_FLT_ASM_H_*/ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Tan_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Tan_F32.h new file mode 100644 index 000000000..8d7875247 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Tan_F32.h @@ -0,0 +1,81 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Tangent +* +*******************************************************************************/ +#ifndef _GFLIB_TAN_F32_H_ +#define _GFLIB_TAN_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Tan_F16_C(f16Angle) GFLIB_Tan_F16_FC(f16Angle, &gsTanCoef) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + const frac32_t f32A[4]; +} GFLIB_TAN_COEF_T_F32; + +typedef struct +{ + GFLIB_TAN_COEF_T_F32 GFLIB_TAN_SECTOR_F32[8]; +} GFLIB_TAN_T_F32; + +/******************************************************************************* +* Global variables +*******************************************************************************/ +extern GFLIB_CONST GFLIB_TAN_T_F32 gsTanCoef; +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac16_t GFLIB_Tan_F16_FC(frac16_t f16Angle, + GFLIB_CONST GFLIB_TAN_T_F32 *const pParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_TAN_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Tan_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Tan_FLT.h new file mode 100644 index 000000000..1719a7dd1 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_Tan_FLT.h @@ -0,0 +1,80 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Tangent +* +*******************************************************************************/ +#ifndef GFLIB_TAN_FLT_H +#define GFLIB_TAN_FLT_H + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Tan_FLT_C(fltAngle) GFLIB_Tan_FLT_FC(fltAngle, &fltgflibTanCoef) +#define GFLIB_Tan_FLTa_C(a32AngleExt) GFLIB_Tan_FLTa_FC(a32AngleExt) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + const float_t fltA[4]; +} GFLIB_TAN_T_FLT; + +/******************************************************************************* +* Global variables +*******************************************************************************/ +extern GFLIB_CONST GFLIB_TAN_T_FLT fltgflibTanCoef; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern float_t GFLIB_Tan_FLT_FC(float_t fltAngle, + GFLIB_CONST GFLIB_TAN_T_FLT *const psParam); +extern float_t GFLIB_Tan_FLTa_FC(acc32_t a32AngleExt); + +#if defined(__cplusplus) +} +#endif + +#endif /* GFLIB_TAN_FLT_H */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_UpperLimit_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_UpperLimit_F16.h new file mode 100644 index 000000000..95fcbe8e4 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_UpperLimit_F16.h @@ -0,0 +1,82 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Upper limit functions with 16-bit fractional output +* +*******************************************************************************/ +#ifndef _GFLIB_UPPERLIMIT_F16_H_ +#define _GFLIB_UPPERLIMIT_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib_types.h" +#include "mlib.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_UpperLimit_F16_Ci(f16Val, f16ULim) \ + GFLIB_UpperLimit_F16_FCi(f16Val, f16ULim) + +/***************************************************************************//*! +* +* @brief Upper limit function +* +* @param in frac16_t f16Val - Argument in <-1;1) in frac16_t +* frac16_t f16ULim - UpperLimit in <-1;1) in frac16_t +* +* @return This function returns - frac16_t value <-1;1) +* +* @remarks This function trims the argument under or equal to upper f16ULim +* limit. +* +****************************************************************************/ +static inline frac16_t GFLIB_UpperLimit_F16_FCi(frac16_t f16Val,frac16_t f16ULim) +{ + if(f16Val > f16ULim) + { + f16Val = f16ULim; + } + return(f16Val); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_UPPERLIMIT_F16_H_ */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_UpperLimit_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_UpperLimit_F32.h new file mode 100644 index 000000000..8a34afc0d --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_UpperLimit_F32.h @@ -0,0 +1,81 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Upper limit functions with 32-bit fractional output +* +*******************************************************************************/ +#ifndef _GFLIB_UPPERLIMIT_F32_H_ +#define _GFLIB_UPPERLIMIT_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_UpperLimit_F32_Ci(f32Val, f32ULim) \ + GFLIB_UpperLimit_F32_FCi(f32Val, f32ULim) + +/***************************************************************************//*! +* +* @brief Upper limit function +* +* @param in frac32_t f32Val - Argument in <-1;1) in frac32_t +* frac32_t f32ULim - LowerLimit in <-1;1) in frac32_t +* +* @return This function returns - frac32_t value <-1;1) +* +* @remarks This function trims the argument under or equal to upper f32ULim +* limit. +* +****************************************************************************/ +static inline frac32_t GFLIB_UpperLimit_F32_FCi(frac32_t f32Val, frac32_t f32ULim) +{ + if(f32Val > f32ULim) + { + f32Val = f32ULim; + } + return(f32Val); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_UPPERLIMIT_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_UpperLimit_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_UpperLimit_FLT.h new file mode 100644 index 000000000..d65aee6bf --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_UpperLimit_FLT.h @@ -0,0 +1,84 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Upper limit functions with float output +* +*******************************************************************************/ +#ifndef _GFLIB_UPPERLIMIT_FLT_H_ +#define _GFLIB_UPPERLIMIT_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_UpperLimit_FLT_Ci(fltVal, fltULim) \ + GFLIB_UpperLimit_FLT_FCi(fltVal, fltULim) + +/***************************************************************************//*! +* +* @brief Upper limit function +* +* @param in float_t fltVal - Argument in float_t +* float_t fltULim - UpperLimit in float_t +* +* @return This function returns - float_t value +* +* @remarks This function trims the argument under or equal to upper fltULim +* limit. +* +****************************************************************************/ +static inline float_t GFLIB_UpperLimit_FLT_FCi(float_t fltVal, float_t fltULim) +{ + if(fltVal > fltULim) + { + fltVal = fltULim; + } + return(fltVal); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_UPPERLIMIT_FLT_H_ */ + + + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_VectorLimit_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_VectorLimit_F16.h new file mode 100644 index 000000000..3d278719c --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_VectorLimit_F16.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Vector limit functions +* +*******************************************************************************/ +#ifndef _GFLIB_VECTORLIMIT_F16_H_ +#define _GFLIB_VECTORLIMIT_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_VectorLimit_F16_C(psVectorIn, f16Lim, psVectorOut) \ + GFLIB_VectorLimit_F16_FC(psVectorIn, f16Lim, psVectorOut) +#define GFLIB_VectorLimit1_F16_C(psVectorIn, f16Lim, psVectorOut) \ + GFLIB_VectorLimit1_F16_FC(psVectorIn, f16Lim, psVectorOut) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac16_t f16A; /* First argument */ + frac16_t f16B; /* Second argument */ +} GFLIB_VECTORLIMIT_T_F16; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern bool_t GFLIB_VectorLimit_F16_FC(const GFLIB_VECTORLIMIT_T_F16 *psVectorIn, + frac16_t f16Lim, + GFLIB_VECTORLIMIT_T_F16 *psVectorOut); +extern bool_t GFLIB_VectorLimit1_F16_FC(const GFLIB_VECTORLIMIT_T_F16 *psVectorIn, + frac16_t f16Lim, + GFLIB_VECTORLIMIT_T_F16 *psVectorOut); +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_VECTORLIMIT_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_VectorLimit_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_VectorLimit_FLT.h new file mode 100644 index 000000000..1a715e5cc --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/GFLIB_VectorLimit_FLT.h @@ -0,0 +1,80 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Vector limit functions with float output +* +*******************************************************************************/ +#ifndef _GFLIB_VECTORLIMIT_FLT_H_ +#define _GFLIB_VECTORLIMIT_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gflib_FP.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_VectorLimit_FLT_C(psVectorIn, fltLim, psVectorOut) \ + GFLIB_VectorLimit_FLT_FC(psVectorIn, fltLim, psVectorOut) +#define GFLIB_VectorLimit1_FLT_C(psVectorIn, fltLim, psVectorOut) \ + GFLIB_VectorLimit1_FLT_FC(psVectorIn, fltLim, psVectorOut) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + float_t fltA; /* First argument */ + float_t fltB; /* Second argument */ +} GFLIB_VECTORLIMIT_T_FLT; + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern bool_t GFLIB_VectorLimit_FLT_FC(const GFLIB_VECTORLIMIT_T_FLT *psVectorIn, + float_t fltLim, + GFLIB_VECTORLIMIT_T_FLT *psVectorOut); +extern bool_t GFLIB_VectorLimit1_FLT_FC(const GFLIB_VECTORLIMIT_T_FLT *psVectorIn, + float_t fltLim, + GFLIB_VECTORLIMIT_T_FLT *psVectorOut); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_ASIN_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/gflib.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/gflib.h new file mode 100644 index 000000000..429295298 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/gflib.h @@ -0,0 +1,137 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Main GFLIB header file for devices without FPU. +* +*******************************************************************************/ +#ifndef _GFLIB_H_ +#define _GFLIB_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "GFLIB_Acos_F16.h" +#include "GFLIB_Asin_F16.h" +#include "GFLIB_AtanYX_F16.h" +#include "GFLIB_Atan_F32.h" +#include "GFLIB_CtrlBetaIPDp_A32.h" +#include "GFLIB_CtrlBetaIPp_A32.h" +#include "GFLIB_CtrlPIDp_A32.h" +#include "GFLIB_CtrlPIp_A32.h" +#include "GFLIB_DFlexRamp_A32.h" +#include "GFLIB_DRamp_F16.h" +#include "GFLIB_DRamp_F32.h" +#include "GFLIB_FlexRamp_A32.h" +#include "GFLIB_FlexSRamp_A32.h" +#include "GFLIB_Hyst_F16_Asmi.h" +#include "GFLIB_Integrator_A32.h" +#include "GFLIB_Limit_F16.h" +#include "GFLIB_Limit_F32.h" +#include "GFLIB_LowerLimit_F16.h" +#include "GFLIB_LowerLimit_F32.h" +#include "GFLIB_LutPer_F16_Asmi.h" +#include "GFLIB_LutPer_F32.h" +#include "GFLIB_Lut_F16_Asmi.h" +#include "GFLIB_Lut_F32.h" +#include "GFLIB_Ramp_F16.h" +#include "GFLIB_Ramp_F32.h" +#include "GFLIB_SinCos_F32.h" +#include "GFLIB_Sqrt_F16.h" +#include "GFLIB_Sqrt_F32.h" +#include "GFLIB_Tan_F32.h" +#include "GFLIB_UpperLimit_F16.h" +#include "GFLIB_UpperLimit_F32.h" +#include "GFLIB_VectorLimit_F16.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Acos_F16(f16Val) GFLIB_Acos_F16_C(f16Val) +#define GFLIB_Asin_F16(f16Val) GFLIB_Asin_F16_C(f16Val) +#define GFLIB_AtanYX_F16(f16Y, f16X, pbErrFlag) GFLIB_AtanYX_F16_Asm(f16Y, f16X, pbErrFlag) +#define GFLIB_Atan_F16(f16Val) GFLIB_Atan_F16_Asm(f16Val) +#define GFLIB_Cos_F16(f16Angle) GFLIB_Cos_F16_Asmi(f16Angle) +#define GFLIB_CtrlBetaIPpAWInit_F16(f16InitVal, psParam) GFLIB_CtrlBetaIPpAWInit_F16_Ci(f16InitVal, psParam) +#define GFLIB_CtrlBetaIPpAW_F16(f16InReq, f16In, pbStopIntegFlag, psParam) GFLIB_CtrlBetaIPpAW_F16_C(f16InReq, f16In, pbStopIntegFlag, psParam) +#define GFLIB_CtrlBetaIPDpAWInit_F16(f16InitVal, psParam) GFLIB_CtrlBetaIPDpAWInit_F16_Ci(f16InitVal, psParam) +#define GFLIB_CtrlBetaIPDpAW_F16(f16InReq, f16In, f16InErrD, pbStopIntegFlag, psParam) GFLIB_CtrlBetaIPDpAW_F16_C(f16InReq, f16In, f16InErrD, pbStopIntegFlag, psParam) +#define GFLIB_CtrlPIDpAWInit_F16(f16InitVal, psParam) GFLIB_CtrlPIDpAWInit_F16_Ci(f16InitVal, psParam) +#define GFLIB_CtrlPIDpAW_F16(f16InErr, f16InErrD, pbStopIntegFlag, psParam) GFLIB_CtrlPIDpAW_F16_Asm(f16InErr, f16InErrD, pbStopIntegFlag, psParam) +#define GFLIB_CtrlPIpAWInit_F16(f16InitVal, psParam) GFLIB_CtrlPIpAWInit_F16_Ci(f16InitVal, psParam) +#define GFLIB_CtrlPIpAW_F16(f16InErr, pbStopIntegFlag, psParam) GFLIB_CtrlPIpAW_F16_Asm(f16InErr, pbStopIntegFlag, psParam) +#define GFLIB_DFlexRampInit_F16(f16InitVal, psParam) GFLIB_DFlexRampInit_F16_C(f16InitVal, psParam) +#define GFLIB_DFlexRampCalcIncr_F16(f16Target, a32Duration, f32IncrSatMot, f32IncrSatGen, psParam) GFLIB_DFlexRampCalcIncr_F16_C(f16Target, a32Duration, f32IncrSatMot, f32IncrSatGen, psParam) +#define GFLIB_DFlexRamp_F16(f16Instant, pbStopFlagMot, pbStopFlagGen,psParam) GFLIB_DFlexRamp_F16_C(f16Instant, pbStopFlagMot, pbStopFlagGen, psParam) +#define GFLIB_DRampInit_F16(f16InitVal, psParam) GFLIB_DRampInit_F16_Ci(f16InitVal, psParam) +#define GFLIB_DRampInit_F32(f32InitVal, psParam) GFLIB_DRampInit_F32_Ci(f32InitVal, psParam) +#define GFLIB_DRamp_F16(f16Target, f16Instant, pbStopFlag, psParam) GFLIB_DRamp_F16_Asm(f16Target, f16Instant, pbStopFlag, psParam) +#define GFLIB_DRamp_F32(f32Target, f32Instant, pbStopFlag, psParam) GFLIB_DRamp_F32_Asm(f32Target, f32Instant, pbStopFlag, psParam) +#define GFLIB_FlexRampInit_F16(f16InitVal, psParam) GFLIB_FlexRampInit_F16_C(f16InitVal, psParam) +#define GFLIB_FlexRampCalcIncr_F16(f16Target, a32Duration, psParam) GFLIB_FlexRampCalcIncr_F16_C(f16Target, a32Duration, psParam) +#define GFLIB_FlexRamp_F16(psParam) GFLIB_FlexRamp_F16_C(psParam) +#define GFLIB_FlexSRampInit_F16(f16InitVal, psParam) GFLIB_FlexSRampInit_F16_C(f16InitVal, psParam) +#define GFLIB_FlexSRampCalcIncr_F16(f16Target, a32Duration, psParam) GFLIB_FlexSRampCalcIncr_F16_C(f16Target, a32Duration, psParam) +#define GFLIB_FlexSRamp_F16(psParam) GFLIB_FlexSRamp_F16_C(psParam) +#define GFLIB_Hyst_F16(f16Val, psParam) GFLIB_Hyst_F16_Asmi(f16Val, psParam) +#define GFLIB_IntegratorInit_F16(f16InitVal, psParam) GFLIB_IntegratorInit_F16_Ci(f16InitVal, psParam) +#define GFLIB_Integrator_F16(f16InVal, psParam) GFLIB_Integrator_F16_Ci(f16InVal, psParam) +#define GFLIB_Limit_F16(f16Val, f16LLim, f16ULim) GFLIB_Limit_F16_Ci(f16Val, f16LLim, f16ULim) +#define GFLIB_Limit_F32(f32Val, f32LLim, f32ULim) GFLIB_Limit_F32_Ci(f32Val, f32LLim, f32ULim) +#define GFLIB_LowerLimit_F16(f16Val, f16LLim) GFLIB_LowerLimit_F16_Ci(f16Val, f16LLim) +#define GFLIB_LowerLimit_F32(f32Val, f32LLim) GFLIB_LowerLimit_F32_Ci(f32Val, f32LLim) +#define GFLIB_Lut1D_F16(f16X, pf16Table, u16TableSize) GFLIB_Lut1D_F16_Asmi(f16X, pf16Table, u16TableSize) +#define GFLIB_LutPer1D_F16(f16X, pf16Table, u16TableSize) GFLIB_LutPer1D_F16_Asmi( f16X, pf16Table, u16TableSize) +#define GFLIB_Lut1D_F32(f32X, pf32Table, u16TableSize) GFLIB_Lut1D_F32_C(f32X, pf32Table, u16TableSize) +#define GFLIB_LutPer1D_F32(f32X, pf32Table, u16TableSize) GFLIB_LutPer1D_F32_C(f32X, pf32Table, u16TableSize) +#define GFLIB_RampInit_F16(f16InitVal, psParam) GFLIB_RampInit_F16_Ci(f16InitVal, psParam) +#define GFLIB_RampInit_F32(f32InitVal, psParam) GFLIB_RampInit_F32_Ci(f32InitVal, psParam) +#define GFLIB_Ramp_F16(f16Target, psParam) GFLIB_Ramp_F16_Ci(f16Target, psParam) +#define GFLIB_Ramp_F32(f32Target, psParam) GFLIB_Ramp_F32_Ci(f32Target, psParam) +#define GFLIB_Sin_F16(f16Angle) GFLIB_Sin_F16_Asm(f16Angle) +#define GFLIB_Sqrt_F16(f16Val) GFLIB_Sqrt_F16_C(f16Val) +#define GFLIB_Sqrt_F16l(f32Val) GFLIB_Sqrt_F16l_C(f32Val) +#define GFLIB_Tan_F16(f16Angle) GFLIB_Tan_F16_C(f16Angle) +#define GFLIB_UpperLimit_F16(f16Val, f16ULim) GFLIB_UpperLimit_F16_Ci(f16Val, f16ULim) +#define GFLIB_UpperLimit_F32(f32Val, f32ULim) GFLIB_UpperLimit_F32_Ci(f32Val, f32ULim) +#define GFLIB_VectorLimit_F16(psVectorIn, f16Lim, psVectorOut) GFLIB_VectorLimit_F16_C(psVectorIn, f16Lim, psVectorOut) +#define GFLIB_VectorLimit1_F16(psVectorIn, f16Lim, psVectorOut) GFLIB_VectorLimit1_F16_C(psVectorIn, f16Lim, psVectorOut) + +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/gflib_FP.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/gflib_FP.h new file mode 100644 index 000000000..6ab64f0db --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/gflib_FP.h @@ -0,0 +1,125 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Main GFLIB header file for devices with FPU. +* +*******************************************************************************/ +#ifndef _GFLIB_FP_H_ +#define _GFLIB_FP_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gflib.h" +#include "GFLIB_Acos_FLT.h" +#include "GFLIB_Asin_FLT.h" +#include "GFLIB_AtanYX_FLT.h" +#include "GFLIB_Atan_FLT.h" +#include "GFLIB_CtrlBetaIPp_FLT.h" +#include "GFLIB_CtrlBetaIPDp_FLT.h" +#include "GFLIB_CtrlPIDp_FLT.h" +#include "GFLIB_CtrlPIp_FLT.h" +#include "GFLIB_DFlexRamp_FLT.h" +#include "GFLIB_FlexRamp_FLT.h" +#include "GFLIB_FlexSRamp_FLT.h" +#include "GFLIB_DRamp_FLT.h" +#include "GFLIB_Hyst_FLT.h" +#include "GFLIB_Integrator_FLT.h" +#include "GFLIB_Limit_FLT.h" +#include "GFLIB_LowerLimit_FLT.h" +#include "GFLIB_Lut_FLT.h" +#include "GFLIB_LutPer_FLT.h" +#include "GFLIB_Ramp_FLT.h" +#include "GFLIB_SinCos_FLT.h" +#include "GFLIB_Sqrt_FLT_Asmi.h" +#include "GFLIB_Tan_FLT.h" +#include "GFLIB_UpperLimit_FLT.h" +#include "GFLIB_VectorLimit_FLT.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_Acos_FLT(fltVal) GFLIB_Acos_FLT_C(fltVal) +#define GFLIB_Asin_FLT(fltVal) GFLIB_Asin_FLT_C(fltVal) +#define GFLIB_AtanYX_A32f(fltY, fltX, pbErrFlag) GFLIB_AtanYX_A32f_C(fltY, fltX, pbErrFlag) +#define GFLIB_AtanYX_FLT(fltY, fltX, pbErrFlag) GFLIB_AtanYX_FLT_C(fltY, fltX, pbErrFlag) +#define GFLIB_Atan_A32f(fltVal) GFLIB_Atan_A32f_C(fltVal) +#define GFLIB_Atan_FLT(fltVal) GFLIB_Atan_FLT_C(fltVal) +#define GFLIB_Cos_FLT(fltAngle) GFLIB_Cos_FLT_C(fltAngle) +#define GFLIB_Cos_FLTa(a32AngleExt) GFLIB_Cos_FLTa_C(a32AngleExt) +#define GFLIB_CtrlBetaIPDpAWInit_FLT(fltInitVal, psParam) GFLIB_CtrlBetaIPDpAWInit_FLT_Ci(fltInitVal, psParam) +#define GFLIB_CtrlBetaIPDpAW_FLT(fltInReq, fltIn, fltInErrD, pbStopIntegFlag, psParam) GFLIB_CtrlBetaIPDpAW_FLT_C(fltInReq, fltIn, fltInErrD, pbStopIntegFlag, psParam) +#define GFLIB_CtrlBetaIPpAWInit_FLT(fltInitVal, psParam) GFLIB_CtrlBetaIPpAWInit_FLT_Ci(fltInitVal, psParam) +#define GFLIB_CtrlBetaIPpAW_FLT(fltInReq, fltIn, pbStopIntegFlag, psParam) GFLIB_CtrlBetaIPpAW_FLT_C(fltInReq, fltIn, pbStopIntegFlag, psParam) +#define GFLIB_CtrlPIDpAWInit_FLT(fltInitVal, psParam) GFLIB_CtrlPIDpAWInit_FLT_Ci(fltInitVal, psParam) +#define GFLIB_CtrlPIDpAW_FLT(fltInErr, fltInErrD, pbStopIntegFlag, psParam) GFLIB_CtrlPIDpAW_FLT_C(fltInErr, fltInErrD, pbStopIntegFlag, psParam) +#define GFLIB_CtrlPIpAWInit_FLT(fltInitVal, psParam) GFLIB_CtrlPIpAWInit_FLT_Ci(fltInitVal, psParam) +#define GFLIB_CtrlPIpAW_FLT(fltInErr, pbStopIntegFlag, psParam) GFLIB_CtrlPIpAW_FLT_C(fltInErr, pbStopIntegFlag, psParam) +#define GFLIB_DFlexRampCalcIncr_FLT(fltTarget, fltDuration, f32IncrSatMot, f32IncrSatGen, psParam) GFLIB_DFlexRampCalcIncr_FLT_C(fltTarget, fltDuration, f32IncrSatMot, f32IncrSatGen, psParam) +#define GFLIB_DFlexRampInit_FLT(fltInitVal, psParam) GFLIB_DFlexRampInit_FLT_C(fltInitVal, psParam) +#define GFLIB_DFlexRamp_FLT(fltInstant, pbStopFlagMot, pbStopFlagGen,psParam) GFLIB_DFlexRamp_FLT_C(fltInstant, pbStopFlagMot, pbStopFlagGen, psParam) +#define GFLIB_DRampInit_FLT(fltInitVal, psParam) GFLIB_DRampInit_FLT_Ci(fltInitVal, psParam) +#define GFLIB_DRamp_FLT(fltTarget, fltInstant, pbStopFlag, psParam) GFLIB_DRamp_FLT_C(fltTarget, fltInstant, pbStopFlag, psParam) +#define GFLIB_FlexRampCalcIncr_FLT(fltTarget, fltDuration, psParam) GFLIB_FlexRampCalcIncr_FLT_C(fltTarget, fltDuration, psParam) +#define GFLIB_FlexRampInit_FLT(fltInitVal, psParam) GFLIB_FlexRampInit_FLT_C(fltInitVal, psParam) +#define GFLIB_FlexRamp_FLT(psParam) GFLIB_FlexRamp_FLT_C(psParam) +#define GFLIB_FlexSRampCalcIncr_FLT(fltTarget, fltDuration, psParam) GFLIB_FlexSRampCalcIncr_FLT_C(fltTarget, fltDuration, psParam) +#define GFLIB_FlexSRampInit_FLT(fltInitVal, psParam) GFLIB_FlexSRampInit_FLT_C(fltInitVal, psParam) +#define GFLIB_FlexSRamp_FLT(psParam) GFLIB_FlexSRamp_FLT_C(psParam) +#define GFLIB_Hyst_FLT(fltVal, psParam) GFLIB_Hyst_FLT_Ci(fltVal, psParam) +#define GFLIB_IntegratorInit_FLT(fltInitVal, psParam) GFLIB_IntegratorInit_FLT_Ci(fltInitVal, psParam) +#define GFLIB_Integrator_FLT(fltInVal, psParam) GFLIB_Integrator_FLT_Ci(fltInVal, psParam) +#define GFLIB_Limit_FLT(fltVal, fltLLim, fltULim) GFLIB_Limit_FLT_Ci(fltVal, fltLLim, fltULim) +#define GFLIB_LowerLimit_FLT(fltVal, fltLLim) GFLIB_LowerLimit_FLT_Ci(fltVal, fltLLim) +#define GFLIB_Lut1DInit_FLT(fltMin, fltMax, pfltTable, psParam) GFLIB_Lut1DInit_FLT_Ci(fltMin, fltMax, pfltTable, psParam) +#define GFLIB_Lut1D_FLT(fltX, pfltTable, psParam) GFLIB_Lut1D_FLT_C(fltX, pfltTable, psParam) +#define GFLIB_LutPer1DInit_FLT(fltMin, fltMax, pfltTable, psParam) GFLIB_LutPer1DInit_FLT_Ci(fltMin, fltMax, pfltTable, psParam) +#define GFLIB_LutPer1D_FLT(fltX, pfltTable, psParam) GFLIB_LutPer1D_FLT_C(fltX, pfltTable, psParam) +#define GFLIB_RampInit_FLT(fltInitVal, psParam) GFLIB_RampInit_FLT_Ci(fltInitVal, psParam) +#define GFLIB_Ramp_FLT(fltTarget, psParam) GFLIB_Ramp_FLT_Ci(fltTarget, psParam) +#define GFLIB_Sin_FLT(fltAngle) GFLIB_Sin_FLT_C(fltAngle) +#define GFLIB_Sin_FLTa(a32AngleExt) GFLIB_Sin_FLTa_C(a32AngleExt) +#define GFLIB_Sqrt_FLT(fltVal) GFLIB_Sqrt_FLT_Asmi(fltVal) +#define GFLIB_Tan_FLT(fltAngle) GFLIB_Tan_FLT_C(fltAngle) +#define GFLIB_Tan_FLTa(a32AngleExt) GFLIB_Tan_FLTa_C(a32AngleExt) +#define GFLIB_UpperLimit_FLT(fltVal, fltULim) GFLIB_UpperLimit_FLT_Ci(fltVal, fltULim) +#define GFLIB_VectorLimit_FLT(psVectorIn, fltLim, psVectorOut) GFLIB_VectorLimit_FLT_C(psVectorIn, fltLim, psVectorOut) +#define GFLIB_VectorLimit1_FLT(psVectorIn, fltLim, psVectorOut) GFLIB_VectorLimit1_FLT_C(psVectorIn, fltLim, psVectorOut) +#if defined(__cplusplus) +} +#endif + +#endif /* _GFLIB_FP_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/gflib_types.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/gflib_types.h new file mode 100644 index 000000000..9a0cdaa20 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/Include/gflib_types.h @@ -0,0 +1,54 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +*******************************************************************************/ + +#ifndef _GFLIB_TYPES_H_ +#define _GFLIB_TYPES_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GFLIB_CONST + +#if defined(__cplusplus) +} +#endif + +#endif /*_GFLIB_TYPES_H_*/ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/libGFLIB.a b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/libGFLIB.a new file mode 100644 index 000000000..75168ae56 Binary files /dev/null and b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GFLIB/libGFLIB.a differ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Clark_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Clark_F16_Asmi.h new file mode 100644 index 000000000..63aa6e716 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Clark_F16_Asmi.h @@ -0,0 +1,198 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Clarke, Inverse Clarke Transformation +* +*******************************************************************************/ +#ifndef _GMCLIB_CLARK_F16_ASMI_H_ +#define _GMCLIB_CLARK_F16_ASMI_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/****************************************************************************** +* Includes +******************************************************************************/ +#include "mlib.h" +#include "gmclib_types.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define GMCLIB_Clark_F16_Asmi(psIn, psOut) GMCLIB_Clark_F16_FAsmi(psIn, psOut) +#define GMCLIB_ClarkInv_F16_Asmi(psIn, psOut) GMCLIB_ClarkInv_F16_FAsmi(psIn, psOut) + +/***************************************************************************//*! +* +* @brief The function calculates Clarke Transformation which is used +* for transforming values (current, voltage, flux) from the +* three phase stationary coordination system to alpha-beta +* stationary orthogonal coordination system. +* +* @param ptr GMCLIB_3COOR_T_F16 *psIn +* IN - pointer to structure containing data of +* three phase stationary system +* GMCLIB_2COOR_ALBE_T_F16 *psOut +* OUT - pointer to structure containing data of +* two phase stationary orthogonal system +* +* @remarks Modifies the structure pointed by psOut pointer +* according to the following equations: +* alpha = a +* beta = b * 1 / sqrt(3) - c * 1 / sqrt(3) +* +****************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_suppress=Pe549 /* Suppresses the Pe549 warning for IAR compiler*/ +#endif +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline void GMCLIB_Clark_F16_FAsmi(const GMCLIB_3COOR_T_F16 *psIn, + GMCLIB_2COOR_ALBE_T_F16 *psOut) +{ + register frac32_t f32Val1=0, f32Val2=0; + + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ ldrsh f32Val1, [psIn, #2] /* f32Val1 = psIn->f16B */ + ldrsh f32Val2, [psIn, #4] /* f32Val2 = psIn->f16C */ + sub f32Val1, f32Val1, f32Val2 /* f32Val1 = f16B - f16C */ + movw f32Val2, #0x49E7 /* f32Val2 = FRAC16(1/sqrt(3)) */ + mul f32Val1, f32Val1, f32Val2 /* f32Val1 = (f16B - f16C)/sqrt(3) */ + ssat f32Val1, #16, f32Val1, asr #15 /* Saturation */ + ldrsh f32Val2, [psIn] /* f32Val2 = psIn->f16A */ + strh f32Val2, [psOut] /* psOut->f16Alpha = f32Val2 */ + strh f32Val1, [psOut, #2] }; /* psOut->f16Beta = f32Val1 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "ldrsh %0, [%2, #2] \n" /* f32Val1 = psIn->f16B */ + "ldrsh %1, [%2, #4] \n" /* f32Val2 = psIn->f16C */ + "sub %0, %0, %1 \n" /* f32Val1 = f16B - f16C */ + "movw %1, #0x49E7 \n" /* f32Val2 = FRAC16(1/sqrt(3)) */ + "mul %0, %0, %1 \n" /* f32Val1 = (f16B - f16C)/sqrt(3) */ + "ssat %0, #16, %0, asr #15 \n" /* Saturation */ + "ldrsh %1, [%2] \n" /* f32Val2 = psIn->f16A */ + "strh %1, [%3] \n" /* psOut->f16Alpha = f32Val2 */ + "strh %0, [%3, #2] \n" /* psOut->f16Beta = f32Val1 */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Val1), "+l"(f32Val2): "l"(psIn), "l"(psOut)); + #endif + + return; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_default=Pe549 +#endif + +/**************************************************************************** +* +* @brief The function calculates Inverse Clarke Transformation which is used +* for transforming values (current, voltage, flux) from alpha-beta +* stationary orthogonal coordination system to three phase +* stationary coordination system +* +* @param ptr GMCLIB_2COOR_ALBE_T_F16 *psIn +* IN - pointer to structure containing data of two phase stationary orthogonal system +* GMCLIB_3COOR_T_F16 *psOut +* OUT - pointer to structure containing data of three phase stationary system +* +* @remarks Modifies the structure pointed by p_abc pointer +* according to the following equations: +* a = alpha +* b = -0.5 * alpha + sgrt(3) / 2 * beta +* c = -0.5 * alpha - sgrt(3) / 2 * beta +* +****************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_suppress=Pe549 /* Suppresses the Pe549 warning for IAR compiler*/ +#endif +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline void GMCLIB_ClarkInv_F16_FAsmi(const GMCLIB_2COOR_ALBE_T_F16 *psIn, + GMCLIB_3COOR_T_F16 *psOut) +{ + register frac32_t f32Val1=0, f32Val2=0, f32Val3=0; + + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ ldrsh f32Val3, [psIn] /* f32Val3 = psIn->f16Alpha */ + ldrsh f32Val1, [psIn, #2] /* f32Val1 = psIn->f16Beta */ + movw f32Val2, #0x6EDA /* f32Val2 = FRAC16(sqrt(3)/2) */ + mul f32Val1, f32Val1, f32Val2 /* f32Val1 = f16Beta * sqrt(3)/2 */ + str f32Val3, [psOut] /* psOut->f16A = f32Val3 */ + asr f32Val1, f32Val1, #15 /* f32Val1 >> 15 */ + add f32Val2, f32Val1, f32Val3, asr #1 /* f32Val2 = f16Beta * sqrt(3)/2 + f16Alpha/2 */ + sub f32Val1, f32Val1, f32Val3, asr #1 /* f32Val1 = f16Beta * sqrt(3)/2 - f16Alpha/2 */ + rsb f32Val2, f32Val2, #0 /* f32Val2 = - f16Beta * sqrt(3)/2 - f16Alpha/2 */ + ssat f32Val1, #16, f32Val1 /* Saturation */ + ssat f32Val2, #16, f32Val2 /* Saturation */ + strh f32Val1, [psOut, #2] /* psOut->f16B = f32Val1 */ + strh f32Val2, [psOut, #4] }; /* psOut->f16C = f32Val2 */ + #else + __asm volatile( "ldrsh %2, [%3] \n" /* f32Val3 = psIn->f16Alpha */ + "ldrsh %0, [%3, #2] \n" /* f32Val1 = psIn->f16Beta */ + "movw %1, #0x6EDA \n" /* f32Val2 = FRAC16(sqrt(3)/2) */ + "mul %0, %0, %1 \n" /* f32Val1 = f16Beta * sqrt(3)/2 */ + "str %2, [%4] \n" /* psOut->f16A = f32Val3 */ + "asr %0, %0, #15 \n" /* f32Val1 >> 15 */ + "add %1, %0, %2, asr #1 \n" /* f32Val2 = f16Beta * sqrt(3)/2 + f16Alpha/2 */ + "sub %0, %0, %2, asr #1 \n" /* f32Val1 = f16Beta * sqrt(3)/2 - f16Alpha/2 */ + "rsb %1, %1, #0 \n" /* f32Val2 = - f16Beta * sqrt(3)/2 - f16Alpha/2 */ + "ssat %0, #16, %0 \n" /* Saturation */ + "ssat %1, #16, %1 \n" /* Saturation */ + "strh %0, [%4, #2] \n" /* psOut->f16B = f32Val1 */ + "strh %1, [%4, #4] \n" /* psOut->f16C = f32Val2 */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Val1), "+l"(f32Val2), "+l"(f32Val3): "l"(psIn), "l"(psOut)); + #endif + + return; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_default=Pe549 +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* _GMCLIB_CLARK_F16_ASMI_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Clark_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Clark_FLT.h new file mode 100644 index 000000000..43299f40f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Clark_FLT.h @@ -0,0 +1,131 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Clarke, Inverse Clarke Transformation +* +*******************************************************************************/ +#ifndef _GMCLIB_CLARK_FLT_H_ +#define _GMCLIB_CLARK_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/****************************************************************************** +* Includes +******************************************************************************/ +#include "mlib_FP.h" +#include "gmclib_types.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define GMCLIB_Clark_FLT_Ci(psIn, psOut) GMCLIB_Clark_FLT_FCi(psIn, psOut) +#define GMCLIB_ClarkInv_FLT_Ci(psIn, psOut) GMCLIB_ClarkInv_FLT_FCi(psIn, psOut) + +/***************************************************************************//*! +* +* @brief The function calculates Clarke Transformation which is used +* for transforming values (current, voltage, flux) from the +* three phase stationary coordination system to alpha-beta +* stationary orthogonal coordination system. +* +* @param ptr - GMCLIB_3COOR_T_FLT *psIn - IN - pointer to structure containing +* data of three phase stationary system +* - GMCLIB_2COOR_ALBE_T_FLT *psOut - OUT - pointer to structure +* containing data of two phase stationary orthogonal system +* +* @remarks Modifies the structure pointed by psOut pointer +* according to the following equations: +* +* alpha = a +* beta = b * 1 / sqrt(3) - c * 1 / sqrt(3) +* +****************************************************************************/ +static inline void GMCLIB_Clark_FLT_FCi(const GMCLIB_3COOR_T_FLT *psIn, + GMCLIB_2COOR_ALBE_T_FLT *psOut) +{ + /* Calculate Alpha orthogonal coordinate [alpha = a] */ + psOut->fltAlpha = psIn->fltA; + + /* Calculate Beta orthogonal coordinate [beta = b * 1 / sqrt(3) - c * 1 / sqrt(3] + and right shift to 16-bit range */ + psOut->fltBeta = MLIB_Mul_FLT(MLIB_Sub_FLT(psIn->fltB, psIn->fltC), GMCLIB_ONE_DIV_SQRT3_FLT); + + return; +} + +/**************************************************************************** +* +* @brief The function calculates Inverse Clarke Transformation which is used +* for transforming values (current, voltage, flux) from alpha-beta +* stationary orthogonal coordination system to three phase +* stationary coordination system +* +* @param ptr - GMCLIB_2COOR_ALBE_T_FLT *psOut - OUT - pointer to structure +* containing data of two phase stationary orthogonal system +* - GMCLIB_3COOR_T_FLT *psIn - IN - pointer to structure containing +* data of three phase stationary system +* +* @remarks Modifies the structure pointed by p_abc pointer +* according to the following equations: +* +* a = alpha +* b = -0.5 * alpha + sgrt(3) / 2 * beta +* c = -0.5 * alpha - sgrt(3) / 2 * beta +* +****************************************************************************/ +static inline void GMCLIB_ClarkInv_FLT_FCi(const GMCLIB_2COOR_ALBE_T_FLT *psIn, + GMCLIB_3COOR_T_FLT *psOut) +{ + /* Store constant alpha * (-0.5) in flt range as fltM2 */ + register float_t fltM1 = MLIB_Mul_FLT(psIn->fltAlpha, -0.5F); + /* Store constant beta * sqrt(3) / 2 in flt range as fltM2 */ + register float_t fltM2 = MLIB_Mul_FLT(psIn->fltBeta, GMCLIB_SQRT3_DIV_2_FLT); + + /* Calculate a coordinate [a = alpha] */ + psOut->fltA = psIn->fltAlpha; + + /* Calculate b coordinate [b = -alpha/2 + beta * sqrt(3) / 2 ] */ + psOut->fltB = MLIB_Add_FLT(fltM1, fltM2); + + /* Calculate c coordinate [c = -alpha/2 - beta * sqrt(3) / 2 ] */ + psOut->fltC = MLIB_Sub_FLT(fltM1, fltM2); + + return; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GMCLIB_CLARK_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Decoupling_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Decoupling_A32.h new file mode 100644 index 000000000..9a33f7297 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Decoupling_A32.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Decoupling calculation +* +*******************************************************************************/ + +#ifndef _GMCLIB_DECOUPLING_A32_H_ +#define _GMCLIB_DECOUPLING_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/**************************************************************************** +* Includes +****************************************************************************/ +#include "mlib.h" +#include "gmclib_types.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define GMCLIB_DecouplingPMSM_F16_Asm(psUDQ, psIDQ, f16SpeedEl, psParam, psUDQDec) \ + GMCLIB_DecouplingPMSM_F16_FAsm(psUDQ, psIDQ, f16SpeedEl, psParam, psUDQDec) + +/****************************************************************************** +* Types +******************************************************************************/ +typedef struct +{ + acc32_t a32KdGain; + acc32_t a32KqGain; +}GMCLIB_DECOUPLINGPMSM_T_A32; + +/**************************************************************************** +* Exported function prototypes +****************************************************************************/ +extern void GMCLIB_DecouplingPMSM_F16_FAsm(const GMCLIB_2COOR_DQ_T_F16 *psUDQ, + const GMCLIB_2COOR_DQ_T_F16 *psIDQ, + frac16_t f16SpeedEl, + const GMCLIB_DECOUPLINGPMSM_T_A32 *psParam, + GMCLIB_2COOR_DQ_T_F16 *psUDQDec); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GMCLIB_DECOUPLING_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Decoupling_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Decoupling_FLT.h new file mode 100644 index 000000000..e9d6849a3 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Decoupling_FLT.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Decoupling calculation +* +*******************************************************************************/ + +#ifndef _GMCLIB_DECOUPLING_FLT_H_ +#define _GMCLIB_DECOUPLING_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/**************************************************************************** +* Includes +****************************************************************************/ +#include "mlib_FP.h" +#include "gmclib_types.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define GMCLIB_DecouplingPMSM_FLT_C(psUDQ, psIDQ, fltSpeedEl, psParam, psUDQDec) \ + GMCLIB_DecouplingPMSM_FLT_FC(psUDQ, psIDQ, fltSpeedEl, psParam, psUDQDec) + +/****************************************************************************** +* Types +******************************************************************************/ +typedef struct +{ + float_t fltLd; + float_t fltLq; +}GMCLIB_DECOUPLINGPMSM_T_FLT; + +/**************************************************************************** +* Exported function prototypes +****************************************************************************/ +extern void GMCLIB_DecouplingPMSM_FLT_FC(const GMCLIB_2COOR_DQ_T_FLT *psUDQ, + const GMCLIB_2COOR_DQ_T_FLT *psIDQ, + float_t fltSpeedEl, + const GMCLIB_DECOUPLINGPMSM_T_FLT *psParam, + GMCLIB_2COOR_DQ_T_FLT *psUDQDec); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GMCLIB_DECOUPLING_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_ElimDcBusRip_A32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_ElimDcBusRip_A32_Asmi.h new file mode 100644 index 000000000..762917e19 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_ElimDcBusRip_A32_Asmi.h @@ -0,0 +1,170 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Elimination of the DC-Bus voltage ripple with index +* +*******************************************************************************/ +#ifndef _GMCLIB_ELIMDCBUSRIP_A32_ASMI_H_ +#define _GMCLIB_ELIMDCBUSRIP_A32_ASMI_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gmclib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GMCLIB_ElimDcBusRip_F16sas_Asmi(f16UDCBus, a32IdxMod, psUAlBe, psUAlBeComp) \ + GMCLIB_ElimDcBusRip_F16sas_FAsmi(f16UDCBus, a32IdxMod, psUAlBe, psUAlBeComp) + +/***************************************************************************//*! +* @brief The function is used for elimination of the DC-Bus voltage ripple. +* +* @param ptr - psUAlBe - Direct(alpha) and quadrature(beta) +* component of the stator voltage vector in the stationary +* reference frame. Format Q15, range 8000-7FFF +* - psUAlBeComp - Direct(alpha) and quadrature(beta) +* component of the stator voltage vector in the stationary +* reference frame. Format Q15, range 8000-7FFF +* @param in - f16UDCBus - Actual effective value of the +* DC-Bus voltage. Format Q15, range 0-7FFF +* - a32IdxMod - Modulation Index, accumulator 32 bit format. +* +* @return Function reads, recalculate and fills variables alpha, +* beta in the data structure GMCLIB_2COOR_ALBE_T_F16. +* +* @remarks: The GMCLIB_ElimDcBusRipFOC function compensates an amplitude +* of the direct-a and the quadrature-ß component of the +* stator-reference voltage vector in the fractional arithmetic by the +* formula shown in the following equations: +* +* for ModIndex > 0 +* UalfaReq = 1.0 if Ua > 0 && Abs(Ua) >= Udcbus / ModIndex +* UalfaReq = -1.0 if Ua < 0 && Abs(Ua) <= Udcbus / ModIndex +* UalfaReq = Ua * ModIndex / Udcbus else +* +* UbetaReq = 1.0 if Ub > 0 && Abs(Ub) >= Udcbus / ModIndex +* UbetaReq = -1.0 if Ub < 0 && Abs(Ub) <= Udcbus / ModIndex +* UbetaReq = Ub * ModIndex / Udcbus else +* +* for ModIndex = 0 +* UaReq = 1.0 Ua > 0 && Udcbus = 0 +* UaReq = -1.0 Ua < 0 && Udcbus = 0 +* UaReq = 0.0 Ua = 0 && Udcbus = 0 +* +* UbReq = 1.0 Ub > 0 && Udcbus = 0 +* UbReq = -1.0 Ub < 0 && Udcbus = 0 +* UbReq = 0.0 Ub = 0 && Udcbus = 0 +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline void GMCLIB_ElimDcBusRip_F16sas_FAsmi(frac16_t f16UDCBus, + acc32_t a32IdxMod, + const GMCLIB_2COOR_ALBE_T_F16 *psUAlBe, + GMCLIB_2COOR_ALBE_T_F16 *psUAlBeComp) +{ + register frac32_t f32Val = 0x40000000; /* f32Val = FRAC32(0.5) */ + + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16UDCBus, f16UDCBus /* Sign extend */ + cmp f16UDCBus, #0 /* Compares Udcbus with 0 */ + it eq /* If Udcbus = 0, then ModIndex / Udcbus = 0x7FFFFFFF */ + qaddeq f16UDCBus, f32Val, f32Val /* Saturation */ + beq.n ElimDcBusRip_UdcZerro /* If Udcbus = 0, then goes to ElimDcBusRip_UdcZerro */ + /* ModIndex / Udcbus */ + sdiv f16UDCBus, f32Val, f16UDCBus /* f16UDCBus = 1 / Udcbus */ + smull f16UDCBus, a32IdxMod, f16UDCBus, a32IdxMod /* a32IdxMod:f16UDCBus = ModIndex / Udcbus */ + lsr f16UDCBus, f16UDCBus, #14 /* f16UDCBus >> 14 */ + add f16UDCBus, f16UDCBus, a32IdxMod, lsl #18 /* f16UDCBus = f16UDCBus + a32IdxMod << 18 */ + asrs a32IdxMod,a32IdxMod, #13 /* a32IdxMod >> 13 */ + it ne /* If a32IdxMod > 0, then saturates result */ + qaddne f16UDCBus, f32Val, f32Val /* Saturation */ + ElimDcBusRip_UdcZerro: + /* UaReq = Ua * ModIndex / Udcbus */ + ldrh a32IdxMod, [psUAlBe] /* Loads Ua */ + smulwb f32Val, f16UDCBus, a32IdxMod /* f32Val = Ua * ModIndex / Udcbus */ + ssat f32Val, #16, f32Val /* Saturation */ + strh f32Val, [psUAlBeComp] /* Stores UaReq */ + /* UbReq = Ub * ModIndex / Udcbus */ + ldrh a32IdxMod, [psUAlBe, #2] /* Loads Ub */ + smulwb f32Val, f16UDCBus, a32IdxMod /* f32Val = Ub * ModIndex / Udcbus */ + ssat f32Val, #16, f32Val /* Saturation */ + strh f32Val, [psUAlBeComp, #2] }; /* Stores UbReq */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Sign extend */ + "cmp %0, #0 \n" /* Compares Udcbus with 0 */ + "it eq \n" /* If Udcbus = 0, then ModIndex / Udcbus = 0x7FFFFFFF */ + "qaddeq %0, %2, %2 \n" /* Saturation */ + "beq.n ElimDcBusRip_UdcZerro \n" /* If Udcbus = 0, then goes to ElimDcBusRip_UdcZerro */ + /* ModIndex / Udcbus */ + "sdiv %0, %2, %0 \n" /* f16UDCBus = 1 / Udcbus */ + "smull %0, %1, %0, %1 \n" /* a32IdxMod:f16UDCBus = ModIndex / Udcbus */ + "lsr %0, %0, #14 \n" /* f16UDCBus >> 14 */ + "add %0, %0, %1, lsl #18 \n" /* f16UDCBus = f16UDCBus + a32IdxMod << 18 */ + "asrs %1,%1, #13 \n" /* a32IdxMod >> 13 */ + "it ne \n" /* If a32IdxMod > 0, then saturates result */ + "qaddne %0, %2, %2 \n" /* Saturation */ + "ElimDcBusRip_UdcZerro: \n" + /* UaReq = Ua * ModIndex / Udcbus */ + "ldrh %1, [%4] \n" /* Loads Ua */ + "smulwb %2, %0, %1 \n" /* f32Val = Ua * ModIndex / Udcbus */ + "ssat %2, #16, %2 \n" /* Saturation */ + "strh %2, [%3] \n" /* Stores UaReq */ + /* UbReq = Ub * ModIndex / Udcbus */ + "ldrh %1, [%4, #2] \n" /* Loads Ub */ + "smulwb %2, %0, %1 \n" /* f32Val = Ub * ModIndex / Udcbus */ + "ssat %2, #16, %2 \n" /* Saturation */ + "strh %2, [%3, #2] \n" /* Stores UbReq */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16UDCBus), "+l"(a32IdxMod), "+l"(f32Val): "l"(psUAlBeComp), "l"(psUAlBe)); + #endif +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _GMCLIB_ELIMDCBUSRIP_A32_ASMI_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_ElimDcBusRip_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_ElimDcBusRip_F16_Asmi.h new file mode 100644 index 000000000..a1976c6cd --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_ElimDcBusRip_F16_Asmi.h @@ -0,0 +1,155 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Elimination of the DC-Bus voltage ripple for FOC +* +*******************************************************************************/ +#ifndef _GMCLIB_ELIMDCBUSRIP_F16_ASMI_H_ +#define _GMCLIB_ELIMDCBUSRIP_F16_ASMI_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gmclib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GMCLIB_ElimDcBusRipFOC_F16_Asmi(f16UDCBus, psUAlBe, psUAlBeComp) \ + GMCLIB_ElimDcBusRipFOC_F16_FAsmi(f16UDCBus, psUAlBe, psUAlBeComp) + +/***************************************************************************//*! +* +* @brief The function is used for elimination of the DC-Bus voltage +* ripple in general cases where the phase voltage is scale as +* measured dc bus voltage divided by the mod. index . +* +* @param ptr - psUAlBe - Direct(alpha) and quadrature(beta) +* component of the stator voltage vector in the stationary +* reference frame. Format Q15, range 8000-7FFF +* - psUAlBeComp - Direct(alpha) and quadrature(beta) +* component of the stator voltage vector in the stationary +* reference frame. Format Q15, range 8000-7FFF +* +* @param in - f16UDCBus - Actual effective value of the +* DC-Bus voltage. Format Q15, range 0-7FFF +* +* @return Function reads, recalculate and fills variables alpha, +* beta in the data structure GMCLIB_2COOR_ALBE_T_F16. +* +* @remarks: The GMCLIB_ElimDcBusRipFOC function compensates an amplitude +* of the direct-a and the quadrature-ß component of the +* stator-reference voltage vector in the fractional arithmetic by the +* formula shown in the following equations: +* +* UalfaReq = 0.0 if Ualfa = 0 && UDCBus = 0 +* UalfaReq = 1.0 if Ualfa > 0 && Abs(Ualfa) >= UDCBus +* UalfaReq = -1.0 if Ualfa < 0 && Abs(Ualfa) <= UDCBus +* UalfaReq = Ualfa/UDCBus else +* +* UbetaReq = 0.0 if Ubeta = 0 && UDCBus = 0 +* UbetaReq = 1.0 if Ubeta > 0 && Abs(Ubeta) >= UDCBus +* UbetaReq = -1.0 if Ubeta < 0 && Abs(Ubeta) <= UDCBus +* UbetaReq = Ubeta/UDCBus else +* +*******************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_suppress=Pe549 /* Suppresses the Pe549 warning for IAR compiler*/ +#endif +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline void GMCLIB_ElimDcBusRipFOC_F16_FAsmi(frac16_t f16UDCBus, + const GMCLIB_2COOR_ALBE_T_F16 *psUAlBe, + GMCLIB_2COOR_ALBE_T_F16 *psUAlBeComp) +{ + register frac32_t f32Val=0; /* f32Val = FRAC32(0.5) */ + + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16UDCBus, f16UDCBus /* Sign extend */ + cmp f16UDCBus, #0 /* Compares Udcbus with 0 */ + it eq /* If Udcbus = 0, then Udcbus = 1 */ + moveq f16UDCBus, #1 /* Udcbus = 1 */ + /* UaReq = Ua / Udcbus */ + ldrsh f32Val, [psUAlBe] /* Loads Ua */ + lsls f32Val, f32Val, #15 /* f32Val << 15 */ + sdiv f32Val, f32Val, f16UDCBus /* f32Val = Ua / Udcbus */ + ssat f32Val, #16, f32Val /* Saturation */ + strh f32Val, [psUAlBeComp] /* Stores UaReq */ + /* UbReq = Ub / Udcbus */ + ldrsh f32Val, [psUAlBe, #2] /* Loads Ub */ + lsls f32Val, f32Val, #15 /* f32Val << 15 */ + sdiv f32Val, f32Val, f16UDCBus /* f32Val = Ub / Udcbus */ + ssat f32Val, #16, f32Val /* Saturation */ + strh f32Val, [psUAlBeComp, #2]};/* Stores UbReq */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Sign extend */ + "cmp %0, #0 \n" /* Compares Udcbus with 0 */ + "it eq \n" /* If Udcbus = 0, then Udcbus = 1 */ + "moveq %0, #1 \n" /* Udcbus = 1 */ + /* UaReq = Ua / Udcbus */ + "ldrsh %1, [%3] \n" /* Loads Ua */ + "lsls %1, %1, #15 \n" /* f32Val << 15 */ + "sdiv %1, %1, %0 \n" /* f32Val = Ua / Udcbus */ + "ssat %1, #16, %1 \n" /* Saturation */ + "strh %1, [%2] \n" /* Stores UaReq */ + /* UbReq = Ub / Udcbus */ + "ldrsh %1, [%3, #2] \n" /* Loads Ub */ + "lsls %1, %1, #15 \n" /* f32Val << 15 */ + "sdiv %1, %1, %0 \n" /* f32Val = Ub / Udcbus */ + "ssat %1, #16, %1 \n" /* Saturation */ + "strh %1, [%2, #2] \n" /* Stores UbReq */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16UDCBus), "+l"(f32Val): "l"(psUAlBeComp), "l"(psUAlBe)); + #endif +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_default=Pe549 +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* _GMCLIB_ELIMDCBUSRIP_F16_ASMI_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_ElimDcBusRip_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_ElimDcBusRip_FLT.h new file mode 100644 index 000000000..fbac92e2c --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_ElimDcBusRip_FLT.h @@ -0,0 +1,72 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Elimination of the DC-Bus voltage ripple for FOC +* +*******************************************************************************/ +#ifndef _GMCLIB_ELIMDCBUSRIP_FLT_H_ +#define _GMCLIB_ELIMDCBUSRIP_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gmclib_types.h" +#include "mlib_FP.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GMCLIB_ElimDcBusRipFOC_F16ff_C(fltUDCBus, psUAlBe, psUAlBeComp) \ + GMCLIB_ElimDcBusRipFOC_F16ff_FC(fltUDCBus, psUAlBe, psUAlBeComp) +#define GMCLIB_ElimDcBusRip_F16fff_C(fltUDCBus, fltIdxMod, psUAlBe, psUAlBeComp) \ + GMCLIB_ElimDcBusRip_F16fff_FC(fltUDCBus, fltIdxMod, psUAlBe, psUAlBeComp) + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern void GMCLIB_ElimDcBusRipFOC_F16ff_FC(float_t fltUDCBus, + const GMCLIB_2COOR_ALBE_T_FLT *psUAlBe, + GMCLIB_2COOR_ALBE_T_F16 *psUAlBeComp); +extern void GMCLIB_ElimDcBusRip_F16fff_FC(float_t fltUDCBus, + float_t fltIdxMod, + const GMCLIB_2COOR_ALBE_T_FLT *psUAlBe, + GMCLIB_2COOR_ALBE_T_F16 *psUAlBeComp); + +#if defined(__cplusplus) +} +#endif + +#endif /* _GMCLIB_ELIMDCBUSRIP_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Park_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Park_F16_Asmi.h new file mode 100644 index 000000000..a8d2d5715 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Park_F16_Asmi.h @@ -0,0 +1,222 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Park, Inverse Park Transformation +* +*******************************************************************************/ +#ifndef _GMCLIB_PARK_F16_ASMI_H_ +#define _GMCLIB_PARK_F16_ASMI_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gmclib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GMCLIB_Park_F16_Asmi(psIn, psAnglePos, psOut) \ + GMCLIB_Park_F16_FAsmi(psIn, psAnglePos, psOut) +#define GMCLIB_ParkInv_F16_Asmi(psIn, psAnglePos, psOut) \ + GMCLIB_ParkInv_F16_FAsmi(psIn, psAnglePos, psOut) + +/***************************************************************************//*! +* +* @brief The function calculates Park Transformation which is used for +* transforming values (current, voltage, flux) from +* alpha-beta stationary orthogonal coordination system +* to d-q rotating orthogonal coordination system +* +* @param ptr GMCLIB_2COOR_ALBE_T_F16 *psIn +* IN - pointer to structure containing data of two phase +* stationary orthogonal system +* GMCLIB_2COORD_SINCOS_T_F16 *psAnglePos +* IN - pointer to structure where the values +* of sine and cosine are stored +* GMCLIB_2_COOR_DQ_T_F16 *psOut +* OUT - pointer to structure containing data of +* DQ coordinate two-phase stationary orthogonal system +* +* @remarks Modifies the structure pointed by pDQ pointer +* according to the following equations +* d = alpha * cos(theta) + beta * sin(theta) +* q = beta * cos(theta) - alpha * sin(theta) +* +*******************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_suppress=Pe549 /* Suppresses the Pe549 warning for IAR compiler*/ +#endif +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline void GMCLIB_Park_F16_FAsmi(const GMCLIB_2COOR_ALBE_T_F16 *psIn, + const GMCLIB_2COOR_SINCOS_T_F16 *psAnglePos, + GMCLIB_2COOR_DQ_T_F16 *psOut) +{ + register frac32_t f32Val1=0, f32Val2=0, f32Val3=0; + + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ ldrsh f32Val1, [psIn] /* Loads alpha */ + ldrsh f32Val2, [psIn, #2] /* Loads beta */ + ldrsh f32Val3, [psAnglePos] /* Loads sin(theta) */ + ldrsh psIn, [psAnglePos, #2] /* Loads cos(theta) */ + + mul psAnglePos, f32Val1, psIn /* alpha * cos(theta) */ + mla psAnglePos, f32Val2, f32Val3, psAnglePos /* alpha * cos(theta) + beta * sin(theta) */ + ssat psAnglePos, #16, psAnglePos, asr #15 /* Saturation */ + mul f32Val2, f32Val2, psIn /* beta * cos(theta) */ + mls f32Val2, f32Val1, f32Val3, f32Val2 /* beta * cos(theta) - alpha * sin(theta) */ + ssat f32Val2, #16, f32Val2, asr #15 /* Saturation */ + + strh psAnglePos, [psOut] /* Stores psOut->f16D */ + strh f32Val2, [psOut, #2] }; /* Stores psOut->f16Q */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "ldrsh %0, [%3] \n" /* Loads alpha */ + "ldrsh %1, [%3, #2] \n" /* Loads beta */ + "ldrsh %2, [%4] \n" /* Loads sin(theta) */ + "ldrsh %3, [%4, #2] \n" /* Loads cos(theta) */ + + "mul %4, %0, %3 \n" /* alpha * cos(theta) */ + "mla %4, %1, %2, %4 \n" /* alpha * cos(theta) + beta * sin(theta) */ + "ssat %4, #16, %4, asr #15 \n" /* Saturation */ + "mul %1, %1, %3 \n" /* beta * cos(theta) */ + "mls %1, %0, %2, %1 \n" /* beta * cos(theta) - alpha * sin(theta) */ + "ssat %1, #16, %1, asr #15 \n" /* Saturation */ + + "strh %4, [%5] \n" /* Stores psOut->f16D */ + "strh %1, [%5, #2] \n" /* Stores psOut->f16Q */ + + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Val1), "+l"(f32Val2), "+l"(f32Val3), "+l"(psIn), "+l"(psAnglePos): "l"(psOut)); + #endif + + return; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_default=Pe549 +#endif + +/***************************************************************************//*! +* +* @brief The function calculates Inverse Park Transformation which is used +* for transforming values (current, voltage, flux) from +* d-q rotating orthogonal coordination system to alpha-beta +* stationary orthogonal coordination system. +* +* @param ptr GMCLIB_2COOR_DQ_T_F16 *psIn +* IN - pointer to structure containing data of +* DQ coordinate two-phase stationary orthogonal system +* GMCLIB_ANGLE_T *psAnglePos +* IN - pointer to structure where the values +* of sine and cosine are stored +* GMCLIB_2COOR_ALBE_T_F16 *psOut +* OUT - pointer to structure containing data of two phase +* stationary orthogonal system +* +* @remarks Modifies the structure pointed by pAlphaBeta pointer +* according following equations: +* alpha = d * cos(theta) - q * sin(theta) +* beta = d * sin(theta) + q * cos(theta) +* +*******************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_suppress=Pe549 /* Suppresses the Pe549 warning for IAR compiler*/ +#endif +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline void GMCLIB_ParkInv_F16_FAsmi(const GMCLIB_2COOR_DQ_T_F16 *psIn, + const GMCLIB_2COOR_SINCOS_T_F16 *psAnglePos, + GMCLIB_2COOR_ALBE_T_F16 *psOut) +{ + register frac32_t f32Val1=0, f32Val2=0, f32Val3=0; + + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ ldrsh f32Val1, [psIn] /* Loads d */ + ldrsh f32Val2, [psIn, #2] /* Loads q */ + ldrsh f32Val3, [psAnglePos] /* Loads sin(theta) */ + ldrsh psIn, [psAnglePos, #2] /* Loads cos(theta) */ + + mul psAnglePos, f32Val1, psIn /* d * cos(theta) */ + mls psAnglePos, f32Val2, f32Val3, psAnglePos /* d * cos(theta) - q * sin(theta) */ + ssat psAnglePos, #16, psAnglePos, asr #15 /* Saturation */ + mul f32Val2, f32Val2, psIn /* q * cos(theta) */ + mla f32Val2, f32Val1, f32Val3, f32Val2 /* q * cos(theta) + d * sin(theta) */ + ssat f32Val2, #16, f32Val2, asr #15 /* Saturation */ + + strh psAnglePos, [psOut] /* Stores psOut->f16Alpha */ + strh f32Val2, [psOut, #2] }; /* Stores psOut->f16Beta */ + #else + __asm volatile( "ldrsh %0, [%3] \n" /* Loads d */ + "ldrsh %1, [%3, #2] \n" /* Loads q */ + "ldrsh %2, [%4] \n" /* Loads sin(theta) */ + "ldrsh %3, [%4, #2] \n" /* Loads cos(theta) */ + + "mul %4, %0, %3 \n" /* d * cos(theta) */ + "mls %4, %1, %2, %4 \n" /* d * cos(theta) - q * sin(theta) */ + "ssat %4, #16, %4, asr #15 \n" /* Saturation */ + "mul %1, %1, %3 \n" /* q * cos(theta) */ + "mla %1, %0, %2, %1 \n" /* q * cos(theta) + d * sin(theta) */ + "ssat %1, #16, %1, asr #15 \n" /* Saturation */ + + "strh %4, [%5] \n" /* Stores psOut->f16Alpha */ + "strh %1, [%5, #2] \n" /* Stores psOut->f16Beta */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Val1), "+l"(f32Val2), "+l"(f32Val3), "+l"(psIn), "+l"(psAnglePos): "l"(psOut)); + #endif + + return; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_default=Pe549 +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* _GMCLIB_PARK_F16_ASMI_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Park_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Park_FLT.h new file mode 100644 index 000000000..703f1d0ea --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Park_FLT.h @@ -0,0 +1,146 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Park, Inverse Park Transformation +* +*******************************************************************************/ +#ifndef _GMCLIB_PARK_FLT_H_ +#define _GMCLIB_PARK_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_FP.h" +#include "gmclib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GMCLIB_Park_FLT_Ci(psIn, psAnglePos, psOut) \ + GMCLIB_Park_FLT_FCi(psIn, psAnglePos, psOut) +#define GMCLIB_ParkInv_FLT_Ci(psIn, psAnglePos, psOut) \ + GMCLIB_ParkInv_FLT_FCi(psIn, psAnglePos, psOut) + +/***************************************************************************//*! +* +* @brief The function calculates Park Transformation which is used for +* transforming values (current, voltage, flux) from +* alpha-beta stationary orthogonal coordination system +* to d-q rotating orthogonal coordination system +* +* @param ptr - GMCLIB_2COOR_ALBE_T_FLT *psOut - OUT - pointer to structure containing +* data of two phase stationary orthogonal system +* - GMCLIB_2COOR_DQ_T_FLT *psIn - IN - pointer to structure containing +* data of DQ coordinate two-phase stationary orthogonal system +* - GMCLIB_2COOR_SINCOS_T_FLT *psAnglePos - IN - pointer to structure +* where the values of sine and cosine are stored +* +* @remarks Modifies the structure pointed by pDQ pointer +* according to the following equations +* +* d = alpha * cos(theta) + beta * sin(theta) +* q = beta * cos(theta) - alpha * sin(theta) +* +*******************************************************************************/ +static inline void GMCLIB_Park_FLT_FCi(const GMCLIB_2COOR_ALBE_T_FLT *psIn, + const GMCLIB_2COOR_SINCOS_T_FLT *psAnglePos, + GMCLIB_2COOR_DQ_T_FLT *psOut) +{ + register float_t fltA; + register float_t fltB; + register float_t fltSin; + register float_t fltCos; + + /* Store values for calculation */ + fltA = (psIn->fltAlpha); + fltB = (psIn->fltBeta); + fltSin = (psAnglePos->fltSin); + fltCos = (psAnglePos->fltCos); + + /* Calculate d = alpha * cos(theta) + beta * sin(theta) */ + psOut->fltD = MLIB_Mac4_FLT (fltA, fltCos, fltB, fltSin) ; + + /* Calculate q = beta * cos(theta) - alpha * sin(theta) */ + psOut->fltQ = MLIB_Msu4_FLT (fltB, fltCos, fltA, fltSin) ; +} + +/***************************************************************************//*! +* +* @brief The function calculates Inverse Park Transformation which is used +* for transforming values (current, voltage, flux) from +* d-q rotating orthogonal coordination system to alpha-beta +* stationary orthogonal coordination system. +* +* @param ptr - GMCLIB_2COOR_DQ_T_FLT *psIn - IN - pointer to structure containing +* data of DQ coordinate two-phase stationary orthogonal system +* - GMCLIB_2COOR_SINCOS_T_FLT *psAnglePos - IN - pointer to structure +* where the values of sine and cosine are stored +* - GMCLIB_2COOR_ALBE_T_FLT *psOut - OUT - pointer to structure containing +* data of two phase stationary orthogonal system +* +* @remarks Modifies the structure pointed by pAlphaBeta pointer +* according following equations: +* +* alpha = d * cos(theta) - q * sin(theta) +* beta = d * sin(theta) + q * cos(theta) +* +***********************************1*******************************************/ +static inline void GMCLIB_ParkInv_FLT_FCi(const GMCLIB_2COOR_DQ_T_FLT *psIn, + const GMCLIB_2COOR_SINCOS_T_FLT *psAnglePos, + GMCLIB_2COOR_ALBE_T_FLT *psOut) +{ + register float_t fltD; + register float_t fltQ; + register float_t fltSin; + register float_t fltCos; + + /* Store values for calculation */ + fltD = (psIn->fltD); + fltQ = (psIn->fltQ); + fltSin = (psAnglePos->fltSin); + fltCos = (psAnglePos->fltCos); + + /* Calculate alpha = d * cos(theta) - q * sin(theta) */ + psOut->fltAlpha = MLIB_Msu4_FLT (fltD, fltCos, fltQ, fltSin); + /* Calculate beta = d * sin(theta) + q * cos(theta) */ + psOut->fltBeta = MLIB_Mac4_FLT (fltD, fltSin, fltQ, fltCos); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _GMCLIB_PARK_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Svm_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Svm_F16.h new file mode 100644 index 000000000..d196fa52f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/GMCLIB_Svm_F16.h @@ -0,0 +1,82 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Space vector modulation +* +*******************************************************************************/ +#ifndef _GMCLIB_SVM_F16_H_ +#define _GMCLIB_SVM_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "gmclib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GMCLIB_SvmStd_F16_Asm(psIn, psOut) GMCLIB_SvmStd_F16_FAsm(psIn, psOut) +#define GMCLIB_SvmIct_F16_C(psIn, psOut) GMCLIB_SvmIct_F16_FC(psIn, psOut) +#define GMCLIB_SvmU7n_F16_C(psIn, psOut) GMCLIB_SvmU7n_F16_FC(psIn, psOut) +#define GMCLIB_SvmU0n_F16_C(psIn, psOut) GMCLIB_SvmU0n_F16_FC(psIn, psOut) +#define GMCLIB_SvmDpwm_F16_C(psIn, psOut) GMCLIB_SvmDpwm_F16_FC(psIn, psOut) +#define GMCLIB_SvmExDpwm_F16_C(psIn, psAngle, psOut) GMCLIB_SvmExDpwm_F16_FC(psIn, psAngle,psOut) +/****************************************************************************** +* Types +******************************************************************************/ + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern uint16_t GMCLIB_SvmStd_F16_FAsm(const GMCLIB_2COOR_ALBE_T_F16 *psIn, + GMCLIB_3COOR_T_F16 *psOut); +extern uint16_t GMCLIB_SvmIct_F16_FC(const GMCLIB_2COOR_ALBE_T_F16 *psIn, + GMCLIB_3COOR_T_F16 *psOut); +extern uint16_t GMCLIB_SvmU7n_F16_FC(const GMCLIB_2COOR_ALBE_T_F16 *psIn, + GMCLIB_3COOR_T_F16 *psOut); +extern uint16_t GMCLIB_SvmU0n_F16_FC(const GMCLIB_2COOR_ALBE_T_F16 *psIn, + GMCLIB_3COOR_T_F16 *psOut); +extern uint16_t GMCLIB_SvmDpwm_F16_FC(const GMCLIB_2COOR_ALBE_T_F16 *psIn, + GMCLIB_3COOR_T_F16 *psOut); +extern uint16_t GMCLIB_SvmExDpwm_F16_FC(const GMCLIB_2COOR_ALBE_T_F16 *psIn, + const GMCLIB_2COOR_SINCOS_T_F16 *psAngle, + GMCLIB_3COOR_T_F16 *psOut); +#if defined(__cplusplus) +} +#endif + +#endif /* _GMCLIB_SVM_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/gmclib.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/gmclib.h new file mode 100644 index 000000000..a5578949d --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/gmclib.h @@ -0,0 +1,87 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Main GMCLIB header file for devices without FPU. +* +*******************************************************************************/ +#ifndef _GMCLIB_H_ +#define _GMCLIB_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "GMCLIB_Clark_F16_Asmi.h" +#include "GMCLIB_Decoupling_A32.h" +#include "GMCLIB_ElimDcBusRip_A32_Asmi.h" +#include "GMCLIB_ElimDcBusRip_F16_Asmi.h" +#include "GMCLIB_Park_F16_Asmi.h" +#include "GMCLIB_Svm_F16.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GMCLIB_Clark_F16(psIn, psOut) \ + GMCLIB_Clark_F16_Asmi(psIn, psOut) +#define GMCLIB_ClarkInv_F16(psIn, psOut) \ + GMCLIB_ClarkInv_F16_Asmi(psIn, psOut) +#define GMCLIB_DecouplingPMSM_F16(psUDQ, psIDQ, f16SpeedEl, psParam, psUDQDec) \ + GMCLIB_DecouplingPMSM_F16_Asm(psUDQ, psIDQ, f16SpeedEl, psParam, psUDQDec) +#define GMCLIB_ElimDcBusRip_F16sas(f16UDCBus, a32IdxMod, psUAlBe, psUAlBeComp) \ + GMCLIB_ElimDcBusRip_F16sas_Asmi(f16UDCBus, a32IdxMod, psUAlBe, psUAlBeComp) +#define GMCLIB_ElimDcBusRipFOC_F16(f16UDCBus, psUAlBe, psUAlBeComp) \ + GMCLIB_ElimDcBusRipFOC_F16_Asmi(f16UDCBus, psUAlBe, psUAlBeComp) +#define GMCLIB_Park_F16(psIn, psAnglePos, psOut) \ + GMCLIB_Park_F16_Asmi(psIn, psAnglePos, psOut) +#define GMCLIB_ParkInv_F16(psIn, psAnglePos, psOut) \ + GMCLIB_ParkInv_F16_Asmi(psIn, psAnglePos, psOut) +#define GMCLIB_SvmIct_F16(psIn, psOut) \ + GMCLIB_SvmIct_F16_C(psIn, psOut) +#define GMCLIB_SvmStd_F16(psIn, psOut) \ + GMCLIB_SvmStd_F16_Asm(psIn, psOut) +#define GMCLIB_SvmU0n_F16(psIn, psOut) \ + GMCLIB_SvmU0n_F16_C(psIn, psOut) +#define GMCLIB_SvmU7n_F16(psIn, psOut) \ + GMCLIB_SvmU7n_F16_C(psIn, psOut) +#define GMCLIB_SvmDpwm_F16(psIn, psOut) \ + GMCLIB_SvmDpwm_F16_C(psIn, psOut) +#define GMCLIB_SvmExDpwm_F16(psIn, psAngle, psOut) \ + GMCLIB_SvmExDpwm_F16_C(psIn, psAngle,psOut) + +#if defined(__cplusplus) +} +#endif + +#endif /* _GMCLIB_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/gmclib_FP.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/gmclib_FP.h new file mode 100644 index 000000000..230f33c48 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/gmclib_FP.h @@ -0,0 +1,74 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Main GMCLIB header file for devices with FPU. +* +*******************************************************************************/ +#ifndef _GMCLIB_FP_H_ +#define _GMCLIB_FP_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "gmclib.h" +#include "GMCLIB_Clark_FLT.h" +#include "GMCLIB_Decoupling_FLT.h" +#include "GMCLIB_ElimDcBusRip_FLT.h" +#include "GMCLIB_Park_FLT.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define GMCLIB_Clark_FLT(psIn, psOut) \ + GMCLIB_Clark_FLT_Ci(psIn, psOut) +#define GMCLIB_ClarkInv_FLT(psIn, psOut) \ + GMCLIB_ClarkInv_FLT_Ci(psIn, psOut) +#define GMCLIB_DecouplingPMSM_FLT(psUDQ, psIDQ, fltSpeedEl, psParam, psUDQDec) \ + GMCLIB_DecouplingPMSM_FLT_C(psUDQ, psIDQ, fltSpeedEl, psParam, psUDQDec) +#define GMCLIB_ElimDcBusRip_F16fff(fltUDCBus, fltIdxMod, psUAlBe, psUAlBeComp) \ + GMCLIB_ElimDcBusRip_F16fff_C(fltUDCBus, fltIdxMod, psUAlBe, psUAlBeComp) +#define GMCLIB_ElimDcBusRipFOC_F16ff(fltUDCBus, psUAlBe, psUAlBeComp) \ + GMCLIB_ElimDcBusRipFOC_F16ff_C(fltUDCBus, psUAlBe, psUAlBeComp) +#define GMCLIB_Park_FLT(psIn, psAnglePos, psOut) \ + GMCLIB_Park_FLT_Ci(psIn, psAnglePos, psOut) +#define GMCLIB_ParkInv_FLT(psIn, psAnglePos, psOut) \ + GMCLIB_ParkInv_FLT_Ci(psIn, psAnglePos, psOut) + +#if defined(__cplusplus) +} +#endif + +#endif /* _GMCLIB_FP_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/gmclib_types.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/gmclib_types.h new file mode 100644 index 000000000..78a1c9c4c --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/Include/gmclib_types.h @@ -0,0 +1,186 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief GMCLIB Types +* +*******************************************************************************/ +#ifndef _GMCLIB_TYPES_H_ +#define _GMCLIB_TYPES_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/****************************************************************************** +* Macros +******************************************************************************/ +#define GMCLIB_CONST + +/* GMCLIB_ONE_DIV_SQRT3_F16 define, the value is: 32768 / sqrt(3) = 18919 = 0x49E7 */ +#define GMCLIB_ONE_DIV_SQRT3_F16 (frac16_t)18919 +/* GMCLIB_SQRT3_DIV_2_F16 define, the value is: 32768 * sqrt(3) / 2 = 28378 = 0x6EDA */ +#define GMCLIB_SQRT3_DIV_2_F16 (frac16_t)28378 + +/* GMCLIB_ONE_DIV_SQRT3_FLT define, the value is: 0.5773502691896258 */ +#define GMCLIB_ONE_DIV_SQRT3_FLT (float_t) 0.5773502691896258F +/* GMCLIB_SQRT3_FLT define, the value is: 0.8660254037844390 */ +#define GMCLIB_SQRT3_DIV_2_FLT (float_t) 0.8660254037844390F +/* GMCLIB_SQRT3_DIVBY_2_FLT define, the value is: 1.7320508075688800 */ +#define GMCLIB_SQRT3_FLT (float_t) 1.7320508075688800F + +/******************************************************************************* +* Types +********************************************************************************/ +/* Integer data types */ + +/* The GMCLIB_3COOR_T_F16 structure type corresponds to the three-phase stationary +coordinate system based on the A, B, C components. */ +typedef struct +{ + frac16_t f16A; + frac16_t f16B; + frac16_t f16C; +} GMCLIB_3COOR_T_F16; + +/* The GMCLIB_2COOR_ALBE_T_F16 structure type corresponds to the two-phase +stationary coordinate system based on the Alpha and Beta orthogonal components. */ +typedef struct +{ + frac16_t f16Alpha; + frac16_t f16Beta; +} GMCLIB_2COOR_ALBE_T_F16; + +/* The GMCLIB_2COOR_DQ_T_F16 structure type corresponds to the two-phase rotating +coordinate system based on the D and Q orthogonal components. */ +typedef struct +{ + frac16_t f16D; + frac16_t f16Q; +} GMCLIB_2COOR_DQ_T_F16; + +/* The GMCLIB_2COOR_SINCOS_T_F16 structure type corresponds to the two-phase +coordinate system based on the Sin and Cos components of certain angle. */ +typedef struct +{ + frac16_t f16Sin; + frac16_t f16Cos; +} GMCLIB_2COOR_SINCOS_T_F16; + +/* The GMCLIB_2COOR_DQ_T_F32 structure type corresponds to the two-phase rotating +coordinate system based on the D and Q orthogonal components. */ +typedef struct +{ + frac32_t f32D; + frac32_t f32Q; +} GMCLIB_2COOR_DQ_T_F32; + +/* The GMCLIB_2COOR_ALBE_T_F16 structure type corresponds to the two-phase +stationary coordinate system based on the Alpha and Beta orthogonal components. */ +typedef struct +{ + frac32_t f32Alpha; + frac32_t f32Beta; +} GMCLIB_2COOR_ALBE_T_F32; + +/* The GMCLIB_2COOR_AB_T_F16 structure type corresponds to the two-phase stationary +coordinate system based on the A and B components. */ + +typedef struct +{ + frac16_t f16A; /* First argument */ + frac16_t f16B; /* Second argument */ +} GMCLIB_2COOR_AB_T_F16; + +/* The GMCLIB_2COOR_AB_T_F32 structure type corresponds to the two-phase stationary +coordinate system based on the A and B components. */ + +typedef struct +{ + frac32_t f32A; /* First argument */ + frac32_t f32B; /* Second argument */ +} GMCLIB_2COOR_AB_T_F32; + + +/* Floating point data types */ + +/* The GMCLIB_3COOR_T_FLT structure type corresponds to the three-phase stationary +coordinate system based on the A, B, C components. */ +typedef struct +{ + float_t fltA; + float_t fltB; + float_t fltC; +} GMCLIB_3COOR_T_FLT; + +/* The GMCLIB_2COOR_ALBE_T_FLT structure type corresponds to the two-phase +stationary coordinate system based on the Alpha and Beta orthogonal components. */ +typedef struct +{ + float_t fltAlpha; + float_t fltBeta; +} GMCLIB_2COOR_ALBE_T_FLT; + +/* The GMCLIB_2COOR_DQ_T_FLT structure type corresponds to the two-phase rotating +coordinate system based on the D and Q orthogonal components. */ +typedef struct +{ + float_t fltD; + float_t fltQ; +} GMCLIB_2COOR_DQ_T_FLT; + +/* The GMCLIB_2COOR_SINCOS_T_FLT structure type corresponds to the two-phase +coordinate system based on the Sin and Cos components of certain angle. */ +typedef struct +{ + float_t fltSin; + float_t fltCos; +} GMCLIB_2COOR_SINCOS_T_FLT; + +/* The GMCLIB_2COOR_AB_T_F32 structure type corresponds to the two-phase stationary +coordinate system based on the A and B components. */ + +typedef struct +{ + float_t fltA; /* First argument */ + float_t fltB; /* Second argument */ +} GMCLIB_2COOR_AB_T_FLT; + +#if defined(__cplusplus) +} +#endif + +#endif /* _GMCLIB_TYPES_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/libGMCLIB.a b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/libGMCLIB.a new file mode 100644 index 000000000..64ef99a1d Binary files /dev/null and b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/GMCLIB/libGMCLIB.a differ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_F16.h new file mode 100644 index 000000000..10cc87b62 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_F16.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Absolute Value +* +*******************************************************************************/ +#ifndef _MLIB_ABS_F16_H_ +#define _MLIB_ABS_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Abs_F16_Ci(f16Val) MLIB_Abs_F16_FCi(f16Val) + +/***************************************************************************//*! +* Absolute value +* f16Out = |f16In| +* not saturated +*******************************************************************************/ +static inline frac16_t MLIB_Abs_F16_FCi(register frac16_t f16Val) +{ + return((f16Val < (frac16_t)0) ? (-f16Val) : (f16Val)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /*_MLIB_ABS_F16_H_*/ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_F16_Asmi.h new file mode 100644 index 000000000..fe4713e11 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_F16_Asmi.h @@ -0,0 +1,91 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Absolute Value +* +*******************************************************************************/ +#ifndef _MLIB_ABS_F16_ASM_H_ +#define _MLIB_ABS_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_AbsSat_F16_Asmi(f16Val) MLIB_AbsSat_F16_FAsmi(f16Val) + +/***************************************************************************//*! +* Absolute value saturated +* f16Out = |f16In| +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_AbsSat_F16_FAsmi(register frac16_t f16Val) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ lsls f16Val, f16Val, #16 /* f16Val << 16 */ + it mi /* If f16Val < 0, then implements next command */ + rsbmi f16Val, f16Val, #0 /* If f16Val < 0, then f16Val = 0 - f16Val */ + lsr f16Val, f16Val, #16 /* f16Val >> 16 */ + usat f16Val, #15, f16Val }; /* Saturates the result */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "lsls %0, %0, #16 \n" /* f16Val << 16 */ + "it mi \n" /* If f16Val < 0, then implements next command */ + "rsbmi %0, %0, #0 \n" /* If f16Val < 0, then f16Val = 0 - f16Val */ + "lsr %0, %0, #16 \n" /* f16Val >> 16 */ + "usat %0, #15, %0 \n" /* Saturates the result */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Val):); + #endif + + return f16Val; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /*_MLIB_ABS_F16_ASM_H_*/ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_F32.h new file mode 100644 index 000000000..6710dc467 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_F32.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Absolute Value +* +*******************************************************************************/ +#ifndef _MLIB_ABS_F32_H_ +#define _MLIB_ABS_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Abs_F32_Ci(f32Val) MLIB_Abs_F32_FCi(f32Val) + +/***************************************************************************//*! +* Absolute value +* f32Out = |f32In| +* not saturated +*******************************************************************************/ +static inline frac32_t MLIB_Abs_F32_FCi(register frac32_t f32Val) +{ + return((f32Val < (frac32_t)0) ? (-f32Val) : (f32Val)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_ABS_F32_H_*/ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_F32_Asmi.h new file mode 100644 index 000000000..fdb798432 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_F32_Asmi.h @@ -0,0 +1,91 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Absolute Value +* +*******************************************************************************/ +#ifndef _MLIB_ABS_F32_ASM_H_ +#define _MLIB_ABS_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_AbsSat_F32_Asmi(f32Val) MLIB_AbsSat_F32_FAsmi(f32Val) + +/***************************************************************************//*! +* Absolute value saturated +* f32Out = |f32In| +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_AbsSat_F32_FAsmi(register frac32_t f32Val) +{ + register frac32_t f32Temp = 1; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ cmp f32Val, #0 /* Compares f32Val with 0 */ + itt lt /* If f32Val < 0, then executes next two commands */ + mvnlt f32Val, f32Val /* f32Val = ~f32Val */ + qaddlt f32Val, f32Val, f32Temp }; /* f32Val = f32Val + 1 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "cmp %0, #0 \n" /* Compares f32Val with 0 */ + "itt lt \n" /* If f32Val < 0, then executes next two commands */ + "mvnlt %0, %0 \n" /* f32Val = ~f32Val */ + "qaddlt %0, %0, %1 \n" /* f32Val = f32Val + 1 */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Val): "l"(f32Temp)); + #endif + + return f32Val; +} +RTCESL_INLINE_OPTIM_RESTORE + + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_ABS_F32_ASM_H_*/ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_FLT.h new file mode 100644 index 000000000..bc384d04c --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_FLT.h @@ -0,0 +1,68 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Absolute Value +* +*******************************************************************************/ +#ifndef _MLIB_ABS_FLT_H_ +#define _MLIB_ABS_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Neg_FLT.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Abs_FLT_Ci(fltVal) MLIB_Abs_FLT_FCi(fltVal) + +/***************************************************************************//*! +* Absolute value +* fltOut = |fltIn| +* The output saturation is not implemented. +*******************************************************************************/ +static inline float_t MLIB_Abs_FLT_FCi(register float_t fltVal) +{ + return((fltVal < (float_t)0) ? (MLIB_Neg_FLT_FCi(fltVal)) : (fltVal)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_ABS_FLT_H_*/ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_FLT_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_FLT_Asmi.h new file mode 100644 index 000000000..23859d952 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Abs_FLT_Asmi.h @@ -0,0 +1,84 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Absolute Value +* +*******************************************************************************/ +#ifndef _MLIB_ABS_FLT_ASMI_H_ +#define _MLIB_ABS_FLT_ASMI_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Abs_FLT_Asmi(fltVal) MLIB_Abs_FLT_FAsmi(fltVal) + +/***************************************************************************//*! +* Absolute value +* fltOut = |fltIn| +* The output saturation is not implemented. +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline float_t MLIB_Abs_FLT_FAsmi(register float_t fltVal) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ vabs.f32 fltVal, fltVal }; /* Absolute value */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vabs.f32 %0, %0 \n" + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+t"(fltVal):); + #endif + + return fltVal; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_ABS_FLT_ASMI_H_*/ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add4_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add4_F16_Asmi.h new file mode 100644 index 000000000..0c96a8980 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add4_F16_Asmi.h @@ -0,0 +1,131 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Summation of four inputs +* +*******************************************************************************/ +#ifndef _MLIB_ADD4_F16_ASM_H_ +#define _MLIB_ADD4_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Add4_F16_Asmi(f16Add1, f16Add2, f16Add3, f16Add4) \ + MLIB_Add4_F16_FAsmi(f16Add1, f16Add2, f16Add3, f16Add4) +#define MLIB_Add4Sat_F16_Asmi(f16Add1, f16Add2, f16Add3, f16Add4) \ + MLIB_Add4Sat_F16_FAsmi(f16Add1, f16Add2, f16Add3, f16Add4) + +/***************************************************************************//*! +* Summation of four inputs +* f16Out = f16Add1 + f16Add2 + f16Add3 + f16Add4 +* function is not saturated +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Add4_F16_FAsmi(register frac16_t f16Add1, register frac16_t f16Add2, + register frac16_t f16Add3, register frac16_t f16Add4) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{add f16Add1, f16Add1, f16Add2 /* f16Add1 = f16Add1 + f16Add2 */ + add f16Add1, f16Add1, f16Add3 /* f16Add1 = f16Add1 + f16Add3 */ + add f16Add1, f16Add1, f16Add4}; /* f16Add1 = f16Add1 + f16Add4 */ + + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "add %0, %0, %1 \n" /* f16Add1 = f16Add1 + f16Add2 */ + "add %0, %0, %2 \n" /* f16Add1 = f16Add1 + f16Add3 */ + "add %0, %0, %3 \n" /* f16Add1 = f16Add1 + f16Add4 */ + : "+l"(f16Add1): "l"(f16Add2), "l"(f16Add3), "l"(f16Add4)); + #endif + + return f16Add1; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* Saturated summation of four inputs +* f16Out = f16Add1 + f16Add2 + f16Add3 + f16Add4 +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Add4Sat_F16_FAsmi(register frac16_t f16Add1, register frac16_t f16Add2, + register frac16_t f16Add3, register frac16_t f16Add4) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Add1, f16Add1 /* Transforms 16-bit input f16Val to 32-bit */ + sxth f16Add2, f16Add2 /* Transforms 16-bit input f16Val to 32-bit */ + sxth f16Add3, f16Add3 /* Transforms 16-bit input f16Val to 32-bit */ + sxth f16Add4, f16Add4 /* Transforms 16-bit input f16Val to 32-bit */ + add f16Add1, f16Add1, f16Add3 /* f16Add1 + f16Add3 */ + add f16Add2, f16Add2, f16Add4 /* f16Add2 + f16Add4 */ + add f16Add1, f16Add1, f16Add2 /* f16Add1 + f16Add3 + f16Add2 + f16Add4 */ + ssat f16Add1, #16, f16Add1 }; /* Saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "sxth %1, %1 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "sxth %2, %2 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "sxth %3, %3 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "add %0, %0, %2 \n" /* f16Add1 + f16Add3 */ + "add %1, %1, %3 \n" /* f16Add2 + f16Add4 */ + "add %0, %0, %1 \n" /* f16Add1 + f16Add3 + f16Add2 + f16Add4 */ + "ssat %0, #16, %0 \n" /* Saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Add1), "+l"(f16Add2), "+l"(f16Add3), "+l"(f16Add4):); + #endif + + return f16Add1; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_ADD4_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add4_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add4_F32_Asmi.h new file mode 100644 index 000000000..c400de63f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add4_F32_Asmi.h @@ -0,0 +1,168 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Summation of four inputs +* +*******************************************************************************/ +#ifndef _MLIB_ADD4_F32_ASM_H_ +#define _MLIB_ADD4_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Add4_F32_Asmi(f32Add1, f32Add2, f32Add3, f32Add4) \ + MLIB_Add4_F32_FAsmi(f32Add1, f32Add2, f32Add3, f32Add4) +#define MLIB_Add4Sat_F32_Asmi(f32Add1, f32Add2, f32Add3, f32Add4) \ + MLIB_Add4Sat_F32_FAsmi(f32Add1, f32Add2, f32Add3, f32Add4) + +/***************************************************************************//*! +* Summation of four inputs +* f32Out = f32Add1 + f32Add2 + f32Add3 + f32Add4 +* function is not saturated +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Add4_F32_FAsmi(register frac32_t f32Add1, register frac32_t f32Add2, + register frac32_t f32Add3, register frac32_t f32Add4) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ add f32Add1, f32Add1, f32Add2 /* f32Add1 = f32Add1 + f32Add2 */ + add f32Add1, f32Add1, f32Add3 /* f32Add1 = f32Add1 + f32Add3 */ + add f32Add1, f32Add1, f32Add4};/* f32Add1 = f32Add1 + f32Add4 */ + + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "add %0, %0, %1 \n" /* f32Add1 = f32Add1 + f32Add2 */ + "add %0, %0, %2 \n" /* f32Add1 = f32Add1 + f32Add3 */ + "add %0, %0, %3 \n" /* f32Add1 = f32Add1 + f32Add4 */ + : "+l"(f32Add1): "l"(f32Add2), "l"(f32Add3), "l"(f32Add4)); + #endif + + return f32Add1; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* Saturated summation of four inputs +* f32Out = f32Add1 + f32Add2 + f32Add3 + f32Add4 +*******************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_suppress=Pe549 /* Suppresses the Pe549 warning for IAR compiler*/ +#endif +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Add4Sat_F32_FAsmi(register frac32_t f32Add1, register frac32_t f32Add2, + register frac32_t f32Add3, register frac32_t f32Add4) +{ + register frac32_t f32Sign1=0, f32Sign2=0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ asr f32Sign1, f32Add1, #31 /* f32Sign1 = sign of f32Add1 */ + asr f32Sign2, f32Add2, #31 /* f32Sign2 = sign of f32Add2 */ + adds f32Add1, f32Add1, f32Add2 /* f32Add1 + f32Add2 */ + adc f32Sign1, f32Sign1, f32Sign2 /* f32Sign1 + f32Sign2 + Carry */ + + asr f32Sign2, f32Add3, #31 /* f32Sign2 = sign of f32Add3 */ + adds f32Add1, f32Add1, f32Add3 /* f32Add1 + f32Add2 + f32Add3 */ + adc f32Sign1, f32Sign1, f32Sign2 /* f32Sign1 + f32Sign2 + Carry */ + + asr f32Sign2, f32Add4, #31 /* f32Sign2 = sign of f32Add4 */ + adds f32Add1, f32Add1, f32Add4 /* f32Add1 + f32Add2 + f32Add3 + f32Add4 */ + adc f32Sign1, f32Sign1, f32Sign2 /* f32Sign1 + f32Sign2 + Carry */ + + mov f32Sign2, #0x80000000 /* f32Sign2 = 0x80000000 */ + + lsr f32Add2, f32Add1, #31 /* First bit of low part of result */ + adds f32Sign1, f32Sign1, f32Add2 + + it gt /* If f32Sign1 > 0, then executes next command */ + subgt f32Add1, f32Sign2, #1 /* Result = 0x7FFFFFFF*/ + + it lt /* If f32Sign1 > 0, then executes next command */ + movlt f32Add1, f32Sign2 }; /* Result = 0x80000000*/ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "asr %0, %2, #31 \n" /* f32Sign1 = sign of f32Add1 */ + "asr %1, %3, #31 \n" /* f32Sign2 = sign of f32Add2 */ + "adds %2, %2, %3 \n" /* f32Add1 + f32Add2 */ + "adc %0, %0, %1 \n" /* f32Sign1 + f32Sign2 + Carry */ + + "asr %1, %4, #31 \n" /* f32Sign2 = sign of f32Add3 */ + "adds %2, %2, %4 \n" /* f32Add1 + f32Add2 + f32Add3 */ + "adc %0, %0, %1 \n" /* f32Sign1 + f32Sign2 + Carry */ + + "asr %1, %5, #31 \n" /* f32Sign2 = sign of f32Add4 */ + "adds %2, %2, %5 \n" /* f32Add1 + f32Add2 + f32Add3 + f32Add4 */ + "adc %0, %0, %1 \n" /* f32Sign1 + f32Sign2 + Carry */ + + "mov %1, #0x80000000 \n" /* f32Sign2 = 0x80000000 */ + "lsr %3, %2, #31 \n" /* First bit of low part of result */ + "adds %0, %0, %3 \n" + + "it gt \n" /* If f32Sign1 > 0, then executes next command */ + "subgt %2, %1, #1 \n" /* Result = 0x7FFFFFFF*/ + + "it lt \n" /* If f32Sign1 > 0, then executes next command */ + "movlt %2, %1 \n" /* Result = 0x80000000*/ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Sign1), "+l"(f32Sign2), "+l"(f32Add1), "+l"(f32Add2): "l"(f32Add3), "l"(f32Add4) ); + #endif + + return f32Add1; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_default=Pe549 +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_ADD4_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add4_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add4_FLT.h new file mode 100644 index 000000000..786152631 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add4_FLT.h @@ -0,0 +1,69 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Summation of four inputs +* +*******************************************************************************/ +#ifndef _MLIB_ADD4_FLT_H_ +#define _MLIB_ADD4_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Add4_FLT_Ci(fltAdd1, fltAdd2, fltAdd3, fltAdd4) \ + MLIB_Add4_FLT_FCi(fltAdd1, fltAdd2, fltAdd3, fltAdd4) + +/***************************************************************************//*! +* Summation of four inputs +* fltOut = fltAdd1 + fltAdd2 + fltAdd3 + fltAdd4 +* The output saturation is not implemented. +*******************************************************************************/ +static inline float_t MLIB_Add4_FLT_FCi(register float_t fltAdd1, register float_t fltAdd2, + register float_t fltAdd3, register float_t fltAdd4) +{ + return((float_t)(fltAdd1 + fltAdd2 + fltAdd3 + fltAdd4)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_ADD4_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_A32.h new file mode 100644 index 000000000..0b3d54842 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_A32.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Addition +* +*******************************************************************************/ +#ifndef _MLIB_ADD_A32_H_ +#define _MLIB_ADD_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Add_A32ss_Ci(f16Add1, f16Add2) MLIB_Add_A32ss_FCi(f16Add1, f16Add2) +#define MLIB_Add_A32as_Ci(a32Accum, f16Add) MLIB_Add_A32as_FCi(a32Accum, f16Add) + +/***************************************************************************//*! +* Addition +* a32Out = f16Add1 + f16Add2 +* Result can overflow through fractional range and is stored in accumulator type +*******************************************************************************/ +static inline acc32_t MLIB_Add_A32ss_FCi(register frac16_t f16Add1, register frac16_t f16Add2) +{ + return((acc32_t)((acc32_t)f16Add1 + (acc32_t)f16Add2)); +} + +/***************************************************************************//*! +* Addition +* a32Out = a32Accum + f16Add +* Result can overflow through fractional range and is stored in accumulator type +*******************************************************************************/ +static inline acc32_t MLIB_Add_A32as_FCi(register acc32_t a32Accum, register frac16_t f16Add) +{ + return((acc32_t)(a32Accum + (acc32_t)(f16Add))); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_ADD_A32_H_*/ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_F16.h new file mode 100644 index 000000000..081cfbd9f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_F16.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Addition +* +*******************************************************************************/ +#ifndef _MLIB_ADD_F16_H_ +#define _MLIB_ADD_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Add_F16_Ci(f16Add1, f16Add2) MLIB_Add_F16_FCi(f16Add1, f16Add2) + +/***************************************************************************//*! +* Addition +* f16Out = f16Add1 + f16Add2 +* function is not saturated +*******************************************************************************/ +static inline frac16_t MLIB_Add_F16_FCi(register frac16_t f16Add1, register frac16_t f16Add2) +{ + return((frac16_t)(f16Add1 + f16Add2)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /*_MLIB_ADD_F16_H_*/ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_F16_Asmi.h new file mode 100644 index 000000000..99861b4bd --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_F16_Asmi.h @@ -0,0 +1,83 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Addition +* +*******************************************************************************/ +#ifndef _MLIB_ADD_F16_ASM_H_ +#define _MLIB_ADD_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_AddSat_F16_Asmi(f16Add1, f16Add2) MLIB_AddSat_F16_FAsmi(f16Add1, f16Add2) + +/***************************************************************************//*! +* Saturated Addition +* f16Out = f16Add1 + f16Add2 +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_AddSat_F16_FAsmi(register frac16_t f16Add1, register frac16_t f16Add2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ qadd16 f16Add1, f16Add1, f16Add2}; /* Adds with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "qadd16 %0, %0, %1 \n" /* Adds with saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Add1): "l"(f16Add2)); + #endif + + return f16Add1; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /*_MLIB_ADD_F16_ASM_H_*/ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_F32.h new file mode 100644 index 000000000..63df4e261 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_F32.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Addition +* +*******************************************************************************/ +#ifndef _MLIB_ADD_F32_H_ +#define _MLIB_ADD_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Add_F32_Ci(f32Add1, f32Add2) MLIB_Add_F32_FCi(f32Add1, f32Add2) + +/***************************************************************************//*! +* Addition +* f32Out = f32Add1 + f32Add2 +* function is not saturated +*******************************************************************************/ +static inline frac32_t MLIB_Add_F32_FCi(register frac32_t f32Add1, register frac32_t f32Add2) +{ + return((frac32_t)(f32Add1 + f32Add2)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_ADD_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_F32_Asmi.h new file mode 100644 index 000000000..070aee293 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_F32_Asmi.h @@ -0,0 +1,84 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Addition +* +*******************************************************************************/ +#ifndef _MLIB_ADD_F32_ASM_H_ +#define _MLIB_ADD_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_AddSat_F32_Asmi(f32Add1, f32Add2) MLIB_AddSat_F32_FAsmi(f32Add1, f32Add2) + +/***************************************************************************//*! +* Saturated Addition +* f32Out = f32Add1 + f32Add2 +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_AddSat_F32_FAsmi(register frac32_t f32Add1, register frac32_t f32Add2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ qadd f32Add1, f32Add1, f32Add2}; /* Adds with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "qadd %0, %0, %1 \n" /* Adds with saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Add1): "l"(f32Add2)); + #endif + + return f32Add1; +} +RTCESL_INLINE_OPTIM_RESTORE + + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_ADD_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_FLT.h new file mode 100644 index 000000000..c43fc7641 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Add_FLT.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Addition +* +*******************************************************************************/ +#ifndef _MLIB_ADD_FLT_H_ +#define _MLIB_ADD_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Add_FLT_Ci(fltAdd1, fltAdd2) MLIB_Add_FLT_FCi(fltAdd1, fltAdd2) + +/***************************************************************************//*! +* Addition +* fltOut = fltAdd1 + fltAdd2 +* The output saturation is not implemented. +*******************************************************************************/ +static inline float_t MLIB_Add_FLT_FCi(register float_t fltAdd1, register float_t fltAdd2) +{ + return((float_t)(fltAdd1 + fltAdd2)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_ADD_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_BiShift_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_BiShift_F16.h new file mode 100644 index 000000000..e521a3bb0 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_BiShift_F16.h @@ -0,0 +1,114 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Shift +* +*******************************************************************************/ +#ifndef _MLIB_BISHIFT_F16_H_ +#define _MLIB_BISHIFT_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F16.h" +#include "MLIB_Shift_F16_Asmi.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_ShLBi_F16_Ci(f16Val, i16Sh) MLIB_ShLBi_F16_FCi(f16Val, i16Sh) +#define MLIB_ShLBiSat_F16_Ci(f16Val, i16Sh) MLIB_ShLBiSat_F16_FCi(f16Val, i16Sh) +#define MLIB_ShRBi_F16_Ci(f16Val, i16Sh) MLIB_ShRBi_F16_FCi(f16Val, i16Sh) +#define MLIB_ShRBiSat_F16_Ci(f16Val, i16Sh) MLIB_ShRBiSat_F16_FCi(f16Val, i16Sh) + +/***************************************************************************//*! +* +* This function returns the f16Val input shifted by the number of i16Sh to the left. +* If the i16Sh is negative, the input is shifted to the right. The function +* does not saturate the output. +* +*******************************************************************************/ +static inline frac16_t MLIB_ShLBi_F16_FCi(register frac16_t f16Val, register int16_t i16Sh) +{ + return (i16Sh<(int16_t)0) ? MLIB_ShR_F16_Ci(f16Val, (uint16_t)(-i16Sh)) : + MLIB_ShL_F16_Ci(f16Val, (uint16_t)(i16Sh)); +} + +/***************************************************************************//*! +* +* This function returns the f16Val input shifted by the number of i16Sh to the left. +* If the i16Sh is negative, the input is shifted to the right. The function +* saturates the output. +* +*******************************************************************************/ +static inline frac16_t MLIB_ShLBiSat_F16_FCi(register frac16_t f16Val, register int16_t i16Sh) +{ + return (i16Sh<(int16_t)0) ? MLIB_ShR_F16_Ci(f16Val, (uint16_t)(-i16Sh)) : + MLIB_ShLSat_F16_Asmi(f16Val, (uint16_t)(i16Sh)); +} + +/***************************************************************************//*! +* +* This function returns the f16Val input shifted by the number of i16Sh to the right. +* If the i16Sh is negative, the input is shifted to the left. The function +* does not saturate the output. +* +*******************************************************************************/ +static inline frac16_t MLIB_ShRBi_F16_FCi(register frac16_t f16Val, register int16_t i16Sh) +{ + return (i16Sh<(int16_t)0) ? MLIB_ShL_F16_Ci(f16Val, (uint16_t)(-i16Sh)) : + MLIB_ShR_F16_Ci(f16Val, (uint16_t)(i16Sh)); +} + +/***************************************************************************//*! +* +* This function returns the f16Val input shifted by the number of i16Sh to the right. +* If the i16Sh is negative, the input is shifted to the left. The function +* saturates the output. +* +*******************************************************************************/ +static inline frac16_t MLIB_ShRBiSat_F16_FCi(register frac16_t f16Val, register int16_t i16Sh) +{ + return (i16Sh<(int16_t)0) ? MLIB_ShLSat_F16_Asmi(f16Val, (uint16_t)(-i16Sh)) : + MLIB_ShR_F16_Ci(f16Val, (uint16_t)(i16Sh)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_BISHIFT_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_BiShift_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_BiShift_F32.h new file mode 100644 index 000000000..bcc7d4e31 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_BiShift_F32.h @@ -0,0 +1,115 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Shift +* +*******************************************************************************/ +#ifndef _MLIB_BISHIFT_F32_H_ +#define _MLIB_BISHIFT_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F32.h" +#include "MLIB_Shift_F32_Asmi.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_ShLBi_F32_Ci(f32Val, i16Sh) MLIB_ShLBi_F32_FCi(f32Val, i16Sh) +#define MLIB_ShLBiSat_F32_Ci(f32Val, i16Sh) MLIB_ShLBiSat_F32_FCi(f32Val, i16Sh) +#define MLIB_ShRBi_F32_Ci(f32Val, i16Sh) MLIB_ShRBi_F32_FCi(f32Val, i16Sh) +#define MLIB_ShRBiSat_F32_Ci(f32Val, i16Sh) MLIB_ShRBiSat_F32_FCi(f32Val, i16Sh) + +/***************************************************************************//*! +* +* This function returns the f32Val input shifted by the number of i16Sh to the left. +* If the i16Sh is negative, the input is shifted to the right. The function +* does not saturate the output. +* +*******************************************************************************/ +static inline frac32_t MLIB_ShLBi_F32_FCi(register frac32_t f32Val, register int16_t i16Sh) +{ + return (i16Sh<(int16_t)0) ? MLIB_ShR_F32_Ci(f32Val, (uint16_t)(-i16Sh)) : + MLIB_ShL_F32_Ci(f32Val, (uint16_t)(i16Sh)); +} + +/***************************************************************************//*! +* +* This function returns the f32Val input shifted by the number of i16Sh to the left. +* If the i16Sh is negative, the input is shifted to the right. The function +* saturates the output. +* +*******************************************************************************/ +static inline frac32_t MLIB_ShLBiSat_F32_Ci(register frac32_t f32Val, register int16_t i16Sh) +{ + return (i16Sh<(int16_t)0) ? MLIB_ShR_F32_Ci(f32Val, (uint16_t)(-i16Sh)) : + MLIB_ShLSat_F32_Asmi(f32Val, (uint16_t)(i16Sh)); +} + +/***************************************************************************//*! +* +* This function returns the f32Val input shifted by the number of i16Sh to the right. +* If the i16Sh is negative, the input is shifted to the left. The function +* does not saturate the output. +* +*******************************************************************************/ +static inline frac32_t MLIB_ShRBi_F32_FCi(register frac32_t f32Val, register int16_t i16Sh) +{ + return (i16Sh<(int16_t)0) ? MLIB_ShL_F32_Ci(f32Val, (uint16_t)(-i16Sh)) : + MLIB_ShR_F32_Ci(f32Val, (uint16_t)(i16Sh)); +} + +/***************************************************************************//*! +* +* This function returns the f32Val input shifted by the number of i16Sh to the right. +* If the i16Sh is negative, the input is shifted to the left. The function +* saturates the output. +* +*******************************************************************************/ +static inline frac32_t MLIB_ShRBiSat_F32_FCi(register frac32_t f32Val, register int16_t i16Sh) +{ + + return (i16Sh<(int16_t)0) ? MLIB_ShLSat_F32_Asmi(f32Val, (uint16_t)(-i16Sh)) : + MLIB_ShR_F32_Ci(f32Val, (uint16_t)(i16Sh)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_BISHIFT_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Clb_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Clb_F16.h new file mode 100644 index 000000000..ef585372a --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Clb_F16.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Count of leading bits +* +*******************************************************************************/ +#ifndef _MLIB_CLB_F16_H_ +#define _MLIB_CLB_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#define _clz(x) __CLZ(x) +#else +#define _clz(x) __builtin_clz(x) +#endif +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Clb_U16s_Ci(f16Val) MLIB_Clb_U16s_FCi(f16Val) + +/***************************************************************************//*! +* +* @brief This function returns the number of left shifts needed to normalize the 16-bit input. +* +* @param in frac16_t f16Num +* - Argument in [-1;1) in frac16_t +* +* @return This function returns +* - uint16_t value +* +* @remarks Depending on the sign of the input value the function counts and returns the +* number of the left shift needed to get an equality between input value and +* the maximum fractional values "1" or "-1". For the input "0" returns "0". +* +****************************************************************************/ +static inline uint16_t MLIB_Clb_U16s_FCi(register frac16_t f16Val) +{ + register frac16_t f16Temp; + register uint16_t u16Temp; + + if (f16Val == 0) + { return 0U; + } + else + { f16Temp = (frac16_t)MLIB_AbsSat_F16_Asmi(f16Val); + u16Temp = (uint16_t)f16Temp; + u16Temp = (uint16_t)_clz(u16Temp) - 0x11U; + return u16Temp; + } +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_CLB_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Clb_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Clb_F32.h new file mode 100644 index 000000000..8caf2410f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Clb_F32.h @@ -0,0 +1,93 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Count of leading bits +* +*******************************************************************************/ +#ifndef _MLIB_CLB_F32_H_ +#define _MLIB_CLB_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Abs_F32_Asmi.h" + +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#define _clzl(x) __CLZ(x) +#else +#define _clzl(x) __builtin_clzl(x) +#endif +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Clb_U16l_Ci(f32Val) MLIB_Clb_U16l_FCi(f32Val) + +/***************************************************************************//*! +* +* @brief This function returns the number of left shifts needed to normalize the 16-bit input. +* +* @param in frac32_t f32Num +* - Argument in [-1;1) in frac32_t +* +* @return This function returns +* - uint16_t value +* +* @remarks Depending on the sign of the input value the function counts and returns the +* number of the left shift needed to get an equality between input value and +* the maximum fractional values "1" or "-1". For the input "0" returns "0". +* +****************************************************************************/ +static inline uint16_t MLIB_Clb_U16l_FCi(register frac32_t f32Val) +{ + register frac32_t f32Temp; + register uint32_t u32Temp; + + if (f32Val == 0) + { return 0U; + } + else + { f32Temp = (frac32_t)MLIB_AbsSat_F32_Asmi(f32Val); + u32Temp = (uint32_t)f32Temp; + return (uint16_t)_clzl(u32Temp) - 0x1U; + } +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_CLB_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_ConvSc_FLT_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_ConvSc_FLT_Asmi.h new file mode 100644 index 000000000..eaaf02bdf --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_ConvSc_FLT_Asmi.h @@ -0,0 +1,342 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Conversion functions +* +*******************************************************************************/ +#ifndef _MLIB_CONVSC_FLT_ASMI_H_ +#define _MLIB_CONVSC_FLT_ASMI_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_ConvSc_FLTsf_Asmi(f16Val, fltSc) MLIB_ConvSc_FLTsf_FAsmi(f16Val, fltSc) +#define MLIB_ConvSc_FLTlf_Asmi(f32Val, fltSc) MLIB_ConvSc_FLTlf_FAsmi(f32Val, fltSc) +#define MLIB_ConvSc_F16ff_Asmi(fltVal, fltSc) MLIB_ConvSc_F16ff_FAsmi(fltVal, fltSc) +#define MLIB_ConvSc_F32ff_Asmi(fltVal, fltSc) MLIB_ConvSc_F32ff_FAsmi(fltVal, fltSc) +#define MLIB_ConvSc_A32ff_Asmi(fltVal, fltSc) MLIB_ConvSc_A32ff_FAsmi(fltVal, fltSc) +#define MLIB_ConvSc_FLTaf_Asmi(a32Val, fltSc) MLIB_ConvSc_FLTaf_FAsmi(a32Val, fltSc) + +/***************************************************************************//*! +* 16-bit fractional to float convert function +* +* @param in float_t f16Val +* - Argument in frac16_t <-1;1) +* float_t fltSc +* - Argument in float_t +* +* @return This function returns +* - float_t value +* +* @remarks This inline function returns converted input value. The input value +* is considered as 16-bit fractional and float data types and output value is +* considered as single precision floating point data type. The input value +* represents the values in unity model. The second value represents the scale +* factor and is considered as single precision float data type and determine the +* scale conversion +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline float_t MLIB_ConvSc_FLTsf_FAsmi(register frac16_t f16Val, + register float_t fltSc) +{ + register float_t fltOut=0.0f; + + #if defined(__CC_ARM) /* For ARM Compiler */ + register float_t fltConv = 1.0f/32768.0f; + __asm volatile{ vmov fltOut, f16Val /* fltOut = f16Val */ + vcvt.f32.s32 fltOut, fltOut /* Converts from integer to float */ + vmul.f32 fltOut, fltOut, fltConv /* fltOut = fltOut / 32768.0f */ + vmul.f32 fltOut, fltOut, fltSc }; /* fltOut = fltOut * fltSc */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vmov %0, %1 \n" /* fltOut = f16Val */ + "vcvt.f32.s16 %0, %0, #15 \n" /* Converts between floating point and fixed point */ + "vmul.f32 %0, %0, %2 \n" /* fltOut = fltOut * fltSc */ + : "=&t"(fltOut): "l"(f16Val), "t"(fltSc)); + #endif + return (fltOut); +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* 32-bit fractional to float convert function +* +* @param in float_t f32Val +* - Argument in frac32_t <-1;1) +* float_t fltSc +* - Argument in float_t +* +* @return This function returns +* - float_t value +* +* @remarks This inline function returns converted input value. The input value +* is considered as 32-bit fractional and float data types and output value is +* considered as single precision floating point data type. The input value +* represents the values in unity model. The second value represents the scale +* factor and is considered as single precision float data type and determine the +* scale conversion +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline float_t MLIB_ConvSc_FLTlf_FAsmi(register frac32_t f32Val, + register float_t fltSc) +{ + register float_t fltOut=0.0f; + + #if defined(__CC_ARM) /* For ARM Compiler */ + register float_t fltConv = 1.0f/2147483648.0f; + __asm volatile{ vmov fltOut, f32Val /* fltOut = f32Val */ + vcvt.f32.s32 fltOut, fltOut /* Converts from integer to float */ + vmul.f32 fltOut, fltOut, fltConv /* fltOut = fltOut / 2147483648.0f */ + vmul.f32 fltOut, fltOut, fltSc }; /* fltOut = fltOut * fltSc */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vmov %0, %1 \n" /* fltOut = f32Val */ + "vcvt.f32.s32 %0, %0, #31 \n" /* Converts between floating point and fixed point */ + "vmul.f32 %0, %0, %2 \n" /* fltOut = fltOut * fltSc */ + : "=&t"(fltOut): "l"(f32Val), "t"(fltSc)); + #endif + return (fltOut); +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* 32-bit accumulator to float convert function +* +* @param in float_t f32Acc +* - Argument in acc32_t [-65536.0, 65536.0) +* float_t fltSc +* - Argument in float_t +* +* @return This function returns +* - float_t value +* +* @remarks This inline function returns converted input value. The input value +* is considered as 32-bit accumulator and float data types and output value is +* considered as single precision floating point data type. The input value +* represents the values in unity model. The second value represents the scale +* factor and is considered as single precision float data type and determine the +* scale conversion. +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline float_t MLIB_ConvSc_FLTaf_FAsmi(register acc32_t a32Val, + register float_t fltSc) +{ + register float_t fltOut=0.0f; + + #if defined(__CC_ARM) /* For ARM Compiler */ + register float_t fltConv = 1.0f/32768.0f; + __asm volatile{ vmov fltOut, a32Val /* fltOut = a32Val */ + vcvt.f32.s32 fltOut, fltOut /* Converts from integer to float */ + vmul.f32 fltOut, fltOut, fltConv /* fltOut = fltOut / 32768.0f */ + vmul.f32 fltOut, fltOut, fltSc }; /* fltOut = fltOut * fltSc */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vmov %0, %1 \n" /* fltOut = a32Val */ + "vcvt.f32.s32 %0, %0, #15 \n" /* Converts between floating point and fixed point */ + "vmul.f32 %0, %0, %2 \n" /* fltOut = fltOut * fltSc */ + : "=&t"(fltOut): "l"(a32Val), "t"(fltSc)); + #endif + return (fltOut); +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* float to 16-bit fractional convert function +* +* @param in fltVal Input value in single precision floating point format +* to be converted. +* fltSc Scale factor in single precision floating point format. +* +* @return This function returns +* - 16-bit fractional value +* +* @remarks This inline function returns converted input value. The input value +* is considered as single precision floating point data type and output value +* is considered as 16-bit fractional data type. The second value represents the +* scale factor and is considered as single precision floating point data type. +* The output value represents the values in unity model. The output saturation +* is implemented in this function, thus in case the input value is outside +* the [-1,1) interval, the output value is limited to the boundary value. +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_ConvSc_F16ff_FAsmi(register float_t fltVal, + register float_t fltSc) +{ + register frac16_t f16Out=0; + + #if defined(__CC_ARM) /* For ARM Compiler */ + register float_t fltConv = 32768.0f; + __asm volatile{ vdiv.f32 fltVal, fltVal, fltSc /* fltVal = fltVal / fltSc */ + vmul.f32 fltVal, fltVal, fltConv /* fltVal = fltVal * 32768.0f */ + vcvt.s32.f32 fltVal, fltVal /* Converts from float to integer */ + vmov f16Out, fltVal /* f16Out = fltVal */ + ssat f16Out, #16, f16Out}; /* f16Out >> 16 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vdiv.f32 %1, %1, %2 \n" /* fltVal = fltVal / fltSc */ + "vcvt.s16.f32 %1, %1, #15 \n" /* Converts between floating point and fixed point */ + "vmov %0, %1 \n" /* f16Out = fltVal */ + : "=l"(f16Out), "+t"(fltVal): "t"(fltSc)); + #endif + return (f16Out); +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* float to 32-bit fractional convert function +* +* @param in fltVal Input value in single precision floating point format +* to be converted. +* fltSc Scale factor in single precision floating point format. +* +* @return This function returns +* - 32-bit fractional value +* +* @remarks This inline function returns converted input value. The input value +* is considered as single precision floating point data type and output value +* is considered as 32-bit fractional data type. The second value represents the +* scale factor and is considered as single precision floating point data type. +* The output value represents the values in unity model. The output saturation +* is implemented in this function, thus in case the input value is outside +* the [-1,1) interval, the output value is limited to the boundary value. +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_ConvSc_F32ff_FAsmi(register float_t fltVal, + register float_t fltSc) +{ + register frac32_t f32Out=0; + + #if defined(__CC_ARM) /* For ARM Compiler */ + register float_t fltConv = 2147483648.0f; + __asm volatile{ vdiv.f32 fltVal, fltVal, fltSc /* fltVal = fltVal * fltSc */ + vmul.f32 fltVal, fltVal, fltConv /* fltVal = fltVal * 2147483648.0f */ + vcvt.s32.f32 fltVal, fltVal /* Converts from float to integer */ + vmov f32Out, fltVal }; /* f32Out = fltVal */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vdiv.f32 %1, %1, %2 \n" /* fltVal = fltVal * fltSc */ + "vcvt.s32.f32 %1, %1, #31 \n" /* Converts between floating point and fixed point */ + "vmov %0, %1 \n" /* f32Out = fltVal */ + : "=l"(f32Out), "+t"(fltVal): "t"(fltSc)); + #endif + return (f32Out); +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* float to 32-bit accumulator convert function +* +* @param in fltVal Input value in single precision floating point format +* to be converted. +* fltSc Scale factor in single precision floating point format. +* +* @return This function returns +* - 32-bit accumulator value [-65536.0, 65536.0) +* +* @remarks This inline function returns converted input value. The input value +* is considered as single precision floating point data type and output value +* is considered as 32-bit accumulator data type. The second value represents the +* scale factor and is considered as single precision floating point data type. +* The output value represents the values in unity model. The output saturation +* is implemented in this function, thus in case the input value is outside +* the [-65536.0, 65536.0) interval, the output value is limited to the boundary value. +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline acc32_t MLIB_ConvSc_A32ff_FAsmi(register float_t fltVal, + register float_t fltSc) +{ + register acc32_t a32Out=0; + + #if defined(__CC_ARM) /* For ARM Compiler */ + register float_t fltConv = 32768.0f; + __asm volatile{ vdiv.f32 fltVal, fltVal, fltSc /* fltVal = fltVal * fltSc */ + vmul.f32 fltVal, fltVal, fltConv /* fltVal = fltVal * 32768.0f */ + vcvt.s32.f32 fltVal, fltVal /* Converts from float to integer */ + vmov a32Out, fltVal }; /* a32Out = fltVal */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vdiv.f32 %1, %1, %2 \n" /* fltVal = fltVal * fltSc */ + "vcvt.s32.f32 %1, %1, #15 \n" /* Converts between floating point and fixed point */ + "vmov %0, %1 \n" /* a32Out = fltVal */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "=l"(a32Out), "+t"(fltVal): "t"(fltSc)); + #endif + return (a32Out); +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_CONVSC_FLT_ASMI_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Conv_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Conv_F32.h new file mode 100644 index 000000000..eca4e66a4 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Conv_F32.h @@ -0,0 +1,94 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Conversion functions +* +*******************************************************************************/ +#ifndef _MLIB_CONV_F32_H_ +#define _MLIB_CONV_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Conv_F32s_Ci(f16Val) MLIB_Conv_F32s_FCi(f16Val) +#define MLIB_Conv_F16l_Ci(f32Val) MLIB_Conv_F16l_FCi(f32Val) + +/***************************************************************************//*! +* +* @brief 16-bit fractional to 32-bit fractional convert function +* +* @param in frac16_t f16Val - Argument in <-1;1) in frac16_t +* +* @return This function returns - frac32_t value <-1;1) +* +* @remarks This function convert the lower 16-bits of the 32-bit input and +* returns the upper 16-bit. +* +*******************************************************************************/ +static inline frac32_t MLIB_Conv_F32s_FCi(register frac16_t f16Val) +{ + register uint32_t ui32temp = (uint32_t)f16Val << 16U; + return (frac32_t)ui32temp; +} + +/***************************************************************************//*! +* +* @brief 32-bit fractional to 16-bit fractional convert function +* +* @param in frac32_t f32Val - Argument in <-1;1) in frac32_t +* +* @return This function returns - frac16_t value <-1;1) +* +* @remarks This function convert the lower 16-bits of the 32-bit input and +* returns the upper 16-bit. +* +*******************************************************************************/ +static inline frac16_t MLIB_Conv_F16l_FCi(register frac32_t f32Val) +{ + register uint16_t u16Temp = (uint16_t)((uint32_t)f32Val >> 16U); + return (frac16_t)u16Temp; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_CONV_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Conv_FLT_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Conv_FLT_Asmi.h new file mode 100644 index 000000000..552b8ade0 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Conv_FLT_Asmi.h @@ -0,0 +1,307 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Conversion functions +* +*******************************************************************************/ +#ifndef _MLIB_CONV_FLT_ASMI_H_ +#define _MLIB_CONV_FLT_ASMI_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Conv_F16f_Asmi(fltVal) MLIB_Conv_F16f_FAsmi(fltVal) +#define MLIB_Conv_F32f_Asmi(fltVal) MLIB_Conv_F32f_FAsmi(fltVal) +#define MLIB_Conv_A32f_Asmi(fltVal) MLIB_Conv_A32f_FAsmi(fltVal) +#define MLIB_Conv_FLTs_Asmi(f16Val) MLIB_Conv_FLTs_FAsmi(f16Val) +#define MLIB_Conv_FLTl_Asmi(f32Val) MLIB_Conv_FLTl_FAsmi(f32Val) +#define MLIB_Conv_FLTa_Asmi(a32Val) MLIB_Conv_FLTa_FAsmi(a32Val) + +/***************************************************************************//*! +* +* @brief This function converts the input value to different representation without scale. +* +* @param in Input value in 16-bit fractional format to be converted. +* +* @return This function returns +* - Converted input value in single precision floating point format. +* +* @remarks This inline function returns converted input value. +* The input value is considered as 16-bit fractional data type and +* output value is considered as single precision floating point data type. +* The input value represents the values in unity model. The output +* saturation is not implemented in this function. +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline float_t MLIB_Conv_FLTs_FAsmi(register frac16_t f16Val) +{ + register float_t fltOut=0.0f; + + #if defined(__CC_ARM) /* For ARM Compiler */ + register float_t fltConv = 1.0f/32768.0f; + __asm volatile{ vmov fltOut, f16Val /* fltOut = f16Val */ + vcvt.f32.s32 fltOut, fltOut /* Converts from integer to float */ + vmul.f32 fltOut, fltOut, fltConv }; /* fltOut = fltOut / 32768.0f */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vmov %0, %1 \n" /* fltOut = f16Val */ + "vcvt.f32.s16 %0, %0, #15 \n" /* Converts between floating point and fixed point */ + : "=t"(fltOut): "l"(f16Val)); + #endif + return (fltOut); +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* @brief This function converts the input value to different representation without scale. +* +* @param in Input value in 32-bit fractional format to be converted. +* +* @return This function returns +* - Converted input value in single precision floating point format. +* +* @remarks This inline function returns converted input value. +* The input value is considered as 32-bit fractional data type and +* output value is considered as single precision floating point data type. +* The input value represents the values in unity model. The output +* saturation is not implemented in this function. +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline float_t MLIB_Conv_FLTl_FAsmi(register frac32_t f32Val) +{ + register float_t fltOut=0.0f; + + #if defined(__CC_ARM) /* For ARM Compiler */ + register float_t fltConv = 1.0f/2147483648.0f; + __asm volatile{ vmov fltOut, f32Val /* fltOut = f32Val */ + vcvt.f32.s32 fltOut, fltOut /* Converts from integer to float */ + vmul.f32 fltOut, fltOut, fltConv }; /* fltOut = fltOut / 2147483648.0f */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vmov %0, %1 \n" /* fltOut = f32Val */ + "vcvt.f32.s32 %0, %0, #31 \n" /* Converts between floating point and fixed point */ + : "=t"(fltOut): "l"(f32Val)); + #endif + return (fltOut); +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* @brief This function converts the input value to different representation without scale. +* +* @param in Input value in 32-bit accumulator format to be converted. +* +* @return This function returns +* - Converted input value in single precision floating point format. +* +* @remarks This inline function returns converted input value. +* The input value is considered as 32-bit accumulator data type and +* output value is considered as single precision floating point data type. +* The input value represents the values in unity model. The output +* saturation is not implemented in this function. +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline float_t MLIB_Conv_FLTa_FAsmi(register acc32_t a32Val) +{ + register float_t fltOut=0.0f; + + #if defined(__CC_ARM) /* For ARM Compiler */ + register float_t fltConv = 1.0f/32768.0f; + __asm volatile{ vmov fltOut, a32Val /* fltOut = a32Val */ + vcvt.f32.s32 fltOut, fltOut /* Converts from integer to float */ + vmul.f32 fltOut, fltOut, fltConv }; /* fltOut = fltOut / 32768.0f */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vmov %0, %1 \n" /* fltOut = a32Val */ + "vcvt.f32.s32 %0, %0, #15 \n" /* Converts between floating point and fixed point */ + : "=t"(fltOut): "l"(a32Val)); + #endif + return (fltOut); +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* @brief This function converts the input value to different representation without scale. +* +* @param in fltVal Input value in single precision floating point format to be converted. +* +* @return This function returns +* - Converted input value in 16-bit fractional format. +* +* @remarks This inline function returns converted input value. The input value is +* considered as single precision floating point data type and output value +* is considered as 16-bit fractional data type. The output value represents +* the values in unity model. The output saturation is implemented in this function, +* thus in case the input value is outside the [-1,1) interval, the output +* value is limited to the boundary value. +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Conv_F16f_FAsmi(register float_t fltVal) +{ + register frac16_t f16Out=0; + + #if defined(__CC_ARM) /* For ARM Compiler */ + register float_t fltConv = 32768.0f; + __asm volatile{ vmul.f32 fltVal, fltVal, fltConv /* fltVal = fltVal * 32768.0f */ + vcvt.s32.f32 fltVal, fltVal /* Converts from float to integer */ + vmov f16Out, fltVal /* f16Out = fltVal */ + ssat f16Out, #16, f16Out}; /* Saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vcvt.s16.f32 %1, %1, #15 \n" /* Converts between floating point and fixed point */ + "vmov %0, %1 \n" /* f16Out = fltVal */ + : "=l"(f16Out): "t"(fltVal)); + #endif + return (f16Out); +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* @brief This function converts the input value to different representation without scale. +* +* @param in fltVal Input value in single precision floating point format to be converted. +* +* @return This function returns +* - Converted input value in 32-bit fractional format. +* +* @remarks This inline function returns converted input value. The input value is +* considered as single precision floating point data type and output value +* is considered as 32-bit fractional data type. The output value represents +* the values in unity model. The output saturation is implemented in this function, +* thus in case the input value is outside the [-1,1) interval, the output +* value is limited to the boundary value. +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Conv_F32f_FAsmi(register float_t fltVal) +{ + register frac32_t f32Out=0; + + #if defined(__CC_ARM) /* For ARM Compiler */ + register float_t fltConv = 2147483648.0f; + __asm volatile{ vmul.f32 fltVal, fltVal, fltConv /* fltVal = fltVal * 2147483648.0f */ + vcvt.s32.f32 fltVal, fltVal /* Converts from float to integer */ + vmov f32Out, fltVal }; /* f32Out = fltVal */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vcvt.s32.f32 %1, %1, #31 \n" /* Converts between floating point and fixed point */ + "vmov %0, %1 \n" /* f32Out = fltVal */ + : "=l"(f32Out): "t"(fltVal)); + #endif + return (f32Out); +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* @brief This function converts the input value to different representation without scale. +* +* @param in fltVal Input value in single precision floating point format to be converted. +* +* @return This function returns +* - Converted input value in 32-bit accumulator format [-65536.0, 65536.0). +* +* @remarks This inline function returns converted input value. The input value is +* considered as single precision floating point data type and output value +* is considered as 32-bit accumulator data type. The output value represents +* the values in unity model. The output saturation is implemented in this function, +* thus in case the input value is outside the [-65536.0, 65536.0) interval, the output +* value is limited to the boundary value. +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline acc32_t MLIB_Conv_A32f_FAsmi(register float_t fltVal) +{ + register acc32_t a32Out=0; + + #if defined(__CC_ARM) /* For ARM Compiler */ + register float_t fltConv = 32768.0f; + __asm volatile{ vmul.f32 fltVal, fltVal, fltConv /* fltVal = fltVal * 32768.0f */ + vcvt.s32.f32 fltVal, fltVal /* Converts from float to integer */ + vmov a32Out, fltVal }; /* a32Out = fltVal */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vcvt.s32.f32 %1, %1, #15 \n" /* Converts between floating point and fixed point */ + "vmov %0, %1 \n" /* a32Out = fltVal */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "=l"(a32Out): "t"(fltVal)); + #endif + return (a32Out); +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_CONV_FLT_ASMI_H_ */ + diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div1Q_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div1Q_A32.h new file mode 100644 index 000000000..b7ce28a9f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div1Q_A32.h @@ -0,0 +1,123 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Division +* +*******************************************************************************/ +#ifndef _MLIB_DIV1Q_A32_H_ +#define _MLIB_DIV1Q_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Clb_F32.h" +#include "MLIB_BiShift_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Div1Q_A32ss_Ci(f16Num, f16Denom) MLIB_Div1Q_A32ss_FCi(f16Num, f16Denom) +#define MLIB_Div1Q_A32ls_Ci(f32Num, f16Denom) MLIB_Div1Q_A32ls_FCi(f32Num, f16Denom) +#define MLIB_Div1Q_A32ll_Asm(f32Num, f32Denom) MLIB_Div1Q_A32ll_FAsm(f32Num, f32Denom) + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ + + extern acc32_t MLIB_Div1Q_A32ll_FAsm(frac32_t f32Num, frac32_t f32Denom); + +/***************************************************************************//*! +* @brief 16-bit numerator, 16-bit denominator inputs 32-bit accumulator output +* 1-quadrant division function +* +* @param in frac16_t f16Num - Numerator in <0;1) in frac16_t +* frac16_t f16Denom- Denominator in <0;1) in frac16_t +* +* @return This function returns - acc32_t value [0;65536.0 - (2^-15)] +* +* @remarks This function divides two positive fractional inputs: +* result = f16Num / f16Denom. +* The output is the accumulator type where the lower +* word is the fractional part. +* If the denominator is 0, the output is 0x7FFF FFFF. +* +*******************************************************************************/ +static inline acc32_t MLIB_Div1Q_A32ss_FCi(register frac16_t f16Num, register frac16_t f16Denom) +{ + if (f16Denom == 0) + { + return(INT32_MAX); + } + else + { + return (acc32_t)(MLIB_ShL_F32_Ci(f16Num, 15U) / (frac32_t)f16Denom); + } +} + +/***************************************************************************//*! +* @brief 32-bit numerator, 16-bit denominator inputs 32-bit accumulator output +* 1-quadrant division function +* +* @param in frac32_t f32Num - Numerator in <0;1) in frac32_t +* frac16_t f16Denom- Denominator in <0;1) in frac16_t +* +* @return This function returns- acc32_t value [0;65536.0 - (2^-15)] +* +* @remarks This function divides two non-negative fractional inputs: +* result = f32Num / f16Denom. +* The output is the accumulator type where the lower +* word is the fractional part. +* If the denominator is 0, the output is 0x7FFF FFFF. +* +*******************************************************************************/ +static inline acc32_t MLIB_Div1Q_A32ls_FCi(register frac32_t f32Num, register frac16_t f16Denom) +{ + if (f16Denom == 0) + { + return(INT32_MAX); + } + else + { + return(acc32_t)MLIB_Sh1R_F32_Ci(f32Num / (frac32_t)f16Denom); + } +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_DIV1Q_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div1Q_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div1Q_F16.h new file mode 100644 index 000000000..c047fbfc6 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div1Q_F16.h @@ -0,0 +1,120 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Division +* +*******************************************************************************/ +#ifndef _MLIB_DIV1Q_F16_H_ +#define _MLIB_DIV1Q_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F32.h" +#include "MLIB_Conv_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Div1Q_F16_Ci(f16Num, f16Denom) MLIB_Div1Q_F16_FCi(f16Num, f16Denom) +#define MLIB_Div1QSat_F16_Ci(f16Num, f16Denom) MLIB_Div1QSat_F16_FCi(f16Num, f16Denom) + +/***************************************************************************//*! +* @brief 16-bit inputs 16-output single quadrant division function +* +* @param in frac16_t f16Num - Numerator in <0;1) in frac16_t +* frac16_t f16Denom - Denominator in <0;1) in frac16_t +* +* @return This function returns - frac16_t value <0;1) +* +* @remarks This function divides two non-negative fractional inputs: +* result = f16Num / f16Denom. +* The function does not saturate the output. +* If the denominator is 0, the output is 0x7FFF. +* +****************************************************************************/ +static inline frac16_t MLIB_Div1Q_F16_FCi(register frac16_t f16Num, register frac16_t f16Denom) +{ + if (f16Denom == (frac16_t)0) + { + return((frac16_t)INT16_MAX); + } + else + { + return (frac16_t)(MLIB_ShL_F32_Ci(f16Num, 15U) / (frac32_t)f16Denom); + } +} + +/***************************************************************************//*! +* @brief 16-bit inputs 16-output single quadrant division function with saturation +* +* @param in frac16_t f16Num - Numerator in <0;1) in frac16_t +* frac16_t f16Denom- Denominator in <0;1) in frac16_t +* +* @return This function returns - frac16_t value <0;1) +* +* @remarks This function divides two non-negative fractional inputs: +* result = f16Num / f16Denom. +* The function saturates the output if f16Num > f16Denom +* to 0x7FFF. +* +****************************************************************************/ +static inline frac16_t MLIB_Div1QSat_F16_FCi(register frac16_t f16Num, register frac16_t f16Denom) +{ + if (f16Denom == (frac16_t)0) + { + return((frac16_t)INT16_MAX); + } + else + { + if (f16Num >= f16Denom) + { + return((frac16_t)INT16_MAX); + } + else + { + return (frac16_t)(MLIB_ShL_F32_Ci(f16Num, 15U) / (frac16_t)f16Denom); + + } + } +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_DIV1Q_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div1Q_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div1Q_F32.h new file mode 100644 index 000000000..a51a1e0b9 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div1Q_F32.h @@ -0,0 +1,140 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Division +* +*******************************************************************************/ +#ifndef _MLIB_DIV1Q_F32_H_ +#define _MLIB_DIV1Q_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Clb_F32.h" +#include "MLIB_BiShift_F32.h" +#include "MLIB_Shift_F32.h" +#include "MLIB_Conv_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Div1Q_F16ls_Ci(f32Num, f16Denom) MLIB_Div1Q_F16ls_FCi(f32Num, f16Denom) +#define MLIB_Div1Q_F32ls_C(f32Num, f16Denom) MLIB_Div1Q_F32ls_FC(f32Num, f16Denom) +#define MLIB_Div1QSat_F16ls_Ci(f32Num, f16Denom) MLIB_Div1QSat_F16ls_FCi(f32Num, f16Denom) +#define MLIB_Div1QSat_F32ls_C(f32Num, f16Denom) MLIB_Div1QSat_F32ls_FC(f32Num, f16Denom) +#define MLIB_Div1Q_F16ll_Asm(f32Num, f32Denom) MLIB_Div1Q_F16ll_FAsm(f32Num, f32Denom) +#define MLIB_Div1Q_F32_Asm(f32Num, f32Denom) MLIB_Div1Q_F32_FAsm(f32Num, f32Denom) +#define MLIB_Div1QSat_F16ll_Asm(f32Num, f32Denom) MLIB_Div1QSat_F16ll_FAsm(f32Num, f32Denom) +#define MLIB_Div1QSat_F32_Asm(f32Num, f32Denom) MLIB_Div1QSat_F32_FAsm(f32Num, f32Denom) + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac32_t MLIB_Div1Q_F32ls_FC(frac32_t f32Num, frac16_t f16Denom); +extern frac32_t MLIB_Div1QSat_F32ls_FC(frac32_t f32Num, frac16_t f16Denom); +extern frac16_t MLIB_Div1Q_F16ll_FAsm(frac32_t f32Num, frac32_t f32Denom); +extern frac32_t MLIB_Div1Q_F32_FAsm(frac32_t f32Num, frac32_t f32Denom); +extern frac16_t MLIB_Div1QSat_F16ll_FAsm(frac32_t f32Num, frac32_t f32Denom); +extern frac32_t MLIB_Div1QSat_F32_FAsm(frac32_t f32Num, frac32_t f32Denom); + +/***************************************************************************//*! +* @brief 32-bit numerator, 16-bit denominator inputs 16-output 1-quadrant +* division function +* +* @param in frac32_t f32Num - Numerator in <-1;1) in frac32_t +* frac16_t f16Denom- Denominator in <-1;1) in frac16_t +* +* @return This function returns - frac16_t value <-1;1) +* +* @remarks This function divides two fractional inputs: +* result = f32Num / f16Denom. +* The function does not saturate the output. +* If the denominator is 0, the output is 0x7FFF. +* +*******************************************************************************/ +static inline frac16_t MLIB_Div1Q_F16ls_FCi(register frac32_t f32Num, register frac16_t f16Denom) +{ + if (f16Denom == (frac16_t)0) + { + return(frac16_t)(INT16_MAX); + } + else + { + return(frac16_t)MLIB_Sh1R_F32_Ci(f32Num / (frac32_t)f16Denom); + + } +} + +/***************************************************************************//*! +* @brief 32-bit numerator, 16-bit denominator inputs 32-output single quadrant +* division function +* +* @param in frac32_t f32Num - Numerator in <-1;1) in frac32_t +* frac16_t f16Denom- Denominator in <-1;1) in frac16_t +* +* @return This function returns- frac16_t value <0;1) +* +* @remarks This function divides two non-negative fractional inputs: +* result = f32Num / f16Denom. +* The function saturates the output if f32Num > f16Denom +* to 0x7FFF FFFF. +* +*******************************************************************************/ +static inline frac16_t MLIB_Div1QSat_F16ls_FCi(register frac32_t f32Num, register frac16_t f16Denom) +{ + if (f16Denom == (frac16_t)0) + { + return(frac16_t)(INT16_MAX); + } + else + { + if (f32Num >= MLIB_Conv_F32s_Ci(f16Denom)) + { + return(frac16_t)(INT16_MAX); + } + else + { + return(frac16_t)MLIB_Sh1R_F32_Ci(f32Num / (frac32_t)f16Denom); + } + } +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_DIV1Q_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div_A32.h new file mode 100644 index 000000000..904ae126e --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div_A32.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Division +* +*******************************************************************************/ +#ifndef _MLIB_DIV_A32_H_ +#define _MLIB_DIV_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_BiShift_F32.h" +#include "MLIB_Clb_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Div_A32ss_Ci(f16Num, f16Denom) MLIB_Div_A32ss_FCi(f16Num, f16Denom) +#define MLIB_Div_A32ls_Ci(f32Num, f16Denom) MLIB_Div_A32ls_FCi(f32Num, f16Denom) +#define MLIB_Div_A32ll_Asm(f32Num, f32Denom) MLIB_Div_A32ll_FAsm(f32Num, f32Denom) + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern acc32_t MLIB_Div_A32ll_FAsm(frac32_t f32Num, frac32_t f32Denom); + +/***************************************************************************//*! +* +* @brief 16-bit numerator, 16-bit denominator inputs 32-bit accumulator output +* 4-quadrant division function +* +* @param in frac16_t f16Num - Numerator in <-1;1) in frac16_t +* frac16_t f16Denom- Denominator in <-1;1) in frac16_t +* +* @return This function returns +* - acc32_t value [-65536.0;65536.0 - (2^-15)] +* +* @remarks This function divides fractional inputs: +* result = f16Num / f16Denom. +* The output is the accumulator type where the lower word is the fractional part. +* If the denominator is 0, the output is 0x7FFF FFFF or 0x8000 0000 +* depending on the numerator's sign. For the both are 0, the output is +* 0x7FFF FFFF. +* +****************************************************************************/ +static inline acc32_t MLIB_Div_A32ss_FCi(register frac16_t f16Num, register frac16_t f16Denom) +{ + if (f16Denom == 0) + { + return((f16Num >= 0) ? (acc32_t)0x7fffffff : (acc32_t)0x80000000U); + } + else + { + return (acc32_t)(MLIB_ShL_F32_Ci(f16Num, 15U) / (frac32_t)f16Denom); + } +} + +/***************************************************************************//*! +* +* @brief 32-bit numerator, 16-bit denominator inputs 32-bit accumulator output +* 4-quadrant division function +* +* @param in frac32_t f32Num - Numerator in <-1;1) in frac32_t +* frac16_t f16Denom - Denominator in <-1;1) in frac16_t +* +* @return This function returns +* - acc32_t value [-65536.0;65536.0 - (2^-15)] +* +* @remarks This function divides two negative fractional inputs: +* result = f32Num / f16Denom. +* The output is the accumulator type where the lower +* word is the fractional part. +* If the denominator is 0, the output is 0x7FFF FFFF or 0x8000 0000 +* depending on the numerator's sign. For the both are 0, the output is +* 0x7FFF FFFF. +* +****************************************************************************/ +static inline acc32_t MLIB_Div_A32ls_FCi(register frac32_t f32Num, register frac16_t f16Denom) +{ + if (f16Denom == 0) + { + return((f32Num >= 0) ? (acc32_t)0x7fffffff : (acc32_t)0x80000000U); + } + else + { + return(acc32_t)MLIB_Sh1R_F32_Ci(f32Num / (frac32_t)f16Denom); + + } +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_DIV_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div_F16.h new file mode 100644 index 000000000..c7a476a95 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div_F16.h @@ -0,0 +1,116 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Division +* +*******************************************************************************/ +#ifndef _MLIB_DIV_F16_H_ +#define _MLIB_DIV_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Div_F16_Ci(f16Num, f16Denom) MLIB_Div_F16_FCi(f16Num, f16Denom) +#define MLIB_DivSat_F16_Ci(f16Num, f16Denom) MLIB_DivSat_F16_FCi(f16Num, f16Denom) + +/***************************************************************************//*! +* @brief 16-bit inputs inputs 16-output 4-quadrant division +* +* @param in frac16_t f16Num - Numerator in <-1;1) in frac16_t +* frac16_t f16Denom- Denominator in <-1;1) in frac16_t +* +* @return This function returns - frac16_t value <-1;1) +* +* @remarks This function divides two fractional inputs: +* result = f16Num / f16Denom. +* The function does not saturate the output. +* If the denominator is 0, the output is 0x7FFF or 0x8000 +* depending on the numerator's sign. For the both are 0, the output is +* 0x7FFF. +* +****************************************************************************/ +static inline frac16_t MLIB_Div_F16_FCi(register frac16_t f16Num, register frac16_t f16Denom) +{ + if (f16Denom == 0) + { + return((f16Num >= 0) ? INT16_MAX : INT16_MIN); + } + else + { + return (frac16_t)(MLIB_ShL_F32_Ci(f16Num, 15U) / (frac32_t)f16Denom); + + } +} + +/***************************************************************************//*! +* @brief 16-bit inputs inputs 16-output 4-quadrant division function with saturation +* +* @param in frac16_t f16Num - Numerator in <-1;1) in frac16_t +* frac16_t f16Denom - Denominator in <-1;1) in frac16_t +* +* @return This function returns - frac16_t value <-1;1) +* +* @remarks This function divides two fractional inputs: +* result = f16Num / f16Denom. +* The function saturates the output if |f16Num| > |f16Denom| +* to 0x7FFF or 0x8000 depending on the signs. +* +****************************************************************************/ +static inline frac16_t MLIB_DivSat_F16_FCi(register frac16_t f16Num, register frac16_t f16Denom) +{ + register frac32_t f32Return; + + if (f16Denom == (frac16_t)0) + { + return ((f16Num >= (frac16_t)0) ? (frac16_t)0x7fff : (frac16_t)0x8000U); + } + else + { + f32Return = (frac32_t)(MLIB_ShL_F32_Ci(f16Num, 15U) / (frac32_t)f16Denom); + return(frac16_t)(f32Return > (frac16_t)(INT16_MAX) ? (frac16_t)(INT16_MAX) : f32Return < (frac16_t)(INT16_MIN) ? (frac16_t)(INT16_MIN) : f32Return); + } +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_DIV_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div_F32.h new file mode 100644 index 000000000..90c624537 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div_F32.h @@ -0,0 +1,136 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Division +* +*******************************************************************************/ +#ifndef _MLIB_DIV_F32_H_ +#define _MLIB_DIV_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Clb_F32.h" +#include "MLIB_BiShift_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Div_F32ls_C(f32Num, f16Denom) MLIB_Div_F32ls_FC(f32Num, f16Denom) +#define MLIB_Div_F16ls_Ci(f32Num, f16Denom) MLIB_Div_F16ls_FCi(f32Num, f16Denom) +#define MLIB_DivSat_F32ls_C(f32Num, f16Denom) MLIB_DivSat_F32ls_FC(f32Num, f16Denom) +#define MLIB_DivSat_F16ls_Ci(f32Num, f16Denom) MLIB_DivSat_F16ls_FCi(f32Num, f16Denom) +#define MLIB_Div_F16ll_Asm(f32Num, f32Denom) MLIB_Div_F16ll_FAsm(f32Num, f32Denom) +#define MLIB_Div_F32_Asm(f32Num, f32Denom) MLIB_Div_F32_FAsm(f32Num, f32Denom) +#define MLIB_DivSat_F16ll_Asm(f32Num, f32Denom) MLIB_DivSat_F16ll_FAsm(f32Num, f32Denom) +#define MLIB_DivSat_F32_Asm(f32Num, f32Denom) MLIB_DivSat_F32_FAsm(f32Num, f32Denom) + +/******************************************************************************* +* Exported function prototypes +*******************************************************************************/ +extern frac32_t MLIB_Div_F32ls_FC(frac32_t f32Num, frac16_t f16Denom); +extern frac32_t MLIB_DivSat_F32ls_FC(frac32_t f32Num, frac16_t f16Denom); + +extern frac32_t MLIB_Div_F32_FAsm(frac32_t f32Num, frac32_t f32Denom); +extern frac16_t MLIB_Div_F16ll_FAsm(frac32_t f32Num, frac32_t f32Denom); +extern frac16_t MLIB_DivSat_F16ll_FAsm(frac32_t f32Num, frac32_t f32Denom); +extern frac32_t MLIB_DivSat_F32_FAsm(frac32_t f32Num, frac32_t f32Denom); + +/***************************************************************************//*! +* @brief 32-bit numerator, 16-bit denominator inputs 16-output 4-quadrant +* division function +* +* @param in frac32_t f32Num - Numerator in <-1;1) in frac32_t +* frac16_t f16Denom- Denominator in <-1;1) in frac16_t +* +* @return This function returns- frac16_t value <-1;1) +* +* @remarks This function divides two fractional inputs: +* result = f32Num / f16Denom. +* The function does not saturate the output. +* If the denominator is 0, the output is 0x7FFF or 0x8000 +* depending on the numerator's sign. For the both are 0, the output is +* 0x7FFF. +* +*******************************************************************************/ +static inline frac16_t MLIB_Div_F16ls_FCi(register frac32_t f32Num, register frac16_t f16Denom) +{ + if (f16Denom == 0) + { + return((f32Num >= 0) ? INT16_MAX : INT16_MIN); + } + else + { + return(frac16_t)MLIB_Sh1R_F32_Ci(f32Num / (frac32_t)f16Denom); + } +} + +/***************************************************************************//*! +* @brief 32-bit numerator, 16-bit denominator inputs 16-output 4-quadrant +* division function +* +* @param in frac32_t f32Num - Numerator in <-1;1) in frac32_t +* frac16_t f16Denom- Denominator in <-1;1) in frac16_t +* +* @return This function returns - frac16_t value <-1;1) +* +* @remarks This function divides two fractional inputs: +* result = f32Num / f16Denom. +* The function saturates the output if |f32Num| > |f16Denom| +* to 0x7FFF or 0x8000 depending on the signs. +* +*******************************************************************************/ +static inline frac16_t MLIB_DivSat_F16ls_FCi(register frac32_t f32Num, register frac16_t f16Denom) +{ + register frac32_t f32Return; + + if (f16Denom == (frac16_t)0) + { + return ((f32Num >= (frac32_t)0) ? (frac16_t)(INT16_MAX) : (frac16_t)(INT16_MIN)); + } + else + { + f32Return = MLIB_Sh1R_F32_Ci(f32Num / (frac32_t)f16Denom); + return(frac16_t)(f32Return > (frac16_t)(INT16_MAX) ? (frac16_t)(INT16_MAX) : f32Return < (frac16_t)(INT16_MIN) ? (frac16_t)(INT16_MIN) : f32Return); + } +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_DIV_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div_FLT.h new file mode 100644 index 000000000..e2017b26c --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Div_FLT.h @@ -0,0 +1,84 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Division +* +*******************************************************************************/ +#ifndef _MLIB_DIV_FLT_H_ +#define _MLIB_DIV_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Div_FLT_Ci(fltNum, fltDenom) MLIB_Div_FLT_FCi(fltNum, fltDenom) + +/**************************************************************************** +* Inline functions +****************************************************************************/ + +/***************************************************************************//*! +* @brief float numerator, float denominator inputs 16-output 1-quadrant +* division function +* +* @param in float_t fltNum - Numerator in float_t +* in float_t fltDenom - Denominator in float_t +* +* @return This function returns - float_t value +* +* @remarks This function divides two fractional: +* result = fltNum / fltDenom. +* If denumerator is +zero(-zero) it returns plus infinity = 0x7F800000 +* (or minus infinity = 0xFF800000). Both are not numbers float value. +* The output saturation is not implemented, thus in case +* the division of input values is outside the (-2^128, 2^128) +* interval, the output value will overflow without any detection. +* +*******************************************************************************/ +static inline float_t MLIB_Div_FLT_FCi(register float_t fltNum, register float_t fltDenom) +{ + return((float_t)(fltNum / fltDenom)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_DIV_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Log2_U16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Log2_U16.h new file mode 100644 index 000000000..a9beef671 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Log2_U16.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Binary logarithm +* +*******************************************************************************/ +#ifndef _MLIB_LOG2_U16_H_ +#define _MLIB_LOG2_U16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#define _clz(x) __CLZ(x) +#else +#define _clz(x) __builtin_clz(x) +#endif + +#define MLIB_Log2_U16_Ci(u16Val) MLIB_Log2_U16_FCi(u16Val) + +/***************************************************************************//*! +* +* @brief Binary logarithm of 16-bit input +* +* @param in uint16_t u16Val - Argument in uint16_t +* +* @return This function returns - uint16_t value +* +* @remarks This function returns the 16-bit integer part of binary logarithm of the input. +* Returns 0 for input u16Val == 0. +* +*******************************************************************************/ +static inline uint16_t MLIB_Log2_U16_FCi(register uint16_t u16Val) +{ + register uint16_t u16Temp; + if ((bool_t)(u16Val == 0U)) + { return (uint16_t)0; + } + else + { + u16Temp = 0x20U - (uint16_t)_clz(u16Val); + return (uint16_t)u16Temp; + } +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_LOG2_U16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4Rnd_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4Rnd_F16_Asmi.h new file mode 100644 index 000000000..d8d4cad9a --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4Rnd_F16_Asmi.h @@ -0,0 +1,127 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate of four inputs with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MAC4RND_F16_ASM_H_ +#define _MLIB_MAC4RND_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mac4Rnd_F16_Asmi(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) \ + MLIB_Mac4Rnd_F16_FAsmi(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) +#define MLIB_Mac4RndSat_F16_Asmi(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) \ + MLIB_Mac4RndSat_F16_FAsmi(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) + +/***************************************************************************//*! +* +* f16Out = (f16Add1Mul1 * f16Add1Mul2) + (f16Add2Mul1 * f16Add2Mul2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Mac4Rnd_F16_FAsmi(register frac16_t f16Add1Mul1, + register frac16_t f16Add1Mul2, register frac16_t f16Add2Mul1, register frac16_t f16Add2Mul2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f16Add1Mul1, f16Add1Mul1, f16Add1Mul2 /* f16Add1Mul1 * f16Add1Mul2 */ + smlabb f16Add1Mul1, f16Add2Mul1, f16Add2Mul2, f16Add1Mul1 /* f16Add1Mul1 * f16Add1Mul2 + f16Add2Mul1 * f16Add2Mul2 */ + add f16Add1Mul1, f16Add1Mul1, #0x4000 /* Rounding */ + asr f16Add1Mul1, f16Add1Mul1, #15 }; /* Result >> 15*/ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %0, %0, %2 \n" /* f16Add1Mul1 * f16Add1Mul2 */ + "smlabb %0, %1, %3, %0 \n" /* f16Add1Mul1 * f16Add1Mul2 + f16Add2Mul1 * f16Add2Mul2 */ + "add %0, %0, #0x4000 \n" /* Rounding */ + "asr %0, %0, #15 \n" /* Result >> 15 */ + : "+l"(f16Add1Mul1): "l"(f16Add2Mul1), "l"(f16Add1Mul2), "l"(f16Add2Mul2)); + #endif + + return f16Add1Mul1; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f16Out = (f16Add1Mul1 * f16Add1Mul2) + (f16Add2Mul1 * f16Add2Mul2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Mac4RndSat_F16_FAsmi(register frac16_t f16Add1Mul1, + register frac16_t f16Add1Mul2, register frac16_t f16Add2Mul1, register frac16_t f16Add2Mul2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f16Add1Mul1, f16Add1Mul1, f16Add1Mul2 /* f16Add1Mul1 * f16Add1Mul2 */ + smulbb f16Add2Mul1, f16Add2Mul1, f16Add2Mul2 /* f16Add2Mul1 * f16Add2Mul2 */ + add f16Add1Mul1, f16Add1Mul1, #0x4000 /* Rounding */ + qadd f16Add1Mul1, f16Add1Mul1, f16Add2Mul1 /* Addition with saturation */ + ssat f16Add1Mul1, #16, f16Add1Mul1, asr #15 }; /* Result = Result >> 15 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %0, %0, %2 \n" /* f16Add1Mul1 * f16Add1Mul2 */ + "smulbb %1, %1, %3 \n" /* f16Add2Mul1 * f16Add2Mul2 */ + "add %0, %0, #0x4000 \n" /* Rounding */ + "qadd %0, %0, %1 \n" /* Addition with saturation */ + "ssat %0, #16, %0, asr #15 \n" /* Result = Result >> 15 */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Add1Mul1), "+l"(f16Add2Mul1): "l"(f16Add1Mul2), "l"(f16Add2Mul2)); + #endif + + return f16Add1Mul1; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MAC4RND_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4Rnd_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4Rnd_F32.h new file mode 100644 index 000000000..5e33ace5e --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4Rnd_F32.h @@ -0,0 +1,79 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate of four inputs with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MAC4RND_F32_H_ +#define _MLIB_MAC4RND_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mac4Rnd_F32_Ci(f32Add1Mul1, f32Add1Mul2, f32Add2Mul1, f32Add2Mul2) \ + MLIB_Mac4Rnd_F32_FCi(f32Add1Mul1, f32Add1Mul2, f32Add2Mul1, f32Add2Mul2) + +/***************************************************************************//*! +* +* f32Out = (f32Add1Mul1 * f32Add1Mul2) + (f32Add2Mul1 * f32Add2Mul2) +* Without saturation +*******************************************************************************/ +static inline frac32_t MLIB_Mac4Rnd_F32_FCi(register frac32_t f32Add1Mul1, register frac32_t f32Add1Mul2, + register frac32_t f32Add2Mul1, register frac32_t f32Add2Mul2) +{ + register uint64_t u64Temp; + register frac64_t f64Temp; + + f64Temp = (((int64_t)f32Add1Mul1 * (int64_t)f32Add1Mul2) + + ((int64_t)f32Add2Mul1 * (int64_t)f32Add2Mul2) + 0x40000000); + u64Temp = (uint64_t)f64Temp >> 31U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x200000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return (frac32_t)u64Temp; /* cast back the corrected values */ + +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MAC4RND_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4Rnd_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4Rnd_F32_Asmi.h new file mode 100644 index 000000000..8188cdfc2 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4Rnd_F32_Asmi.h @@ -0,0 +1,108 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate of four inputs with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MAC4RND_F32_ASM_H_ +#define _MLIB_MAC4RND_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mac4RndSat_F32_Asmi(f32Add1Mul1, f32Add1Mul2, f32Add2Mul1, f32Add2Mul2) \ + MLIB_Mac4RndSat_F32_FAsmi(f32Add1Mul1, f32Add1Mul2, f32Add2Mul1, f32Add2Mul2) + +/***************************************************************************//*! +* +* f32Out = (f32Add1Mul1 * f32Add1Mul2) + (f32Add2Mul1 * f32Add2Mul2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Mac4RndSat_F32_FAsmi(register frac32_t f32Add1Mul1, register frac32_t f32Add1Mul2, + register frac32_t f32Add2Mul1, register frac32_t f32Add2Mul2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Add1Mul2, f32Add1Mul1, f32Add1Mul2, f32Add1Mul1 /* f16Add1Mul1 * f16Add1Mul2 */ + smlal f32Add1Mul2, f32Add1Mul1, f32Add2Mul2, f32Add2Mul1 /* f16Add1Mul1 * f16Add1Mul2 + f16Add2Mul1 * f16Add2Mul2 */ + adds f32Add1Mul2, f32Add1Mul2, #0x40000000 /* Rounding */ + adc f32Add1Mul1, f32Add1Mul1, #0 /* Adds carry bit */ + cmp f32Add1Mul1, #0x80000000 /* Compares the high part of result with fractional (-1) */ + it eq /* If result is fractional (-1), then saturates */ + subeq f32Add1Mul1, f32Add1Mul1, #1 /* result = result - 1 */ + add f32Add2Mul1, f32Add1Mul1, f32Add1Mul1 /* Converts high part of result to fractional value */ + qadd f32Add1Mul1, f32Add1Mul1, f32Add1Mul1 /* Converts high part of result to fractional value with saturation */ + cmp f32Add1Mul1, f32Add2Mul1 /* Compares result with saturation and result without saturation */ + it eq /* If results are equal, then adds the last bit */ + orreq f32Add1Mul1, f32Add1Mul1, f32Add1Mul2, lsr #31 }; /* Result = Result + Last bit */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %1, %0, %1, %0 \n" /* f16Add1Mul1 * f16Add1Mul2 */ + "smlal %1, %0, %3, %2 \n" /* f16Add1Mul1 * f16Add1Mul2 + f16Add2Mul1 * f16Add2Mul2 */ + "adds %1, %1, #0x40000000 \n" /* Rounding */ + "adc %0, %0, #0 \n" /* Adds carry bit */ + "cmp %0, #0x80000000 \n" /* Compares the high part of result with fractional (-1) */ + "it eq \n" /* If result is fractional (-1), then saturates */ + "subeq %0, %0, #1 \n" /* result = result - 1 */ + "add %2, %0, %0 \n" /* Converts high part of result to fractional value */ + "qadd %0, %0, %0 \n" /* Converts high part of result to fractional value with saturation */ + "cmp %0, %2 \n" /* Compares result with saturation and result without saturation */ + "it eq \n" /* If results are equal, then adds the last bit */ + "orreq %0, %0, %1, lsr #31 \n" /* Result = Result + Last bit */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Add1Mul1), "+l"(f32Add1Mul2), "+l"(f32Add2Mul1), "+l"(f32Add2Mul2):); + #endif + + return f32Add1Mul1; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MAC4RND_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4_F32.h new file mode 100644 index 000000000..3a0d8bc09 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4_F32.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate of four inputs +* +*******************************************************************************/ +#ifndef _MLIB_MAC4_F32_H_ +#define _MLIB_MAC4_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mac4_F32ssss_Ci(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) \ + MLIB_Mac4_F32ssss_FCi(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) + +/***************************************************************************//*! +* +* f32Out = (f16Add1Mul1 * f16Add1Mul2) + (f16Add2Mul1 * f16Add2Mul2) +* Without saturation +*******************************************************************************/ +static inline frac32_t MLIB_Mac4_F32ssss_FCi(register frac16_t f16Add1Mul1, register frac16_t f16Add1Mul2, + register frac16_t f16Add2Mul1, register frac16_t f16Add2Mul2) +{ + return (MLIB_Sh1L_F32_Ci(((int32_t)f16Add1Mul1 * (int32_t)f16Add1Mul2) + + ((int32_t)f16Add2Mul1 * (int32_t)f16Add2Mul2))); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MAC4_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4_F32_Asmi.h new file mode 100644 index 000000000..637123216 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4_F32_Asmi.h @@ -0,0 +1,93 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate of four inputs +* +*******************************************************************************/ +#ifndef _MLIB_MAC4_F32_ASM_H_ +#define _MLIB_MAC4_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mac4Sat_F32ssss_Asmi(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) \ + MLIB_Mac4Sat_F32ssss_FAsmi(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) + +/***************************************************************************//*! +* +* f32Out = (f16Add1Mul1 * f16Add1Mul2) + (f16Add2Mul1 * f16Add2Mul2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Mac4Sat_F32ssss_FAsmi(register frac16_t f16Add1Mul1, register frac16_t f16Add1Mul2, + register frac16_t f16Add2Mul1, register frac16_t f16Add2Mul2) +{ + register frac32_t f32Out=0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f16Add1Mul1, f16Add1Mul1, f16Add1Mul2 /* f16Add1Mul1 * f16Add1Mul2 */ + smulbb f32Out, f16Add2Mul1, f16Add2Mul2 /* f16Add2Mul1 * f16Add2Mul2 */ + qadd f32Out, f32Out, f16Add1Mul1 /* Addition with saturation */ + qadd f32Out, f32Out, f32Out }; /* Addition with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %1, %1, %2 \n" /* f16Add1Mul1 * f16Add1Mul2 */ + "smulbb %2, %3, %4 \n" /* f16Add2Mul1 * f16Add2Mul2 */ + "qadd %2, %2, %1 \n" /* Addition with saturation */ + "qadd %0, %2, %2 \n" /* Addition with saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "=l"(f32Out), "+l"(f16Add1Mul1), "+l"(f16Add1Mul2): "l"(f16Add2Mul1), "l"(f16Add2Mul2)); + #endif + + return f32Out; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MAC4_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4_FLT.h new file mode 100644 index 000000000..bfceea30c --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac4_FLT.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate of four inputs +* +*******************************************************************************/ +#ifndef _MLIB_MAC4_FLT_H_ +#define _MLIB_MAC4_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mac4_FLT_Ci(fltAdd1Mul1, fltAdd1Mul2, fltAdd2Mul1, fltAdd2Mul2) \ + MLIB_Mac4_FLT_FCi(fltAdd1Mul1, fltAdd1Mul2, fltAdd2Mul1, fltAdd2Mul2) + +/***************************************************************************//*! +* +* fltOut = (fltAdd1Mul1 * fltAdd1Mul2) + (fltAdd2Mul1 * fltAdd2Mul2) +* The output saturation is not implemented, thus in case +* the MAC4 of input values is outside the (-2^128, 2^128) +* interval, the output value will overflow without any detection. +*******************************************************************************/ +static inline float_t MLIB_Mac4_FLT_FCi(register float_t fltAdd1Mul1, register float_t fltAdd1Mul2, + register float_t fltAdd2Mul1, register float_t fltAdd2Mul2) +{ + return ((float_t)((fltAdd1Mul1 * fltAdd1Mul2) + (fltAdd2Mul1 * fltAdd2Mul2))); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MAC4_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MacRnd_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MacRnd_A32.h new file mode 100644 index 000000000..0cd7fd5d9 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MacRnd_A32.h @@ -0,0 +1,73 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MACRND_A32_H_ +#define _MLIB_MACRND_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MacRnd_A32ass_Ci(a32Accum, f16Mult1, f16Mult2) \ + MLIB_MacRnd_A32ass_FCi(a32Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* a32Out = a32Accum + ( f16Mult1 * f16Mult2) +* +*******************************************************************************/ +static inline acc32_t MLIB_MacRnd_A32ass_FCi(register acc32_t a32Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + register acc32_t a32Temp; + + a32Temp = ((int32_t)f16Mult1 * (int32_t)f16Mult2); + a32Temp = MLIB_ShR_F32_Ci(a32Temp + 0x00004000, 15U); + return (a32Accum + a32Temp); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MACRND_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MacRnd_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MacRnd_F16_Asmi.h new file mode 100644 index 000000000..e5c39af7a --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MacRnd_F16_Asmi.h @@ -0,0 +1,127 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MACRND_F16_ASM_H_ +#define _MLIB_MACRND_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MacRnd_F16_Asmi( f16Accum, f16Mult1, f16Mult2) \ + MLIB_MacRnd_F16_FAsmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_MacRndSat_F16_Asmi( f16Accum, f16Mult1, f16Mult2) \ + MLIB_MacRndSat_F16_FAsmi( f16Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f16Out = f16Accum + ( f16Mult1 * f16Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MacRnd_F16_FAsmi(register frac16_t f16Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Accum, f16Accum /* Transforms 16-bit input f16Val to 32-bit */ + smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + add f16Mult1, f16Mult1, #0x4000 /* Rounding */ + add f16Accum, f16Accum, f16Mult1, asr #15 }; /* f16Accum = f16Accum + f16Mult1 * f16Mult2 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "add %1, %1, #0x4000 \n" /* Rounding */ + "add %0, %0, %1, asr #15 \n" /* f16Accum = f16Accum + f16Mult1 * f16Mult2 */ + : "+l"(f16Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f16Out = f16Accum + ( f16Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MacRndSat_F16_FAsmi(register frac16_t f16Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Accum, f16Accum /* Transforms 16-bit input f16Val to 32-bit */ + smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + add f16Mult1, f16Mult1, #0x4000 /* Rounding */ + add f16Accum, f16Accum, f16Mult1, asr #15 /* f16Accum = f16Accum + f16Mult1 * f16Mult2 */ + ssat f16Accum, #16, f16Accum }; /* Saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "add %1, %1, #0x4000 \n" /* Rounding */ + "add %0, %0, %1, asr #15 \n" /* f16Accum = f16Accum + f16Mult1 * f16Mult2 */ + "ssat %0, #16, %0 \n" /* Saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MACRND_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MacRnd_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MacRnd_F32.h new file mode 100644 index 000000000..107700842 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MacRnd_F32.h @@ -0,0 +1,77 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MACRND_F32_H_ +#define _MLIB_MACRND_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MacRnd_F32lls_Ci(f32Accum, f32Mult1, f16Mult2) \ + MLIB_MacRnd_F32lls_FCi(f32Accum, f32Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = f32Accum + ( f32Mult1 * f16Mult2) +* Without saturation +*******************************************************************************/ +static inline frac32_t MLIB_MacRnd_F32lls_FCi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac16_t f16Mult2) +{ + register uint64_t u64Temp; + register frac64_t f64Temp; + + f64Temp = (frac64_t)f32Mult1 * (frac16_t)f16Mult2 + 0x4000; + u64Temp = (uint64_t)f64Temp >> 15U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x2000000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return ((frac32_t)u64Temp + (frac32_t)f32Accum); /* cast back the corrected values and add accumulator */ +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MACRND_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MacRnd_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MacRnd_F32_Asmi.h new file mode 100644 index 000000000..fc7ea6e89 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MacRnd_F32_Asmi.h @@ -0,0 +1,176 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MACRND_F32_ASM_H_ +#define _MLIB_MACRND_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MacRnd_F32_Asmi(f32Accum, f32Mult1, f32Mult2) \ + MLIB_MacRnd_F32_FAsmi(f32Accum, f32Mult1, f32Mult2) +#define MLIB_MacRndSat_F32_Asmi(f32Accum, f32Mult1, f32Mult2) \ + MLIB_MacRndSat_F32_FAsmi(f32Accum, f32Mult1, f32Mult2) +#define MLIB_MacRndSat_F32lls_Asmi(f32Accum, f32Mult1, f16Mult2) \ + MLIB_MacRndSat_F32lls_FAsmi(f32Accum, f32Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = f32Accum + ( f32Mult1 * f32Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MacRnd_F32_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Mult2, f32Mult1, f32Mult2, f32Mult1 /* R1:R2 = Mul1 * Mul2 */ + adds f32Mult2, f32Mult2, #0x40000000 /* Rounding */ + adc f32Mult1, f32Mult1, #0 /* Adds carry */ + lsr f32Mult2, f32Mult2, #31 /* R2 >> 31 */ + orr f32Mult1, f32Mult2, f32Mult1, lsl #1 /* (R1 << 1) | R2*/ + add f32Accum, f32Accum, f32Mult1 }; /* Acc + Mul1 * Mul2 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %2, %1, %2, %1 \n" /* R1:R2 = Mul1 * Mul2 */ + "adds %2, %2, #0x40000000 \n" /* Rounding */ + "adc %1, %1, #0 \n" /* Adds carry */ + "lsr %2, %2, #31 \n" /* R2 >> 31 */ + "orr %1, %2, %1, lsl #1 \n" /* (R1 << 1) | R2*/ + "add %0, %0, %1 \n" /* Acc + Mul1 * Mul2 */ + : "+l"(f32Accum), "+l"(f32Mult1), "+l"(f32Mult2):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = f32Accum + ( f32Mult1 * f32Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MacRndSat_F32_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Mult2, f32Mult1, f32Mult2, f32Mult1 /* R1:R2 = Mul1 * Mul2 */ + adds f32Mult2, f32Mult2, #0x40000000 /* Rounding */ + adc f32Mult1, f32Mult1, #0 /* Adds carry*/ + lsr f32Mult2, f32Mult2, #31 /* R2 >> 31 */ + orr f32Mult1, f32Mult2, f32Mult1, lsl #1 /* (R1 << 1) | R2*/ + rsb f32Mult1, f32Mult1, #0 /* Negation for case of multiplication (-1)*(-1) */ + qsub f32Accum, f32Accum, f32Mult1 }; /* Acc - ( - Mul1 * Mul2) */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %2, %1, %2, %1 \n" /* R1:R2 = Mul1 * Mul2 */ + "adds %2, %2, #0x40000000 \n" /* Rounding */ + "adc %1, %1, #0 \n" /* Adds carry*/ + "lsr %2, %2, #31 \n" /* R2 >> 31 */ + "orr %1, %2, %1, lsl #1 \n" /* (R1 << 1) | R2*/ + "rsb %1, %1, #0 \n" /* Negation for case of multiplication (-1)*(-1) */ + "qsub %0, %0, %1 \n" /* Acc - ( - Mul1 * Mul2) */ + : "+l"(f32Accum), "+l"(f32Mult1), "+l"(f32Mult2):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = f32Accum + ( f32Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MacRndSat_F32lls_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Mult2, f16Mult2 /* Transforms 16-bit input f16Mult2 to 32-bit */ + smull f32Mult1, f16Mult2, f16Mult2, f32Mult1 /* f32Mult1:f32Mult2 = f32Mult1 * f16Mult2 */ + adds f32Mult1, f32Mult1, #0x4000 /* Rounding*/ + adc f16Mult2, f16Mult2, #0 /* Adds Carry Bit */ + lsl f16Mult2, f16Mult2, #17 /* f32Mult1 << 17 */ + orr f16Mult2, f16Mult2, f32Mult1, lsr #15 /* Adds last 17 bits of result */ + rsb f16Mult2, f16Mult2, #0 /* Negation for case of multiplication (-1)*(-1) */ + qsub f32Accum, f32Accum, f16Mult2 }; /* Acc - ( - Mul1 * Mul2) */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %1, %1 \n" /* Transforms 16-bit input f16Mult2 to 32-bit */ + "smull %2, %1, %1, %2 \n" /* f32Mult1:f32Mult2 = f32Mult1 * f16Mult2 */ + "adds %2, %2, #0x4000 \n" /* Rounding*/ + "adc %1, %1, #0 \n" /* Adds Carry Bit */ + "lsl %1, %1, #17 \n" /* f32Mult1 << 17 */ + "orr %1, %1, %2, lsr #15 \n" /* Adds last 17 bits of result */ + "rsb %1, %1, #0 \n" /* Negation for case of multiplication (-1)*(-1) */ + "qsub %0, %0, %1 \n" /* Acc - ( - Mul1 * Mul2) */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Accum), "+l"(f16Mult2), "+l"(f32Mult1):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MACRND_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_A32.h new file mode 100644 index 000000000..4922a8635 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_A32.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate +* +*******************************************************************************/ +#ifndef _MLIB_MAC_A32_H_ +#define _MLIB_MAC_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mac_A32ass_Ci(a32Accum, f16Mult1, f16Mult2) \ + MLIB_Mac_A32ass_FCi(a32Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* a32Out = a32Accum + ( f16Mult1 * f16Mult2 ) +* +*******************************************************************************/ +static inline acc32_t MLIB_Mac_A32ass_FCi(register acc32_t a32Accum, + register frac16_t f16Mult1,register frac16_t f16Mult2) +{ + return (acc32_t)(MLIB_ShR_F32_Ci(((int32_t)f16Mult1 * (int32_t)f16Mult2), 15U) + a32Accum); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MAC_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_F16_Asmi.h new file mode 100644 index 000000000..fdf174477 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_F16_Asmi.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate +* +*******************************************************************************/ +#ifndef _MLIB_MAC_F16_ASM_H_ +#define _MLIB_MAC_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mac_F16_Asmi( f16Accum, f16Mult1, f16Mult2) \ + MLIB_Mac_F16_FAsmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_MacSat_F16_Asmi( f16Accum, f16Mult1, f16Mult2) \ + MLIB_MacSat_F16_FAsmi( f16Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f16Out = f16Accum + ( f16Mult1 * f16Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Mac_F16_FAsmi(register frac16_t f16Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Accum, f16Accum /* Transforms 16-bit input f16Val to 32-bit */ + smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + add f16Accum, f16Accum, f16Mult1, asr #15 }; /* f16Accum = f16Accum + f16Mult1 * f16Mult2 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "add %0, %0, %1, asr #15 \n" /* f16Accum = f16Accum + f16Mult1 * f16Mult2 */ + : "+l"(f16Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f16Out = f16Accum + ( f16Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MacSat_F16_FAsmi(register frac16_t f16Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Accum, f16Accum /* Transforms 16-bit input f16Val to 32-bit */ + smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + add f16Accum, f16Accum, f16Mult1, asr #15 /* f16Accum = f16Accum + f16Mult1 * f16Mult2 */ + ssat f16Accum, #16, f16Accum }; /* Saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "add %0, %0, %1, asr #15 \n" /* f16Accum = f16Accum + f16Mult1 * f16Mult2 */ + "ssat %0, #16, %0 \n" /* Saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MAC_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_F32.h new file mode 100644 index 000000000..bd867948e --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_F32.h @@ -0,0 +1,77 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate +* +*******************************************************************************/ +#ifndef _MLIB_MAC_F32_H_ +#define _MLIB_MAC_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Sub_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MacSat_F32lss_Ci(f32Accum, f16Mult1, f16Mult2) \ + MLIB_MacSat_F32lss_FCi(f32Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = f32Accum + ( f16Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +static inline frac32_t MLIB_MacSat_F32lss_FCi(register frac32_t f32Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + register frac32_t f32Temp; + + f32Temp = ((int32_t)f16Mult1 * (int32_t)f16Mult2); + f32Accum = f32Accum >> 1; + f32Temp = f32Accum + f32Temp; + f32Temp = (f32Temp > 1073741823) ? 1073741823 : f32Temp; + f32Temp = (f32Temp < -1073741824) ? -1073741824 : f32Temp; + return(f32Temp << 1); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MAC_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_F32_Asmi.h new file mode 100644 index 000000000..d64f9f644 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_F32_Asmi.h @@ -0,0 +1,181 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate +* +*******************************************************************************/ +#ifndef _MLIB_MAC_F32_ASM_H_ +#define _MLIB_MAC_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mac_F32_Asmi(f32Accum, f32Mult1, f32Mult2) MLIB_Mac_F32_FAsmi(f32Accum, f32Mult1, f32Mult2) +#define MLIB_Mac_F32lss_Asmi(f32Accum, f16Mult1, f16Mult2) MLIB_Mac_F32lss_FAsmi(f32Accum, f16Mult1, f16Mult2) +#define MLIB_MacSat_F32_Asmi(f32Accum, f32Mult1, f32Mult2) MLIB_MacSat_F32_FAsmi(f32Accum, f32Mult1, f32Mult2) +#define MLIB_MacSat_F32lss_Asmi(f32Accum, f16Mult1, f16Mult2) MLIB_MacSat_F32lss_FAsmi(f32Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = f32Accum + ( f32Mult1 * f32Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Mac_F32_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Mult2, f32Mult1, f32Mult2, f32Mult1 /* R1:R2 = Mul1 * Mul2 */ + lsr f32Mult2, f32Mult2, #31 /* R2 >> 31 */ + orr f32Mult1, f32Mult2, f32Mult1, lsl #1 /* (R1 << 1) | R2*/ + add f32Accum, f32Accum, f32Mult1 }; /* Acc + Mul1 * Mul2 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %2, %1, %2, %1 \n" /* R1:R2 = Mul1 * Mul2 */ + "lsr %2, %2, #31 \n" /* R2 >> 31 */ + "orr %1, %2, %1, lsl #1 \n" /* (R1 << 1) | R2*/ + "add %0, %0, %1 \n" /* Acc + Mul1 * Mul2 */ + : "+l"(f32Accum), "+l"(f32Mult1), "+l"(f32Mult2):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = f32Accum + ( f16Mult1 * f16Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Mac_F32lss_FAsmi(register frac32_t f32Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + add f32Accum, f32Accum, f16Mult1, lsl #1 }; /* Addition without saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "add %0, %0, %1, lsl #1 \n" /* Addition without saturation */ + : "+l"(f32Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = f32Accum + ( f32Mult1 * f32Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MacSat_F32_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Mult2, f32Mult1, f32Mult2, f32Mult1 /* R1:R2 = Mul1 * Mul2 */ + lsr f32Mult2, f32Mult2, #31 /* R2 >> 31 */ + orr f32Mult1, f32Mult2, f32Mult1, lsl #1 /* (R1 << 1) | R2 */ + rsb f32Mult1, f32Mult1, #0 /* Negation for case of multiplication (-1)*(-1) */ + qsub f32Accum, f32Accum, f32Mult1 }; /* Acc - (- Mul1 * Mul2) */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %2, %1, %2, %1 \n" /* R1:R2 = Mul1 * Mul2 */ + "lsr %2, %2, #31 \n" /* R2 >> 31 */ + "orr %1, %2, %1, lsl #1 \n" /* (R1 << 1) | R2 */ + "rsb %1, %1, #0 \n" /* Negation for case of multiplication (-1)*(-1) */ + "qsub %0, %0, %1 \n" /* Acc - (- Mul1 * Mul2) */ + : "+l"(f32Accum), "+l"(f32Mult1), "+l"(f32Mult2):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = f32Accum + ( f16Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MacSat_F32lss_FAsmi(register frac32_t f32Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + qdadd f32Accum, f32Accum, f16Mult1 }; /* Addition with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "qdadd %0, %0, %1 \n" /* Addition with saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MAC_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_FLT.h new file mode 100644 index 000000000..2f6b4803f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mac_FLT.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply accumulate +* +*******************************************************************************/ +#ifndef _MLIB_MAC_FLT_H_ +#define _MLIB_MAC_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mac_FLT_Ci(fltAccum, fltMult1, fltMult2) \ + MLIB_Mac_FLT_FCi(fltAccum, fltMult1, fltMult2) + +/***************************************************************************//*! +* +* fltOut = fltAccum + ( fltMult1 * fltMult2) +* The output saturation is not implemented, thus in case +* the MAC of input values is outside the (-2^128, 2^128) +* interval, the output value will overflow without any detection. +*******************************************************************************/ +static inline float_t MLIB_Mac_FLT_FCi(register float_t fltAccum, + register float_t fltMult1, register float_t fltMult2) +{ + return((float_t) (fltAccum + (fltMult1 * fltMult2))); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MAC_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MnacRnd_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MnacRnd_A32.h new file mode 100644 index 000000000..a6b11bca7 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MnacRnd_A32.h @@ -0,0 +1,74 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply negate accumulate with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MNACRND_A32_H_ +#define _MLIB_MNACRND_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MnacRnd_A32ass_Ci(a32Accum, f16Mult1, f16Mult2) \ + MLIB_MnacRnd_A32ass_FCi(a32Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* a32Out = - a32Accum + ( f16Mult1 * f16Mult2) +* +*******************************************************************************/ +static inline acc32_t MLIB_MnacRnd_A32ass_FCi(register acc32_t a32Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + register acc32_t a32Temp; + + a32Temp = (int32_t)f16Mult1 * (int32_t)f16Mult2; + a32Temp = a32Temp + 0x00004000; + a32Temp = MLIB_ShR_F32_Ci(a32Temp, 15U); + return (a32Temp - a32Accum); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MNACRND_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MnacRnd_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MnacRnd_F16_Asmi.h new file mode 100644 index 000000000..288b17d7c --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MnacRnd_F16_Asmi.h @@ -0,0 +1,131 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply negate accumulate with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MNACRND_F16_ASM_H_ +#define _MLIB_MNACRND_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MnacRnd_F16_Asmi( f16Accum, f16Mult1, f16Mult2) \ + MLIB_MnacRnd_F16_FAsmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_MnacRndSat_F16_Asmi( f16Accum, f16Mult1, f16Mult2) \ + MLIB_MnacRndSat_F16_FAsmi( f16Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f16Out = - f16Accum + ( f16Mult1 * f16Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MnacRnd_F16_FAsmi(register frac16_t f16Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Accum, f16Accum /* Transforms 16-bit input f16Val to 32-bit */ + smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + add f16Mult1, f16Mult1, #0x4000 /* Rounding */ + asr f16Mult1, f16Mult1, #15 /* f16Mult1 * f16Mult2 >> 15 */ + sub f16Accum, f16Mult1, f16Accum }; /* f16Accum = f16Accum + f16Mult1 * f16Mult2 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "add %1, %1, #0x4000 \n" /* Rounding */ + "asr %1, %1, #15 \n" /* f16Mult1 * f16Mult2 >> 15 */ + "sub %0, %1, %0 \n" /* f16Accum = f16Mult1 * f16Mult2 - f16Accum*/ + : "+l"(f16Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f16Out = - f16Accum + ( f16Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MnacRndSat_F16_FAsmi(register frac16_t f16Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Accum, f16Accum /* Transforms 16-bit input f16Val to 32-bit */ + smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + add f16Mult1, f16Mult1, #0x4000 /* Rounding */ + asr f16Mult1, f16Mult1, #15 /* f16Mult1 * f16Mult2 >> 15 */ + sub f16Accum, f16Mult1, f16Accum /* f16Accum = f16Accum + f16Mult1 * f16Mult2 */ + ssat f16Accum, #16, f16Accum }; /* Saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "add %1, %1, #0x4000 \n" /* Rounding */ + "asr %1, %1, #15 \n" /* f16Mult1 * f16Mult2 >> 15 */ + "sub %0, %1, %0 \n" /* f16Accum = f16Mult1 * f16Mult2 - f16Accum*/ + "ssat %0, #16, %0 \n" /* Saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MNACRND_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MnacRnd_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MnacRnd_F32.h new file mode 100644 index 000000000..798ed2856 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MnacRnd_F32.h @@ -0,0 +1,77 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply negate accumulate with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MNACRND_F32_H_ +#define _MLIB_MNACRND_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Sub_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MnacRnd_F32lls_Ci(f32Accum, f32Mult1, f16Mult2) \ + MLIB_MnacRnd_F32lls_FCi(f32Accum, f32Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = - f32Accum + ( f32Mult1 * f16Mult2) +* Without saturation +*******************************************************************************/ +static inline frac32_t MLIB_MnacRnd_F32lls_FCi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac16_t f16Mult2) +{ + register uint64_t u64Temp; + register frac64_t f64Temp; + + f64Temp = (frac64_t)f32Mult1*(frac16_t)f16Mult2 + 0x4000; + u64Temp = (uint64_t)f64Temp >> 15U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x8000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return (frac32_t)((frac32_t)u64Temp - (frac32_t)f32Accum); /* cast back the corrected values */ +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MNACRND_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MnacRnd_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MnacRnd_F32_Asmi.h new file mode 100644 index 000000000..ec4055d46 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MnacRnd_F32_Asmi.h @@ -0,0 +1,172 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply negate accumulate with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MNACRND_F32_ASM_H_ +#define _MLIB_MNACRND_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MnacRnd_F32_Asmi(f32Accum, f32Mult1, f32Mult2) \ + MLIB_MnacRnd_F32_FAsmi(f32Accum, f32Mult1, f32Mult2) +#define MLIB_MnacRndSat_F32_Asmi(f32Accum, f32Mult1, f32Mult2) \ + MLIB_MnacRndSat_F32_FAsmi(f32Accum, f32Mult1, f32Mult2) +#define MLIB_MnacRndSat_F32lls_Asmi(f32Accum, f32Mult1, f16Mult2) \ + MLIB_MnacRndSat_F32lls_FAsmi(f32Accum, f32Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = - f32Accum + ( f32Mult1 * f32Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MnacRnd_F32_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Mult2, f32Mult1, f32Mult2, f32Mult1 /* R1:R2 = Mul1 * Mul2 */ + adds f32Mult2, f32Mult2, #0x40000000 /* Rounding */ + adc f32Mult1, f32Mult1, #0 /* Adds carry */ + lsr f32Mult2, f32Mult2, #31 /* R2 >> 31 */ + orr f32Mult1, f32Mult2, f32Mult1, lsl #1 /* (R1 << 1) | R2*/ + sub f32Accum, f32Mult1, f32Accum }; /* Mul1 * Mul2 - Acc */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %2, %1, %2, %1 \n" /* R1:R2 = Mul1 * Mul2 */ + "adds %2, %2, #0x40000000 \n" /* Rounding */ + "adc %1, %1, #0 \n" /* Adds carry */ + "lsr %2, %2, #31 \n" /* R2 >> 31 */ + "orr %1, %2, %1, lsl #1 \n" /* (R1 << 1) | R2*/ + "sub %0, %1, %0 \n" /* Mul1 * Mul2 - Acc */ + : "+l"(f32Accum), "+l"(f32Mult1), "+l"(f32Mult2):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = - f32Accum + ( f32Mult1 * f32Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MnacRndSat_F32_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Mult2, f32Mult1, f32Mult2, f32Mult1 /* R1:R2 = Mul1 * Mul2 */ + adds f32Mult2, f32Mult2, #0x40000000 /* Rounding */ + adc f32Mult1, f32Mult1, #0 /* Adds carry*/ + lsr f32Mult2, f32Mult2, #31 /* R2 >> 31 */ + orr f32Mult1, f32Mult2, f32Mult1, lsl #1 /* (R1 << 1) | R2*/ + qsub f32Accum, f32Mult1, f32Accum }; /* ( Mul1 * Mul2) - Acc */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %2, %1, %2, %1 \n" /* R1:R2 = Mul1 * Mul2 */ + "adds %2, %2, #0x40000000 \n" /* Rounding */ + "adc %1, %1, #0 \n" /* Adds carry*/ + "lsr %2, %2, #31 \n" /* R2 >> 31 */ + "orr %1, %2, %1, lsl #1 \n" /* (R1 << 1) | R2*/ + "qsub %0, %1, %0 \n" /* ( Mul1 * Mul2) - Acc */ + : "+l"(f32Accum), "+l"(f32Mult1), "+l"(f32Mult2):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = - f32Accum + ( f32Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MnacRndSat_F32lls_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f32Mult1, f32Mult1 /* Transforms 16-bit input f16Mult2 to 32-bit */ + smull f16Mult2, f32Mult1, f32Mult1, f16Mult2 /* f32Mult1:f32Mult2 = f32Mult1 * f16Mult2 */ + adds f16Mult2, f16Mult2, #0x4000 /* Rounding*/ + adc f32Mult1, f32Mult1, #0 /* Adds Carry Bit */ + lsl f32Mult1, f32Mult1, #17 /* f32Mult1 << 17 */ + orr f32Mult1, f32Mult1, f16Mult2, lsr #15 /* Adds last 17 bits of result */ + qsub f32Accum, f32Mult1, f32Accum }; /* (Mul1 * Mul2) - Acc */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %1, %1 \n" /* Transforms 16-bit input f16Mult2 to 32-bit */ + "smull %2, %1, %1, %2 \n" /* f32Mult1:f32Mult2 = f32Mult1 * f16Mult2 */ + "adds %2, %2, #0x4000 \n" /* Rounding*/ + "adc %1, %1, #0 \n" /* Adds Carry Bit */ + "lsl %1, %1, #17 \n" /* f32Mult1 << 17 */ + "orr %1, %1, %2, lsr #15 \n" /* Adds last 17 bits of result */ + "qsub %0, %1, %0 \n" /* (Mul1 * Mul2) - Acc */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Accum), "+l"(f16Mult2), "+l"(f32Mult1):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MNACRND_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_A32.h new file mode 100644 index 000000000..1c8c79a69 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_A32.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply negate accumulate +* +*******************************************************************************/ +#ifndef _MLIB_MNAC_A32_H_ +#define _MLIB_MNAC_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mnac_A32ass_Ci(a32Accum, f16Mult1, f16Mult2) \ + MLIB_Mnac_A32ass_FCi(a32Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* a32Out = - a32Accum + ( f16Mult1 * f16Mult2 ) +* +*******************************************************************************/ +static inline acc32_t MLIB_Mnac_A32ass_FCi(register acc32_t a32Accum, + register frac16_t f16Mult1,register frac16_t f16Mult2) +{ + return (acc32_t)(MLIB_ShR_F32_Ci(((int32_t)f16Mult1 * (int32_t)f16Mult2), 15U) - a32Accum); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MNAC_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_F16_Asmi.h new file mode 100644 index 000000000..214b8b64a --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_F16_Asmi.h @@ -0,0 +1,127 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply negate accumulate +* +*******************************************************************************/ +#ifndef _MLIB_MNAC_F16_ASM_H_ +#define _MLIB_MNAC_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mnac_F16_Asmi( f16Accum, f16Mult1, f16Mult2) \ + MLIB_Mnac_F16_FAsmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_MnacSat_F16_Asmi( f16Accum, f16Mult1, f16Mult2) \ + MLIB_MnacSat_F16_FAsmi( f16Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f16Out = - f16Accum + ( f16Mult1 * f16Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Mnac_F16_FAsmi(register frac16_t f16Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Accum, f16Accum /* Transforms 16-bit input f16Val to 32-bit */ + smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + asr f16Mult1, f16Mult1, #15 /* f16Mult1 * f16Mult2 >> 15 */ + sub f16Accum, f16Mult1, f16Accum}; /* f16Accum = f16Mult1 * f16Mult2 - f16Accum*/ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "asr %1, %1, #15 \n" /* f16Mult1 * f16Mult2 >> 15 */ + "sub %0, %1, %0 \n" /* f16Accum = f16Mult1 * f16Mult2 - f16Accum*/ + : "+l"(f16Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f16Out = - f16Accum + ( f16Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MnacSat_F16_FAsmi(register frac16_t f16Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Accum, f16Accum /* Transforms 16-bit input f16Val to 32-bit */ + smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + asr f16Mult1, f16Mult1, #15 /* f16Mult1 * f16Mult2 >> 15 */ + sub f16Accum, f16Mult1, f16Accum /* f16Accum = f16Mult1 * f16Mult2 - f16Accum*/ + ssat f16Accum, #16, f16Accum}; /* Saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "asr %1, %1, #15 \n" /* f16Mult1 * f16Mult2 >> 15 */ + "sub %0, %1, %0 \n" /* f16Accum = f16Mult1 * f16Mult2 - f16Accum*/ + "ssat %0, #16, %0 \n" /* Saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MNAC_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_F32.h new file mode 100644 index 000000000..303102405 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_F32.h @@ -0,0 +1,77 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply negate accumulate +* +*******************************************************************************/ +#ifndef _MLIB_MNAC_F32_H_ +#define _MLIB_MNAC_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Sub_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MnacSat_F32lss_Ci(f32Accum, f16Mult1, f16Mult2) \ + MLIB_MnacSat_F32lss_FCi(f32Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = - f32Accum + ( f16Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +static inline frac32_t MLIB_MnacSat_F32lss_FCi(register frac32_t f32Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + register frac32_t f32Temp; + + f32Temp = ((int32_t)f16Mult1 * (int32_t)f16Mult2); + f32Accum = MLIB_Sh1R_F32_Ci(f32Accum); + f32Temp = f32Temp - f32Accum; + f32Temp = (f32Temp > 1073741823) ? 1073741823 : f32Temp; + f32Temp = (f32Temp < -1073741824) ? -1073741824 : f32Temp; + return MLIB_Sh1L_F32_Ci(f32Temp); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MNAC_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_F32_Asmi.h new file mode 100644 index 000000000..45a74b20f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_F32_Asmi.h @@ -0,0 +1,187 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply negate accumulate +* +*******************************************************************************/ +#ifndef _MLIB_MNAC_F32_ASM_H_ +#define _MLIB_MNAC_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mnac_F32_Asmi(f32Accum, f32Mult1, f32Mult2) \ + MLIB_Mnac_F32_FAsmi(f32Accum, f32Mult1, f32Mult2) +#define MLIB_Mnac_F32lss_Asmi(f32Accum, f16Mult1, f16Mult2) \ + MLIB_Mnac_F32lss_FAsmi(f32Accum, f16Mult1, f16Mult2) +#define MLIB_MnacSat_F32_Asmi(f32Accum, f32Mult1, f32Mult2) \ + MLIB_MnacSat_F32_FAsmi(f32Accum, f32Mult1, f32Mult2) +#define MLIB_MnacSat_F32lss_Asmi(f32Accum, f16Mult1, f16Mult2) \ + MLIB_MnacSat_F32lss_FAsmi(f32Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = - f32Accum + ( f32Mult1 * f32Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Mnac_F32_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Mult2, f32Mult1, f32Mult2, f32Mult1 /* R1:R2 = Mul1 * Mul2 */ + lsr f32Mult2, f32Mult2, #31 /* R2 >> 31 */ + orr f32Mult1, f32Mult2, f32Mult1, lsl #1 /* (R1 << 1) | R2*/ + sub f32Accum, f32Mult1, f32Accum }; /* Mul1 * Mul2 - Acc */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %2, %1, %2, %1 \n" /* R1:R2 = Mul1 * Mul2 */ + "lsr %2, %2, #31 \n" /* R2 >> 31 */ + "orr %1, %2, %1, lsl #1 \n" /* (R1 << 1) | R2*/ + "sub %0, %1, %0 \n" /* Mul1 * Mul2 - Acc */ + : "+l"(f32Accum), "+l"(f32Mult1), "+l"(f32Mult2):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = - f32Accum + ( f16Mult1 * f16Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Mnac_F32lss_FAsmi(register frac32_t f32Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + lsl f16Mult1, f16Mult1, #1 /* f16Mult1 * f16Mult2 << 1*/ + sub f32Accum, f16Mult1, f32Accum }; /* Substraction without saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "lsl %1, %1, #1 \n" /* f16Mult1 * f16Mult2 << 1*/ + "sub %0, %1, %0 \n" /* Substraction without saturation */ + : "+l"(f32Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = - f32Accum + ( f32Mult1 * f32Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MnacSat_F32_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Mult2, f32Mult1, f32Mult2, f32Mult1 /* R1:R2 = Mul1 * Mul2 */ + lsr f32Mult2, f32Mult2, #31 /* R2 >> 31 */ + orr f32Mult1, f32Mult2, f32Mult1, lsl #1 /* (R1 << 1) | R2 */ + qsub f32Accum, f32Mult1, f32Accum }; /* (Mul1 * Mul2) - Acc */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %2, %1, %2, %1 \n" /* R1:R2 = Mul1 * Mul2 */ + "lsr %2, %2, #31 \n" /* R2 >> 31 */ + "orr %1, %2, %1, lsl #1 \n" /* (R1 << 1) | R2 */ + "qsub %0, %1, %0 \n" /* (Mul1 * Mul2) - Acc */ + : "+l"(f32Accum), "+l"(f32Mult1), "+l"(f32Mult2):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = - f32Accum + ( f16Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MnacSat_F32lss_FAsmi(register frac32_t f32Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ register frac32_t f32Out = 0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + qsub f32Accum, f32Out, f32Accum /* Accumulator negation */ + qdadd f32Accum, f32Accum, f16Mult1}; /* Addition with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %2, %2, %3 \n" /* f16Mult1 * f16Mult2 */ + "qsub %1, %0, %1 \n" /* Accumulator negation */ + "qdadd %1, %1, %2 \n" /* Addition with saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Out), "+l"(f32Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MNAC_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_FLT.h new file mode 100644 index 000000000..92ab67599 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mnac_FLT.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply negate accumulate +* +*******************************************************************************/ +#ifndef _MLIB_MNAC_FLT_H_ +#define _MLIB_MNAC_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mnac_FLT_Ci( fltAccum, fltMult1, fltMult2) \ + MLIB_Mnac_FLT_FCi(fltAccum, fltMult1, fltMult2) + +/***************************************************************************//*! +* +* fltOut = - fltAccum + ( fltMult1 * fltMult2) +* The output saturation is not implemented, thus in case +* the Mnac of input values is outside the (-2^128, 2^128) interval. +*******************************************************************************/ +static inline float_t MLIB_Mnac_FLT_FCi(register float_t fltAccum, + register float_t fltMult1, register float_t fltMult2) +{ + return((float_t) ((fltMult1 * fltMult2) - fltAccum)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MNAC_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4Rnd_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4Rnd_F16.h new file mode 100644 index 000000000..e753fbb24 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4Rnd_F16.h @@ -0,0 +1,74 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract of four inputs with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MSU4RND_F16_H_ +#define _MLIB_MSU4RND_F16_H_ + + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Sub_F16.h" +#include "MLIB_MulRnd_F16.h" +#include "MLIB_Sub_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Msu4Rnd_F16_Ci(f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) \ + MLIB_Msu4Rnd_F16_FCi(f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) + +/***************************************************************************//*! +* +* f16Out = (f16MinMul1 * f16MinMul2) - (f16SubMul1 * f16SubMul2) +* Without saturation +*******************************************************************************/ +static inline frac16_t MLIB_Msu4Rnd_F16_FCi(register frac16_t f16MinMul1, register frac16_t f16MinMul2, + register frac16_t f16SubMul1, register frac16_t f16SubMul2) +{ + return(frac16_t)MLIB_ShR_F32_Ci(((MLIB_Sub_F32_Ci((int32_t)f16MinMul1 * (int32_t)f16MinMul2, + (int32_t)f16SubMul1 * (int32_t)f16SubMul2)) + 0x4000), 15U); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSU4RND_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4Rnd_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4Rnd_F16_Asmi.h new file mode 100644 index 000000000..7cb99d7c5 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4Rnd_F16_Asmi.h @@ -0,0 +1,95 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract of four inputs with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MSU4RND_F16_ASM_H_ +#define _MLIB_MSU4RND_F16_ASM_H_ + + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Msu4RndSat_F16_Asmi(f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) \ + MLIB_Msu4RndSat_F16_FAsmi(f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) + +/***************************************************************************//*! +* +* f16Out = (f16MinMul1 * f16MinMul2) - (f16SubMul1 * f16SubMul2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Msu4RndSat_F16_FAsmi(register frac16_t f16MinMul1, register frac16_t f16MinMul2, + register frac16_t f16SubMul1, register frac16_t f16SubMul2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f16MinMul1, f16MinMul1, f16MinMul2 /* f16MinMul1 * f16MinMul2 */ + smulbb f16SubMul1, f16SubMul1, f16SubMul2 /* f16SubMul1 * f16SubMul2 */ + add f16MinMul1, f16MinMul1, #0x4000 /* Rounding */ + qsub f16MinMul1, f16MinMul1, f16SubMul1 /* Addition with saturation */ + ssat f16MinMul1, #16, f16MinMul1, asr #15 }; /* Result = Result * 2 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %0, %0, %2 \n" /* f16MinMul1 * f16MinMul2 */ + "smulbb %1, %1, %3 \n" /* f16SubMul1 * f16SubMul2 */ + "add %0, %0, #0x4000 \n" /* Rounding */ + "qsub %0, %0, %1 \n" /* Addition with saturation */ + "ssat %0, #16, %0, asr #15 \n" /* Result = Result * 2 */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16MinMul1), "+l"(f16SubMul1): "l"(f16MinMul2), "l"(f16SubMul2)); + #endif + + return f16MinMul1; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSU4RND_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4Rnd_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4Rnd_F32.h new file mode 100644 index 000000000..87e46c301 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4Rnd_F32.h @@ -0,0 +1,80 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract of four inputs with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MSU4RND_F32_H_ +#define _MLIB_MSU4RND_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Sub_F64.h" +#include "MLIB_Sub_F32.h" +#include "MLIB_MulRnd_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Msu4Rnd_F32_Ci( f32MinMul1, f32MinMul2, f32SubMul1, f32SubMul2) \ + MLIB_Msu4Rnd_F32_FCi( f32MinMul1, f32MinMul2, f32SubMul1, f32SubMul2) + +/***************************************************************************//*! +* +* f32Out = (f32MinMul1 * f32MinMul2) - (f32SubMul1 * f32SubMul2) +* Without saturation +*******************************************************************************/ +static inline frac32_t MLIB_Msu4Rnd_F32_FCi(register frac32_t f32MinMul1, register frac32_t f32MinMul2, + register frac32_t f32SubMul1, register frac32_t f32SubMul2) +{ + frac64_t f64Temp; + uint64_t u64Temp; + + f64Temp = (((int64_t)f32MinMul1 * (int64_t)f32MinMul2) - + ((int64_t)f32SubMul1 * (int64_t)f32SubMul2) + 0x40000000); + u64Temp = (uint64_t)f64Temp >> 31U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x200000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return (frac32_t)u64Temp; /* cast back the corrected values */ +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSU4RND_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4Rnd_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4Rnd_F32_Asmi.h new file mode 100644 index 000000000..364995b56 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4Rnd_F32_Asmi.h @@ -0,0 +1,106 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract of four inputs with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MSU4RND_F32_ASM_H_ +#define _MLIB_MSU4RND_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Msu4RndSat_F32_Asmi( f32MinMul1, f32MinMul2, f32SubMul1, f32SubMul2) \ + MLIB_Msu4RndSat_F32_FAsmi( f32MinMul1, f32MinMul2, f32SubMul1, f32SubMul2) + +/***************************************************************************//*! +* +* f32Out = (f32MinMul1 * f32MinMul2) - (f32SubMul1 * f32SubMul2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Msu4RndSat_F32_FAsmi(register frac32_t f32MinMul1,register frac32_t f32MinMul2, + register frac32_t f32SubMul1,register frac32_t f32SubMul2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32MinMul2, f32MinMul1, f32MinMul2, f32MinMul1 /* f16Add1Mul1 * f16Add1Mul2 */ + smull f32SubMul2, f32SubMul1, f32SubMul2, f32SubMul1 /* f16Add2Mul1 * f16Add2Mul2 */ + subs f32MinMul2, f32MinMul2, f32SubMul2 /* Subtraction of lower parts */ + sbc f32MinMul1, f32MinMul1, f32SubMul1 /* Subtraction of higher parts */ + adds f32MinMul2, f32MinMul2, #0x40000000 /* Rounding */ + adc f32MinMul1, f32MinMul1, #0 /* Adds carry bit */ + add f32SubMul1, f32MinMul1, f32MinMul1 /* Converts high part of result to fractional value */ + qadd f32MinMul1, f32MinMul1, f32MinMul1 /* Converts high part of result to fractional value with saturation */ + cmp f32MinMul1, f32SubMul1 /* Compares result with saturation and result without saturation */ + it eq /* If values are equal, then adds the last bit */ + orreq f32MinMul1, f32MinMul1, f32MinMul2, lsr #31 }; /* Result = Result + Last bit */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %1, %0, %1, %0 \n" /* f16Add1Mul1 * f16Add1Mul2 */ + "smull %3, %2, %3, %2 \n" /* f16Add2Mul1 * f16Add2Mul2 */ + "subs %1, %1, %3 \n" /* Subtraction of lower parts */ + "sbc %0, %0, %2 \n" /* Subtraction of higher parts */ + "adds %1, %1, #0x40000000 \n" /* Rounding */ + "adc %0, %0, #0 \n" /* Adds carry bit */ + "add %2, %0, %0 \n" /* Converts high part of result to fractional value */ + "qadd %0, %0, %0 \n" /* Converts high part of result to fractional value with saturation */ + "cmp %0, %2 \n" /* Compares result with saturation and result without saturation */ + "it eq \n" /* If values are equal, then adds the last bit */ + "orreq %0, %0, %1, lsr #31 \n" /* Result = Result + Last bit */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32MinMul1), "+l"(f32MinMul2), "+l"(f32SubMul1), "+l"(f32SubMul2):); + #endif + + return f32MinMul1; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSU4RND_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4_F32.h new file mode 100644 index 000000000..a929f1607 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4_F32.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract of four inputs +* +*******************************************************************************/ +#ifndef _MLIB_MSU4_F32_H_ +#define _MLIB_MSU4_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Msu4_F32ssss_Ci(f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) \ + MLIB_Msu4_F32ssss_FCi(f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) + +/***************************************************************************//*! +* +* f32Out = (f16MinMul1 * f16MinMul2) - (f16SubMul1 * f16SubMul2) +* Without saturation +*******************************************************************************/ +static inline frac32_t MLIB_Msu4_F32ssss_FCi(register frac16_t f16MinMul1, register frac16_t f16MinMul2, + register frac16_t f16SubMul1, register frac16_t f16SubMul2) +{ + return (MLIB_Sh1L_F32_Ci(((int32_t)f16MinMul1 * (int32_t)f16MinMul2) - + ((int32_t)f16SubMul1 * (int32_t)f16SubMul2))); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSU4_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4_F32_Asmi.h new file mode 100644 index 000000000..57615ce18 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4_F32_Asmi.h @@ -0,0 +1,94 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract of four inputs +* +*******************************************************************************/ +#ifndef _MLIB_MSU4_F32_ASM_H_ +#define _MLIB_MSU4_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Msu4Sat_F32ssss_Asmi(f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) \ + MLIB_Msu4Sat_F32ssss_FAsmi(f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) + +/***************************************************************************//*! +* +* f32Out = (f16MinMul1 * f16MinMul2) - (f16SubMul1 * f16SubMul2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Msu4Sat_F32ssss_FAsmi(register frac16_t f16MinMul1,register frac16_t f16MinMul2, + register frac16_t f16SubMul1,register frac16_t f16SubMul2) +{ + register frac32_t f32Out=0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f32Out, f16MinMul1, f16MinMul2 /* f16MinMul1 * f16MinMul2 */ + smulbb f16MinMul1, f16SubMul1, f16SubMul2 /* f16SubMul1 * f16SubMul2 */ + qsub f32Out, f32Out, f16MinMul1 /* Subtraction with saturation */ + qadd f32Out, f32Out, f32Out }; /* Addition with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %1, %1, %2 \n" /* f16MinMul1 * f16MinMul2 */ + "smulbb %2, %3, %4 \n" /* f16SubMul1 * f16SubMul2 */ + "qsub %2, %1, %2 \n" /* Subtraction with saturation */ + "qadd %0, %2, %2 \n" /* Addition with saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "=l"(f32Out), "+l"(f16MinMul1), "+l"(f16MinMul2): "l"(f16SubMul1), "l"(f16SubMul2)); + #endif + + return f32Out; +} +RTCESL_INLINE_OPTIM_RESTORE + + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSU4_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4_FLT.h new file mode 100644 index 000000000..185cc41c9 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu4_FLT.h @@ -0,0 +1,72 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract of four inputs +* +*******************************************************************************/ +#ifndef _MLIB_MSU4_FLT_H_ +#define _MLIB_MSU4_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Msu4_FLT_Ci(fltMinMul1, fltMinMul2, fltSubMul1, fltSubMul2) \ + MLIB_Msu4_FLT_FCi(fltMinMul1, fltMinMul2, fltSubMul1, fltSubMul2) + +/***************************************************************************//*! +* +* fltOut = (fltMinMul1 * fltMinMul2) - (fltSubMul1 * fltSubMul2) +* The output saturation is not implemented, thus in case +* the MSU4 of input values is outside the (-2^128, 2^128) +* interval, the output value will overflow without any detection. +*******************************************************************************/ +static inline float_t MLIB_Msu4_FLT_FCi(register float_t fltMinMul1, register float_t fltMinMul2, + register float_t fltSubMul1, register float_t fltSubMul2) +{ + return (float_t)(((float_t)fltMinMul1 * (float_t)fltMinMul2) - + ((float_t)fltSubMul1 * (float_t)fltSubMul2)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSU4_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MsuRnd_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MsuRnd_A32.h new file mode 100644 index 000000000..47b75987f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MsuRnd_A32.h @@ -0,0 +1,81 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MSURND_A32_H_ +#define _MLIB_MSURND_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MsuRnd_A32ass_Ci(a32Accum, f16Mult1, f16Mult2) \ + MLIB_MsuRnd_A32ass_FCi(a32Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* a32Out = a32Accum - ( f16Mult1 * f16Mult2) +* +*******************************************************************************/ +static inline acc32_t MLIB_MsuRnd_A32ass_FCi(register acc32_t a32Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + u64Temp = (uint64_t)a32Accum << 15U; + if (a32Accum < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x0800000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + f64Temp = (frac64_t)u64Temp; /* cast back the corrected values */ + f64Temp += (frac64_t)((int64_t)f16Mult1 * (int64_t)(-f16Mult2)) + 0x00004000; + u64Temp = (uint64_t)f64Temp >> 15U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x2000000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return (acc32_t)u64Temp; /* cast back the corrected values */ +} + + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSURND_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MsuRnd_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MsuRnd_F16_Asmi.h new file mode 100644 index 000000000..f63b2c329 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MsuRnd_F16_Asmi.h @@ -0,0 +1,127 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MSURND_F16_ASM_H_ +#define _MLIB_MSURND_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MsuRnd_F16_Asmi(f16Accum, f16Mult1, f16Mult2) \ + MLIB_MsuRnd_F16_FAsmi(f16Accum, f16Mult1, f16Mult2) +#define MLIB_MsuRndSat_F16_Asmi(f16Accum, f16Mult1, f16Mult2) \ + MLIB_MsuRndSat_F16_FAsmi(f16Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f16Out = f16Accum - ( f16Mult1 * f16Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MsuRnd_F16_FAsmi(register frac16_t f16Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Accum, f16Accum /* Transforms 16-bit input f16Val to 32-bit */ + smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + add f16Mult1, f16Mult1, #0x4000 /* Rounding */ + sub f16Accum, f16Accum, f16Mult1, asr #15 }; /* f16Accum = f16Accum - f16Mult1 * f16Mult2 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "add %1, %1, #0x4000 \n" /* Rounding */ + "sub %0, %0, %1, asr #15 \n" /* f16Accum = f16Accum - f16Mult1 * f16Mult2 */ + : "+l"(f16Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f16Out = f16Accum - ( f16Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MsuRndSat_F16_FAsmi(register frac16_t f16Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Accum, f16Accum /* Transforms 16-bit input f16Val to 32-bit */ + smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + add f16Mult1, f16Mult1, #0x4000 /* Rounding */ + sub f16Accum, f16Accum, f16Mult1, asr #15 /* f16Accum = f16Accum - f16Mult1 * f16Mult2 */ + ssat f16Accum, #16, f16Accum }; /* Saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "add %1, %1, #0x4000 \n" /* Rounding */ + "sub %0, %0, %1, asr #15 \n" /* f16Accum = f16Accum - f16Mult1 * f16Mult2 */ + "ssat %0, #16, %0 \n" /* Saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSURND_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MsuRnd_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MsuRnd_F32.h new file mode 100644 index 000000000..573f37d9c --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MsuRnd_F32.h @@ -0,0 +1,79 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MSURND_F32_H_ +#define _MLIB_MSURND_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MsuRnd_F32_Ci(f32Accum, f32Mult1, f32Mult2) \ + MLIB_MsuRnd_F32_FCi(f32Accum, f32Mult1, f32Mult2) + +/***************************************************************************//*! +* +* f32Out = f32Accum - ( f32Mult1 * f32Mult2) +* Without saturation +*******************************************************************************/ +static inline frac32_t MLIB_MsuRnd_F32_FCi(register frac32_t f32Accum, + register frac32_t f32Mult1,register frac32_t f32Mult2) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (((int64_t)f32Mult1 * (int64_t)f32Mult2)+ 0x40000000); + u64Temp = (uint64_t)f64Temp >> 31U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x200000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + f64Temp = (frac64_t)f32Accum - (frac64_t)u64Temp; /* cast back the corrected values */ + return((frac32_t)f64Temp); + +} + + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSURND_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MsuRnd_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MsuRnd_F32_Asmi.h new file mode 100644 index 000000000..802c2f335 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MsuRnd_F32_Asmi.h @@ -0,0 +1,178 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MSURND_F32_ASM_H_ +#define _MLIB_MSURND_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MsuRnd_F32lls_Asmi( f32Accum, f32Mult1, f16Mult2) \ + MLIB_MsuRnd_F32lls_FAsmi( f32Accum, f32Mult1, f16Mult2) +#define MLIB_MsuRndSat_F32_Asmi( f32Accum, f32Mult1, f32Mult2) \ + MLIB_MsuRndSat_F32_FAsmi( f32Accum, f32Mult1, f32Mult2) +#define MLIB_MsuRndSat_F32lls_Asmi( f32Accum, f32Mult1, f16Mult2) \ + MLIB_MsuRndSat_F32lls_FAsmi( f32Accum, f32Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = f32Accum - ( f32Mult1 * f16Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MsuRnd_F32lls_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1,register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Mult2, f16Mult2 /* Transforms 16-bit input f16Mult2 to 32-bit */ + smull f32Mult1, f16Mult2, f16Mult2, f32Mult1 /* f32Mult1:f32Mult2 = f32Mult1 * f16Mult2 */ + adds f32Mult1, f32Mult1, #0x4000 /* Rounding*/ + adc f16Mult2, f16Mult2, #0 /* Adds Carry Bit */ + lsl f16Mult2, f16Mult2, #17 /* f32Mult1 << 17 */ + orr f16Mult2, f16Mult2, f32Mult1, lsr #15 /* Adds last 17 bits of result */ + sub f32Accum, f32Accum, f16Mult2 }; /* Adds f32Accum */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %1, %1 \n" /* Transforms 16-bit input f16Mult2 to 32-bit */ + "smull %2, %1, %1, %2 \n" /* f32Mult1:f32Mult2 = f32Mult1 * f16Mult2 */ + "adds %2, %2, #0x4000 \n" /* Rounding*/ + "adc %1, %1, #0 \n" /* Adds Carry Bit */ + "lsl %1, %1, #17 \n" /* f32Mult1 << 17 */ + "orr %1, %1, %2, lsr #15 \n" /* Adds last 17 bits of result */ + "sub %0, %0, %1 \n" /* Adds f32Accum */ + : "+l"(f32Accum), "+l"(f16Mult2), "+l"(f32Mult1):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = f32Accum - ( f32Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MsuRndSat_F32lls_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1,register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Mult2, f16Mult2 /* Transforms 16-bit input f16Mult2 to 32-bit */ + smull f32Mult1, f16Mult2, f16Mult2, f32Mult1 /* f32Mult1:f32Mult2 = f32Mult1 * f16Mult2 */ + adds f32Mult1, f32Mult1, #0x4000 /* Rounding*/ + adc f16Mult2, f16Mult2, #0 /* Adds Carry Bit */ + lsl f16Mult2, f16Mult2, #17 /* f32Mult1 << 17 */ + orr f16Mult2, f16Mult2, f32Mult1, lsr #15 /* Adds last 17 bits of result */ + rsb f16Mult2, f16Mult2, #0 /* Negation for case of multiplication (-1)*(-1) */ + qadd f32Accum, f32Accum, f16Mult2 }; /* Acc + ( - Mul1 * Mul2) */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %1, %1 \n" /* Transforms 16-bit input f16Mult2 to 32-bit */ + "smull %2, %1, %1, %2 \n" /* f32Mult1:f32Mult2 = f32Mult1 * f16Mult2 */ + "adds %2, %2, #0x4000 \n" /* Rounding*/ + "adc %1, %1, #0 \n" /* Adds Carry Bit */ + "lsl %1, %1, #17 \n" /* f32Mult1 << 17 */ + "orr %1, %1, %2, lsr #15 \n" /* Adds last 17 bits of result */ + "rsb %1, %1, #0 \n" /* Negation for case of multiplication (-1)*(-1) */ + "qadd %0, %0, %1 \n" /* Acc + ( - Mul1 * Mul2) */ + : "+l"(f32Accum), "+l"(f16Mult2), "+l"(f32Mult1):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = f32Accum - ( f32Mult1 * f32Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MsuRndSat_F32_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1,register frac32_t f32Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Mult2, f32Mult1, f32Mult2, f32Mult1 /* R1:R2 = Mul1 * Mul2 */ + adds f32Mult2, f32Mult2, #0x40000000 /* Rounding */ + adc f32Mult1, f32Mult1, #0 /* Adds carry*/ + lsr f32Mult2, f32Mult2, #31 /* R2 >> 31 */ + orr f32Mult1, f32Mult2, f32Mult1, lsl #1 /* (R1 << 1) | R2*/ + rsb f32Mult1, f32Mult1, #0 /* Negation for case of multiplication (-1)*(-1) */ + qadd f32Accum, f32Accum, f32Mult1 }; /* Acc + ( - Mul1 * Mul2) */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %2, %1, %2, %1 \n" /* R1:R2 = Mul1 * Mul2 */ + "adds %2, %2, #0x40000000 \n" /* Rounding */ + "adc %1, %1, #0 \n" /* Adds carry*/ + "lsr %2, %2, #31 \n" /* R2 >> 31 */ + "orr %1, %2, %1, lsl #1 \n" /* (R1 << 1) | R2*/ + "rsb %1, %1, #0 \n" /* Negation for case of multiplication (-1)*(-1) */ + "qadd %0, %0, %1 \n" /* Acc + ( - Mul1 * Mul2) */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Accum), "+l"(f32Mult1), "+l"(f32Mult2):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSURND_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu_A32.h new file mode 100644 index 000000000..021f69bb0 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu_A32.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract +* +*******************************************************************************/ +#ifndef _MLIB_MSU_A32_H_ +#define _MLIB_MSU_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Msu_A32ass_Ci(a32Accum, f16Mult1, f16Mult2) \ + MLIB_Msu_A32ass_FCi(a32Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* a32Out = a32Accum - ( f16Mult1 * f16Mult2) +* +*******************************************************************************/ +static inline acc32_t MLIB_Msu_A32ass_FCi(register acc32_t a32Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + return (acc32_t)(a32Accum - MLIB_ShR_F32_Ci(((int32_t)f16Mult1 * (int32_t)f16Mult2), 15U)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSU_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu_F16_Asmi.h new file mode 100644 index 000000000..f42050e64 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu_F16_Asmi.h @@ -0,0 +1,123 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract +* +*******************************************************************************/ +#ifndef _MLIB_MSU_F16_ASM_H_ +#define _MLIB_MSU_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Msu_F16_Asmi(f16Accum, f16Mult1, f16Mult2) \ + MLIB_Msu_F16_FAsmi(f16Accum, f16Mult1, f16Mult2) +#define MLIB_MsuSat_F16_Asmi(f16Accum, f16Mult1, f16Mult2) \ + MLIB_MsuSat_F16_FAsmi(f16Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f16Out = f16Accum - ( f16Mult1 * f16Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Msu_F16_FAsmi(register frac16_t f16Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Accum, f16Accum /* Transforms 16-bit input f16Val to 32-bit */ + smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + sub f16Accum, f16Accum, f16Mult1, asr #15 }; /* f16Accum = f16Accum - f16Mult1 * f16Mult2 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "sub %0, %0, %1, asr #15 \n" /* f16Accum = f16Accum - f16Mult1 * f16Mult2 */ + : "+l"(f16Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f16Out = f16Accum - ( f16Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MsuSat_F16_FAsmi(register frac16_t f16Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Accum, f16Accum /* Transforms 16-bit input f16Val to 32-bit */ + smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + sub f16Accum, f16Accum, f16Mult1, asr #15 /* f16Accum = f16Accum - f16Mult1 * f16Mult2 */ + ssat f16Accum, #16, f16Accum }; /* Saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "sub %0, %0, %1, asr #15 \n" /* f16Accum = f16Accum - f16Mult1 * f16Mult2 */ + "ssat %0, #16, %0 \n" /* Saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSU_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu_F32_Asmi.h new file mode 100644 index 000000000..84235469d --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu_F32_Asmi.h @@ -0,0 +1,184 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract +* +*******************************************************************************/ +#ifndef _MLIB_MSU_F32_ASM_H_ +#define _MLIB_MSU_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Msu_F32_Asmi(f32Accum, f32Mult1, f32Mult2) \ + MLIB_Msu_F32_FAsmi(f32Accum, f32Mult1, f32Mult2) +#define MLIB_Msu_F32lss_Asmi(f32Accum, f16Mult1, f16Mult2) \ + MLIB_Msu_F32lss_FAsmi(f32Accum, f16Mult1, f16Mult2) +#define MLIB_MsuSat_F32_Asmi(f32Accum, f32Mult1, f32Mult2) \ + MLIB_MsuSat_F32_FAsmi(f32Accum, f32Mult1, f32Mult2) +#define MLIB_MsuSat_F32lss_Asmi(f32Accum, f16Mult1, f16Mult2) \ + MLIB_MsuSat_F32lss_FAsmi(f32Accum, f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = f32Accum - ( f32Mult1 * f32Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Msu_F32_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Mult2, f32Mult1, f32Mult2, f32Mult1 /* R1:R2 = Mul1 * Mul2 */ + lsr f32Mult2, f32Mult2, #31 /* R2 >> 31 */ + orr f32Mult1, f32Mult2, f32Mult1, lsl #1 /* (R1 << 1) | R2*/ + sub f32Accum, f32Accum, f32Mult1 }; /* Acc - Mul1 * Mul2 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %2, %1, %2, %1 \n" /* R1:R2 = Mul1 * Mul2 */ + "lsr %2, %2, #31 \n" /* R2 >> 31 */ + "orr %1, %2, %1, lsl #1 \n" /* (R1 << 1) | R2*/ + "sub %0, %0, %1 \n" /* Acc - Mul1 * Mul2 */ + : "+l"(f32Accum), "+l"(f32Mult1), "+l"(f32Mult2):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = f32Accum - ( f16Mult1 * f16Mult2) +* Without saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Msu_F32lss_FAsmi(register frac32_t f32Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + sub f32Accum, f32Accum, f16Mult1, lsl #1 }; /* Subtraction without saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "sub %0, %0, %1, lsl #1 \n" /* Subtraction without saturation */ + : "+l"(f32Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = f32Accum - ( f32Mult1 * f32Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MsuSat_F32_FAsmi(register frac32_t f32Accum, + register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Mult2, f32Mult1, f32Mult2, f32Mult1 /* R1:R2 = Mul1 * Mul2 */ + lsr f32Mult2, f32Mult2, #31 /* R2 >> 31 */ + orr f32Mult1, f32Mult2, f32Mult1, lsl #1 /* (R1 << 1) | R2 */ + rsb f32Mult1, f32Mult1, #0 /* Negation for case of multiplication (-1)*(-1) */ + qadd f32Accum, f32Accum, f32Mult1 }; /* Acc + (- Mul1 * Mul2) */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %2, %1, %2, %1 \n" /* R1:R2 = Mul1 * Mul2 */ + "lsr %2, %2, #31 \n" /* R2 >> 31 */ + "orr %1, %2, %1, lsl #1 \n" /* (R1 << 1) | R2 */ + "rsb %1, %1, #0 \n" /* Negation for case of multiplication (-1)*(-1) */ + "qadd %0, %0, %1 \n" /* Acc + (- Mul1 * Mul2) */ + : "+l"(f32Accum), "+l"(f32Mult1), "+l"(f32Mult2):); + #endif + + return f32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = f32Accum - ( f16Mult1 * f16Mult2) +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MsuSat_F32lss_FAsmi(register frac32_t f32Accum, + register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + qdsub f32Accum, f32Accum, f16Mult1 }; /* Subtraction with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "qdsub %0, %0, %1 \n" /* Subtraction with saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Accum), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f32Accum; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSU_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu_FLT.h new file mode 100644 index 000000000..7e272f07f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Msu_FLT.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply subtract +* +*******************************************************************************/ +#ifndef _MLIB_MSU_FLT_H_ +#define _MLIB_MSU_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Msu_FLT_Ci(fltAccum, fltMult1, fltMult2) \ + MLIB_Msu_FLT_FCi(fltAccum, fltMult1, fltMult2) + +/***************************************************************************//*! +* +* fltOut = fltAccum - ( fltMult1 * fltMult2) +* The output saturation is not implemented, thus in case +* the MSU of input values is outside the (-2^128, 2^128) +* interval, the output value will overflow without any detection. +*******************************************************************************/ +static inline float_t MLIB_Msu_FLT_FCi(register float_t fltAccum, + register float_t fltMult1, register float_t fltMult2) +{ + return((float_t) (fltAccum - (fltMult1 * fltMult2))); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MSU_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_A32.h new file mode 100644 index 000000000..3899de40a --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_A32.h @@ -0,0 +1,129 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MULRND_A32_H_ +#define _MLIB_MULRND_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MulRnd_F16as_Ci(a32Accum, f16Mult) MLIB_MulRnd_F16as_FCi(a32Accum, f16Mult) +#define MLIB_MulNegRnd_F16as_Ci(a32Accum, f16Mult) MLIB_MulNegRnd_F16as_FCi(a32Accum, f16Mult) +#define MLIB_MulRnd_A32_Ci(a32Mult1, a32Mult2) MLIB_MulRnd_A32_FCi(a32Mult1, a32Mult2) +#define MLIB_MulNegRnd_A32_Ci(a32Mult1, a32Mult2) MLIB_MulNegRnd_A32_FCi(a32Mult1, a32Mult2) + +/***************************************************************************//*! +* +* f16Out = a32Accum * f16Mult +* Without saturation +*******************************************************************************/ +static inline frac16_t MLIB_MulRnd_F16as_FCi(register acc32_t a32Accum, register frac16_t f16Mult) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (frac64_t)a32Accum * f16Mult + 0x4000; + u64Temp = (uint64_t)f64Temp >> 15U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x2000000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return (frac16_t)u64Temp; /* cast back the corrected values */ +} + +/***************************************************************************//*! +* +* f16Out = a32Accum * -f16Mult +* +*******************************************************************************/ +static inline frac16_t MLIB_MulNegRnd_F16as_FCi(register acc32_t a32Accum, register frac16_t f16Mult) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (frac64_t)a32Accum * (-f16Mult) + 0x4000; + u64Temp = (uint64_t)f64Temp >> 15U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x2000000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return (frac16_t)u64Temp; /* cast back the corrected values */ +} + +/***************************************************************************//*! +* +* a32Out = a32Mult1 * a32Mult2 +* Without saturation +*******************************************************************************/ +static inline acc32_t MLIB_MulRnd_A32_FCi(register acc32_t a32Mult1, register acc32_t a32Mult2) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (acc64_t)a32Mult1 * a32Mult2 + (acc64_t)0x4000; + u64Temp = (uint64_t)f64Temp >> 15U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x2000000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return (acc32_t)u64Temp; /* cast back the corrected values */ +} + +/***************************************************************************//*! +* +* a32Out = - a32Mult1 * a32Mult2 +* Without saturation +*******************************************************************************/ +static inline acc32_t MLIB_MulNegRnd_A32_FCi(register acc32_t a32Mult1, register acc32_t a32Mult2) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (acc64_t)a32Mult1 * (-a32Mult2) + (acc64_t)0x4000; + u64Temp = (uint64_t)f64Temp >> 15U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x2000000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return (acc32_t)u64Temp; /* cast back the corrected values */ +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MULRND_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_A32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_A32_Asmi.h new file mode 100644 index 000000000..9421a2473 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_A32_Asmi.h @@ -0,0 +1,214 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MULRND_A32_ASM_H_ +#define _MLIB_MULRND_A32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MulRndSat_F16as_Asmi(a32Accum, f16Mult) MLIB_MulRndSat_F16as_FAsmi(a32Accum, f16Mult) +#define MLIB_MulNegRndSat_F16as_Asmi(a32Accum, f16Mult) MLIB_MulNegRndSat_F16as_FAsmi(a32Accum, f16Mult) +#define MLIB_MulRndSat_A32_Asmi(a32Mult1, a32Mult2) MLIB_MulRndSat_A32_FAsmi(a32Mult1, a32Mult2) +#define MLIB_MulNegRndSat_A32_Asmi(a32Mult1, a32Mult2) MLIB_MulNegRndSat_A32_FAsmi(a32Mult1, a32Mult2) +/***************************************************************************//*! +* +* f16Out = a32Accum * f16Mult +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MulRndSat_F16as_FAsmi(register acc32_t a32Accum, register frac16_t f16Mult) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ lsl f16Mult, f16Mult, #16 /* f16Mult << 16 */ + smull a32Accum, f16Mult, f16Mult, a32Accum /* a32Accum * (f16Mult << 16) */ + lsrs a32Accum, a32Accum, #31 /* a32Accum >> 31 */ + adc a32Accum, a32Accum, #0 /* Rounding */ + qdadd f16Mult, a32Accum, f16Mult /* Correction of result for fractional multiplication */ + ssat f16Mult, #16, f16Mult }; /* Saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "lsl %0, %0, #16 \n" /* f16Mult << 16 */ + "smull %1, %0, %0, %1 \n" /* a32Accum * (f16Mult << 16) */ + "lsrs %1, %1, #31 \n" /* a32Accum >> 31 */ + "adc %1, %1, #0 \n" /* Rounding */ + "qdadd %0, %1, %0 \n" /* Correction of result for fractional multiplication */ + "ssat %0, #16, %0 \n" /* Saturation */ + : "+l"(f16Mult), "+l"(a32Accum):); + #endif + + return f16Mult; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f16Out = - a32Accum * f16Mult +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MulNegRndSat_F16as_FAsmi(register acc32_t a32Accum, register frac16_t f16Mult) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ lsl f16Mult, f16Mult, #16 /* f16Mult << 16 */ + smull a32Accum, f16Mult, f16Mult, a32Accum /* a32Accum * (f16Mult << 16) */ + lsrs a32Accum, a32Accum, #31 /* a32Accum >> 31 */ + adc a32Accum, a32Accum, #0 /* Rounding */ + rsb a32Accum, a32Accum, #0 /* a32Accum = - a32Accum */ + qdsub f16Mult, a32Accum, f16Mult /* f16Mult = a32Accum - 2 * f16Mult */ + ssat f16Mult, #16, f16Mult }; /* Saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "lsl %0, %0, #16 \n" /* f16Mult << 16 */ + "smull %1, %0, %0, %1 \n" /* a32Accum * (f16Mult << 16) */ + "lsrs %1, %1, #31 \n" /* a32Accum >> 31 */ + "adc %1, %1, #0 \n" /* Rounding */ + "rsb %1, %1, #0 \n" /* a32Accum = - a32Accum */ + "qdsub %0, %1, %0 \n" /* f16Mult = a32Accum - 2 * f16Mult */ + "ssat %0, #16, %0 \n" /* Saturation */ + : "+l"(f16Mult), "+l"(a32Accum):); + #endif + + return f16Mult; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* a32Out = a32Mult1 * a32Mult2 +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline acc32_t MLIB_MulRndSat_A32_FAsmi(register acc32_t a32Mult1, register acc32_t a32Mult2) +{ + register acc32_t a32Out=0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull a32Mult1, a32Mult2, a32Mult2, a32Mult1 /* a32Mult1 * a32Mult2 */ + lsrs a32Mult1, a32Mult1, #15 /* a32Mult1 >> 15 */ + adc a32Mult1, a32Mult1, #0 /* Rounding */ + ssat a32Out, #15, a32Mult2 /* Saturates to a signed 15-bit value */ + cmp a32Out, a32Mult2 /* Compares saturated and unsaturated values */ + lsl a32Out, a32Out, #17 /* a32Out << 17 */ + it ne /* Condition block */ + movne a32Mult1, a32Out /* If saturated and unsaturated values are not equal, then a32Mult1 = a32Out */ + qadd a32Out, a32Out, a32Mult1 }; /* a32Out = a32Out + a32Mult1 with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %1, %2, %2, %1 \n" /* a32Mult1 * a32Mult2 */ + "lsrs %1, %1, #15\n" /* a32Mult1 >> 15 */ + "adc %1, %1, #0 \n" /* Rounding */ + "ssat %0, #15, %2 \n" /* Saturates to a signed 15-bit value */ + "cmp %0, %2 \n" /* Compares saturated and unsaturated values */ + "lsl %0, %0, #17 \n" /* a32Out << 17 */ + "it ne \n" /* Condition block */ + "movne %1, %0 \n" /* If saturated and unsaturated values are not equal, then a32Mult1 = a32Out */ + "qadd %0, %0, %1 \n" /* a32Out = a32Out + a32Mult1 with saturation */ + : "=&l"(a32Out), "+l"(a32Mult1), "+l"(a32Mult2):); + #endif + + return a32Out; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* a32Out = - a32Mult1 * a32Mult2 +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline acc32_t MLIB_MulNegRndSat_A32_FAsmi(register acc32_t a32Mult1, register acc32_t a32Mult2) +{ + register acc32_t a32Out=0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull a32Mult1, a32Mult2, a32Mult2, a32Mult1 /* a32Mult1 * a32Mult2 */ + lsrs a32Mult1, a32Mult1, #15 /* a32Mult1 >> 15 */ + adc a32Mult1, a32Mult1, #-1 /* a32Mult1 = a32Mult1 - 1 + Carry */ + ssat a32Out, #15, a32Mult2 /* Saturates to a signed 15-bit value */ + cmp a32Out, a32Mult2 /* Compares saturated and unsaturated values */ + it ne /* Condition block */ + lslne a32Mult1, a32Out, #17 /* If saturated and unsaturated values are not equal, then a32Mult1 = a32Out << 17 */ + mvn a32Mult2, a32Out, lsl #17 /* a32Mult2 = -1 - a32Out << 17 */ + qsub a32Out, a32Mult2, a32Mult1 }; /* a32Out = (-1 - a32Out << 17) - a32Mult1 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %1, %2, %2, %1 \n" /* a32Mult1 * a32Mult2 */ + "lsrs %1, %1, #15\n" /* a32Mult1 >> 15 */ + "adc %1, %1, #-1 \n" /* a32Mult1 = a32Mult1 - 1 + Carry */ + "ssat %0, #15, %2 \n" /* Saturates to a signed 15-bit value */ + "cmp %0, %2 \n" /* Compares saturated and unsaturated values */ + "it ne \n" /* Condition block */ + "lslne %1, %0, #17 \n" /* If saturated and unsaturated values are not equal, then a32Mult1 = a32Out << 17 */ + "mvn %2, %0, lsl #17 \n" /* a32Mult2 = -1 - a32Out << 17 */ + "qsub %0, %2, %1 \n" /* a32Out = (-1 - a32Out << 17) - a32Mult1 */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "=&l"(a32Out), "+l"(a32Mult1), "+l"(a32Mult2):); + #endif + + return a32Out; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MULRND_A32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_F16.h new file mode 100644 index 000000000..b92068cbe --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_F16.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MULRND_F16_H_ +#define _MLIB_MULRND_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MulRnd_F16_Ci(f16Mult1, f16Mult2) MLIB_MulRnd_F16_FCi(f16Mult1, f16Mult2) +#define MLIB_MulNegRnd_F16_Ci(f16Mult1, f16Mult2) MLIB_MulNegRnd_F16_FCi(f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f16Out = f16Mult1 * f16Mult2 +* Without saturation +*******************************************************************************/ +static inline frac16_t MLIB_MulRnd_F16_FCi(register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + return(frac16_t)MLIB_ShR_F32_Ci((int32_t)f16Mult1 * (int32_t)f16Mult2 + 0x4000, 15U); +} + +/***************************************************************************//*! +* +* f16Out = f16Mult1 * f16Mult2 +* +*******************************************************************************/ +static inline frac16_t MLIB_MulNegRnd_F16_FCi(register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + return(frac16_t)MLIB_ShR_F32_Ci((int32_t)f16Mult1 * (int32_t)(-f16Mult2) + 0x4000, 15U); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MULRND_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_F16_Asmi.h new file mode 100644 index 000000000..8c47761f4 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_F16_Asmi.h @@ -0,0 +1,88 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MULRND_F16_ASM_H_ +#define _MLIB_MULRND_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MulRndSat_F16_Asmi(f16Mult1, f16Mult2) MLIB_MulRndSat_F16_FAsmi(f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f16Out = f16Mult1 * f16Mult2 +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MulRndSat_F16_FAsmi(register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + add f16Mult1, f16Mult1, #0x4000 /* Rounding */ + ssat f16Mult1, #16, f16Mult1, asr #15 }; /* Converts result to frac16 and saturates */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %0, %0, %1 \n" /* f16Mult1 * f16Mult2 */ + "add %0, %0, #0x4000 \n" /* Rounding */ + "ssat %0, #16, %0, asr #15 \n" /* Converts result to frac16 and saturates */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Mult1; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MULRND_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_F32.h new file mode 100644 index 000000000..e8f137ba6 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_F32.h @@ -0,0 +1,129 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MULRND_F32_H_ +#define _MLIB_MULRND_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Neg_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MulRnd_F32_Ci(f32Mult1, f32Mult2) MLIB_MulRnd_F32_FCi(f32Mult1, f32Mult2) +#define MLIB_MulRnd_F32ls_Ci(f32Mult1, f16Mult2) MLIB_MulRnd_F32ls_FCi(f32Mult1, f16Mult2) +#define MLIB_MulNegRnd_F32_Ci(f32Mult1, f32Mult2) MLIB_MulNegRnd_F32_FCi(f32Mult1, f32Mult2) +#define MLIB_MulNegRnd_F32ls_Ci(f32Mult1, f16Mult2) MLIB_MulNegRnd_F32ls_FCi(f32Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = f32Mult1 * f32Mult2 +* Without saturation +*******************************************************************************/ +static inline frac32_t MLIB_MulRnd_F32_FCi(register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (int64_t)f32Mult1 * f32Mult2 + (int64_t)0x40000000; + u64Temp = (uint64_t)f64Temp >> 31U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x200000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return (frac32_t)u64Temp; /* cast back the corrected values */ +} + +/***************************************************************************//*! +* +* f32Out = f32Mult1 * f16Mult2 +* Without saturation +*******************************************************************************/ +static inline frac32_t MLIB_MulRnd_F32ls_FCi(register frac32_t f32Mult1, register frac16_t f16Mult2) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (int64_t)f32Mult1 * (int16_t)f16Mult2 + 0x4000; + u64Temp = (uint64_t)f64Temp >> 15U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x2000000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return (frac32_t)u64Temp; /* cast back the corrected values */ +} + +/***************************************************************************//*! +* +* f32Out = f32Mult1 * -f32Mult2 +* +*******************************************************************************/ +static inline frac32_t MLIB_MulNegRnd_F32_FCi(register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (int64_t)f32Mult1 * (int64_t)f32Mult2 + 0x40000000; + u64Temp = (uint64_t)f64Temp >> 31U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x200000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return MLIB_Neg_F32_FCi((frac32_t)u64Temp); /* cast back the corrected values */ +} + +/***************************************************************************//*! +* +* f32Out = f32Mult1 * -f16Mult2 +* +*******************************************************************************/ +static inline frac32_t MLIB_MulNegRnd_F32ls_FCi(register frac32_t f32Mult1, register frac16_t f16Mult2) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (int64_t)f32Mult1 * (int64_t)f16Mult2 + 0x4000; + u64Temp = (uint64_t)f64Temp >> 15U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x2000000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return MLIB_Neg_F32_FCi((frac32_t)u64Temp); /* cast back the corrected values */ +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MULRND_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_F32_Asmi.h new file mode 100644 index 000000000..20219c3a1 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_MulRnd_F32_Asmi.h @@ -0,0 +1,123 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply with rounding +* +*******************************************************************************/ +#ifndef _MLIB_MULRND_F32_ASM_H_ +#define _MLIB_MULRND_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MulRndSat_F32_Asmi(f32Mult1, f32Mult2) MLIB_MulRndSat_F32_FAsmi(f32Mult1, f32Mult2) +#define MLIB_MulRndSat_F32ls_Asmi(f32Mult1, f16Mult2) MLIB_MulRndSat_F32ls_FAsmi(f32Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = f32Mult1 * f32Mult2 +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MulRndSat_F32_FAsmi(register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Mult2, f32Mult1, f32Mult1, f32Mult2 /* f32Mult1 * f32Mult2 */ + lsrs f32Mult2, f32Mult2, #31 /* f32Mult2 >> 31 */ + adc f32Mult2, f32Mult2, #0 /* Rounding */ + qdadd f32Mult1, f32Mult2, f32Mult1 }; /* 2 * f32Mult1 + f32Mult2 with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %1, %0, %0, %1 \n" /* f32Mult1:f32Mult2 = f32Mult1 * f32Mult2 */ + "lsrs %1, %1, #31 \n" /* f32Mult2 >> 31 */ + "adc %1, %1, #0 \n" /* Rounding */ + "qdadd %0, %1, %0 \n" /* 2 * f32Mult1 + f32Mult2 with saturation */ + : "+l"(f32Mult1), "+l"(f32Mult2):); + #endif + + return f32Mult1; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = f32Mult1 * f16Mult2 +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MulRndSat_F32ls_FAsmi(register frac32_t f32Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ lsl f16Mult2, f16Mult2, #16 /* f16Mult2 << 16 */ + smull f16Mult2, f32Mult1, f32Mult1, f16Mult2 /* f32Mult1 * f16Mult2 */ + lsrs f16Mult2, f16Mult2, #31 /* f16Mult2 >> 31 */ + adc f16Mult2, f16Mult2, #0 /* Rounding */ + qdadd f32Mult1, f16Mult2, f32Mult1 }; /* 2 * f32Mult1 + f16Mult2 with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "lsl %1, %1, #16 \n" /* f16Mult2 << 16 */ + "smull %1, %0, %0, %1 \n" /* f32Mult1:f16Mult2 = f32Mult1 * f16Mult2 */ + "lsrs %1, %1, #31 \n" /* f16Mult2 >> 31 */ + "adc %1, %1, #0 \n" /* Rounding */ + "qdadd %0, %1, %0 \n" /* 2 * f32Mult1 + f16Mult2 with saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Mult1), "+l"(f16Mult2):); + #endif + + return f32Mult1; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MULRND_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_A32.h new file mode 100644 index 000000000..013301317 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_A32.h @@ -0,0 +1,131 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply +* +*******************************************************************************/ +#ifndef _MLIB_MUL_A32_H_ +#define _MLIB_MUL_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mul_F16as_Ci(a32Accum, f16Mult) MLIB_Mul_F16as_FCi(a32Accum, f16Mult) +#define MLIB_MulNeg_F16as_Ci(a32Accum, f16Mult) MLIB_MulNeg_F16as_FCi(a32Accum, f16Mult) +#define MLIB_Mul_A32_Ci(a32Mult1, a32Mult2) MLIB_Mul_A32_FCi( a32Mult1, a32Mult2) +#define MLIB_MulNeg_A32_Ci(a32Mult1, a32Mult2) MLIB_MulNeg_A32_FCi( a32Mult1, a32Mult2) + +/***************************************************************************//*! +* +* f16Out = a32Accum * f16Mult +* Without saturation +*******************************************************************************/ +static inline frac16_t MLIB_Mul_F16as_FCi(register acc32_t a32Accum, register frac16_t f16Mult) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (frac64_t)a32Accum * f16Mult; + u64Temp = (uint64_t)f64Temp >> 15U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x2000000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return (frac16_t)u64Temp; /* cast back the corrected values */ +} + +/***************************************************************************//*! +* +* f16Out = a32Accum * -f16Mult + +*******************************************************************************/ +static inline frac16_t MLIB_MulNeg_F16as_FCi(register acc32_t a32Accum, register frac16_t f16Mult) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (frac64_t)a32Accum * (-f16Mult); + u64Temp = (uint64_t)f64Temp >> 15U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x2000000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return (frac16_t)u64Temp; /* cast back the corrected values */ +} + +/***************************************************************************//*! +* +* a32Out = a32Mult1 * a32Mult2 + +*******************************************************************************/ +static inline acc32_t MLIB_Mul_A32_FCi(register acc32_t a32Mult1, register acc32_t a32Mult2) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (acc64_t)a32Mult1 * a32Mult2; + u64Temp = (uint64_t)f64Temp >> 15U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x2000000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + + return (acc32_t)u64Temp; /* cast back the corrected values */ +} + +/***************************************************************************//*! +* +* a32Out = - a32Mult1 * a32Mult2 + +*******************************************************************************/ +static inline acc32_t MLIB_MulNeg_A32_FCi(register acc32_t a32Mult1, register acc32_t a32Mult2) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (acc64_t)a32Mult1 * (-a32Mult2); + u64Temp = (uint64_t)f64Temp >> 15U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x2000000000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + + return (acc32_t)u64Temp; /* cast back the corrected values */ +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MUL_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_A32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_A32_Asmi.h new file mode 100644 index 000000000..f0e288681 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_A32_Asmi.h @@ -0,0 +1,206 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply +* +*******************************************************************************/ +#ifndef _MLIB_MUL_A32_ASM_H_ +#define _MLIB_MUL_A32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MulSat_F16as_Asmi(a32Accum, f16Mult) MLIB_MulSat_F16as_FAsmi(a32Accum, f16Mult) +#define MLIB_MulNegSat_F16as_Asmi(a32Accum, f16Mult) MLIB_MulNegSat_F16as_FAsmi(a32Accum, f16Mult) +#define MLIB_MulSat_A32_Asmi(a32Mult1, a32Mult2) MLIB_MulSat_A32_FAsmi(a32Mult1, a32Mult2) +#define MLIB_MulNegSat_A32_Asmi(a32Mult1, a32Mult2) MLIB_MulNegSat_A32_FAsmi(a32Mult1, a32Mult2) +/***************************************************************************//*! +* +* f16Out = a32Accum * f16Mult +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MulSat_F16as_FAsmi(register acc32_t a32Accum, register frac16_t f16Mult) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ lsl f16Mult, f16Mult, #16 /* f16Mult << 16 */ + smull a32Accum, f16Mult, f16Mult, a32Accum /* a32Accum * (f16Mult << 16) */ + lsr a32Accum, a32Accum, #31 /* a32Accum >> 31 */ + qdadd f16Mult, a32Accum, f16Mult /* Correction of result for fractional multiplication */ + ssat f16Mult, #16, f16Mult }; /* Saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "lsl %0, %0, #16 \n" /* f16Mult << 16 */ + "smull %1, %0, %0, %1 \n" /* a32Accum * (f16Mult << 16) */ + "lsr %1, %1, #31 \n" /* a32Accum >> 31 */ + "qdadd %0, %1, %0 \n" /* Correction of result for fractional multiplication */ + "ssat %0, #16, %0 \n" /* Saturation */ + : "+l"(f16Mult), "+l"(a32Accum):); + #endif + + return f16Mult; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f16Out = - a32Accum * f16Mult +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MulNegSat_F16as_FAsmi(register acc32_t a32Accum, register frac16_t f16Mult) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ lsl f16Mult, f16Mult, #16 /* f16Mult << 16 */ + smull a32Accum, f16Mult, f16Mult, a32Accum /* a32Accum * (f16Mult << 16) */ + lsr a32Accum, a32Accum, #31 /* a32Accum >> 31 */ + rsb a32Accum, a32Accum, #0 /* a32Accum = - a32Accum */ + qdsub f16Mult, a32Accum, f16Mult /* f16Mult = a32Accum - 2 * f16Mult */ + ssat f16Mult, #16, f16Mult }; /* Saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "lsl %0, %0, #16 \n" /* f16Mult << 16 */ + "smull %1, %0, %0, %1 \n" /* a32Accum * (f16Mult << 16) */ + "lsr %1, %1, #31 \n" /* a32Accum >> 31 */ + "rsb %1, %1, #0 \n" /* a32Accum = - a32Accum */ + "qdsub %0, %1, %0 \n" /* f16Mult = a32Accum - 2 * f16Mult */ + "ssat %0, #16, %0 \n" /* Saturation */ + : "+l"(f16Mult), "+l"(a32Accum):); + #endif + + return f16Mult; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = f32Mult1 * f32Mult2 +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline acc32_t MLIB_MulSat_A32_FAsmi(register acc32_t a32Mult1, register acc32_t a32Mult2) +{ + register acc32_t a32Out=0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull a32Mult1, a32Mult2, a32Mult2, a32Mult1 /* a32Mult1 * a32Mult2 */ + ssat a32Out, #15, a32Mult2 /* Saturates to a signed 15-bit value */ + cmp a32Out, a32Mult2 /* Compares saturated and unsaturated values */ + lsl a32Out, a32Out, #17 /* a32Out << 17 */ + ite eq /* Condition block */ + addeq a32Out, a32Out, a32Mult1, lsr #15 /* If saturated and unsaturated values are equal, then does not saturate result */ + qaddne a32Out, a32Out, a32Out }; /* If saturated and unsaturated values are not equal, then saturates result */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %1, %2, %2, %1 \n" /* a32Mult1 * a32Mult2 */ + "ssat %0, #15, %2 \n" /* Saturates to a signed 15-bit value */ + "cmp %0, %2 \n" /* Compares saturated and unsaturated values */ + "lsl %0, %0, #17 \n" /* a32Out << 17 */ + "ite eq \n" /* Condition block */ + "addeq %0, %0, %1, lsr #15 \n" /* If saturated and unsaturated values are equal, then does not saturate result */ + "qaddne %0, %0, %0 \n" /* If saturated and unsaturated values are not equal, then saturates result */ + : "=&l"(a32Out), "+l"(a32Mult1), "+l"(a32Mult2):); + #endif + + return a32Out; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = - f32Mult1 * f32Mult2 +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline acc32_t MLIB_MulNegSat_A32_FAsmi(register acc32_t a32Mult1, register acc32_t a32Mult2) +{ + register acc32_t a32Out=0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull a32Mult1, a32Mult2, a32Mult2, a32Mult1 /* a32Mult1 * a32Mult2 */ + ssat a32Out, #15, a32Mult2 /* Saturates to a signed 15-bit value */ + cmp a32Out, a32Mult2 /* Compares saturated and unsaturated values */ + lsl a32Out, a32Out, #17 /* a32Out << 17 */ + ittee eq /* Condition block */ + addeq a32Out, a32Out, a32Mult1, lsr #15 /* If saturated and unsaturated values are equal, then does not saturate result */ + rsbeq a32Out, a32Out, #0 /* Negation */ + qaddne a32Out, a32Out, a32Out /* If saturated and unsaturated values are not equal, then saturates result */ + mvnne a32Out, a32Out }; /* Negation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %1, %2, %2, %1 \n" /* a32Mult1 * a32Mult2 */ + "ssat %0, #15, %2 \n" /* Saturates to a signed 15-bit value */ + "cmp %0, %2 \n" /* Compares saturated and unsaturated values */ + "lsl %0, %0, #17 \n" /* a32Out << 17 */ + "ittee eq \n" /* Condition block */ + "addeq %0, %0, %1, lsr #15 \n" /* If saturated and unsaturated values are equal, then does not saturate result */ + "rsbeq %0, %0, #0 \n" /* Negation */ + "qaddne %0, %0, %0 \n" /* If saturated and unsaturated values are not equal, then saturates result */ + "mvnne %0, %0 \n" /* Negation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "=&l"(a32Out), "+l"(a32Mult1), "+l"(a32Mult2):); + #endif + + return a32Out; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MUL_A32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_F16.h new file mode 100644 index 000000000..43852bd06 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_F16.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply +* +*******************************************************************************/ +#ifndef _MLIB_MUL_F16_H_ +#define _MLIB_MUL_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mul_F16_Ci(f16Mult1, f16Mult2) MLIB_Mul_F16_FCi(f16Mult1, f16Mult2) +#define MLIB_MulNeg_F16_Ci(f16Mult1, f16Mult2) MLIB_MulNeg_F16_FCi(f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f16Out = f16Mult1 * f16Mult2 +* Without saturation +*******************************************************************************/ +static inline frac16_t MLIB_Mul_F16_FCi(register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + return(frac16_t)MLIB_ShR_F32_Ci((int32_t)f16Mult1 * (int32_t)f16Mult2, 15U); +} + +/***************************************************************************//*! +* +* f16Out = f16Mult1 * f16Mult2 +* +*******************************************************************************/ +static inline frac16_t MLIB_MulNeg_F16_FCi(register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + return(frac16_t)MLIB_ShR_F32_Ci((int32_t)f16Mult1 * (int32_t)(-f16Mult2), 15U); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MUL_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_F16_Asmi.h new file mode 100644 index 000000000..2ab74c8c9 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_F16_Asmi.h @@ -0,0 +1,86 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply +* +*******************************************************************************/ +#ifndef _MLIB_MUL_F16_ASM_H_ +#define _MLIB_MUL_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MulSat_F16_Asmi(f16Mult1, f16Mult2) MLIB_MulSat_F16_FAsmi(f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f16Out = f16Mult1 * f16Mult2 +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_MulSat_F16_FAsmi(register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + ssat f16Mult1, #16, f16Mult1, asr #15 }; /* Converts result to frac16 and saturates */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %0, %0, %1 \n" /* f16Mult1 * f16Mult2 */ + "ssat %0, #16, %0, asr #15 \n" /* Converts result to frac16 and saturates */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f16Mult1; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MUL_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_F32.h new file mode 100644 index 000000000..3f80648e7 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_F32.h @@ -0,0 +1,115 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply +* +*******************************************************************************/ +#ifndef _MLIB_MUL_F32_H_ +#define _MLIB_MUL_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Shift_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mul_F32_Ci(f32Mult1, f32Mult2) MLIB_Mul_F32_FCi(f32Mult1, f32Mult2) +#define MLIB_Mul_F32ss_Ci(f16Mult1, f16Mult2) MLIB_Mul_F32ss_FCi(f16Mult1, f16Mult2) +#define MLIB_MulNeg_F32_Ci(f32Mult1, f32Mult2) MLIB_MulNeg_F32_FCi(f32Mult1, f32Mult2) +#define MLIB_MulNeg_F32ss_Ci(f16Mult1, f16Mult2) MLIB_MulNeg_F32ss_FCi(f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = f32Mult1 * f32Mult2 +* Without saturation +*******************************************************************************/ +static inline frac32_t MLIB_Mul_F32_FCi(register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (frac64_t)f32Mult1 * f32Mult2; + u64Temp = (uint64_t)f64Temp >> 31U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x200000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return (frac32_t)u64Temp; /* cast back the corrected values */ +} + +/***************************************************************************//*! +* +* f32Out = f16Mult1 * f16Mult2 +* Without saturation +*******************************************************************************/ +static inline frac32_t MLIB_Mul_F32ss_FCi(register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + return(frac32_t) MLIB_Sh1L_F32_Ci((int32_t)f16Mult1 * (int32_t)f16Mult2); +} + +/***************************************************************************//*! +* +* f32Out = f32Mult1 * -f32Mult2 +* +*******************************************************************************/ +static inline frac32_t MLIB_MulNeg_F32_FCi(register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + register frac64_t f64Temp; + register uint64_t u64Temp; + + f64Temp = (frac64_t)f32Mult1 * f32Mult2; + u64Temp = (uint64_t)(f64Temp) >> 31U; /* Misra compliance signed shift using unsigned type*/ + if (f64Temp < 0) /* to compensate unsigned shift error with signed type need to */ + { u64Temp -= 0x200000000U;} /* subtract the value 2^(data type bits number - shifted value) */ + return MLIB_Neg_F32_FCi((frac32_t)u64Temp); /* cast back the corrected values */ +} + +/***************************************************************************//*! +* +* f32Out = f16Mult1 * -f16Mult2 +* +*******************************************************************************/ +static inline frac32_t MLIB_MulNeg_F32ss_FCi(register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + return(frac32_t)(MLIB_Sh1L_F32_Ci((int32_t)f16Mult1 * (int32_t)(-f16Mult2))); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MUL_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_F32_Asmi.h new file mode 100644 index 000000000..366edc890 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_F32_Asmi.h @@ -0,0 +1,116 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply +* +*******************************************************************************/ +#ifndef _MLIB_MUL_F32_ASM_H_ +#define _MLIB_MUL_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_MulSat_F32_Asmi(f32Mult1, f32Mult2) MLIB_MulSat_F32_FAsmi(f32Mult1, f32Mult2) +#define MLIB_MulSat_F32ss_Asmi(f16Mult1, f16Mult2) MLIB_MulSat_F32ss_FAsmi(f16Mult1, f16Mult2) + +/***************************************************************************//*! +* +* f32Out = f32Mult1 * f32Mult2 +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MulSat_F32_FAsmi(register frac32_t f32Mult1, register frac32_t f32Mult2) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smull f32Mult2, f32Mult1, f32Mult1, f32Mult2 /* f32Mult1 * f32Mult2 */ + lsr f32Mult2, f32Mult2, #31 /* f32Mult2 >> 31 */ + qdadd f32Mult1, f32Mult2, f32Mult1 }; /* Converts result to frac32 and saturates */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smull %1, %0, %0, %1 \n" /* f32Mult1 * f32Mult2 */ + "lsr %1, %1, #31 \n" /* f32Mult2 >> 31 */ + "qdadd %0, %1, %0 \n" /* Converts result to frac32 and saturates */ + : "+l"(f32Mult1), "+l"(f32Mult2):); + #endif + + return f32Mult1; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* f32Out = f16Mult1 * f16Mult2 +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_MulSat_F32ss_FAsmi(register frac16_t f16Mult1, register frac16_t f16Mult2) +{ + register frac32_t f32Out=0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ smulbb f16Mult1, f16Mult1, f16Mult2 /* f16Mult1 * f16Mult2 */ + qadd f32Out, f16Mult1, f16Mult1 }; /* Converts result to fractional and saturates */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "smulbb %1, %1, %2 \n" /* f16Mult1 * f16Mult2 */ + "qadd %0, %1, %1 \n" /* Converts result to fractional and saturates */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "=l"(f32Out), "+l"(f16Mult1): "l"(f16Mult2)); + #endif + + return f32Out; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MUL_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_FLT.h new file mode 100644 index 000000000..870c2df26 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Mul_FLT.h @@ -0,0 +1,83 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Multiply +* +*******************************************************************************/ +#ifndef _MLIB_MUL_FLT_H_ +#define _MLIB_MUL_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Mul_FLT_Ci(fltMult1, fltMult2) MLIB_Mul_FLT_FCi(fltMult1, fltMult2) +#define MLIB_MulNeg_FLT_Ci(fltMult1, fltMult2) MLIB_MulNeg_FLT_FCi(fltMult1, fltMult2) + +/***************************************************************************//*! +* +* fltOut = fltMult1 * fltMult2 +* The output saturation is not implemented, thus in case +* the multiplication of input values is outside the (-2^128, 2^128) +* interval, the output value will overflow without any detection. +*******************************************************************************/ +static inline float_t MLIB_Mul_FLT_FCi(register float_t fltMult1, register float_t fltMult2) +{ + return((float_t)(fltMult1 * fltMult2)); +} + +/***************************************************************************//*! +* +* fltOut = fltMult1 * -fltMult2 +* The output saturation is not implemented, thus in case +* the multiplication of input values is outside the (-2^128, 2^128) +* interval, the output value will overflow without any detection. +* +*******************************************************************************/ +static inline float_t MLIB_MulNeg_FLT_FCi(register float_t fltMult1, register float_t fltMult2) +{ + return (float_t)(-(fltMult1 * fltMult2)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_MUL_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_F16.h new file mode 100644 index 000000000..91d609405 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_F16.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Negation +* +*******************************************************************************/ +#ifndef _MLIB_NEG_F16_H_ +#define _MLIB_NEG_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Neg_F16_Ci(f16Val) MLIB_Neg_F16_FCi(f16Val) + +/***************************************************************************//*! +* +* f16Out = -f16Val +* Without saturation +*******************************************************************************/ +static inline frac16_t MLIB_Neg_F16_FCi(register frac16_t f16Val) +{ + return((frac16_t)(-f16Val)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_NEG_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_F16_Asmi.h new file mode 100644 index 000000000..c0a1d6871 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_F16_Asmi.h @@ -0,0 +1,86 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Negation +* +*******************************************************************************/ +#ifndef _MLIB_NEG_F16_ASM_H_ +#define _MLIB_NEG_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_NegSat_F16_Asmi(f16Val) MLIB_NegSat_F16_FAsmi(f16Val) + +/***************************************************************************//*! +* +* f16Out = -f16Val +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_NegSat_F16_FAsmi(register frac16_t f16Val) +{ + register frac16_t f16Out = 0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ qsub16 f16Out, f16Out, f16Val }; /* f16Out = 0 - f16Val */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "qsub16 %0, %0, %1 \n" /* f16Out = 0 - f16Val */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Out): "l"(f16Val)); + #endif + + return f16Out; +} +RTCESL_INLINE_OPTIM_RESTORE + + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_NEG_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_F32.h new file mode 100644 index 000000000..c0e5d6459 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_F32.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Negation +* +*******************************************************************************/ +#ifndef _MLIB_NEG_F32_H_ +#define _MLIB_NEG_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Neg_F32_Ci(f32Val) MLIB_Neg_F32_FCi(f32Val) + +/***************************************************************************//*! +* +* f32Out = -f32Val +* Without saturation +*******************************************************************************/ +static inline frac32_t MLIB_Neg_F32_FCi(register frac32_t f32Val) +{ + return((frac32_t)(-f32Val)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_NEG_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_F32_Asmi.h new file mode 100644 index 000000000..2c36979a1 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_F32_Asmi.h @@ -0,0 +1,86 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Negation +* +*******************************************************************************/ +#ifndef _MLIB_NEG_F32_ASM_H_ +#define _MLIB_NEG_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_NegSat_F32_Asmi(f32Val) MLIB_NegSat_F32_FAsmi(f32Val) + +/***************************************************************************//*! +* +* f32Out = -f32Val +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_NegSat_F32_FAsmi(register frac32_t f32Val) +{ + register frac32_t f32Out = 0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ qsub f32Out, f32Out, f32Val }; /* f32Out = 0 - f32Val */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "qsub %0, %0, %1 \n" /* f32Out = 0 - f32Val */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Out): "l"(f32Val)); + #endif + + return f32Out; +} +RTCESL_INLINE_OPTIM_RESTORE + + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_NEG_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_FLT.h new file mode 100644 index 000000000..b3556dfd1 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Neg_FLT.h @@ -0,0 +1,69 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Negation +* +*******************************************************************************/ +#ifndef _MLIB_NEG_FLT_H_ +#define _MLIB_NEG_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Neg_FLT_Ci(fltVal) MLIB_Neg_FLT_FCi(fltVal) + +/***************************************************************************//*! +* +* fltOut = -fltVal +* The output saturation is not implemented, thus in case +* the negation of input value is outside the (-2^128, 2^128) +* interval, the output value will overflow without any detection. +*******************************************************************************/ +static inline float_t MLIB_Neg_FLT_FCi(register float_t fltVal) +{ + return((float_t)(-fltVal)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_NEG_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Rcp1Q_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Rcp1Q_A32.h new file mode 100644 index 000000000..3e0e42fef --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Rcp1Q_A32.h @@ -0,0 +1,108 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Reciprocal value +* +*******************************************************************************/ +#ifndef _MLIB_RCP1Q_A32_H_ +#define _MLIB_RCP1Q_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Rcp1Q1_A32s_Ci(f16Denom) MLIB_Rcp1Q1_A32s_FCi(f16Denom) +#define MLIB_Rcp1Q_A32s_Ci(f16Denom) MLIB_Rcp1Q_A32s_FCi(f16Denom) + +/***************************************************************************//*! +* @brief 16-bit input 32-output 16-bit precision one quadrant reciprocal function +* +* @param in frac16_t f16Denom - Denominator in <-1;1) in frac16_t +* @return This function returns - acc32_t value [-65536.0;65536.0 - (2^-15)] +* +* @remarks This function calculates the multiplicative inverse value of +* the fractional input: +* result = FRAC16(1) / f16Denom. The function calculates +* the result with 16-bit division precision. +* If the denominator is 0, the output is 0x7FFF FFFF. +* +*******************************************************************************/ +static inline acc32_t MLIB_Rcp1Q1_A32s_FCi(register frac16_t f16Denom) +{ + if (f16Denom == 0) + { + return(frac32_t)(INT32_MAX); + } + else + { + return(acc32_t)((frac32_t)0x40000000 / (frac32_t)f16Denom); + } +} + +/***************************************************************************//*! +* @brief 16-bit input 32-output 16-bit precision one quadrant reciprocal function +* +* @param in frac16_t f16Denom - Denominator in <-1;1) in frac16_t +* @return This function returns- acc32_t value [-65536.0;65536.0 - (2^-15)] +* +* @remarks This function calculates the multiplicative inverse value of +* the fractional input: +* result = FRAC16(1) / f16Denom. The function calculates +* the result with 16-bit division precision. +* If the denominator is 0, the output is 0x7FFF FFFF. +* +*******************************************************************************/ +static inline acc32_t MLIB_Rcp1Q_A32s_FCi(register frac16_t f16Denom) +{ + if (f16Denom == 0) + { + return(frac32_t)(INT32_MAX); + } + else + { + return(acc32_t)((frac32_t)0x40000000 / (frac32_t)f16Denom); + } +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_RCP1Q_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Rcp_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Rcp_A32.h new file mode 100644 index 000000000..e5af406de --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Rcp_A32.h @@ -0,0 +1,108 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Reciprocal value +* +*******************************************************************************/ +#ifndef _MLIB_RCP_A32_H_ +#define _MLIB_RCP_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Rcp1_A32s_Ci(f16Denom) MLIB_Rcp1_A32s_FCi(f16Denom) +#define MLIB_Rcp_A32s_Ci(f16Denom) MLIB_Rcp_A32s_FCi(f16Denom) + +/***************************************************************************//*! +* @brief 16-bit input 32-output 16-bit precision reciprocal function +* +* @param in frac16_t f16Denom - Denominator in <-1;1) in frac16_t +* @return This function returns - acc32_t value [-65536.0;65536.0 - (2^-15)] +* +* @remarks This function calculates the multiplicative inverse value of +* the fractional input: +* result = FRAC16(1) / f16Denom. The function calculates +* the result with 16-bit division precision. +* If the denominator is 0, the output is 0x7FFF FFFF. +* +*******************************************************************************/ +static inline acc32_t MLIB_Rcp1_A32s_FCi(register frac16_t f16Denom) +{ + if (f16Denom == 0) + { + return(frac32_t)(INT32_MAX); + } + else + { + return(acc32_t)((frac32_t)0x40000000 / (frac32_t)f16Denom); + } +} + +/***************************************************************************//*! +* @brief 16-bit input 32-output 16-bit precision reciprocal function +* +* @param in frac16_t f16Denom - Denominator in <-1;1) in frac16_t +* @return This function returns - acc32_t value [-65536.0;65536.0 - (2^-15)] +* +* @remarks This function calculates the multiplicative inverse value of +* the fractional input: +* result = FRAC16(1) / f16Denom. The function calculates +* the result with 16-bit division precision. +* If the denominator is 0, the output is 0x7FFF FFFF. +* +*******************************************************************************/ +static inline acc32_t MLIB_Rcp_A32s_FCi(register frac16_t f16Denom) +{ + if (f16Denom == 0) + { + return(frac32_t)(INT32_MAX); + } + else + { + return(acc32_t)((frac32_t)0x40000000 / (frac32_t)f16Denom); + } +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_RCP_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Rnd_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Rnd_F32.h new file mode 100644 index 000000000..698e14595 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Rnd_F32.h @@ -0,0 +1,69 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Rounding +* +*******************************************************************************/ +#ifndef _MLIB_RND_F32_H_ +#define _MLIB_RND_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Add_F32.h" +#include "MLIB_Conv_F32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Rnd_F16l_Ci(f32Val) MLIB_Rnd_F16l_FCi(f32Val) + +/***************************************************************************//*! +* +* Converts 32-bit number into 16-bit with rounding +* Without saturation +*******************************************************************************/ +static inline frac16_t MLIB_Rnd_F16l_FCi(register frac32_t f32Val) +{ + return(frac16_t)MLIB_Conv_F16l_Ci(MLIB_Add_F32_Ci(f32Val, (frac32_t)0x00008000)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_RND_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Rnd_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Rnd_F32_Asmi.h new file mode 100644 index 000000000..21e841eb3 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Rnd_F32_Asmi.h @@ -0,0 +1,88 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Rounding +* +*******************************************************************************/ +#ifndef _MLIB_RND_F32_ASM_H_ +#define _MLIB_RND_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_RndSat_F16l_Asmi(f32Val) MLIB_RndSat_F16l_FAsmi(f32Val) + +/***************************************************************************//*! +* +* Converts 32-bit number into 16-bit with rounding +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_RndSat_F16l_FAsmi(register frac32_t f32Val) +{ + register frac32_t f32RndVal = 0x8000; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ qadd f32Val, f32Val, f32RndVal /* f32Val = f32Val + 0x00008000 with saturation */ + asr f32Val, f32Val, #16 }; /* f32Val >> 16 */ + + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "qadd %0, %0, %1 \n" /* f32Val = f32Val + 0x00008000 with saturation */ + "asr %0, %0, #16 \n" /* f32Val >> 16 */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Val): "l"(f32RndVal)); + #endif + + return (frac16_t)f32Val; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_RND_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sat_A32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sat_A32_Asmi.h new file mode 100644 index 000000000..9745224a0 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sat_A32_Asmi.h @@ -0,0 +1,85 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Saturation +* +*******************************************************************************/ +#ifndef _MLIB_SAT_A32_ASM_H_ +#define _MLIB_SAT_A32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sat_F16a_Asmi(a32Accum) MLIB_Sat_F16a_FAsmi(a32Accum) + +/***************************************************************************//*! +* +* Takes the fractional part from number in accumulator format and saturate if the original number is greater than 1. +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Sat_F16a_FAsmi(register acc32_t a32Accum) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ ssat a32Accum, #16, a32Accum }; /* Saturation */ + + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "ssat %0, #16, %0 \n" /* Saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(a32Accum):); + #endif + + return (frac16_t)a32Accum; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SAT_A32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Shift_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Shift_F16.h new file mode 100644 index 000000000..76b510555 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Shift_F16.h @@ -0,0 +1,107 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Shift +* +*******************************************************************************/ +#ifndef _MLIB_SHIFT_F16_H_ +#define _MLIB_SHIFT_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sh1L_F16_Ci(f16Val) MLIB_Sh1L_F16_FCi(f16Val) +#define MLIB_Sh1R_F16_Ci(f16Val) MLIB_Sh1R_F16_FCi(f16Val) +#define MLIB_Sh1R_F16_Ci(f16Val) MLIB_Sh1R_F16_FCi(f16Val) +#define MLIB_ShL_F16_Ci(f16Val, u16Sh) MLIB_ShL_F16_FCi(f16Val, u16Sh) +#define MLIB_ShR_F16_Ci(f16Val, u16Sh) MLIB_ShR_F16_FCi(f16Val, u16Sh) + +/***************************************************************************//*! +* +* This function returns the f16Val input shifted by 1 to the left. +* The function does not saturate the output. +* +*******************************************************************************/ +static inline frac16_t MLIB_Sh1L_F16_FCi(register frac16_t f16Val) +{ + register uint32_t ui32temp = (uint32_t)f16Val << 1U; + return (frac16_t)ui32temp; +} + +/***************************************************************************//*! +* +* This function returns the f16Val input shifted by 1 to the right. +* +*******************************************************************************/ +static inline frac16_t MLIB_Sh1R_F16_FCi(register frac16_t f16Val) +{ + register uint32_t ui32temp = (uint32_t)f16Val >> 1U; + return (frac16_t)ui32temp; +} + +/***************************************************************************//*! +* +* This function returns the f16Val input shifted by the number of u16Sh to the left. +* The function does not saturate the output. +* +*******************************************************************************/ +static inline frac16_t MLIB_ShL_F16_FCi(register frac16_t f16Val, register uint16_t u16Sh) +{ + register uint32_t ui32temp = (uint32_t)f16Val << u16Sh; + return (frac16_t)ui32temp; +} + +/***************************************************************************//*! +* +* This function returns the f16Val input shifted by the number of u16Sh to the right. +* +*******************************************************************************/ +static inline frac16_t MLIB_ShR_F16_FCi(register frac16_t f16Val, register uint16_t u16Sh) +{ + register uint32_t ui32temp = (uint32_t)f16Val >> u16Sh; + return (frac16_t)ui32temp; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SHIFT_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Shift_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Shift_F16_Asmi.h new file mode 100644 index 000000000..9b52588e8 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Shift_F16_Asmi.h @@ -0,0 +1,120 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Shift +* +*******************************************************************************/ +#ifndef _MLIB_SHIFT_F16_ASM_H_ +#define _MLIB_SHIFT_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sh1LSat_F16_Asmi(f16Val) MLIB_Sh1LSat_F16_FAsmi(f16Val) +#define MLIB_ShLSat_F16_Asmi(f16Val, u16Sh) MLIB_ShLSat_F16_FAsmi(f16Val, u16Sh) + +/***************************************************************************//*! +* +* This function returns the f16Val input shifted by 1 to the left. +* The function saturates the output. +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Sh1LSat_F16_FAsmi(register frac16_t f16Val) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ qadd16 f16Val, f16Val, f16Val }; /* Addition with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "qadd16 %0, %0, %0 \n" /* Addition with saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Val):); + #endif + + return f16Val; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* This function returns the f16Val input shifted by the number of u16Sh to the left. +* The function saturates the output. +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_ShLSat_F16_FAsmi(register frac16_t f16Val, register uint16_t u16Sh) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Val, f16Val /* Transforms 16-bit input f16Val to 32-bit */ + usat u16Sh, #4, u16Sh /* Saturates to 4-bit value */ + lsl f16Val, f16Val, u16Sh /* f16Val << u16Sh */ + ssat f16Val, #16, f16Val }; /* Saturates to 16-bit value */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "usat %1, #4, %1 \n" /* Saturates to 4-bit value */ + "lsl %0, %0, %1 \n" /* f16Val << u16Sh */ + "ssat %0, #16, %0 \n" /* Saturates to 16-bit value */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Val), "+l"(u16Sh):); + #endif + + return f16Val; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SHIFT_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Shift_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Shift_F32.h new file mode 100644 index 000000000..258b4789d --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Shift_F32.h @@ -0,0 +1,106 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Shift +* +*******************************************************************************/ +#ifndef _MLIB_SHIFT_F32_H_ +#define _MLIB_SHIFT_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sh1L_F32_Ci(f32Val) MLIB_Sh1L_F32_FCi(f32Val) +#define MLIB_Sh1R_F32_Ci(f32Val) MLIB_Sh1R_F32_FCi(f32Val) +#define MLIB_ShL_F32_Ci(f32Val, u16Sh) MLIB_ShL_F32_FCi(f32Val, u16Sh) +#define MLIB_ShR_F32_Ci(f32Val, u16Sh) MLIB_ShR_F32_FCi(f32Val, u16Sh) + +/***************************************************************************//*! +* +* This function returns the f32Val input shifted by 1 to the left. +* The function does not saturate the output. +* +*******************************************************************************/ +static inline frac32_t MLIB_Sh1L_F32_FCi(register frac32_t f32Val) +{ + register uint64_t ui64temp = (uint64_t)f32Val << 1U; + return (frac32_t)ui64temp; +} + +/***************************************************************************//*! +* +* This function returns the f32Val input shifted by 1 to the right. +* +*******************************************************************************/ +static inline frac32_t MLIB_Sh1R_F32_FCi(register frac32_t f32Val) +{ + register uint64_t ui64temp = (uint64_t)f32Val >> 1U; + return (frac32_t)ui64temp; +} + +/***************************************************************************//*! +* +* This function returns the f32Val input shifted by the number of u16Sh to the left. +* The function does not saturate the output. +* +*******************************************************************************/ +static inline frac32_t MLIB_ShL_F32_FCi(register frac32_t f32Val, register uint16_t u16Sh) +{ + register uint64_t ui64temp = (uint64_t)f32Val << u16Sh; + return (frac32_t)ui64temp; +} + +/***************************************************************************//*! +* +* This function returns the f32Val input shifted by the number of u16Sh to the right. +* +*******************************************************************************/ +static inline frac32_t MLIB_ShR_F32_FCi(register frac32_t f32Val, register uint16_t u16Sh) +{ + register uint64_t ui64temp = (uint64_t)f32Val >> u16Sh; + return (frac32_t)ui64temp; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SHIFT_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Shift_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Shift_F32_Asmi.h new file mode 100644 index 000000000..3d9d9b9d1 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Shift_F32_Asmi.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Shift +* +*******************************************************************************/ +#ifndef _MLIB_SHIFT_F32_ASM_H_ +#define _MLIB_SHIFT_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sh1LSat_F32_Asmi(f32Val) MLIB_Sh1LSat_F32_FAsmi(f32Val) +#define MLIB_ShLSat_F32_Asmi(f32Val, u16Sh) MLIB_ShLSat_F32_FAsmi(f32Val, u16Sh) + +/***************************************************************************//*! +* +* This function returns the f32Val input shifted by 1 to the left. +* The function saturates the output. +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Sh1LSat_F32_FAsmi(register frac32_t f32Val) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ qadd f32Val, f32Val, f32Val }; /* Addition with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "qadd %0, %0, %0 \n" /* Addition with saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Val):); + #endif + + return f32Val; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* +* This function returns the f32Val input shifted by the number of u16Sh to the left. +* The function saturates the output. +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_ShLSat_F32_FAsmi(register frac32_t f32Val, register uint16_t u16Sh) +{ + register frac32_t f32Out=0; + register frac32_t f32SatVal = f32Val; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ ssat f32SatVal, #2, f32SatVal /* Saturates f32SatVal to 2-bit value */ + lsl f32SatVal, f32SatVal, #30 /* f32SatVal << 30 */ + qadd f32SatVal, f32SatVal, f32SatVal /* Addition with saturation */ + lsl f32Out, f32Val, u16Sh /* f32Out = f32Val << u16Sh */ + asr u16Sh, f32Out, u16Sh /* u16Sh = f32Out << u16Sh */ + cmp u16Sh, f32Val /* Compares u16Sh and f32Val */ + it ne /* If u16Sh != f32Val, then returns the saturate value */ + movne f32Out, f32SatVal }; + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "ssat %1, #2, %1 \n" /* Saturates f32SatVal to 2-bit value */ + "lsl %1, %1, #30 \n" /* f32SatVal << 30 */ + "qadd %1, %1, %1 \n" /* Addition with saturation */ + "lsl %0, %2, %3 \n" /* f32Out = f32Val << u16Sh */ + "asr %3, %0, %3 \n" /* u16Sh = f32Out << u16Sh */ + "cmp %3, %2 \n" /* Compares u16Sh and f32Val */ + "it ne \n" /* If u16Sh != f32Val, then returns the saturate value */ + "movne %0, %1 \n" + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "=&l"(f32Out), "+l"(f32SatVal), "+l"(f32Val), "+l"(u16Sh):); + #endif + + return f32Out; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SHIFT_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sign_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sign_F16_Asmi.h new file mode 100644 index 000000000..62dad4288 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sign_F16_Asmi.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Sign +* +*******************************************************************************/ +#ifndef _MLIB_SIGN_F16_ASM_H_ +#define _MLIB_SIGN_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sign_F16_Asmi(f16Val) MLIB_Sign_F16_FAsmi(f16Val) + +/***************************************************************************//*! +* This function returns the sign of the argument: +* f16Val = 0: returns 0 +* f16Val > 0: returns 32767 (fractional 1.0) +* f16Val < 0: returns -32768 (fractional -1.0) +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Sign_F16_FAsmi(register frac16_t f16Val) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ lsl f16Val, f16Val, #16 /* f16Val << 16 */ + ssat f16Val, #16, f16Val }; /* Saturates to 16-bit value */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "lsl %0, %0, #16 \n" /* f16Val << 16 */ + "ssat %0, #16, %0 \n" /* Saturates to 16-bit value */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Val):); + #endif + + return f16Val; +} +RTCESL_INLINE_OPTIM_RESTORE + + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SIGN_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sign_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sign_F32_Asmi.h new file mode 100644 index 000000000..50fe1b054 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sign_F32_Asmi.h @@ -0,0 +1,90 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Sign +* +*******************************************************************************/ +#ifndef _MLIB_SIGN_F32_ASM_H_ +#define _MLIB_SIGN_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sign_F32_Asmi(f32Val) MLIB_Sign_F32_FAsmi(f32Val) + +/***************************************************************************//*! +* This function returns the sign of the argument: +* f32Val = 0: returns 0 +* f32Val > 0: returns 2147483647 (fractional 1.0) +* f32Val < 0: returns -2147483648 (fractional -1.0) +* +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Sign_F32_FAsmi(register frac32_t f32Val) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ ssat f32Val, #2, f32Val /* Saturates input to 2-bit value */ + lsl f32Val, f32Val, #30 /* f16Val << 30 */ + qadd f32Val, f32Val, f32Val }; /* Addition with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "ssat %0, #2, %0 \n" /* Saturates input to 2-bit value */ + "lsl %0, %0, #30 \n" /* f16Val << 30 */ + "qadd %0, %0, %0 \n" /* Addition with saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Val):); + #endif + + return f32Val; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SIGN_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sign_FLT_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sign_FLT_Asmi.h new file mode 100644 index 000000000..ebdf78db0 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sign_FLT_Asmi.h @@ -0,0 +1,104 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Sign +* +*******************************************************************************/ +#ifndef _MLIB_SIGN_FLT_ASMI_H_ +#define _MLIB_SIGN_FLT_ASMI_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sign_FLT_Asmi(fltVal) MLIB_Sign_FLT_FAsmi(fltVal) + +/***************************************************************************//*! +* This function returns the sign of the argument: +* fltVal = 0: returns 0.0F +* fltVal > 0: returns 1.0F +* fltVal < 0: returns -1.0F +* +*******************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_suppress=Pe549 /* Suppresses the Pe549 warning for IAR compiler*/ +#endif +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline float_t MLIB_Sign_FLT_FAsmi(register float_t fltVal) +{ + register frac32_t f32Val1=0, f32Val2=0; + + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ vmov f32Val1, fltVal /* f32Val = fltVal */ + lsls f32Val2, f32Val1, #1 /* Clears the sign */ + itt ne /* If fltVal != 0, then executes next two commands */ + andne f32Val1, f32Val1, #0x80000000 /* f32Val = f32Val & 0x80000000 */ + orrne f32Val1, f32Val1, #0x3F800000 /* f32Val = f32Val | 0x3F800000 */ + vmov fltVal, f32Val1 }; /* fltVal = f32Val */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "vmov %1, %0 \n" /* f32Val = fltVal */ + "lsls %2, %1, #1 \n" /* Clears the sign */ + "itt ne \n" /* If fltVal != 0, then executes next two commands */ + "andne %1, %1, #0x80000000 \n" /* f32Val = f32Val & 0x80000000 */ + "orrne %1, %1, #0x3F800000 \n" /* f32Val = f32Val | 0x3F800000 */ + "vmov %0, %1 \n" /* fltVal = f32Val */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+t"(fltVal), "+l"(f32Val1), "+l"(f32Val2):); + #endif + return (fltVal); +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_default=Pe549 +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SIGN_FLT_ASMI_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub4_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub4_F16_Asmi.h new file mode 100644 index 000000000..e2fcd2484 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub4_F16_Asmi.h @@ -0,0 +1,131 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Subtraction of three input values from the first input +* +*******************************************************************************/ +#ifndef _MLIB_SUB4_F16_ASM_H_ +#define _MLIB_SUB4_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sub4_F16_Asmi(f16Min, f16Sub1, f16Sub2, f16Sub3) \ + MLIB_Sub4_F16_FAsmi(f16Min, f16Sub1, f16Sub2, f16Sub3) +#define MLIB_Sub4Sat_F16_Asmi(f16Min, f16Sub1, f16Sub2, f16Sub3) \ + MLIB_Sub4Sat_F16_FAsmi(f16Min, f16Sub1, f16Sub2, f16Sub3) + +/***************************************************************************//*! +* Subtraction of three input values from the first input +* f16Out = f16Min - f16Sub1 - f16Sub2 - f16Sub3 +* function is not saturated +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Sub4_F16_FAsmi(register frac16_t f16Min, register frac16_t f16Sub1, + register frac16_t f16Sub2, register frac16_t f16Sub3) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{sub f16Min, f16Min, f16Sub1 /* f16Min = f16Min - f16Sub1 */ + sub f16Min, f16Min, f16Sub2 /* f16Min = f16Min - f16Sub2 */ + sub f16Min, f16Min, f16Sub3}; /* f16Min = f16Min - f16Sub3 */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sub %0, %0, %1 \n" /* f16Min = f16Min - f16Sub1 */ + "sub %0, %0, %2 \n" /* f16Min = f16Min - f16Sub2 */ + "sub %0, %0, %3 \n" /* f16Min = f16Min - f16Sub3 */ + : "+l"(f16Min): "l"(f16Sub1), "l"(f16Sub2), "l"(f16Sub3)); + #endif + + return f16Min; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* Subtraction of three input values from the first input +* f16Out = f16Min - f16Sub1 - f16Sub2 - f16Sub3 +* function is saturated +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_Sub4Sat_F16_FAsmi(register frac16_t f16Min, register frac16_t f16Sub1, + register frac16_t f16Sub2, register frac16_t f16Sub3) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ sxth f16Min, f16Min /* Transforms 16-bit input f16Val to 32-bit */ + sxth f16Sub1, f16Sub1 /* Transforms 16-bit input f16Val to 32-bit */ + sxth f16Sub2, f16Sub2 /* Transforms 16-bit input f16Val to 32-bit */ + sxth f16Sub3, f16Sub3 /* Transforms 16-bit input f16Val to 32-bit */ + sub f16Min, f16Min, f16Sub2 /* f16Min - f16Sub2 */ + add f16Sub1, f16Sub1, f16Sub3 /* f16Sub1 + f16Sub3 */ + sub f16Min, f16Min, f16Sub1 /* f16Min - f16Sub2 - f16Sub1 - f16Sub3 */ + ssat f16Min, #16, f16Min }; /* Saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sxth %0, %0 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "sxth %1, %1 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "sxth %2, %2 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "sxth %3, %3 \n" /* Transforms 16-bit input f16Val to 32-bit */ + "sub %0, %0, %2 \n" /* f16Min - f16Sub2 */ + "add %1, %1, %3 \n" /* f16Sub1 + f16Sub3 */ + "sub %0, %0, %1 \n" /* f16Min - f16Sub2 - f16Sub1 - f16Sub3 */ + "ssat %0, #16, %0 \n" /* Saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Min), "+l"(f16Sub1), "+l"(f16Sub2), "+l"(f16Sub3):); + #endif + + return f16Min; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif /* _MLIB_SUB4_F16_ASM_H_ */ + +#endif diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub4_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub4_F32_Asmi.h new file mode 100644 index 000000000..4450b8d13 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub4_F32_Asmi.h @@ -0,0 +1,174 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Subtraction of three input values from the first input +* +*******************************************************************************/ +#ifndef _MLIB_SUB4_F32_ASM_H_ +#define _MLIB_SUB4_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sub4_F32_Asmi(f32Min, f32Sub1, f32Sub2, f32Sub3) \ + MLIB_Sub4_F32_FAsmi(f32Min, f32Sub1, f32Sub2, f32Sub3) +#define MLIB_Sub4Sat_F32_Asmi(f32Min, f32Sub1, f32Sub2, f32Sub3) \ + MLIB_Sub4Sat_F32_FAsmi(f32Min, f32Sub1, f32Sub2, f32Sub3) + +/***************************************************************************//*! +* Subtraction of three input values from the first input +* f32Out = f32Min + f32Sub1 + f32Sub2 + f32Sub3 +* function is not saturated +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Sub4_F32_FAsmi(register frac32_t f32Min, register frac32_t f32Sub1, + register frac32_t f32Sub2, register frac32_t f32Sub3) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{sub f32Min, f32Min, f32Sub1 /* f32Min = f32Min - f32Sub1 */ + sub f32Min, f32Min, f32Sub2 /* f32Min = f32Min - f32Sub2 */ + sub f32Min, f32Min, f32Sub3}; /* f32Min = f32Min - f32Sub3 */ + + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "sub %0, %0, %1 \n" /* f32Min = f32Min - f32Sub1 */ + "sub %0, %0, %2 \n" /* f32Min = f32Min - f32Sub2 */ + "sub %0, %0, %3 \n" /* f32Min = f32Min - f32Sub3 */ + + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Min): "l"(f32Sub1), "l"(f32Sub2), "l"(f32Sub3)); + #endif + + return f32Min; +} +RTCESL_INLINE_OPTIM_RESTORE + +/***************************************************************************//*! +* Subtraction of three input values from the first input +* f32Out = f32Min + f32Sub1 + f32Sub2 + f32Sub3 +* function is saturated +*******************************************************************************/ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_suppress=Pe549 /* Suppresses the Pe549 warning for IAR compiler*/ +#endif +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_Sub4Sat_F32_FAsmi(register frac32_t f32Min, register frac32_t f32Sub1, + register frac32_t f32Sub2, register frac32_t f32Sub3) +{ + register frac32_t f32Sign1=0, f32Sign2=0; + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ asr f32Sign1, f32Min, #31 /* f32Sign1 = sign of f32Min */ + asr f32Sign2, f32Sub1, #31 /* f32Sign2 = sign of f32Sub1 */ + subs f32Min, f32Min, f32Sub1 /* f32Min - f32Sub1 */ + sbc f32Sign1, f32Sign1, f32Sign2 /* f32Sign1 - f32Sign2 - Carry */ + + asr f32Sign2, f32Sub2, #31 /* f32Sign2 = sign of f32Sub2 */ + subs f32Min, f32Min, f32Sub2 /* f32Min - f32Sub1 - f32Sub2 */ + sbc f32Sign1, f32Sign1, f32Sign2 /* f32Sign1 - f32Sign2 - Carry */ + + asr f32Sign2, f32Sub3, #31 /* f32Sign2 = sign of f32Sub3 */ + subs f32Min, f32Min, f32Sub3 /* f32Min - f32Sub1 - f32Sub2 - f32Sub3 */ + sbc f32Sign1, f32Sign1, f32Sign2 /* f32Sign1 - f32Sign2 - Carry */ + + mov f32Sign2, #0x80000000 /* f32Sign2 = 0x80000000 */ + + lsr f32Sub1, f32Min, #31 /* First bit of low part of result */ + adds f32Sign1, f32Sign1, f32Sub1 + + it gt /* If f32Sign1 > 0, then executes next command */ + subgt f32Min, f32Sign2, #1 /* Result = 0x7FFFFFFF*/ + + it lt /* If f32Sign1 > 0, then executes next command */ + movlt f32Min, f32Sign2 }; /* Result = 0x80000000*/ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "asr %0, %2, #31 \n" /* f32Sign1 = sign of f32Min */ + "asr %1, %3, #31 \n" /* f32Sign2 = sign of f32Sub1 */ + "subs %2, %2, %3 \n" /* f32Min - f32Sub1 */ + "sbc %0, %0, %1 \n" /* f32Sign1 - f32Sign2 - Carry */ + + "asr %1, %4, #31 \n" /* f32Sign2 = sign of f32Sub2 */ + "subs %2, %2, %4 \n" /* f32Min - f32Sub1 - f32Sub2 */ + "sbc %0, %0, %1 \n" /* f32Sign1 - f32Sign2 - Carry */ + + "asr %1, %5, #31 \n" /* f32Sign2 = sign of f32Sub3 */ + "subs %2, %2, %5 \n" /* f32Min - f32Sub1 - f32Sub2 - f32Sub3 */ + "sbc %0, %0, %1 \n" /* f32Sign1 - f32Sign2 - Carry */ + + "mov %1, #0x80000000 \n" /* f32Sign2 = 0x80000000 */ + + "lsr %3, %2, #31 \n" /* First bit of low part of result */ + "adds %0, %0, %3 \n" + + "it gt \n" /* If f32Sign1 > 0, then executes next command */ + "subgt %2, %1, #1 \n" /* Result = 0x7FFFFFFF*/ + + "it lt \n" /* If f32Sign1 > 0, then executes next command */ + "movlt %2, %1 \n" /* Result = 0x80000000*/ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Sign1), "+l"(f32Sign2), "+l"(f32Min), "+l"(f32Sub1): "l"(f32Sub2), "l"(f32Sub3) ); + #endif + + return f32Min; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ +#pragma diag_default=Pe549 +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SUB4_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub4_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub4_FLT.h new file mode 100644 index 000000000..29d468225 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub4_FLT.h @@ -0,0 +1,73 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Subtraction of three input values from the first input +* +*******************************************************************************/ +#ifndef _MLIB_SUB4_FLT_H_ +#define _MLIB_SUB4_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sub4_FLT_Ci(fltMin, fltSub1, fltSub2, fltSub3) \ + MLIB_Sub4_FLT_FCi(fltMin, fltSub1, fltSub2, fltSub3) + +/***************************************************************************//*! +* Subtraction of three input values from the first input +* fltOut = fltMin - fltSub1 - fltSub2 - fltSub3 +* The output saturation is not implemented, thus in case +* the subtraction of input value is outside the (-2^128, 2^128) +* interval, the output value will overflow without any detection. +*******************************************************************************/ +static inline float_t MLIB_Sub4_FLT_FCi(register float_t fltMin, + register float_t fltSub1, + register float_t fltSub2, + register float_t fltSub3) +{ + return((float_t)(fltMin - fltSub1 - fltSub2 - fltSub3)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SUB4_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_A32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_A32.h new file mode 100644 index 000000000..fdcb8b330 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_A32.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Subtraction +* +*******************************************************************************/ +#ifndef _MLIB_SUB_A32_H_ +#define _MLIB_SUB_A32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sub_A32ss_Ci(f16Min, f16Sub) MLIB_Sub_A32ss_FCi(f16Min, f16Sub) +#define MLIB_Sub_A32as_Ci(a32Accum, f16Sub) MLIB_Sub_A32as_FCi(a32Accum, f16Sub) + +/***************************************************************************//*! +* +* a32Out = f16Min - f16Sub +* +*******************************************************************************/ +static inline acc32_t MLIB_Sub_A32ss_FCi(register frac16_t f16Min, register frac16_t f16Sub) +{ + return((acc32_t)((acc32_t)f16Min - (acc32_t)f16Sub)); +} + +/***************************************************************************//*! +* +* a32Out = a32Accum - f16Sub +* +*******************************************************************************/ +static inline acc32_t MLIB_Sub_A32as_FCi(register acc32_t a32Accum, register frac16_t f16Sub) +{ + return ((acc32_t)((acc32_t)a32Accum -(acc32_t)f16Sub)); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SUB_A32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F16.h new file mode 100644 index 000000000..0fd690263 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F16.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Subtraction +* +*******************************************************************************/ +#ifndef _MLIB_SUB_F16_H_ +#define _MLIB_SUB_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sub_F16_Ci(f16Min, f16Sub) MLIB_Sub_F16_FCi(f16Min, f16Sub) + +/***************************************************************************//*! +* +* f16Out = f16Min - f16Sub +* Without saturation +*******************************************************************************/ +static inline frac16_t MLIB_Sub_F16_FCi(register frac16_t f16Min, register frac16_t f16Sub) +{ + return(f16Min - f16Sub); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SUB_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F16_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F16_Asmi.h new file mode 100644 index 000000000..72a5cda07 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F16_Asmi.h @@ -0,0 +1,84 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Subtraction +* +*******************************************************************************/ +#ifndef _MLIB_SUB_F16_ASM_H_ +#define _MLIB_SUB_F16_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_SubSat_F16_Asmi(f16Min, f16Sub) MLIB_SubSat_F16_FAsmi(f16Min, f16Sub) + +/***************************************************************************//*! +* +* f16Out = f16Min - f16Sub +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac16_t MLIB_SubSat_F16_FAsmi(register frac16_t f16Min, register frac16_t f16Sub) +{ + #if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ qsub16 f16Min, f16Min, f16Sub}; /* Subtracts with saturation */ + #else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "qsub16 %0, %0, %1 \n" /* Subtracts with saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f16Min): "l"(f16Sub)); + #endif + + return f16Min; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SUB_F16_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F32.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F32.h new file mode 100644 index 000000000..30fc6706c --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F32.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Subtraction +* +*******************************************************************************/ +#ifndef _MLIB_SUB_F32_H_ +#define _MLIB_SUB_F32_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sub_F32_Ci(f32Min, f32Sub) MLIB_Sub_F32_FCi(f32Min, f32Sub) + +/***************************************************************************//*! +* +* f32Out = f32Min - f32Sub +* Without saturation +*******************************************************************************/ +static inline frac32_t MLIB_Sub_F32_FCi(register frac32_t f32Min, register frac32_t f32Sub) +{ + return(f32Min - f32Sub); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SUB_F32_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F32_Asmi.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F32_Asmi.h new file mode 100644 index 000000000..241d16b50 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F32_Asmi.h @@ -0,0 +1,84 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Subtraction +* +*******************************************************************************/ +#ifndef _MLIB_SUB_F32_ASM_H_ +#define _MLIB_SUB_F32_ASM_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_SubSat_F32_Asmi(f32Min, f32Sub) MLIB_SubSat_F32_FAsmi(f32Min, f32Sub) + +/***************************************************************************//*! +* +* f32Out = f32Min - f32Sub +* With saturation +*******************************************************************************/ +RTCESL_INLINE_OPTIM_SAVE +RTCESL_INLINE_OPTIM_SET +static inline frac32_t MLIB_SubSat_F32_FAsmi(register frac32_t f32Min, register frac32_t f32Sub) +{ +#if defined(__CC_ARM) /* For ARM Compiler */ + __asm volatile{ qsub f32Min, f32Min, f32Sub}; /* Subtracts with saturation */ +#else + __asm volatile( + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax unified \n" /* Using unified asm syntax */ + #endif + "qsub %0, %0, %1 \n" /* Subtracts with saturation */ + #if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* For GCC compiler */ + ".syntax divided \n" + #endif + : "+l"(f32Min): "l"(f32Sub)); +#endif + + return f32Min; +} +RTCESL_INLINE_OPTIM_RESTORE + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SUB_F32_ASM_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F64.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F64.h new file mode 100644 index 000000000..e2021c101 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_F64.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Subtraction +* +*******************************************************************************/ +#ifndef _MLIB_SUB_F64_H_ +#define _MLIB_SUB_F64_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sub_F64_Ci(f64Min, f64Sub) MLIB_Sub_F64_FCi(f64Min, f64Sub) +#define MLIB_SubSat_F64_Ci(f64Min, f64Sub) MLIB_SubSat_F64_FCi(f64Min, f64Sub) + +/***************************************************************************//*! +* +* f64Out = f64Min - f64Sub +* Without saturation +*******************************************************************************/ +static inline frac64_t MLIB_Sub_F64_FCi(register frac64_t f64Min, register frac64_t f64Sub) +{ + return(f64Min - f64Sub); +} + +/***************************************************************************//*! +* +* f64Out = f64Min - f64Sub +* With saturation +*******************************************************************************/ +static inline frac64_t MLIB_SubSat_F64_FCi(register frac64_t f64Min, register frac64_t f64Sub) +{ + register int64_t i64Temp; + register uint64_t u64satmin, u64satmax; + + i64Temp = MLIB_Sub_F64_FCi(f64Min, f64Sub); + u64satmax = (~(uint64_t)f64Min) & (uint64_t)f64Sub; + u64satmax = u64satmax & (uint64_t)i64Temp; + u64satmin = (uint64_t)f64Min & (~(uint64_t)f64Sub); + u64satmin = u64satmin & (~(uint64_t)i64Temp); + + i64Temp = ((int64_t)u64satmin < 0) ? (int64_t)0x8000000000000000U : i64Temp; + i64Temp = ((int64_t)u64satmax < 0) ? (int64_t)0x7FFFFFFFFFFFFFFF : i64Temp; + return(i64Temp); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SUB_F64_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_FLT.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_FLT.h new file mode 100644 index 000000000..7d910513f --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/MLIB_Sub_FLT.h @@ -0,0 +1,69 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Subtraction +* +*******************************************************************************/ +#ifndef _MLIB_SUB_FLT_H_ +#define _MLIB_SUB_FLT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Sub_FLT_Ci(fltMin, fltSub) MLIB_Sub_FLT_FCi(fltMin, fltSub) + +/***************************************************************************//*! +* +* fltOut = fltMin - fltSub +* The output saturation is not implemented, thus in case +* the subtraction of input value is outside the (-2^128, 2^128) +* interval, the output value will overflow without any detection. +*******************************************************************************/ +static inline float_t MLIB_Sub_FLT_FCi(register float_t fltMin, register float_t fltSub) +{ + return(fltMin - fltSub); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_SUB_FLT_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/RTCESL_cfg.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/RTCESL_cfg.h new file mode 100644 index 000000000..5ae2fb86c --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/RTCESL_cfg.h @@ -0,0 +1,80 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief RTCESL configuration file +* +*******************************************************************************/ +#ifndef _RTCESL_CFG_H_ +#define _RTCESL_CFG_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* RTCESL vesion +*******************************************************************************/ +/* RTCESL version is 4.6.2 */ +#define RTCESL_VERSION 4.6.2 + + +/******************************************************************************* +* User Modified Macros +*******************************************************************************/ +/* Inline assembler function optimization setting */ +/* Only for functions written as inline assembler. The setting can be changed, but the RTCESL was tested + with following original setting. In case of any change the functionality is not guaranteed. + This is a solution for each compiler which have the issue of passing function parameter on to the function + when maximum speed optimization is used. Therefore optimization level is decreased and no save/restore + pragma is used for inline assembler functions. */ + +#if defined(__IAR_SYSTEMS_ICC__) /* For IAR compiler */ + #define RTCESL_INLINE_OPTIM_SAVE /* Save original level - no value */ + #define RTCESL_INLINE_OPTIM_SET _Pragma("optimize=none") /* Set low level */ + #define RTCESL_INLINE_OPTIM_RESTORE /* Restore original level - no value*/ +#elif defined(__CC_ARM) /* For ARM(KEIL) compiler */ + #define RTCESL_INLINE_OPTIM_SAVE /* Save original level - no value */ + #define RTCESL_INLINE_OPTIM_SET _Pragma("O0") /* Set low level */ + #define RTCESL_INLINE_OPTIM_RESTORE /* Restore original level - no value*/ +#elif defined(__GNUC__) && (__ARMCC_VERSION) /* For ARM(KEIL) version >= 6 compiler */ + #define RTCESL_INLINE_OPTIM_SAVE /* Save original level - no value */ + #define RTCESL_INLINE_OPTIM_SET /* Set low level */ + #define RTCESL_INLINE_OPTIM_RESTORE /* Restore original level - no value*/ +#elif defined(__GNUC__) /* For GCC compiler */ + #define RTCESL_INLINE_OPTIM_SAVE /* Save original level - no value */ + #define RTCESL_INLINE_OPTIM_SET __attribute__((optimize("O0"))) /* Set low level */ + #define RTCESL_INLINE_OPTIM_RESTORE /* Restore original level - no value*/ +#else /* Other compiler used */ + #warning "Unsupported compiler/IDE used !" +#endif + +#endif /*_RTCESL_CFG_H_*/ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/asm_mac.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/asm_mac.h new file mode 100644 index 000000000..26b783a64 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/asm_mac.h @@ -0,0 +1,103 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief asm_mac.h +* +*******************************************************************************/ + +#ifndef ASM_MAC_H_ +#define ASM_MAC_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Macros +*******************************************************************************/ + +#if defined(__IAR_SYSTEMS_ASM__) /* IAR compiler */ + #define ASM_PREFIX(x) x + #define ASM_LABEL(label) label + #define ASM_EXTERN(label) EXTERN label + #define ASM_ALIGN(value) ALIGNROM value + #define ASM_PUBLIC(label) PUBLIC label + #define ASM_CONST16(value) DC16 value + #define ASM_CONST32(value) DC32 value + #define ASM_LABEL_CONST32(label,value) ASM_LABEL(label) ASM_CONST32(value) + #define ASM_DATA_SECTION(label) SECTION label : DATA (4) + #define ASM_CODE_SECTION(label) SECTION label : CODE (4) + #define ASM_END END + #define ASM_EQUATE(label, value) label EQU value + #define ASM_COMP_SPECIFIC_DIRECTIVES + #define ASM_CODE CODE + #define ASM_DATA DATA +#elif defined(__GNUC__) /* GCC compiler */ + #define ASM_PREFIX(x) x + #define ASM_LABEL(label) label: + #define ASM_EXTERN(label) .extern ASM_PREFIX(label) + #define ASM_ALIGN(value) .balign value + #define ASM_PUBLIC(label) .type ASM_PREFIX(label), %function; \ + .global ASM_PREFIX(label); + #define ASM_CONST16(value) .short value + #define ASM_CONST32(value) .long value + #define ASM_LABEL_CONST32(label,value) ASM_LABEL(label) ASM_CONST32(value) + #define ASM_DATA_SECTION(name) .section name + #define ASM_CODE_SECTION(name) .section name + #define ASM_END .end + #define ASM_EQUATE(label,value) .equ label, value + #define ASM_COMP_SPECIFIC_DIRECTIVES .syntax unified + #define ASM_CODE .thumb + #define ASM_DATA +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) /* ARM compiler */ + #define ASM_PREFIX(x) x + #define ASM_LABEL(label) label + #define ASM_EXTERN(label) EXTERN label + #define ASM_ALIGN(value) ALIGN value + #define ASM_PUBLIC(label) EXPORT label + #define ASM_CONST16(value) DCWU value + #define ASM_CONST32(value) DCDU value + #define ASM_LABEL_CONST32(label,value) ASM_LABEL(label) ASM_CONST32(value) + #define ASM_DATA_SECTION(label) AREA |label|, DATA + #define ASM_CODE_SECTION(label) AREA |label|, CODE + #define ASM_END END + #define ASM_EQUATE(label, value) label EQU value + #define ASM_COMP_SPECIFIC_DIRECTIVES + #define ASM_CODE THUMB + #define ASM_DATA +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* ASM_MAC_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/mlib.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/mlib.h new file mode 100644 index 000000000..7cf4c8f27 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/mlib.h @@ -0,0 +1,327 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Main MLIB header file for devices without FPU. +* +*******************************************************************************/ +#ifndef _MLIB_H_ +#define _MLIB_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/****************************************************************************** +* Includes +******************************************************************************/ +#include "mlib_types.h" +#include "MLIB_Abs_F16.h" +#include "MLIB_Abs_F16_Asmi.h" +#include "MLIB_Abs_F32.h" +#include "MLIB_Abs_F32_Asmi.h" +#include "MLIB_Add4_F16_Asmi.h" +#include "MLIB_Add4_F32_Asmi.h" +#include "MLIB_Add_F16.h" +#include "MLIB_Add_F16_Asmi.h" +#include "MLIB_Add_F32.h" +#include "MLIB_Add_F32_Asmi.h" +#include "MLIB_Add_A32.h" +#include "MLIB_Clb_F16.h" +#include "MLIB_Clb_F32.h" +#include "MLIB_Conv_F32.h" +#include "MLIB_Div1Q_F16.h" +#include "MLIB_Div1Q_F32.h" +#include "MLIB_Div1Q_A32.h" +#include "MLIB_Div_F16.h" +#include "MLIB_Div_F32.h" +#include "MLIB_Div_A32.h" +#include "MLIB_Log2_U16.h" +#include "MLIB_Mac4Rnd_F16_Asmi.h" +#include "MLIB_Mac4Rnd_F32.h" +#include "MLIB_Mac4Rnd_F32_Asmi.h" +#include "MLIB_Mac4_F32.h" +#include "MLIB_Mac4_F32_Asmi.h" +#include "MLIB_MacRnd_F16_Asmi.h" +#include "MLIB_MacRnd_F32.h" +#include "MLIB_MacRnd_F32_Asmi.h" +#include "MLIB_MacRnd_A32.h" +#include "MLIB_Mac_F16_Asmi.h" +#include "MLIB_Mac_F32_Asmi.h" +#include "MLIB_Mac_A32.h" +#include "MLIB_Mnac_F32.h" +#include "MLIB_Mnac_A32.h" +#include "MLIB_Mnac_F16_Asmi.h" +#include "MLIB_MnacRnd_F16_Asmi.h" +#include "MLIB_MnacRnd_F32.h" +#include "MLIB_MnacRnd_F32_Asmi.h" +#include "MLIB_Mnac_F32_Asmi.h" +#include "MLIB_MnacRnd_A32.h" +#include "MLIB_Mnac_F32.h" +#include "MLIB_Msu4Rnd_F16.h" +#include "MLIB_Msu4Rnd_F16_Asmi.h" +#include "MLIB_Msu4Rnd_F32.h" +#include "MLIB_Msu4Rnd_F32_Asmi.h" +#include "MLIB_Msu4_F32.h" +#include "MLIB_Msu4_F32_Asmi.h" +#include "MLIB_MsuRnd_F16_Asmi.h" +#include "MLIB_MsuRnd_F32.h" +#include "MLIB_MsuRnd_F32_Asmi.h" +#include "MLIB_MsuRnd_A32.h" +#include "MLIB_Msu_F16_Asmi.h" +#include "MLIB_Msu_F32_Asmi.h" +#include "MLIB_Msu_A32.h" +#include "MLIB_MulRnd_F16.h" +#include "MLIB_MulRnd_F16_Asmi.h" +#include "MLIB_MulRnd_F32.h" +#include "MLIB_MulRnd_F32_Asmi.h" +#include "MLIB_MulRnd_A32.h" +#include "MLIB_MulRnd_A32_Asmi.h" +#include "MLIB_Mul_F16.h" +#include "MLIB_Mul_F16_Asmi.h" +#include "MLIB_Mul_F32.h" +#include "MLIB_Mul_F32_Asmi.h" +#include "MLIB_Mul_A32.h" +#include "MLIB_Mul_A32_Asmi.h" +#include "MLIB_Neg_F16.h" +#include "MLIB_Neg_F16_Asmi.h" +#include "MLIB_Neg_F32.h" +#include "MLIB_Neg_F32_Asmi.h" +#include "MLIB_Rcp1Q_A32.h" +#include "MLIB_Rcp_A32.h" +#include "MLIB_Rnd_F32.h" +#include "MLIB_Rnd_F32_Asmi.h" +#include "MLIB_Sat_A32_Asmi.h" +#include "MLIB_Shift_F16.h" +#include "MLIB_Shift_F16_Asmi.h" +#include "MLIB_Shift_F32.h" +#include "MLIB_Shift_F32_Asmi.h" +#include "MLIB_BiShift_F16.h" +#include "MLIB_BiShift_F32.h" +#include "MLIB_Sign_F16_Asmi.h" +#include "MLIB_Sign_F32_Asmi.h" +#include "MLIB_Sub4_F16_Asmi.h" +#include "MLIB_Sub4_F32_Asmi.h" +#include "MLIB_Sub_F16.h" +#include "MLIB_Sub_F16_Asmi.h" +#include "MLIB_Sub_F32.h" +#include "MLIB_Sub_F32_Asmi.h" +#include "MLIB_Sub_A32.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_AbsSat_F16(f16Val) MLIB_AbsSat_F16_Asmi(f16Val) +#define MLIB_AbsSat_F32(f32Val) MLIB_AbsSat_F32_Asmi(f32Val) +#define MLIB_Abs_F16(f16Val) MLIB_Abs_F16_Ci(f16Val) +#define MLIB_Abs_F32(f32Val) MLIB_Abs_F32_Ci(f32Val) +#define MLIB_Add4Sat_F16(f16Add1, f16Add2, f16Add3, f16Add4) MLIB_Add4Sat_F16_Asmi(f16Add1, f16Add2, f16Add3, f16Add4) +#define MLIB_Add4Sat_F32(f32Add1, f32Add2, f32Add3, f32Add4) MLIB_Add4Sat_F32_Asmi(f32Add1, f32Add2, f32Add3, f32Add4) +#define MLIB_Add4_F16(f16Add1, f16Add2, f16Add3, f16Add4) MLIB_Add4_F16_Asmi(f16Add1, f16Add2, f16Add3, f16Add4) +#define MLIB_Add4_F32(f32Add1, f32Add2, f32Add3, f32Add4) MLIB_Add4_F32_Asmi(f32Add1, f32Add2, f32Add3, f32Add4) +#define MLIB_AddSat_F16(f16Add1, f16Add2) MLIB_AddSat_F16_Asmi(f16Add1, f16Add2) +#define MLIB_AddSat_F32(f32Add1, f32Add2) MLIB_AddSat_F32_Asmi(f32Add1, f32Add2) +#define MLIB_Add_A32as(a32Accum, f16Add) MLIB_Add_A32as_Ci(a32Accum, f16Add) +#define MLIB_Add_A32ss(f16Add1, f16Add2) MLIB_Add_A32ss_Ci(f16Add1, f16Add2) +#define MLIB_Add_F16(f16Add1, f16Add2) MLIB_Add_F16_Ci(f16Add1, f16Add2) +#define MLIB_Add_F32(f32Add1, f32Add2) MLIB_Add_F32_Ci(f32Add1, f32Add2) +#define MLIB_Clb_U16l(f32Val) MLIB_Clb_U16l_Ci(f32Val) +#define MLIB_Clb_U16s(f16Val) MLIB_Clb_U16s_Ci(f16Val) +#define MLIB_Conv_F16l(f32Val) MLIB_Conv_F16l_Ci(f32Val) +#define MLIB_Conv_F32s(f16Val) MLIB_Conv_F32s_Ci(f16Val) +#define MLIB_Div1QSat_F16(f16Num, f16Denom) MLIB_Div1QSat_F16_Ci(f16Num, f16Denom) +#define MLIB_Div1QSat_F16ll(f32Num, f32Denom) MLIB_Div1QSat_F16ll_Asm(f32Num, f32Denom) +#define MLIB_Div1QSat_F16ls(f32Num, f16Denom) MLIB_Div1QSat_F16ls_Ci(f32Num, f16Denom) +#define MLIB_Div1QSat_F32(f32Num, f32Denom) MLIB_Div1QSat_F32_Asm(f32Num, f32Denom) +#define MLIB_Div1QSat_F32ls(f32Num, f16Denom) MLIB_Div1QSat_F32ls_C(f32Num, f16Denom) +#define MLIB_Div1QSat_A32as(a32Num, f16Denom) MLIB_Div1QSat_F32ls_C(a32Num, f16Denom) +#define MLIB_Div1Q_A32ll(f32Num, f32Denom) MLIB_Div1Q_A32ll_Asm(f32Num, f32Denom) +#define MLIB_Div1Q_A32ls(f32Num, f16Denom) MLIB_Div1Q_A32ls_Ci(f32Num, f16Denom) +#define MLIB_Div1Q_A32ss(f16Num, f16Denom) MLIB_Div1Q_A32ss_Ci(f16Num, f16Denom) +#define MLIB_Div1Q_F16(f16Num, f16Denom) MLIB_Div1Q_F16_Ci(f16Num, f16Denom) +#define MLIB_Div1Q_F16ll(f32Num, f32Denom) MLIB_Div1Q_F16ll_Asm(f32Num, f32Denom) +#define MLIB_Div1Q_F16ls(f32Num, f16Denom) MLIB_Div1Q_F16ls_Ci(f32Num, f16Denom) +#define MLIB_Div1Q_F32(f32Num, f32Denom) MLIB_Div1Q_F32_Asm(f32Num, f32Denom) +#define MLIB_Div1Q_F32ls(f32Num, f16Denom) MLIB_Div1Q_F32ls_C(f32Num, f16Denom) +#define MLIB_Div1Q_A32as(a32Num, f16Denom) MLIB_Div1Q_F32ls_C(a32Num, f16Denom) +#define MLIB_DivSat_F16(f16Num, f16Denom) MLIB_DivSat_F16_Ci(f16Num, f16Denom) +#define MLIB_DivSat_F16ll(f32Num, f32Denom) MLIB_DivSat_F16ll_Asm(f32Num, f32Denom) +#define MLIB_DivSat_F16ls(f32Num, f16Denom) MLIB_DivSat_F16ls_Ci(f32Num, f16Denom) +#define MLIB_DivSat_F32(f32Num, f32Denom) MLIB_DivSat_F32_Asm(f32Num, f32Denom) +#define MLIB_DivSat_F32ls(f32Num, f16Denom) MLIB_DivSat_F32ls_C(f32Num, f16Denom) +#define MLIB_DivSat_A32as(a32Num, f16Denom) MLIB_DivSat_F32ls_C(a32Num, f16Denom) +#define MLIB_Div_A32ll(f32Num, f32Denom) MLIB_Div_A32ll_Asm(f32Num, f32Denom) +#define MLIB_Div_A32ls(f32Num, f16Denom) MLIB_Div_A32ls_Ci(f32Num, f16Denom) +#define MLIB_Div_A32ss(f16Num, f16Denom) MLIB_Div_A32ss_Ci(f16Num, f16Denom) +#define MLIB_Div_A32as(a32Num, f16Denom) MLIB_Div_F32ls_C(a32Num, f16Denom) +#define MLIB_Div_F16(f16Num, f16Denom) MLIB_Div_F16_Ci(f16Num, f16Denom) +#define MLIB_Div_F16ll(f32Num, f32Denom) MLIB_Div_F16ll_Asm(f32Num, f32Denom) +#define MLIB_Div_F16ls(f32Num, f16Denom) MLIB_Div_F16ls_Ci(f32Num, f16Denom) +#define MLIB_Div_F32(f32Num, f32Denom) MLIB_Div_F32_Asm(f32Num, f32Denom) +#define MLIB_Div_F32ls(f32Num, f16Denom) MLIB_Div_F32ls_C(f32Num, f16Denom) +#define MLIB_Log2_U16(u16Val) MLIB_Log2_U16_Ci(u16Val) +#define MLIB_Mac4RndSat_F16(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) MLIB_Mac4RndSat_F16_Asmi(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) +#define MLIB_Mac4RndSat_F32(f32Add1Mul1, f32Add1Mul2, f32Add2Mul1, f32Add2Mul2) MLIB_Mac4RndSat_F32_Asmi(f32Add1Mul1, f32Add1Mul2, f32Add2Mul1, f32Add2Mul2) +#define MLIB_Mac4Rnd_F16(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) MLIB_Mac4Rnd_F16_Asmi(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) +#define MLIB_Mac4Rnd_F32(f32Add1Mul1, f32Add1Mul2, f32Add2Mul1, f32Add2Mul2) MLIB_Mac4Rnd_F32_Ci(f32Add1Mul1, f32Add1Mul2, f32Add2Mul1, f32Add2Mul2) +#define MLIB_Mac4Sat_F32ssss(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) MLIB_Mac4Sat_F32ssss_Asmi(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) +#define MLIB_Mac4_F32ssss(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) MLIB_Mac4_F32ssss_Ci(f16Add1Mul1, f16Add1Mul2, f16Add2Mul1, f16Add2Mul2) +#define MLIB_MacRndSat_F16( f16Accum, f16Mult1, f16Mult2) MLIB_MacRndSat_F16_Asmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_MacRndSat_F32( f32Accum, f32Mult1, f32Mult2) MLIB_MacRndSat_F32_Asmi( f32Accum, f32Mult1, f32Mult2) +#define MLIB_MacRndSat_F32lls( f32Accum, f32Mult1, f16Mult2) MLIB_MacRndSat_F32lls_Asmi( f32Accum, f32Mult1, f16Mult2) +#define MLIB_MacRnd_A32ass(a32Accum, f16Mult1, f16Mult2) MLIB_MacRnd_A32ass_Ci(a32Accum, f16Mult1, f16Mult2) +#define MLIB_MacRnd_F16( f16Accum, f16Mult1, f16Mult2) MLIB_MacRnd_F16_Asmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_MacRnd_F32( f32Accum, f32Mult1, f32Mult2) MLIB_MacRnd_F32_Asmi( f32Accum, f32Mult1, f32Mult2) +#define MLIB_MacRnd_F32lls( f32Accum, f32Mult1, f16Mult2) MLIB_MacRnd_F32lls_Ci( f32Accum, f32Mult1, f16Mult2) +#define MLIB_MacSat_F16( f16Accum, f16Mult1, f16Mult2) MLIB_MacSat_F16_Asmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_MacSat_F32( f32Accum, f32Mult1, f32Mult2) MLIB_MacSat_F32_Asmi( f32Accum, f32Mult1, f32Mult2) +#define MLIB_MacSat_F32lss( f32Accum, f16Mult1, f16Mult2) MLIB_MacSat_F32lss_Asmi( f32Accum, f16Mult1, f16Mult2) +#define MLIB_Mac_A32ass(a32Accum, f16Mult1, f16Mult2) MLIB_Mac_A32ass_Ci(a32Accum, f16Mult1, f16Mult2) +#define MLIB_Mac_F16( f16Accum, f16Mult1, f16Mult2) MLIB_Mac_F16_Asmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_Mac_F32( f32Accum, f32Mult1, f32Mult2) MLIB_Mac_F32_Asmi( f32Accum, f32Mult1, f32Mult2) +#define MLIB_Mac_F32lss( f32Accum, f16Mult1, f16Mult2) MLIB_Mac_F32lss_Asmi( f32Accum, f16Mult1, f16Mult2) +#define MLIB_MnacRndSat_F16( f16Accum, f16Mult1, f16Mult2) MLIB_MnacRndSat_F16_Asmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_MnacRndSat_F32( f32Accum, f32Mult1, f32Mult2) MLIB_MnacRndSat_F32_Asmi( f32Accum, f32Mult1, f32Mult2) +#define MLIB_MnacRndSat_F32lls( f32Accum, f32Mult1, f16Mult2) MLIB_MnacRndSat_F32lls_Asmi( f32Accum, f32Mult1, f16Mult2) +#define MLIB_MnacRnd_A32ass(a32Accum, f16Mult1, f16Mult2) MLIB_MnacRnd_A32ass_Ci(a32Accum, f16Mult1, f16Mult2) +#define MLIB_MnacRnd_F16( f16Accum, f16Mult1, f16Mult2) MLIB_MnacRnd_F16_Asmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_MnacRnd_F32( f32Accum, f32Mult1, f32Mult2) MLIB_MnacRnd_F32_Asmi( f32Accum, f32Mult1, f32Mult2) +#define MLIB_MnacRnd_F32lls( f32Accum, f32Mult1, f16Mult2) MLIB_MnacRnd_F32lls_Ci( f32Accum, f32Mult1, f16Mult2) +#define MLIB_MnacSat_F16( f16Accum, f16Mult1, f16Mult2) MLIB_MnacSat_F16_Asmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_MnacSat_F32( f32Accum, f32Mult1, f32Mult2) MLIB_MnacSat_F32_Asmi( f32Accum, f32Mult1, f32Mult2) +#define MLIB_MnacSat_F32lss( f32Accum, f16Mult1, f16Mult2) MLIB_MnacSat_F32lss_Asmi( f32Accum, f16Mult1, f16Mult2) +#define MLIB_Mnac_A32ass(a32Accum, f16Mult1, f16Mult2) MLIB_Mnac_A32ass_Ci(a32Accum, f16Mult1, f16Mult2) +#define MLIB_Mnac_F16( f16Accum, f16Mult1, f16Mult2) MLIB_Mnac_F16_Asmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_Mnac_F32( f32Accum, f32Mult1, f32Mult2) MLIB_Mnac_F32_Asmi( f32Accum, f32Mult1, f32Mult2) +#define MLIB_Mnac_F32lss( f32Accum, f16Mult1, f16Mult2) MLIB_Mnac_F32lss_Asmi( f32Accum, f16Mult1, f16Mult2) +#define MLIB_Msu4RndSat_F16( f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) MLIB_Msu4RndSat_F16_Asmi( f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) +#define MLIB_Msu4RndSat_F32( f32MinMul1, f32MinMul2, f32SubMul1, f32SubMul2) MLIB_Msu4RndSat_F32_Asmi( f32MinMul1, f32MinMul2, f32SubMul1, f32SubMul2) +#define MLIB_Msu4Rnd_F16( f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) MLIB_Msu4Rnd_F16_Ci( f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) +#define MLIB_Msu4Rnd_F32( f32MinMul1, f32MinMul2, f32SubMul1, f32SubMul2) MLIB_Msu4Rnd_F32_Ci( f32MinMul1, f32MinMul2, f32SubMul1, f32SubMul2) +#define MLIB_Msu4Sat_F32ssss(f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) MLIB_Msu4Sat_F32ssss_Asmi(f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) +#define MLIB_Msu4_F32ssss(f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) MLIB_Msu4_F32ssss_Ci(f16MinMul1, f16MinMul2, f16SubMul1, f16SubMul2) +#define MLIB_MsuRndSat_F16( f16Accum, f16Mult1, f16Mult2) MLIB_MsuRndSat_F16_Asmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_MsuRndSat_F32( f32Accum, f32Mult1, f32Mult2) MLIB_MsuRndSat_F32_Asmi( f32Accum, f32Mult1, f32Mult2) +#define MLIB_MsuRndSat_F32lls( f32Accum, f32Mult1, f16Mult2) MLIB_MsuRndSat_F32lls_Asmi( f32Accum, f32Mult1, f16Mult2) +#define MLIB_MsuRnd_A32ass( a32Accum, f16Mult1, f16Mult2) MLIB_MsuRnd_A32ass_Ci( a32Accum, f16Mult1, f16Mult2) +#define MLIB_MsuRnd_F16( f16Accum, f16Mult1, f16Mult2) MLIB_MsuRnd_F16_Asmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_MsuRnd_F32( f32Accum, f32Mult1, f32Mult2) MLIB_MsuRnd_F32_Ci( f32Accum, f32Mult1, f32Mult2) +#define MLIB_MsuRnd_F32lls( f32Accum, f32Mult1, f16Mult2) MLIB_MsuRnd_F32lls_Asmi( f32Accum, f32Mult1, f16Mult2) +#define MLIB_MsuSat_F16( f16Accum, f16Mult1, f16Mult2) MLIB_MsuSat_F16_Asmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_MsuSat_F32( f32Accum, f32Mult1, f32Mult2) MLIB_MsuSat_F32_Asmi( f32Accum, f32Mult1, f32Mult2) +#define MLIB_MsuSat_F32lss( f32Accum, f16Mult1, f16Mult2) MLIB_MsuSat_F32lss_Asmi( f32Accum, f16Mult1, f16Mult2) +#define MLIB_Msu_A32ass( a32Accum, f16Mult1, f16Mult2) MLIB_Msu_A32ass_Ci( a32Accum, f16Mult1, f16Mult2) +#define MLIB_Msu_F16( f16Accum, f16Mult1, f16Mult2) MLIB_Msu_F16_Asmi( f16Accum, f16Mult1, f16Mult2) +#define MLIB_Msu_F32( f32Accum, f32Mult1, f32Mult2) MLIB_Msu_F32_Asmi( f32Accum, f32Mult1, f32Mult2) +#define MLIB_Msu_F32lss( f32Accum, f16Mult1, f16Mult2) MLIB_Msu_F32lss_Asmi( f32Accum, f16Mult1, f16Mult2) +#define MLIB_MulNegRndSat_A32( a32Mult1, a32Mult2) MLIB_MulNegRndSat_A32_Asmi( a32Mult1, a32Mult2) +#define MLIB_MulNegRndSat_F16as( a32Accum, f16Mult) MLIB_MulNegRndSat_F16as_Asmi( a32Accum, f16Mult) +#define MLIB_MulNegRnd_F16( f16Mult1, f16Mult2) MLIB_MulNegRnd_F16_Ci( f16Mult1, f16Mult2) +#define MLIB_MulNegRnd_F16as( a32Accum, f16Mult) MLIB_MulNegRnd_F16as_Ci( a32Accum, f16Mult) +#define MLIB_MulNegRnd_F32( f32Mult1, f32Mult2) MLIB_MulNegRnd_F32_Ci( f32Mult1, f32Mult2) +#define MLIB_MulNegRnd_F32ls( f32Mult1, f16Mult2) MLIB_MulNegRnd_F32ls_Ci( f32Mult1, f16Mult2) +#define MLIB_MulNegRnd_A32( a32Mult1, a32Mult2) MLIB_MulNegRnd_A32_Ci( a32Mult1, a32Mult2) +#define MLIB_MulNeg_F16( f16Mult1, f16Mult2) MLIB_MulNeg_F16_Ci( f16Mult1, f16Mult2) +#define MLIB_MulNeg_F16as( a32Accum, f16Mult) MLIB_MulNeg_F16as_Ci( a32Accum, f16Mult) +#define MLIB_MulNeg_F32( f32Mult1, f32Mult2) MLIB_MulNeg_F32_Ci( f32Mult1, f32Mult2) +#define MLIB_MulNeg_F32ss( f16Mult1, f16Mult2) MLIB_MulNeg_F32ss_Ci( f16Mult1, f16Mult2) +#define MLIB_MulNeg_A32( a32Mult1, a32Mult2) MLIB_MulNeg_A32_Ci( a32Mult1, a32Mult2) +#define MLIB_MulNegSat_A32( a32Mult1, a32Mult2) MLIB_MulNegSat_A32_Asmi( a32Mult1, a32Mult2) +#define MLIB_MulNegSat_F16as( a32Accum, f16Mult) MLIB_MulNegSat_F16as_Asmi( a32Accum, f16Mult) +#define MLIB_MulRndSat_F16( f16Mult1, f16Mult2) MLIB_MulRndSat_F16_Asmi( f16Mult1, f16Mult2) +#define MLIB_MulRndSat_F16as( a32Accum, f16Mult) MLIB_MulRndSat_F16as_Asmi( a32Accum, f16Mult) +#define MLIB_MulRndSat_F32( f32Mult1, f32Mult2) MLIB_MulRndSat_F32_Asmi( f32Mult1, f32Mult2) +#define MLIB_MulRndSat_F32ls( f32Mult1, f16Mult2) MLIB_MulRndSat_F32ls_Asmi( f32Mult1, f16Mult2) +#define MLIB_MulRndSat_A32( a32Mult1, a32Mult2) MLIB_MulRndSat_A32_Asmi( a32Mult1, a32Mult2) +#define MLIB_MulRnd_F16( f16Mult1, f16Mult2) MLIB_MulRnd_F16_Ci( f16Mult1, f16Mult2) +#define MLIB_MulRnd_F16as( a32Accum, f16Mult) MLIB_MulRnd_F16as_Ci( a32Accum, f16Mult) +#define MLIB_MulRnd_F32( f32Mult1, f32Mult2) MLIB_MulRnd_F32_Ci( f32Mult1, f32Mult2) +#define MLIB_MulRnd_F32ls( f32Mult1, f16Mult2) MLIB_MulRnd_F32ls_Ci( f32Mult1, f16Mult2) +#define MLIB_MulRnd_A32( a32Mult1, a32Mult2) MLIB_MulRnd_A32_Ci( a32Mult1, a32Mult2) +#define MLIB_MulSat_F16( f16Mult1, f16Mult2) MLIB_MulSat_F16_Asmi( f16Mult1, f16Mult2) +#define MLIB_MulSat_F16as( a32Accum, f16Mult) MLIB_MulSat_F16as_Asmi( a32Accum, f16Mult) +#define MLIB_MulSat_F32( f32Mult1, f32Mult2) MLIB_MulSat_F32_Asmi( f32Mult1, f32Mult2) +#define MLIB_MulSat_F32ss( f16Mult1, f16Mult2) MLIB_MulSat_F32ss_Asmi( f16Mult1, f16Mult2) +#define MLIB_MulSat_A32( a32Mult1, a32Mult2) MLIB_MulSat_A32_Asmi( a32Mult1, a32Mult2) +#define MLIB_Mul_F16( f16Mult1, f16Mult2) MLIB_Mul_F16_Ci( f16Mult1, f16Mult2) +#define MLIB_Mul_F16as( a32Accum, f16Mult) MLIB_Mul_F16as_Ci( a32Accum, f16Mult) +#define MLIB_Mul_F32( f32Mult1, f32Mult2) MLIB_Mul_F32_Ci( f32Mult1, f32Mult2) +#define MLIB_Mul_F32ss( f16Mult1, f16Mult2) MLIB_Mul_F32ss_Ci( f16Mult1, f16Mult2) +#define MLIB_Mul_A32( a32Mult1, a32Mult2) MLIB_Mul_A32_Ci( a32Mult1, a32Mult2) +#define MLIB_NegSat_F16(f16Val) MLIB_NegSat_F16_Asmi(f16Val) +#define MLIB_NegSat_F32(f32Val) MLIB_NegSat_F32_Asmi(f32Val) +#define MLIB_Neg_F16(f16Val) MLIB_Neg_F16_Ci(f16Val) +#define MLIB_Neg_F32(f32Val) MLIB_Neg_F32_Ci(f32Val) +#define MLIB_Rcp1Q1_A32s(f16Denom) MLIB_Rcp1Q1_A32s_Ci(f16Denom) +#define MLIB_Rcp1Q_A32s(f16Denom) MLIB_Rcp1Q_A32s_Ci(f16Denom) +#define MLIB_Rcp1_A32s(f16Denom) MLIB_Rcp1_A32s_Ci(f16Denom) +#define MLIB_Rcp_A32s(f16Denom) MLIB_Rcp_A32s_Ci(f16Denom) +#define MLIB_RndSat_F16l(f32Val) MLIB_RndSat_F16l_Asmi(f32Val) +#define MLIB_Rnd_F16l(f32Val) MLIB_Rnd_F16l_Ci(f32Val) +#define MLIB_Sat_F16a(a32Accum) MLIB_Sat_F16a_Asmi(a32Accum) +#define MLIB_Sh1LSat_F16(f16Val) MLIB_Sh1LSat_F16_Asmi(f16Val) +#define MLIB_Sh1LSat_F32(f32Val) MLIB_Sh1LSat_F32_Asmi(f32Val) +#define MLIB_Sh1L_F16(f16Val) MLIB_Sh1L_F16_Ci(f16Val) +#define MLIB_Sh1L_F32(f32Val) MLIB_Sh1L_F32_Ci(f32Val) +#define MLIB_Sh1R_F16(f16Val) MLIB_Sh1R_F16_Ci(f16Val) +#define MLIB_Sh1R_F32(f32Val) MLIB_Sh1R_F32_Ci(f32Val) +#define MLIB_ShLBiSat_F16(f16Val, i16Sh) MLIB_ShLBiSat_F16_Ci(f16Val, i16Sh) +#define MLIB_ShLBiSat_F32(f32Val, i16Sh) MLIB_ShLBiSat_F32_Ci(f32Val, i16Sh) +#define MLIB_ShLBi_F16(f16Val, i16Sh) MLIB_ShLBi_F16_Ci(f16Val, i16Sh) +#define MLIB_ShLBi_F32(f32Val, i16Sh) MLIB_ShLBi_F32_Ci(f32Val, i16Sh) +#define MLIB_ShLSat_F16(f16Val, u16Sh) MLIB_ShLSat_F16_Asmi(f16Val, u16Sh) +#define MLIB_ShLSat_F32(f32Val, u16Sh) MLIB_ShLSat_F32_Asmi(f32Val, u16Sh) +#define MLIB_ShL_F16(f16Val, u16Sh) MLIB_ShL_F16_Ci(f16Val, u16Sh) +#define MLIB_ShL_F32(f32Val, u16Sh) MLIB_ShL_F32_Ci(f32Val, u16Sh) +#define MLIB_ShRBiSat_F16(f16Val, i16Sh) MLIB_ShRBiSat_F16_Ci(f16Val, i16Sh) +#define MLIB_ShRBiSat_F32(f32Val, i16Sh) MLIB_ShRBiSat_F32_Ci(f32Val, i16Sh) +#define MLIB_ShRBi_F16(f16Val, i16Sh) MLIB_ShRBi_F16_Ci(f16Val, i16Sh) +#define MLIB_ShRBi_F32(f32Val, i16Sh) MLIB_ShRBi_F32_Ci(f32Val, i16Sh) +#define MLIB_ShR_F16(f16Val, u16Sh) MLIB_ShR_F16_Ci(f16Val, u16Sh) +#define MLIB_ShR_F32(f32Val, u16Sh) MLIB_ShR_F32_Ci(f32Val, u16Sh) +#define MLIB_Sign_F16(f16Val) MLIB_Sign_F16_Asmi(f16Val) +#define MLIB_Sign_F32(f32Val) MLIB_Sign_F32_Asmi(f32Val) +#define MLIB_Sub4Sat_F16(f16Min, f16Sub1, f16Sub2, f16Sub3) MLIB_Sub4Sat_F16_Asmi(f16Min, f16Sub1, f16Sub2, f16Sub3) +#define MLIB_Sub4Sat_F32(f32Min, f32Sub1, f32Sub2, f32Sub3) MLIB_Sub4Sat_F32_Asmi(f32Min, f32Sub1, f32Sub2, f32Sub3) +#define MLIB_Sub4_F16(f16Min, f16Sub1, f16Sub2, f16Sub3) MLIB_Sub4_F16_Asmi(f16Min, f16Sub1, f16Sub2, f16Sub3) +#define MLIB_Sub4_F32(f32Min, f32Sub1, f32Sub2, f32Sub3) MLIB_Sub4_F32_Asmi(f32Min, f32Sub1, f32Sub2, f32Sub3) +#define MLIB_SubSat_F16(f16Min, f16Sub) MLIB_SubSat_F16_Asmi(f16Min, f16Sub) +#define MLIB_SubSat_F32(f32Min, f32Sub) MLIB_SubSat_F32_Asmi(f32Min, f32Sub) +#define MLIB_Sub_A32as(a32Accum, f16Sub) MLIB_Sub_A32as_Ci(a32Accum, f16Sub) +#define MLIB_Sub_A32ss(f16Min, f16Sub) MLIB_Sub_A32ss_Ci(f16Min, f16Sub) +#define MLIB_Sub_F16(f16Min, f16Sub) MLIB_Sub_F16_Ci(f16Min, f16Sub) +#define MLIB_Sub_F32(f32Min, f32Sub) MLIB_Sub_F32_Ci(f32Min, f32Sub) + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/mlib_FP.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/mlib_FP.h new file mode 100644 index 000000000..bdfdbc6a5 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/mlib_FP.h @@ -0,0 +1,100 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Main MLIB header file for devices with FPU. +* +*******************************************************************************/ +#ifndef _MLIB_FP_H_ +#define _MLIB_FP_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/****************************************************************************** +* Includes +******************************************************************************/ +#include "mlib.h" +#include "MLIB_Abs_FLT.h" +#include "MLIB_Abs_FLT_Asmi.h" +#include "MLIB_Add4_FLT.h" +#include "MLIB_Add_FLT.h" +#include "MLIB_ConvSc_FLT_Asmi.h" +#include "MLIB_Conv_FLT_Asmi.h" +#include "MLIB_Div_FLT.h" +#include "MLIB_Mac4_FLT.h" +#include "MLIB_Mac_FLT.h" +#include "MLIB_Mnac_FLT.h" +#include "MLIB_Msu4_FLT.h" +#include "MLIB_Msu_FLT.h" +#include "MLIB_Mul_FLT.h" +#include "MLIB_Neg_FLT.h" +#include "MLIB_Sign_FLT_Asmi.h" +#include "MLIB_Sub4_FLT.h" +#include "MLIB_Sub_FLT.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_Abs_FLT(fltVal) MLIB_Abs_FLT_Asmi(fltVal) +#define MLIB_Add4_FLT(fltAdd1, fltAdd2, fltAdd3, fltAdd4) MLIB_Add4_FLT_Ci(fltAdd1, fltAdd2, fltAdd3, fltAdd4) +#define MLIB_Add_FLT(fltAdd1, fltAdd2) MLIB_Add_FLT_Ci(fltAdd1, fltAdd2) +#define MLIB_ConvSc_F16ff(fltVal, fltSc) MLIB_ConvSc_F16ff_Asmi(fltVal, fltSc) +#define MLIB_ConvSc_F32ff(fltVal, fltSc) MLIB_ConvSc_F32ff_Asmi(fltVal, fltSc) +#define MLIB_ConvSc_FLTlf(f32Val, fltSc) MLIB_ConvSc_FLTlf_Asmi(f32Val, fltSc) +#define MLIB_ConvSc_FLTsf(f16Val, fltSc) MLIB_ConvSc_FLTsf_Asmi(f16Val, fltSc) +#define MLIB_ConvSc_A32ff(fltVal, fltSc) MLIB_ConvSc_A32ff_Asmi(fltVal, fltSc) +#define MLIB_ConvSc_FLTaf(a32Val, fltSc) MLIB_ConvSc_FLTaf_Asmi(a32Val, fltSc) +#define MLIB_Conv_F16f(fltVal) MLIB_Conv_F16f_Asmi(fltVal) +#define MLIB_Conv_F32f(fltVal) MLIB_Conv_F32f_Asmi(fltVal) +#define MLIB_Conv_FLTl(f32Val) MLIB_Conv_FLTl_Asmi(f32Val) +#define MLIB_Conv_FLTs(f16Val) MLIB_Conv_FLTs_Asmi(f16Val) +#define MLIB_Conv_A32f(fltVal) MLIB_Conv_A32f_Asmi(fltVal) +#define MLIB_Conv_FLTa(a32Val) MLIB_Conv_FLTa_Asmi(a32Val) +#define MLIB_Div_FLT(fltNum, fltDenom) MLIB_Div_FLT_Ci(fltNum, fltDenom) +#define MLIB_Mac4_FLT(fltAdd1Mul1, fltAdd1Mul2, fltAdd2Mul1, fltAdd2Mul2) MLIB_Mac4_FLT_Ci(fltAdd1Mul1, fltAdd1Mul2, fltAdd2Mul1, fltAdd2Mul2) +#define MLIB_Mac_FLT(fltAccum, fltMult1, fltMult2) MLIB_Mac_FLT_Ci(fltAccum, fltMult1, fltMult2) +#define MLIB_Mnac_FLT(fltAccum, fltMult1, fltMult2) MLIB_Mnac_FLT_Ci(fltAccum, fltMult1, fltMult2) +#define MLIB_Msu4_FLT(fltMinMul1, fltMinMul2, fltSubMul1, fltSubMul2) MLIB_Msu4_FLT_Ci(fltMinMul1, fltMinMul2, fltSubMul1, fltSubMul2) +#define MLIB_Msu_FLT(fltAccum, fltMult1, fltMult2) MLIB_Msu_FLT_Ci(fltAccum, fltMult1, fltMult2) +#define MLIB_MulNeg_FLT( fltAccum, fltMult) MLIB_MulNeg_FLT_Ci( fltAccum, fltMult) +#define MLIB_Mul_FLT(fltAccum, fltMult) MLIB_Mul_FLT_Ci(fltAccum, fltMult) +#define MLIB_Neg_FLT(fltVal) MLIB_Neg_FLT_Ci(fltVal) +#define MLIB_Sign_FLT(fltVal) MLIB_Sign_FLT_Asmi(fltVal) +#define MLIB_Sub4_FLT(fltMin, fltSub1, fltSub2, fltSub3) MLIB_Sub4_FLT_Ci(fltMin, fltSub1, fltSub2, fltSub3) +#define MLIB_Sub_FLT(fltMin, fltSub) MLIB_Sub_FLT_Ci(fltMin, fltSub) + +#if defined(__cplusplus) +} +#endif + +#endif /* _MLIB_FP_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/mlib_types.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/mlib_types.h new file mode 100644 index 000000000..68a2df636 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/Include/mlib_types.h @@ -0,0 +1,237 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Basic types for RTCESL +* +*******************************************************************************/ +#ifndef _MLIB_TYPES_H_ +#define _MLIB_TYPES_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/****************************************************************************** +* Includes +******************************************************************************/ +#include /* stdint.h include for data types */ +#include "RTCESL_cfg.h" /* includes the RTCESL configuration */ + +/* Include intrinsic functions */ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ + #include /* To use intrinsic functions */ +#endif + +/*! Definition of inline. */ +#if defined(__CC_ARM) + #define inline __inline +#endif + +/******************************************************************************* +* Types +*******************************************************************************/ +/* Boolean data types */ +typedef unsigned short bool_t; + +#if !defined(__MSL_BUILD__) +#if !defined( __STDINT_DECLS) +/* Signed and Unsigned integer data types */ + +/* 8 bits */ +#if !defined( __int8_t_defined) +#if !defined(__INT8_T_TYPE__) +typedef signed char int8_t; +#endif /* __INT8_T_TYPE__ */ +#if !defined(__INT8_T_TYPE__) +typedef unsigned char uint8_t; +#endif /* __INT8_T_TYPE__ */ +#define __int8_t_defined 1 +#endif /* __int8_t_defined */ + +/* 16 bits */ +#if !defined( __int16_t_defined) +#if !defined(__INT16_T_TYPE__) +typedef signed short int16_t; +#endif /* __INT16_T_TYPE__ */ +#if !defined(__INT16_T_TYPE__) +typedef unsigned short uint16_t; +#endif /* __INT16_T_TYPE__ */ +#define __int16_t_defined 1 +#endif /* __int16_t_defined */ + +/* 32 bits */ +#if !defined( __int32_t_defined) +#if !defined(__STDINT_H_INCLUDED) +#if !defined(__INT32_T_TYPE__) +typedef signed long int32_t; +#endif /* __INT32_T_TYPE__ */ +#if !defined(__INT32_T_TYPE__) +typedef unsigned long uint32_t; +#endif /* __INT32_T_TYPE__ */ +#define __int32_t_defined 1 +#endif /* __STDINT_H_INCLUDED */ +#endif /* __int32_t_defined */ + +/* 64 bits */ +#if !defined( __int64_t_defined) +#if !defined(__INT64_T_TYPE__) +typedef signed long long int64_t; +#endif /* __INT64_T_TYPE__ */ +#if !defined(__INT64_T_TYPE__) +typedef unsigned long long uint64_t; +#endif /* __INT64_T_TYPE__ */ +#define __int64_t_defined 1 +#endif /* __int64_t_defined */ + +#endif /* __STDINT_DECLS */ +#endif /* __MSL_BUILD__ */ + +/* Fractional data types */ +typedef signed char frac8_t; +typedef signed short frac16_t; +typedef signed long frac32_t; +typedef signed long long frac64_t; + +/* Accumulator data types */ +typedef signed short acc16_t; +typedef signed long acc32_t; +typedef signed long long acc64_t; + +/* Float data types */ +typedef float float_t; + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define MLIB_CONST + +/* bool */ +#ifndef FALSE +#define FALSE ((bool_t)0) +#endif + +#ifndef TRUE +#define TRUE ((bool_t)1) +#endif + +/* unsigned min, max */ +#ifndef INT16_MIN +#define INT16_MIN ((int16_t) 0x8000) +#endif + +#ifndef INT16_MAX +#define INT16_MAX ((int16_t) 0x7fff) +#endif + +#ifndef INT32_MIN +#define INT32_MIN ((int32_t) 0x80000000U) +#endif + +#ifndef INT32_MAX +#define INT32_MAX ((int32_t) 0x7fffffff) +#endif + +#ifndef INT64_MIN +#define INT64_MIN ((int64_t) 0x8000000000000000U) +#endif + +#ifndef INT64_MAX +#define INT64_MAX ((int64_t) 0x7fffffffffffffff) +#endif + +/* unsigned min, max */ +#ifndef UINT16_MAX +#define UINT16_MAX ((uint16_t) 0x8000U) +#endif + +#ifndef UINT32_MAX +#define UINT32_MAX ((uint32_t) 0x80000000U) +#endif + +/* float */ +#ifndef FLOAT_MINUS_MIN +#define FLOAT_MINUS_MIN ((float_t)(-0x1p-126)) /* -1.17549435E-38, 0x80800000 */ +#endif + +#ifndef FLOAT_PLUS_MIN +#define FLOAT_PLUS_MIN ((float_t)(0x1p-126)) /* 1.17549435E-38, 0x00800000*/ +#endif + +#ifndef FLOAT_MINUS_MAX +#define FLOAT_MINUS_MAX ((float_t)(-0x1.FFFFFEp127)) /* -3.40282346E+38, 0xFF7FFFFF */ +#endif + +#ifndef FLOAT_PLUS_MAX +#define FLOAT_PLUS_MAX ((float_t)(0x1.FFFFFEp127)) /* 3.40282346E+38F, 0x7F7FFFFF */ +#endif + +#ifndef FLOAT_PI /* 3.1415927411 = */ +#define FLOAT_PI ((float_t)(0x1.921FB6P1)) /* = 1.1001 0010 0001 1111 1011 0110 = */ +#endif /* = 0x1.921FB6P1, 0x40490FDB */ + +/* Not a number constant */ +#if defined(__IAR_SYSTEMS_ICC__) /* IAR compiler */ + #define RTCESL_NAN ((float_t)(0.Nan)) /* 0x7FFFFFFF = quiet NaN */ +#elif defined(__CC_ARM) /* ARM(KEIL) compiler */ + #define RTCESL_NAN (__ESCAPE__(0f_7FC00000)) /* 7FC00000 = Quiet NaN */ +#else /* GCC(KDS) compiler */ + #define RTCESL_NAN ((float_t)0x7FC00000) /* 7FC00000 = Quiet NaN */ +#endif + +/* Fractional conversion macros */ +#if !defined(FRAC8) +#define FRAC8(x) ((frac8_t)((x) < 0.9921875 ? ((x) >= -1.0 ? (x)*((double)0x80U) : ((double)0x80U)) : ((double)0x7FU))) +#endif /*FRAC8*/ + +#if !defined(FRAC16) +#define FRAC16(x) ((frac16_t)((x) < 0.999969482421875 ? ((x) >= -1.0 ? (x)*((double)0x8000U) : ((double)0x8000U)) : ((double)0x7FFFU))) +#endif /*FRAC16 */ + +#if !defined(FRAC32) +#define FRAC32(x) ((frac32_t)((x) < 1.0 ? ((x) >= -1.0 ? (x)*((double)0x80000000U) : ((double)-2147483648)) : ((double)0x7FFFFFFFU))) +#endif /*FRAC64*/ + +/* Accumulator conversion macros */ +#if !defined(ACC16) +#define ACC16(x) ((acc16_t)((x) < 255.9921875 ? ((x) >= -256.0 ? (x)*((double)0x80U) : ((double)0x8000U)) : ((double)0x7FFFU))) +#endif /*ACC16*/ + +#if !defined(ACC32) +#define ACC32(x) ((acc32_t)((x) < 65535.999969482421875 ? ((x) >= -65536.0 ? (x)*((double)0x8000U) : ((double)-2147483648)) : ((double)0x7FFFFFFFU))) +#endif /*ACC32*/ + + +#if defined(__cplusplus) +} +#endif + +#endif /*_MLIB_TYPES_H_*/ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/libMLIB.a b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/libMLIB.a new file mode 100644 index 000000000..284bc1893 Binary files /dev/null and b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/MLIB/libMLIB.a differ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_Ctrl2P2Z_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_Ctrl2P2Z_F16.h new file mode 100644 index 000000000..db9037e39 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_Ctrl2P2Z_F16.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************/ +#ifndef _PCLIB_CTRL2P2Z_F16_H_ +#define _PCLIB_CTRL2P2Z_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "pclib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define PCLIB_Ctrl2P2ZInit_F16_C(psParam) PCLIB_Ctrl2P2ZInit_F16_FC(psParam) +#define PCLIB_Ctrl2P2Z_F16_C(f16InErr, psParam) PCLIB_Ctrl2P2Z_F16_FC(f16InErr, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac16_t f16CoeffB0; /* Controller coefficient for present error. */ + frac16_t f16CoeffB1; /* Controller coefficient for past error. */ + frac16_t f16CoeffB2; /* Controller coefficient for past to past error. */ + frac16_t f16CoeffA1; /* Controller coefficient for past result. */ + frac16_t f16CoeffA2; /* Controller coefficient for past to past result. */ + frac16_t f16DelayX1; /* Controller delay parameter, past error. */ + frac16_t f16DelayX2; /* Controller delay parameter, past to past error. */ + frac16_t f16DelayY1; /* Controller delay parameter, past result. */ + frac16_t f16DelayY2; /* Controller delay parameter, past to past result. */ +} PCLIB_CTRL_2P2Z_T_F16; + +/**************************************************************************** +* Exported function prototypes +****************************************************************************/ +extern void PCLIB_Ctrl2P2ZInit_F16_FC(PCLIB_CTRL_2P2Z_T_F16 *psParam); +extern frac16_t PCLIB_Ctrl2P2Z_F16_FC(frac16_t f16InErr, PCLIB_CTRL_2P2Z_T_F16 *psParam); + + +#if defined(__cplusplus) +} +#endif + +#endif /* _PCLIB_CTRL2P2Z_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_Ctrl3P3Z_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_Ctrl3P3Z_F16.h new file mode 100644 index 000000000..c59e43342 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_Ctrl3P3Z_F16.h @@ -0,0 +1,81 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************/ +#ifndef _PCLIB_CTRL3P3Z_F16_H_ +#define _PCLIB_CTRL3P3Z_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "pclib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define PCLIB_Ctrl3P3ZInit_F16_C(psParam) PCLIB_Ctrl3P3ZInit_F16_FC(psParam) +#define PCLIB_Ctrl3P3Z_F16_C(f16InErr, psParam) PCLIB_Ctrl3P3Z_F16_FC(f16InErr, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac16_t f16CoeffB0; /* Controller coefficient for present error. */ + frac16_t f16CoeffB1; /* Controller coefficient for past error. */ + frac16_t f16CoeffB2; /* Controller coefficient for past to past error. */ + frac16_t f16CoeffB3; /* Controller coefficient for past to past to past error. */ + frac16_t f16CoeffA1; /* Controller coefficient for past result. */ + frac16_t f16CoeffA2; /* Controller coefficient for past to past result. */ + frac16_t f16CoeffA3; /* Controller coefficient for past to past to past result. */ + frac16_t f16DelayX1; /* Controller delay parameter, past error. */ + frac16_t f16DelayX2; /* Controller delay parameter, past to past error. */ + frac16_t f16DelayX3; /* Controller delay parameter, past to past to past error. */ + frac16_t f16DelayY1; /* Controller delay parameter, past result. */ + frac16_t f16DelayY2; /* Controller delay parameter, past to past result. */ + frac16_t f16DelayY3; /* Controller delay parameter, past to past to past result. */ +} PCLIB_CTRL_3P3Z_T_F16; + +/**************************************************************************** +* Exported function prototypes +****************************************************************************/ +extern void PCLIB_Ctrl3P3ZInit_F16_FC(PCLIB_CTRL_3P3Z_T_F16 *psParam); +extern frac16_t PCLIB_Ctrl3P3Z_F16_FC(frac16_t f16InErr, PCLIB_CTRL_3P3Z_T_F16 *psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PCLIB_CTRL3P3Z_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_CtrlPID_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_CtrlPID_F16.h new file mode 100644 index 000000000..0f002738b --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_CtrlPID_F16.h @@ -0,0 +1,77 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************/ +#ifndef _PCLIB_CTRLPID_F16_H_ +#define _PCLIB_CTRLPID_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "pclib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define PCLIB_CtrlPIDInit_F16_C(psParam) PCLIB_CtrlPIDInit_F16_FC(psParam) +#define PCLIB_CtrlPID_F16_C(f16InErr, psParam) PCLIB_CtrlPID_F16_FC(f16InErr, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac16_t f16Ka; /* Controller coefficient for present error. */ + frac16_t f16Kb; /* Controller coefficient for past error. */ + frac16_t f16Kc; /* Controller coefficient for past to past error. */ + frac16_t f16DelayX1; /* Controller delay parameter, past error. */ + frac16_t f16DelayX2; /* Controller delay parameter, past to past error. */ + frac16_t f16DelayY1; /* Controller delay parameter, past result. */ + frac16_t f16UpperLimit; /* Control Loop Output Upper Limit */ + frac16_t f16LowerLimit; /* Control Loop Output Lower Limit */ +} PCLIB_CTRL_PID_T_F16; + +/**************************************************************************** +* Exported function prototypes +****************************************************************************/ +extern void PCLIB_CtrlPIDInit_F16_FC(PCLIB_CTRL_PID_T_F16 *psParam); +extern frac16_t PCLIB_CtrlPID_F16_FC(frac16_t f16InErr, PCLIB_CTRL_PID_T_F16 *psParam); + + +#if defined(__cplusplus) +} +#endif + +#endif /* _PCLIB_CTRLPID_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_CtrlPI_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_CtrlPI_F16.h new file mode 100644 index 000000000..6ebb8374b --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_CtrlPI_F16.h @@ -0,0 +1,75 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************/ +#ifndef _PCLIB_CTRLPI_F16_H_ +#define _PCLIB_CTRLPI_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "pclib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define PCLIB_CtrlPIInit_F16_C(psParam) PCLIB_CtrlPIInit_F16_FC(psParam) +#define PCLIB_CtrlPI_F16_C(f16InErr, psParam) PCLIB_CtrlPI_F16_FC(f16InErr, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac16_t f16Kp; /* Proportional Gain. */ + frac16_t f16Ki; /* Integral Gain. */ + frac16_t f16IntegralUpperLimit; /* Integral Upper limit */ + frac16_t f16IntegralLowerLimit; /* Integral Lower limit */ + frac16_t f16PreviousIntegralOutput; /* Previous Integral output (n-1) */ + frac16_t f16UpperLimit; /* Control Loop Output Upper Limit */ + frac16_t f16LowerLimit; /* Control Loop Output Lower Limit */ +} PCLIB_CTRL_PI_T_F16; + +/**************************************************************************** +* Exported function prototypes +****************************************************************************/ +extern void PCLIB_CtrlPIInit_F16_FC(PCLIB_CTRL_PI_T_F16 *psParam); +extern frac16_t PCLIB_CtrlPI_F16_FC(frac16_t f16InErr, PCLIB_CTRL_PI_T_F16 *psParam); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PCLIB_CTRLPI_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_CtrlPIandLPFilter_F16.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_CtrlPIandLPFilter_F16.h new file mode 100644 index 000000000..bc0ae4959 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/PCLIB_CtrlPIandLPFilter_F16.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************/ +#ifndef _PCLIB_CTRLPILP_F16_H_ +#define _PCLIB_CTRLPILP_F16_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Includes +*******************************************************************************/ +#include "mlib.h" +#include "pclib_types.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define PCLIB_CtrlPIandLPInit_F16_C(psParam) PCLIB_CtrlPIandLPInit_F16_FC(psParam) +#define PCLIB_CtrlPIandLP_F16_C(f16InErr, psParam) PCLIB_CtrlPIandLP_F16_FC(f16InErr, psParam) + +/******************************************************************************* +* Types +*******************************************************************************/ +typedef struct +{ + frac16_t f16CoeffB0; /*!< Controller coefficient for present error. */ + frac16_t f16CoeffB1; /*!< Controller coefficient for past error. */ + frac16_t f16CoeffB2; /*!< Controller coefficient for past to past error. */ + frac16_t f16CoeffA1; /*!< Controller coefficient for past result. */ + frac16_t f16CoeffA2; /*!< Controller coefficient for past to past result. */ + frac16_t f16DelayX1; /*!< Controller delay parameter, past error. */ + frac16_t f16DelayX2; /*!< Controller delay parameter, past to past error. */ + frac16_t f16DelayY1; /*!< Controller delay parameter, past result. */ + frac16_t f16DelayY2; /*!< Controller delay parameter, past to past result. */ +} PCLIB_CTRL_PI_LP_T_F16; + +/**************************************************************************** +* Exported function prototypes +****************************************************************************/ +extern void PCLIB_CtrlPIandLPInit_F16_FC(PCLIB_CTRL_PI_LP_T_F16 *psParam); +extern frac16_t PCLIB_CtrlPIandLP_F16_FC(frac16_t f16InErr, PCLIB_CTRL_PI_LP_T_F16 *psParam); + + +#if defined(__cplusplus) +} +#endif + +#endif /* _PCLIB_CTRLPILP_F16_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/pclib.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/pclib.h new file mode 100644 index 000000000..9f53ab65c --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/pclib.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Main PCLIB header file for devices without FPU. +* +*******************************************************************************/ + +#ifndef _PCLIB_H_ +#define _PCLIB_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/****************************************************************************** +* Includes +******************************************************************************/ +#include "PCLIB_Ctrl2P2Z_F16.h" +#include "PCLIB_Ctrl3P3Z_F16.h" +#include "PCLIB_CtrlPID_F16.h" +#include "PCLIB_CtrlPI_F16.h" +#include "PCLIB_CtrlPIandLPFilter_F16.h" + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define PCLIB_Ctrl2P2ZInit_F16(psParam) PCLIB_Ctrl2P2ZInit_F16_C(psParam) +#define PCLIB_Ctrl2P2Z_F16(f16InErr, psParam) PCLIB_Ctrl2P2Z_F16_C(f16InErr, psParam) +#define PCLIB_Ctrl3P3ZInit_F16(psParam) PCLIB_Ctrl3P3ZInit_F16_C(psParam) +#define PCLIB_Ctrl3P3Z_F16(f16InErr, psParam) PCLIB_Ctrl3P3Z_F16_C(f16InErr, psParam) +#define PCLIB_CtrlPIDInit_F16(psParam) PCLIB_CtrlPIDInit_F16_C(psParam) +#define PCLIB_CtrlPID_F16(f16InErr, psParam) PCLIB_CtrlPID_F16_C(f16InErr, psParam) +#define PCLIB_CtrlPIInit_F16(psParam) PCLIB_CtrlPIInit_F16_C(psParam) +#define PCLIB_CtrlPI_F16(f16InErr, psParam) PCLIB_CtrlPI_F16_C(f16InErr, psParam) +#define PCLIB_CtrlPIandLPInit_F16(psParam) PCLIB_CtrlPIandLPInit_F16_C(psParam) +#define PCLIB_CtrlPIandLP_F16(f16InErr, psParam) PCLIB_CtrlPIandLP_F16_C(f16InErr, psParam) + +#if defined(__cplusplus) +} +#endif + +#endif /* _PCLIB_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/pclib_types.h b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/pclib_types.h new file mode 100644 index 000000000..027b31d03 --- /dev/null +++ b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/Include/pclib_types.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* + * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +****************************************************************************//*! +* +* @brief Basic types for PCLIB +* +*******************************************************************************/ +#ifndef _PCLIB_TYPES_H_ +#define _PCLIB_TYPES_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Macros +*******************************************************************************/ +#define PCLIB_CONST const + + +#if defined(__cplusplus) +} +#endif + +#endif /* _PCLIB_TYPES_H_ */ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/libPCLIB.a b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/libPCLIB.a new file mode 100644 index 000000000..2e1db2f89 Binary files /dev/null and b/middleware/rtcesl/CM4F_RTCESL_4.6.2_MCUX/PCLIB/libPCLIB.a differ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FAMCLIBUG.pdf b/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FAMCLIBUG.pdf new file mode 100644 index 000000000..13e4ae681 Binary files /dev/null and b/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FAMCLIBUG.pdf differ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FGDFLIBUG.pdf b/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FGDFLIBUG.pdf new file mode 100644 index 000000000..272a371e9 Binary files /dev/null and b/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FGDFLIBUG.pdf differ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FGFLIBUG.pdf b/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FGFLIBUG.pdf new file mode 100644 index 000000000..11c67d438 Binary files /dev/null and b/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FGFLIBUG.pdf differ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FGMCLIBUG.pdf b/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FGMCLIBUG.pdf new file mode 100644 index 000000000..e0a6ad3bf Binary files /dev/null and b/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FGMCLIBUG.pdf differ diff --git a/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FMLIBUG.pdf b/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FMLIBUG.pdf new file mode 100644 index 000000000..952461abe Binary files /dev/null and b/middleware/rtcesl/CM4F_RTCESL_4.6.2_doc/CM4FMLIBUG.pdf differ diff --git a/middleware/usb/device/usb_device.h b/middleware/usb/device/usb_device.h new file mode 100644 index 000000000..d3262a638 --- /dev/null +++ b/middleware/usb/device/usb_device.h @@ -0,0 +1,660 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __USB_DEVICE_H__ +#define __USB_DEVICE_H__ + +#include "usb.h" + +/*! + * @addtogroup usb_device_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines Get/Set status Types */ +typedef enum _usb_device_status +{ + kUSB_DeviceStatusTestMode = 1U, /*!< Test mode */ + kUSB_DeviceStatusSpeed, /*!< Current speed */ + kUSB_DeviceStatusOtg, /*!< OTG status */ + kUSB_DeviceStatusDevice, /*!< Device status */ + kUSB_DeviceStatusEndpoint, /*!< Endpoint state usb_device_endpoint_status_t */ + kUSB_DeviceStatusDeviceState, /*!< Device state */ + kUSB_DeviceStatusAddress, /*!< Device address */ + kUSB_DeviceStatusSynchFrame, /*!< Current frame */ + kUSB_DeviceStatusBus, /*!< Bus status */ + kUSB_DeviceStatusBusSuspend, /*!< Bus suspend */ + kUSB_DeviceStatusBusSleep, /*!< Bus suspend */ + kUSB_DeviceStatusBusResume, /*!< Bus resume */ + kUSB_DeviceStatusRemoteWakeup, /*!< Remote wakeup state */ + kUSB_DeviceStatusBusSleepResume, /*!< Bus resume */ +#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U) + kUSB_DeviceStatusGetCurrentFrameCount, /*!< Get current frame count */ +#endif +} usb_device_status_t; + +/*! @brief Defines USB 2.0 device state */ +typedef enum _usb_device_state +{ + kUSB_DeviceStateConfigured = 0U, /*!< Device state, Configured*/ + kUSB_DeviceStateAddress, /*!< Device state, Address*/ + kUSB_DeviceStateDefault, /*!< Device state, Default*/ + kUSB_DeviceStateAddressing, /*!< Device state, Address setting*/ + kUSB_DeviceStateTestMode, /*!< Device state, Test mode*/ +} usb_device_state_t; + +/*! @brief Defines endpoint state */ +typedef enum _usb_endpoint_status +{ + kUSB_DeviceEndpointStateIdle = 0U, /*!< Endpoint state, idle*/ + kUSB_DeviceEndpointStateStalled, /*!< Endpoint state, stalled*/ +} usb_device_endpoint_status_t; + +/*! @brief Control endpoint index */ +#define USB_CONTROL_ENDPOINT (0U) +/*! @brief Control endpoint maxPacketSize */ +#define USB_CONTROL_MAX_PACKET_SIZE (64U) + +#if (USB_DEVICE_CONFIG_EHCI && (USB_CONTROL_MAX_PACKET_SIZE != (64U))) +#error For high speed, USB_CONTROL_MAX_PACKET_SIZE must be 64!!! +#endif + +/*! @brief The setup packet size of USB control transfer. */ +#define USB_SETUP_PACKET_SIZE (8U) +/*! @brief USB endpoint mask */ +#define USB_ENDPOINT_NUMBER_MASK (0x0FU) + +/*! @brief uninitialized value */ +#define USB_UNINITIALIZED_VAL_32 (0xFFFFFFFFU) + +/*! @brief the endpoint callback length of cancelled transfer */ +#define USB_CANCELLED_TRANSFER_LENGTH (0xFFFFFFFFU) + +/*! @brief invalid tranfer buffer addresss */ +#define USB_INVALID_TRANSFER_BUFFER (0xFFFFFFFEU) + +#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U) +/* USB device IP3511 max frame count */ +#define USB_DEVICE_IP3511_MAX_FRAME_COUNT (0x000007FFU) +/* USB device EHCI max frame count */ +#define USB_DEVICE_EHCI_MAX_FRAME_COUNT (0x00003FFFU) +/* USB device EHCI max frame count */ +#define USB_DEVICE_KHCI_MAX_FRAME_COUNT (0x000007FFU) + +/*! @brief usb device controller max frame count */ +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +#define USB_DEVICE_MAX_FRAME_COUNT (USB_DEVICE_KHCI_MAX_FRAME_COUNT) +#elif (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +#define USB_DEVICE_MAX_FRAME_COUNT (USB_DEVICE_IP3511_MAX_FRAME_COUNT) +#elif ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +#define USB_DEVICE_MAX_FRAME_COUNT (USB_DEVICE_EHCI_MAX_FRAME_COUNT) +#endif +#endif + +/*! @brief Available common EVENT types in device callback */ +typedef enum _usb_device_event +{ + kUSB_DeviceEventBusReset = 1U, /*!< USB bus reset signal detected */ + kUSB_DeviceEventSuspend, /*!< USB bus suspend signal detected */ + kUSB_DeviceEventResume, /*!< USB bus resume signal detected. The resume signal is driven by itself or a host */ + kUSB_DeviceEventSleeped, /*!< USB bus LPM suspend signal detected */ + kUSB_DeviceEventLPMResume, /*!< USB bus LPM resume signal detected. The resume signal is driven by itself or a host + */ + kUSB_DeviceEventError, /*!< An error is happened in the bus. */ + kUSB_DeviceEventDetach, /*!< USB device is disconnected from a host. */ + kUSB_DeviceEventAttach, /*!< USB device is connected to a host. */ + kUSB_DeviceEventSetConfiguration, /*!< Set configuration. */ + kUSB_DeviceEventSetInterface, /*!< Set interface. */ + + kUSB_DeviceEventGetDeviceDescriptor, /*!< Get device descriptor. */ + kUSB_DeviceEventGetConfigurationDescriptor, /*!< Get configuration descriptor. */ + kUSB_DeviceEventGetStringDescriptor, /*!< Get string descriptor. */ + kUSB_DeviceEventGetHidDescriptor, /*!< Get HID descriptor. */ + kUSB_DeviceEventGetHidReportDescriptor, /*!< Get HID report descriptor. */ + kUSB_DeviceEventGetHidPhysicalDescriptor, /*!< Get HID physical descriptor. */ + kUSB_DeviceEventGetBOSDescriptor, /*!< Get configuration descriptor. */ + kUSB_DeviceEventGetDeviceQualifierDescriptor, /*!< Get device qualifier descriptor. */ + kUSB_DeviceEventVendorRequest, /*!< Vendor request. */ + kUSB_DeviceEventSetRemoteWakeup, /*!< Enable or disable remote wakeup function. */ + kUSB_DeviceEventGetConfiguration, /*!< Get current configuration index */ + kUSB_DeviceEventGetInterface, /*!< Get current interface alternate setting value */ + kUSB_DeviceEventSetBHNPEnable, +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) + kUSB_DeviceEventDcdDetectionfinished, /*!< The DCD detection finished */ +#endif +} usb_device_event_t; + +/*! @brief Endpoint callback message structure */ +typedef struct _usb_device_endpoint_callback_message_struct +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ + uint8_t isSetup; /*!< Is in a setup phase */ +} usb_device_endpoint_callback_message_struct_t; + +/*! + * @brief Endpoint callback function typedef. + * + * This callback function is used to notify the upper layer what the transfer result is. + * This callback pointer is passed when a specified endpoint is initialized by calling API #USB_DeviceInitEndpoint. + * + * @param handle The device handle. It equals to the value returned from #USB_DeviceInit. + * @param message The result of a transfer, which includes transfer buffer, transfer length, and whether is in a + * setup phase. + * phase for control pipe. + * @param callbackParam The parameter for this callback. It is same with + * usb_device_endpoint_callback_struct_t::callbackParam. + * + * @return A USB error code or kStatus_USB_Success. + */ +typedef usb_status_t (*usb_device_endpoint_callback_t)(usb_device_handle handle, + usb_device_endpoint_callback_message_struct_t *message, + void *callbackParam); + +/*! + * @brief Device callback function typedef. + * + * This callback function is used to notify the upper layer that the device status has changed. + * This callback pointer is passed by calling API #USB_DeviceInit. + * + * @param handle The device handle. It equals the value returned from #USB_DeviceInit. + * @param callbackEvent The callback event type. See enumeration #usb_device_event_t. + * @param eventParam The event parameter for this callback. The parameter type is determined by the callback event. + * + * @return A USB error code or kStatus_USB_Success. + */ +typedef usb_status_t (*usb_device_callback_t)(usb_device_handle handle, uint32_t callbackEvent, void *eventParam); + +/*! @brief Endpoint callback structure */ +typedef struct _usb_device_endpoint_callback_struct +{ + usb_device_endpoint_callback_t callbackFn; /*!< Endpoint callback function*/ + void *callbackParam; /*!< Parameter for callback function*/ + uint8_t isBusy; +} usb_device_endpoint_callback_struct_t; + +/*! @brief Endpoint initialization structure */ +typedef struct _usb_device_endpoint_init_struct +{ + uint16_t maxPacketSize; /*!< Endpoint maximum packet size */ + uint8_t endpointAddress; /*!< Endpoint address*/ + uint8_t transferType; /*!< Endpoint transfer type*/ + uint8_t zlt; /*!< ZLT flag*/ + uint8_t interval; /*!< Endpoint interval*/ +} usb_device_endpoint_init_struct_t; + +/*! @brief Endpoint status structure */ +typedef struct _usb_device_endpoint_status_struct +{ + uint8_t endpointAddress; /*!< Endpoint address */ + uint16_t endpointStatus; /*!< Endpoint status : idle or stalled */ +} usb_device_endpoint_status_struct_t; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @name USB device APIs + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Initializes the USB device stack. + * + * This function initializes the USB device module specified by the controllerId. + * + * @param[in] controllerId The controller ID of the USB IP. See the enumeration #usb_controller_index_t. + * @param[in] deviceCallback Function pointer of the device callback. + * @param[out] handle It is an out parameter used to return the pointer of the device handle to the caller. + * + * @retval kStatus_USB_Success The device is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. + * @retval kStatus_USB_Busy Cannot allocate a device handle. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id. + * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invalid. There is an empty + * interface entity. + * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than the IP's endpoint number. + * Or, the device has been initialized. + * Or, the mutex or message queue is created failed. + */ +extern usb_status_t USB_DeviceInit(uint8_t controllerId, + usb_device_callback_t deviceCallback, + usb_device_handle *handle); + +/*! + * @brief Enables the device functionality. + * + * The function enables the device functionality, so that the device can be recognized by the host when the device + * detects that it has been connected to a host. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +extern usb_status_t USB_DeviceRun(usb_device_handle handle); + +/*! + * @brief Disables the device functionality. + * + * The function disables the device functionality. After this function called, even if the device is detached to the + * host, + * it can't work. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + */ +extern usb_status_t USB_DeviceStop(usb_device_handle handle); + +/*! + * @brief De-initializes the device controller. + * + * The function de-initializes the device controller specified by the handle. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + */ +extern usb_status_t USB_DeviceDeinit(usb_device_handle handle); + +/*! + * @brief Sends data through a specified endpoint. + * + * The function is used to send data through a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to hold the data need to be sent. The function is not reentrant. + * @param[in] length The data length need to be sent. + * + * @retval kStatus_USB_Success The send request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value indicates whether the sending request is successful or not. The transfer done is notified by + * the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue on the application level. + * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +extern usb_status_t USB_DeviceSendRequest(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Receives data through a specified endpoint. + * + * The function is used to receive data through a specified endpoint. The function is not reentrant. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to save the received data. + * @param[in] length The data length want to be received. + * + * @retval kStatus_USB_Success The receive request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value indicates whether the receiving request is successful or not. The transfer done is notified by + * the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue on the application level. + * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +extern usb_status_t USB_DeviceRecvRequest(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Cancels the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The transfer is cancelled. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Initializes a specified endpoint. + * + * The function is used to initialize a specified endpoint. The corresponding endpoint callback is also initialized. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] epInit Endpoint initialization structure. See the structure usb_device_endpoint_init_struct_t. + * @param[in] epCallback Endpoint callback structure. See the structure + * usb_device_endpoint_callback_struct_t. + * + * @retval kStatus_USB_Success The endpoint is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is + * more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle, + usb_device_endpoint_init_struct_t *epInit, + usb_device_endpoint_callback_struct_t *epCallback); + +/*! + * @brief Deinitializes a specified endpoint. + * + * The function is used to deinitializes a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is de-initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Stalls a specified endpoint. + * + * The function is used to stall a specified endpoint. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is stalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Un-stall a specified endpoint. + * + * The function is used to unstall a specified endpoint. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is un-stalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Gets the status of the selected item. + * + * The function is used to get the status of the selected item. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] type The selected item. See the structure #usb_device_status_t. + * @param[out] param The parameter type is determined by the selected item. + * + * @retval kStatus_USB_Success Get status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The parameter is NULL pointer. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type. + */ +extern usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param); + +/*! + * @brief Sets the status of the selected item. + * + * The function is used to set the status of the selected item. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] type The selected item. See the structure #usb_device_status_t. + * @param[in] param The parameter type is determined by the selected item. + * + * @retval kStatus_USB_Success Set status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type or the parameter is NULL pointer. + */ +extern usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param); + +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) +/*! + * @brief Enable the device dcd module. + * + * The function enable the device dcd module. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device could run. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +extern usb_status_t USB_DeviceDcdEnable(usb_device_handle handle); + +/*! + * @brief Disable the device dcd module. + * + * The function disable the device dcd module. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The dcd is reset and stopped. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + * + */ +extern usb_status_t USB_DeviceDcdDisable(usb_device_handle handle); +#endif + +#if ((defined(USB_DEVICE_CONFIG_USE_TASK)) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) +/*! + * @brief Device task function. + * + * The function is used to handle the controller message. + * This function should not be called in the application directly. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceTaskFunction(void *deviceHandle); +#endif + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +#if ((defined(USB_DEVICE_CONFIG_USE_TASK)) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) +/*! + * @brief Device KHCI task function. + * + * The function is used to handle the KHCI controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceKhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#endif +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +#if ((defined(USB_DEVICE_CONFIG_USE_TASK)) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) +/*! + * @brief Device EHCI task function. + * + * The function is used to handle the EHCI controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceEhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#endif +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) +#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +/*! + * @brief Device ehci DCD ISR function. + * + * The function is the ehci DCD interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceEhciIsrHSDCDFunction(void *deviceHandle); +#endif +#endif +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +#if ((defined(USB_DEVICE_CONFIG_USE_TASK)) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) +/*! + * @brief Device LPC ip3511 controller task function. + * + * The function is used to handle the LPC ip3511 controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceLpcIp3511TaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#endif +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) +#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +/*! + * @brief Device IP3511 DCD ISR function. + * + * The function is the IP3511 DCD interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceLpcIp3511IsrDCDFunction(void *deviceHandle); +#endif +#endif +#endif + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +/*! + * @brief Device KHCI ISR function. + * + * The function is the KHCI interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceKhciIsrFunction(void *deviceHandle); +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) +#if (defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) +#if 0U /* it is not implemented yet */ +/*! + * @brief Device KHCI DCD ISR function. + * + * The function is the KHCI DCD interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceDcdIsrFunction(void *deviceHandle); +#endif +#endif +#endif +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/*! + * @brief Device EHCI ISR function. + * + * The function is the EHCI interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceEhciIsrFunction(void *deviceHandle); +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +/*! + * @brief Device LPC USB ISR function. + * + * The function is the LPC USB interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceLpcIp3511IsrFunction(void *deviceHandle); +#endif + +#if (((defined(USB_DEVICE_CONFIG_DWC3)) && (USB_DEVICE_CONFIG_DWC3 > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_DWC3)) && (USB_DEVICE_CONFIG_DWC3 > 0U))) +/*! + * @brief Device USB DWC3 ISR function. + * + * The function is the USB interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceDwc3IsrFunction(void *deviceHandle); +#endif + +/*! + * @brief Gets the device stack version function. + * + * The function is used to get the device stack version. + * + * @param[out] version The version structure pointer to keep the device stack version. + * + */ +extern void USB_DeviceGetVersion(uint32_t *version); + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) || \ + (((defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U)))) +/*! + * @brief Update the hardware tick. + * + * The function is used to update the hardware tick. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] tick Current hardware tick(uint is ms). + * + */ +extern usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick); +#endif + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* __USB_DEVICE_H__ */ diff --git a/middleware/usb/device/usb_device_dci.h b/middleware/usb/device/usb_device_dci.h new file mode 100644 index 000000000..d8f9555f4 --- /dev/null +++ b/middleware/usb/device/usb_device_dci.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __USB_DEVICE_DCI_H__ +#define __USB_DEVICE_DCI_H__ + +/*! + * @addtogroup usb_device_controller_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Macro to define controller handle */ +#define usb_device_controller_handle usb_device_handle +#define USB_DEVICE_MESSAGES_SIZE \ + (sizeof(uint32_t) * (1U + (sizeof(usb_device_callback_message_struct_t) - 1U) / sizeof(uint32_t))) +/*! @brief Available notify types for device notification */ +typedef enum _usb_device_notification +{ + kUSB_DeviceNotifyBusReset = 0x10U, /*!< Reset signal detected */ + kUSB_DeviceNotifySuspend, /*!< Suspend signal detected */ + kUSB_DeviceNotifyResume, /*!< Resume signal detected */ + kUSB_DeviceNotifyLPMSleep, /*!< LPM signal detected */ + kUSB_DeviceNotifyLPMResume, /*!< Resume signal detected */ + kUSB_DeviceNotifyError, /*!< Errors happened in bus */ + kUSB_DeviceNotifyDetach, /*!< Device disconnected from a host */ + kUSB_DeviceNotifyAttach, /*!< Device connected to a host */ +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) + kUSB_DeviceNotifyDcdDetectFinished, /*!< Device charger detection finished */ +#endif +} usb_device_notification_t; + +/*! @brief Device notification message structure */ +typedef struct _usb_device_callback_message_struct +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ + uint8_t code; /*!< Notification code */ + uint8_t isSetup; /*!< Is in a setup phase */ +} usb_device_callback_message_struct_t; + +/*! @brief Control type for controller */ +typedef enum _usb_device_control_type +{ + kUSB_DeviceControlRun = 0U, /*!< Enable the device functionality */ + kUSB_DeviceControlStop, /*!< Disable the device functionality */ + kUSB_DeviceControlEndpointInit, /*!< Initialize a specified endpoint */ + kUSB_DeviceControlEndpointDeinit, /*!< De-initialize a specified endpoint */ + kUSB_DeviceControlEndpointStall, /*!< Stall a specified endpoint */ + kUSB_DeviceControlEndpointUnstall, /*!< Un-stall a specified endpoint */ + kUSB_DeviceControlGetDeviceStatus, /*!< Get device status */ + kUSB_DeviceControlGetEndpointStatus, /*!< Get endpoint status */ + kUSB_DeviceControlSetDeviceAddress, /*!< Set device address */ + kUSB_DeviceControlGetSynchFrame, /*!< Get current frame */ + kUSB_DeviceControlResume, /*!< Drive controller to generate a resume signal in USB bus */ + kUSB_DeviceControlSleepResume, /*!< Drive controller to generate a LPM resume signal in USB bus */ + kUSB_DeviceControlSuspend, /*!< Drive controller to enter into suspend mode */ + kUSB_DeviceControlSleep, /*!< Drive controller to enter into sleep mode */ + kUSB_DeviceControlSetDefaultStatus, /*!< Set controller to default status */ + kUSB_DeviceControlGetSpeed, /*!< Get current speed */ + kUSB_DeviceControlGetOtgStatus, /*!< Get OTG status */ + kUSB_DeviceControlSetOtgStatus, /*!< Set OTG status */ + kUSB_DeviceControlSetTestMode, /*!< Drive xCHI into test mode */ + kUSB_DeviceControlGetRemoteWakeUp, /*!< Get flag of LPM Remote Wake-up Enabled by USB host. */ +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) + kUSB_DeviceControlDcdDisable, /*!< disable dcd module function. */ + kUSB_DeviceControlDcdEnable, /*!< enable dcd module function. */ +#endif + kUSB_DeviceControlPreSetDeviceAddress, /*!< Pre set device address */ + kUSB_DeviceControlUpdateHwTick, /*!< update hardware tick */ +#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U) + kUSB_DeviceControlGetCurrentFrameCount, /*!< Get current frame count */ +#endif +} usb_device_control_type_t; + +/*! @brief USB device controller initialization function typedef */ +typedef usb_status_t (*usb_device_controller_init_t)(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *controllerHandle); + +/*! @brief USB device controller de-initialization function typedef */ +typedef usb_status_t (*usb_device_controller_deinit_t)(usb_device_controller_handle controllerHandle); + +/*! @brief USB device controller send data function typedef */ +typedef usb_status_t (*usb_device_controller_send_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! @brief USB device controller receive data function typedef */ +typedef usb_status_t (*usb_device_controller_recv_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! @brief USB device controller cancel transfer function in a specified endpoint typedef */ +typedef usb_status_t (*usb_device_controller_cancel_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress); + +/*! @brief USB device controller control function typedef */ +typedef usb_status_t (*usb_device_controller_control_t)(usb_device_controller_handle controllerHandle, + usb_device_control_type_t command, + void *param); + +/*! @brief USB device controller interface structure */ +typedef struct _usb_device_controller_interface_struct +{ + usb_device_controller_init_t deviceInit; /*!< Controller initialization */ + usb_device_controller_deinit_t deviceDeinit; /*!< Controller de-initialization */ + usb_device_controller_send_t deviceSend; /*!< Controller send data */ + usb_device_controller_recv_t deviceRecv; /*!< Controller receive data */ + usb_device_controller_cancel_t deviceCancel; /*!< Controller cancel transfer */ + usb_device_controller_control_t deviceControl; /*!< Controller control */ +} usb_device_controller_interface_struct_t; + +/*! @brief USB device status structure */ +typedef struct _usb_device_struct +{ +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) || \ + (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U)) + volatile uint64_t hwTick; /*!< Current hw tick(ms)*/ +#endif + usb_device_controller_handle controllerHandle; /*!< Controller handle */ + const usb_device_controller_interface_struct_t *controllerInterface; /*!< Controller interface handle */ +#if USB_DEVICE_CONFIG_USE_TASK + OSA_MSGQ_HANDLE_DEFINE(notificationQueueBuffer, + USB_DEVICE_CONFIG_MAX_MESSAGES, + USB_DEVICE_MESSAGES_SIZE); /*!< Message queue buffer*/ + osa_msgq_handle_t notificationQueue; /*!< Message queue*/ +#endif + usb_device_callback_t deviceCallback; /*!< Device callback function pointer */ + usb_device_endpoint_callback_struct_t + epCallback[USB_DEVICE_CONFIG_ENDPOINTS << 1U]; /*!< Endpoint callback function structure */ + uint8_t deviceAddress; /*!< Current device address */ + uint8_t controllerId; /*!< Controller ID */ + uint8_t state; /*!< Current device state */ +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + uint8_t remotewakeup; /*!< Remote wakeup is enabled or not */ +#endif + uint8_t isResetting; /*!< Is doing device reset or not */ +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + uint8_t epCallbackDirectly; /*!< Whether call ep callback directly when the task is enabled */ +#endif +} usb_device_struct_t; + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief Notify the device that the controller status changed. + * + * This function is used to notify the device that the controller status changed. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg); +/*! @}*/ + +#endif /* __USB_DEVICE_DCI_H__ */ diff --git a/middleware/usb/include/usb.h b/middleware/usb/include/usb.h new file mode 100644 index 000000000..483d8a1f3 --- /dev/null +++ b/middleware/usb/include/usb.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __USB_H__ +#define __USB_H__ + +#include +#include +#include "fsl_common.h" +#include "fsl_os_abstraction.h" +#include "usb_misc.h" +#include "usb_spec.h" + +/*! + * @addtogroup usb_drv + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Defines USB stack major version */ +#define USB_STACK_VERSION_MAJOR (2UL) +/*! @brief Defines USB stack minor version */ +#define USB_STACK_VERSION_MINOR (8UL) +/*! @brief Defines USB stack bugfix version */ +#define USB_STACK_VERSION_BUGFIX (0U) + +/*! @brief USB stack version definition */ +#define USB_MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @brief USB stack component version definition, changed with component in yaml together */ +#define USB_STACK_COMPONENT_VERSION \ + MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX) + +/* + * Component ID used by tools + * + * FSL_COMPONENT_ID "middleware.usb.stack_common" + */ + +/*! @brief USB error code */ +typedef enum _usb_status +{ + kStatus_USB_Success = 0x00U, /*!< Success */ + kStatus_USB_Error, /*!< Failed */ + + kStatus_USB_Busy, /*!< Busy */ + kStatus_USB_InvalidHandle, /*!< Invalid handle */ + kStatus_USB_InvalidParameter, /*!< Invalid parameter */ + kStatus_USB_InvalidRequest, /*!< Invalid request */ + kStatus_USB_ControllerNotFound, /*!< Controller cannot be found */ + kStatus_USB_InvalidControllerInterface, /*!< Invalid controller interface */ + + kStatus_USB_NotSupported, /*!< Configuration is not supported */ + kStatus_USB_Retry, /*!< Enumeration get configuration retry */ + kStatus_USB_TransferStall, /*!< Transfer stalled */ + kStatus_USB_TransferFailed, /*!< Transfer failed */ + kStatus_USB_AllocFail, /*!< Allocation failed */ + kStatus_USB_LackSwapBuffer, /*!< Insufficient swap buffer for KHCI */ + kStatus_USB_TransferCancel, /*!< The transfer cancelled */ + kStatus_USB_BandwidthFail, /*!< Allocate bandwidth failed */ + kStatus_USB_MSDStatusFail, /*!< For MSD, the CSW status means fail */ + kStatus_USB_EHCIAttached, + kStatus_USB_EHCIDetached, + kStatus_USB_DataOverRun, /*!< The amount of data returned by the endpoint exceeded + either the size of the maximum data packet allowed + from the endpoint or the remaining buffer size. */ +} usb_status_t; + +/*! @brief USB host handle type define */ +typedef void *usb_host_handle; + +/*! @brief USB device handle type define. For device stack it is the whole device handle; for host stack it is the + * attached device instance handle*/ +typedef void *usb_device_handle; + +/*! @brief USB OTG handle type define */ +typedef void *usb_otg_handle; + +/*! @brief USB controller ID */ +typedef enum _usb_controller_index +{ + kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */ + kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved + to be used in the future. */ + kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */ + kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U, Currently, there are no platforms which have two EHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */ + kUSB_ControllerLpcIp3511Fs1 = 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511 + IPs, this is reserved to be used in the future. */ + + kUSB_ControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */ + kUSB_ControllerLpcIp3511Hs1 = 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511 + IPs, this is reserved to be used in the future. */ + + kUSB_ControllerOhci0 = 8U, /*!< OHCI 0U */ + kUSB_ControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */ + kUSB_ControllerIp3516Hs1 = 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs, + this is reserved to be used in the future. */ + kUSB_ControllerDwc30 = 12U, /*!< DWC3 0U */ + kUSB_ControllerDwc31 = 13U, /*!< DWC3 1U Currently, there are no platforms which have two Dwc IPs, this is reserved + to be used in the future.*/ +} usb_controller_index_t; + +/** + * @brief USB stack version fields + */ +typedef struct _usb_version +{ + uint8_t major; /*!< Major */ + uint8_t minor; /*!< Minor */ + uint8_t bugfix; /*!< Bug fix */ +} usb_version_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! @} */ + +#endif /* __USB_H__ */ diff --git a/middleware/usb/include/usb_misc.h b/middleware/usb/include/usb_misc.h new file mode 100644 index 000000000..af134c889 --- /dev/null +++ b/middleware/usb/include/usb_misc.h @@ -0,0 +1,502 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016, 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __USB_MISC_H__ +#define __USB_MISC_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Define big endian */ +#define USB_BIG_ENDIAN (0U) +/*! @brief Define little endian */ +#define USB_LITTLE_ENDIAN (1U) + +/*! @brief Define current endian */ +#ifndef ENDIANNESS +#define ENDIANNESS USB_LITTLE_ENDIAN +#endif +/*! @brief Define default timeout value */ +#if (defined(USE_RTOS) && (USE_RTOS > 0)) +#define USB_OSA_WAIT_TIMEOUT (osaWaitForever_c) +#else +#define USB_OSA_WAIT_TIMEOUT (0U) +#endif /* (defined(USE_RTOS) && (USE_RTOS > 0)) */ + +/*! @brief Define USB printf */ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +extern int DbgConsole_Printf(const char *fmt_s, ...); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#if defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE < 1) +#define usb_echo printf +#else +#define usb_echo DbgConsole_Printf +#endif + +#if defined(__ICCARM__) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED __packed +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED +#endif + +#elif defined(__GNUC__) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED __attribute__((__packed__)) +#endif + +#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION)) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED _Pragma("pack(1U)") +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED _Pragma("pack()") +#endif + +#elif (defined(__DSC__) || defined(__CW__)) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED __attribute__((packed)) +#endif +#endif + +#define USB_SHORT_GET_LOW(x) (((uint16_t)x) & 0xFFU) +#define USB_SHORT_GET_HIGH(x) ((uint8_t)(((uint16_t)x) >> 8U) & 0xFFU) + +#define USB_LONG_GET_BYTE0(x) ((uint8_t)(((uint32_t)(x))) & 0xFFU) +#define USB_LONG_GET_BYTE1(x) ((uint8_t)(((uint32_t)(x)) >> 8U) & 0xFFU) +#define USB_LONG_GET_BYTE2(x) ((uint8_t)(((uint32_t)(x)) >> 16U) & 0xFFU) +#define USB_LONG_GET_BYTE3(x) ((uint8_t)(((uint32_t)(x)) >> 24U) & 0xFFU) + +#define USB_MEM4_ALIGN_MASK (0x03U) + +/* accessory macro */ +#define USB_MEM4_ALIGN(n) ((n + 3U) & (0xFFFFFFFCu)) +#define USB_MEM32_ALIGN(n) ((n + 31U) & (0xFFFFFFE0u)) +#define USB_MEM64_ALIGN(n) ((n + 63U) & (0xFFFFFFC0u)) + +/* big/little endian */ +#define SWAP2BYTE_CONST(n) ((((n)&0x00FFU) << 8U) | (((n)&0xFF00U) >> 8U)) +#define SWAP4BYTE_CONST(n) \ + ((((n)&0x000000FFU) << 24U) | (((n)&0x0000FF00U) << 8U) | (((n)&0x00FF0000U) >> 8U) | (((n)&0xFF000000U) >> 24U)) + +#define USB_ASSIGN_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \ + *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \ + *((uint8_t *)&(n) + 2) = *((uint8_t *)&(m) + 2); \ + *((uint8_t *)&(n) + 3) = *((uint8_t *)&(m) + 3); \ + } + +#define USB_ASSIGN_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \ + *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \ + } + +#define USB_ASSIGN_MACRO_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = (uint8_t)m; \ + *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \ + *((uint8_t *)&(n) + 2) = (uint8_t)(m >> 16); \ + *((uint8_t *)&(n) + 3) = (uint8_t)(m >> 24); \ + } + +#define USB_ASSIGN_MACRO_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = (uint8_t)m; \ + *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \ + } + +#if (ENDIANNESS == USB_BIG_ENDIAN) + +#define USB_SHORT_TO_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_TO_LITTLE_ENDIAN(n) SWAP4BYTE_CONST(n) +#define USB_SHORT_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) + +#define USB_SHORT_TO_BIG_ENDIAN(n) (n) +#define USB_LONG_TO_BIG_ENDIAN(n) (n) +#define USB_SHORT_FROM_BIG_ENDIAN(n) (n) +#define USB_LONG_FROM_BIG_ENDIAN(n) (n) + +#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[3] = (uint8_t)((((uint32_t)(n)) >> 24U) & 0xFFU); \ + m[2] = (uint8_t)((((uint32_t)(n)) >> 16U) & 0xFFU); \ + m[1] = (uint8_t)((((uint32_t)(n)) >> 8U) & 0xFFU); \ + m[0] = (uint8_t)(((uint32_t)(n)) & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint32_t)n[3]) << 24U) | (((uint32_t)n[2]) << 16U) | (((uint32_t)n[1]) << 8U) | \ + (((uint32_t)n[0]) << 0U))) + +#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((((uint32_t)(n)) >> 24U) & 0xFFU); \ + m[1] = ((((uint32_t)(n)) >> 16U) & 0xFFU); \ + m[2] = ((((uint32_t)(n)) >> 8U) & 0xFFU); \ + m[3] = (((uint32_t)(n)) & 0xFFU); \ + } + +#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint32_t)n[0]) << 24U) | (((uint32_t)n[1]) << 16U) | (((uint32_t)n[2]) << 8U) | \ + (((uint32_t)n[3]) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[1] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \ + m[0] = (((uint16_t)(n)) & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[1]) << 8U) | (((uint16_t)n[0]) << 0U))) + +#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \ + m[1] = (((uint16_t)(n)) & 0xFFU); \ + } + +#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[0]) << 8U) | (((uint16_t)n[1]) << 0U))) + +#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 3) = ((((uint32_t)(n)) >> 24U) & 0xFFU); \ + *((uint8_t *)&(m) + 2) = ((((uint32_t)(n)) >> 16U) & 0xFFU); \ + *((uint8_t *)&(m) + 1) = ((((uint32_t)(n)) >> 8U) & 0xFFU); \ + *((uint8_t *)&(m) + 0) = (((uint32_t)(n)) & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint32_t)(((uint32_t)(*((uint8_t *)&(n) + 3)) << 24U) | ((uint32_t)(*((uint8_t *)&(n) + 2)) << 16U) | \ + ((uint32_t)(*((uint8_t *)&(n) + 1)) << 8U) | ((uint32_t)(*((uint8_t *)&(n))) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 1) = ((((uint16_t)(n)) >> 8U) & 0xFFU); \ + *((uint8_t *)&(m)) = ((((uint16_t)(n))) & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint16_t)((uint16_t)(*((uint8_t *)&(n) + 1)) << 8U) | ((uint16_t)(*((uint8_t *)&(n))))) + +#else + +#define USB_SHORT_TO_LITTLE_ENDIAN(n) (n) +#define USB_LONG_TO_LITTLE_ENDIAN(n) (n) +#define USB_SHORT_FROM_LITTLE_ENDIAN(n) (n) +#define USB_LONG_FROM_LITTLE_ENDIAN(n) (n) + +#define USB_SHORT_TO_BIG_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_TO_BIG_ENDIAN(n) SWAP4BYTE_CONST(n) +#define USB_SHORT_FROM_BIG_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_FROM_BIG_ENDIAN(n) SWAP4BYTE_CONST(n) + +#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[3] = (uint8_t)((((uint32_t)(n)) >> 24U) & 0xFFU); \ + m[2] = (uint8_t)((((uint32_t)(n)) >> 16U) & 0xFFU); \ + m[1] = (uint8_t)((((uint32_t)(n)) >> 8U) & 0xFFU); \ + m[0] = (uint8_t)(((uint32_t)(n)) & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint32_t)n[3]) << 24U) | (((uint32_t)n[2]) << 16U) | (((uint32_t)n[1]) << 8U) | \ + (((uint32_t)n[0]) << 0U))) + +#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((((uint32_t)(n)) >> 24U) & 0xFFU); \ + m[1] = ((((uint32_t)(n)) >> 16U) & 0xFFU); \ + m[2] = ((((uint32_t)(n)) >> 8U) & 0xFFU); \ + m[3] = (((uint32_t)(n)) & 0xFFU); \ + } + +#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint32_t)n[0]) << 24U) | (((uint32_t)n[1]) << 16U) | (((uint32_t)n[2]) << 8U) | \ + (((uint32_t)n[3]) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[1] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \ + m[0] = (((uint16_t)(n)) & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[1]) << 8U) | (((uint16_t)n[0]) << 0U))) + +#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \ + m[1] = (((uint16_t)(n)) & 0xFFU); \ + } + +#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[0]) << 8U) | (((uint16_t)n[1]) << 0U))) + +#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 3) = ((((uint32_t)(n)) >> 24U) & 0xFFU); \ + *((uint8_t *)&(m) + 2) = ((((uint32_t)(n)) >> 16U) & 0xFFU); \ + *((uint8_t *)&(m) + 1) = ((((uint32_t)(n)) >> 8U) & 0xFFU); \ + *((uint8_t *)&(m) + 0) = (((uint32_t)(n)) & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint32_t)(((uint32_t)(*((uint8_t *)&(n) + 3)) << 24U) | ((uint32_t)(*((uint8_t *)&(n) + 2)) << 16U) | \ + ((uint32_t)(*((uint8_t *)&(n) + 1)) << 8U) | ((uint32_t)(*((uint8_t *)&(n))) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 1) = ((((uint16_t)(n)) >> 8U) & 0xFFU); \ + *((uint8_t *)&(m)) = ((((uint16_t)(n))) & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint16_t)(((uint16_t)(*(((uint8_t *)&(n)) + 1)) << 8U) | ((uint16_t)(*((uint8_t *)&(n)))))) + +#endif + +/* + * The following MACROs (USB_GLOBAL, USB_BDT, USB_RAM_ADDRESS_ALIGNMENT, etc) are only used for USB device stack. + * The USB device global variables are put into the section m_usb_global and m_usb_bdt + * by using the MACRO USB_GLOBAL and USB_BDT. In this way, the USB device + * global variables can be linked into USB dedicated RAM by USB_STACK_USE_DEDICATED_RAM. + * The MACRO USB_STACK_USE_DEDICATED_RAM is used to decide the USB stack uses dedicated RAM or not. The value of + * the macro can be set as 0, USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL, or USB_STACK_DEDICATED_RAM_TYPE_BDT. + * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL means USB device global variables, including USB_BDT and + * USB_GLOBAL, are put into the USB dedicated RAM. This feature can only be enabled when the USB dedicated RAM + * is not less than 2K Bytes. + * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT means USB device global variables, only including USB_BDT, are put + * into the USB dedicated RAM, the USB_GLOBAL will be put into .bss section. This feature is used for some SOCs, + * the USB dedicated RAM size is not more than 512 Bytes. + */ +#define USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL 1 +#define USB_STACK_DEDICATED_RAM_TYPE_BDT 2 + +#if defined(__ICCARM__) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +/* disable misra 19.13 */ +_Pragma("diag_suppress=Pm120") +#define USB_ALIGN_PRAGMA(x) _Pragma(#x) + _Pragma("diag_default=Pm120") + +#define USB_RAM_ADDRESS_ALIGNMENT(n) USB_ALIGN_PRAGMA(data_alignment = n) + _Pragma("diag_suppress=Pm120") +#define USB_LINK_SECTION_PART(str) _Pragma(#str) +#define USB_LINK_DMA_INIT_DATA(sec) USB_LINK_SECTION_PART(location = #sec) +#define USB_LINK_USB_GLOBAL _Pragma("location = \"m_usb_global\"") +#define USB_LINK_USB_BDT _Pragma("location = \"m_usb_bdt\"") +#define USB_LINK_USB_GLOBAL_BSS +#define USB_LINK_USB_BDT_BSS + _Pragma("diag_default=Pm120") +#define USB_LINK_DMA_NONINIT_DATA _Pragma("location = \"m_usb_dma_noninit_data\"") +#define USB_LINK_NONCACHE_NONINIT_DATA _Pragma("location = \"NonCacheable\"") +#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION)) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) +#define USB_LINK_DMA_INIT_DATA(sec) __attribute__((section(#sec))) +#if defined(__CC_ARM) +#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global"))) __attribute__((zero_init)) +#else +#define USB_LINK_USB_GLOBAL __attribute__((section(".bss.m_usb_global"))) +#endif +#if defined(__CC_ARM) +#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt"))) __attribute__((zero_init)) +#else +#define USB_LINK_USB_BDT __attribute__((section(".bss.m_usb_bdt"))) +#endif +#define USB_LINK_USB_GLOBAL_BSS +#define USB_LINK_USB_BDT_BSS +#if defined(__CC_ARM) +#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data"))) __attribute__((zero_init)) +#else +#define USB_LINK_DMA_NONINIT_DATA __attribute__((section(".bss.m_usb_dma_noninit_data"))) +#endif +#if defined(__CC_ARM) +#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable"))) __attribute__((zero_init)) +#else +#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section(".bss.NonCacheable"))) +#endif + +#elif defined(__GNUC__) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) +#define USB_LINK_DMA_INIT_DATA(sec) __attribute__((section(#sec))) +#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global, \"aw\", %nobits @"))) +#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt, \"aw\", %nobits @"))) +#define USB_LINK_USB_GLOBAL_BSS +#define USB_LINK_USB_BDT_BSS +#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data, \"aw\", %nobits @"))) +#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable, \"aw\", %nobits @"))) + +#elif (defined(__DSC__) && defined(__CW__)) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) +#define USB_LINK_USB_BDT_BSS +#define USB_LINK_USB_GLOBAL_BSS +#else +#error The tool-chain is not supported. +#endif + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + +#if ((defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) && (defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#elif (defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) +#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, 0) +#elif (defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)) +#define USB_CACHE_LINESIZE MAX(0, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#else +#define USB_CACHE_LINESIZE 4U +#endif + +#else +#define USB_CACHE_LINESIZE 4U +#endif + +#if (USB_CACHE_LINESIZE > 4U) +#define USB_DATA_ALIGN_SIZE USB_CACHE_LINESIZE +#else +/* Change the USB_DATA_ALIGN_SIZE to 4, For the lpcip3511 driver, the lpcip3511 driver will do the memcpy for the + transfer buffer that is not in the USB dedicated RAM or not aligned to 64-byte boundaries. Hence the changes do not + bring the risk and improve the RAM usage rate but cause the lower perfromance. If requiring a higher performance on + the lpcip3511 platform, please change the macro to 64 and put the transfer buffer into the USB dedicated RAM. */ +#define USB_DATA_ALIGN_SIZE 4U +#endif + +/* Due to the change of USB_DATA_ALIGN_SIZE from 64 to 4 on the lpcip3511 platform, the size of variables defined by + using this marco may be smaller on the lpcip3511 platform. If users don't want the lpcip3511 driver to do memcpy, + please use the macro to define the transfer buffer and change the USB_DATA_ALIGN_SIZE to 64 and put the transfer + buffer into the USB dedicated RAM. */ +#define USB_DATA_ALIGN_SIZE_MULTIPLE(n) (((n) + USB_DATA_ALIGN_SIZE - 1U) & (~(USB_DATA_ALIGN_SIZE - 1U))) + +#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL) + +#define USB_GLOBAL USB_LINK_USB_GLOBAL +#define USB_BDT USB_LINK_USB_BDT + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE)) +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(NonCacheable.init) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA USB_LINK_USB_GLOBAL +#endif +#endif + +#elif defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT) + +#define USB_BDT USB_LINK_USB_BDT + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE)) +#define USB_GLOBAL USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(NonCacheable.init) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA +#endif +#endif + +#else + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + +#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA +#define USB_BDT USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA + +#else + +#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE)) +#define USB_GLOBAL USB_LINK_NONCACHE_NONINIT_DATA +#define USB_BDT USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(NonCacheable.init) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS +#define USB_BDT USB_LINK_USB_BDT_BSS +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA +#endif + +#endif + +#endif + +#define USB_DMA_NONINIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_INIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_INIT_SUB + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_DMA_DATA_NONCACHEABLE USB_LINK_NONCACHE_NONINIT_DATA + +#else +#define USB_DMA_DATA_NONCACHEABLE +#endif + +#define USB_GLOBAL_DEDICATED_RAM USB_LINK_USB_GLOBAL + +/* #define USB_RAM_ADDRESS_NONCACHEREG_ALIGNMENT(n, var) AT_NONCACHEABLE_SECTION_ALIGN(var, n) */ +/* #define USB_RAM_ADDRESS_NONCACHEREG(var) AT_NONCACHEABLE_SECTION(var) */ + +#endif /* __USB_MISC_H__ */ diff --git a/middleware/usb/include/usb_spec.h b/middleware/usb/include/usb_spec.h new file mode 100644 index 000000000..a642bd518 --- /dev/null +++ b/middleware/usb/include/usb_spec.h @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __USB_SPEC_H__ +#define __USB_SPEC_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* USB speed (the value cannot be changed because EHCI QH use the value directly)*/ +#define USB_SPEED_FULL (0x00U) +#define USB_SPEED_LOW (0x01U) +#define USB_SPEED_HIGH (0x02U) +#define USB_SPEED_SUPER (0x04U) + +/* Set up packet structure */ +typedef struct _usb_setup_struct +{ + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} usb_setup_struct_t; + +/* USB standard descriptor endpoint type */ +#define USB_ENDPOINT_CONTROL (0x00U) +#define USB_ENDPOINT_ISOCHRONOUS (0x01U) +#define USB_ENDPOINT_BULK (0x02U) +#define USB_ENDPOINT_INTERRUPT (0x03U) + +/* USB standard descriptor transfer direction (cannot change the value because iTD use the value directly) */ +#define USB_OUT (0U) +#define USB_IN (1U) + +/* USB standard descriptor length */ +#define USB_DESCRIPTOR_LENGTH_DEVICE (0x12U) +#define USB_DESCRIPTOR_LENGTH_CONFIGURE (0x09U) +#define USB_DESCRIPTOR_LENGTH_INTERFACE (0x09U) +#define USB_DESCRIPTOR_LENGTH_ENDPOINT (0x07U) +#define USB_DESCRIPTOR_LENGTH_ENDPOINT_COMPANION (0x06U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_QUALITIER (0x0AU) +#define USB_DESCRIPTOR_LENGTH_OTG_DESCRIPTOR (5U) +#define USB_DESCRIPTOR_LENGTH_BOS_DESCRIPTOR (5U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_CAPABILITY_USB20_EXTENSION (0x07U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_CAPABILITY_SUPERSPEED (0x0AU) + +/* USB Device Capability Type Codes */ +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_WIRELESS (0x01U) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_USB20_EXTENSION (0x02U) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_SUPERSPEED (0x03U) + +/* USB standard descriptor type */ +#define USB_DESCRIPTOR_TYPE_DEVICE (0x01U) +#define USB_DESCRIPTOR_TYPE_CONFIGURE (0x02U) +#define USB_DESCRIPTOR_TYPE_STRING (0x03U) +#define USB_DESCRIPTOR_TYPE_INTERFACE (0x04U) +#define USB_DESCRIPTOR_TYPE_ENDPOINT (0x05U) +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALITIER (0x06U) +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION (0x07U) +#define USB_DESCRIPTOR_TYPE_INTERFAACE_POWER (0x08U) +#define USB_DESCRIPTOR_TYPE_OTG (0x09U) +#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION (0x0BU) +#define USB_DESCRIPTOR_TYPE_BOS (0x0F) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY (0x10) + +#define USB_DESCRIPTOR_TYPE_HID (0x21U) +#define USB_DESCRIPTOR_TYPE_HID_REPORT (0x22U) +#define USB_DESCRIPTOR_TYPE_HID_PHYSICAL (0x23U) + +#define USB_DESCRIPTOR_TYPE_ENDPOINT_COMPANION (0x30U) + +/* USB standard request type */ +#define USB_REQUEST_TYPE_DIR_MASK (0x80U) +#define USB_REQUEST_TYPE_DIR_SHIFT (7U) +#define USB_REQUEST_TYPE_DIR_OUT (0x00U) +#define USB_REQUEST_TYPE_DIR_IN (0x80U) + +#define USB_REQUEST_TYPE_TYPE_MASK (0x60U) +#define USB_REQUEST_TYPE_TYPE_SHIFT (5U) +#define USB_REQUEST_TYPE_TYPE_STANDARD (0U) +#define USB_REQUEST_TYPE_TYPE_CLASS (0x20U) +#define USB_REQUEST_TYPE_TYPE_VENDOR (0x40U) + +#define USB_REQUEST_TYPE_RECIPIENT_MASK (0x1FU) +#define USB_REQUEST_TYPE_RECIPIENT_SHIFT (0U) +#define USB_REQUEST_TYPE_RECIPIENT_DEVICE (0x00U) +#define USB_REQUEST_TYPE_RECIPIENT_INTERFACE (0x01U) +#define USB_REQUEST_TYPE_RECIPIENT_ENDPOINT (0x02U) +#define USB_REQUEST_TYPE_RECIPIENT_OTHER (0x03U) + +/* USB standard request */ +#define USB_REQUEST_STANDARD_GET_STATUS (0x00U) +#define USB_REQUEST_STANDARD_CLEAR_FEATURE (0x01U) +#define USB_REQUEST_STANDARD_SET_FEATURE (0x03U) +#define USB_REQUEST_STANDARD_SET_ADDRESS (0x05U) +#define USB_REQUEST_STANDARD_GET_DESCRIPTOR (0x06U) +#define USB_REQUEST_STANDARD_SET_DESCRIPTOR (0x07U) +#define USB_REQUEST_STANDARD_GET_CONFIGURATION (0x08U) +#define USB_REQUEST_STANDARD_SET_CONFIGURATION (0x09U) +#define USB_REQUEST_STANDARD_GET_INTERFACE (0x0AU) +#define USB_REQUEST_STANDARD_SET_INTERFACE (0x0BU) +#define USB_REQUEST_STANDARD_SYNCH_FRAME (0x0CU) + +/* USB standard request GET Status */ +#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT (0U) +#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT (1U) + +#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_MASK (0x01U) +#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_SHIFT (0U) + +#define USB_REQUEST_STANDARD_GET_STATUS_OTG_STATUS_SELECTOR (0xF000U) + +/* USB standard request CLEAR/SET feature */ +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT (0U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP (1U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE (2U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_B_HNP_ENABLE (3U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_HNP_SUPPORT (4U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_ALT_HNP_SUPPORT (5U) + +/* USB standard descriptor configure bmAttributes */ +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK (0x80U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_SHIFT (7U) + +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_MASK (0x40U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT (6U) + +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_MASK (0x20U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT (5U) + +/* USB standard descriptor endpoint bmAttributes */ +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK (0x80U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT (7U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_OUT (0U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN (0x80U) + +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK (0x0FU) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_SHFIT (0U) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK (0x03U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_NUMBER_SHFIT (0U) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_MASK (0x0CU) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SHFIT (2U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_NO_SYNC (0x00U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ASYNC (0x04U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ADAPTIVE (0x08U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SYNC (0x0CU) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_MASK (0x30U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_SHFIT (4U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_DATA_ENDPOINT (0x00U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_FEEDBACK_ENDPOINT (0x10U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_IMPLICIT_FEEDBACK_DATA_ENDPOINT (0x20U) + +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK (0x07FFu) +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK (0x1800u) +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT (11U) + +/* USB standard descriptor otg bmAttributes */ +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_SRP_MASK (0x01u) +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_HNP_MASK (0x02u) +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_ADP_MASK (0x04u) + +/* USB standard descriptor device capability usb20 extension bmAttributes */ +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_MASK (0x02U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_SHIFT (1U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_MASK (0x04U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_SHIFT (2U) + +/* Language structure */ +typedef struct _usb_language +{ + uint8_t **string; /* The Strings descriptor array */ + uint32_t *length; /* The strings descriptor length array */ + uint16_t languageId; /* The language id of current language */ +} usb_language_t; + +typedef struct _usb_language_list +{ + uint8_t *languageString; /* The String 0U pointer */ + uint32_t stringLength; /* The String 0U Length */ + usb_language_t *languageList; /* The language list */ + uint8_t count; /* The language count */ +} usb_language_list_t; + +typedef struct _usb_descriptor_common +{ + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* DEVICE Descriptor Type */ + uint8_t bData[1]; /* Data */ +} usb_descriptor_common_t; + +typedef struct _usb_descriptor_device +{ + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* DEVICE Descriptor Type */ + uint8_t bcdUSB[2]; /* UUSB Specification Release Number in Binary-Coded Decimal, e.g. 0x0200U */ + uint8_t bDeviceClass; /* Class code */ + uint8_t bDeviceSubClass; /* Sub-Class code */ + uint8_t bDeviceProtocol; /* Protocol code */ + uint8_t bMaxPacketSize0; /* Maximum packet size for endpoint zero */ + uint8_t idVendor[2]; /* Vendor ID (assigned by the USB-IF) */ + uint8_t idProduct[2]; /* Product ID (assigned by the manufacturer) */ + uint8_t bcdDevice[2]; /* Device release number in binary-coded decimal */ + uint8_t iManufacturer; /* Index of string descriptor describing manufacturer */ + uint8_t iProduct; /* Index of string descriptor describing product */ + uint8_t iSerialNumber; /* Index of string descriptor describing the device serial number */ + uint8_t bNumConfigurations; /* Number of possible configurations */ +} usb_descriptor_device_t; + +typedef struct _usb_descriptor_configuration +{ + uint8_t bLength; /* Descriptor size in bytes = 9U */ + uint8_t bDescriptorType; /* CONFIGURATION type = 2U or 7U */ + uint8_t wTotalLength[2]; /* Length of concatenated descriptors */ + uint8_t bNumInterfaces; /* Number of interfaces, this configuration. */ + uint8_t bConfigurationValue; /* Value to set this configuration. */ + uint8_t iConfiguration; /* Index to configuration string */ + uint8_t bmAttributes; /* Configuration characteristics */ + uint8_t bMaxPower; /* Maximum power from bus, 2 mA units */ +} usb_descriptor_configuration_t; + +typedef struct _usb_descriptor_interface +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} usb_descriptor_interface_t; + +typedef struct _usb_descriptor_endpoint +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSize[2]; + uint8_t bInterval; +} usb_descriptor_endpoint_t; + +typedef struct _usb_descriptor_endpoint_companion +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bMaxBurst; + uint8_t bmAttributes; + uint8_t wBytesPerInterval[2]; +} usb_descriptor_endpoint_companion_t; + +typedef struct _usb_descriptor_binary_device_object_store +{ + uint8_t bLength; /* Descriptor size in bytes = 5U */ + uint8_t bDescriptorType; /* BOS Descriptor type = 0FU*/ + uint8_t wTotalLength[2]; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bNumDeviceCaps; /*The number of separate device capability descriptors in the BOS*/ +} usb_descriptor_bos_t; + +typedef struct _usb_descriptor_usb20_extension +{ + uint8_t bLength; /* Descriptor size in bytes = 7U */ + uint8_t bDescriptorType; /* DEVICE CAPABILITY Descriptor type = 0x10U*/ + uint8_t bDevCapabilityType; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bmAttributes[4]; /*Bitmap encoding of supported device level features.*/ +} usb_descriptor_usb20_extension_t; +typedef struct _usb_descriptor_super_speed_device_capability +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bmAttributes; + uint8_t wSpeedsSupported[2]; + uint8_t bFunctionalitySupport; + uint8_t bU1DevExitLat; + uint8_t wU2DevExitLat[2]; +} usb_bos_device_capability_susperspeed_desc_t; +typedef union _usb_descriptor_union +{ + usb_descriptor_common_t common; /* Common descriptor */ + usb_descriptor_device_t device; /* Device descriptor */ + usb_descriptor_configuration_t configuration; /* Configuration descriptor */ + usb_descriptor_interface_t interface; /* Interface descriptor */ + usb_descriptor_endpoint_t endpoint; /* Endpoint descriptor */ + usb_descriptor_endpoint_companion_t endpointCompanion; /* Endpoint companion descriptor */ +} usb_descriptor_union_t; + +#endif /* __USB_SPEC_H__ */ diff --git a/rtos/freertos/middleware_freertos-kernel_MIMX8MQ6.cmake b/rtos/freertos/middleware_freertos-kernel_MIMX8MQ6.cmake new file mode 100644 index 000000000..c01a4482c --- /dev/null +++ b/rtos/freertos/middleware_freertos-kernel_MIMX8MQ6.cmake @@ -0,0 +1,23 @@ +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/list.c + ${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/queue.c + ${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/timers.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/include + ${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension_MIMX8MQ6) + diff --git a/rtos/freertos/middleware_freertos-kernel_extension_MIMX8MQ6.cmake b/rtos/freertos/middleware_freertos-kernel_extension_MIMX8MQ6.cmake new file mode 100644 index 000000000..967a3d07b --- /dev/null +++ b/rtos/freertos/middleware_freertos-kernel_extension_MIMX8MQ6.cmake @@ -0,0 +1,8 @@ +include_guard(GLOBAL) +message("middleware_freertos-kernel_extension component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/include +) + diff --git a/rtos/freertos/middleware_freertos-kernel_heap_4_MIMX8MQ6.cmake b/rtos/freertos/middleware_freertos-kernel_heap_4_MIMX8MQ6.cmake new file mode 100644 index 000000000..d5483796b --- /dev/null +++ b/rtos/freertos/middleware_freertos-kernel_heap_4_MIMX8MQ6.cmake @@ -0,0 +1,10 @@ +include_guard(GLOBAL) +message("middleware_freertos-kernel_heap_4 component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/portable/MemMang/heap_4.c +) + + +include(middleware_freertos-kernel_MIMX8MQ6) +